Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.48 99.10 97.95 98.37 97.67 99.02 98.41 91.83


Total test records in report: 1071
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T199 /workspace/coverage/default/31.keymgr_lc_disable.509043010 Feb 19 03:12:36 PM PST 24 Feb 19 03:12:42 PM PST 24 134145400 ps
T1012 /workspace/coverage/default/35.keymgr_hwsw_invalid_input.323953197 Feb 19 03:12:44 PM PST 24 Feb 19 03:12:53 PM PST 24 155510037 ps
T1013 /workspace/coverage/default/20.keymgr_sideload_protect.511932610 Feb 19 03:11:26 PM PST 24 Feb 19 03:11:31 PM PST 24 269068216 ps
T1014 /workspace/coverage/default/13.keymgr_sideload_otbn.244610512 Feb 19 03:10:36 PM PST 24 Feb 19 03:10:52 PM PST 24 247256926 ps
T1015 /workspace/coverage/default/23.keymgr_sideload_otbn.2187820856 Feb 19 03:11:33 PM PST 24 Feb 19 03:11:40 PM PST 24 72220378 ps
T1016 /workspace/coverage/default/2.keymgr_sideload_aes.2736124011 Feb 19 03:08:53 PM PST 24 Feb 19 03:09:00 PM PST 24 198419176 ps
T1017 /workspace/coverage/default/28.keymgr_alert_test.2403639607 Feb 19 03:12:10 PM PST 24 Feb 19 03:12:13 PM PST 24 44140597 ps
T1018 /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.88601760 Feb 19 03:12:55 PM PST 24 Feb 19 03:13:13 PM PST 24 2415592054 ps
T351 /workspace/coverage/default/0.keymgr_kmac_rsp_err.3238833613 Feb 19 03:08:25 PM PST 24 Feb 19 03:08:31 PM PST 24 290799034 ps
T1019 /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1253555377 Feb 19 03:12:13 PM PST 24 Feb 19 03:12:23 PM PST 24 221880559 ps
T1020 /workspace/coverage/default/19.keymgr_custom_cm.599645374 Feb 19 03:11:22 PM PST 24 Feb 19 03:11:54 PM PST 24 5352029044 ps
T1021 /workspace/coverage/default/11.keymgr_smoke.30594853 Feb 19 03:10:24 PM PST 24 Feb 19 03:10:30 PM PST 24 618607152 ps
T1022 /workspace/coverage/default/4.keymgr_smoke.2406958063 Feb 19 03:09:25 PM PST 24 Feb 19 03:09:38 PM PST 24 186703119 ps
T1023 /workspace/coverage/default/20.keymgr_alert_test.2208005330 Feb 19 03:11:25 PM PST 24 Feb 19 03:11:28 PM PST 24 49817762 ps
T1024 /workspace/coverage/default/41.keymgr_alert_test.1897966624 Feb 19 03:13:22 PM PST 24 Feb 19 03:13:27 PM PST 24 11620461 ps
T1025 /workspace/coverage/default/17.keymgr_sideload_kmac.3925317610 Feb 19 03:11:05 PM PST 24 Feb 19 03:11:12 PM PST 24 60607942 ps
T200 /workspace/coverage/default/46.keymgr_lc_disable.1412610979 Feb 19 03:13:36 PM PST 24 Feb 19 03:13:55 PM PST 24 198356690 ps
T1026 /workspace/coverage/default/40.keymgr_smoke.1267744041 Feb 19 03:13:02 PM PST 24 Feb 19 03:13:06 PM PST 24 53614399 ps
T1027 /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2152359201 Feb 19 03:10:02 PM PST 24 Feb 19 03:10:07 PM PST 24 570969446 ps
T1028 /workspace/coverage/default/46.keymgr_direct_to_disabled.2180661242 Feb 19 03:13:39 PM PST 24 Feb 19 03:13:56 PM PST 24 185596800 ps
T1029 /workspace/coverage/default/8.keymgr_sw_invalid_input.2556883160 Feb 19 03:09:58 PM PST 24 Feb 19 03:10:10 PM PST 24 786518598 ps
T1030 /workspace/coverage/default/43.keymgr_random.1959671900 Feb 19 03:13:29 PM PST 24 Feb 19 03:13:40 PM PST 24 90661216 ps
T1031 /workspace/coverage/default/42.keymgr_direct_to_disabled.314831018 Feb 19 03:13:17 PM PST 24 Feb 19 03:13:27 PM PST 24 74342270 ps
T1032 /workspace/coverage/default/16.keymgr_random.118563339 Feb 19 03:10:59 PM PST 24 Feb 19 03:11:37 PM PST 24 1428251931 ps
T1033 /workspace/coverage/default/1.keymgr_sideload.3562959982 Feb 19 03:08:35 PM PST 24 Feb 19 03:08:39 PM PST 24 285109974 ps
T1034 /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1015398119 Feb 19 03:10:35 PM PST 24 Feb 19 03:10:47 PM PST 24 416017530 ps
T1035 /workspace/coverage/default/0.keymgr_custom_cm.1192053543 Feb 19 03:08:30 PM PST 24 Feb 19 03:08:38 PM PST 24 193706373 ps
T1036 /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3956390839 Feb 19 03:08:29 PM PST 24 Feb 19 03:09:13 PM PST 24 4803471074 ps
T312 /workspace/coverage/default/2.keymgr_sideload_protect.4290093346 Feb 19 03:09:00 PM PST 24 Feb 19 03:09:08 PM PST 24 345092829 ps
T1037 /workspace/coverage/default/24.keymgr_alert_test.1926859178 Feb 19 03:11:53 PM PST 24 Feb 19 03:11:57 PM PST 24 11773538 ps
T1038 /workspace/coverage/default/5.keymgr_sideload_aes.1711212475 Feb 19 03:09:27 PM PST 24 Feb 19 03:09:40 PM PST 24 153157430 ps
T1039 /workspace/coverage/default/21.keymgr_sideload_kmac.230379151 Feb 19 03:11:23 PM PST 24 Feb 19 03:11:29 PM PST 24 305268477 ps
T1040 /workspace/coverage/default/5.keymgr_stress_all.1596898061 Feb 19 03:09:40 PM PST 24 Feb 19 03:09:59 PM PST 24 823326635 ps
T1041 /workspace/coverage/default/25.keymgr_lc_disable.3106913444 Feb 19 03:11:50 PM PST 24 Feb 19 03:11:56 PM PST 24 532132899 ps
T1042 /workspace/coverage/default/8.keymgr_stress_all.4094734434 Feb 19 03:09:58 PM PST 24 Feb 19 03:10:23 PM PST 24 1111961964 ps
T1043 /workspace/coverage/default/37.keymgr_lc_disable.2892144025 Feb 19 03:12:51 PM PST 24 Feb 19 03:13:00 PM PST 24 405724369 ps
T1044 /workspace/coverage/default/5.keymgr_sideload_otbn.2507911412 Feb 19 03:09:32 PM PST 24 Feb 19 03:09:41 PM PST 24 184564419 ps
T265 /workspace/coverage/default/6.keymgr_kmac_rsp_err.940241331 Feb 19 03:09:43 PM PST 24 Feb 19 03:11:50 PM PST 24 14210152588 ps
T1045 /workspace/coverage/default/7.keymgr_random.2041852826 Feb 19 03:09:44 PM PST 24 Feb 19 03:09:53 PM PST 24 755319820 ps
T1046 /workspace/coverage/default/3.keymgr_sideload_otbn.134881260 Feb 19 03:09:08 PM PST 24 Feb 19 03:09:16 PM PST 24 535418449 ps
T1047 /workspace/coverage/default/39.keymgr_sideload_aes.984781003 Feb 19 03:13:04 PM PST 24 Feb 19 03:13:28 PM PST 24 2792068914 ps
T1048 /workspace/coverage/default/0.keymgr_smoke.1171454434 Feb 19 03:08:20 PM PST 24 Feb 19 03:08:26 PM PST 24 103842259 ps
T1049 /workspace/coverage/default/9.keymgr_sideload_aes.1932819850 Feb 19 03:10:02 PM PST 24 Feb 19 03:10:34 PM PST 24 881382273 ps
T1050 /workspace/coverage/default/36.keymgr_smoke.3288783907 Feb 19 03:12:55 PM PST 24 Feb 19 03:13:06 PM PST 24 1182005536 ps
T105 /workspace/coverage/default/45.keymgr_custom_cm.288284687 Feb 19 03:13:39 PM PST 24 Feb 19 03:13:56 PM PST 24 248858962 ps
T1051 /workspace/coverage/default/44.keymgr_sideload_otbn.499715706 Feb 19 03:13:29 PM PST 24 Feb 19 03:13:38 PM PST 24 163195364 ps
T1052 /workspace/coverage/default/47.keymgr_stress_all.1692438861 Feb 19 03:13:40 PM PST 24 Feb 19 03:14:16 PM PST 24 2127688434 ps
T1053 /workspace/coverage/default/42.keymgr_alert_test.1333484636 Feb 19 03:13:33 PM PST 24 Feb 19 03:13:44 PM PST 24 15567647 ps
T1054 /workspace/coverage/default/15.keymgr_hwsw_invalid_input.43352106 Feb 19 03:10:47 PM PST 24 Feb 19 03:10:56 PM PST 24 151828930 ps
T359 /workspace/coverage/default/18.keymgr_cfg_regwen.3595720769 Feb 19 03:11:13 PM PST 24 Feb 19 03:11:21 PM PST 24 95592423 ps
T1055 /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1163998789 Feb 19 03:11:28 PM PST 24 Feb 19 03:11:33 PM PST 24 164736307 ps
T1056 /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.4085294673 Feb 19 03:11:24 PM PST 24 Feb 19 03:11:42 PM PST 24 537586987 ps
T305 /workspace/coverage/default/38.keymgr_kmac_rsp_err.2888686719 Feb 19 03:12:55 PM PST 24 Feb 19 03:13:03 PM PST 24 237844553 ps
T1057 /workspace/coverage/default/35.keymgr_alert_test.1186991555 Feb 19 03:12:50 PM PST 24 Feb 19 03:12:54 PM PST 24 15275693 ps
T369 /workspace/coverage/default/8.keymgr_kmac_rsp_err.4229398773 Feb 19 03:09:59 PM PST 24 Feb 19 03:10:05 PM PST 24 118611854 ps
T1058 /workspace/coverage/default/47.keymgr_alert_test.1032062447 Feb 19 03:13:42 PM PST 24 Feb 19 03:13:55 PM PST 24 75294322 ps
T1059 /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2030203274 Feb 19 03:09:21 PM PST 24 Feb 19 03:09:25 PM PST 24 101697581 ps
T1060 /workspace/coverage/default/34.keymgr_sideload.1252069641 Feb 19 03:12:52 PM PST 24 Feb 19 03:13:30 PM PST 24 1352497150 ps
T1061 /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2798536467 Feb 19 03:09:29 PM PST 24 Feb 19 03:09:49 PM PST 24 515009960 ps
T1062 /workspace/coverage/default/33.keymgr_stress_all.410029505 Feb 19 03:12:48 PM PST 24 Feb 19 03:12:57 PM PST 24 205554998 ps
T1063 /workspace/coverage/default/40.keymgr_hwsw_invalid_input.4035076071 Feb 19 03:13:11 PM PST 24 Feb 19 03:13:19 PM PST 24 135017145 ps
T322 /workspace/coverage/default/39.keymgr_random.736418633 Feb 19 03:13:00 PM PST 24 Feb 19 03:13:10 PM PST 24 228647773 ps
T1064 /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3001668787 Feb 19 03:13:33 PM PST 24 Feb 19 03:13:46 PM PST 24 90649464 ps
T1065 /workspace/coverage/default/6.keymgr_smoke.2443898873 Feb 19 03:09:40 PM PST 24 Feb 19 03:09:51 PM PST 24 4767312943 ps
T1066 /workspace/coverage/default/36.keymgr_sideload_kmac.1164466378 Feb 19 03:12:53 PM PST 24 Feb 19 03:13:02 PM PST 24 965932545 ps
T203 /workspace/coverage/default/26.keymgr_stress_all.3066115095 Feb 19 03:12:11 PM PST 24 Feb 19 03:12:50 PM PST 24 2350752506 ps
T1067 /workspace/coverage/default/15.keymgr_sideload_aes.4168726842 Feb 19 03:10:45 PM PST 24 Feb 19 03:10:50 PM PST 24 241057579 ps
T1068 /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2680332519 Feb 19 03:13:31 PM PST 24 Feb 19 03:13:40 PM PST 24 246457444 ps
T1069 /workspace/coverage/default/29.keymgr_cfg_regwen.2355956068 Feb 19 03:12:15 PM PST 24 Feb 19 03:12:20 PM PST 24 54690539 ps
T1070 /workspace/coverage/default/42.keymgr_sideload_kmac.132516628 Feb 19 03:13:17 PM PST 24 Feb 19 03:13:25 PM PST 24 113792811 ps
T1071 /workspace/coverage/default/18.keymgr_direct_to_disabled.2678188098 Feb 19 03:11:14 PM PST 24 Feb 19 03:11:20 PM PST 24 1077481382 ps

Test location /workspace/coverage/default/33.keymgr_custom_cm.1035162084
Short name T4
Test name
Test status
Simulation time 430289150 ps
CPU time 4.79 seconds
Started Feb 19 03:12:42 PM PST 24
Finished Feb 19 03:12:49 PM PST 24
Peak memory 208648 kb
Host smart-99ccd9fb-e568-425f-b985-f61abbb919fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035162084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1035162084
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.959020589
Short name T39
Test name
Test status
Simulation time 2775292305 ps
CPU time 69.53 seconds
Started Feb 19 03:10:48 PM PST 24
Finished Feb 19 03:12:00 PM PST 24
Peak memory 222524 kb
Host smart-ede167a0-4dac-40ca-9472-b21bfe131350
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959020589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.959020589
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3145847307
Short name T7
Test name
Test status
Simulation time 14376412318 ps
CPU time 142.97 seconds
Started Feb 19 03:13:37 PM PST 24
Finished Feb 19 03:16:12 PM PST 24
Peak memory 216684 kb
Host smart-c2597f8c-da22-4584-a727-ea5f495dfb67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145847307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3145847307
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3054882527
Short name T10
Test name
Test status
Simulation time 56935312077 ps
CPU time 212.84 seconds
Started Feb 19 03:09:28 PM PST 24
Finished Feb 19 03:13:10 PM PST 24
Peak memory 303484 kb
Host smart-6ef188c2-0e87-424d-b2ba-c82cd0ffc44d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054882527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3054882527
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2629687777
Short name T91
Test name
Test status
Simulation time 327098470 ps
CPU time 4.63 seconds
Started Feb 19 03:10:36 PM PST 24
Finished Feb 19 03:10:48 PM PST 24
Peak memory 222540 kb
Host smart-b69bc251-8648-4b5d-a4b0-4afa572a04c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629687777 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2629687777
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3858730821
Short name T52
Test name
Test status
Simulation time 17923120712 ps
CPU time 102.95 seconds
Started Feb 19 03:13:11 PM PST 24
Finished Feb 19 03:14:59 PM PST 24
Peak memory 215324 kb
Host smart-569a54e1-620e-4ac4-af04-1380232b1ed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858730821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3858730821
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2577861139
Short name T108
Test name
Test status
Simulation time 212145519 ps
CPU time 7.76 seconds
Started Feb 19 12:36:43 PM PST 24
Finished Feb 19 12:36:54 PM PST 24
Peak memory 213624 kb
Host smart-e9c29477-a96e-483e-9a7b-d8814052bba9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577861139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2577861139
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2583834126
Short name T46
Test name
Test status
Simulation time 2100679088 ps
CPU time 13.25 seconds
Started Feb 19 03:10:31 PM PST 24
Finished Feb 19 03:10:48 PM PST 24
Peak memory 211060 kb
Host smart-9b5aec54-6b1c-4209-88ec-29ffe36d4825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583834126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2583834126
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1192106781
Short name T40
Test name
Test status
Simulation time 40197901468 ps
CPU time 410.77 seconds
Started Feb 19 03:11:54 PM PST 24
Finished Feb 19 03:18:48 PM PST 24
Peak memory 217692 kb
Host smart-7cf89212-077c-4f91-b5cd-9272347e9466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192106781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1192106781
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2744255310
Short name T113
Test name
Test status
Simulation time 10367183519 ps
CPU time 67.36 seconds
Started Feb 19 03:13:25 PM PST 24
Finished Feb 19 03:14:36 PM PST 24
Peak memory 214372 kb
Host smart-5a04940a-ec08-43a3-94c5-1c211faa6abd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2744255310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2744255310
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3241513650
Short name T282
Test name
Test status
Simulation time 1083691980 ps
CPU time 29.8 seconds
Started Feb 19 03:11:00 PM PST 24
Finished Feb 19 03:11:31 PM PST 24
Peak memory 215236 kb
Host smart-229b1618-6cbf-457f-9ce8-a5b46b5c16ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3241513650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3241513650
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3697922504
Short name T92
Test name
Test status
Simulation time 626879818 ps
CPU time 11.65 seconds
Started Feb 19 03:13:43 PM PST 24
Finished Feb 19 03:14:07 PM PST 24
Peak memory 222624 kb
Host smart-5661dd42-12b3-49c7-8ba7-54821c742fd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697922504 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3697922504
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1453597703
Short name T23
Test name
Test status
Simulation time 494153144 ps
CPU time 10.51 seconds
Started Feb 19 03:13:24 PM PST 24
Finished Feb 19 03:13:39 PM PST 24
Peak memory 214464 kb
Host smart-07c3bee1-3410-445a-924b-565d5ae6cbac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453597703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1453597703
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2065614952
Short name T336
Test name
Test status
Simulation time 575736920 ps
CPU time 32.7 seconds
Started Feb 19 03:13:25 PM PST 24
Finished Feb 19 03:14:01 PM PST 24
Peak memory 214260 kb
Host smart-eec04d01-e27a-4ef8-a267-5272480546be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2065614952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2065614952
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2838494449
Short name T42
Test name
Test status
Simulation time 107832871816 ps
CPU time 592.83 seconds
Started Feb 19 03:10:14 PM PST 24
Finished Feb 19 03:20:11 PM PST 24
Peak memory 230272 kb
Host smart-c7aff527-fef8-44e4-9dce-565ed123b178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838494449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2838494449
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.971002043
Short name T335
Test name
Test status
Simulation time 12029605110 ps
CPU time 161.06 seconds
Started Feb 19 03:12:25 PM PST 24
Finished Feb 19 03:15:08 PM PST 24
Peak memory 215724 kb
Host smart-ca41961b-a70e-472e-b40a-00c27d901fbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=971002043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.971002043
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.25039211
Short name T13
Test name
Test status
Simulation time 762536630 ps
CPU time 23.79 seconds
Started Feb 19 03:12:44 PM PST 24
Finished Feb 19 03:13:10 PM PST 24
Peak memory 214440 kb
Host smart-7a5dcbac-a800-48be-84dc-7cf6395c5045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25039211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.25039211
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3034240989
Short name T76
Test name
Test status
Simulation time 165820531 ps
CPU time 7.03 seconds
Started Feb 19 03:12:04 PM PST 24
Finished Feb 19 03:12:13 PM PST 24
Peak memory 214536 kb
Host smart-b284bb75-165a-4c3b-a1f3-33ce5618c5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034240989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3034240989
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1817026048
Short name T241
Test name
Test status
Simulation time 198646586 ps
CPU time 10.44 seconds
Started Feb 19 03:12:47 PM PST 24
Finished Feb 19 03:13:01 PM PST 24
Peak memory 215436 kb
Host smart-4f1ce4af-1818-43e2-9a2f-0eb514d2f681
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1817026048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1817026048
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2982009287
Short name T401
Test name
Test status
Simulation time 1583097223 ps
CPU time 11.72 seconds
Started Feb 19 03:13:32 PM PST 24
Finished Feb 19 03:13:54 PM PST 24
Peak memory 214548 kb
Host smart-5a56767f-f44d-4bdd-a8cb-7611ac657451
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2982009287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2982009287
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1695665269
Short name T84
Test name
Test status
Simulation time 132236862 ps
CPU time 2.75 seconds
Started Feb 19 03:13:00 PM PST 24
Finished Feb 19 03:13:04 PM PST 24
Peak memory 222476 kb
Host smart-a3204071-22af-40f7-aeff-2bb6a8a0647c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695665269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1695665269
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.591729737
Short name T43
Test name
Test status
Simulation time 40468408683 ps
CPU time 72.99 seconds
Started Feb 19 03:11:27 PM PST 24
Finished Feb 19 03:12:43 PM PST 24
Peak memory 216468 kb
Host smart-7984d0e8-8231-426f-952f-0784f51a332a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591729737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.591729737
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3548620646
Short name T185
Test name
Test status
Simulation time 137427180 ps
CPU time 4.26 seconds
Started Feb 19 03:10:32 PM PST 24
Finished Feb 19 03:10:43 PM PST 24
Peak memory 220416 kb
Host smart-ceb70373-a65b-4f28-ba9d-a28d9e6d0819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548620646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3548620646
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.299083945
Short name T28
Test name
Test status
Simulation time 724218600 ps
CPU time 4.57 seconds
Started Feb 19 03:10:02 PM PST 24
Finished Feb 19 03:10:08 PM PST 24
Peak memory 218580 kb
Host smart-961528f7-aec3-4bdf-a654-eb086a3fe571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299083945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.299083945
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2837591232
Short name T395
Test name
Test status
Simulation time 1172540416 ps
CPU time 15.16 seconds
Started Feb 19 03:13:40 PM PST 24
Finished Feb 19 03:14:08 PM PST 24
Peak memory 215104 kb
Host smart-c491524a-2e6e-436f-a6d3-9bbd98290c6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2837591232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2837591232
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3143076975
Short name T111
Test name
Test status
Simulation time 1939889324 ps
CPU time 41.42 seconds
Started Feb 19 12:36:54 PM PST 24
Finished Feb 19 12:37:37 PM PST 24
Peak memory 229964 kb
Host smart-f14afdb7-b2b2-415c-8d1b-57eaca2a954f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143076975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3143076975
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2632794169
Short name T148
Test name
Test status
Simulation time 247548474 ps
CPU time 9.64 seconds
Started Feb 19 12:36:56 PM PST 24
Finished Feb 19 12:37:07 PM PST 24
Peak memory 213540 kb
Host smart-4661bec4-a442-4b3d-a133-fb7f8b7c6ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632794169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2632794169
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1881820726
Short name T21
Test name
Test status
Simulation time 1761605293 ps
CPU time 5.95 seconds
Started Feb 19 03:13:45 PM PST 24
Finished Feb 19 03:14:03 PM PST 24
Peak memory 218372 kb
Host smart-b6a3adf5-b2a2-4257-b559-f097481b335c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881820726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1881820726
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1033456300
Short name T104
Test name
Test status
Simulation time 665336044 ps
CPU time 5.74 seconds
Started Feb 19 03:10:57 PM PST 24
Finished Feb 19 03:11:04 PM PST 24
Peak memory 217720 kb
Host smart-4287e693-8ff0-40fb-b9c9-fcef5ef016cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033456300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1033456300
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.524809683
Short name T276
Test name
Test status
Simulation time 201946310 ps
CPU time 10.5 seconds
Started Feb 19 03:10:32 PM PST 24
Finished Feb 19 03:10:49 PM PST 24
Peak memory 222584 kb
Host smart-e082171b-be72-4287-ba68-a65fa5f344f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=524809683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.524809683
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.321265415
Short name T71
Test name
Test status
Simulation time 23845610 ps
CPU time 0.73 seconds
Started Feb 19 03:11:24 PM PST 24
Finished Feb 19 03:11:27 PM PST 24
Peak memory 205820 kb
Host smart-b4580df7-2399-4dc4-84c4-6961dd2fad3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321265415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.321265415
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1142852546
Short name T168
Test name
Test status
Simulation time 283715931 ps
CPU time 6.16 seconds
Started Feb 19 03:10:26 PM PST 24
Finished Feb 19 03:10:33 PM PST 24
Peak memory 214476 kb
Host smart-a7f02cb3-0fda-4651-95a7-33b2f416066c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142852546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1142852546
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.524221150
Short name T61
Test name
Test status
Simulation time 1862508321 ps
CPU time 23.75 seconds
Started Feb 19 03:10:32 PM PST 24
Finished Feb 19 03:11:01 PM PST 24
Peak memory 214716 kb
Host smart-b6916ffa-856f-4198-a984-db8628a272c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524221150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.524221150
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2326116109
Short name T220
Test name
Test status
Simulation time 250269041 ps
CPU time 13.55 seconds
Started Feb 19 03:11:06 PM PST 24
Finished Feb 19 03:11:25 PM PST 24
Peak memory 214556 kb
Host smart-df0774b0-cbe0-4fbb-8f9e-07216058ab06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2326116109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2326116109
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2641333770
Short name T224
Test name
Test status
Simulation time 457107012 ps
CPU time 15.14 seconds
Started Feb 19 03:13:43 PM PST 24
Finished Feb 19 03:14:11 PM PST 24
Peak memory 215260 kb
Host smart-44839f10-304c-4efe-9bb4-59bcc0313e52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2641333770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2641333770
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1605837754
Short name T141
Test name
Test status
Simulation time 11220294685 ps
CPU time 72.25 seconds
Started Feb 19 12:37:03 PM PST 24
Finished Feb 19 12:38:18 PM PST 24
Peak memory 218088 kb
Host smart-2ca24014-10f2-4472-b6a6-2abe01027db1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605837754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1605837754
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2961156650
Short name T183
Test name
Test status
Simulation time 531529915 ps
CPU time 25.53 seconds
Started Feb 19 03:12:48 PM PST 24
Finished Feb 19 03:13:17 PM PST 24
Peak memory 215804 kb
Host smart-de25c101-b98c-4586-8fc8-22d25d24ade9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961156650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2961156650
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1690367594
Short name T778
Test name
Test status
Simulation time 4917354386 ps
CPU time 54.27 seconds
Started Feb 19 03:08:45 PM PST 24
Finished Feb 19 03:09:46 PM PST 24
Peak memory 216992 kb
Host smart-eeac82b6-5640-4fd3-b85b-9ff63082f31a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690367594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1690367594
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.264374484
Short name T184
Test name
Test status
Simulation time 1053761763 ps
CPU time 40.42 seconds
Started Feb 19 03:09:00 PM PST 24
Finished Feb 19 03:09:45 PM PST 24
Peak memory 216780 kb
Host smart-c208c60d-0e57-495e-998d-8d7593b75d56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264374484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.264374484
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3066115095
Short name T203
Test name
Test status
Simulation time 2350752506 ps
CPU time 35.18 seconds
Started Feb 19 03:12:11 PM PST 24
Finished Feb 19 03:12:50 PM PST 24
Peak memory 222620 kb
Host smart-d81e996f-370a-4dbe-80d8-dc1da6b52423
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066115095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3066115095
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2876262560
Short name T309
Test name
Test status
Simulation time 482788135 ps
CPU time 5.66 seconds
Started Feb 19 03:12:09 PM PST 24
Finished Feb 19 03:12:16 PM PST 24
Peak memory 214356 kb
Host smart-f5533465-f3e6-4a62-87cd-c56f5199c2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876262560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2876262560
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1611867666
Short name T332
Test name
Test status
Simulation time 177790467 ps
CPU time 9.81 seconds
Started Feb 19 03:13:04 PM PST 24
Finished Feb 19 03:13:16 PM PST 24
Peak memory 214940 kb
Host smart-0b01428d-6ebd-474e-951d-8ce2abf380bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611867666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1611867666
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2706743222
Short name T445
Test name
Test status
Simulation time 192014249 ps
CPU time 3.04 seconds
Started Feb 19 12:36:51 PM PST 24
Finished Feb 19 12:36:56 PM PST 24
Peak memory 221676 kb
Host smart-ed868ea7-74a9-4a0a-aaf8-87b458f899a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706743222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2706743222
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1434406697
Short name T142
Test name
Test status
Simulation time 1970277062 ps
CPU time 7.51 seconds
Started Feb 19 12:36:40 PM PST 24
Finished Feb 19 12:36:52 PM PST 24
Peak memory 208924 kb
Host smart-b43176df-20e9-4f4d-b57a-d22bbcc6fd5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434406697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1434406697
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.6916093
Short name T102
Test name
Test status
Simulation time 510745649 ps
CPU time 4.19 seconds
Started Feb 19 03:13:29 PM PST 24
Finished Feb 19 03:13:40 PM PST 24
Peak memory 222660 kb
Host smart-44a0298a-dff1-4f98-bbc7-bb7ba367f3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6916093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.6916093
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.288284687
Short name T105
Test name
Test status
Simulation time 248858962 ps
CPU time 3.94 seconds
Started Feb 19 03:13:39 PM PST 24
Finished Feb 19 03:13:56 PM PST 24
Peak memory 215396 kb
Host smart-cd2d2c83-afc9-4c4c-9f73-b3f6559a1a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288284687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.288284687
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3474308469
Short name T247
Test name
Test status
Simulation time 1349310042 ps
CPU time 12.12 seconds
Started Feb 19 03:09:02 PM PST 24
Finished Feb 19 03:09:17 PM PST 24
Peak memory 222388 kb
Host smart-b97c8fa5-31d1-4928-a599-80964448d28b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474308469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3474308469
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.972240797
Short name T130
Test name
Test status
Simulation time 900706249 ps
CPU time 13.15 seconds
Started Feb 19 03:12:54 PM PST 24
Finished Feb 19 03:13:11 PM PST 24
Peak memory 215648 kb
Host smart-248c68b4-81db-478b-9d40-6fc2b5af4c57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=972240797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.972240797
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1552769749
Short name T114
Test name
Test status
Simulation time 592845309 ps
CPU time 8.13 seconds
Started Feb 19 03:12:55 PM PST 24
Finished Feb 19 03:13:07 PM PST 24
Peak memory 214260 kb
Host smart-872fd89f-bf99-40a2-8cfd-945044a6deaf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552769749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1552769749
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1221891663
Short name T208
Test name
Test status
Simulation time 808315342 ps
CPU time 23.68 seconds
Started Feb 19 03:13:45 PM PST 24
Finished Feb 19 03:14:20 PM PST 24
Peak memory 215736 kb
Host smart-65d73953-61f3-4ba2-aa10-3ad279e6de79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221891663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1221891663
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2866311194
Short name T333
Test name
Test status
Simulation time 6322320447 ps
CPU time 82.18 seconds
Started Feb 19 03:09:42 PM PST 24
Finished Feb 19 03:11:06 PM PST 24
Peak memory 222480 kb
Host smart-93348ed1-37d4-42c6-84d0-c124132f1670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2866311194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2866311194
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.940241331
Short name T265
Test name
Test status
Simulation time 14210152588 ps
CPU time 125.92 seconds
Started Feb 19 03:09:43 PM PST 24
Finished Feb 19 03:11:50 PM PST 24
Peak memory 229768 kb
Host smart-1e24de3f-3690-42a7-9d96-4022e4aa4579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940241331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.940241331
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.66071659
Short name T147
Test name
Test status
Simulation time 118410928 ps
CPU time 3.51 seconds
Started Feb 19 12:36:56 PM PST 24
Finished Feb 19 12:37:01 PM PST 24
Peak memory 208940 kb
Host smart-fb63b039-8993-44e1-b9a2-2aab4524fabe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66071659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.66071659
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2070360030
Short name T103
Test name
Test status
Simulation time 360856082 ps
CPU time 2.78 seconds
Started Feb 19 03:12:48 PM PST 24
Finished Feb 19 03:12:54 PM PST 24
Peak memory 218508 kb
Host smart-40214c88-fc4c-4c30-ab25-5157b8a305e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070360030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2070360030
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.4128347199
Short name T357
Test name
Test status
Simulation time 1573869096 ps
CPU time 5.11 seconds
Started Feb 19 03:10:32 PM PST 24
Finished Feb 19 03:10:42 PM PST 24
Peak memory 214296 kb
Host smart-db0e72fe-0527-41eb-9ff0-7caf123fa772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128347199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.4128347199
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_random.2073793346
Short name T165
Test name
Test status
Simulation time 302480862 ps
CPU time 10.14 seconds
Started Feb 19 03:10:47 PM PST 24
Finished Feb 19 03:11:00 PM PST 24
Peak memory 209076 kb
Host smart-1bd29a9c-3fba-418f-8466-0064a9e10836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073793346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2073793346
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1092678097
Short name T298
Test name
Test status
Simulation time 5032354287 ps
CPU time 50.58 seconds
Started Feb 19 03:11:13 PM PST 24
Finished Feb 19 03:12:08 PM PST 24
Peak memory 220812 kb
Host smart-a7788ec5-71b1-4c50-bd26-05da8bf23141
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092678097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1092678097
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.205121979
Short name T149
Test name
Test status
Simulation time 336626439 ps
CPU time 8.66 seconds
Started Feb 19 12:36:58 PM PST 24
Finished Feb 19 12:37:08 PM PST 24
Peak memory 213520 kb
Host smart-3093dd54-d2a2-4d72-884e-08daa82e262c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205121979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.205121979
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1399818646
Short name T151
Test name
Test status
Simulation time 1266825741 ps
CPU time 6.18 seconds
Started Feb 19 12:37:02 PM PST 24
Finished Feb 19 12:37:11 PM PST 24
Peak memory 209000 kb
Host smart-5fd3b88b-f48e-42a4-9080-fabbd013d6b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399818646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1399818646
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2942774466
Short name T98
Test name
Test status
Simulation time 239607422 ps
CPU time 2.74 seconds
Started Feb 19 03:08:47 PM PST 24
Finished Feb 19 03:08:55 PM PST 24
Peak memory 210648 kb
Host smart-d7b0f456-cfa4-4c8b-93a1-054658951c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942774466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2942774466
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.4035076071
Short name T1063
Test name
Test status
Simulation time 135017145 ps
CPU time 2.71 seconds
Started Feb 19 03:13:11 PM PST 24
Finished Feb 19 03:13:19 PM PST 24
Peak memory 219140 kb
Host smart-1a6dae2f-c0a4-41a6-9b06-0a8f6ebe87ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035076071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.4035076071
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2932535749
Short name T245
Test name
Test status
Simulation time 1242254093 ps
CPU time 13.86 seconds
Started Feb 19 03:08:46 PM PST 24
Finished Feb 19 03:09:05 PM PST 24
Peak memory 210768 kb
Host smart-abdfee1b-848b-4b4e-8720-3c3158b11b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932535749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2932535749
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2922992655
Short name T299
Test name
Test status
Simulation time 228649708 ps
CPU time 7.77 seconds
Started Feb 19 03:10:23 PM PST 24
Finished Feb 19 03:10:33 PM PST 24
Peak memory 222636 kb
Host smart-eaeecf7d-6cdc-4f71-9261-4027d7e98b99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2922992655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2922992655
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1657425608
Short name T85
Test name
Test status
Simulation time 254372052 ps
CPU time 3.31 seconds
Started Feb 19 03:10:48 PM PST 24
Finished Feb 19 03:10:54 PM PST 24
Peak memory 214388 kb
Host smart-d0299e06-bc37-49ad-9bff-a59cf48a2121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657425608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1657425608
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2719790779
Short name T294
Test name
Test status
Simulation time 353569934 ps
CPU time 3.98 seconds
Started Feb 19 03:11:32 PM PST 24
Finished Feb 19 03:11:38 PM PST 24
Peak memory 208584 kb
Host smart-fffe9e4c-89a7-44d0-858a-9f6dd1bfdb24
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719790779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2719790779
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2575580077
Short name T204
Test name
Test status
Simulation time 24374354217 ps
CPU time 256.94 seconds
Started Feb 19 03:11:42 PM PST 24
Finished Feb 19 03:16:00 PM PST 24
Peak memory 222404 kb
Host smart-fb51ebdb-8843-40bc-8452-28d83754b80d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575580077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2575580077
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.116046163
Short name T191
Test name
Test status
Simulation time 1363182046 ps
CPU time 20.07 seconds
Started Feb 19 03:11:54 PM PST 24
Finished Feb 19 03:12:17 PM PST 24
Peak memory 222448 kb
Host smart-4e7b06d9-fc3d-4311-977f-20433af6a9ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116046163 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.116046163
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2472061996
Short name T273
Test name
Test status
Simulation time 361855494 ps
CPU time 4.05 seconds
Started Feb 19 03:12:11 PM PST 24
Finished Feb 19 03:12:18 PM PST 24
Peak memory 208892 kb
Host smart-aa72ed43-73b6-4c97-8292-bc9ef56c366e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472061996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2472061996
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.143652610
Short name T269
Test name
Test status
Simulation time 64213000 ps
CPU time 4.36 seconds
Started Feb 19 03:12:02 PM PST 24
Finished Feb 19 03:12:08 PM PST 24
Peak memory 215352 kb
Host smart-f5e3393d-5090-453f-b0d3-4321dbebd60a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=143652610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.143652610
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.133613217
Short name T172
Test name
Test status
Simulation time 207057688 ps
CPU time 2.95 seconds
Started Feb 19 03:12:50 PM PST 24
Finished Feb 19 03:12:56 PM PST 24
Peak memory 206856 kb
Host smart-40dc5a86-6110-4100-bef5-7382fd5f16cd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133613217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.133613217
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1250897217
Short name T128
Test name
Test status
Simulation time 135073367 ps
CPU time 4.46 seconds
Started Feb 19 12:37:01 PM PST 24
Finished Feb 19 12:37:07 PM PST 24
Peak memory 213380 kb
Host smart-629bac01-b310-4183-9964-a12b56b3210a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250897217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1250897217
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1334987485
Short name T122
Test name
Test status
Simulation time 119707757 ps
CPU time 5.11 seconds
Started Feb 19 12:37:15 PM PST 24
Finished Feb 19 12:37:22 PM PST 24
Peak memory 208744 kb
Host smart-37c0c6da-5e54-4e07-946f-434717ed160f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334987485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1334987485
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2096024547
Short name T659
Test name
Test status
Simulation time 104874573 ps
CPU time 1.96 seconds
Started Feb 19 03:10:34 PM PST 24
Finished Feb 19 03:10:43 PM PST 24
Peak memory 221076 kb
Host smart-83a358f2-890f-49c7-add9-192e8da71654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096024547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2096024547
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2421842344
Short name T152
Test name
Test status
Simulation time 41254186 ps
CPU time 1.9 seconds
Started Feb 19 03:13:40 PM PST 24
Finished Feb 19 03:13:55 PM PST 24
Peak memory 209724 kb
Host smart-95643edc-bd8f-4670-b5e7-930523de6240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421842344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2421842344
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1192053543
Short name T1035
Test name
Test status
Simulation time 193706373 ps
CPU time 7.55 seconds
Started Feb 19 03:08:30 PM PST 24
Finished Feb 19 03:08:38 PM PST 24
Peak memory 221932 kb
Host smart-4f60c3ad-a612-4303-8877-dd30a368e0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192053543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1192053543
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2251872139
Short name T79
Test name
Test status
Simulation time 397306836 ps
CPU time 4.37 seconds
Started Feb 19 03:08:27 PM PST 24
Finished Feb 19 03:08:32 PM PST 24
Peak memory 214320 kb
Host smart-be834539-f3ad-439f-9981-9f31bacff202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251872139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2251872139
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3238833613
Short name T351
Test name
Test status
Simulation time 290799034 ps
CPU time 5.2 seconds
Started Feb 19 03:08:25 PM PST 24
Finished Feb 19 03:08:31 PM PST 24
Peak memory 211132 kb
Host smart-a5a2f179-177e-4145-bb16-545c51130496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238833613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3238833613
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.288019716
Short name T257
Test name
Test status
Simulation time 212342292 ps
CPU time 5.27 seconds
Started Feb 19 03:08:32 PM PST 24
Finished Feb 19 03:08:37 PM PST 24
Peak memory 218292 kb
Host smart-2e36f898-fcab-44a2-876f-739941c95e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288019716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.288019716
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2717811393
Short name T310
Test name
Test status
Simulation time 57088822 ps
CPU time 3.41 seconds
Started Feb 19 03:10:22 PM PST 24
Finished Feb 19 03:10:26 PM PST 24
Peak memory 209772 kb
Host smart-fa7432af-9a24-4f86-b9f0-1fcb2e464067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717811393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2717811393
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3117319677
Short name T189
Test name
Test status
Simulation time 89443751 ps
CPU time 3.92 seconds
Started Feb 19 03:10:34 PM PST 24
Finished Feb 19 03:10:45 PM PST 24
Peak memory 220228 kb
Host smart-15e6eb67-8f19-490f-9785-043f49b6c2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117319677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3117319677
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3371850449
Short name T291
Test name
Test status
Simulation time 205075402 ps
CPU time 2.33 seconds
Started Feb 19 03:10:34 PM PST 24
Finished Feb 19 03:10:43 PM PST 24
Peak memory 209652 kb
Host smart-9b0b661c-fb1f-4302-97a7-69a643e743a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371850449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3371850449
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.4032725886
Short name T314
Test name
Test status
Simulation time 1113134890 ps
CPU time 7.34 seconds
Started Feb 19 03:10:39 PM PST 24
Finished Feb 19 03:10:51 PM PST 24
Peak memory 209584 kb
Host smart-00c0936a-0d22-46eb-b26f-56760efe16fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032725886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.4032725886
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.570243030
Short name T198
Test name
Test status
Simulation time 79016855 ps
CPU time 4.06 seconds
Started Feb 19 03:10:46 PM PST 24
Finished Feb 19 03:10:53 PM PST 24
Peak memory 209660 kb
Host smart-a9c7a6f1-7327-4716-8d18-4c3e1a6ab981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570243030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.570243030
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.88366129
Short name T718
Test name
Test status
Simulation time 160425601 ps
CPU time 2.55 seconds
Started Feb 19 03:10:44 PM PST 24
Finished Feb 19 03:10:50 PM PST 24
Peak memory 209944 kb
Host smart-0140c31c-d1b1-4068-88bc-e4d3d0a07957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88366129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.88366129
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.338841046
Short name T202
Test name
Test status
Simulation time 46492773648 ps
CPU time 483.64 seconds
Started Feb 19 03:10:53 PM PST 24
Finished Feb 19 03:18:58 PM PST 24
Peak memory 222584 kb
Host smart-bc4f9cc0-4a5a-45cb-987d-fbef7075fb9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338841046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.338841046
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.8644826
Short name T30
Test name
Test status
Simulation time 931888963 ps
CPU time 3.58 seconds
Started Feb 19 03:09:00 PM PST 24
Finished Feb 19 03:09:08 PM PST 24
Peak memory 222776 kb
Host smart-803dda6b-8576-4670-bcdf-22909f2c47e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8644826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.8644826
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.4067913058
Short name T998
Test name
Test status
Simulation time 582643471 ps
CPU time 6.82 seconds
Started Feb 19 03:11:24 PM PST 24
Finished Feb 19 03:11:33 PM PST 24
Peak memory 222616 kb
Host smart-91214c44-9016-4ece-aa38-bd4136ef2d29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067913058 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.4067913058
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.4183825819
Short name T196
Test name
Test status
Simulation time 72487344 ps
CPU time 3 seconds
Started Feb 19 03:11:27 PM PST 24
Finished Feb 19 03:11:32 PM PST 24
Peak memory 215964 kb
Host smart-f1e0337e-7b33-4a1b-ac0d-94b8c9f415e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183825819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.4183825819
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2657509782
Short name T197
Test name
Test status
Simulation time 1283776232 ps
CPU time 11.98 seconds
Started Feb 19 03:11:27 PM PST 24
Finished Feb 19 03:11:42 PM PST 24
Peak memory 221764 kb
Host smart-f7f16adc-96c5-428e-99af-72f983c3adda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657509782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2657509782
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3605274958
Short name T374
Test name
Test status
Simulation time 768211881 ps
CPU time 3.27 seconds
Started Feb 19 03:11:52 PM PST 24
Finished Feb 19 03:11:58 PM PST 24
Peak memory 214308 kb
Host smart-4530e943-e672-43a0-8b9b-aeeae2fe6fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605274958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3605274958
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1873643547
Short name T186
Test name
Test status
Simulation time 109122469 ps
CPU time 3.47 seconds
Started Feb 19 03:12:13 PM PST 24
Finished Feb 19 03:12:19 PM PST 24
Peak memory 222820 kb
Host smart-aff793ca-739c-45cf-8522-65bae6035ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873643547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1873643547
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3802382639
Short name T367
Test name
Test status
Simulation time 84900025 ps
CPU time 3.05 seconds
Started Feb 19 03:12:07 PM PST 24
Finished Feb 19 03:12:13 PM PST 24
Peak memory 207780 kb
Host smart-e32503bf-091b-4353-aafe-c727e43fb138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802382639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3802382639
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1282103021
Short name T60
Test name
Test status
Simulation time 218414065 ps
CPU time 7.63 seconds
Started Feb 19 03:09:17 PM PST 24
Finished Feb 19 03:09:26 PM PST 24
Peak memory 209872 kb
Host smart-4702a617-183b-4109-8d1e-1f8479236af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282103021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1282103021
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.745454193
Short name T205
Test name
Test status
Simulation time 5243672956 ps
CPU time 58.82 seconds
Started Feb 19 03:12:18 PM PST 24
Finished Feb 19 03:13:19 PM PST 24
Peak memory 222464 kb
Host smart-3773b8c7-862d-42f9-b536-f3b6229cd9e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745454193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.745454193
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3061944359
Short name T373
Test name
Test status
Simulation time 160877162 ps
CPU time 2.95 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:12:58 PM PST 24
Peak memory 208836 kb
Host smart-066a44ee-7afa-48c7-b80d-df3c4f38ee7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061944359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3061944359
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1514577601
Short name T227
Test name
Test status
Simulation time 343912438 ps
CPU time 9.78 seconds
Started Feb 19 03:09:57 PM PST 24
Finished Feb 19 03:10:08 PM PST 24
Peak memory 222484 kb
Host smart-aba960c0-60dd-481c-8a5d-9bf273dedf04
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1514577601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1514577601
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1013922222
Short name T133
Test name
Test status
Simulation time 511655186 ps
CPU time 7.27 seconds
Started Feb 19 12:36:29 PM PST 24
Finished Feb 19 12:36:39 PM PST 24
Peak memory 205192 kb
Host smart-739b6eca-5583-4c8d-a898-1b63120940f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013922222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
013922222
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.928777264
Short name T463
Test name
Test status
Simulation time 129092647 ps
CPU time 7.27 seconds
Started Feb 19 12:36:24 PM PST 24
Finished Feb 19 12:36:32 PM PST 24
Peak memory 205212 kb
Host smart-96f1914c-0e4b-4017-99fc-3d9e36aae0f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928777264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.928777264
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2126202629
Short name T512
Test name
Test status
Simulation time 16717119 ps
CPU time 1.07 seconds
Started Feb 19 12:36:22 PM PST 24
Finished Feb 19 12:36:23 PM PST 24
Peak memory 205212 kb
Host smart-4d5708e0-93fd-4fa6-a8d5-219416032cc8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126202629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
126202629
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.313061154
Short name T503
Test name
Test status
Simulation time 33882169 ps
CPU time 1.75 seconds
Started Feb 19 12:36:30 PM PST 24
Finished Feb 19 12:36:35 PM PST 24
Peak memory 213596 kb
Host smart-d86d6390-e850-4469-b807-9efbd7260761
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313061154 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.313061154
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1529033979
Short name T476
Test name
Test status
Simulation time 8208118 ps
CPU time 0.76 seconds
Started Feb 19 12:36:24 PM PST 24
Finished Feb 19 12:36:25 PM PST 24
Peak memory 205140 kb
Host smart-090617ff-d6e5-4af9-b940-162c5e96f59c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529033979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1529033979
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3278463366
Short name T479
Test name
Test status
Simulation time 38978860 ps
CPU time 2.66 seconds
Started Feb 19 12:36:30 PM PST 24
Finished Feb 19 12:36:36 PM PST 24
Peak memory 205364 kb
Host smart-b720302a-8459-4ad2-aa6d-14f72dc81cc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278463366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3278463366
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.483876601
Short name T515
Test name
Test status
Simulation time 3875618642 ps
CPU time 32.83 seconds
Started Feb 19 12:36:26 PM PST 24
Finished Feb 19 12:37:00 PM PST 24
Peak memory 218588 kb
Host smart-435e3d50-cf91-49c4-b998-9063533f386f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483876601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.483876601
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1478623188
Short name T457
Test name
Test status
Simulation time 151480071 ps
CPU time 3.56 seconds
Started Feb 19 12:36:27 PM PST 24
Finished Feb 19 12:36:32 PM PST 24
Peak memory 213460 kb
Host smart-c455c53d-a5bf-4d80-83f3-1faf4dee5421
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478623188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1478623188
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.35904509
Short name T143
Test name
Test status
Simulation time 412040598 ps
CPU time 9.37 seconds
Started Feb 19 12:36:25 PM PST 24
Finished Feb 19 12:36:36 PM PST 24
Peak memory 208884 kb
Host smart-922c8dac-bbdb-44f0-938b-ed744a1301f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35904509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.35904509
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2834741347
Short name T139
Test name
Test status
Simulation time 74535411 ps
CPU time 4.83 seconds
Started Feb 19 12:36:27 PM PST 24
Finished Feb 19 12:36:33 PM PST 24
Peak memory 205228 kb
Host smart-5f4526e1-d3e0-49b7-b4e4-41116e4a8fc7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834741347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
834741347
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2006753437
Short name T160
Test name
Test status
Simulation time 120182884 ps
CPU time 1.44 seconds
Started Feb 19 12:36:35 PM PST 24
Finished Feb 19 12:36:43 PM PST 24
Peak memory 205240 kb
Host smart-d9cd6dc3-7f86-4751-aaa3-4cf40cc3efb0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006753437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
006753437
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1315298842
Short name T121
Test name
Test status
Simulation time 244806463 ps
CPU time 1.57 seconds
Started Feb 19 12:36:29 PM PST 24
Finished Feb 19 12:36:32 PM PST 24
Peak memory 213612 kb
Host smart-93d39e66-a60b-494b-b237-8b728e12670c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315298842 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1315298842
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1566273403
Short name T415
Test name
Test status
Simulation time 34261501 ps
CPU time 0.99 seconds
Started Feb 19 12:36:28 PM PST 24
Finished Feb 19 12:36:30 PM PST 24
Peak memory 205048 kb
Host smart-9fe8500b-68fb-45b8-b346-ccf9286bf2f8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566273403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1566273403
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.115883179
Short name T520
Test name
Test status
Simulation time 13779534 ps
CPU time 0.76 seconds
Started Feb 19 12:36:29 PM PST 24
Finished Feb 19 12:36:32 PM PST 24
Peak memory 205124 kb
Host smart-9279c70b-e201-4be0-b635-2b1c4e7ac9c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115883179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.115883179
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.653079746
Short name T498
Test name
Test status
Simulation time 140632546 ps
CPU time 2.54 seconds
Started Feb 19 12:36:29 PM PST 24
Finished Feb 19 12:36:33 PM PST 24
Peak memory 205288 kb
Host smart-ae16ddb4-00c7-4aa1-99ba-1f2b1e4b23ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653079746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.653079746
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4050106876
Short name T496
Test name
Test status
Simulation time 383550314 ps
CPU time 3.69 seconds
Started Feb 19 12:36:27 PM PST 24
Finished Feb 19 12:36:31 PM PST 24
Peak memory 213772 kb
Host smart-291a119e-7a73-448b-a49e-6a57084748a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050106876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.4050106876
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1690672519
Short name T115
Test name
Test status
Simulation time 878569045 ps
CPU time 5.78 seconds
Started Feb 19 12:36:34 PM PST 24
Finished Feb 19 12:36:43 PM PST 24
Peak memory 213736 kb
Host smart-747837bd-62f4-426b-b480-f96adce1d4ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690672519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1690672519
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.181310440
Short name T466
Test name
Test status
Simulation time 47020975 ps
CPU time 1.84 seconds
Started Feb 19 12:36:28 PM PST 24
Finished Feb 19 12:36:30 PM PST 24
Peak memory 213604 kb
Host smart-df54bb83-17a7-4690-b774-a45c0b12816d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181310440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.181310440
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2084417528
Short name T460
Test name
Test status
Simulation time 15629956 ps
CPU time 1.15 seconds
Started Feb 19 12:36:57 PM PST 24
Finished Feb 19 12:36:59 PM PST 24
Peak memory 213552 kb
Host smart-e61bb3fd-3838-4002-8ef6-fee8277397bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084417528 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2084417528
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1170359957
Short name T138
Test name
Test status
Simulation time 16894335 ps
CPU time 1.33 seconds
Started Feb 19 12:36:57 PM PST 24
Finished Feb 19 12:36:59 PM PST 24
Peak memory 205236 kb
Host smart-fe1b2363-f743-48f4-8442-d35963140df3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170359957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1170359957
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.317543784
Short name T416
Test name
Test status
Simulation time 35515625 ps
CPU time 0.71 seconds
Started Feb 19 12:36:55 PM PST 24
Finished Feb 19 12:36:58 PM PST 24
Peak memory 205068 kb
Host smart-78002f79-8f99-4984-ae4e-7a14cf0d8fa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317543784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.317543784
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1910772987
Short name T431
Test name
Test status
Simulation time 349342384 ps
CPU time 3.69 seconds
Started Feb 19 12:36:51 PM PST 24
Finished Feb 19 12:36:56 PM PST 24
Peak memory 205304 kb
Host smart-3aff22bf-af6e-433f-b4c5-e86342b63ba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910772987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1910772987
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.707569823
Short name T158
Test name
Test status
Simulation time 61309229 ps
CPU time 1.23 seconds
Started Feb 19 12:36:53 PM PST 24
Finished Feb 19 12:36:56 PM PST 24
Peak memory 205348 kb
Host smart-ab134d9e-c719-40a2-9007-b77ce6ed4d09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707569823 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.707569823
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1790309459
Short name T456
Test name
Test status
Simulation time 38146401 ps
CPU time 0.69 seconds
Started Feb 19 12:36:56 PM PST 24
Finished Feb 19 12:36:58 PM PST 24
Peak memory 205144 kb
Host smart-6d0ac651-73cc-47dc-ade3-5d56da19ed12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790309459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1790309459
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1291056057
Short name T116
Test name
Test status
Simulation time 93792185 ps
CPU time 3.06 seconds
Started Feb 19 12:36:50 PM PST 24
Finished Feb 19 12:36:55 PM PST 24
Peak memory 213760 kb
Host smart-05ba8eb2-363c-4bfe-929b-04042c2fa8d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291056057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1291056057
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1340333980
Short name T518
Test name
Test status
Simulation time 115338421 ps
CPU time 4.62 seconds
Started Feb 19 12:36:55 PM PST 24
Finished Feb 19 12:37:01 PM PST 24
Peak memory 213752 kb
Host smart-d75a5a1e-563f-4441-b88c-a243102627c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340333980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1340333980
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2767225762
Short name T511
Test name
Test status
Simulation time 73262382 ps
CPU time 2.75 seconds
Started Feb 19 12:36:58 PM PST 24
Finished Feb 19 12:37:02 PM PST 24
Peak memory 213568 kb
Host smart-3a6beb46-b95a-42b2-9561-dfbf7255bd4b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767225762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2767225762
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.476005053
Short name T485
Test name
Test status
Simulation time 71937255 ps
CPU time 1.06 seconds
Started Feb 19 12:36:55 PM PST 24
Finished Feb 19 12:36:58 PM PST 24
Peak memory 205264 kb
Host smart-8e946a88-d184-4bb6-a522-882a79ecb0dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476005053 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.476005053
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.88818268
Short name T134
Test name
Test status
Simulation time 18214310 ps
CPU time 0.91 seconds
Started Feb 19 12:37:02 PM PST 24
Finished Feb 19 12:37:04 PM PST 24
Peak memory 205016 kb
Host smart-e16185de-7a20-48d7-834f-2cf28328a8a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88818268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.88818268
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.126565970
Short name T489
Test name
Test status
Simulation time 10265524 ps
CPU time 0.77 seconds
Started Feb 19 12:36:54 PM PST 24
Finished Feb 19 12:36:57 PM PST 24
Peak memory 205160 kb
Host smart-c8074ef4-c4ef-480f-8fe5-6e1828affdf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126565970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.126565970
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.445939765
Short name T427
Test name
Test status
Simulation time 193018572 ps
CPU time 1.57 seconds
Started Feb 19 12:37:01 PM PST 24
Finished Feb 19 12:37:04 PM PST 24
Peak memory 205212 kb
Host smart-0e5aa5f5-e7bc-434e-a715-7a02c3d20b53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445939765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.445939765
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1339746085
Short name T459
Test name
Test status
Simulation time 225773688 ps
CPU time 4.24 seconds
Started Feb 19 12:36:54 PM PST 24
Finished Feb 19 12:37:00 PM PST 24
Peak memory 213612 kb
Host smart-2901e94d-82c5-4eee-862d-66d36dbda34c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339746085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1339746085
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1953495457
Short name T531
Test name
Test status
Simulation time 359011915 ps
CPU time 5.16 seconds
Started Feb 19 12:36:55 PM PST 24
Finished Feb 19 12:37:02 PM PST 24
Peak memory 213748 kb
Host smart-9bad9cc8-f20e-4fc3-9d3e-894b881dce64
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953495457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1953495457
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2054144546
Short name T482
Test name
Test status
Simulation time 88657784 ps
CPU time 2.93 seconds
Started Feb 19 12:36:54 PM PST 24
Finished Feb 19 12:36:59 PM PST 24
Peak memory 213520 kb
Host smart-6494c4c4-ee58-4cab-bf76-e6076739aae9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054144546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2054144546
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1804819573
Short name T451
Test name
Test status
Simulation time 67294801 ps
CPU time 1.51 seconds
Started Feb 19 12:36:54 PM PST 24
Finished Feb 19 12:36:57 PM PST 24
Peak memory 217136 kb
Host smart-ec7b2d21-2c69-4228-8c7a-ffd81da7e34b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804819573 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1804819573
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3773450639
Short name T428
Test name
Test status
Simulation time 53610416 ps
CPU time 1.33 seconds
Started Feb 19 12:36:53 PM PST 24
Finished Feb 19 12:36:57 PM PST 24
Peak memory 205228 kb
Host smart-f3818bdc-1b27-4e6b-a04a-9c27a0ae22c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773450639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3773450639
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.4140060242
Short name T419
Test name
Test status
Simulation time 130009642 ps
CPU time 0.7 seconds
Started Feb 19 12:36:53 PM PST 24
Finished Feb 19 12:36:55 PM PST 24
Peak memory 205160 kb
Host smart-ce783308-cc05-4ef9-a7a5-6f4a010933fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140060242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.4140060242
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.468665566
Short name T458
Test name
Test status
Simulation time 67281669 ps
CPU time 2.02 seconds
Started Feb 19 12:36:53 PM PST 24
Finished Feb 19 12:36:56 PM PST 24
Peak memory 205240 kb
Host smart-ef3785fc-aa5b-42a9-a469-e11c98eb3333
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468665566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.468665566
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2137728887
Short name T155
Test name
Test status
Simulation time 320410896 ps
CPU time 4.88 seconds
Started Feb 19 12:37:02 PM PST 24
Finished Feb 19 12:37:08 PM PST 24
Peak memory 213584 kb
Host smart-06868b82-5872-4cc2-9331-46b3bd22af7c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137728887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2137728887
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3682078529
Short name T110
Test name
Test status
Simulation time 364442116 ps
CPU time 6.85 seconds
Started Feb 19 12:37:02 PM PST 24
Finished Feb 19 12:37:10 PM PST 24
Peak memory 213596 kb
Host smart-a88e6881-f11b-438d-adde-44d861d11b6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682078529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3682078529
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1065871079
Short name T487
Test name
Test status
Simulation time 129531002 ps
CPU time 3.35 seconds
Started Feb 19 12:37:02 PM PST 24
Finished Feb 19 12:37:07 PM PST 24
Peak memory 213580 kb
Host smart-a824450a-607c-46bd-b556-bb0844ab8c58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065871079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1065871079
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3279436377
Short name T157
Test name
Test status
Simulation time 73833525 ps
CPU time 1.05 seconds
Started Feb 19 12:37:00 PM PST 24
Finished Feb 19 12:37:02 PM PST 24
Peak memory 205244 kb
Host smart-183bd302-857a-4633-8a39-b197fc25d48c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279436377 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3279436377
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2856088698
Short name T453
Test name
Test status
Simulation time 23757026 ps
CPU time 1.17 seconds
Started Feb 19 12:37:09 PM PST 24
Finished Feb 19 12:37:15 PM PST 24
Peak memory 205128 kb
Host smart-a7b7f7ca-a706-4b51-a8e7-bc6c6fccdc6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856088698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2856088698
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.338539900
Short name T536
Test name
Test status
Simulation time 12471310 ps
CPU time 0.74 seconds
Started Feb 19 12:37:04 PM PST 24
Finished Feb 19 12:37:07 PM PST 24
Peak memory 205068 kb
Host smart-8f74ebb9-1a0e-4c4c-8bbf-d3e641cf2544
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338539900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.338539900
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1043226041
Short name T481
Test name
Test status
Simulation time 92667535 ps
CPU time 1.42 seconds
Started Feb 19 12:37:07 PM PST 24
Finished Feb 19 12:37:12 PM PST 24
Peak memory 205292 kb
Host smart-558bf7a1-e0de-4153-894b-ec31b9f24889
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043226041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1043226041
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3075406709
Short name T117
Test name
Test status
Simulation time 804833135 ps
CPU time 5.68 seconds
Started Feb 19 12:36:56 PM PST 24
Finished Feb 19 12:37:03 PM PST 24
Peak memory 213708 kb
Host smart-6c267e2b-e716-406e-bdf0-b9fb90502f59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075406709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3075406709
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3122366030
Short name T470
Test name
Test status
Simulation time 412568124 ps
CPU time 5.7 seconds
Started Feb 19 12:36:56 PM PST 24
Finished Feb 19 12:37:03 PM PST 24
Peak memory 221916 kb
Host smart-be2443e1-45c9-4c3f-85e3-301d36032ec7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122366030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3122366030
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2098742315
Short name T433
Test name
Test status
Simulation time 563766027 ps
CPU time 3.27 seconds
Started Feb 19 12:36:53 PM PST 24
Finished Feb 19 12:36:58 PM PST 24
Peak memory 213496 kb
Host smart-967446b9-872a-4adc-b3a3-6b6f1c1e717c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098742315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2098742315
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1147647015
Short name T534
Test name
Test status
Simulation time 147534166 ps
CPU time 1.74 seconds
Started Feb 19 12:36:59 PM PST 24
Finished Feb 19 12:37:02 PM PST 24
Peak memory 213620 kb
Host smart-63b61512-80bb-4daf-b9e0-f329ae97cce2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147647015 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1147647015
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1994779715
Short name T509
Test name
Test status
Simulation time 58138773 ps
CPU time 0.88 seconds
Started Feb 19 12:37:01 PM PST 24
Finished Feb 19 12:37:04 PM PST 24
Peak memory 205040 kb
Host smart-3904763a-1550-4cb8-a7c2-5e1a1fa9afbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994779715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1994779715
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.679933656
Short name T471
Test name
Test status
Simulation time 43159347 ps
CPU time 0.87 seconds
Started Feb 19 12:37:01 PM PST 24
Finished Feb 19 12:37:04 PM PST 24
Peak memory 205148 kb
Host smart-86d46c8e-5bd1-436f-9355-248a9f7e811c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679933656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.679933656
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3265851437
Short name T436
Test name
Test status
Simulation time 192895436 ps
CPU time 2.07 seconds
Started Feb 19 12:37:04 PM PST 24
Finished Feb 19 12:37:09 PM PST 24
Peak memory 205288 kb
Host smart-9581df52-7cd1-4b3d-a04f-93834afb520e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265851437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3265851437
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2974081578
Short name T454
Test name
Test status
Simulation time 355676461 ps
CPU time 7.37 seconds
Started Feb 19 12:37:01 PM PST 24
Finished Feb 19 12:37:10 PM PST 24
Peak memory 213840 kb
Host smart-b0ae0538-eb56-484c-aec9-30d6ac7b0c0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974081578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2974081578
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.4173646826
Short name T528
Test name
Test status
Simulation time 104982908 ps
CPU time 5.61 seconds
Started Feb 19 12:37:07 PM PST 24
Finished Feb 19 12:37:16 PM PST 24
Peak memory 213724 kb
Host smart-a3c6be6d-d4b8-43cf-b2e0-551c949a5822
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173646826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.4173646826
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.826477850
Short name T120
Test name
Test status
Simulation time 48366133 ps
CPU time 1.55 seconds
Started Feb 19 12:37:01 PM PST 24
Finished Feb 19 12:37:04 PM PST 24
Peak memory 213480 kb
Host smart-de66c7cf-a61a-4585-819b-6afe17299365
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826477850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.826477850
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.845269972
Short name T162
Test name
Test status
Simulation time 45595880 ps
CPU time 1.17 seconds
Started Feb 19 12:37:02 PM PST 24
Finished Feb 19 12:37:06 PM PST 24
Peak memory 213648 kb
Host smart-2980c407-2ead-4406-82cc-40d892463152
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845269972 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.845269972
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.688111818
Short name T439
Test name
Test status
Simulation time 80084780 ps
CPU time 1.18 seconds
Started Feb 19 12:37:10 PM PST 24
Finished Feb 19 12:37:15 PM PST 24
Peak memory 205224 kb
Host smart-e664c004-09ca-49d5-9ad3-a0b1348c4483
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688111818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.688111818
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1956025137
Short name T371
Test name
Test status
Simulation time 28583302 ps
CPU time 0.74 seconds
Started Feb 19 12:37:01 PM PST 24
Finished Feb 19 12:37:03 PM PST 24
Peak memory 205028 kb
Host smart-579cd560-1153-46f9-abc4-ed1773d9b9f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956025137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1956025137
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.705036924
Short name T438
Test name
Test status
Simulation time 209204443 ps
CPU time 2.26 seconds
Started Feb 19 12:37:00 PM PST 24
Finished Feb 19 12:37:04 PM PST 24
Peak memory 205076 kb
Host smart-8724bc67-9a90-4688-b468-f7d26eff74e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705036924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.705036924
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2184646728
Short name T112
Test name
Test status
Simulation time 2430169800 ps
CPU time 3.78 seconds
Started Feb 19 12:37:02 PM PST 24
Finished Feb 19 12:37:08 PM PST 24
Peak memory 221944 kb
Host smart-6f934406-32d1-4b41-9aa1-796452657772
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184646728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2184646728
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3657176582
Short name T540
Test name
Test status
Simulation time 963832058 ps
CPU time 8.54 seconds
Started Feb 19 12:37:02 PM PST 24
Finished Feb 19 12:37:12 PM PST 24
Peak memory 219920 kb
Host smart-fcc2b214-746e-4c88-9cac-c1c3bc1048bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657176582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3657176582
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2158158201
Short name T535
Test name
Test status
Simulation time 162609052 ps
CPU time 2.43 seconds
Started Feb 19 12:37:00 PM PST 24
Finished Feb 19 12:37:03 PM PST 24
Peak memory 213576 kb
Host smart-9e8bad56-3878-46fb-914d-2024e14f0bed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158158201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2158158201
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.875252190
Short name T447
Test name
Test status
Simulation time 16178757 ps
CPU time 1.1 seconds
Started Feb 19 12:37:07 PM PST 24
Finished Feb 19 12:37:12 PM PST 24
Peak memory 205356 kb
Host smart-848e5a9a-16e4-4488-8c22-41efdd70019b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875252190 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.875252190
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2617659450
Short name T118
Test name
Test status
Simulation time 40638536 ps
CPU time 0.94 seconds
Started Feb 19 12:37:08 PM PST 24
Finished Feb 19 12:37:14 PM PST 24
Peak memory 205096 kb
Host smart-726555e8-026a-408d-b480-313339928bfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617659450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2617659450
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3551334121
Short name T505
Test name
Test status
Simulation time 27924434 ps
CPU time 0.73 seconds
Started Feb 19 12:37:06 PM PST 24
Finished Feb 19 12:37:11 PM PST 24
Peak memory 205132 kb
Host smart-9c5431ae-b7cf-494c-abaf-0247d29b3861
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551334121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3551334121
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3321234839
Short name T432
Test name
Test status
Simulation time 157133002 ps
CPU time 2.61 seconds
Started Feb 19 12:37:09 PM PST 24
Finished Feb 19 12:37:15 PM PST 24
Peak memory 205276 kb
Host smart-a96b7822-0b8c-4ddf-a43f-73b167fc9340
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321234839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3321234839
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2507250119
Short name T532
Test name
Test status
Simulation time 354951178 ps
CPU time 3.31 seconds
Started Feb 19 12:37:06 PM PST 24
Finished Feb 19 12:37:14 PM PST 24
Peak memory 221876 kb
Host smart-f190c266-2576-4fd8-a97c-5d9bf08d8ad7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507250119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2507250119
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2857576438
Short name T444
Test name
Test status
Simulation time 408847313 ps
CPU time 2.19 seconds
Started Feb 19 12:37:04 PM PST 24
Finished Feb 19 12:37:09 PM PST 24
Peak memory 213460 kb
Host smart-60d99637-4657-468a-a58e-f48290bba800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857576438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2857576438
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3910140296
Short name T154
Test name
Test status
Simulation time 510144930 ps
CPU time 4.42 seconds
Started Feb 19 12:37:04 PM PST 24
Finished Feb 19 12:37:11 PM PST 24
Peak memory 208456 kb
Host smart-30f0c5ff-2922-44fe-aa8e-7e94ae43f5fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910140296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3910140296
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3505804634
Short name T521
Test name
Test status
Simulation time 38676506 ps
CPU time 1.36 seconds
Started Feb 19 12:37:06 PM PST 24
Finished Feb 19 12:37:12 PM PST 24
Peak memory 213344 kb
Host smart-f1a18967-98e0-4175-9d2a-903882206a64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505804634 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3505804634
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2655297043
Short name T137
Test name
Test status
Simulation time 14947549 ps
CPU time 1.07 seconds
Started Feb 19 12:37:06 PM PST 24
Finished Feb 19 12:37:11 PM PST 24
Peak memory 205176 kb
Host smart-4fe9a858-ea02-4f82-9031-b5d58b881955
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655297043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2655297043
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.245395178
Short name T495
Test name
Test status
Simulation time 10942543 ps
CPU time 0.8 seconds
Started Feb 19 12:37:06 PM PST 24
Finished Feb 19 12:37:11 PM PST 24
Peak memory 205068 kb
Host smart-fb38ccfd-0172-402e-80f7-73c571cfbeed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245395178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.245395178
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2340730310
Short name T421
Test name
Test status
Simulation time 393794208 ps
CPU time 3.68 seconds
Started Feb 19 12:37:07 PM PST 24
Finished Feb 19 12:37:15 PM PST 24
Peak memory 205352 kb
Host smart-3c40de3d-25fc-4a81-a5fa-f181c0f80e57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340730310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2340730310
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3706239200
Short name T483
Test name
Test status
Simulation time 379859530 ps
CPU time 2.77 seconds
Started Feb 19 12:37:10 PM PST 24
Finished Feb 19 12:37:16 PM PST 24
Peak memory 218208 kb
Host smart-4382a4d5-2b5b-47a9-9bdc-a2fd0ee845df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706239200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3706239200
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2007909932
Short name T502
Test name
Test status
Simulation time 711889433 ps
CPU time 9.41 seconds
Started Feb 19 12:37:06 PM PST 24
Finished Feb 19 12:37:20 PM PST 24
Peak memory 219892 kb
Host smart-3c3059bc-19a0-4d91-98dc-234737d58146
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007909932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2007909932
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1906831671
Short name T449
Test name
Test status
Simulation time 21268339 ps
CPU time 1.71 seconds
Started Feb 19 12:37:07 PM PST 24
Finished Feb 19 12:37:13 PM PST 24
Peak memory 214092 kb
Host smart-7ead3be7-f0fc-4cbe-89e9-09daa1037a14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906831671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1906831671
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.4076660860
Short name T429
Test name
Test status
Simulation time 30679235 ps
CPU time 1.18 seconds
Started Feb 19 12:37:11 PM PST 24
Finished Feb 19 12:37:15 PM PST 24
Peak memory 213328 kb
Host smart-acf0613e-2485-49c2-99fa-5c70c080a6f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076660860 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.4076660860
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2836427340
Short name T443
Test name
Test status
Simulation time 14761239 ps
CPU time 1.13 seconds
Started Feb 19 12:37:06 PM PST 24
Finished Feb 19 12:37:12 PM PST 24
Peak memory 204980 kb
Host smart-b32daf76-2bca-45a2-a775-ae3c146edcba
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836427340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2836427340
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3327200708
Short name T539
Test name
Test status
Simulation time 10019676 ps
CPU time 0.81 seconds
Started Feb 19 12:37:15 PM PST 24
Finished Feb 19 12:37:18 PM PST 24
Peak memory 205092 kb
Host smart-baedba65-5b05-4000-95d3-c252c3b281a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327200708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3327200708
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3953694870
Short name T140
Test name
Test status
Simulation time 35252990 ps
CPU time 1.84 seconds
Started Feb 19 12:37:09 PM PST 24
Finished Feb 19 12:37:15 PM PST 24
Peak memory 205296 kb
Host smart-61709168-ded9-4e06-87a1-27df08cf2ac8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953694870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3953694870
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3382793348
Short name T490
Test name
Test status
Simulation time 250361766 ps
CPU time 5.13 seconds
Started Feb 19 12:37:08 PM PST 24
Finished Feb 19 12:37:18 PM PST 24
Peak memory 213764 kb
Host smart-3e4cd407-e918-4ae3-8c68-e6131245384f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382793348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3382793348
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.695482662
Short name T544
Test name
Test status
Simulation time 292855436 ps
CPU time 11.74 seconds
Started Feb 19 12:37:08 PM PST 24
Finished Feb 19 12:37:25 PM PST 24
Peak memory 213720 kb
Host smart-146df946-4fc0-4b64-b752-da19acb677bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695482662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
keymgr_shadow_reg_errors_with_csr_rw.695482662
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4216283424
Short name T124
Test name
Test status
Simulation time 153010803 ps
CPU time 2.88 seconds
Started Feb 19 12:37:06 PM PST 24
Finished Feb 19 12:37:13 PM PST 24
Peak memory 215544 kb
Host smart-bc1572d9-885d-4fc0-b9d3-f194fe755e27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216283424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.4216283424
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.587215287
Short name T533
Test name
Test status
Simulation time 2411432852 ps
CPU time 13.45 seconds
Started Feb 19 12:36:32 PM PST 24
Finished Feb 19 12:36:48 PM PST 24
Peak memory 205272 kb
Host smart-786fd2bb-ba84-4592-b0ba-37a3c7569c43
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587215287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.587215287
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.30953226
Short name T164
Test name
Test status
Simulation time 77931618 ps
CPU time 2.11 seconds
Started Feb 19 12:36:29 PM PST 24
Finished Feb 19 12:36:34 PM PST 24
Peak memory 205204 kb
Host smart-16fbbcbb-5967-43dc-a7d6-bccef06d351d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30953226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.30953226
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.12772682
Short name T541
Test name
Test status
Simulation time 45399721 ps
CPU time 0.96 seconds
Started Feb 19 12:36:32 PM PST 24
Finished Feb 19 12:36:36 PM PST 24
Peak memory 205284 kb
Host smart-e8d1a8e5-ce84-4af3-bee7-5f1dbd566246
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12772682 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.12772682
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2605066337
Short name T455
Test name
Test status
Simulation time 8175518 ps
CPU time 0.71 seconds
Started Feb 19 12:36:30 PM PST 24
Finished Feb 19 12:36:34 PM PST 24
Peak memory 205128 kb
Host smart-635a12b8-4fed-4a8b-b359-e52e512befa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605066337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2605066337
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2715681420
Short name T507
Test name
Test status
Simulation time 2355853840 ps
CPU time 15.74 seconds
Started Feb 19 12:36:29 PM PST 24
Finished Feb 19 12:36:48 PM PST 24
Peak memory 214360 kb
Host smart-65005c10-503b-4b0a-84a0-d3b619de001e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715681420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2715681420
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2999325289
Short name T527
Test name
Test status
Simulation time 205545272 ps
CPU time 10.39 seconds
Started Feb 19 12:36:27 PM PST 24
Finished Feb 19 12:36:38 PM PST 24
Peak memory 213696 kb
Host smart-9fde15be-7f32-4920-9192-62ab147c8b9d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999325289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2999325289
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2318136683
Short name T106
Test name
Test status
Simulation time 164258024 ps
CPU time 2.87 seconds
Started Feb 19 12:36:30 PM PST 24
Finished Feb 19 12:36:36 PM PST 24
Peak memory 213468 kb
Host smart-4116f90f-e0a2-46ed-aef8-cec641b39aec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318136683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2318136683
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2315795158
Short name T522
Test name
Test status
Simulation time 420366108 ps
CPU time 3.57 seconds
Started Feb 19 12:36:27 PM PST 24
Finished Feb 19 12:36:31 PM PST 24
Peak memory 213444 kb
Host smart-9065d310-d034-4cd7-916f-b1f9f2072e9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315795158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2315795158
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2650484167
Short name T462
Test name
Test status
Simulation time 32328143 ps
CPU time 0.73 seconds
Started Feb 19 12:37:13 PM PST 24
Finished Feb 19 12:37:16 PM PST 24
Peak memory 205368 kb
Host smart-8158596d-4f8e-4d04-9734-2c03e58a2a1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650484167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2650484167
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1948186572
Short name T473
Test name
Test status
Simulation time 10143774 ps
CPU time 0.73 seconds
Started Feb 19 12:37:12 PM PST 24
Finished Feb 19 12:37:16 PM PST 24
Peak memory 205140 kb
Host smart-ec4e86d0-8851-4f4e-bbaa-b50fb2f25175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948186572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1948186572
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3337216560
Short name T434
Test name
Test status
Simulation time 92819736 ps
CPU time 0.74 seconds
Started Feb 19 12:37:08 PM PST 24
Finished Feb 19 12:37:13 PM PST 24
Peak memory 205140 kb
Host smart-fbedbe94-6b40-44ef-80ee-1380077d2e46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337216560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3337216560
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1537250707
Short name T546
Test name
Test status
Simulation time 6859006 ps
CPU time 0.73 seconds
Started Feb 19 12:37:13 PM PST 24
Finished Feb 19 12:37:16 PM PST 24
Peak memory 205088 kb
Host smart-c0896e56-8a51-4210-a5aa-3456329643e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537250707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1537250707
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2493998879
Short name T422
Test name
Test status
Simulation time 11115521 ps
CPU time 0.73 seconds
Started Feb 19 12:37:09 PM PST 24
Finished Feb 19 12:37:14 PM PST 24
Peak memory 205140 kb
Host smart-28039bea-58a5-45cd-8a7f-a2b5168f6418
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493998879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2493998879
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1414821313
Short name T448
Test name
Test status
Simulation time 120124890 ps
CPU time 0.86 seconds
Started Feb 19 12:37:09 PM PST 24
Finished Feb 19 12:37:14 PM PST 24
Peak memory 205072 kb
Host smart-b8be1dea-34c8-4c86-a612-c6f4beec55f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414821313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1414821313
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2374219653
Short name T437
Test name
Test status
Simulation time 37745829 ps
CPU time 0.73 seconds
Started Feb 19 12:37:08 PM PST 24
Finished Feb 19 12:37:12 PM PST 24
Peak memory 205056 kb
Host smart-4c42b91a-bc3c-47c4-a4d7-9c1654648353
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374219653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2374219653
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2100176074
Short name T542
Test name
Test status
Simulation time 26105785 ps
CPU time 0.77 seconds
Started Feb 19 12:37:11 PM PST 24
Finished Feb 19 12:37:15 PM PST 24
Peak memory 205012 kb
Host smart-1b8553ae-d2b0-4473-a624-7a45c1d5bc9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100176074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2100176074
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3116947510
Short name T525
Test name
Test status
Simulation time 20865069 ps
CPU time 0.71 seconds
Started Feb 19 12:37:09 PM PST 24
Finished Feb 19 12:37:14 PM PST 24
Peak memory 205124 kb
Host smart-33502678-80cb-45b7-a98e-884c7cbb5ad1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116947510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3116947510
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.244811340
Short name T529
Test name
Test status
Simulation time 22081110 ps
CPU time 0.68 seconds
Started Feb 19 12:37:08 PM PST 24
Finished Feb 19 12:37:13 PM PST 24
Peak memory 205032 kb
Host smart-4733434c-9356-4b48-9d3f-88eada0eb8ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244811340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.244811340
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2044397227
Short name T465
Test name
Test status
Simulation time 1054035927 ps
CPU time 4.84 seconds
Started Feb 19 12:36:32 PM PST 24
Finished Feb 19 12:36:40 PM PST 24
Peak memory 204404 kb
Host smart-d08f263e-5f21-43f3-8288-daefbfca6d08
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044397227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
044397227
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1034578684
Short name T514
Test name
Test status
Simulation time 534578646 ps
CPU time 11.53 seconds
Started Feb 19 12:36:43 PM PST 24
Finished Feb 19 12:36:58 PM PST 24
Peak memory 205080 kb
Host smart-1f5dd32d-6ed3-40c3-b6df-cef5ef791231
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034578684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
034578684
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1978996123
Short name T500
Test name
Test status
Simulation time 36455126 ps
CPU time 1.46 seconds
Started Feb 19 12:36:30 PM PST 24
Finished Feb 19 12:36:34 PM PST 24
Peak memory 205292 kb
Host smart-eb83bfda-3ff6-4c19-bb8a-0a994e5354a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978996123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
978996123
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.392341430
Short name T468
Test name
Test status
Simulation time 43875566 ps
CPU time 1.14 seconds
Started Feb 19 12:36:43 PM PST 24
Finished Feb 19 12:36:48 PM PST 24
Peak memory 205316 kb
Host smart-b284a8b9-6a8c-41db-aed9-2903da1cc943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392341430 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.392341430
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.814177940
Short name T493
Test name
Test status
Simulation time 81567349 ps
CPU time 1.13 seconds
Started Feb 19 12:36:39 PM PST 24
Finished Feb 19 12:36:45 PM PST 24
Peak memory 205140 kb
Host smart-1ee9b3b5-a0e0-45e3-9bc7-e0ef6f7f4ab4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814177940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.814177940
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3367212563
Short name T440
Test name
Test status
Simulation time 13480713 ps
CPU time 0.86 seconds
Started Feb 19 12:36:36 PM PST 24
Finished Feb 19 12:36:44 PM PST 24
Peak memory 205096 kb
Host smart-509dd18b-efdd-4c34-b9d2-8d321115d622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367212563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3367212563
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3351084496
Short name T132
Test name
Test status
Simulation time 183940153 ps
CPU time 1.61 seconds
Started Feb 19 12:36:32 PM PST 24
Finished Feb 19 12:36:37 PM PST 24
Peak memory 204740 kb
Host smart-34de52c1-0b1a-4354-9b5c-8b0f756229c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351084496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3351084496
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2193269862
Short name T109
Test name
Test status
Simulation time 198960691 ps
CPU time 2.64 seconds
Started Feb 19 12:36:39 PM PST 24
Finished Feb 19 12:36:47 PM PST 24
Peak memory 213792 kb
Host smart-408d5a97-a2c8-4358-91c5-97d5d904604f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193269862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2193269862
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1357242140
Short name T123
Test name
Test status
Simulation time 674523837 ps
CPU time 2.92 seconds
Started Feb 19 12:36:36 PM PST 24
Finished Feb 19 12:36:46 PM PST 24
Peak memory 213524 kb
Host smart-d8259245-a279-4293-b4e4-1324149b034e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357242140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1357242140
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2512642111
Short name T506
Test name
Test status
Simulation time 577989447 ps
CPU time 5.94 seconds
Started Feb 19 12:36:43 PM PST 24
Finished Feb 19 12:36:52 PM PST 24
Peak memory 208904 kb
Host smart-8a19f15c-2601-4adc-828c-a3c3f068bb03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512642111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2512642111
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3432963581
Short name T504
Test name
Test status
Simulation time 15987669 ps
CPU time 0.72 seconds
Started Feb 19 12:37:11 PM PST 24
Finished Feb 19 12:37:15 PM PST 24
Peak memory 205052 kb
Host smart-1bc2153a-95a9-46c1-bc72-9df8a408726c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432963581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3432963581
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2818442153
Short name T135
Test name
Test status
Simulation time 34012407 ps
CPU time 0.83 seconds
Started Feb 19 12:37:10 PM PST 24
Finished Feb 19 12:37:15 PM PST 24
Peak memory 205100 kb
Host smart-7b4fb34e-ebcb-49d3-a502-fc233e435f47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818442153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2818442153
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2343858848
Short name T420
Test name
Test status
Simulation time 84000122 ps
CPU time 0.73 seconds
Started Feb 19 12:37:14 PM PST 24
Finished Feb 19 12:37:18 PM PST 24
Peak memory 205116 kb
Host smart-575ef7c5-ba8f-4176-8a4d-1fa14614ba84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343858848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2343858848
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1505897784
Short name T501
Test name
Test status
Simulation time 38515615 ps
CPU time 0.69 seconds
Started Feb 19 12:37:12 PM PST 24
Finished Feb 19 12:37:16 PM PST 24
Peak memory 205088 kb
Host smart-2a12b69e-244a-4101-ad98-aa99c8596a35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505897784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1505897784
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1196724543
Short name T526
Test name
Test status
Simulation time 19497566 ps
CPU time 1.03 seconds
Started Feb 19 12:37:14 PM PST 24
Finished Feb 19 12:37:17 PM PST 24
Peak memory 205100 kb
Host smart-ef26ea94-113f-4053-a799-864d481c4ef2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196724543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1196724543
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.4265694183
Short name T497
Test name
Test status
Simulation time 19208523 ps
CPU time 0.76 seconds
Started Feb 19 12:37:14 PM PST 24
Finished Feb 19 12:37:17 PM PST 24
Peak memory 205140 kb
Host smart-0a6d166b-71b3-4000-ab4d-e577e54f823e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265694183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.4265694183
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1174188303
Short name T423
Test name
Test status
Simulation time 9884267 ps
CPU time 0.83 seconds
Started Feb 19 12:37:09 PM PST 24
Finished Feb 19 12:37:14 PM PST 24
Peak memory 205080 kb
Host smart-43384c61-30d7-4657-a884-fd11c9da50d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174188303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1174188303
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.496689296
Short name T475
Test name
Test status
Simulation time 25645217 ps
CPU time 0.71 seconds
Started Feb 19 12:37:11 PM PST 24
Finished Feb 19 12:37:15 PM PST 24
Peak memory 204956 kb
Host smart-8fb4268a-aaf9-49ad-bf87-6c9363435c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496689296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.496689296
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2157655214
Short name T435
Test name
Test status
Simulation time 16679486 ps
CPU time 0.66 seconds
Started Feb 19 12:37:09 PM PST 24
Finished Feb 19 12:37:14 PM PST 24
Peak memory 205144 kb
Host smart-939428d6-f7da-42c9-a9a4-b4ae91693100
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157655214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2157655214
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1997028489
Short name T136
Test name
Test status
Simulation time 26398564 ps
CPU time 0.73 seconds
Started Feb 19 12:37:13 PM PST 24
Finished Feb 19 12:37:17 PM PST 24
Peak memory 205152 kb
Host smart-62535fae-fe0e-4d65-8ea1-6e2530165265
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997028489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1997028489
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2382025646
Short name T494
Test name
Test status
Simulation time 532708773 ps
CPU time 6.92 seconds
Started Feb 19 12:36:42 PM PST 24
Finished Feb 19 12:36:52 PM PST 24
Peak memory 205116 kb
Host smart-c729d4bb-0d99-4dba-be28-9e2a77ed7432
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382025646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
382025646
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3029856959
Short name T472
Test name
Test status
Simulation time 67013353 ps
CPU time 1.2 seconds
Started Feb 19 12:36:37 PM PST 24
Finished Feb 19 12:36:44 PM PST 24
Peak memory 205224 kb
Host smart-7c47ce97-d15e-4e7d-9e2a-c6eb4741cb5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029856959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
029856959
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2855892523
Short name T537
Test name
Test status
Simulation time 164348324 ps
CPU time 1.6 seconds
Started Feb 19 12:36:37 PM PST 24
Finished Feb 19 12:36:45 PM PST 24
Peak memory 213580 kb
Host smart-acb7a82b-0265-417a-af55-cdc3727945b8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855892523 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2855892523
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3720355736
Short name T486
Test name
Test status
Simulation time 35455452 ps
CPU time 0.79 seconds
Started Feb 19 12:36:38 PM PST 24
Finished Feb 19 12:36:44 PM PST 24
Peak memory 205164 kb
Host smart-f91dbde3-25dd-4b1f-b3f0-8e21cf3749ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720355736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3720355736
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2512601150
Short name T452
Test name
Test status
Simulation time 44348616 ps
CPU time 1.34 seconds
Started Feb 19 12:36:36 PM PST 24
Finished Feb 19 12:36:44 PM PST 24
Peak memory 205100 kb
Host smart-9d8f89fb-fd6c-46ee-b16a-03e2031f2f98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512601150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2512601150
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1088733942
Short name T513
Test name
Test status
Simulation time 113417713 ps
CPU time 2.3 seconds
Started Feb 19 12:36:39 PM PST 24
Finished Feb 19 12:36:46 PM PST 24
Peak memory 213716 kb
Host smart-2d1dcf81-7fad-40cd-84dc-aead7ffb889b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088733942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1088733942
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.116883163
Short name T469
Test name
Test status
Simulation time 563109229 ps
CPU time 2.64 seconds
Started Feb 19 12:36:32 PM PST 24
Finished Feb 19 12:36:37 PM PST 24
Peak memory 213456 kb
Host smart-4cdba296-3048-4fd5-94a3-a6bd39114d89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116883163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.116883163
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2173920560
Short name T370
Test name
Test status
Simulation time 416389356 ps
CPU time 5.07 seconds
Started Feb 19 12:36:36 PM PST 24
Finished Feb 19 12:36:48 PM PST 24
Peak memory 213452 kb
Host smart-80a5f660-3399-4af0-9538-4d9e0dbc16cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173920560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2173920560
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3221982393
Short name T510
Test name
Test status
Simulation time 77543178 ps
CPU time 0.7 seconds
Started Feb 19 12:37:13 PM PST 24
Finished Feb 19 12:37:17 PM PST 24
Peak memory 205128 kb
Host smart-50fe01f8-1d24-4fe3-9ea7-d82a223afa7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221982393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3221982393
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3075523447
Short name T523
Test name
Test status
Simulation time 14518798 ps
CPU time 0.76 seconds
Started Feb 19 12:37:17 PM PST 24
Finished Feb 19 12:37:20 PM PST 24
Peak memory 205092 kb
Host smart-57c42e26-e26c-4f2d-8995-76bf673d60f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075523447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3075523447
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1277123325
Short name T484
Test name
Test status
Simulation time 15848029 ps
CPU time 0.81 seconds
Started Feb 19 12:37:14 PM PST 24
Finished Feb 19 12:37:18 PM PST 24
Peak memory 205072 kb
Host smart-f1f9b79f-573a-4ce6-8a3f-40e4fb5ba892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277123325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1277123325
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2482152347
Short name T464
Test name
Test status
Simulation time 47436656 ps
CPU time 0.79 seconds
Started Feb 19 12:37:18 PM PST 24
Finished Feb 19 12:37:22 PM PST 24
Peak memory 205072 kb
Host smart-8c234d7a-993d-45b5-87a7-c81caad1ddc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482152347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2482152347
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3724476936
Short name T426
Test name
Test status
Simulation time 58298804 ps
CPU time 0.7 seconds
Started Feb 19 12:37:15 PM PST 24
Finished Feb 19 12:37:18 PM PST 24
Peak memory 205160 kb
Host smart-292064fc-eaf3-40b1-9444-777e92f47054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724476936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3724476936
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2684033218
Short name T492
Test name
Test status
Simulation time 12483414 ps
CPU time 0.87 seconds
Started Feb 19 12:37:18 PM PST 24
Finished Feb 19 12:37:22 PM PST 24
Peak memory 205140 kb
Host smart-c471e202-0f5f-4527-85a5-f7669dc1af7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684033218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2684033218
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2355053513
Short name T519
Test name
Test status
Simulation time 11943086 ps
CPU time 0.7 seconds
Started Feb 19 12:37:18 PM PST 24
Finished Feb 19 12:37:22 PM PST 24
Peak memory 205140 kb
Host smart-99ca45d4-2572-4cb0-8d80-0de3fa874978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355053513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2355053513
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3759716187
Short name T424
Test name
Test status
Simulation time 28471026 ps
CPU time 0.82 seconds
Started Feb 19 12:37:14 PM PST 24
Finished Feb 19 12:37:18 PM PST 24
Peak memory 205116 kb
Host smart-3bf0144e-91ee-428b-9472-38f1a098d5b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759716187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3759716187
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.4124206421
Short name T414
Test name
Test status
Simulation time 15920559 ps
CPU time 0.74 seconds
Started Feb 19 12:37:16 PM PST 24
Finished Feb 19 12:37:19 PM PST 24
Peak memory 204960 kb
Host smart-e54146c0-4942-457f-9a59-8e2f86d088a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124206421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.4124206421
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.880264180
Short name T417
Test name
Test status
Simulation time 11817987 ps
CPU time 0.78 seconds
Started Feb 19 12:37:17 PM PST 24
Finished Feb 19 12:37:21 PM PST 24
Peak memory 205124 kb
Host smart-f5f1bdb1-7891-4522-a6ab-7dd649283607
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880264180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.880264180
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1302244309
Short name T159
Test name
Test status
Simulation time 66334381 ps
CPU time 0.99 seconds
Started Feb 19 12:36:47 PM PST 24
Finished Feb 19 12:36:50 PM PST 24
Peak memory 205188 kb
Host smart-cb52d3f1-6c8f-4e8d-8d56-c45b6d4d76d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302244309 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1302244309
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1198540132
Short name T491
Test name
Test status
Simulation time 12159140 ps
CPU time 0.87 seconds
Started Feb 19 12:36:37 PM PST 24
Finished Feb 19 12:36:44 PM PST 24
Peak memory 205056 kb
Host smart-1b506952-5b46-45ff-aa65-c3cf59c55614
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198540132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1198540132
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2547040533
Short name T477
Test name
Test status
Simulation time 350490857 ps
CPU time 3.34 seconds
Started Feb 19 12:36:37 PM PST 24
Finished Feb 19 12:36:46 PM PST 24
Peak memory 205324 kb
Host smart-4a3c3176-105e-4f30-9d92-9b2a2753d2da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547040533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2547040533
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.9369674
Short name T538
Test name
Test status
Simulation time 434521211 ps
CPU time 3.26 seconds
Started Feb 19 12:36:37 PM PST 24
Finished Feb 19 12:36:46 PM PST 24
Peak memory 214036 kb
Host smart-76e7df3d-89e9-41d0-97c3-71684eaab28c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9369674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_r
eg_errors.9369674
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.4294512497
Short name T508
Test name
Test status
Simulation time 428423749 ps
CPU time 15.11 seconds
Started Feb 19 12:36:42 PM PST 24
Finished Feb 19 12:37:01 PM PST 24
Peak memory 213576 kb
Host smart-48b451c2-d058-43d4-b7ff-d46ad342b846
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294512497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.4294512497
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2855386393
Short name T129
Test name
Test status
Simulation time 53714919 ps
CPU time 1.88 seconds
Started Feb 19 12:36:38 PM PST 24
Finished Feb 19 12:36:45 PM PST 24
Peak memory 213712 kb
Host smart-994f88e5-7a48-4d0f-a687-7a53688fafde
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855386393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2855386393
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1041915837
Short name T524
Test name
Test status
Simulation time 44397170 ps
CPU time 0.96 seconds
Started Feb 19 12:36:45 PM PST 24
Finished Feb 19 12:36:48 PM PST 24
Peak memory 205252 kb
Host smart-3ae1ffe7-93a2-4bae-917b-5fb9f4610f19
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041915837 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1041915837
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.553222020
Short name T488
Test name
Test status
Simulation time 36174637 ps
CPU time 1.11 seconds
Started Feb 19 12:36:42 PM PST 24
Finished Feb 19 12:36:47 PM PST 24
Peak memory 205236 kb
Host smart-ce74f7ff-24c1-47fe-a5d4-d9b11c72799e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553222020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.553222020
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1354492700
Short name T418
Test name
Test status
Simulation time 20394606 ps
CPU time 0.84 seconds
Started Feb 19 12:36:45 PM PST 24
Finished Feb 19 12:36:49 PM PST 24
Peak memory 205052 kb
Host smart-f4f99962-413d-4f05-a4a6-5e71b038436c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354492700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1354492700
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4216636093
Short name T474
Test name
Test status
Simulation time 385359432 ps
CPU time 8.2 seconds
Started Feb 19 12:36:43 PM PST 24
Finished Feb 19 12:36:55 PM PST 24
Peak memory 213668 kb
Host smart-68f478ff-5a43-4fc1-8932-418a84334cd9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216636093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.4216636093
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.503887599
Short name T543
Test name
Test status
Simulation time 207490162 ps
CPU time 4.63 seconds
Started Feb 19 12:36:43 PM PST 24
Finished Feb 19 12:36:51 PM PST 24
Peak memory 220444 kb
Host smart-197980f6-79f9-4654-8a3b-10452937094b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503887599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.503887599
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3146681629
Short name T430
Test name
Test status
Simulation time 160805699 ps
CPU time 2.65 seconds
Started Feb 19 12:36:45 PM PST 24
Finished Feb 19 12:36:50 PM PST 24
Peak memory 213544 kb
Host smart-7bf3afb8-028b-46d1-9950-f81ed925a42f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146681629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3146681629
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2328877603
Short name T478
Test name
Test status
Simulation time 20325543 ps
CPU time 1.49 seconds
Started Feb 19 12:36:43 PM PST 24
Finished Feb 19 12:36:48 PM PST 24
Peak memory 213548 kb
Host smart-e0f79c41-6259-4b0c-9f21-c45903b6aeb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328877603 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2328877603
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2081039930
Short name T480
Test name
Test status
Simulation time 72781438 ps
CPU time 1.22 seconds
Started Feb 19 12:36:43 PM PST 24
Finished Feb 19 12:36:48 PM PST 24
Peak memory 205212 kb
Host smart-f95c4662-b85a-4a47-b630-0bac59482eee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081039930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2081039930
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3948978145
Short name T499
Test name
Test status
Simulation time 25537116 ps
CPU time 0.74 seconds
Started Feb 19 12:36:43 PM PST 24
Finished Feb 19 12:36:47 PM PST 24
Peak memory 205124 kb
Host smart-770ecb4f-ee70-4aa7-b62d-ddb80e90b753
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948978145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3948978145
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2522950997
Short name T461
Test name
Test status
Simulation time 674640856 ps
CPU time 2.3 seconds
Started Feb 19 12:36:41 PM PST 24
Finished Feb 19 12:36:47 PM PST 24
Peak memory 205164 kb
Host smart-9b369c5b-4d04-4437-b53d-7a31eff54782
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522950997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2522950997
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1458118359
Short name T517
Test name
Test status
Simulation time 230273504 ps
CPU time 6.19 seconds
Started Feb 19 12:36:43 PM PST 24
Finished Feb 19 12:36:53 PM PST 24
Peak memory 218608 kb
Host smart-161c988a-294c-4ea0-9a4b-04c06f787c42
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458118359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1458118359
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.57645445
Short name T450
Test name
Test status
Simulation time 603503201 ps
CPU time 9.48 seconds
Started Feb 19 12:36:46 PM PST 24
Finished Feb 19 12:36:58 PM PST 24
Peak memory 213628 kb
Host smart-65682522-ab64-46d2-a4bd-57eca5c6c771
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57645445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.ke
ymgr_shadow_reg_errors_with_csr_rw.57645445
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1089326712
Short name T467
Test name
Test status
Simulation time 714780293 ps
CPU time 3.63 seconds
Started Feb 19 12:36:43 PM PST 24
Finished Feb 19 12:36:50 PM PST 24
Peak memory 213436 kb
Host smart-da1d64c9-76a5-49fb-ab25-168047c27480
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089326712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1089326712
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3939796578
Short name T144
Test name
Test status
Simulation time 470667490 ps
CPU time 5.41 seconds
Started Feb 19 12:36:46 PM PST 24
Finished Feb 19 12:36:54 PM PST 24
Peak memory 213540 kb
Host smart-7f0a6590-b281-4259-a17a-582fd92161f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939796578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3939796578
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1298509101
Short name T119
Test name
Test status
Simulation time 27531310 ps
CPU time 1.68 seconds
Started Feb 19 12:36:50 PM PST 24
Finished Feb 19 12:36:54 PM PST 24
Peak memory 213492 kb
Host smart-f783219f-f639-492e-90cf-316f4dc069bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298509101 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1298509101
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3032954998
Short name T530
Test name
Test status
Simulation time 10315986 ps
CPU time 0.82 seconds
Started Feb 19 12:36:50 PM PST 24
Finished Feb 19 12:36:53 PM PST 24
Peak memory 205068 kb
Host smart-0ff23218-c2ac-4dfe-a3c7-798c4a459523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032954998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3032954998
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3602210090
Short name T446
Test name
Test status
Simulation time 319913182 ps
CPU time 6.97 seconds
Started Feb 19 12:36:46 PM PST 24
Finished Feb 19 12:36:55 PM PST 24
Peak memory 213796 kb
Host smart-83b619fb-6b3d-4e4b-a753-b7094cc4f325
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602210090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3602210090
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2680419441
Short name T516
Test name
Test status
Simulation time 210928866 ps
CPU time 4.55 seconds
Started Feb 19 12:36:47 PM PST 24
Finished Feb 19 12:36:53 PM PST 24
Peak memory 219840 kb
Host smart-7a023be7-caa6-40bb-8073-1fb5f7381610
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680419441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2680419441
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.421517716
Short name T163
Test name
Test status
Simulation time 1363922149 ps
CPU time 3.29 seconds
Started Feb 19 12:36:52 PM PST 24
Finished Feb 19 12:36:56 PM PST 24
Peak memory 216652 kb
Host smart-fa5b251f-46d5-4f77-9728-24f31b4a236d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421517716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.421517716
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3943232925
Short name T161
Test name
Test status
Simulation time 33559392 ps
CPU time 1.32 seconds
Started Feb 19 12:36:58 PM PST 24
Finished Feb 19 12:37:00 PM PST 24
Peak memory 213580 kb
Host smart-7a7a5622-138f-4ae8-baef-aacd372135dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943232925 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3943232925
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.836571661
Short name T425
Test name
Test status
Simulation time 156551607 ps
CPU time 1.2 seconds
Started Feb 19 12:36:50 PM PST 24
Finished Feb 19 12:36:53 PM PST 24
Peak memory 205224 kb
Host smart-8e5406cf-3cf4-422c-89b9-15d2148140fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836571661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.836571661
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1325337240
Short name T441
Test name
Test status
Simulation time 37665603 ps
CPU time 0.68 seconds
Started Feb 19 12:36:50 PM PST 24
Finished Feb 19 12:36:53 PM PST 24
Peak memory 205148 kb
Host smart-b75d2579-1b74-40fe-9229-6649a93524b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325337240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1325337240
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1970115096
Short name T545
Test name
Test status
Simulation time 627271176 ps
CPU time 7.43 seconds
Started Feb 19 12:36:50 PM PST 24
Finished Feb 19 12:37:00 PM PST 24
Peak memory 213764 kb
Host smart-492e5e62-e260-4a1c-b1fd-b24f50d990c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970115096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1970115096
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2083606740
Short name T442
Test name
Test status
Simulation time 222358591 ps
CPU time 8.14 seconds
Started Feb 19 12:36:51 PM PST 24
Finished Feb 19 12:37:00 PM PST 24
Peak memory 213608 kb
Host smart-b9adda23-d430-4eac-b306-b52effda8bac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083606740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2083606740
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2423554782
Short name T107
Test name
Test status
Simulation time 291142433 ps
CPU time 3.51 seconds
Started Feb 19 12:36:52 PM PST 24
Finished Feb 19 12:36:56 PM PST 24
Peak memory 213708 kb
Host smart-32830bf2-c686-4e1d-afed-2d43f21f1c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423554782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2423554782
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2003824437
Short name T712
Test name
Test status
Simulation time 45037238 ps
CPU time 0.74 seconds
Started Feb 19 03:08:34 PM PST 24
Finished Feb 19 03:08:36 PM PST 24
Peak memory 205852 kb
Host smart-643cc50a-de9f-48fa-ac6b-5b420eb09eb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003824437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2003824437
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.4175859739
Short name T213
Test name
Test status
Simulation time 229477097 ps
CPU time 3.12 seconds
Started Feb 19 03:08:20 PM PST 24
Finished Feb 19 03:08:25 PM PST 24
Peak memory 207848 kb
Host smart-9b5c2885-c4a2-4b82-ae07-73ba24637784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175859739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.4175859739
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.835141559
Short name T47
Test name
Test status
Simulation time 370026453 ps
CPU time 4.32 seconds
Started Feb 19 03:08:27 PM PST 24
Finished Feb 19 03:08:32 PM PST 24
Peak memory 222540 kb
Host smart-d3724480-d95d-4e11-a17e-9e0debdcad0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835141559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.835141559
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1269157849
Short name T892
Test name
Test status
Simulation time 58464592 ps
CPU time 2.38 seconds
Started Feb 19 03:08:20 PM PST 24
Finished Feb 19 03:08:24 PM PST 24
Peak memory 207784 kb
Host smart-261d474f-6666-431a-ac1d-6a22d52c7826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269157849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1269157849
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3944040096
Short name T93
Test name
Test status
Simulation time 1187687462 ps
CPU time 27.27 seconds
Started Feb 19 03:08:39 PM PST 24
Finished Feb 19 03:09:07 PM PST 24
Peak memory 239024 kb
Host smart-8d1b65e2-8770-495f-bd8a-fb988e008aea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944040096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3944040096
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1861980330
Short name T3
Test name
Test status
Simulation time 1475552415 ps
CPU time 21.75 seconds
Started Feb 19 03:08:21 PM PST 24
Finished Feb 19 03:08:44 PM PST 24
Peak memory 207972 kb
Host smart-88fef677-adb2-4475-bcb7-28d8d84f1d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861980330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1861980330
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3967332870
Short name T345
Test name
Test status
Simulation time 751932763 ps
CPU time 9.32 seconds
Started Feb 19 03:08:20 PM PST 24
Finished Feb 19 03:08:31 PM PST 24
Peak memory 208068 kb
Host smart-abc90527-ff98-4fc4-879a-22971c1549ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967332870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3967332870
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.4001314532
Short name T278
Test name
Test status
Simulation time 3115613149 ps
CPU time 19.87 seconds
Started Feb 19 03:08:23 PM PST 24
Finished Feb 19 03:08:45 PM PST 24
Peak memory 208236 kb
Host smart-75fcaff5-c2f8-4c4a-aacc-4535843a74c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001314532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.4001314532
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.528827909
Short name T710
Test name
Test status
Simulation time 234898217 ps
CPU time 3.02 seconds
Started Feb 19 03:08:21 PM PST 24
Finished Feb 19 03:08:27 PM PST 24
Peak memory 206828 kb
Host smart-c20745f3-02e0-4e97-9d04-db8e7fe5fdbf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528827909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.528827909
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1171454434
Short name T1048
Test name
Test status
Simulation time 103842259 ps
CPU time 3.8 seconds
Started Feb 19 03:08:20 PM PST 24
Finished Feb 19 03:08:26 PM PST 24
Peak memory 206576 kb
Host smart-90f2c992-bcf4-4b1d-825d-1b367798efe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171454434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1171454434
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1427939815
Short name T67
Test name
Test status
Simulation time 1278752014 ps
CPU time 28.25 seconds
Started Feb 19 03:08:30 PM PST 24
Finished Feb 19 03:08:59 PM PST 24
Peak memory 215432 kb
Host smart-2f54d76a-52fb-4cb4-87ca-6858c20c4543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427939815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1427939815
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.750737170
Short name T767
Test name
Test status
Simulation time 351535238 ps
CPU time 4.6 seconds
Started Feb 19 03:08:31 PM PST 24
Finished Feb 19 03:08:36 PM PST 24
Peak memory 222652 kb
Host smart-7fb19901-4225-48ce-8e69-c2871285ee5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750737170 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.750737170
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2103974566
Short name T937
Test name
Test status
Simulation time 173404960 ps
CPU time 7.17 seconds
Started Feb 19 03:08:24 PM PST 24
Finished Feb 19 03:08:32 PM PST 24
Peak memory 210144 kb
Host smart-21f93363-7ff3-42b9-98a4-32d47c59ee04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103974566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2103974566
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3956390839
Short name T1036
Test name
Test status
Simulation time 4803471074 ps
CPU time 43.35 seconds
Started Feb 19 03:08:29 PM PST 24
Finished Feb 19 03:09:13 PM PST 24
Peak memory 211852 kb
Host smart-b2b69c92-f3ea-45cf-acd1-7750a9a522d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956390839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3956390839
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1952348944
Short name T800
Test name
Test status
Simulation time 36800713 ps
CPU time 0.81 seconds
Started Feb 19 03:08:49 PM PST 24
Finished Feb 19 03:08:53 PM PST 24
Peak memory 205640 kb
Host smart-ce0fc77c-df40-4d8b-b894-0a484d254e44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952348944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1952348944
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3712981444
Short name T396
Test name
Test status
Simulation time 585880871 ps
CPU time 4.51 seconds
Started Feb 19 03:08:44 PM PST 24
Finished Feb 19 03:08:54 PM PST 24
Peak memory 214320 kb
Host smart-4e24f594-e761-4c8a-bd10-89a6037f1a02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3712981444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3712981444
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1674712253
Short name T721
Test name
Test status
Simulation time 409553537 ps
CPU time 3.16 seconds
Started Feb 19 03:08:43 PM PST 24
Finished Feb 19 03:08:48 PM PST 24
Peak memory 210180 kb
Host smart-ff04e866-172b-45db-ac9c-06222f049a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674712253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1674712253
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1265374358
Short name T65
Test name
Test status
Simulation time 992251783 ps
CPU time 14.18 seconds
Started Feb 19 03:08:46 PM PST 24
Finished Feb 19 03:09:06 PM PST 24
Peak memory 210300 kb
Host smart-ff08c6a9-4ea6-4386-a192-c647e14ba9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265374358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1265374358
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1876180696
Short name T316
Test name
Test status
Simulation time 165860418 ps
CPU time 3.21 seconds
Started Feb 19 03:08:42 PM PST 24
Finished Feb 19 03:08:48 PM PST 24
Peak memory 214176 kb
Host smart-103d9087-3c49-4d79-b808-7441ffe839a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876180696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1876180696
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2701082691
Short name T399
Test name
Test status
Simulation time 128645737 ps
CPU time 2.86 seconds
Started Feb 19 03:08:44 PM PST 24
Finished Feb 19 03:08:52 PM PST 24
Peak memory 222476 kb
Host smart-142bb571-f0cc-43cd-9924-2605707e3e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701082691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2701082691
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3144612922
Short name T775
Test name
Test status
Simulation time 298346113 ps
CPU time 4.31 seconds
Started Feb 19 03:08:40 PM PST 24
Finished Feb 19 03:08:46 PM PST 24
Peak memory 207244 kb
Host smart-c987a18c-a6bb-4c94-b4bd-fc19557b4501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144612922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3144612922
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.653812859
Short name T12
Test name
Test status
Simulation time 3099687039 ps
CPU time 60.96 seconds
Started Feb 19 03:08:49 PM PST 24
Finished Feb 19 03:09:53 PM PST 24
Peak memory 244292 kb
Host smart-e7e77174-2859-40ad-a691-72d75a20cea2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653812859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.653812859
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3562959982
Short name T1033
Test name
Test status
Simulation time 285109974 ps
CPU time 3.36 seconds
Started Feb 19 03:08:35 PM PST 24
Finished Feb 19 03:08:39 PM PST 24
Peak memory 208368 kb
Host smart-9d5c1b77-7303-4dcf-97cb-3d45bee5fef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562959982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3562959982
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1201494117
Short name T702
Test name
Test status
Simulation time 665171363 ps
CPU time 5.06 seconds
Started Feb 19 03:08:33 PM PST 24
Finished Feb 19 03:08:40 PM PST 24
Peak memory 208732 kb
Host smart-cf13ecf0-88e2-4670-bf82-baec4179bf41
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201494117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1201494117
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.347114734
Short name T983
Test name
Test status
Simulation time 1285057878 ps
CPU time 33.89 seconds
Started Feb 19 03:08:43 PM PST 24
Finished Feb 19 03:09:19 PM PST 24
Peak memory 208516 kb
Host smart-d2d5187e-8da0-4cae-a92a-02022e1c4aaa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347114734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.347114734
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1839125759
Short name T734
Test name
Test status
Simulation time 146597907 ps
CPU time 2.64 seconds
Started Feb 19 03:08:38 PM PST 24
Finished Feb 19 03:08:42 PM PST 24
Peak memory 207060 kb
Host smart-25641f6e-0e2c-4809-8356-0ba9a8b3322c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839125759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1839125759
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.52076634
Short name T615
Test name
Test status
Simulation time 32049497 ps
CPU time 1.57 seconds
Started Feb 19 03:08:49 PM PST 24
Finished Feb 19 03:08:54 PM PST 24
Peak memory 207304 kb
Host smart-f361924b-e785-4f70-b684-06ec4bff14bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52076634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.52076634
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1756704295
Short name T630
Test name
Test status
Simulation time 132338701 ps
CPU time 3.55 seconds
Started Feb 19 03:08:34 PM PST 24
Finished Feb 19 03:08:39 PM PST 24
Peak memory 208564 kb
Host smart-b7e98764-c23e-4c6f-b7b8-cd08b80bba62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756704295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1756704295
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.365688186
Short name T607
Test name
Test status
Simulation time 178911254 ps
CPU time 6.11 seconds
Started Feb 19 03:08:46 PM PST 24
Finished Feb 19 03:08:57 PM PST 24
Peak memory 218612 kb
Host smart-17189cf8-0624-42f1-abf9-65c60e8fee41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365688186 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.365688186
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.61099281
Short name T576
Test name
Test status
Simulation time 198793963 ps
CPU time 7.07 seconds
Started Feb 19 03:08:45 PM PST 24
Finished Feb 19 03:08:57 PM PST 24
Peak memory 209512 kb
Host smart-31e9763a-704c-4cc6-be64-2aa8825e70a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61099281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.61099281
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2072411334
Short name T602
Test name
Test status
Simulation time 10187904 ps
CPU time 0.87 seconds
Started Feb 19 03:10:32 PM PST 24
Finished Feb 19 03:10:39 PM PST 24
Peak memory 205784 kb
Host smart-7cfbba1b-c96c-43c0-b7c2-6b36fb82a574
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072411334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2072411334
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.4156503067
Short name T909
Test name
Test status
Simulation time 42272273 ps
CPU time 2.85 seconds
Started Feb 19 03:10:21 PM PST 24
Finished Feb 19 03:10:25 PM PST 24
Peak memory 214324 kb
Host smart-b851921f-0634-4564-a10e-49de43d05ed7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4156503067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.4156503067
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3117792755
Short name T55
Test name
Test status
Simulation time 84498260 ps
CPU time 4.67 seconds
Started Feb 19 03:10:21 PM PST 24
Finished Feb 19 03:10:26 PM PST 24
Peak memory 214616 kb
Host smart-72852863-837f-40e3-88a7-dc5ea87805db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117792755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3117792755
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1765664886
Short name T660
Test name
Test status
Simulation time 63741227 ps
CPU time 2.76 seconds
Started Feb 19 03:10:25 PM PST 24
Finished Feb 19 03:10:29 PM PST 24
Peak memory 209608 kb
Host smart-afdc92b9-b629-47b9-8f00-96cc7b672452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765664886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1765664886
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.334616295
Short name T943
Test name
Test status
Simulation time 512711221 ps
CPU time 5.21 seconds
Started Feb 19 03:10:27 PM PST 24
Finished Feb 19 03:10:34 PM PST 24
Peak memory 208900 kb
Host smart-10d17482-9701-40a9-85af-0b71c87a17c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334616295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.334616295
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.4001928374
Short name T41
Test name
Test status
Simulation time 77597679 ps
CPU time 3.7 seconds
Started Feb 19 03:10:22 PM PST 24
Finished Feb 19 03:10:26 PM PST 24
Peak memory 220428 kb
Host smart-01956ad6-b3d4-4751-aca1-3fbef5f6c328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001928374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.4001928374
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.4036546271
Short name T551
Test name
Test status
Simulation time 128388595 ps
CPU time 2.77 seconds
Started Feb 19 03:10:23 PM PST 24
Finished Feb 19 03:10:27 PM PST 24
Peak memory 207764 kb
Host smart-cf914105-01aa-4457-a2bc-30867a30d61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036546271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.4036546271
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3515255884
Short name T209
Test name
Test status
Simulation time 82285421 ps
CPU time 1.94 seconds
Started Feb 19 03:10:21 PM PST 24
Finished Feb 19 03:10:24 PM PST 24
Peak memory 208632 kb
Host smart-393a393c-83d6-4183-a183-65f5960a3bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515255884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3515255884
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3637294827
Short name T989
Test name
Test status
Simulation time 143975508 ps
CPU time 4.3 seconds
Started Feb 19 03:10:20 PM PST 24
Finished Feb 19 03:10:26 PM PST 24
Peak memory 206912 kb
Host smart-c9378fb0-c511-4f55-ad40-ba37612a3b15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637294827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3637294827
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.794749869
Short name T813
Test name
Test status
Simulation time 34012689 ps
CPU time 2.41 seconds
Started Feb 19 03:10:20 PM PST 24
Finished Feb 19 03:10:23 PM PST 24
Peak memory 207348 kb
Host smart-df785e38-741b-4c0e-a349-65c1e2c9907d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794749869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.794749869
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.270735995
Short name T553
Test name
Test status
Simulation time 1175051761 ps
CPU time 37.62 seconds
Started Feb 19 03:10:21 PM PST 24
Finished Feb 19 03:10:59 PM PST 24
Peak memory 207924 kb
Host smart-033e4039-a945-4a12-8023-ec2b3a1ef6a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270735995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.270735995
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.531150238
Short name T302
Test name
Test status
Simulation time 689247441 ps
CPU time 4.97 seconds
Started Feb 19 03:10:19 PM PST 24
Finished Feb 19 03:10:25 PM PST 24
Peak memory 208344 kb
Host smart-1a9883fe-c8d2-4b6e-a139-7c9137f70bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531150238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.531150238
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3762451561
Short name T962
Test name
Test status
Simulation time 1077688265 ps
CPU time 6.04 seconds
Started Feb 19 03:10:16 PM PST 24
Finished Feb 19 03:10:24 PM PST 24
Peak memory 207300 kb
Host smart-76205e7b-dee3-4095-88cb-ac3a93b4b7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762451561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3762451561
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3432538267
Short name T646
Test name
Test status
Simulation time 675449710 ps
CPU time 13.91 seconds
Started Feb 19 03:10:30 PM PST 24
Finished Feb 19 03:10:49 PM PST 24
Peak memory 216332 kb
Host smart-04fda984-5d34-4d70-b564-b0d87e1cf972
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432538267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3432538267
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3188504427
Short name T865
Test name
Test status
Simulation time 602521939 ps
CPU time 6.29 seconds
Started Feb 19 03:10:26 PM PST 24
Finished Feb 19 03:10:33 PM PST 24
Peak memory 222608 kb
Host smart-5cf8d221-1169-449b-8e45-dddeaaf1d6c1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188504427 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3188504427
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2505386708
Short name T275
Test name
Test status
Simulation time 314223677 ps
CPU time 4.47 seconds
Started Feb 19 03:10:20 PM PST 24
Finished Feb 19 03:10:26 PM PST 24
Peak memory 214232 kb
Host smart-69f3cb90-3f0c-4b96-858c-3fdebb2fd431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505386708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2505386708
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2878321175
Short name T595
Test name
Test status
Simulation time 93932429 ps
CPU time 1.38 seconds
Started Feb 19 03:10:33 PM PST 24
Finished Feb 19 03:10:40 PM PST 24
Peak memory 209600 kb
Host smart-c5fd8e17-ec85-407d-a7cc-588b3005a6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878321175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2878321175
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2913474839
Short name T762
Test name
Test status
Simulation time 18600538 ps
CPU time 0.81 seconds
Started Feb 19 03:10:34 PM PST 24
Finished Feb 19 03:10:42 PM PST 24
Peak memory 205796 kb
Host smart-363888af-574e-4429-96ce-36bc5d988ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913474839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2913474839
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.494116984
Short name T606
Test name
Test status
Simulation time 105910911 ps
CPU time 2.72 seconds
Started Feb 19 03:10:27 PM PST 24
Finished Feb 19 03:10:32 PM PST 24
Peak memory 207892 kb
Host smart-0ec9f3f1-766a-42ce-860b-386d652592df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494116984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.494116984
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3970063447
Short name T379
Test name
Test status
Simulation time 261171977 ps
CPU time 2.93 seconds
Started Feb 19 03:10:34 PM PST 24
Finished Feb 19 03:10:44 PM PST 24
Peak memory 218876 kb
Host smart-33f3b286-c275-45ca-9481-7065ab7d97cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970063447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3970063447
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3089398595
Short name T239
Test name
Test status
Simulation time 10834553531 ps
CPU time 60.18 seconds
Started Feb 19 03:10:32 PM PST 24
Finished Feb 19 03:11:39 PM PST 24
Peak memory 209756 kb
Host smart-3067b161-624c-4d44-b090-09137021e281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089398595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3089398595
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2560858367
Short name T365
Test name
Test status
Simulation time 95386683 ps
CPU time 4.18 seconds
Started Feb 19 03:10:29 PM PST 24
Finished Feb 19 03:10:39 PM PST 24
Peak memory 208460 kb
Host smart-cbe51dd9-0f64-4f49-b922-87a1eb666567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560858367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2560858367
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2966968582
Short name T818
Test name
Test status
Simulation time 202423340 ps
CPU time 2.93 seconds
Started Feb 19 03:10:25 PM PST 24
Finished Feb 19 03:10:29 PM PST 24
Peak memory 206704 kb
Host smart-0fb6aacd-bb52-4ae5-9aae-282b6c9da285
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966968582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2966968582
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.4185837612
Short name T629
Test name
Test status
Simulation time 42152679 ps
CPU time 1.94 seconds
Started Feb 19 03:10:24 PM PST 24
Finished Feb 19 03:10:28 PM PST 24
Peak memory 207276 kb
Host smart-83e4234a-99de-4390-beaf-2f400b67e12c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185837612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.4185837612
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.251944493
Short name T222
Test name
Test status
Simulation time 38012088 ps
CPU time 2.59 seconds
Started Feb 19 03:10:23 PM PST 24
Finished Feb 19 03:10:27 PM PST 24
Peak memory 208744 kb
Host smart-674094c2-a7bd-4f17-a8c9-abe02053dd98
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251944493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.251944493
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3610157958
Short name T572
Test name
Test status
Simulation time 1008820472 ps
CPU time 9.35 seconds
Started Feb 19 03:10:33 PM PST 24
Finished Feb 19 03:10:49 PM PST 24
Peak memory 208612 kb
Host smart-92aa3f13-3aef-46f2-a349-e7fcc1a88f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610157958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3610157958
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.30594853
Short name T1021
Test name
Test status
Simulation time 618607152 ps
CPU time 4.71 seconds
Started Feb 19 03:10:24 PM PST 24
Finished Feb 19 03:10:30 PM PST 24
Peak memory 206724 kb
Host smart-3d7e2fb7-4f0f-4d6f-8b1c-007bcc6ef106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30594853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.30594853
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1656950735
Short name T928
Test name
Test status
Simulation time 546412539 ps
CPU time 5.34 seconds
Started Feb 19 03:10:33 PM PST 24
Finished Feb 19 03:10:45 PM PST 24
Peak memory 209292 kb
Host smart-ce65f456-a513-4be7-8306-39a97853d1d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656950735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1656950735
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.4251514272
Short name T187
Test name
Test status
Simulation time 809290452 ps
CPU time 7.17 seconds
Started Feb 19 03:10:27 PM PST 24
Finished Feb 19 03:10:35 PM PST 24
Peak memory 222480 kb
Host smart-d1981805-b035-46e9-a2a3-40bacb3088b9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251514272 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.4251514272
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.588034256
Short name T1
Test name
Test status
Simulation time 450947139 ps
CPU time 6.96 seconds
Started Feb 19 03:10:32 PM PST 24
Finished Feb 19 03:10:44 PM PST 24
Peak memory 214344 kb
Host smart-f0cc1e40-25e0-4bad-81d3-ce451bcfcebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588034256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.588034256
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2567002717
Short name T763
Test name
Test status
Simulation time 27946978 ps
CPU time 0.93 seconds
Started Feb 19 03:10:35 PM PST 24
Finished Feb 19 03:10:43 PM PST 24
Peak memory 206052 kb
Host smart-d7313d06-f93b-481f-9c95-484f76e25ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567002717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2567002717
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2474879947
Short name T53
Test name
Test status
Simulation time 68686406 ps
CPU time 2.51 seconds
Started Feb 19 03:10:37 PM PST 24
Finished Feb 19 03:10:46 PM PST 24
Peak memory 207540 kb
Host smart-4f9534c3-27f5-4313-b736-8709874ef539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474879947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2474879947
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1015398119
Short name T1034
Test name
Test status
Simulation time 416017530 ps
CPU time 5.44 seconds
Started Feb 19 03:10:35 PM PST 24
Finished Feb 19 03:10:47 PM PST 24
Peak memory 222668 kb
Host smart-f8eefbe8-1322-4c47-b83e-3a6862e46019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015398119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1015398119
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1197927424
Short name T33
Test name
Test status
Simulation time 625775628 ps
CPU time 5.97 seconds
Started Feb 19 03:10:31 PM PST 24
Finished Feb 19 03:10:41 PM PST 24
Peak memory 209992 kb
Host smart-08403859-e876-446c-a17d-f98f2013a843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197927424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1197927424
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.2382668736
Short name T958
Test name
Test status
Simulation time 2162842831 ps
CPU time 9.32 seconds
Started Feb 19 03:10:33 PM PST 24
Finished Feb 19 03:10:49 PM PST 24
Peak memory 208928 kb
Host smart-e561a998-e42c-4cbe-98b3-d3a2ec6b473d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382668736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2382668736
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3746394661
Short name T715
Test name
Test status
Simulation time 70123547 ps
CPU time 2.34 seconds
Started Feb 19 03:10:31 PM PST 24
Finished Feb 19 03:10:37 PM PST 24
Peak memory 206748 kb
Host smart-481f91dd-463c-4239-9b37-0d79d52e2074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746394661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3746394661
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2661715028
Short name T946
Test name
Test status
Simulation time 271449128 ps
CPU time 3.59 seconds
Started Feb 19 03:10:35 PM PST 24
Finished Feb 19 03:10:46 PM PST 24
Peak memory 208468 kb
Host smart-72f0383b-3645-4913-a846-bab4d9afcd1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661715028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2661715028
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.777618305
Short name T808
Test name
Test status
Simulation time 104430686 ps
CPU time 3.09 seconds
Started Feb 19 03:10:36 PM PST 24
Finished Feb 19 03:10:46 PM PST 24
Peak memory 208292 kb
Host smart-dd8e2536-bc8d-4df6-b196-57378554dd1f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777618305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.777618305
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.14834598
Short name T554
Test name
Test status
Simulation time 2802330590 ps
CPU time 18.78 seconds
Started Feb 19 03:10:32 PM PST 24
Finished Feb 19 03:10:56 PM PST 24
Peak memory 208492 kb
Host smart-b4bef7e1-9c27-4040-91d0-e8177984c022
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14834598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.14834598
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1540222159
Short name T562
Test name
Test status
Simulation time 1199264342 ps
CPU time 12.08 seconds
Started Feb 19 03:10:32 PM PST 24
Finished Feb 19 03:10:49 PM PST 24
Peak memory 207768 kb
Host smart-71c67e11-6e95-4c17-8210-3d96bbf678a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540222159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1540222159
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1778276833
Short name T723
Test name
Test status
Simulation time 99457109 ps
CPU time 4.79 seconds
Started Feb 19 03:10:35 PM PST 24
Finished Feb 19 03:10:47 PM PST 24
Peak memory 218684 kb
Host smart-c1602467-0852-48b2-8d2d-e8344baeb3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778276833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1778276833
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2908365402
Short name T851
Test name
Test status
Simulation time 39675386 ps
CPU time 2.1 seconds
Started Feb 19 03:10:35 PM PST 24
Finished Feb 19 03:10:44 PM PST 24
Peak memory 209860 kb
Host smart-d116e489-4e71-4f2a-9a48-edf652973298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908365402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2908365402
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2759121753
Short name T978
Test name
Test status
Simulation time 58481016 ps
CPU time 0.8 seconds
Started Feb 19 03:10:44 PM PST 24
Finished Feb 19 03:10:48 PM PST 24
Peak memory 205880 kb
Host smart-caa290ee-12c3-4cf3-8397-6df226ce7e6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759121753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2759121753
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.591719597
Short name T403
Test name
Test status
Simulation time 45305117 ps
CPU time 3.45 seconds
Started Feb 19 03:10:44 PM PST 24
Finished Feb 19 03:10:50 PM PST 24
Peak memory 214336 kb
Host smart-b654c740-a869-45a9-8c2f-f3ecb3e51479
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=591719597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.591719597
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3620121268
Short name T832
Test name
Test status
Simulation time 557592508 ps
CPU time 3.83 seconds
Started Feb 19 03:10:35 PM PST 24
Finished Feb 19 03:10:47 PM PST 24
Peak memory 208476 kb
Host smart-14536f5d-1b33-42a5-8580-d632c1256c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620121268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3620121268
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1278414985
Short name T251
Test name
Test status
Simulation time 862665433 ps
CPU time 7.98 seconds
Started Feb 19 03:10:37 PM PST 24
Finished Feb 19 03:10:51 PM PST 24
Peak memory 222508 kb
Host smart-fde7139f-0e3b-4d2d-888d-0f3b30f4853d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278414985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1278414985
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2491491428
Short name T180
Test name
Test status
Simulation time 526750935 ps
CPU time 4.55 seconds
Started Feb 19 03:10:35 PM PST 24
Finished Feb 19 03:10:47 PM PST 24
Peak memory 215564 kb
Host smart-762ecf5e-761b-43d0-bf08-3b24b1478adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491491428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2491491428
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1658137442
Short name T837
Test name
Test status
Simulation time 149760297 ps
CPU time 6.87 seconds
Started Feb 19 03:10:33 PM PST 24
Finished Feb 19 03:10:47 PM PST 24
Peak memory 210516 kb
Host smart-e9050b3f-0e51-4e2b-8826-d922a33cd5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658137442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1658137442
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1673907862
Short name T559
Test name
Test status
Simulation time 59458630 ps
CPU time 2.98 seconds
Started Feb 19 03:10:34 PM PST 24
Finished Feb 19 03:10:44 PM PST 24
Peak memory 207892 kb
Host smart-ff2e0da6-c019-44f2-ad02-645954593c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673907862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1673907862
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3175038072
Short name T914
Test name
Test status
Simulation time 2129471529 ps
CPU time 9.23 seconds
Started Feb 19 03:10:34 PM PST 24
Finished Feb 19 03:10:50 PM PST 24
Peak memory 208140 kb
Host smart-2dd77202-a4cc-4330-bf5c-dd3f307609ed
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175038072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3175038072
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.719891465
Short name T838
Test name
Test status
Simulation time 280805032 ps
CPU time 7.39 seconds
Started Feb 19 03:10:43 PM PST 24
Finished Feb 19 03:10:52 PM PST 24
Peak memory 207760 kb
Host smart-4b556219-9c70-4c6f-9ba0-83773e187c96
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719891465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.719891465
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.244610512
Short name T1014
Test name
Test status
Simulation time 247256926 ps
CPU time 8.58 seconds
Started Feb 19 03:10:36 PM PST 24
Finished Feb 19 03:10:52 PM PST 24
Peak memory 207812 kb
Host smart-02a255fb-8e44-4fd7-916d-1761ac15bd0b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244610512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.244610512
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3113572248
Short name T984
Test name
Test status
Simulation time 49029809 ps
CPU time 1.79 seconds
Started Feb 19 03:10:34 PM PST 24
Finished Feb 19 03:10:43 PM PST 24
Peak memory 208896 kb
Host smart-3018f606-54de-462f-8232-6ce79c04d936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113572248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3113572248
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3327081275
Short name T701
Test name
Test status
Simulation time 429368112 ps
CPU time 9.57 seconds
Started Feb 19 03:10:35 PM PST 24
Finished Feb 19 03:10:51 PM PST 24
Peak memory 208076 kb
Host smart-4e928d28-c661-4db1-bea2-edcb5fcaf5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327081275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3327081275
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.634780423
Short name T341
Test name
Test status
Simulation time 7774611393 ps
CPU time 68.94 seconds
Started Feb 19 03:10:36 PM PST 24
Finished Feb 19 03:11:52 PM PST 24
Peak memory 218288 kb
Host smart-6999cba7-e7b0-4d95-8e40-ba62315591fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634780423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.634780423
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2537398042
Short name T960
Test name
Test status
Simulation time 367916020 ps
CPU time 14.73 seconds
Started Feb 19 03:10:48 PM PST 24
Finished Feb 19 03:11:05 PM PST 24
Peak memory 223228 kb
Host smart-6fe4cb6d-b01e-4261-bd7e-b18990ae76de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537398042 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2537398042
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1250399429
Short name T242
Test name
Test status
Simulation time 133526250 ps
CPU time 5.67 seconds
Started Feb 19 03:10:39 PM PST 24
Finished Feb 19 03:10:50 PM PST 24
Peak memory 209464 kb
Host smart-dbd1cbdc-3877-4ba0-9221-6f2e4146b44f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250399429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1250399429
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1946816172
Short name T797
Test name
Test status
Simulation time 94614264 ps
CPU time 2.79 seconds
Started Feb 19 03:10:36 PM PST 24
Finished Feb 19 03:10:46 PM PST 24
Peak memory 210296 kb
Host smart-e209151d-3302-441c-b8a3-4fd49673c151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946816172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1946816172
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2200675473
Short name T560
Test name
Test status
Simulation time 11172824 ps
CPU time 0.71 seconds
Started Feb 19 03:10:46 PM PST 24
Finished Feb 19 03:10:50 PM PST 24
Peak memory 205872 kb
Host smart-3e7e2650-9a16-483d-88bf-c512d79954ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200675473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2200675473
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2419919358
Short name T402
Test name
Test status
Simulation time 762641418 ps
CPU time 7.16 seconds
Started Feb 19 03:10:44 PM PST 24
Finished Feb 19 03:10:54 PM PST 24
Peak memory 214432 kb
Host smart-1386d213-b5a9-4346-af1c-26249c42a3c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2419919358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2419919358
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.4219337406
Short name T811
Test name
Test status
Simulation time 58992224 ps
CPU time 3.81 seconds
Started Feb 19 03:10:43 PM PST 24
Finished Feb 19 03:10:50 PM PST 24
Peak memory 220896 kb
Host smart-4df36ab1-0df9-42e2-b168-100a530c9503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219337406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.4219337406
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1972587885
Short name T244
Test name
Test status
Simulation time 73450686 ps
CPU time 3.27 seconds
Started Feb 19 03:10:41 PM PST 24
Finished Feb 19 03:10:48 PM PST 24
Peak memory 210048 kb
Host smart-df70204c-44df-48f2-8a9f-771c9cf4e837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972587885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1972587885
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.446795097
Short name T267
Test name
Test status
Simulation time 275140135 ps
CPU time 11.36 seconds
Started Feb 19 03:10:46 PM PST 24
Finished Feb 19 03:11:00 PM PST 24
Peak memory 214256 kb
Host smart-7c98bafb-0b86-4287-8674-cbef435b45ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446795097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.446795097
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_random.2841849559
Short name T761
Test name
Test status
Simulation time 785746610 ps
CPU time 19.15 seconds
Started Feb 19 03:10:43 PM PST 24
Finished Feb 19 03:11:04 PM PST 24
Peak memory 207980 kb
Host smart-9e643331-6df9-4cda-9e54-8d0bd2bd7451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841849559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2841849559
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1955027658
Short name T657
Test name
Test status
Simulation time 140838045 ps
CPU time 2.78 seconds
Started Feb 19 03:10:43 PM PST 24
Finished Feb 19 03:10:49 PM PST 24
Peak memory 206740 kb
Host smart-35bed25e-2041-4216-9415-dc87ca355376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955027658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1955027658
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3883134465
Short name T633
Test name
Test status
Simulation time 3565393066 ps
CPU time 7.78 seconds
Started Feb 19 03:10:44 PM PST 24
Finished Feb 19 03:10:55 PM PST 24
Peak memory 208008 kb
Host smart-eea9b0c7-eb24-4723-ae93-0a15d213b0fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883134465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3883134465
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1135361105
Short name T317
Test name
Test status
Simulation time 227349936 ps
CPU time 3.02 seconds
Started Feb 19 03:10:40 PM PST 24
Finished Feb 19 03:10:48 PM PST 24
Peak memory 208532 kb
Host smart-b0d5246b-4adf-445d-8fbb-f4e5cd096596
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135361105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1135361105
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2962363211
Short name T383
Test name
Test status
Simulation time 108205892 ps
CPU time 2.87 seconds
Started Feb 19 03:10:43 PM PST 24
Finished Feb 19 03:10:49 PM PST 24
Peak memory 208924 kb
Host smart-456c3a03-3549-4c94-8965-fa2e37f9499e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962363211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2962363211
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.4212062596
Short name T879
Test name
Test status
Simulation time 170204888 ps
CPU time 4.53 seconds
Started Feb 19 03:10:46 PM PST 24
Finished Feb 19 03:10:53 PM PST 24
Peak memory 210184 kb
Host smart-fd200b9e-3bd5-425f-8975-53344769cab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212062596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.4212062596
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1893217992
Short name T995
Test name
Test status
Simulation time 95541841 ps
CPU time 2.81 seconds
Started Feb 19 03:10:44 PM PST 24
Finished Feb 19 03:10:50 PM PST 24
Peak memory 206640 kb
Host smart-3454c066-468d-41d3-ba64-d60157881ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893217992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1893217992
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2232367927
Short name T923
Test name
Test status
Simulation time 1235908793 ps
CPU time 6.4 seconds
Started Feb 19 03:10:47 PM PST 24
Finished Feb 19 03:10:56 PM PST 24
Peak memory 222700 kb
Host smart-2890ec0a-21aa-4a67-beec-974d59c52b2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232367927 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2232367927
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.124230494
Short name T685
Test name
Test status
Simulation time 134349109 ps
CPU time 4.51 seconds
Started Feb 19 03:10:47 PM PST 24
Finished Feb 19 03:10:54 PM PST 24
Peak memory 207816 kb
Host smart-d7fc86f9-1b14-4d2a-bc3b-e481ec0c1f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124230494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.124230494
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1211304837
Short name T759
Test name
Test status
Simulation time 58452596 ps
CPU time 0.94 seconds
Started Feb 19 03:10:57 PM PST 24
Finished Feb 19 03:10:59 PM PST 24
Peak memory 205992 kb
Host smart-d2c67c36-c849-4127-8eb8-efbfe95d7e17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211304837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1211304837
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1232289852
Short name T408
Test name
Test status
Simulation time 84056108 ps
CPU time 3.31 seconds
Started Feb 19 03:10:48 PM PST 24
Finished Feb 19 03:10:54 PM PST 24
Peak memory 215356 kb
Host smart-8a23b471-0951-49df-b499-b781cc40c09c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1232289852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1232289852
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.700080311
Short name T9
Test name
Test status
Simulation time 2116702643 ps
CPU time 17.45 seconds
Started Feb 19 03:10:54 PM PST 24
Finished Feb 19 03:11:13 PM PST 24
Peak memory 217544 kb
Host smart-42642eab-6103-4259-9639-bf8ccb1f91cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700080311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.700080311
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1824603441
Short name T349
Test name
Test status
Simulation time 1352988846 ps
CPU time 24.41 seconds
Started Feb 19 03:10:49 PM PST 24
Finished Feb 19 03:11:16 PM PST 24
Peak memory 208236 kb
Host smart-d07b30be-1d62-40da-a598-591d804a8969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824603441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1824603441
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.43352106
Short name T1054
Test name
Test status
Simulation time 151828930 ps
CPU time 6.01 seconds
Started Feb 19 03:10:47 PM PST 24
Finished Feb 19 03:10:56 PM PST 24
Peak memory 208356 kb
Host smart-b2ccc8d6-c802-4fd1-86f6-f8bbf5e9bc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43352106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.43352106
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2052291455
Short name T156
Test name
Test status
Simulation time 166081763 ps
CPU time 3.91 seconds
Started Feb 19 03:10:50 PM PST 24
Finished Feb 19 03:10:56 PM PST 24
Peak memory 211096 kb
Host smart-dedac5a4-5d8d-4027-a39a-770336084df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052291455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2052291455
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.912757153
Short name T758
Test name
Test status
Simulation time 607882797 ps
CPU time 6.8 seconds
Started Feb 19 03:10:49 PM PST 24
Finished Feb 19 03:10:58 PM PST 24
Peak memory 207244 kb
Host smart-02e9d6ff-bd78-45f6-8f5e-b24252a44dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912757153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.912757153
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2372869896
Short name T232
Test name
Test status
Simulation time 338653246 ps
CPU time 4.31 seconds
Started Feb 19 03:10:46 PM PST 24
Finished Feb 19 03:10:53 PM PST 24
Peak memory 208684 kb
Host smart-215592ab-7a51-4c6c-a5b3-9c3a2067c612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372869896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2372869896
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.4168726842
Short name T1067
Test name
Test status
Simulation time 241057579 ps
CPU time 1.99 seconds
Started Feb 19 03:10:45 PM PST 24
Finished Feb 19 03:10:50 PM PST 24
Peak memory 206744 kb
Host smart-2c9f0467-205d-4d16-a4ed-5f85cd8ee42a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168726842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.4168726842
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3318936484
Short name T347
Test name
Test status
Simulation time 23562164 ps
CPU time 1.83 seconds
Started Feb 19 03:10:45 PM PST 24
Finished Feb 19 03:10:51 PM PST 24
Peak memory 206788 kb
Host smart-a53f91d6-bc6a-4a54-a5c1-1826004096d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318936484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3318936484
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1229059258
Short name T652
Test name
Test status
Simulation time 114683195 ps
CPU time 3.14 seconds
Started Feb 19 03:10:52 PM PST 24
Finished Feb 19 03:10:56 PM PST 24
Peak memory 208752 kb
Host smart-2595eac6-db0f-4f60-84bb-bdd45a256fbb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229059258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1229059258
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1910215468
Short name T323
Test name
Test status
Simulation time 517363927 ps
CPU time 2.8 seconds
Started Feb 19 03:10:55 PM PST 24
Finished Feb 19 03:10:59 PM PST 24
Peak memory 209112 kb
Host smart-7b48ed82-40f3-4d04-a07d-d6f76d5b5fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910215468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1910215468
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.4061337118
Short name T2
Test name
Test status
Simulation time 917623079 ps
CPU time 19.07 seconds
Started Feb 19 03:10:45 PM PST 24
Finished Feb 19 03:11:08 PM PST 24
Peak memory 207936 kb
Host smart-30dcc891-4908-4a31-ba36-7ca009fcde08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061337118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.4061337118
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2090833094
Short name T656
Test name
Test status
Simulation time 91686068 ps
CPU time 4.12 seconds
Started Feb 19 03:10:56 PM PST 24
Finished Feb 19 03:11:01 PM PST 24
Peak memory 222616 kb
Host smart-cab65a79-b189-43d1-af95-fd4da7099bac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090833094 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2090833094
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2785948828
Short name T235
Test name
Test status
Simulation time 58693530 ps
CPU time 3.44 seconds
Started Feb 19 03:10:48 PM PST 24
Finished Feb 19 03:10:54 PM PST 24
Peak memory 219548 kb
Host smart-108dcf04-eb05-4249-aee5-1456866c4334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785948828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2785948828
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.601208270
Short name T956
Test name
Test status
Simulation time 374342256 ps
CPU time 6.89 seconds
Started Feb 19 03:10:53 PM PST 24
Finished Feb 19 03:11:01 PM PST 24
Peak memory 209888 kb
Host smart-a62131b7-34e1-442b-8d52-aee814b7f81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601208270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.601208270
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1606641103
Short name T929
Test name
Test status
Simulation time 41320923 ps
CPU time 0.87 seconds
Started Feb 19 03:11:10 PM PST 24
Finished Feb 19 03:11:15 PM PST 24
Peak memory 205856 kb
Host smart-45f46d75-d9f8-436f-99cf-afac04dec1f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606641103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1606641103
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3145071663
Short name T927
Test name
Test status
Simulation time 3632666136 ps
CPU time 34.76 seconds
Started Feb 19 03:11:01 PM PST 24
Finished Feb 19 03:11:37 PM PST 24
Peak memory 209460 kb
Host smart-82cb3aff-0925-4489-aef3-632167b46eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145071663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3145071663
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2285349331
Short name T82
Test name
Test status
Simulation time 1212795149 ps
CPU time 12.65 seconds
Started Feb 19 03:11:02 PM PST 24
Finished Feb 19 03:11:17 PM PST 24
Peak memory 214316 kb
Host smart-139e796f-71ab-4976-84a4-45cf6b80c606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285349331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2285349331
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3483939762
Short name T88
Test name
Test status
Simulation time 32251595 ps
CPU time 2.33 seconds
Started Feb 19 03:11:02 PM PST 24
Finished Feb 19 03:11:05 PM PST 24
Peak memory 209832 kb
Host smart-0748a469-028a-498a-b1ed-30f1433dbd49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483939762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3483939762
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1885605424
Short name T643
Test name
Test status
Simulation time 496061619 ps
CPU time 15.87 seconds
Started Feb 19 03:10:58 PM PST 24
Finished Feb 19 03:11:15 PM PST 24
Peak memory 214356 kb
Host smart-11682fa5-2a4e-4793-bafe-f691114b86f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885605424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1885605424
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.118563339
Short name T1032
Test name
Test status
Simulation time 1428251931 ps
CPU time 36.33 seconds
Started Feb 19 03:10:59 PM PST 24
Finished Feb 19 03:11:37 PM PST 24
Peak memory 209532 kb
Host smart-95c38c46-5cd3-4171-a38c-2d4ccd6da852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118563339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.118563339
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.250838934
Short name T866
Test name
Test status
Simulation time 553532117 ps
CPU time 8.69 seconds
Started Feb 19 03:11:03 PM PST 24
Finished Feb 19 03:11:14 PM PST 24
Peak memory 208628 kb
Host smart-f6690bfb-e50a-4787-986d-de00889d5424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250838934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.250838934
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3411518849
Short name T565
Test name
Test status
Simulation time 108131492 ps
CPU time 4.53 seconds
Started Feb 19 03:10:59 PM PST 24
Finished Feb 19 03:11:06 PM PST 24
Peak memory 208340 kb
Host smart-397ef523-8c9e-4d93-8042-d50557475a45
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411518849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3411518849
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.4221204155
Short name T640
Test name
Test status
Simulation time 966126906 ps
CPU time 7.35 seconds
Started Feb 19 03:11:03 PM PST 24
Finished Feb 19 03:11:12 PM PST 24
Peak memory 208040 kb
Host smart-ebe588dd-e9de-4130-ad6f-3e9e25210965
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221204155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.4221204155
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3870782923
Short name T876
Test name
Test status
Simulation time 884915943 ps
CPU time 7.09 seconds
Started Feb 19 03:11:02 PM PST 24
Finished Feb 19 03:11:12 PM PST 24
Peak memory 208608 kb
Host smart-bf893fe9-bc96-47ed-8244-5934f8a471e6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870782923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3870782923
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.783659709
Short name T622
Test name
Test status
Simulation time 28111678 ps
CPU time 1.99 seconds
Started Feb 19 03:10:57 PM PST 24
Finished Feb 19 03:11:00 PM PST 24
Peak memory 214192 kb
Host smart-f4919934-36e7-4ea4-afbb-516e2e7e4884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783659709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.783659709
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.161882420
Short name T581
Test name
Test status
Simulation time 194748007 ps
CPU time 2.63 seconds
Started Feb 19 03:11:02 PM PST 24
Finished Feb 19 03:11:06 PM PST 24
Peak memory 206688 kb
Host smart-e500be67-c49e-4c36-b375-7b13d1ebce25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161882420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.161882420
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.352408142
Short name T947
Test name
Test status
Simulation time 2489835336 ps
CPU time 17.32 seconds
Started Feb 19 03:11:02 PM PST 24
Finished Feb 19 03:11:22 PM PST 24
Peak memory 218628 kb
Host smart-a71ca5e4-9429-4b7f-a2a7-b831364ecfae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352408142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.352408142
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.901802090
Short name T621
Test name
Test status
Simulation time 81522613 ps
CPU time 2.61 seconds
Started Feb 19 03:11:02 PM PST 24
Finished Feb 19 03:11:07 PM PST 24
Peak memory 218304 kb
Host smart-2d22c184-47e4-4842-a2bb-672f8f8929ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901802090 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.901802090
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3045363153
Short name T578
Test name
Test status
Simulation time 247165487 ps
CPU time 7.71 seconds
Started Feb 19 03:10:58 PM PST 24
Finished Feb 19 03:11:08 PM PST 24
Peak memory 209104 kb
Host smart-08dfc381-a0cf-4f95-9cb3-d53669ba2054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045363153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3045363153
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1647221560
Short name T146
Test name
Test status
Simulation time 91907487 ps
CPU time 2.25 seconds
Started Feb 19 03:11:02 PM PST 24
Finished Feb 19 03:11:07 PM PST 24
Peak memory 209720 kb
Host smart-723e8d75-fa1e-4337-a2a3-a89e6b08a979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647221560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1647221560
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3499953168
Short name T564
Test name
Test status
Simulation time 44040539 ps
CPU time 0.79 seconds
Started Feb 19 03:11:12 PM PST 24
Finished Feb 19 03:11:17 PM PST 24
Peak memory 205992 kb
Host smart-294ec43f-5836-4699-be99-870365576de1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499953168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3499953168
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.4242076221
Short name T834
Test name
Test status
Simulation time 193075915 ps
CPU time 1.78 seconds
Started Feb 19 03:11:10 PM PST 24
Finished Feb 19 03:11:17 PM PST 24
Peak memory 215836 kb
Host smart-d8f9c00d-7886-41c5-97bf-c0a5b03c39f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242076221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.4242076221
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.23168972
Short name T255
Test name
Test status
Simulation time 89523576 ps
CPU time 3.71 seconds
Started Feb 19 03:11:04 PM PST 24
Finished Feb 19 03:11:12 PM PST 24
Peak memory 214332 kb
Host smart-b929878f-da16-441c-9feb-fa6565e12616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23168972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.23168972
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1245363808
Short name T318
Test name
Test status
Simulation time 1401959262 ps
CPU time 5.23 seconds
Started Feb 19 03:11:11 PM PST 24
Finished Feb 19 03:11:20 PM PST 24
Peak memory 214308 kb
Host smart-f74eadcf-bc73-45db-a7f7-e77c7d37fb15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245363808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1245363808
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1846774532
Short name T935
Test name
Test status
Simulation time 403460279 ps
CPU time 5.37 seconds
Started Feb 19 03:11:11 PM PST 24
Finished Feb 19 03:11:21 PM PST 24
Peak memory 214212 kb
Host smart-18d24a52-aa13-40a2-aa49-2f339be2b048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846774532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1846774532
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.545349231
Short name T261
Test name
Test status
Simulation time 215967392 ps
CPU time 4.07 seconds
Started Feb 19 03:11:05 PM PST 24
Finished Feb 19 03:11:14 PM PST 24
Peak memory 214344 kb
Host smart-5b1c94b6-7edd-4c74-9759-932201d6d592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545349231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.545349231
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2253551690
Short name T684
Test name
Test status
Simulation time 201632253 ps
CPU time 3.63 seconds
Started Feb 19 03:11:05 PM PST 24
Finished Feb 19 03:11:14 PM PST 24
Peak memory 209816 kb
Host smart-f23de3f1-7a48-4131-946d-69176e72fcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253551690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2253551690
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2399673103
Short name T221
Test name
Test status
Simulation time 2718380528 ps
CPU time 8.59 seconds
Started Feb 19 03:11:01 PM PST 24
Finished Feb 19 03:11:11 PM PST 24
Peak memory 208536 kb
Host smart-0e33fc95-6c48-4f93-ba4f-2ed963d74064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399673103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2399673103
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3624960498
Short name T733
Test name
Test status
Simulation time 75516266 ps
CPU time 3.8 seconds
Started Feb 19 03:11:01 PM PST 24
Finished Feb 19 03:11:06 PM PST 24
Peak memory 206876 kb
Host smart-c4bd0321-f9e7-4718-a3da-6b54ba54a4bb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624960498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3624960498
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3925317610
Short name T1025
Test name
Test status
Simulation time 60607942 ps
CPU time 2.55 seconds
Started Feb 19 03:11:05 PM PST 24
Finished Feb 19 03:11:12 PM PST 24
Peak memory 208556 kb
Host smart-d88e16f9-f544-48f7-93d5-729115ca1bf2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925317610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3925317610
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3272346621
Short name T953
Test name
Test status
Simulation time 361898873 ps
CPU time 4.35 seconds
Started Feb 19 03:11:04 PM PST 24
Finished Feb 19 03:11:13 PM PST 24
Peak memory 208756 kb
Host smart-26d5c98a-1eb4-49d1-92eb-3b5baf7ed460
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272346621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3272346621
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1526607531
Short name T94
Test name
Test status
Simulation time 202479030 ps
CPU time 2.3 seconds
Started Feb 19 03:11:10 PM PST 24
Finished Feb 19 03:11:17 PM PST 24
Peak memory 207804 kb
Host smart-558b1080-440d-4ee5-a655-4c77349c871f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526607531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1526607531
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.825204350
Short name T74
Test name
Test status
Simulation time 374837376 ps
CPU time 7.18 seconds
Started Feb 19 03:11:02 PM PST 24
Finished Feb 19 03:11:10 PM PST 24
Peak memory 206752 kb
Host smart-67a56c1b-05eb-4c84-b60b-ce4d3e0e2923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825204350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.825204350
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.223283432
Short name T855
Test name
Test status
Simulation time 150171262 ps
CPU time 4.77 seconds
Started Feb 19 03:11:11 PM PST 24
Finished Feb 19 03:11:20 PM PST 24
Peak memory 222556 kb
Host smart-c217e7ca-8cba-4c85-8947-7cdc2d589c72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223283432 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.223283432
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1861588643
Short name T982
Test name
Test status
Simulation time 50740148 ps
CPU time 3.34 seconds
Started Feb 19 03:11:06 PM PST 24
Finished Feb 19 03:11:14 PM PST 24
Peak memory 218168 kb
Host smart-c878b118-2f02-445e-889b-554b20e6eddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861588643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1861588643
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1427609663
Short name T153
Test name
Test status
Simulation time 95755251 ps
CPU time 2.4 seconds
Started Feb 19 03:11:10 PM PST 24
Finished Feb 19 03:11:17 PM PST 24
Peak memory 210248 kb
Host smart-f0f1a6a8-2dda-4065-983d-6a4ea6f72839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427609663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1427609663
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.4076499195
Short name T830
Test name
Test status
Simulation time 9207229 ps
CPU time 0.8 seconds
Started Feb 19 03:11:16 PM PST 24
Finished Feb 19 03:11:20 PM PST 24
Peak memory 205876 kb
Host smart-14c793c0-1ab5-496c-b84c-9c9e45cd3143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076499195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.4076499195
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3595720769
Short name T359
Test name
Test status
Simulation time 95592423 ps
CPU time 3.53 seconds
Started Feb 19 03:11:13 PM PST 24
Finished Feb 19 03:11:21 PM PST 24
Peak memory 215420 kb
Host smart-2d38f12e-9d9c-4a32-811c-6e25f388f942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3595720769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3595720769
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3240757345
Short name T587
Test name
Test status
Simulation time 582510624 ps
CPU time 4.01 seconds
Started Feb 19 03:11:10 PM PST 24
Finished Feb 19 03:11:19 PM PST 24
Peak memory 209068 kb
Host smart-929be661-a8d2-46ee-a82e-ca74ac93f8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240757345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3240757345
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2678188098
Short name T1071
Test name
Test status
Simulation time 1077481382 ps
CPU time 2.66 seconds
Started Feb 19 03:11:14 PM PST 24
Finished Feb 19 03:11:20 PM PST 24
Peak memory 207128 kb
Host smart-a0984a27-48b0-42a2-a3e6-65a049d96304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678188098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2678188098
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1302382052
Short name T957
Test name
Test status
Simulation time 612432748 ps
CPU time 7.17 seconds
Started Feb 19 03:11:11 PM PST 24
Finished Feb 19 03:11:23 PM PST 24
Peak memory 214256 kb
Host smart-f88cd136-dd8c-4317-b935-58df417f3bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302382052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1302382052
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.52969957
Short name T840
Test name
Test status
Simulation time 503799736 ps
CPU time 6.68 seconds
Started Feb 19 03:11:10 PM PST 24
Finished Feb 19 03:11:21 PM PST 24
Peak memory 222388 kb
Host smart-a3a1cb6c-03dd-4d54-b0f0-7ccbbd57f9d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52969957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.52969957
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.4228129330
Short name T857
Test name
Test status
Simulation time 73725981 ps
CPU time 3.81 seconds
Started Feb 19 03:11:09 PM PST 24
Finished Feb 19 03:11:18 PM PST 24
Peak memory 222556 kb
Host smart-8ffbd747-fe79-4995-b092-69c7296ff4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228129330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4228129330
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3861425893
Short name T600
Test name
Test status
Simulation time 1560151375 ps
CPU time 16.43 seconds
Started Feb 19 03:11:18 PM PST 24
Finished Feb 19 03:11:37 PM PST 24
Peak memory 214260 kb
Host smart-c487ac85-9fe5-4f0f-be58-1f93583c5c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861425893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3861425893
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.683708655
Short name T339
Test name
Test status
Simulation time 397432807 ps
CPU time 3.2 seconds
Started Feb 19 03:11:09 PM PST 24
Finished Feb 19 03:11:17 PM PST 24
Peak memory 206872 kb
Host smart-1b53b496-cb2a-4e2c-aa5c-d0e141164409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683708655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.683708655
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1218793964
Short name T689
Test name
Test status
Simulation time 2300047753 ps
CPU time 83.05 seconds
Started Feb 19 03:11:10 PM PST 24
Finished Feb 19 03:12:38 PM PST 24
Peak memory 208580 kb
Host smart-d71e6a83-7c60-4701-8fae-3febfec63db3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218793964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1218793964
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.3048821710
Short name T716
Test name
Test status
Simulation time 122415393 ps
CPU time 2.6 seconds
Started Feb 19 03:11:13 PM PST 24
Finished Feb 19 03:11:20 PM PST 24
Peak memory 206744 kb
Host smart-90de0c40-a743-489f-82ce-765686244e39
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048821710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.3048821710
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2284019904
Short name T644
Test name
Test status
Simulation time 268257354 ps
CPU time 3.6 seconds
Started Feb 19 03:11:17 PM PST 24
Finished Feb 19 03:11:24 PM PST 24
Peak memory 208700 kb
Host smart-8fdf3882-40eb-43d4-aa12-6737b5632273
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284019904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2284019904
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.137278001
Short name T573
Test name
Test status
Simulation time 174870296 ps
CPU time 2.66 seconds
Started Feb 19 03:11:13 PM PST 24
Finished Feb 19 03:11:20 PM PST 24
Peak memory 218260 kb
Host smart-65013edc-b515-4dfc-b040-ad26de04fb1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137278001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.137278001
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3583654294
Short name T746
Test name
Test status
Simulation time 226084629 ps
CPU time 3.62 seconds
Started Feb 19 03:11:11 PM PST 24
Finished Feb 19 03:11:19 PM PST 24
Peak memory 206804 kb
Host smart-5d124984-bec7-49ea-ba18-5b3e7df14348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583654294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3583654294
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2592762342
Short name T334
Test name
Test status
Simulation time 1110967420 ps
CPU time 43.42 seconds
Started Feb 19 03:11:15 PM PST 24
Finished Feb 19 03:12:01 PM PST 24
Peak memory 222360 kb
Host smart-6d53e323-8ae5-4215-8178-7750f04a7e30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592762342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2592762342
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.879078919
Short name T878
Test name
Test status
Simulation time 313992366 ps
CPU time 10.09 seconds
Started Feb 19 03:11:17 PM PST 24
Finished Feb 19 03:11:30 PM PST 24
Peak memory 222576 kb
Host smart-55e105be-44e2-4dd1-88d3-f9650ced3c58
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879078919 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.879078919
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.374358036
Short name T26
Test name
Test status
Simulation time 445410681 ps
CPU time 3.85 seconds
Started Feb 19 03:11:09 PM PST 24
Finished Feb 19 03:11:18 PM PST 24
Peak memory 207824 kb
Host smart-3c017e38-47d1-4d3b-a7e6-04728ab7ff0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374358036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.374358036
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1394223409
Short name T568
Test name
Test status
Simulation time 77562536 ps
CPU time 2.13 seconds
Started Feb 19 03:11:20 PM PST 24
Finished Feb 19 03:11:24 PM PST 24
Peak memory 210008 kb
Host smart-85a97947-9218-47fc-83a2-aef15cd37f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394223409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1394223409
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.273973290
Short name T949
Test name
Test status
Simulation time 13761906 ps
CPU time 0.91 seconds
Started Feb 19 03:11:27 PM PST 24
Finished Feb 19 03:11:30 PM PST 24
Peak memory 206028 kb
Host smart-f24e912a-5f10-4652-a962-5edb5c6a9a7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273973290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.273973290
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2651514839
Short name T400
Test name
Test status
Simulation time 33283681 ps
CPU time 2.6 seconds
Started Feb 19 03:11:23 PM PST 24
Finished Feb 19 03:11:28 PM PST 24
Peak memory 214236 kb
Host smart-12032685-496e-4417-a23e-0a48693e3176
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2651514839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2651514839
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.599645374
Short name T1020
Test name
Test status
Simulation time 5352029044 ps
CPU time 29.9 seconds
Started Feb 19 03:11:22 PM PST 24
Finished Feb 19 03:11:54 PM PST 24
Peak memory 217416 kb
Host smart-8109f52c-6f7b-46be-91ec-348659658d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599645374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.599645374
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3550801724
Short name T977
Test name
Test status
Simulation time 235871044 ps
CPU time 4.23 seconds
Started Feb 19 03:11:24 PM PST 24
Finished Feb 19 03:11:31 PM PST 24
Peak memory 208792 kb
Host smart-f3103f89-301d-4eaf-bc24-690997ca015d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550801724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3550801724
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.4198886571
Short name T372
Test name
Test status
Simulation time 53938594 ps
CPU time 3.19 seconds
Started Feb 19 03:11:26 PM PST 24
Finished Feb 19 03:11:31 PM PST 24
Peak memory 218212 kb
Host smart-d4688c89-0455-42c2-b7d9-d22e3e25af65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198886571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.4198886571
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3777284447
Short name T331
Test name
Test status
Simulation time 882895263 ps
CPU time 7.94 seconds
Started Feb 19 03:11:26 PM PST 24
Finished Feb 19 03:11:37 PM PST 24
Peak memory 210128 kb
Host smart-6628795f-e938-49f8-a161-c47cc241b9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777284447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3777284447
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3706299122
Short name T599
Test name
Test status
Simulation time 60631027 ps
CPU time 2.97 seconds
Started Feb 19 03:11:22 PM PST 24
Finished Feb 19 03:11:27 PM PST 24
Peak memory 210324 kb
Host smart-00266807-26ee-4a53-a8ea-ab94700bb1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706299122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3706299122
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1770047460
Short name T913
Test name
Test status
Simulation time 270175995 ps
CPU time 3.67 seconds
Started Feb 19 03:11:19 PM PST 24
Finished Feb 19 03:11:25 PM PST 24
Peak memory 207516 kb
Host smart-54c42970-a5cf-44ad-a8e8-5d73cf341335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770047460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1770047460
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.72210820
Short name T254
Test name
Test status
Simulation time 362611548 ps
CPU time 3.61 seconds
Started Feb 19 03:11:17 PM PST 24
Finished Feb 19 03:11:23 PM PST 24
Peak memory 206712 kb
Host smart-cf0e20e6-ee0c-4630-bca4-2451add69fcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72210820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.72210820
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2527466173
Short name T362
Test name
Test status
Simulation time 89721598 ps
CPU time 2.81 seconds
Started Feb 19 03:11:24 PM PST 24
Finished Feb 19 03:11:29 PM PST 24
Peak memory 207004 kb
Host smart-321a2ac4-8420-4266-9c18-0eddd7f8baf5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527466173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2527466173
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.4073914998
Short name T72
Test name
Test status
Simulation time 132406161 ps
CPU time 2.52 seconds
Started Feb 19 03:11:15 PM PST 24
Finished Feb 19 03:11:21 PM PST 24
Peak memory 206868 kb
Host smart-97454e70-e33f-4772-bcaf-1197aaca33ad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073914998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.4073914998
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.917552739
Short name T805
Test name
Test status
Simulation time 3744005592 ps
CPU time 31.35 seconds
Started Feb 19 03:11:24 PM PST 24
Finished Feb 19 03:11:57 PM PST 24
Peak memory 208716 kb
Host smart-9b9cc4ae-a37d-4777-9c06-2e0835d60360
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917552739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.917552739
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2516234053
Short name T725
Test name
Test status
Simulation time 87900798 ps
CPU time 3.08 seconds
Started Feb 19 03:11:22 PM PST 24
Finished Feb 19 03:11:26 PM PST 24
Peak memory 218176 kb
Host smart-9299003a-0663-43fc-b129-390e443d6529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516234053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2516234053
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.4070634417
Short name T786
Test name
Test status
Simulation time 498937280 ps
CPU time 9.02 seconds
Started Feb 19 03:11:23 PM PST 24
Finished Feb 19 03:11:34 PM PST 24
Peak memory 208556 kb
Host smart-841cc996-cf1b-444f-9620-af854b904a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070634417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.4070634417
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.4085294673
Short name T1056
Test name
Test status
Simulation time 537586987 ps
CPU time 16.14 seconds
Started Feb 19 03:11:24 PM PST 24
Finished Feb 19 03:11:42 PM PST 24
Peak memory 222832 kb
Host smart-8c236080-20a8-4a01-afea-b150052f0616
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085294673 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.4085294673
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2587781518
Short name T68
Test name
Test status
Simulation time 318943928 ps
CPU time 9.29 seconds
Started Feb 19 03:11:23 PM PST 24
Finished Feb 19 03:11:35 PM PST 24
Peak memory 210148 kb
Host smart-7ea54507-4370-41e2-b25f-9440b525c499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587781518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2587781518
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.77232207
Short name T872
Test name
Test status
Simulation time 243221675 ps
CPU time 2.49 seconds
Started Feb 19 03:11:21 PM PST 24
Finished Feb 19 03:11:25 PM PST 24
Peak memory 210088 kb
Host smart-d92b2b7f-4ed2-4fa0-acef-9df62384884d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77232207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.77232207
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2871569871
Short name T899
Test name
Test status
Simulation time 9720780 ps
CPU time 0.81 seconds
Started Feb 19 03:09:06 PM PST 24
Finished Feb 19 03:09:08 PM PST 24
Peak memory 205784 kb
Host smart-19a06bbe-517a-46cb-aca3-ef19e66f6ecf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871569871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2871569871
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.704766317
Short name T936
Test name
Test status
Simulation time 53691293 ps
CPU time 3.56 seconds
Started Feb 19 03:08:59 PM PST 24
Finished Feb 19 03:09:08 PM PST 24
Peak memory 214432 kb
Host smart-f4dd6126-dfa6-4743-b5f7-f31d36fbebb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=704766317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.704766317
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.383333697
Short name T944
Test name
Test status
Simulation time 130090290 ps
CPU time 1.87 seconds
Started Feb 19 03:08:59 PM PST 24
Finished Feb 19 03:09:06 PM PST 24
Peak memory 208252 kb
Host smart-5f72541a-371b-42b3-88d7-20c45e8efa29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383333697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.383333697
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.15296712
Short name T89
Test name
Test status
Simulation time 187859410 ps
CPU time 4.38 seconds
Started Feb 19 03:08:59 PM PST 24
Finished Feb 19 03:09:09 PM PST 24
Peak memory 208404 kb
Host smart-4351a887-d292-417b-8332-c8a66d4740b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15296712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.15296712
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2162783147
Short name T360
Test name
Test status
Simulation time 795415747 ps
CPU time 5.79 seconds
Started Feb 19 03:08:58 PM PST 24
Finished Feb 19 03:09:08 PM PST 24
Peak memory 210056 kb
Host smart-a6ac704b-5f34-4da9-bcde-38ad66700e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162783147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2162783147
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.631888242
Short name T938
Test name
Test status
Simulation time 5197890606 ps
CPU time 86.8 seconds
Started Feb 19 03:08:54 PM PST 24
Finished Feb 19 03:10:23 PM PST 24
Peak memory 218568 kb
Host smart-0b768934-de48-4fd3-8d34-27fa1acdb0b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631888242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.631888242
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3242424864
Short name T11
Test name
Test status
Simulation time 8193142136 ps
CPU time 91.66 seconds
Started Feb 19 03:09:08 PM PST 24
Finished Feb 19 03:10:43 PM PST 24
Peak memory 252528 kb
Host smart-50aa5949-f9a1-48f6-b510-42367702af49
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242424864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3242424864
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.137973036
Short name T963
Test name
Test status
Simulation time 85773103 ps
CPU time 3.12 seconds
Started Feb 19 03:08:54 PM PST 24
Finished Feb 19 03:08:59 PM PST 24
Peak memory 206708 kb
Host smart-10f4921f-5c83-4835-9d2a-2b0f3f31ec7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137973036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.137973036
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2736124011
Short name T1016
Test name
Test status
Simulation time 198419176 ps
CPU time 3.92 seconds
Started Feb 19 03:08:53 PM PST 24
Finished Feb 19 03:09:00 PM PST 24
Peak memory 208592 kb
Host smart-eb68156c-eb67-41a6-9f8c-71608808dedb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736124011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2736124011
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.774478535
Short name T596
Test name
Test status
Simulation time 130161634 ps
CPU time 2.49 seconds
Started Feb 19 03:08:52 PM PST 24
Finished Feb 19 03:08:57 PM PST 24
Peak memory 207372 kb
Host smart-fc1a1288-e069-4fd2-8100-d0e2a526f355
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774478535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.774478535
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3046841018
Short name T902
Test name
Test status
Simulation time 3187605549 ps
CPU time 24.61 seconds
Started Feb 19 03:08:57 PM PST 24
Finished Feb 19 03:09:23 PM PST 24
Peak memory 208124 kb
Host smart-0062744b-9e32-4085-a5d7-1d2caf4723e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046841018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3046841018
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.4290093346
Short name T312
Test name
Test status
Simulation time 345092829 ps
CPU time 3.85 seconds
Started Feb 19 03:09:00 PM PST 24
Finished Feb 19 03:09:08 PM PST 24
Peak memory 210360 kb
Host smart-a5572648-9517-498c-be86-561be4c68813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290093346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.4290093346
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.84495740
Short name T996
Test name
Test status
Simulation time 127490566 ps
CPU time 2.25 seconds
Started Feb 19 03:08:55 PM PST 24
Finished Feb 19 03:08:59 PM PST 24
Peak memory 208568 kb
Host smart-664da7bf-e5de-42c9-97f8-6fa612174bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84495740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.84495740
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.834124932
Short name T687
Test name
Test status
Simulation time 167763481 ps
CPU time 5.87 seconds
Started Feb 19 03:09:00 PM PST 24
Finished Feb 19 03:09:10 PM PST 24
Peak memory 214284 kb
Host smart-d50f499e-2efd-40b7-92c6-25b6ebd1fb76
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834124932 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.834124932
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3575111984
Short name T297
Test name
Test status
Simulation time 211208270 ps
CPU time 8.09 seconds
Started Feb 19 03:08:59 PM PST 24
Finished Feb 19 03:09:12 PM PST 24
Peak memory 207448 kb
Host smart-87beb3f2-aebc-40bf-a983-e750e1625c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575111984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3575111984
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3798982099
Short name T389
Test name
Test status
Simulation time 37310838 ps
CPU time 2.04 seconds
Started Feb 19 03:09:06 PM PST 24
Finished Feb 19 03:09:10 PM PST 24
Peak memory 209972 kb
Host smart-8d172118-4ce1-492d-a0a0-1a452f2f9591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798982099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3798982099
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2208005330
Short name T1023
Test name
Test status
Simulation time 49817762 ps
CPU time 0.77 seconds
Started Feb 19 03:11:25 PM PST 24
Finished Feb 19 03:11:28 PM PST 24
Peak memory 205876 kb
Host smart-6068cefd-9d8e-4542-bb70-27681f49af56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208005330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2208005330
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3409567922
Short name T290
Test name
Test status
Simulation time 537676279 ps
CPU time 6.24 seconds
Started Feb 19 03:11:22 PM PST 24
Finished Feb 19 03:11:30 PM PST 24
Peak memory 222472 kb
Host smart-649e35c3-d079-47c2-ab5e-b164c0dbb2f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3409567922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3409567922
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2682944548
Short name T194
Test name
Test status
Simulation time 411867514 ps
CPU time 4.48 seconds
Started Feb 19 03:11:23 PM PST 24
Finished Feb 19 03:11:30 PM PST 24
Peak memory 222808 kb
Host smart-3cda4e43-a64f-4b49-bb1c-1d4e168106bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682944548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2682944548
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.756041303
Short name T769
Test name
Test status
Simulation time 28356972 ps
CPU time 1.95 seconds
Started Feb 19 03:11:23 PM PST 24
Finished Feb 19 03:11:27 PM PST 24
Peak memory 207516 kb
Host smart-c8ce4668-214a-464a-9520-391145281cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756041303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.756041303
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.589041790
Short name T77
Test name
Test status
Simulation time 1756900620 ps
CPU time 10.43 seconds
Started Feb 19 03:11:21 PM PST 24
Finished Feb 19 03:11:33 PM PST 24
Peak memory 208580 kb
Host smart-fcf96201-7eb5-4243-8fe6-0ca1f94c6706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589041790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.589041790
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2547832633
Short name T24
Test name
Test status
Simulation time 134475566 ps
CPU time 6.35 seconds
Started Feb 19 03:11:26 PM PST 24
Finished Feb 19 03:11:34 PM PST 24
Peak memory 210392 kb
Host smart-159893e3-5f8a-4d00-a70d-03fec831899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547832633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2547832633
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3162703981
Short name T724
Test name
Test status
Simulation time 96857823 ps
CPU time 4.53 seconds
Started Feb 19 03:11:27 PM PST 24
Finished Feb 19 03:11:34 PM PST 24
Peak memory 209656 kb
Host smart-7d257ccf-5a6f-4e41-9ce7-71f65c5c1d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162703981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3162703981
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1557367645
Short name T823
Test name
Test status
Simulation time 48389848 ps
CPU time 2.76 seconds
Started Feb 19 03:11:19 PM PST 24
Finished Feb 19 03:11:24 PM PST 24
Peak memory 206888 kb
Host smart-c842be89-de2b-417b-a13c-6d5d9f41a756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557367645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1557367645
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2337890429
Short name T860
Test name
Test status
Simulation time 353419396 ps
CPU time 4.66 seconds
Started Feb 19 03:11:22 PM PST 24
Finished Feb 19 03:11:28 PM PST 24
Peak memory 208500 kb
Host smart-a88e1eea-48a5-4bf1-bc49-edf1f4067ff9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337890429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2337890429
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.60980136
Short name T729
Test name
Test status
Simulation time 236379369 ps
CPU time 3.2 seconds
Started Feb 19 03:11:26 PM PST 24
Finished Feb 19 03:11:31 PM PST 24
Peak memory 206668 kb
Host smart-a13e5da2-0d65-42b0-bbe0-d46a23b50fd0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60980136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.60980136
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3546672010
Short name T897
Test name
Test status
Simulation time 65061529 ps
CPU time 3.16 seconds
Started Feb 19 03:11:27 PM PST 24
Finished Feb 19 03:11:32 PM PST 24
Peak memory 207088 kb
Host smart-9408a0bc-91bc-4eb2-94c7-0d7964235f75
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546672010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3546672010
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.511932610
Short name T1013
Test name
Test status
Simulation time 269068216 ps
CPU time 1.92 seconds
Started Feb 19 03:11:26 PM PST 24
Finished Feb 19 03:11:31 PM PST 24
Peak memory 209072 kb
Host smart-789ea5b9-4ea9-44a6-bd55-71b80413c3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511932610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.511932610
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3193032329
Short name T919
Test name
Test status
Simulation time 30047506 ps
CPU time 2.09 seconds
Started Feb 19 03:11:25 PM PST 24
Finished Feb 19 03:11:30 PM PST 24
Peak memory 206780 kb
Host smart-805e791c-9f2a-42f1-8277-e555babd06f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193032329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3193032329
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.890994819
Short name T695
Test name
Test status
Simulation time 1274412278 ps
CPU time 13.69 seconds
Started Feb 19 03:11:24 PM PST 24
Finished Feb 19 03:11:40 PM PST 24
Peak memory 208748 kb
Host smart-1e74faff-4481-49b6-8658-b774610d5d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890994819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.890994819
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1947108881
Short name T145
Test name
Test status
Simulation time 307700116 ps
CPU time 2.45 seconds
Started Feb 19 03:11:28 PM PST 24
Finished Feb 19 03:11:34 PM PST 24
Peak memory 210784 kb
Host smart-195921ff-e4b9-4770-9bcc-cd09a7f93dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947108881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1947108881
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2236644519
Short name T411
Test name
Test status
Simulation time 346615617 ps
CPU time 2.78 seconds
Started Feb 19 03:11:24 PM PST 24
Finished Feb 19 03:11:30 PM PST 24
Peak memory 222480 kb
Host smart-ed1193aa-7c1b-4c3d-a51e-0b7410d9bf59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2236644519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2236644519
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1874939917
Short name T66
Test name
Test status
Simulation time 306634345 ps
CPU time 4.9 seconds
Started Feb 19 03:11:24 PM PST 24
Finished Feb 19 03:11:32 PM PST 24
Peak memory 208424 kb
Host smart-6812ba41-7789-40cd-af26-9f0283e329a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874939917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1874939917
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1528083720
Short name T854
Test name
Test status
Simulation time 2501715702 ps
CPU time 9.25 seconds
Started Feb 19 03:11:24 PM PST 24
Finished Feb 19 03:11:35 PM PST 24
Peak memory 214352 kb
Host smart-1b2bc7be-177a-4aa1-b04c-5b168e026e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528083720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1528083720
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2386460832
Short name T54
Test name
Test status
Simulation time 1673973699 ps
CPU time 31.77 seconds
Started Feb 19 03:11:24 PM PST 24
Finished Feb 19 03:11:57 PM PST 24
Peak memory 214200 kb
Host smart-bff85de6-84b3-4e38-a27f-19b4d36bd791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386460832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2386460832
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2251222786
Short name T190
Test name
Test status
Simulation time 80953529 ps
CPU time 4.25 seconds
Started Feb 19 03:11:25 PM PST 24
Finished Feb 19 03:11:32 PM PST 24
Peak memory 220432 kb
Host smart-6489f77d-3326-441a-ba36-0a0a791b815e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251222786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2251222786
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2727007612
Short name T961
Test name
Test status
Simulation time 6188266873 ps
CPU time 38.7 seconds
Started Feb 19 03:11:25 PM PST 24
Finished Feb 19 03:12:06 PM PST 24
Peak memory 210620 kb
Host smart-e6ddaa91-23db-4ee8-a21d-6348e10c8462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727007612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2727007612
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2150641761
Short name T752
Test name
Test status
Simulation time 71421480 ps
CPU time 2.48 seconds
Started Feb 19 03:11:27 PM PST 24
Finished Feb 19 03:11:32 PM PST 24
Peak memory 206712 kb
Host smart-077ed9c7-b3e3-4f26-9936-a6697fd18590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150641761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2150641761
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2187197554
Short name T801
Test name
Test status
Simulation time 113497186 ps
CPU time 3.74 seconds
Started Feb 19 03:11:24 PM PST 24
Finished Feb 19 03:11:30 PM PST 24
Peak memory 206780 kb
Host smart-11920171-8a48-4e56-be2f-f39eb5b8ba1c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187197554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2187197554
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.230379151
Short name T1039
Test name
Test status
Simulation time 305268477 ps
CPU time 4.15 seconds
Started Feb 19 03:11:23 PM PST 24
Finished Feb 19 03:11:29 PM PST 24
Peak memory 206884 kb
Host smart-31af8962-1ea2-4a81-bec7-bdd71fc7e67a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230379151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.230379151
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3530029294
Short name T871
Test name
Test status
Simulation time 81398805 ps
CPU time 2.87 seconds
Started Feb 19 03:11:26 PM PST 24
Finished Feb 19 03:11:32 PM PST 24
Peak memory 209396 kb
Host smart-2b2cb348-5229-4f81-8b4a-889418566300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530029294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3530029294
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3473144087
Short name T815
Test name
Test status
Simulation time 223682219 ps
CPU time 7.72 seconds
Started Feb 19 03:11:30 PM PST 24
Finished Feb 19 03:11:40 PM PST 24
Peak memory 208404 kb
Host smart-11d9a6d8-e9c4-445b-8534-11f4b1e31a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473144087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3473144087
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2786451987
Short name T806
Test name
Test status
Simulation time 635352643 ps
CPU time 7.95 seconds
Started Feb 19 03:11:28 PM PST 24
Finished Feb 19 03:11:38 PM PST 24
Peak memory 219468 kb
Host smart-3247541b-314c-4a2c-82a5-94718d73d40c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786451987 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2786451987
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1699895338
Short name T167
Test name
Test status
Simulation time 1039922198 ps
CPU time 21.45 seconds
Started Feb 19 03:11:23 PM PST 24
Finished Feb 19 03:11:47 PM PST 24
Peak memory 209072 kb
Host smart-c5ffff36-2dd0-44ea-9c1f-6f89ebba16a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699895338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1699895338
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.663590350
Short name T894
Test name
Test status
Simulation time 55760885 ps
CPU time 2.96 seconds
Started Feb 19 03:11:26 PM PST 24
Finished Feb 19 03:11:32 PM PST 24
Peak memory 210288 kb
Host smart-940c93af-e737-438b-8bfd-a2ad10217d2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663590350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.663590350
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2482037534
Short name T90
Test name
Test status
Simulation time 169741251 ps
CPU time 0.93 seconds
Started Feb 19 03:11:36 PM PST 24
Finished Feb 19 03:11:42 PM PST 24
Peak memory 205872 kb
Host smart-4573b601-9d5d-49fa-b306-855aec7460e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482037534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2482037534
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2744853716
Short name T407
Test name
Test status
Simulation time 253681135 ps
CPU time 3.89 seconds
Started Feb 19 03:11:29 PM PST 24
Finished Feb 19 03:11:35 PM PST 24
Peak memory 214320 kb
Host smart-0d9b1e14-f9a8-4ed2-8cc1-9a9f68759fcf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2744853716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2744853716
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2835838552
Short name T20
Test name
Test status
Simulation time 252308053 ps
CPU time 3.93 seconds
Started Feb 19 03:11:36 PM PST 24
Finished Feb 19 03:11:45 PM PST 24
Peak memory 214484 kb
Host smart-80a20ab7-7734-4681-9564-0a809ca5bcf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835838552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2835838552
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2733598086
Short name T280
Test name
Test status
Simulation time 38697301 ps
CPU time 2.05 seconds
Started Feb 19 03:11:36 PM PST 24
Finished Feb 19 03:11:43 PM PST 24
Peak memory 209712 kb
Host smart-d0cd36f2-5127-47c7-9fbb-408b3f26f16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733598086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2733598086
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.665944013
Short name T25
Test name
Test status
Simulation time 2305636566 ps
CPU time 72.58 seconds
Started Feb 19 03:11:28 PM PST 24
Finished Feb 19 03:12:43 PM PST 24
Peak memory 214380 kb
Host smart-08a54fb7-4122-4905-a70f-28e301e86326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665944013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.665944013
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3533109980
Short name T268
Test name
Test status
Simulation time 323956389 ps
CPU time 5.86 seconds
Started Feb 19 03:11:31 PM PST 24
Finished Feb 19 03:11:40 PM PST 24
Peak memory 214268 kb
Host smart-812de13f-0ed2-46fd-864e-6be5dfdb088f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533109980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3533109980
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1181828114
Short name T804
Test name
Test status
Simulation time 128395262 ps
CPU time 3.34 seconds
Started Feb 19 03:11:29 PM PST 24
Finished Feb 19 03:11:35 PM PST 24
Peak memory 209752 kb
Host smart-a66047a9-c76f-4cb7-bece-336bcefd5191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181828114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1181828114
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1392191073
Short name T166
Test name
Test status
Simulation time 2653609364 ps
CPU time 64 seconds
Started Feb 19 03:11:29 PM PST 24
Finished Feb 19 03:12:35 PM PST 24
Peak memory 209256 kb
Host smart-73786999-ff6c-481c-9988-48aa32fd4ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392191073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1392191073
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.4242094237
Short name T616
Test name
Test status
Simulation time 4078961853 ps
CPU time 17.61 seconds
Started Feb 19 03:11:30 PM PST 24
Finished Feb 19 03:11:50 PM PST 24
Peak memory 208104 kb
Host smart-3ab1e955-c23b-49b9-b92f-5500e1b78b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242094237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.4242094237
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3400840108
Short name T279
Test name
Test status
Simulation time 499069325 ps
CPU time 10.75 seconds
Started Feb 19 03:11:31 PM PST 24
Finished Feb 19 03:11:44 PM PST 24
Peak memory 208704 kb
Host smart-2cef2d50-b48f-4160-ba59-e4adc7e6ae56
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400840108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3400840108
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3687909740
Short name T639
Test name
Test status
Simulation time 54540575 ps
CPU time 2.94 seconds
Started Feb 19 03:11:26 PM PST 24
Finished Feb 19 03:11:32 PM PST 24
Peak memory 206932 kb
Host smart-59f3de2d-ebd6-48f3-a6fb-4cfb12403bf8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687909740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3687909740
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.606699898
Short name T567
Test name
Test status
Simulation time 278743481 ps
CPU time 6.61 seconds
Started Feb 19 03:11:28 PM PST 24
Finished Feb 19 03:11:38 PM PST 24
Peak memory 207016 kb
Host smart-da4e7f8b-89e3-45f5-964e-0487db402292
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606699898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.606699898
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2754544643
Short name T910
Test name
Test status
Simulation time 45758127 ps
CPU time 3.23 seconds
Started Feb 19 03:11:30 PM PST 24
Finished Feb 19 03:11:35 PM PST 24
Peak memory 214336 kb
Host smart-7f27b925-1142-4a7f-880a-06f8f48d2132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754544643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2754544643
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2951162518
Short name T679
Test name
Test status
Simulation time 115886205 ps
CPU time 4.89 seconds
Started Feb 19 03:11:26 PM PST 24
Finished Feb 19 03:11:33 PM PST 24
Peak memory 208728 kb
Host smart-fd531a05-6839-472d-ad2d-3108094cef7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951162518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2951162518
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.775902586
Short name T51
Test name
Test status
Simulation time 24210170721 ps
CPU time 467.09 seconds
Started Feb 19 03:11:32 PM PST 24
Finished Feb 19 03:19:23 PM PST 24
Peak memory 222476 kb
Host smart-12179ad9-67f6-4455-b553-29b8ac3a1d57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775902586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.775902586
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2875568486
Short name T792
Test name
Test status
Simulation time 123237996 ps
CPU time 5.15 seconds
Started Feb 19 03:11:35 PM PST 24
Finished Feb 19 03:11:46 PM PST 24
Peak memory 207336 kb
Host smart-471a66f4-b558-483e-be6d-9248dce02e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875568486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2875568486
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1163998789
Short name T1055
Test name
Test status
Simulation time 164736307 ps
CPU time 2.62 seconds
Started Feb 19 03:11:28 PM PST 24
Finished Feb 19 03:11:33 PM PST 24
Peak memory 210444 kb
Host smart-0d5a0094-7de5-448a-a13d-1ddcb8c75b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163998789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1163998789
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3050875670
Short name T888
Test name
Test status
Simulation time 27898587 ps
CPU time 0.94 seconds
Started Feb 19 03:11:52 PM PST 24
Finished Feb 19 03:11:55 PM PST 24
Peak memory 206224 kb
Host smart-5ab80f38-512e-423c-b0db-7ab50ee24213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050875670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3050875670
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1418981407
Short name T393
Test name
Test status
Simulation time 3093195482 ps
CPU time 85.78 seconds
Started Feb 19 03:11:38 PM PST 24
Finished Feb 19 03:13:08 PM PST 24
Peak memory 215976 kb
Host smart-aa27da5a-75dd-4056-9d05-53ac90ef8a88
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418981407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1418981407
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.105618068
Short name T641
Test name
Test status
Simulation time 172974017 ps
CPU time 6.86 seconds
Started Feb 19 03:11:38 PM PST 24
Finished Feb 19 03:11:49 PM PST 24
Peak memory 222708 kb
Host smart-70a4023e-e905-4cf7-8586-97d68d2fc501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105618068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.105618068
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2322908994
Short name T57
Test name
Test status
Simulation time 109975196 ps
CPU time 3.2 seconds
Started Feb 19 03:11:34 PM PST 24
Finished Feb 19 03:11:42 PM PST 24
Peak memory 210472 kb
Host smart-2879286b-f2f7-4a9e-8372-6f0045f45119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322908994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2322908994
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1632839735
Short name T1006
Test name
Test status
Simulation time 39318343 ps
CPU time 2.2 seconds
Started Feb 19 03:11:38 PM PST 24
Finished Feb 19 03:11:44 PM PST 24
Peak memory 210052 kb
Host smart-b9d58b35-f579-4abd-9491-d13e4da862b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632839735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1632839735
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1780338863
Short name T845
Test name
Test status
Simulation time 208428628 ps
CPU time 8.86 seconds
Started Feb 19 03:11:38 PM PST 24
Finished Feb 19 03:11:51 PM PST 24
Peak memory 222356 kb
Host smart-c7932e2a-5b08-4dd4-9634-e701e323ce64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780338863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1780338863
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3903719599
Short name T920
Test name
Test status
Simulation time 228590462 ps
CPU time 3.14 seconds
Started Feb 19 03:11:35 PM PST 24
Finished Feb 19 03:11:43 PM PST 24
Peak memory 210268 kb
Host smart-a4f71436-58e0-475f-b423-8df00d82f1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903719599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3903719599
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_sideload.143012033
Short name T891
Test name
Test status
Simulation time 139666662 ps
CPU time 5.32 seconds
Started Feb 19 03:11:34 PM PST 24
Finished Feb 19 03:11:44 PM PST 24
Peak memory 206812 kb
Host smart-f8ba0b51-2a99-4516-8915-39ea6c727bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143012033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.143012033
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3201453519
Short name T377
Test name
Test status
Simulation time 120390698 ps
CPU time 4.4 seconds
Started Feb 19 03:11:34 PM PST 24
Finished Feb 19 03:11:43 PM PST 24
Peak memory 208648 kb
Host smart-e9c0a341-5dba-4f01-be36-33d0fd952faa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201453519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3201453519
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.970250018
Short name T1005
Test name
Test status
Simulation time 48297310 ps
CPU time 2.12 seconds
Started Feb 19 03:11:36 PM PST 24
Finished Feb 19 03:11:43 PM PST 24
Peak memory 208448 kb
Host smart-c1b0ba53-d4d4-43e2-ba3e-6e4ac25a2c31
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970250018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.970250018
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2187820856
Short name T1015
Test name
Test status
Simulation time 72220378 ps
CPU time 3.55 seconds
Started Feb 19 03:11:33 PM PST 24
Finished Feb 19 03:11:40 PM PST 24
Peak memory 208476 kb
Host smart-eadd361c-cb59-4a79-8678-4d50629e2a56
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187820856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2187820856
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2464680607
Short name T669
Test name
Test status
Simulation time 105469142 ps
CPU time 3.64 seconds
Started Feb 19 03:11:37 PM PST 24
Finished Feb 19 03:11:45 PM PST 24
Peak memory 214304 kb
Host smart-1969dbe5-0700-4dd9-bf2b-16fd1460fbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464680607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2464680607
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3752185085
Short name T678
Test name
Test status
Simulation time 63439112 ps
CPU time 2.95 seconds
Started Feb 19 03:11:41 PM PST 24
Finished Feb 19 03:11:46 PM PST 24
Peak memory 208400 kb
Host smart-d7c61a92-c0b2-4ca0-bdbf-13673d59ef28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752185085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3752185085
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.1808315760
Short name T353
Test name
Test status
Simulation time 57945298 ps
CPU time 4.43 seconds
Started Feb 19 03:11:47 PM PST 24
Finished Feb 19 03:11:53 PM PST 24
Peak memory 218496 kb
Host smart-0c5693f8-bb47-4c2f-8309-f32998c99e45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808315760 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.1808315760
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2486251830
Short name T223
Test name
Test status
Simulation time 578883095 ps
CPU time 8.39 seconds
Started Feb 19 03:11:37 PM PST 24
Finished Feb 19 03:11:50 PM PST 24
Peak memory 208836 kb
Host smart-1098b1de-544d-4916-8542-0eb88882d98d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486251830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2486251830
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3444272450
Short name T637
Test name
Test status
Simulation time 4671656723 ps
CPU time 27.78 seconds
Started Feb 19 03:11:39 PM PST 24
Finished Feb 19 03:12:10 PM PST 24
Peak memory 211672 kb
Host smart-af1099da-6fb7-4df0-8af2-a23f4c4d402a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444272450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3444272450
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1926859178
Short name T1037
Test name
Test status
Simulation time 11773538 ps
CPU time 0.89 seconds
Started Feb 19 03:11:53 PM PST 24
Finished Feb 19 03:11:57 PM PST 24
Peak memory 205796 kb
Host smart-5c7d9c24-ca06-415e-be87-1664704a878d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926859178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1926859178
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1052068531
Short name T397
Test name
Test status
Simulation time 915570621 ps
CPU time 48.44 seconds
Started Feb 19 03:11:52 PM PST 24
Finished Feb 19 03:12:42 PM PST 24
Peak memory 215152 kb
Host smart-b8149f9c-06cf-4d6c-ad76-3cd1da6dd93c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1052068531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1052068531
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2462444627
Short name T14
Test name
Test status
Simulation time 524081942 ps
CPU time 3.13 seconds
Started Feb 19 03:11:52 PM PST 24
Finished Feb 19 03:11:57 PM PST 24
Peak memory 209808 kb
Host smart-5ef81176-c4c9-42de-bfb6-9472a4cb4a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462444627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2462444627
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.699643128
Short name T614
Test name
Test status
Simulation time 145609841 ps
CPU time 3.54 seconds
Started Feb 19 03:11:45 PM PST 24
Finished Feb 19 03:11:51 PM PST 24
Peak memory 209196 kb
Host smart-6a3b27ae-53ae-42b0-a61c-1863ef51b0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699643128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.699643128
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1287566833
Short name T307
Test name
Test status
Simulation time 591637908 ps
CPU time 5.25 seconds
Started Feb 19 03:11:52 PM PST 24
Finished Feb 19 03:12:01 PM PST 24
Peak memory 211548 kb
Host smart-90c597ed-baa8-40f8-b1a1-3bcdcf0fea5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287566833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1287566833
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.486536866
Short name T561
Test name
Test status
Simulation time 82343129 ps
CPU time 2.01 seconds
Started Feb 19 03:11:50 PM PST 24
Finished Feb 19 03:11:54 PM PST 24
Peak memory 206120 kb
Host smart-ee4d74bf-163c-42d7-ad38-ca48e4d42f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486536866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.486536866
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2920552977
Short name T773
Test name
Test status
Simulation time 2143836793 ps
CPU time 15.87 seconds
Started Feb 19 03:11:52 PM PST 24
Finished Feb 19 03:12:11 PM PST 24
Peak memory 208892 kb
Host smart-c3c08061-7ff5-4695-b0e7-985e3cba7786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920552977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2920552977
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2203532582
Short name T940
Test name
Test status
Simulation time 155295220 ps
CPU time 3.63 seconds
Started Feb 19 03:11:44 PM PST 24
Finished Feb 19 03:11:49 PM PST 24
Peak memory 208732 kb
Host smart-febbdb70-9c0a-4f9f-855d-8d4ae3533238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203532582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2203532582
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1432467644
Short name T126
Test name
Test status
Simulation time 198520604 ps
CPU time 5.44 seconds
Started Feb 19 03:11:49 PM PST 24
Finished Feb 19 03:11:57 PM PST 24
Peak memory 208600 kb
Host smart-1a7088da-474a-44a7-8b92-5d00b15bb69b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432467644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1432467644
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3076133977
Short name T378
Test name
Test status
Simulation time 2642663071 ps
CPU time 10.21 seconds
Started Feb 19 03:11:52 PM PST 24
Finished Feb 19 03:12:05 PM PST 24
Peak memory 206972 kb
Host smart-9fe95a6c-67e5-4f55-8e1b-ed6f4d487587
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076133977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3076133977
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1791146729
Short name T719
Test name
Test status
Simulation time 1203480458 ps
CPU time 8.25 seconds
Started Feb 19 03:11:49 PM PST 24
Finished Feb 19 03:12:00 PM PST 24
Peak memory 208872 kb
Host smart-adb5f485-58b7-456f-9ff0-4e334e9f3979
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791146729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1791146729
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.4180149832
Short name T376
Test name
Test status
Simulation time 1614330294 ps
CPU time 4.03 seconds
Started Feb 19 03:11:50 PM PST 24
Finished Feb 19 03:11:56 PM PST 24
Peak memory 208612 kb
Host smart-98a6c754-7155-496f-959d-d050ed768fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180149832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.4180149832
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1542088281
Short name T988
Test name
Test status
Simulation time 149342671 ps
CPU time 2.72 seconds
Started Feb 19 03:11:49 PM PST 24
Finished Feb 19 03:11:55 PM PST 24
Peak memory 208832 kb
Host smart-465825c5-fe74-49f1-a301-c9759cfd4b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542088281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1542088281
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1267618619
Short name T328
Test name
Test status
Simulation time 493965669 ps
CPU time 6.25 seconds
Started Feb 19 03:11:49 PM PST 24
Finished Feb 19 03:11:58 PM PST 24
Peak memory 222500 kb
Host smart-b4cfbbb8-16e2-4d36-bf13-d0c3ec604b67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267618619 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1267618619
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3858513833
Short name T236
Test name
Test status
Simulation time 408739801 ps
CPU time 4.75 seconds
Started Feb 19 03:11:51 PM PST 24
Finished Feb 19 03:11:58 PM PST 24
Peak memory 218428 kb
Host smart-fc9917ce-040a-47ac-a82b-0a6b703b256c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858513833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3858513833
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2578103286
Short name T671
Test name
Test status
Simulation time 270831849 ps
CPU time 2.47 seconds
Started Feb 19 03:11:50 PM PST 24
Finished Feb 19 03:11:55 PM PST 24
Peak memory 210612 kb
Host smart-cc5f8980-0d16-4e10-9d45-b4f8070c3b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578103286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2578103286
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3299752003
Short name T597
Test name
Test status
Simulation time 21441992 ps
CPU time 0.99 seconds
Started Feb 19 03:11:52 PM PST 24
Finished Feb 19 03:11:56 PM PST 24
Peak memory 206032 kb
Host smart-cd4b1167-9464-479f-87d8-df7f61b938ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299752003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3299752003
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3796504001
Short name T392
Test name
Test status
Simulation time 4552077443 ps
CPU time 40 seconds
Started Feb 19 03:11:56 PM PST 24
Finished Feb 19 03:12:39 PM PST 24
Peak memory 215088 kb
Host smart-ffa27d35-05eb-413c-8393-ec4d7f2efe29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3796504001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3796504001
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3795871824
Short name T229
Test name
Test status
Simulation time 133942154 ps
CPU time 3.91 seconds
Started Feb 19 03:11:54 PM PST 24
Finished Feb 19 03:12:01 PM PST 24
Peak memory 214672 kb
Host smart-74a37944-315f-4155-bcf4-b46348345110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795871824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3795871824
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2171380611
Short name T612
Test name
Test status
Simulation time 315655476 ps
CPU time 4.76 seconds
Started Feb 19 03:11:56 PM PST 24
Finished Feb 19 03:12:03 PM PST 24
Peak memory 207576 kb
Host smart-4562fb8b-fe57-4149-96d8-fe1fccaf690b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171380611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2171380611
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3753069987
Short name T228
Test name
Test status
Simulation time 111159133 ps
CPU time 5.03 seconds
Started Feb 19 03:11:51 PM PST 24
Finished Feb 19 03:11:59 PM PST 24
Peak memory 220052 kb
Host smart-f42217ba-d3c5-4668-bd5c-802ef2979b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753069987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3753069987
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1425629342
Short name T212
Test name
Test status
Simulation time 309340992 ps
CPU time 3.83 seconds
Started Feb 19 03:11:54 PM PST 24
Finished Feb 19 03:12:00 PM PST 24
Peak memory 211636 kb
Host smart-3203d6c3-93a7-42ad-8d90-4e8b69ce8db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425629342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1425629342
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3106913444
Short name T1041
Test name
Test status
Simulation time 532132899 ps
CPU time 3.1 seconds
Started Feb 19 03:11:50 PM PST 24
Finished Feb 19 03:11:56 PM PST 24
Peak memory 210408 kb
Host smart-7e6d8421-ecf4-460e-bbea-7fcfd4ed9714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106913444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3106913444
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2763331099
Short name T861
Test name
Test status
Simulation time 314765722 ps
CPU time 4.2 seconds
Started Feb 19 03:11:52 PM PST 24
Finished Feb 19 03:11:58 PM PST 24
Peak memory 207816 kb
Host smart-23136250-140b-4c39-a299-750796a39056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763331099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2763331099
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2794396915
Short name T1003
Test name
Test status
Simulation time 92477827 ps
CPU time 3.69 seconds
Started Feb 19 03:11:49 PM PST 24
Finished Feb 19 03:11:56 PM PST 24
Peak memory 206676 kb
Host smart-67d61b74-3f89-4460-9ad0-f7a9ad68b3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794396915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2794396915
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1293978723
Short name T874
Test name
Test status
Simulation time 358859148 ps
CPU time 8.66 seconds
Started Feb 19 03:11:56 PM PST 24
Finished Feb 19 03:12:08 PM PST 24
Peak memory 208556 kb
Host smart-511d469e-c0c7-4196-b06e-5bf2cb11e49a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293978723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1293978723
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1409686080
Short name T552
Test name
Test status
Simulation time 34672393 ps
CPU time 2.43 seconds
Started Feb 19 03:11:52 PM PST 24
Finished Feb 19 03:11:57 PM PST 24
Peak memory 207480 kb
Host smart-a377c5a0-0ba5-4a17-bad8-1e3059e2b554
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409686080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1409686080
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.197597522
Short name T776
Test name
Test status
Simulation time 230176176 ps
CPU time 3.19 seconds
Started Feb 19 03:11:53 PM PST 24
Finished Feb 19 03:11:59 PM PST 24
Peak memory 207156 kb
Host smart-a57ed38e-217b-402d-8086-d320b5846374
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197597522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.197597522
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2375816679
Short name T253
Test name
Test status
Simulation time 1045742095 ps
CPU time 7.53 seconds
Started Feb 19 03:11:56 PM PST 24
Finished Feb 19 03:12:07 PM PST 24
Peak memory 209644 kb
Host smart-60887279-3e27-4b7e-8e6b-bd577630c642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375816679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2375816679
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2128418652
Short name T696
Test name
Test status
Simulation time 88291185 ps
CPU time 2.88 seconds
Started Feb 19 03:11:50 PM PST 24
Finished Feb 19 03:11:56 PM PST 24
Peak memory 207160 kb
Host smart-e61fb522-32f1-414e-9c31-5fa7670ca274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128418652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2128418652
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3015212710
Short name T974
Test name
Test status
Simulation time 11235822275 ps
CPU time 74.04 seconds
Started Feb 19 03:11:52 PM PST 24
Finished Feb 19 03:13:09 PM PST 24
Peak memory 221360 kb
Host smart-930ff886-2a6b-448a-b3b8-7f04cb80d9cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015212710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3015212710
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.409021179
Short name T352
Test name
Test status
Simulation time 234355943 ps
CPU time 5.23 seconds
Started Feb 19 03:11:52 PM PST 24
Finished Feb 19 03:11:59 PM PST 24
Peak memory 214312 kb
Host smart-dbca8a79-e7e4-4bd5-a274-2a7b82fd1fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409021179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.409021179
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.4284709465
Short name T918
Test name
Test status
Simulation time 226589716 ps
CPU time 2.29 seconds
Started Feb 19 03:11:50 PM PST 24
Finished Feb 19 03:11:55 PM PST 24
Peak memory 210348 kb
Host smart-1fe82c7f-6cbb-4b65-9680-2f04efd4a26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284709465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.4284709465
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.4017149168
Short name T740
Test name
Test status
Simulation time 41176266 ps
CPU time 0.85 seconds
Started Feb 19 03:12:00 PM PST 24
Finished Feb 19 03:12:04 PM PST 24
Peak memory 205820 kb
Host smart-06e59ea5-0ff3-4733-b5fa-7ee05d99f793
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017149168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.4017149168
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.234293233
Short name T210
Test name
Test status
Simulation time 40864432 ps
CPU time 2.97 seconds
Started Feb 19 03:11:56 PM PST 24
Finished Feb 19 03:12:02 PM PST 24
Peak memory 215400 kb
Host smart-fb9435fa-4ece-49ac-84b2-66df1d4ca12f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=234293233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.234293233
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1974545426
Short name T789
Test name
Test status
Simulation time 412187239 ps
CPU time 6.27 seconds
Started Feb 19 03:12:00 PM PST 24
Finished Feb 19 03:12:09 PM PST 24
Peak memory 221104 kb
Host smart-ca9a857c-ddf3-4269-b378-a4d39f4b4116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974545426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1974545426
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.323181397
Short name T348
Test name
Test status
Simulation time 292648753 ps
CPU time 3.85 seconds
Started Feb 19 03:11:57 PM PST 24
Finished Feb 19 03:12:04 PM PST 24
Peak memory 218308 kb
Host smart-178dcd7d-75b1-4688-b5fb-7b9902aadc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323181397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.323181397
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.734292541
Short name T287
Test name
Test status
Simulation time 304822424 ps
CPU time 3.81 seconds
Started Feb 19 03:12:01 PM PST 24
Finished Feb 19 03:12:07 PM PST 24
Peak memory 220036 kb
Host smart-bf5c8208-da12-4e47-a922-8d5fe184f849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734292541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.734292541
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1326425820
Short name T330
Test name
Test status
Simulation time 738181516 ps
CPU time 26.92 seconds
Started Feb 19 03:11:59 PM PST 24
Finished Feb 19 03:12:28 PM PST 24
Peak memory 214180 kb
Host smart-27e331fc-66c4-4490-a565-e96ebc67d4e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326425820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1326425820
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3520655555
Short name T569
Test name
Test status
Simulation time 64186408 ps
CPU time 2.08 seconds
Started Feb 19 03:11:59 PM PST 24
Finished Feb 19 03:12:04 PM PST 24
Peak memory 214432 kb
Host smart-440b968d-602d-4922-af38-4c6fbbf0237a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520655555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3520655555
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3558447305
Short name T570
Test name
Test status
Simulation time 38140462 ps
CPU time 2.63 seconds
Started Feb 19 03:12:11 PM PST 24
Finished Feb 19 03:12:17 PM PST 24
Peak memory 214404 kb
Host smart-4bbe7f58-d11b-4069-8012-5b88d47ffb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558447305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3558447305
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1560687038
Short name T550
Test name
Test status
Simulation time 565673552 ps
CPU time 6.63 seconds
Started Feb 19 03:11:54 PM PST 24
Finished Feb 19 03:12:03 PM PST 24
Peak memory 208392 kb
Host smart-5081fd11-09b5-4cac-ba8d-00202f9def8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560687038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1560687038
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3860355650
Short name T604
Test name
Test status
Simulation time 2244789656 ps
CPU time 57.7 seconds
Started Feb 19 03:12:01 PM PST 24
Finished Feb 19 03:13:01 PM PST 24
Peak memory 208092 kb
Host smart-6372c225-d1a6-4d9b-8f18-0baef7fca93f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860355650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3860355650
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3247114464
Short name T1009
Test name
Test status
Simulation time 288911563 ps
CPU time 7.92 seconds
Started Feb 19 03:11:54 PM PST 24
Finished Feb 19 03:12:04 PM PST 24
Peak memory 207856 kb
Host smart-74d2ee63-f5f0-487c-8567-8b8c37739567
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247114464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3247114464
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.541570621
Short name T739
Test name
Test status
Simulation time 608322643 ps
CPU time 10.18 seconds
Started Feb 19 03:11:55 PM PST 24
Finished Feb 19 03:12:08 PM PST 24
Peak memory 209412 kb
Host smart-304a7158-6fa6-4b80-94ee-692ddd9e1671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541570621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.541570621
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.4176535352
Short name T852
Test name
Test status
Simulation time 340894543 ps
CPU time 2.82 seconds
Started Feb 19 03:11:55 PM PST 24
Finished Feb 19 03:12:01 PM PST 24
Peak memory 208720 kb
Host smart-09954bee-f9ac-4d95-93fe-a0ed36fa6a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176535352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.4176535352
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3591669442
Short name T398
Test name
Test status
Simulation time 261298635 ps
CPU time 7.75 seconds
Started Feb 19 03:12:02 PM PST 24
Finished Feb 19 03:12:11 PM PST 24
Peak memory 222560 kb
Host smart-edcc9864-0991-4d61-a0ac-38878e31a0ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591669442 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3591669442
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.224741187
Short name T993
Test name
Test status
Simulation time 138001099 ps
CPU time 3.66 seconds
Started Feb 19 03:11:54 PM PST 24
Finished Feb 19 03:12:00 PM PST 24
Peak memory 207124 kb
Host smart-e4664508-6e98-4cbc-9ff9-e28b94cba22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224741187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.224741187
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1487819376
Short name T49
Test name
Test status
Simulation time 192759961 ps
CPU time 5.39 seconds
Started Feb 19 03:11:54 PM PST 24
Finished Feb 19 03:12:02 PM PST 24
Peak memory 210468 kb
Host smart-1fd90b53-21fb-4049-a197-e868a63a5f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487819376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1487819376
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1071067526
Short name T764
Test name
Test status
Simulation time 134481231 ps
CPU time 0.78 seconds
Started Feb 19 03:12:09 PM PST 24
Finished Feb 19 03:12:12 PM PST 24
Peak memory 205876 kb
Host smart-77ea3144-1f29-4499-b104-f18cc29c0a41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071067526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1071067526
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3242158681
Short name T22
Test name
Test status
Simulation time 35392234 ps
CPU time 1.47 seconds
Started Feb 19 03:12:12 PM PST 24
Finished Feb 19 03:12:17 PM PST 24
Peak memory 209832 kb
Host smart-b4fa7bcb-e13b-434b-b40d-fed890e07110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242158681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3242158681
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2327138759
Short name T717
Test name
Test status
Simulation time 245886321 ps
CPU time 2.43 seconds
Started Feb 19 03:12:00 PM PST 24
Finished Feb 19 03:12:05 PM PST 24
Peak memory 218504 kb
Host smart-98eecbd1-c3ea-4129-b392-29b6119c006e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327138759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2327138759
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.235026275
Short name T226
Test name
Test status
Simulation time 140307733 ps
CPU time 6.79 seconds
Started Feb 19 03:12:12 PM PST 24
Finished Feb 19 03:12:22 PM PST 24
Peak memory 210628 kb
Host smart-00c854bc-76a0-43a1-86ad-0b4d321e4b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235026275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.235026275
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2179412919
Short name T605
Test name
Test status
Simulation time 91364741 ps
CPU time 3.18 seconds
Started Feb 19 03:12:07 PM PST 24
Finished Feb 19 03:12:12 PM PST 24
Peak memory 219624 kb
Host smart-a89fee21-2797-4a0f-9eb8-bab1e50382c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179412919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2179412919
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.775203711
Short name T948
Test name
Test status
Simulation time 227242421 ps
CPU time 4.24 seconds
Started Feb 19 03:12:03 PM PST 24
Finished Feb 19 03:12:09 PM PST 24
Peak memory 218324 kb
Host smart-473f64ac-291c-44c2-9068-691171b0973e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775203711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.775203711
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2247004570
Short name T674
Test name
Test status
Simulation time 196132182 ps
CPU time 2.88 seconds
Started Feb 19 03:12:01 PM PST 24
Finished Feb 19 03:12:06 PM PST 24
Peak memory 206804 kb
Host smart-ab9d1d81-041f-42a6-9bf7-6310461b7bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247004570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2247004570
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1467403109
Short name T320
Test name
Test status
Simulation time 1415354792 ps
CPU time 35.12 seconds
Started Feb 19 03:12:11 PM PST 24
Finished Feb 19 03:12:49 PM PST 24
Peak memory 208524 kb
Host smart-63384593-d247-476f-b5f5-528a50430462
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467403109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1467403109
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1310284161
Short name T233
Test name
Test status
Simulation time 251560223 ps
CPU time 3.72 seconds
Started Feb 19 03:12:03 PM PST 24
Finished Feb 19 03:12:09 PM PST 24
Peak memory 208852 kb
Host smart-c968223e-a0b8-4fd3-a207-9c01d331eb35
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310284161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1310284161
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2501576705
Short name T649
Test name
Test status
Simulation time 257003962 ps
CPU time 9.84 seconds
Started Feb 19 03:12:11 PM PST 24
Finished Feb 19 03:12:24 PM PST 24
Peak memory 207908 kb
Host smart-7b478e49-4c9a-47ce-bf11-88f89ddba43d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501576705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2501576705
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2354549157
Short name T283
Test name
Test status
Simulation time 64391164 ps
CPU time 3.68 seconds
Started Feb 19 03:12:11 PM PST 24
Finished Feb 19 03:12:18 PM PST 24
Peak memory 218408 kb
Host smart-9a2e530b-beb4-469b-842a-907c01e77834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354549157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2354549157
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1016095010
Short name T839
Test name
Test status
Simulation time 198926580 ps
CPU time 5.99 seconds
Started Feb 19 03:12:03 PM PST 24
Finished Feb 19 03:12:12 PM PST 24
Peak memory 207956 kb
Host smart-c0b9ca11-300f-4931-92a5-5c9388691eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016095010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1016095010
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1606430
Short name T997
Test name
Test status
Simulation time 2299177570 ps
CPU time 27.95 seconds
Started Feb 19 03:12:02 PM PST 24
Finished Feb 19 03:12:32 PM PST 24
Peak memory 222484 kb
Host smart-1aa38626-077b-41f2-85c1-66f020b2fa9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1606430
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1282752010
Short name T271
Test name
Test status
Simulation time 168185315 ps
CPU time 5.17 seconds
Started Feb 19 03:12:10 PM PST 24
Finished Feb 19 03:12:19 PM PST 24
Peak memory 222668 kb
Host smart-b31e481e-535a-444b-88c8-2a1c2e02fdad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282752010 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1282752010
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.302175067
Short name T258
Test name
Test status
Simulation time 374428659 ps
CPU time 4.09 seconds
Started Feb 19 03:12:02 PM PST 24
Finished Feb 19 03:12:08 PM PST 24
Peak memory 209232 kb
Host smart-2b84cf2e-ff54-4f75-8473-f06a465f254d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302175067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.302175067
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1020662018
Short name T664
Test name
Test status
Simulation time 78451897 ps
CPU time 3.45 seconds
Started Feb 19 03:12:02 PM PST 24
Finished Feb 19 03:12:08 PM PST 24
Peak memory 210316 kb
Host smart-5f0d80db-e6ff-4010-b750-c4d9d48f73fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020662018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1020662018
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2403639607
Short name T1017
Test name
Test status
Simulation time 44140597 ps
CPU time 0.92 seconds
Started Feb 19 03:12:10 PM PST 24
Finished Feb 19 03:12:13 PM PST 24
Peak memory 206080 kb
Host smart-191d1242-86a2-49d2-947c-22139919c453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403639607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2403639607
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2731718496
Short name T394
Test name
Test status
Simulation time 744955868 ps
CPU time 10.32 seconds
Started Feb 19 03:12:02 PM PST 24
Finished Feb 19 03:12:14 PM PST 24
Peak memory 215368 kb
Host smart-0fbd3057-3dcf-435e-8ea7-d24001f382f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2731718496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2731718496
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.751610677
Short name T56
Test name
Test status
Simulation time 100182892 ps
CPU time 2.59 seconds
Started Feb 19 03:12:09 PM PST 24
Finished Feb 19 03:12:14 PM PST 24
Peak memory 209696 kb
Host smart-6d3fb44d-e09d-4942-831e-251daced94a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751610677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.751610677
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3794144174
Short name T252
Test name
Test status
Simulation time 113685565 ps
CPU time 1.99 seconds
Started Feb 19 03:12:12 PM PST 24
Finished Feb 19 03:12:17 PM PST 24
Peak memory 209600 kb
Host smart-7ec198b8-9f95-42c1-9451-c297d2afa62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794144174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3794144174
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1884442087
Short name T266
Test name
Test status
Simulation time 4140943026 ps
CPU time 85.98 seconds
Started Feb 19 03:12:09 PM PST 24
Finished Feb 19 03:13:37 PM PST 24
Peak memory 226140 kb
Host smart-24f4797a-660b-4d37-a23e-ed6323ae6d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884442087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1884442087
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.4133559476
Short name T651
Test name
Test status
Simulation time 1558170316 ps
CPU time 5.91 seconds
Started Feb 19 03:12:09 PM PST 24
Finished Feb 19 03:12:16 PM PST 24
Peak memory 210064 kb
Host smart-4ba7cd87-5ae6-47f3-a1f5-5e550e0e3cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133559476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.4133559476
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2008461703
Short name T610
Test name
Test status
Simulation time 352040582 ps
CPU time 4.71 seconds
Started Feb 19 03:12:11 PM PST 24
Finished Feb 19 03:12:19 PM PST 24
Peak memory 209120 kb
Host smart-d84cc986-c5da-4337-81f9-29d2b4d01dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008461703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2008461703
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3055355023
Short name T990
Test name
Test status
Simulation time 562141203 ps
CPU time 6.63 seconds
Started Feb 19 03:12:03 PM PST 24
Finished Feb 19 03:12:11 PM PST 24
Peak memory 208520 kb
Host smart-979a1b72-4929-4654-8197-838f747fa1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055355023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3055355023
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1689020039
Short name T781
Test name
Test status
Simulation time 679921324 ps
CPU time 7.32 seconds
Started Feb 19 03:12:05 PM PST 24
Finished Feb 19 03:12:15 PM PST 24
Peak memory 207904 kb
Host smart-aba9138d-05ad-40b6-a1d6-43d0a075b6e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689020039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1689020039
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1548921564
Short name T285
Test name
Test status
Simulation time 1635190923 ps
CPU time 9.1 seconds
Started Feb 19 03:12:10 PM PST 24
Finished Feb 19 03:12:23 PM PST 24
Peak memory 208672 kb
Host smart-9a28bcad-0062-453d-84c9-c476a519d572
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548921564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1548921564
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2355800518
Short name T745
Test name
Test status
Simulation time 332726248 ps
CPU time 4.51 seconds
Started Feb 19 03:12:03 PM PST 24
Finished Feb 19 03:12:10 PM PST 24
Peak memory 206948 kb
Host smart-7e8e6b05-23bc-44fd-bef0-42a7e6fa1226
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355800518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2355800518
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1674109026
Short name T15
Test name
Test status
Simulation time 22656364 ps
CPU time 1.94 seconds
Started Feb 19 03:12:07 PM PST 24
Finished Feb 19 03:12:11 PM PST 24
Peak memory 215692 kb
Host smart-8eb5f268-6c0e-4a18-b2e0-d726ec628bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674109026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1674109026
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3255440129
Short name T930
Test name
Test status
Simulation time 165085075 ps
CPU time 4.45 seconds
Started Feb 19 03:12:02 PM PST 24
Finished Feb 19 03:12:08 PM PST 24
Peak memory 208652 kb
Host smart-a06a982a-7884-456d-8279-b78de195c1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255440129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3255440129
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2920913626
Short name T311
Test name
Test status
Simulation time 14154125508 ps
CPU time 343.41 seconds
Started Feb 19 03:12:09 PM PST 24
Finished Feb 19 03:17:55 PM PST 24
Peak memory 218088 kb
Host smart-a97252ff-f498-4540-bb8e-d594517cf3cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920913626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2920913626
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1253555377
Short name T1019
Test name
Test status
Simulation time 221880559 ps
CPU time 6.62 seconds
Started Feb 19 03:12:13 PM PST 24
Finished Feb 19 03:12:23 PM PST 24
Peak memory 223744 kb
Host smart-3d5d78ec-8f25-4f2a-b609-7c4209d5ab10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253555377 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1253555377
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.686037210
Short name T1002
Test name
Test status
Simulation time 2112545746 ps
CPU time 9 seconds
Started Feb 19 03:12:09 PM PST 24
Finished Feb 19 03:12:20 PM PST 24
Peak memory 208628 kb
Host smart-7048a86e-f454-4360-b9da-f8e4886621ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686037210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.686037210
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1074885521
Short name T668
Test name
Test status
Simulation time 98243791 ps
CPU time 2.23 seconds
Started Feb 19 03:12:15 PM PST 24
Finished Feb 19 03:12:20 PM PST 24
Peak memory 210240 kb
Host smart-a7b0df6e-d2a7-400a-9938-abb75e7569e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074885521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1074885521
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.303009490
Short name T628
Test name
Test status
Simulation time 80411453 ps
CPU time 0.8 seconds
Started Feb 19 03:12:14 PM PST 24
Finished Feb 19 03:12:18 PM PST 24
Peak memory 205896 kb
Host smart-16e584e7-31c7-4c8a-9a8e-bdc870f2eda4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303009490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.303009490
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2355956068
Short name T1069
Test name
Test status
Simulation time 54690539 ps
CPU time 2.44 seconds
Started Feb 19 03:12:15 PM PST 24
Finished Feb 19 03:12:20 PM PST 24
Peak memory 214300 kb
Host smart-7fe74ae0-aced-4871-887d-65cde366455d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2355956068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2355956068
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2473952012
Short name T19
Test name
Test status
Simulation time 108401217 ps
CPU time 3.46 seconds
Started Feb 19 03:12:13 PM PST 24
Finished Feb 19 03:12:20 PM PST 24
Peak memory 222756 kb
Host smart-3bef0713-a4ca-4aff-8411-cb61a3d6725e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473952012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2473952012
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.565214523
Short name T966
Test name
Test status
Simulation time 241051943 ps
CPU time 3.86 seconds
Started Feb 19 03:12:08 PM PST 24
Finished Feb 19 03:12:14 PM PST 24
Peak memory 220344 kb
Host smart-94032b33-3201-43dd-9bcd-02684e4bca9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565214523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.565214523
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.299995318
Short name T665
Test name
Test status
Simulation time 176537110 ps
CPU time 2.43 seconds
Started Feb 19 03:12:08 PM PST 24
Finished Feb 19 03:12:12 PM PST 24
Peak memory 206012 kb
Host smart-aaa5c046-a76c-42bb-9d26-6be4e9eacf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299995318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.299995318
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.351728808
Short name T970
Test name
Test status
Simulation time 393040375 ps
CPU time 5.24 seconds
Started Feb 19 03:12:09 PM PST 24
Finished Feb 19 03:12:16 PM PST 24
Peak memory 208708 kb
Host smart-7746a4d9-49c5-43fb-a937-6ed54f8af00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351728808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.351728808
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3755184034
Short name T766
Test name
Test status
Simulation time 88646458 ps
CPU time 3.83 seconds
Started Feb 19 03:12:10 PM PST 24
Finished Feb 19 03:12:17 PM PST 24
Peak memory 206824 kb
Host smart-681ff639-409e-4d68-9b60-33eaee6588b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755184034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3755184034
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2756012675
Short name T663
Test name
Test status
Simulation time 216632177 ps
CPU time 3.05 seconds
Started Feb 19 03:12:09 PM PST 24
Finished Feb 19 03:12:14 PM PST 24
Peak memory 207012 kb
Host smart-58f816c6-ae3f-4d59-926b-d257d40f2365
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756012675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2756012675
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1342971349
Short name T881
Test name
Test status
Simulation time 2060011990 ps
CPU time 58.77 seconds
Started Feb 19 03:12:14 PM PST 24
Finished Feb 19 03:13:16 PM PST 24
Peak memory 208472 kb
Host smart-f3cb8cae-4c78-4462-9a8b-c7a16283822b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342971349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1342971349
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2971052452
Short name T611
Test name
Test status
Simulation time 277847414 ps
CPU time 4.87 seconds
Started Feb 19 03:12:08 PM PST 24
Finished Feb 19 03:12:15 PM PST 24
Peak memory 208768 kb
Host smart-317cd8f9-858a-4b6d-940e-26ad6adf8f73
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971052452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2971052452
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.4285007942
Short name T869
Test name
Test status
Simulation time 1239350113 ps
CPU time 24.82 seconds
Started Feb 19 03:12:08 PM PST 24
Finished Feb 19 03:12:35 PM PST 24
Peak memory 214292 kb
Host smart-3aefc932-d3cb-4e55-94fd-2fe11a23881e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285007942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4285007942
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2178382759
Short name T903
Test name
Test status
Simulation time 26540634 ps
CPU time 2.01 seconds
Started Feb 19 03:12:06 PM PST 24
Finished Feb 19 03:12:11 PM PST 24
Peak memory 208540 kb
Host smart-5bd5e104-e2f4-41fc-ab69-ffd403b8ca35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178382759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2178382759
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3269537351
Short name T361
Test name
Test status
Simulation time 3342108123 ps
CPU time 29.93 seconds
Started Feb 19 03:12:17 PM PST 24
Finished Feb 19 03:12:50 PM PST 24
Peak memory 222556 kb
Host smart-a8fa5dce-5e5d-45df-ab23-63819fcba1cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269537351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3269537351
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1797657365
Short name T788
Test name
Test status
Simulation time 378901699 ps
CPU time 10.86 seconds
Started Feb 19 03:12:13 PM PST 24
Finished Feb 19 03:12:27 PM PST 24
Peak memory 222452 kb
Host smart-ede412ac-4143-4959-82f2-6100d4691e13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797657365 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1797657365
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2850170078
Short name T697
Test name
Test status
Simulation time 254135915 ps
CPU time 3.99 seconds
Started Feb 19 03:12:09 PM PST 24
Finished Feb 19 03:12:15 PM PST 24
Peak memory 214400 kb
Host smart-b5152348-909e-400b-82ef-03f54cdcc33d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850170078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2850170078
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3895049037
Short name T751
Test name
Test status
Simulation time 93242213 ps
CPU time 2.31 seconds
Started Feb 19 03:12:17 PM PST 24
Finished Feb 19 03:12:21 PM PST 24
Peak memory 210264 kb
Host smart-bc5db9f6-d6ce-48bc-9a45-826e75bf0134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895049037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3895049037
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2361151448
Short name T973
Test name
Test status
Simulation time 20021031 ps
CPU time 0.81 seconds
Started Feb 19 03:09:21 PM PST 24
Finished Feb 19 03:09:24 PM PST 24
Peak memory 205888 kb
Host smart-15896284-0364-41df-81b8-987b789c719d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361151448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2361151448
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2260791131
Short name T234
Test name
Test status
Simulation time 132245144 ps
CPU time 7.38 seconds
Started Feb 19 03:09:07 PM PST 24
Finished Feb 19 03:09:16 PM PST 24
Peak memory 222492 kb
Host smart-406aa267-fb1a-4502-9791-86a59d68ecea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2260791131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2260791131
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.759528742
Short name T896
Test name
Test status
Simulation time 319392517 ps
CPU time 6.2 seconds
Started Feb 19 03:09:11 PM PST 24
Finished Feb 19 03:09:18 PM PST 24
Peak memory 221208 kb
Host smart-3ea858bb-fab9-42ff-a05c-abdb089a7a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759528742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.759528742
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2868055274
Short name T795
Test name
Test status
Simulation time 1137284319 ps
CPU time 30.63 seconds
Started Feb 19 03:09:09 PM PST 24
Finished Feb 19 03:09:43 PM PST 24
Peak memory 209592 kb
Host smart-4792eaad-0d28-4eb6-adda-81f1fb60a24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868055274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2868055274
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3298291759
Short name T87
Test name
Test status
Simulation time 1152272590 ps
CPU time 31.97 seconds
Started Feb 19 03:09:15 PM PST 24
Finished Feb 19 03:09:49 PM PST 24
Peak memory 214296 kb
Host smart-45b1e9ce-301c-40b5-8ede-e08d46218d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298291759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3298291759
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3086630576
Short name T632
Test name
Test status
Simulation time 133333631 ps
CPU time 4.08 seconds
Started Feb 19 03:09:12 PM PST 24
Finished Feb 19 03:09:17 PM PST 24
Peak memory 208972 kb
Host smart-971c229f-6004-4044-9ec4-9c5dade74dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086630576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3086630576
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2710918032
Short name T895
Test name
Test status
Simulation time 478728509 ps
CPU time 7.6 seconds
Started Feb 19 03:09:07 PM PST 24
Finished Feb 19 03:09:17 PM PST 24
Peak memory 209572 kb
Host smart-b0e229d9-ceec-464b-8bff-576370927afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710918032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2710918032
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1083685265
Short name T38
Test name
Test status
Simulation time 345505444 ps
CPU time 11.77 seconds
Started Feb 19 03:09:12 PM PST 24
Finished Feb 19 03:09:24 PM PST 24
Peak memory 229968 kb
Host smart-045654dd-8338-49cc-a051-2ef780dd1a05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083685265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1083685265
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4110551383
Short name T237
Test name
Test status
Simulation time 77151277 ps
CPU time 1.92 seconds
Started Feb 19 03:09:05 PM PST 24
Finished Feb 19 03:09:08 PM PST 24
Peak memory 206772 kb
Host smart-181a3a8f-1135-4495-8754-ec1ce3e02f6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110551383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4110551383
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3805759967
Short name T555
Test name
Test status
Simulation time 83858196 ps
CPU time 2.31 seconds
Started Feb 19 03:09:06 PM PST 24
Finished Feb 19 03:09:09 PM PST 24
Peak memory 206724 kb
Host smart-2be8a920-2c3a-4ba3-aa2e-94fe2370a4b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805759967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3805759967
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3495455266
Short name T803
Test name
Test status
Simulation time 357751981 ps
CPU time 7.55 seconds
Started Feb 19 03:09:07 PM PST 24
Finished Feb 19 03:09:16 PM PST 24
Peak memory 208488 kb
Host smart-012e5301-a08f-4b88-981a-9f6cbbc663a3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495455266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3495455266
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.134881260
Short name T1046
Test name
Test status
Simulation time 535418449 ps
CPU time 4.3 seconds
Started Feb 19 03:09:08 PM PST 24
Finished Feb 19 03:09:16 PM PST 24
Peak memory 206872 kb
Host smart-da9356f5-cb55-4a51-ab73-d4bb939e9c5c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134881260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.134881260
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.165391499
Short name T783
Test name
Test status
Simulation time 221699092 ps
CPU time 1.69 seconds
Started Feb 19 03:09:11 PM PST 24
Finished Feb 19 03:09:14 PM PST 24
Peak memory 207896 kb
Host smart-40ec9a84-6033-4df0-908c-65ccb8e17965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165391499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.165391499
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3285790830
Short name T603
Test name
Test status
Simulation time 475272236 ps
CPU time 5.31 seconds
Started Feb 19 03:09:06 PM PST 24
Finished Feb 19 03:09:12 PM PST 24
Peak memory 208004 kb
Host smart-a6121148-29b4-4e86-8b15-9986678944cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285790830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3285790830
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1300787575
Short name T877
Test name
Test status
Simulation time 1269418545 ps
CPU time 48.31 seconds
Started Feb 19 03:09:17 PM PST 24
Finished Feb 19 03:10:06 PM PST 24
Peak memory 222544 kb
Host smart-a4b9acae-6707-4e75-bdaf-19104fe1de42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300787575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1300787575
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.404677317
Short name T594
Test name
Test status
Simulation time 121346419 ps
CPU time 4.69 seconds
Started Feb 19 03:09:13 PM PST 24
Finished Feb 19 03:09:20 PM PST 24
Peak memory 219100 kb
Host smart-a94ea3bd-d859-45ad-a97f-5f9eaf04d70a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404677317 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.404677317
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.605951715
Short name T911
Test name
Test status
Simulation time 392656789 ps
CPU time 6.31 seconds
Started Feb 19 03:09:17 PM PST 24
Finished Feb 19 03:09:24 PM PST 24
Peak memory 207296 kb
Host smart-ac93a14a-c105-4df1-8668-93e11f04566b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605951715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.605951715
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1831356105
Short name T912
Test name
Test status
Simulation time 241806577 ps
CPU time 2.87 seconds
Started Feb 19 03:09:14 PM PST 24
Finished Feb 19 03:09:18 PM PST 24
Peak memory 210360 kb
Host smart-77ddcd4e-f22d-432a-9ce6-96cd3d7dbe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831356105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1831356105
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2118851771
Short name T760
Test name
Test status
Simulation time 55217039 ps
CPU time 0.97 seconds
Started Feb 19 03:12:17 PM PST 24
Finished Feb 19 03:12:21 PM PST 24
Peak memory 206040 kb
Host smart-4773ad23-6f11-477d-8c0e-8ff5ee36a7eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118851771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2118851771
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3623239488
Short name T410
Test name
Test status
Simulation time 81200857 ps
CPU time 4.81 seconds
Started Feb 19 03:12:11 PM PST 24
Finished Feb 19 03:12:20 PM PST 24
Peak memory 222444 kb
Host smart-b1161cef-e1cc-42ea-a384-dba7247baca9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3623239488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3623239488
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1540408219
Short name T931
Test name
Test status
Simulation time 431995674 ps
CPU time 5.76 seconds
Started Feb 19 03:12:17 PM PST 24
Finished Feb 19 03:12:26 PM PST 24
Peak memory 221580 kb
Host smart-4aa5f299-6481-435a-9887-6b975c46b36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540408219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1540408219
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3918647612
Short name T598
Test name
Test status
Simulation time 27023736 ps
CPU time 1.63 seconds
Started Feb 19 03:12:15 PM PST 24
Finished Feb 19 03:12:20 PM PST 24
Peak memory 209216 kb
Host smart-810eb243-8104-439b-aefe-24f7f546b684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918647612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3918647612
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2269294493
Short name T1011
Test name
Test status
Simulation time 96273544 ps
CPU time 4.73 seconds
Started Feb 19 03:12:19 PM PST 24
Finished Feb 19 03:12:26 PM PST 24
Peak memory 208984 kb
Host smart-9e62a43e-53c6-432e-bef6-ba8c9f55e632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269294493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2269294493
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2733596638
Short name T624
Test name
Test status
Simulation time 217643644 ps
CPU time 3.69 seconds
Started Feb 19 03:12:18 PM PST 24
Finished Feb 19 03:12:24 PM PST 24
Peak memory 207932 kb
Host smart-479a767c-956b-40d3-9929-ce2cb96e0657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733596638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2733596638
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3641609917
Short name T890
Test name
Test status
Simulation time 560660913 ps
CPU time 6.21 seconds
Started Feb 19 03:12:11 PM PST 24
Finished Feb 19 03:12:21 PM PST 24
Peak memory 210232 kb
Host smart-b961bffb-6ffa-4cb1-beac-9c8776456f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641609917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3641609917
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1541496664
Short name T263
Test name
Test status
Simulation time 482629335 ps
CPU time 4.82 seconds
Started Feb 19 03:12:13 PM PST 24
Finished Feb 19 03:12:22 PM PST 24
Peak memory 208608 kb
Host smart-e84eb4cb-1acb-444b-9578-60a43f460247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541496664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1541496664
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.924423279
Short name T686
Test name
Test status
Simulation time 1093555181 ps
CPU time 29.01 seconds
Started Feb 19 03:12:16 PM PST 24
Finished Feb 19 03:12:48 PM PST 24
Peak memory 208700 kb
Host smart-2491e323-aa76-4479-a576-f39a40165e5a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924423279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.924423279
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1789076872
Short name T215
Test name
Test status
Simulation time 37156383 ps
CPU time 2.47 seconds
Started Feb 19 03:12:16 PM PST 24
Finished Feb 19 03:12:22 PM PST 24
Peak memory 206540 kb
Host smart-146b7972-ad43-4431-a770-7a12ec9c012d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789076872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1789076872
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2432950101
Short name T691
Test name
Test status
Simulation time 378499647 ps
CPU time 3.76 seconds
Started Feb 19 03:12:11 PM PST 24
Finished Feb 19 03:12:19 PM PST 24
Peak memory 207120 kb
Host smart-97e5126c-affe-4f96-b093-79e8e19d577f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432950101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2432950101
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2386845536
Short name T1000
Test name
Test status
Simulation time 332293149 ps
CPU time 2.43 seconds
Started Feb 19 03:12:19 PM PST 24
Finished Feb 19 03:12:24 PM PST 24
Peak memory 208176 kb
Host smart-9ca2598b-c14b-4d60-aea0-ffd0c5033b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386845536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2386845536
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2536159578
Short name T99
Test name
Test status
Simulation time 285616959 ps
CPU time 7.5 seconds
Started Feb 19 03:12:12 PM PST 24
Finished Feb 19 03:12:23 PM PST 24
Peak memory 207884 kb
Host smart-0e2c48c6-8a25-4e01-875c-50fefa0d891d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536159578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2536159578
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3033011082
Short name T195
Test name
Test status
Simulation time 1002874286 ps
CPU time 8.68 seconds
Started Feb 19 03:12:32 PM PST 24
Finished Feb 19 03:12:46 PM PST 24
Peak memory 222660 kb
Host smart-4fdc0074-f584-46be-9a82-551fc09927da
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033011082 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.3033011082
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1530868097
Short name T882
Test name
Test status
Simulation time 1064919447 ps
CPU time 11.77 seconds
Started Feb 19 03:12:16 PM PST 24
Finished Feb 19 03:12:31 PM PST 24
Peak memory 222436 kb
Host smart-52c1c065-a116-40d1-8f86-71360c48a0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530868097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1530868097
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.346186883
Short name T584
Test name
Test status
Simulation time 635668108 ps
CPU time 4.25 seconds
Started Feb 19 03:12:32 PM PST 24
Finished Feb 19 03:12:41 PM PST 24
Peak memory 210908 kb
Host smart-3157cecc-c612-4477-a169-101bdddae18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346186883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.346186883
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2920092335
Short name T623
Test name
Test status
Simulation time 34066206 ps
CPU time 0.92 seconds
Started Feb 19 03:12:28 PM PST 24
Finished Feb 19 03:12:30 PM PST 24
Peak memory 206048 kb
Host smart-a82bd368-6212-4b94-ab45-fffa7ba6dff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920092335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2920092335
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3478720327
Short name T301
Test name
Test status
Simulation time 227136246 ps
CPU time 11.81 seconds
Started Feb 19 03:12:17 PM PST 24
Finished Feb 19 03:12:31 PM PST 24
Peak memory 214332 kb
Host smart-858a554e-bbcc-477f-9442-60b0d5b9bdae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3478720327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3478720327
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4204339763
Short name T31
Test name
Test status
Simulation time 388935408 ps
CPU time 10.44 seconds
Started Feb 19 03:12:24 PM PST 24
Finished Feb 19 03:12:36 PM PST 24
Peak memory 214588 kb
Host smart-37337438-cedd-4221-b9af-13971318e1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204339763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4204339763
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.457986896
Short name T264
Test name
Test status
Simulation time 74681625 ps
CPU time 2.36 seconds
Started Feb 19 03:12:22 PM PST 24
Finished Feb 19 03:12:26 PM PST 24
Peak memory 209108 kb
Host smart-d1553fdf-62d2-448c-8614-8d0faca90cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457986896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.457986896
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2766112744
Short name T75
Test name
Test status
Simulation time 376081697 ps
CPU time 4.21 seconds
Started Feb 19 03:12:28 PM PST 24
Finished Feb 19 03:12:34 PM PST 24
Peak memory 208700 kb
Host smart-27b21682-00a3-45d0-a288-13ed17a34f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766112744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2766112744
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.509043010
Short name T199
Test name
Test status
Simulation time 134145400 ps
CPU time 2.39 seconds
Started Feb 19 03:12:36 PM PST 24
Finished Feb 19 03:12:42 PM PST 24
Peak memory 220196 kb
Host smart-a1385dbc-dcaf-44a5-8441-6e6abb4ae38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509043010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.509043010
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3398494659
Short name T635
Test name
Test status
Simulation time 1034103556 ps
CPU time 7 seconds
Started Feb 19 03:12:32 PM PST 24
Finished Feb 19 03:12:44 PM PST 24
Peak memory 207316 kb
Host smart-f7efa60b-7267-46e9-a3f8-0796a2f39d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398494659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3398494659
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.426673
Short name T673
Test name
Test status
Simulation time 63140727 ps
CPU time 2.86 seconds
Started Feb 19 03:12:17 PM PST 24
Finished Feb 19 03:12:23 PM PST 24
Peak memory 208460 kb
Host smart-4711a107-d244-458d-bd56-5b135e91d2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.426673
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2689228692
Short name T741
Test name
Test status
Simulation time 146185760 ps
CPU time 3.11 seconds
Started Feb 19 03:12:19 PM PST 24
Finished Feb 19 03:12:24 PM PST 24
Peak memory 206960 kb
Host smart-b1226a7d-6126-42b4-bc89-7423478d92c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689228692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2689228692
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3420450060
Short name T175
Test name
Test status
Simulation time 136837316 ps
CPU time 3.74 seconds
Started Feb 19 03:12:19 PM PST 24
Finished Feb 19 03:12:25 PM PST 24
Peak memory 207056 kb
Host smart-3269f236-180e-4327-b288-474606d413bc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420450060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3420450060
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3500043692
Short name T933
Test name
Test status
Simulation time 132087504 ps
CPU time 3.34 seconds
Started Feb 19 03:12:22 PM PST 24
Finished Feb 19 03:12:26 PM PST 24
Peak memory 206748 kb
Host smart-b0a33f04-66fe-4398-8856-2b556f62db07
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500043692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3500043692
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.4077956081
Short name T558
Test name
Test status
Simulation time 69474565 ps
CPU time 2.43 seconds
Started Feb 19 03:12:29 PM PST 24
Finished Feb 19 03:12:33 PM PST 24
Peak memory 215544 kb
Host smart-9849ce7f-981e-40ae-b98e-569ce87b060c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077956081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.4077956081
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1412384715
Short name T557
Test name
Test status
Simulation time 73182795 ps
CPU time 2.46 seconds
Started Feb 19 03:12:32 PM PST 24
Finished Feb 19 03:12:39 PM PST 24
Peak memory 208232 kb
Host smart-840a48a9-9269-4a03-9563-866939944347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412384715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1412384715
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1507299987
Short name T243
Test name
Test status
Simulation time 11988701320 ps
CPU time 290.64 seconds
Started Feb 19 03:12:26 PM PST 24
Finished Feb 19 03:17:18 PM PST 24
Peak memory 222476 kb
Host smart-90981812-c0cc-40d9-a2b0-de0f7839fb9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507299987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1507299987
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.300478087
Short name T179
Test name
Test status
Simulation time 382921963 ps
CPU time 12.79 seconds
Started Feb 19 03:12:31 PM PST 24
Finished Feb 19 03:12:48 PM PST 24
Peak memory 220228 kb
Host smart-7d946e7c-a3d0-424e-bec0-dd21a5a535a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300478087 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.300478087
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3027369393
Short name T822
Test name
Test status
Simulation time 133460645 ps
CPU time 3.39 seconds
Started Feb 19 03:12:26 PM PST 24
Finished Feb 19 03:12:31 PM PST 24
Peak memory 207584 kb
Host smart-b56adc55-dc59-40fa-a7c3-42b0f246ed74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027369393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3027369393
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2719109203
Short name T100
Test name
Test status
Simulation time 46695042 ps
CPU time 2.57 seconds
Started Feb 19 03:12:36 PM PST 24
Finished Feb 19 03:12:42 PM PST 24
Peak memory 210188 kb
Host smart-b0071ce4-ad70-4388-ac39-171252e18a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719109203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2719109203
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.89215075
Short name T727
Test name
Test status
Simulation time 36191774 ps
CPU time 0.96 seconds
Started Feb 19 03:12:43 PM PST 24
Finished Feb 19 03:12:47 PM PST 24
Peak memory 205880 kb
Host smart-82831784-7426-4935-b6c6-14fa44022256
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89215075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.89215075
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3542722973
Short name T645
Test name
Test status
Simulation time 105005409 ps
CPU time 4 seconds
Started Feb 19 03:12:32 PM PST 24
Finished Feb 19 03:12:41 PM PST 24
Peak memory 216932 kb
Host smart-ef2e6722-dfa3-4e5a-a8b6-898a85f6f98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542722973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3542722973
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1399128722
Short name T296
Test name
Test status
Simulation time 425678130 ps
CPU time 3.81 seconds
Started Feb 19 03:12:32 PM PST 24
Finished Feb 19 03:12:40 PM PST 24
Peak memory 207328 kb
Host smart-c44b527f-d950-4bd6-b3b3-44b4ee4136c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399128722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1399128722
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1075991347
Short name T250
Test name
Test status
Simulation time 280942326 ps
CPU time 3.95 seconds
Started Feb 19 03:12:34 PM PST 24
Finished Feb 19 03:12:42 PM PST 24
Peak memory 214316 kb
Host smart-be0963c4-a8e5-4008-885d-2cd6db442368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075991347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1075991347
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3460771405
Short name T281
Test name
Test status
Simulation time 263068885 ps
CPU time 6.19 seconds
Started Feb 19 03:12:26 PM PST 24
Finished Feb 19 03:12:33 PM PST 24
Peak memory 222356 kb
Host smart-7e02d562-0cf5-41f4-a1be-0e116febb888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460771405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3460771405
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.118833051
Short name T677
Test name
Test status
Simulation time 681024006 ps
CPU time 3.93 seconds
Started Feb 19 03:12:28 PM PST 24
Finished Feb 19 03:12:34 PM PST 24
Peak memory 219748 kb
Host smart-01b8a452-3693-4c2b-9383-10d1ba9413b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118833051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.118833051
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.4010489270
Short name T289
Test name
Test status
Simulation time 244308301 ps
CPU time 6.88 seconds
Started Feb 19 03:12:32 PM PST 24
Finished Feb 19 03:12:44 PM PST 24
Peak memory 209220 kb
Host smart-1a90424c-46af-46a7-8665-f646c49aeed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010489270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.4010489270
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3202600922
Short name T626
Test name
Test status
Simulation time 4093489257 ps
CPU time 10.03 seconds
Started Feb 19 03:12:26 PM PST 24
Finished Feb 19 03:12:37 PM PST 24
Peak memory 208124 kb
Host smart-a3802ff1-1d9b-4156-9fe5-87eba00082cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202600922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3202600922
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2745487588
Short name T650
Test name
Test status
Simulation time 62942040 ps
CPU time 3.06 seconds
Started Feb 19 03:12:32 PM PST 24
Finished Feb 19 03:12:40 PM PST 24
Peak memory 207976 kb
Host smart-af90e8e2-8acc-4b84-8b37-61c83db0c1d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745487588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2745487588
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1143090264
Short name T700
Test name
Test status
Simulation time 54104657 ps
CPU time 2.94 seconds
Started Feb 19 03:12:27 PM PST 24
Finished Feb 19 03:12:31 PM PST 24
Peak memory 208772 kb
Host smart-f36a69a9-9c32-4fe6-8503-5916b675e849
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143090264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1143090264
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1660531783
Short name T883
Test name
Test status
Simulation time 3275774936 ps
CPU time 8.82 seconds
Started Feb 19 03:12:27 PM PST 24
Finished Feb 19 03:12:38 PM PST 24
Peak memory 209012 kb
Host smart-582942e5-f91d-42e4-a8c2-337249b8ff66
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660531783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1660531783
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3723714847
Short name T211
Test name
Test status
Simulation time 226723537 ps
CPU time 2.49 seconds
Started Feb 19 03:12:48 PM PST 24
Finished Feb 19 03:12:53 PM PST 24
Peak memory 209112 kb
Host smart-c3483c45-7761-4903-b450-3faf260fdd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723714847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3723714847
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.4283508222
Short name T791
Test name
Test status
Simulation time 129948714 ps
CPU time 4.8 seconds
Started Feb 19 03:12:29 PM PST 24
Finished Feb 19 03:12:37 PM PST 24
Peak memory 206668 kb
Host smart-6a2f6b28-0bd8-4463-aaf2-0535b2181cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283508222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.4283508222
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.723428166
Short name T736
Test name
Test status
Simulation time 860419881 ps
CPU time 5.99 seconds
Started Feb 19 03:12:42 PM PST 24
Finished Feb 19 03:12:51 PM PST 24
Peak memory 222580 kb
Host smart-53a77615-35fd-4dcd-8afa-0313f4ebdf65
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723428166 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.723428166
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2462557109
Short name T972
Test name
Test status
Simulation time 207172098 ps
CPU time 7.23 seconds
Started Feb 19 03:12:32 PM PST 24
Finished Feb 19 03:12:44 PM PST 24
Peak memory 210336 kb
Host smart-fb40e3ae-d475-432a-b395-b99f45497485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462557109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2462557109
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1534792494
Short name T150
Test name
Test status
Simulation time 82997739 ps
CPU time 3.06 seconds
Started Feb 19 03:12:46 PM PST 24
Finished Feb 19 03:12:51 PM PST 24
Peak memory 210684 kb
Host smart-ab233ca3-bc92-4852-951c-c2ab31c01b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534792494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1534792494
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.4286429544
Short name T850
Test name
Test status
Simulation time 51230714 ps
CPU time 0.85 seconds
Started Feb 19 03:12:46 PM PST 24
Finished Feb 19 03:12:48 PM PST 24
Peak memory 206052 kb
Host smart-b4541211-8644-4158-8d42-14d9eb27244c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286429544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.4286429544
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3882116697
Short name T262
Test name
Test status
Simulation time 299569169 ps
CPU time 2.14 seconds
Started Feb 19 03:12:49 PM PST 24
Finished Feb 19 03:12:54 PM PST 24
Peak memory 214320 kb
Host smart-c2047f26-d3ff-4490-ae89-5c96e63394f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3882116697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3882116697
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3504073951
Short name T743
Test name
Test status
Simulation time 1891090295 ps
CPU time 14.73 seconds
Started Feb 19 03:12:41 PM PST 24
Finished Feb 19 03:12:59 PM PST 24
Peak memory 209444 kb
Host smart-89c2696c-4b7a-4e8d-bfdc-d8823344057d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504073951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3504073951
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2311811120
Short name T945
Test name
Test status
Simulation time 203921164 ps
CPU time 6.09 seconds
Started Feb 19 03:12:47 PM PST 24
Finished Feb 19 03:12:56 PM PST 24
Peak memory 209784 kb
Host smart-c6c44cdf-876d-46b1-a245-da15a8fcbb0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311811120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2311811120
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2701041536
Short name T338
Test name
Test status
Simulation time 228951865 ps
CPU time 5.82 seconds
Started Feb 19 03:12:41 PM PST 24
Finished Feb 19 03:12:50 PM PST 24
Peak memory 214316 kb
Host smart-3e790d2c-94bd-4b21-a0f5-c2708576482d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701041536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2701041536
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.684741026
Short name T125
Test name
Test status
Simulation time 74286018 ps
CPU time 3.63 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:12:57 PM PST 24
Peak memory 207752 kb
Host smart-d93a448a-fb09-45f1-9fb9-5017ed1d9107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684741026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.684741026
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.707974229
Short name T366
Test name
Test status
Simulation time 316109890 ps
CPU time 3.96 seconds
Started Feb 19 03:12:42 PM PST 24
Finished Feb 19 03:12:49 PM PST 24
Peak memory 206864 kb
Host smart-cd5983e1-77a6-4374-8bb7-5d6fe58913c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707974229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.707974229
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2375500377
Short name T381
Test name
Test status
Simulation time 979727588 ps
CPU time 29.48 seconds
Started Feb 19 03:12:43 PM PST 24
Finished Feb 19 03:13:15 PM PST 24
Peak memory 208836 kb
Host smart-66f1ef29-e29a-453b-87ab-e89c02298933
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375500377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2375500377
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.454178251
Short name T670
Test name
Test status
Simulation time 583887638 ps
CPU time 11.2 seconds
Started Feb 19 03:12:43 PM PST 24
Finished Feb 19 03:12:56 PM PST 24
Peak memory 207012 kb
Host smart-78fce8c6-0842-4939-920a-9db57accf0cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454178251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.454178251
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3472057415
Short name T286
Test name
Test status
Simulation time 53313225 ps
CPU time 3.11 seconds
Started Feb 19 03:12:46 PM PST 24
Finished Feb 19 03:12:51 PM PST 24
Peak memory 209012 kb
Host smart-47993a37-e1df-4444-afe5-d138c93266a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472057415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3472057415
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2347862112
Short name T238
Test name
Test status
Simulation time 248544691 ps
CPU time 2.94 seconds
Started Feb 19 03:12:46 PM PST 24
Finished Feb 19 03:12:51 PM PST 24
Peak memory 213304 kb
Host smart-f4737a25-0c12-4819-8461-99e901962a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347862112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2347862112
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2772868791
Short name T70
Test name
Test status
Simulation time 1276933522 ps
CPU time 7.2 seconds
Started Feb 19 03:12:41 PM PST 24
Finished Feb 19 03:12:51 PM PST 24
Peak memory 208780 kb
Host smart-9245c927-6518-4ab8-8391-2f247b636647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772868791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2772868791
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.410029505
Short name T1062
Test name
Test status
Simulation time 205554998 ps
CPU time 6.14 seconds
Started Feb 19 03:12:48 PM PST 24
Finished Feb 19 03:12:57 PM PST 24
Peak memory 208148 kb
Host smart-80726dd4-8000-4146-90c2-82450207038b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410029505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.410029505
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3557339900
Short name T748
Test name
Test status
Simulation time 476830193 ps
CPU time 11.2 seconds
Started Feb 19 03:12:43 PM PST 24
Finished Feb 19 03:12:56 PM PST 24
Peak memory 208928 kb
Host smart-dea20889-e3c1-4410-b22f-8261bdf1b848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557339900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3557339900
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2113786535
Short name T388
Test name
Test status
Simulation time 1146260852 ps
CPU time 8.15 seconds
Started Feb 19 03:12:47 PM PST 24
Finished Feb 19 03:12:57 PM PST 24
Peak memory 211036 kb
Host smart-b9b9dda5-2115-4b80-a924-18995e96597e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113786535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2113786535
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1883473554
Short name T620
Test name
Test status
Simulation time 14053720 ps
CPU time 0.94 seconds
Started Feb 19 03:12:47 PM PST 24
Finished Feb 19 03:12:50 PM PST 24
Peak memory 206024 kb
Host smart-20375a3f-b050-4ca0-a0ad-60bbd7ead183
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883473554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1883473554
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2590901083
Short name T898
Test name
Test status
Simulation time 1113314971 ps
CPU time 23.22 seconds
Started Feb 19 03:12:41 PM PST 24
Finished Feb 19 03:13:08 PM PST 24
Peak memory 208768 kb
Host smart-5e20e2e7-fbd8-4994-883b-fafba002eec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590901083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2590901083
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.430213324
Short name T356
Test name
Test status
Simulation time 227580292 ps
CPU time 6.66 seconds
Started Feb 19 03:12:48 PM PST 24
Finished Feb 19 03:12:57 PM PST 24
Peak memory 219728 kb
Host smart-4f0788d8-5fa7-499e-adb3-0e08c9ac23b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430213324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.430213324
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.120373157
Short name T350
Test name
Test status
Simulation time 113015988 ps
CPU time 2.54 seconds
Started Feb 19 03:12:44 PM PST 24
Finished Feb 19 03:12:49 PM PST 24
Peak memory 211332 kb
Host smart-8292294f-d2a4-4f57-8714-ec46507cf47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120373157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.120373157
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.4171877822
Short name T201
Test name
Test status
Simulation time 422220911 ps
CPU time 6.54 seconds
Started Feb 19 03:12:45 PM PST 24
Finished Feb 19 03:12:53 PM PST 24
Peak memory 214296 kb
Host smart-e4df08b1-9109-48d2-8cf7-b40a177b7dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171877822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.4171877822
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3382467044
Short name T720
Test name
Test status
Simulation time 213441190 ps
CPU time 6.25 seconds
Started Feb 19 03:12:41 PM PST 24
Finished Feb 19 03:12:50 PM PST 24
Peak memory 214336 kb
Host smart-1b9c0e65-4bd6-4b18-9893-3f6473ff1db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382467044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3382467044
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1252069641
Short name T1060
Test name
Test status
Simulation time 1352497150 ps
CPU time 33.57 seconds
Started Feb 19 03:12:52 PM PST 24
Finished Feb 19 03:13:30 PM PST 24
Peak memory 208028 kb
Host smart-dc6f8344-7c91-449a-83cc-4df63a7e459b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252069641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1252069641
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3782986554
Short name T173
Test name
Test status
Simulation time 2499516745 ps
CPU time 25.14 seconds
Started Feb 19 03:12:45 PM PST 24
Finished Feb 19 03:13:12 PM PST 24
Peak memory 208968 kb
Host smart-9c463029-9c9d-457f-803a-56043df46e1e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782986554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3782986554
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.566063483
Short name T176
Test name
Test status
Simulation time 265548007 ps
CPU time 3.42 seconds
Started Feb 19 03:12:42 PM PST 24
Finished Feb 19 03:12:48 PM PST 24
Peak memory 206736 kb
Host smart-1c1d41e8-517b-456c-992e-3be37d74de01
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566063483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.566063483
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.208235699
Short name T579
Test name
Test status
Simulation time 65824545 ps
CPU time 2.04 seconds
Started Feb 19 03:12:46 PM PST 24
Finished Feb 19 03:12:49 PM PST 24
Peak memory 208552 kb
Host smart-c5e246c9-0ad6-43d2-87de-318d8ad1101b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208235699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.208235699
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3449052266
Short name T922
Test name
Test status
Simulation time 715963369 ps
CPU time 7.69 seconds
Started Feb 19 03:12:44 PM PST 24
Finished Feb 19 03:12:54 PM PST 24
Peak memory 215864 kb
Host smart-65cfbd7e-dd8b-40f1-8955-f6f6ac7ee9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449052266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3449052266
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.935555922
Short name T169
Test name
Test status
Simulation time 185849717 ps
CPU time 2.59 seconds
Started Feb 19 03:12:46 PM PST 24
Finished Feb 19 03:12:50 PM PST 24
Peak memory 206864 kb
Host smart-c77f9571-2efe-4904-899e-8674bda32e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935555922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.935555922
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3372001047
Short name T288
Test name
Test status
Simulation time 5667059921 ps
CPU time 57.18 seconds
Started Feb 19 03:12:47 PM PST 24
Finished Feb 19 03:13:47 PM PST 24
Peak memory 222548 kb
Host smart-ab6069ea-32dd-4a8a-9f02-8c311f083532
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372001047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3372001047
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1456597272
Short name T731
Test name
Test status
Simulation time 138950098 ps
CPU time 6.19 seconds
Started Feb 19 03:12:49 PM PST 24
Finished Feb 19 03:12:59 PM PST 24
Peak memory 222600 kb
Host smart-c9fb3bb9-5703-4cd1-b016-17260247005f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456597272 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1456597272
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1324958491
Short name T942
Test name
Test status
Simulation time 145226501 ps
CPU time 4.08 seconds
Started Feb 19 03:12:42 PM PST 24
Finished Feb 19 03:12:49 PM PST 24
Peak memory 207300 kb
Host smart-aab5c5f9-76cc-4469-96ae-c687df3f195e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324958491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1324958491
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.516225711
Short name T654
Test name
Test status
Simulation time 522563687 ps
CPU time 3.42 seconds
Started Feb 19 03:12:45 PM PST 24
Finished Feb 19 03:12:50 PM PST 24
Peak memory 210656 kb
Host smart-f8bbe104-d04e-4073-98c5-ea1f3af7bfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516225711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.516225711
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1186991555
Short name T1057
Test name
Test status
Simulation time 15275693 ps
CPU time 0.94 seconds
Started Feb 19 03:12:50 PM PST 24
Finished Feb 19 03:12:54 PM PST 24
Peak memory 206028 kb
Host smart-60e3fb38-e1bf-4026-8fab-f41805c2c141
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186991555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1186991555
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2993939186
Short name T326
Test name
Test status
Simulation time 716172610 ps
CPU time 39.31 seconds
Started Feb 19 03:12:46 PM PST 24
Finished Feb 19 03:13:27 PM PST 24
Peak memory 213288 kb
Host smart-cf1a7914-ba1c-4243-ac0d-0cdd78ec176b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2993939186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2993939186
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3708732082
Short name T8
Test name
Test status
Simulation time 134194027 ps
CPU time 3.25 seconds
Started Feb 19 03:12:48 PM PST 24
Finished Feb 19 03:12:55 PM PST 24
Peak memory 221712 kb
Host smart-597601c7-3e0e-4baf-9f21-07e07e558645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708732082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3708732082
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.557194998
Short name T354
Test name
Test status
Simulation time 58754224 ps
CPU time 1.86 seconds
Started Feb 19 03:12:47 PM PST 24
Finished Feb 19 03:12:52 PM PST 24
Peak memory 216972 kb
Host smart-67740b0e-d819-4a3f-8300-172fe2b92f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557194998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.557194998
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.323953197
Short name T1012
Test name
Test status
Simulation time 155510037 ps
CPU time 6.52 seconds
Started Feb 19 03:12:44 PM PST 24
Finished Feb 19 03:12:53 PM PST 24
Peak memory 214400 kb
Host smart-c50d9c23-51c2-49e2-b33e-b1e179b47093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323953197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.323953197
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2283776570
Short name T1004
Test name
Test status
Simulation time 1548451609 ps
CPU time 42.76 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:13:38 PM PST 24
Peak memory 209308 kb
Host smart-6a3e5875-3eed-48ab-99a9-c51c0e1d642e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283776570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2283776570
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3364253663
Short name T6
Test name
Test status
Simulation time 383307833 ps
CPU time 6.22 seconds
Started Feb 19 03:12:55 PM PST 24
Finished Feb 19 03:13:06 PM PST 24
Peak memory 209452 kb
Host smart-a137d1d7-7470-4075-a78e-cee0c68c45da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364253663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3364253663
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3956831505
Short name T340
Test name
Test status
Simulation time 866440445 ps
CPU time 21.61 seconds
Started Feb 19 03:12:50 PM PST 24
Finished Feb 19 03:13:15 PM PST 24
Peak memory 208204 kb
Host smart-607e0e33-4a59-496e-8e8b-bc2fac1afee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956831505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3956831505
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1988716711
Short name T985
Test name
Test status
Simulation time 74051559 ps
CPU time 3.03 seconds
Started Feb 19 03:12:47 PM PST 24
Finished Feb 19 03:12:52 PM PST 24
Peak memory 206876 kb
Host smart-7eb55d5f-d6cb-474b-a6c7-131522eaa84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988716711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1988716711
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2361736913
Short name T592
Test name
Test status
Simulation time 577184410 ps
CPU time 5.07 seconds
Started Feb 19 03:12:43 PM PST 24
Finished Feb 19 03:12:50 PM PST 24
Peak memory 206772 kb
Host smart-73aa2d5f-73bb-479a-a64d-2094e884c9f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361736913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2361736913
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.120359907
Short name T737
Test name
Test status
Simulation time 64961948 ps
CPU time 3.37 seconds
Started Feb 19 03:12:47 PM PST 24
Finished Feb 19 03:12:53 PM PST 24
Peak memory 206764 kb
Host smart-9f764249-c7c6-4c85-ac6d-5c11ec8d046c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120359907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.120359907
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.212667025
Short name T880
Test name
Test status
Simulation time 153148722 ps
CPU time 3.98 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:12:58 PM PST 24
Peak memory 209636 kb
Host smart-8aaf74a8-8e3d-42fe-8dd3-4ee672937fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212667025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.212667025
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2908415837
Short name T824
Test name
Test status
Simulation time 838047804 ps
CPU time 6.2 seconds
Started Feb 19 03:12:47 PM PST 24
Finished Feb 19 03:12:55 PM PST 24
Peak memory 208404 kb
Host smart-48a828ca-05db-464f-aa57-fde74ead2b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908415837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2908415837
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.4233387282
Short name T321
Test name
Test status
Simulation time 1726084193 ps
CPU time 15.28 seconds
Started Feb 19 03:12:45 PM PST 24
Finished Feb 19 03:13:02 PM PST 24
Peak memory 222468 kb
Host smart-dc1eab64-6c68-4b5a-8c57-8326db4b344c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233387282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.4233387282
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3688498989
Short name T821
Test name
Test status
Simulation time 507133527 ps
CPU time 4.4 seconds
Started Feb 19 03:12:46 PM PST 24
Finished Feb 19 03:12:52 PM PST 24
Peak memory 222544 kb
Host smart-a4f679bd-3347-4c15-8577-3036661d0b96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688498989 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3688498989
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2196998697
Short name T216
Test name
Test status
Simulation time 197289275 ps
CPU time 5.08 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:12:59 PM PST 24
Peak memory 214232 kb
Host smart-3d609779-eb67-4791-b997-eabf492d3df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196998697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2196998697
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.948338576
Short name T566
Test name
Test status
Simulation time 57215843 ps
CPU time 2.42 seconds
Started Feb 19 03:12:47 PM PST 24
Finished Feb 19 03:12:51 PM PST 24
Peak memory 210112 kb
Host smart-c95622b6-6285-40d9-8711-96a785c6633c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948338576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.948338576
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3930728724
Short name T412
Test name
Test status
Simulation time 30316670 ps
CPU time 0.75 seconds
Started Feb 19 03:12:54 PM PST 24
Finished Feb 19 03:12:59 PM PST 24
Peak memory 205868 kb
Host smart-c28437a5-af67-435f-a9c3-a93f30649830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930728724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3930728724
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.700358693
Short name T270
Test name
Test status
Simulation time 60808895 ps
CPU time 3.99 seconds
Started Feb 19 03:12:49 PM PST 24
Finished Feb 19 03:12:56 PM PST 24
Peak memory 215420 kb
Host smart-dba0e698-cc8e-4a32-b725-8853e822bbb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=700358693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.700358693
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1312392386
Short name T793
Test name
Test status
Simulation time 125236995 ps
CPU time 2.82 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:12:58 PM PST 24
Peak memory 221348 kb
Host smart-87f7e2c6-655d-40c4-9874-efd07fd226a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312392386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1312392386
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.6753182
Short name T58
Test name
Test status
Simulation time 23328700 ps
CPU time 1.22 seconds
Started Feb 19 03:12:48 PM PST 24
Finished Feb 19 03:12:53 PM PST 24
Peak memory 206188 kb
Host smart-62818559-2936-4ad3-9990-2f4fbc0b60f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6753182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.6753182
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2661792912
Short name T83
Test name
Test status
Simulation time 1854760554 ps
CPU time 13.64 seconds
Started Feb 19 03:12:49 PM PST 24
Finished Feb 19 03:13:06 PM PST 24
Peak memory 222340 kb
Host smart-a5f70856-cbd2-48c9-ae7e-fa0bf2bf2f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661792912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2661792912
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1980727519
Short name T304
Test name
Test status
Simulation time 223343401 ps
CPU time 8.17 seconds
Started Feb 19 03:12:54 PM PST 24
Finished Feb 19 03:13:06 PM PST 24
Peak memory 211980 kb
Host smart-7ef29388-8cbb-4c6a-ae2d-940f580820ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980727519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1980727519
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2464272042
Short name T987
Test name
Test status
Simulation time 1146361774 ps
CPU time 14.06 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:13:09 PM PST 24
Peak memory 219716 kb
Host smart-b3eeef48-7d21-43cf-95e0-d3cf1c150cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464272042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2464272042
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3985386494
Short name T885
Test name
Test status
Simulation time 157308661 ps
CPU time 4.87 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:12:59 PM PST 24
Peak memory 218216 kb
Host smart-9b727bcd-0722-4bbc-a34a-7812c4e67274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985386494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3985386494
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.113616075
Short name T676
Test name
Test status
Simulation time 222847388 ps
CPU time 2.76 seconds
Started Feb 19 03:12:53 PM PST 24
Finished Feb 19 03:13:01 PM PST 24
Peak memory 207308 kb
Host smart-8caef69d-2d1e-4ac0-b93b-774d911fa1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113616075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.113616075
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.631474418
Short name T617
Test name
Test status
Simulation time 2878832845 ps
CPU time 57.03 seconds
Started Feb 19 03:12:50 PM PST 24
Finished Feb 19 03:13:51 PM PST 24
Peak memory 208560 kb
Host smart-35995e79-f9af-40b1-884c-13019f2622d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631474418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.631474418
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1164466378
Short name T1066
Test name
Test status
Simulation time 965932545 ps
CPU time 5.57 seconds
Started Feb 19 03:12:53 PM PST 24
Finished Feb 19 03:13:02 PM PST 24
Peak memory 208960 kb
Host smart-224a7070-c802-429e-9d13-4eef202937b8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164466378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1164466378
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3867295376
Short name T292
Test name
Test status
Simulation time 73167359 ps
CPU time 2.98 seconds
Started Feb 19 03:12:55 PM PST 24
Finished Feb 19 03:13:02 PM PST 24
Peak memory 206884 kb
Host smart-74c9f775-1340-496e-b62e-2a2b0319687b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867295376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3867295376
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3846966681
Short name T864
Test name
Test status
Simulation time 34099475 ps
CPU time 1.75 seconds
Started Feb 19 03:12:45 PM PST 24
Finished Feb 19 03:12:49 PM PST 24
Peak memory 209132 kb
Host smart-53debea7-cff6-4cab-a4ee-cf0a07d3f5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846966681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3846966681
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3288783907
Short name T1050
Test name
Test status
Simulation time 1182005536 ps
CPU time 6.97 seconds
Started Feb 19 03:12:55 PM PST 24
Finished Feb 19 03:13:06 PM PST 24
Peak memory 207024 kb
Host smart-9c6d7c3d-5c7a-4256-ac61-38864b292b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288783907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3288783907
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3455940274
Short name T908
Test name
Test status
Simulation time 127678107 ps
CPU time 5.26 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:13:00 PM PST 24
Peak memory 219572 kb
Host smart-3dc75ee2-634d-49e4-ad82-b9e70c66183f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455940274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3455940274
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.2242261349
Short name T178
Test name
Test status
Simulation time 765387752 ps
CPU time 7.3 seconds
Started Feb 19 03:12:52 PM PST 24
Finished Feb 19 03:13:03 PM PST 24
Peak memory 222544 kb
Host smart-fd1b0d4c-5901-4257-a42a-73d561067227
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242261349 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.2242261349
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3423195818
Short name T653
Test name
Test status
Simulation time 541903142 ps
CPU time 8.33 seconds
Started Feb 19 03:12:50 PM PST 24
Finished Feb 19 03:13:02 PM PST 24
Peak memory 209372 kb
Host smart-8c6c780b-b05d-4f3f-9577-3e6f9606585e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423195818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3423195818
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1961101784
Short name T842
Test name
Test status
Simulation time 89678502 ps
CPU time 1.4 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:12:55 PM PST 24
Peak memory 208476 kb
Host smart-2d9f461a-068e-41b2-b01e-ba25b6ea413f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961101784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1961101784
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2994184501
Short name T833
Test name
Test status
Simulation time 63483769 ps
CPU time 0.76 seconds
Started Feb 19 03:12:50 PM PST 24
Finished Feb 19 03:12:54 PM PST 24
Peak memory 205816 kb
Host smart-0f40abb9-841f-464d-a7de-4f87da06013d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994184501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2994184501
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1514285713
Short name T796
Test name
Test status
Simulation time 222956654 ps
CPU time 4 seconds
Started Feb 19 03:12:54 PM PST 24
Finished Feb 19 03:13:03 PM PST 24
Peak memory 209996 kb
Host smart-7f708628-e0ca-4ce8-8f5e-aece54c44eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514285713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1514285713
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2892144025
Short name T1043
Test name
Test status
Simulation time 405724369 ps
CPU time 4.74 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:13:00 PM PST 24
Peak memory 220128 kb
Host smart-34764ec4-7230-4fd2-bb27-e22ae003ee3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892144025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2892144025
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2958535097
Short name T965
Test name
Test status
Simulation time 5152292872 ps
CPU time 33.57 seconds
Started Feb 19 03:12:49 PM PST 24
Finished Feb 19 03:13:26 PM PST 24
Peak memory 209204 kb
Host smart-a1ca1ede-a6f0-44e0-b3ed-df1e60e88138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958535097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2958535097
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3977514833
Short name T240
Test name
Test status
Simulation time 1406460957 ps
CPU time 27.22 seconds
Started Feb 19 03:12:53 PM PST 24
Finished Feb 19 03:13:25 PM PST 24
Peak memory 208148 kb
Host smart-245ca952-3cb9-481d-a7ee-069bef191809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977514833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3977514833
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2460610451
Short name T952
Test name
Test status
Simulation time 1152351048 ps
CPU time 9.65 seconds
Started Feb 19 03:12:52 PM PST 24
Finished Feb 19 03:13:05 PM PST 24
Peak memory 208008 kb
Host smart-38c2da98-12c0-4d8a-9c5f-2c7b0981a6e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460610451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2460610451
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2854769397
Short name T547
Test name
Test status
Simulation time 582487751 ps
CPU time 2.56 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:12:57 PM PST 24
Peak memory 206844 kb
Host smart-a97e5287-524d-4cfb-8197-e6d9681f0544
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854769397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2854769397
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3577248415
Short name T971
Test name
Test status
Simulation time 534046592 ps
CPU time 2.77 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:12:57 PM PST 24
Peak memory 208816 kb
Host smart-0b2d72b6-95e9-4c43-bdc2-9d58346d53df
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577248415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3577248415
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3320759759
Short name T214
Test name
Test status
Simulation time 585238302 ps
CPU time 3.08 seconds
Started Feb 19 03:12:53 PM PST 24
Finished Feb 19 03:13:01 PM PST 24
Peak memory 215416 kb
Host smart-55e79e41-500e-4c09-bc8a-90f4c9de9180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320759759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3320759759
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1406220145
Short name T548
Test name
Test status
Simulation time 259021250 ps
CPU time 6.61 seconds
Started Feb 19 03:12:55 PM PST 24
Finished Feb 19 03:13:06 PM PST 24
Peak memory 206860 kb
Host smart-c00902b5-1efc-4a81-83a0-4c2faedccfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406220145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1406220145
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.356893704
Short name T768
Test name
Test status
Simulation time 1004805667 ps
CPU time 11.6 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:13:07 PM PST 24
Peak memory 214956 kb
Host smart-22956852-2c30-4756-aace-60390adba934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356893704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.356893704
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.88601760
Short name T1018
Test name
Test status
Simulation time 2415592054 ps
CPU time 14.44 seconds
Started Feb 19 03:12:55 PM PST 24
Finished Feb 19 03:13:13 PM PST 24
Peak memory 220856 kb
Host smart-5403db1f-d33c-4a43-a2bf-087f7ca1f824
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88601760 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.88601760
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3369287941
Short name T666
Test name
Test status
Simulation time 444751523 ps
CPU time 10.96 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:13:06 PM PST 24
Peak memory 214196 kb
Host smart-5db98dcd-e1c5-4bcc-9a30-71fee2881dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369287941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3369287941
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1834611600
Short name T722
Test name
Test status
Simulation time 732319087 ps
CPU time 3.82 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:12:59 PM PST 24
Peak memory 210232 kb
Host smart-818501ae-b611-4e37-ac68-6855df191a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834611600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1834611600
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2530108474
Short name T816
Test name
Test status
Simulation time 41168613 ps
CPU time 0.69 seconds
Started Feb 19 03:12:55 PM PST 24
Finished Feb 19 03:13:00 PM PST 24
Peak memory 205880 kb
Host smart-644f986e-78d0-47da-b151-7430a13722cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530108474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2530108474
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2404775271
Short name T680
Test name
Test status
Simulation time 8922936590 ps
CPU time 55.93 seconds
Started Feb 19 03:12:59 PM PST 24
Finished Feb 19 03:13:57 PM PST 24
Peak memory 222400 kb
Host smart-c9b9fd60-b48d-4068-a286-56650a467447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404775271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2404775271
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2267179858
Short name T730
Test name
Test status
Simulation time 122185442 ps
CPU time 1.93 seconds
Started Feb 19 03:12:59 PM PST 24
Finished Feb 19 03:13:03 PM PST 24
Peak memory 207328 kb
Host smart-2d1ad36c-b180-4415-a822-ea11a9b304b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267179858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2267179858
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2556588788
Short name T81
Test name
Test status
Simulation time 322818078 ps
CPU time 10.81 seconds
Started Feb 19 03:12:56 PM PST 24
Finished Feb 19 03:13:11 PM PST 24
Peak memory 209232 kb
Host smart-d8246511-455e-4c45-b54f-d4a274576e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556588788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2556588788
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2888686719
Short name T305
Test name
Test status
Simulation time 237844553 ps
CPU time 4.2 seconds
Started Feb 19 03:12:55 PM PST 24
Finished Feb 19 03:13:03 PM PST 24
Peak memory 210076 kb
Host smart-47720374-1cbe-4bf3-b144-3b36d3f7b036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888686719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2888686719
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3864439724
Short name T704
Test name
Test status
Simulation time 134596908 ps
CPU time 3.83 seconds
Started Feb 19 03:13:04 PM PST 24
Finished Feb 19 03:13:10 PM PST 24
Peak memory 209820 kb
Host smart-46e4247c-de5a-48ca-bdf7-60dac16e75fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864439724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3864439724
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3007785708
Short name T981
Test name
Test status
Simulation time 1526740912 ps
CPU time 16 seconds
Started Feb 19 03:12:53 PM PST 24
Finished Feb 19 03:13:14 PM PST 24
Peak memory 214252 kb
Host smart-b06301e8-f9b4-4d4e-82f1-243efa1e7c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007785708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3007785708
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3587132726
Short name T968
Test name
Test status
Simulation time 72053352 ps
CPU time 2.64 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:12:57 PM PST 24
Peak memory 208660 kb
Host smart-fd5ed698-678a-4433-8db3-62d25919806f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587132726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3587132726
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.49051922
Short name T706
Test name
Test status
Simulation time 307216152 ps
CPU time 9.29 seconds
Started Feb 19 03:13:04 PM PST 24
Finished Feb 19 03:13:15 PM PST 24
Peak memory 208012 kb
Host smart-7ca8b113-875d-433b-97ff-7beafb222f25
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49051922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.49051922
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.238455211
Short name T327
Test name
Test status
Simulation time 31634921 ps
CPU time 2.18 seconds
Started Feb 19 03:12:54 PM PST 24
Finished Feb 19 03:13:01 PM PST 24
Peak memory 206852 kb
Host smart-37e98404-cab6-445a-982f-f3c47116c19c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238455211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.238455211
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3304931424
Short name T127
Test name
Test status
Simulation time 1302228059 ps
CPU time 30.67 seconds
Started Feb 19 03:13:04 PM PST 24
Finished Feb 19 03:13:37 PM PST 24
Peak memory 208424 kb
Host smart-3d566c95-9503-4c84-b32d-220ba0dd8b4a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304931424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3304931424
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3455775949
Short name T319
Test name
Test status
Simulation time 85258992 ps
CPU time 2.59 seconds
Started Feb 19 03:12:56 PM PST 24
Finished Feb 19 03:13:03 PM PST 24
Peak memory 209820 kb
Host smart-f2239bdf-a823-403a-b22c-bd8fa4df232e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455775949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3455775949
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.4199665588
Short name T900
Test name
Test status
Simulation time 292803074 ps
CPU time 4.52 seconds
Started Feb 19 03:12:51 PM PST 24
Finished Feb 19 03:12:59 PM PST 24
Peak memory 206704 kb
Host smart-c4032481-8a76-4a8b-a24a-96843b808d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199665588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.4199665588
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.4069849531
Short name T272
Test name
Test status
Simulation time 356476872 ps
CPU time 14.3 seconds
Started Feb 19 03:12:54 PM PST 24
Finished Feb 19 03:13:12 PM PST 24
Peak memory 216348 kb
Host smart-318a0f01-e781-4591-b382-acba97e786e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069849531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.4069849531
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.610488683
Short name T343
Test name
Test status
Simulation time 139323950 ps
CPU time 6.17 seconds
Started Feb 19 03:12:57 PM PST 24
Finished Feb 19 03:13:07 PM PST 24
Peak memory 222528 kb
Host smart-06986a47-19d0-4631-a458-a25bb7edee2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610488683 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.610488683
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1484581473
Short name T835
Test name
Test status
Simulation time 145960778 ps
CPU time 4.57 seconds
Started Feb 19 03:12:53 PM PST 24
Finished Feb 19 03:13:02 PM PST 24
Peak memory 207468 kb
Host smart-ec385ae8-63bd-44ec-b613-228ac7912385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484581473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1484581473
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.175439438
Short name T844
Test name
Test status
Simulation time 25831350 ps
CPU time 1.33 seconds
Started Feb 19 03:12:56 PM PST 24
Finished Feb 19 03:13:01 PM PST 24
Peak memory 209692 kb
Host smart-0e6b3735-9d39-4dca-ae09-0e5eedd3f78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175439438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.175439438
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1878879271
Short name T17
Test name
Test status
Simulation time 37424545 ps
CPU time 0.72 seconds
Started Feb 19 03:13:11 PM PST 24
Finished Feb 19 03:13:16 PM PST 24
Peak memory 205824 kb
Host smart-8268cd06-59f7-4c88-a7ff-27b7aba57dfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878879271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1878879271
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1628897900
Short name T5
Test name
Test status
Simulation time 169046507 ps
CPU time 5.91 seconds
Started Feb 19 03:13:00 PM PST 24
Finished Feb 19 03:13:08 PM PST 24
Peak memory 219476 kb
Host smart-47e25b97-7693-4c70-8c4e-bbcbe3795a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628897900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1628897900
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.4154854500
Short name T755
Test name
Test status
Simulation time 235396721 ps
CPU time 2.96 seconds
Started Feb 19 03:13:01 PM PST 24
Finished Feb 19 03:13:06 PM PST 24
Peak memory 210152 kb
Host smart-29dabc17-9155-448d-bd95-eed7ee0a22aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154854500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.4154854500
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1565480865
Short name T306
Test name
Test status
Simulation time 86909400 ps
CPU time 4.48 seconds
Started Feb 19 03:13:07 PM PST 24
Finished Feb 19 03:13:12 PM PST 24
Peak memory 211072 kb
Host smart-5e81676a-8b11-419f-828f-9583f0b294da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565480865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1565480865
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.391110552
Short name T206
Test name
Test status
Simulation time 541457280 ps
CPU time 3.46 seconds
Started Feb 19 03:13:04 PM PST 24
Finished Feb 19 03:13:09 PM PST 24
Peak memory 218996 kb
Host smart-20fa6f16-bf0a-4570-a367-5772a5d0d273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391110552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.391110552
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.736418633
Short name T322
Test name
Test status
Simulation time 228647773 ps
CPU time 8.05 seconds
Started Feb 19 03:13:00 PM PST 24
Finished Feb 19 03:13:10 PM PST 24
Peak memory 218068 kb
Host smart-e2dc9200-bb17-4970-9e90-5f429510ec37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736418633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.736418633
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3695708723
Short name T18
Test name
Test status
Simulation time 44935895 ps
CPU time 2.58 seconds
Started Feb 19 03:13:04 PM PST 24
Finished Feb 19 03:13:09 PM PST 24
Peak memory 207988 kb
Host smart-23fcbe95-009b-48b0-91cb-750cdb6a8d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695708723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3695708723
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.984781003
Short name T1047
Test name
Test status
Simulation time 2792068914 ps
CPU time 21.6 seconds
Started Feb 19 03:13:04 PM PST 24
Finished Feb 19 03:13:28 PM PST 24
Peak memory 207960 kb
Host smart-f8b76fc2-18ce-49b4-bc28-0976f1fd20bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984781003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.984781003
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2894763118
Short name T293
Test name
Test status
Simulation time 71929596 ps
CPU time 3.11 seconds
Started Feb 19 03:13:11 PM PST 24
Finished Feb 19 03:13:19 PM PST 24
Peak memory 206348 kb
Host smart-64249c32-1f4e-40f4-98f3-f8450f6fb297
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894763118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2894763118
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3468121620
Short name T975
Test name
Test status
Simulation time 43878098 ps
CPU time 2.66 seconds
Started Feb 19 03:13:04 PM PST 24
Finished Feb 19 03:13:09 PM PST 24
Peak memory 207272 kb
Host smart-d2f30e10-d9d4-42d6-9d55-d91ae0a6b01d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468121620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3468121620
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2724060572
Short name T380
Test name
Test status
Simulation time 128496576 ps
CPU time 3.45 seconds
Started Feb 19 03:13:02 PM PST 24
Finished Feb 19 03:13:06 PM PST 24
Peak memory 208888 kb
Host smart-03fdbad4-c1ca-4208-aa3f-7ee731410c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724060572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2724060572
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1952245428
Short name T959
Test name
Test status
Simulation time 10503103813 ps
CPU time 25.94 seconds
Started Feb 19 03:12:56 PM PST 24
Finished Feb 19 03:13:26 PM PST 24
Peak memory 208196 kb
Host smart-f9c32277-cf0b-42e2-b06e-bad7cb6e6bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952245428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1952245428
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2885260508
Short name T798
Test name
Test status
Simulation time 146621532 ps
CPU time 7.39 seconds
Started Feb 19 03:13:04 PM PST 24
Finished Feb 19 03:13:13 PM PST 24
Peak memory 220276 kb
Host smart-242f7282-8d6e-4107-ad80-9b7b57674033
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885260508 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2885260508
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3294315883
Short name T693
Test name
Test status
Simulation time 452585930 ps
CPU time 4.11 seconds
Started Feb 19 03:12:59 PM PST 24
Finished Feb 19 03:13:05 PM PST 24
Peak memory 209028 kb
Host smart-86818da3-5f8c-4c90-ba88-e49cb17f8f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294315883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3294315883
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2580514523
Short name T631
Test name
Test status
Simulation time 159032125 ps
CPU time 2.77 seconds
Started Feb 19 03:13:11 PM PST 24
Finished Feb 19 03:13:19 PM PST 24
Peak memory 209376 kb
Host smart-aa7e33cc-5975-4bc6-93dd-178f2a808d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580514523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2580514523
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1569051346
Short name T954
Test name
Test status
Simulation time 12451403 ps
CPU time 0.85 seconds
Started Feb 19 03:09:28 PM PST 24
Finished Feb 19 03:09:38 PM PST 24
Peak memory 205792 kb
Host smart-b8e72699-830b-44e4-9b0b-fda3214b15f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569051346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1569051346
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2325557029
Short name T405
Test name
Test status
Simulation time 30168963 ps
CPU time 2.62 seconds
Started Feb 19 03:09:20 PM PST 24
Finished Feb 19 03:09:25 PM PST 24
Peak memory 214312 kb
Host smart-32fdbe62-96d6-4187-a2a1-6fc9c832b101
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2325557029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2325557029
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1771641540
Short name T29
Test name
Test status
Simulation time 4317164822 ps
CPU time 14.96 seconds
Started Feb 19 03:09:23 PM PST 24
Finished Feb 19 03:09:40 PM PST 24
Peak memory 218328 kb
Host smart-79626288-0d79-4c97-92a5-78253187a39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771641540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1771641540
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.203076689
Short name T329
Test name
Test status
Simulation time 281877856 ps
CPU time 4.47 seconds
Started Feb 19 03:09:16 PM PST 24
Finished Feb 19 03:09:23 PM PST 24
Peak memory 214400 kb
Host smart-541f2de6-bad5-40b2-a89f-cbc28833fe49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203076689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.203076689
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1250747412
Short name T300
Test name
Test status
Simulation time 1670696493 ps
CPU time 18.78 seconds
Started Feb 19 03:09:19 PM PST 24
Finished Feb 19 03:09:39 PM PST 24
Peak memory 218420 kb
Host smart-da66a1a6-6053-4e69-85bd-dbb2c35f703e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250747412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1250747412
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3492888465
Short name T16
Test name
Test status
Simulation time 259948990 ps
CPU time 3.9 seconds
Started Feb 19 03:09:19 PM PST 24
Finished Feb 19 03:09:25 PM PST 24
Peak memory 222576 kb
Host smart-88b746c9-ba05-4930-808c-2bff5ae576df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492888465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3492888465
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2230283287
Short name T976
Test name
Test status
Simulation time 78990734 ps
CPU time 2.87 seconds
Started Feb 19 03:09:21 PM PST 24
Finished Feb 19 03:09:26 PM PST 24
Peak memory 210252 kb
Host smart-0ebc0caf-fc3b-4f19-b587-b01a71ff1d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230283287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2230283287
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1464284104
Short name T324
Test name
Test status
Simulation time 34178789 ps
CPU time 2.33 seconds
Started Feb 19 03:09:21 PM PST 24
Finished Feb 19 03:09:25 PM PST 24
Peak memory 207252 kb
Host smart-2c973499-91ec-4063-a972-f0e4372870aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464284104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1464284104
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1903080311
Short name T784
Test name
Test status
Simulation time 119776905 ps
CPU time 2.57 seconds
Started Feb 19 03:09:21 PM PST 24
Finished Feb 19 03:09:26 PM PST 24
Peak memory 208508 kb
Host smart-b0c22e70-3d2d-4312-a261-6fb0bdc2885c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903080311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1903080311
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1455421387
Short name T692
Test name
Test status
Simulation time 3744502374 ps
CPU time 56.59 seconds
Started Feb 19 03:09:23 PM PST 24
Finished Feb 19 03:10:21 PM PST 24
Peak memory 208448 kb
Host smart-2f08128e-5b59-4ff1-be6f-5654931d6f56
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455421387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1455421387
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.117874086
Short name T638
Test name
Test status
Simulation time 191824168 ps
CPU time 3.21 seconds
Started Feb 19 03:09:16 PM PST 24
Finished Feb 19 03:09:21 PM PST 24
Peak memory 206876 kb
Host smart-0c670dec-f7ed-4d25-bada-167ad6b79077
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117874086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.117874086
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3704056022
Short name T284
Test name
Test status
Simulation time 110693793 ps
CPU time 2.59 seconds
Started Feb 19 03:09:22 PM PST 24
Finished Feb 19 03:09:26 PM PST 24
Peak memory 209912 kb
Host smart-58f7d4c1-9dc9-4325-b58d-25d1b508c57d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704056022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3704056022
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2406958063
Short name T1022
Test name
Test status
Simulation time 186703119 ps
CPU time 5.3 seconds
Started Feb 19 03:09:25 PM PST 24
Finished Feb 19 03:09:38 PM PST 24
Peak memory 208448 kb
Host smart-e0e8d6b2-d497-46c3-b5e9-f32726ec1ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406958063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2406958063
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2798536467
Short name T1061
Test name
Test status
Simulation time 515009960 ps
CPU time 10.8 seconds
Started Feb 19 03:09:29 PM PST 24
Finished Feb 19 03:09:49 PM PST 24
Peak memory 222556 kb
Host smart-156df30c-ef83-4189-8283-4970f11eecf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798536467 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2798536467
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.607595471
Short name T260
Test name
Test status
Simulation time 197714339 ps
CPU time 3.39 seconds
Started Feb 19 03:09:20 PM PST 24
Finished Feb 19 03:09:25 PM PST 24
Peak memory 207644 kb
Host smart-aa633db2-2ca5-49b0-bdf0-76f82d3b24c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607595471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.607595471
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2030203274
Short name T1059
Test name
Test status
Simulation time 101697581 ps
CPU time 1.91 seconds
Started Feb 19 03:09:21 PM PST 24
Finished Feb 19 03:09:25 PM PST 24
Peak memory 210188 kb
Host smart-57b3c3aa-6a0e-4e3e-a701-0ad54c77eb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030203274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2030203274
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2887495641
Short name T413
Test name
Test status
Simulation time 15245231 ps
CPU time 0.78 seconds
Started Feb 19 03:13:07 PM PST 24
Finished Feb 19 03:13:09 PM PST 24
Peak memory 205820 kb
Host smart-b22cb6f9-4dac-468d-9017-0f948ca06feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887495641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2887495641
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2898756798
Short name T218
Test name
Test status
Simulation time 35338990 ps
CPU time 2.46 seconds
Started Feb 19 03:13:10 PM PST 24
Finished Feb 19 03:13:17 PM PST 24
Peak memory 215028 kb
Host smart-2f3d344a-4f7c-4155-84ac-075fe34cf425
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2898756798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2898756798
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.859585688
Short name T50
Test name
Test status
Simulation time 165588136 ps
CPU time 4.12 seconds
Started Feb 19 03:13:09 PM PST 24
Finished Feb 19 03:13:17 PM PST 24
Peak memory 210472 kb
Host smart-1fcb511f-1183-4aaf-bee9-eebe06a9d19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859585688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.859585688
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2111271271
Short name T893
Test name
Test status
Simulation time 127064350 ps
CPU time 3.18 seconds
Started Feb 19 03:13:08 PM PST 24
Finished Feb 19 03:13:15 PM PST 24
Peak memory 209704 kb
Host smart-f4415688-905a-4405-82c8-cc0db91d606d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111271271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2111271271
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.535461349
Short name T249
Test name
Test status
Simulation time 199496567 ps
CPU time 7.93 seconds
Started Feb 19 03:13:07 PM PST 24
Finished Feb 19 03:13:16 PM PST 24
Peak memory 222440 kb
Host smart-a42c7847-cd4c-47ea-bf18-ae37d45a9b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535461349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.535461349
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.127210434
Short name T608
Test name
Test status
Simulation time 241497926 ps
CPU time 3.16 seconds
Started Feb 19 03:13:04 PM PST 24
Finished Feb 19 03:13:10 PM PST 24
Peak memory 219340 kb
Host smart-55df1f9f-edc5-4c5d-82b2-6f0802f390e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127210434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.127210434
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1418147464
Short name T385
Test name
Test status
Simulation time 67127208 ps
CPU time 4.04 seconds
Started Feb 19 03:13:03 PM PST 24
Finished Feb 19 03:13:09 PM PST 24
Peak memory 218528 kb
Host smart-a0fadbd6-1adf-4e84-a1f1-b9948ed893b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418147464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1418147464
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3934437182
Short name T342
Test name
Test status
Simulation time 200785175 ps
CPU time 3 seconds
Started Feb 19 03:13:06 PM PST 24
Finished Feb 19 03:13:10 PM PST 24
Peak memory 207084 kb
Host smart-5a99e6e6-a0f3-4e64-8134-01d6dec4930d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934437182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3934437182
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1082939056
Short name T753
Test name
Test status
Simulation time 108581104 ps
CPU time 3.79 seconds
Started Feb 19 03:13:10 PM PST 24
Finished Feb 19 03:13:19 PM PST 24
Peak memory 208920 kb
Host smart-73b39f39-9e20-4d52-a47d-b737acdbab1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082939056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1082939056
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2477612654
Short name T662
Test name
Test status
Simulation time 10769785750 ps
CPU time 53.73 seconds
Started Feb 19 03:13:11 PM PST 24
Finished Feb 19 03:14:10 PM PST 24
Peak memory 207212 kb
Host smart-1a3682b3-870d-450a-8822-4f74ce086dcb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477612654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2477612654
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2297665067
Short name T820
Test name
Test status
Simulation time 176522374 ps
CPU time 5.23 seconds
Started Feb 19 03:13:08 PM PST 24
Finished Feb 19 03:13:14 PM PST 24
Peak memory 208952 kb
Host smart-e063746f-78a3-42c1-b4e0-8cda016003eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297665067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2297665067
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2813818854
Short name T905
Test name
Test status
Simulation time 3317789740 ps
CPU time 4.08 seconds
Started Feb 19 03:13:11 PM PST 24
Finished Feb 19 03:13:19 PM PST 24
Peak memory 208696 kb
Host smart-85f48f9d-8a31-45a1-96ca-68188624ca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813818854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2813818854
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1267744041
Short name T1026
Test name
Test status
Simulation time 53614399 ps
CPU time 2.66 seconds
Started Feb 19 03:13:02 PM PST 24
Finished Feb 19 03:13:06 PM PST 24
Peak memory 208096 kb
Host smart-604634c1-312b-4f97-9c7a-ff445251b411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267744041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1267744041
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2902055817
Short name T917
Test name
Test status
Simulation time 796428589 ps
CPU time 19.71 seconds
Started Feb 19 03:13:14 PM PST 24
Finished Feb 19 03:13:39 PM PST 24
Peak memory 220476 kb
Host smart-19248f25-b19e-4b0e-b49c-f3e2574e3ed8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902055817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2902055817
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3533725487
Short name T96
Test name
Test status
Simulation time 993243530 ps
CPU time 9.8 seconds
Started Feb 19 03:13:10 PM PST 24
Finished Feb 19 03:13:24 PM PST 24
Peak memory 220520 kb
Host smart-b6809527-7c84-465b-a665-4d601fdc79e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533725487 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3533725487
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.913112312
Short name T563
Test name
Test status
Simulation time 108631539 ps
CPU time 4.71 seconds
Started Feb 19 03:13:08 PM PST 24
Finished Feb 19 03:13:14 PM PST 24
Peak memory 208676 kb
Host smart-c0129b83-d724-4a2a-a971-a1395d565064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913112312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.913112312
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.711075578
Short name T634
Test name
Test status
Simulation time 68851778 ps
CPU time 2.31 seconds
Started Feb 19 03:13:11 PM PST 24
Finished Feb 19 03:13:18 PM PST 24
Peak memory 210348 kb
Host smart-82fcb329-11a8-462e-afc6-a88a78d1a187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711075578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.711075578
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1897966624
Short name T1024
Test name
Test status
Simulation time 11620461 ps
CPU time 0.73 seconds
Started Feb 19 03:13:22 PM PST 24
Finished Feb 19 03:13:27 PM PST 24
Peak memory 205808 kb
Host smart-ea5fdc55-1450-4a7d-8118-bee5642ca39f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897966624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1897966624
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1418072304
Short name T915
Test name
Test status
Simulation time 108844283 ps
CPU time 2.84 seconds
Started Feb 19 03:13:22 PM PST 24
Finished Feb 19 03:13:29 PM PST 24
Peak memory 222868 kb
Host smart-0894ceae-cf5c-49e9-bb60-fda48d46c73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418072304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1418072304
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.4260365981
Short name T790
Test name
Test status
Simulation time 113100651 ps
CPU time 3.62 seconds
Started Feb 19 03:13:16 PM PST 24
Finished Feb 19 03:13:25 PM PST 24
Peak memory 208784 kb
Host smart-b7db2bf9-aa9c-4cf3-97a6-3ad950dafbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260365981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.4260365981
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3510412094
Short name T732
Test name
Test status
Simulation time 466041878 ps
CPU time 5.97 seconds
Started Feb 19 03:13:15 PM PST 24
Finished Feb 19 03:13:26 PM PST 24
Peak memory 209292 kb
Host smart-169ac477-bd1e-42e5-ba4b-19978675885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510412094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3510412094
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.4013100181
Short name T994
Test name
Test status
Simulation time 390933255 ps
CPU time 8.8 seconds
Started Feb 19 03:13:16 PM PST 24
Finished Feb 19 03:13:30 PM PST 24
Peak memory 214556 kb
Host smart-dce794ee-7ed9-4268-95e6-ded1636b024c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013100181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.4013100181
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1424932600
Short name T45
Test name
Test status
Simulation time 434884910 ps
CPU time 7.21 seconds
Started Feb 19 03:13:11 PM PST 24
Finished Feb 19 03:13:24 PM PST 24
Peak memory 220316 kb
Host smart-6a763b81-04e6-4ab1-9836-1805128d1343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424932600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1424932600
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2975259336
Short name T807
Test name
Test status
Simulation time 49603252 ps
CPU time 2.66 seconds
Started Feb 19 03:13:17 PM PST 24
Finished Feb 19 03:13:25 PM PST 24
Peak memory 207412 kb
Host smart-57d85640-72e3-40ed-be69-470cf96fe444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975259336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2975259336
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.4198355006
Short name T698
Test name
Test status
Simulation time 41313571 ps
CPU time 1.83 seconds
Started Feb 19 03:13:14 PM PST 24
Finished Feb 19 03:13:21 PM PST 24
Peak memory 206820 kb
Host smart-4afb4daf-ef82-47d9-a3a5-c2b10e30da87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198355006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.4198355006
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1822204634
Short name T593
Test name
Test status
Simulation time 61390675 ps
CPU time 2.7 seconds
Started Feb 19 03:13:09 PM PST 24
Finished Feb 19 03:13:16 PM PST 24
Peak memory 208132 kb
Host smart-192d60e3-a0cb-40b2-85da-a6064aa3332e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822204634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1822204634
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3541389061
Short name T688
Test name
Test status
Simulation time 216963587 ps
CPU time 3.09 seconds
Started Feb 19 03:13:09 PM PST 24
Finished Feb 19 03:13:17 PM PST 24
Peak memory 206748 kb
Host smart-23237032-dce5-4e96-bb32-4cd16109d24e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541389061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3541389061
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2310052668
Short name T256
Test name
Test status
Simulation time 7179506971 ps
CPU time 48.19 seconds
Started Feb 19 03:13:08 PM PST 24
Finished Feb 19 03:14:00 PM PST 24
Peak memory 209024 kb
Host smart-35c6b1d2-6e9b-46a8-8efc-bae1cc9c1046
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310052668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2310052668
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3746100730
Short name T690
Test name
Test status
Simulation time 56166205 ps
CPU time 3.16 seconds
Started Feb 19 03:13:14 PM PST 24
Finished Feb 19 03:13:22 PM PST 24
Peak memory 209052 kb
Host smart-3f874f51-9c9a-45cf-b10b-71f27e17755a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746100730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3746100730
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3522827635
Short name T699
Test name
Test status
Simulation time 82514509 ps
CPU time 3.36 seconds
Started Feb 19 03:13:12 PM PST 24
Finished Feb 19 03:13:20 PM PST 24
Peak memory 208532 kb
Host smart-2c32b853-f5d3-4698-9de1-e63dc726fef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522827635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3522827635
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2546097827
Short name T613
Test name
Test status
Simulation time 361191629 ps
CPU time 15.63 seconds
Started Feb 19 03:13:21 PM PST 24
Finished Feb 19 03:13:41 PM PST 24
Peak memory 215000 kb
Host smart-a941bd19-0a62-44ec-b810-a2b1105f17f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546097827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2546097827
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3361452634
Short name T924
Test name
Test status
Simulation time 215386457 ps
CPU time 12.29 seconds
Started Feb 19 03:13:23 PM PST 24
Finished Feb 19 03:13:39 PM PST 24
Peak memory 222592 kb
Host smart-a27de803-51ff-482e-bcca-b52e6ba99a51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361452634 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3361452634
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3189545635
Short name T231
Test name
Test status
Simulation time 1737485821 ps
CPU time 9.26 seconds
Started Feb 19 03:13:16 PM PST 24
Finished Feb 19 03:13:31 PM PST 24
Peak memory 218376 kb
Host smart-33843730-9274-436c-9f18-267bf9e57c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189545635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3189545635
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.4080336359
Short name T655
Test name
Test status
Simulation time 635210513 ps
CPU time 4.25 seconds
Started Feb 19 03:13:23 PM PST 24
Finished Feb 19 03:13:31 PM PST 24
Peak memory 209780 kb
Host smart-fa0f208b-3aa4-4deb-8139-0e7cb8c965ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080336359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.4080336359
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1333484636
Short name T1053
Test name
Test status
Simulation time 15567647 ps
CPU time 0.77 seconds
Started Feb 19 03:13:33 PM PST 24
Finished Feb 19 03:13:44 PM PST 24
Peak memory 205880 kb
Host smart-44106d29-b961-42f8-8739-085fa63c6630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333484636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1333484636
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2031714738
Short name T875
Test name
Test status
Simulation time 193079596 ps
CPU time 7.9 seconds
Started Feb 19 03:13:34 PM PST 24
Finished Feb 19 03:13:52 PM PST 24
Peak memory 218432 kb
Host smart-3245171b-4eac-4bbb-964e-899a59d22d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031714738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2031714738
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.314831018
Short name T1031
Test name
Test status
Simulation time 74342270 ps
CPU time 3.74 seconds
Started Feb 19 03:13:17 PM PST 24
Finished Feb 19 03:13:27 PM PST 24
Peak memory 207676 kb
Host smart-80f0fa88-fa53-4aa2-997b-ab25f5ea4085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314831018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.314831018
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2180073068
Short name T934
Test name
Test status
Simulation time 1739894853 ps
CPU time 11.91 seconds
Started Feb 19 03:13:24 PM PST 24
Finished Feb 19 03:13:40 PM PST 24
Peak memory 214412 kb
Host smart-1626eebc-2a8b-4909-aa56-45e7cef46457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180073068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2180073068
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2549474704
Short name T308
Test name
Test status
Simulation time 222998514 ps
CPU time 4.06 seconds
Started Feb 19 03:13:25 PM PST 24
Finished Feb 19 03:13:33 PM PST 24
Peak memory 222376 kb
Host smart-b8ee87f1-fee2-4a66-87c1-b1a6e793d805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549474704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2549474704
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1933444034
Short name T192
Test name
Test status
Simulation time 146267300 ps
CPU time 3.64 seconds
Started Feb 19 03:13:16 PM PST 24
Finished Feb 19 03:13:25 PM PST 24
Peak memory 214308 kb
Host smart-5c09cb22-345a-4fa5-a3eb-c1b04a701d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933444034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1933444034
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3249851361
Short name T951
Test name
Test status
Simulation time 198581638 ps
CPU time 4.93 seconds
Started Feb 19 03:13:16 PM PST 24
Finished Feb 19 03:13:27 PM PST 24
Peak memory 206732 kb
Host smart-ccb8ec93-c8f5-4b93-b937-2173b03407c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249851361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3249851361
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1046818689
Short name T714
Test name
Test status
Simulation time 2681623232 ps
CPU time 9.19 seconds
Started Feb 19 03:13:23 PM PST 24
Finished Feb 19 03:13:36 PM PST 24
Peak memory 208752 kb
Host smart-681b7da5-43db-41bd-8be9-ef08d1d33b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046818689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1046818689
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2540154465
Short name T708
Test name
Test status
Simulation time 457072780 ps
CPU time 2.87 seconds
Started Feb 19 03:13:24 PM PST 24
Finished Feb 19 03:13:30 PM PST 24
Peak memory 206940 kb
Host smart-c18a096d-a020-4370-a94f-5ca74388b42f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540154465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2540154465
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.132516628
Short name T1070
Test name
Test status
Simulation time 113792811 ps
CPU time 2.49 seconds
Started Feb 19 03:13:17 PM PST 24
Finished Feb 19 03:13:25 PM PST 24
Peak memory 206732 kb
Host smart-589a930b-a180-47a9-b6ee-de9a7d5182eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132516628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.132516628
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2023464356
Short name T590
Test name
Test status
Simulation time 614912562 ps
CPU time 3.02 seconds
Started Feb 19 03:13:17 PM PST 24
Finished Feb 19 03:13:25 PM PST 24
Peak memory 206764 kb
Host smart-f0431cfa-7129-449f-87e9-243de274693e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023464356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2023464356
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1988094219
Short name T950
Test name
Test status
Simulation time 2792240128 ps
CPU time 24.61 seconds
Started Feb 19 03:13:34 PM PST 24
Finished Feb 19 03:14:08 PM PST 24
Peak memory 209164 kb
Host smart-ab7965fa-4c25-41da-8826-7548f814972a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988094219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1988094219
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.4113270687
Short name T799
Test name
Test status
Simulation time 201484405 ps
CPU time 2.67 seconds
Started Feb 19 03:13:17 PM PST 24
Finished Feb 19 03:13:25 PM PST 24
Peak memory 206744 kb
Host smart-219d411f-2dcc-452a-b0cb-0ba593bd0c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113270687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4113270687
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.478493760
Short name T986
Test name
Test status
Simulation time 531840484 ps
CPU time 0.91 seconds
Started Feb 19 03:13:23 PM PST 24
Finished Feb 19 03:13:28 PM PST 24
Peak memory 205804 kb
Host smart-e7141552-5c38-4609-86ec-955749530068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478493760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.478493760
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.28009108
Short name T364
Test name
Test status
Simulation time 179176252 ps
CPU time 11.33 seconds
Started Feb 19 03:13:28 PM PST 24
Finished Feb 19 03:13:44 PM PST 24
Peak memory 222664 kb
Host smart-be5f1548-11a3-4c14-bb4e-bbd0dd5b3d99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28009108 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.28009108
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3759688494
Short name T887
Test name
Test status
Simulation time 242717449 ps
CPU time 7.56 seconds
Started Feb 19 03:13:17 PM PST 24
Finished Feb 19 03:13:29 PM PST 24
Peak memory 207232 kb
Host smart-d925be4c-8f85-4f2a-87c5-3fbbc2d13da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759688494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3759688494
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.110230403
Short name T619
Test name
Test status
Simulation time 44953483 ps
CPU time 2.15 seconds
Started Feb 19 03:13:24 PM PST 24
Finished Feb 19 03:13:30 PM PST 24
Peak memory 210112 kb
Host smart-3829751c-881e-4c75-b4d4-24a8e50b4fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110230403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.110230403
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.605343308
Short name T1008
Test name
Test status
Simulation time 21742702 ps
CPU time 0.85 seconds
Started Feb 19 03:13:31 PM PST 24
Finished Feb 19 03:13:39 PM PST 24
Peak memory 205884 kb
Host smart-944656c2-5346-4f1e-ad46-19afe0a08b68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605343308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.605343308
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.422762198
Short name T406
Test name
Test status
Simulation time 927033313 ps
CPU time 6.53 seconds
Started Feb 19 03:13:28 PM PST 24
Finished Feb 19 03:13:39 PM PST 24
Peak memory 214420 kb
Host smart-9a6735cd-e6c5-41fb-8665-5c73378902a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=422762198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.422762198
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.995843598
Short name T384
Test name
Test status
Simulation time 897773465 ps
CPU time 11.07 seconds
Started Feb 19 03:13:39 PM PST 24
Finished Feb 19 03:14:03 PM PST 24
Peak memory 209088 kb
Host smart-aa7b0835-6e56-4b7b-8aba-fe0d93d0f4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995843598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.995843598
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.266504012
Short name T315
Test name
Test status
Simulation time 248092741 ps
CPU time 5.1 seconds
Started Feb 19 03:13:31 PM PST 24
Finished Feb 19 03:13:44 PM PST 24
Peak memory 218280 kb
Host smart-acce4c52-04ca-4111-950e-f2dc0cd88e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266504012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.266504012
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.258351905
Short name T193
Test name
Test status
Simulation time 110105885 ps
CPU time 3.39 seconds
Started Feb 19 03:13:26 PM PST 24
Finished Feb 19 03:13:33 PM PST 24
Peak memory 216040 kb
Host smart-bbce7b0a-1436-44fe-abb1-a63e93c35f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258351905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.258351905
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1959671900
Short name T1030
Test name
Test status
Simulation time 90661216 ps
CPU time 4.39 seconds
Started Feb 19 03:13:29 PM PST 24
Finished Feb 19 03:13:40 PM PST 24
Peak memory 207480 kb
Host smart-442e67ba-83e8-4901-a899-e4043c4c8831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959671900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1959671900
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3134262185
Short name T591
Test name
Test status
Simulation time 61866901 ps
CPU time 3.11 seconds
Started Feb 19 03:13:28 PM PST 24
Finished Feb 19 03:13:36 PM PST 24
Peak memory 206816 kb
Host smart-fbffef09-1dc7-4193-8d75-d7ddac7a0d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134262185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3134262185
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1047964876
Short name T636
Test name
Test status
Simulation time 342157912 ps
CPU time 3.25 seconds
Started Feb 19 03:13:28 PM PST 24
Finished Feb 19 03:13:35 PM PST 24
Peak memory 206868 kb
Host smart-db089e98-5dca-4409-bf76-05d6e4b39bdb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047964876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1047964876
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.66043781
Short name T925
Test name
Test status
Simulation time 6012293714 ps
CPU time 44.44 seconds
Started Feb 19 03:13:26 PM PST 24
Finished Feb 19 03:14:14 PM PST 24
Peak memory 208632 kb
Host smart-780ab1ee-2e7f-4c17-9600-55e1770d3b42
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66043781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.66043781
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2336365723
Short name T863
Test name
Test status
Simulation time 156673908 ps
CPU time 2.7 seconds
Started Feb 19 03:13:27 PM PST 24
Finished Feb 19 03:13:34 PM PST 24
Peak memory 207872 kb
Host smart-3629aa21-85f2-448b-8022-2d5b8f820d4a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336365723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2336365723
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.969444863
Short name T683
Test name
Test status
Simulation time 361003283 ps
CPU time 2.86 seconds
Started Feb 19 03:13:25 PM PST 24
Finished Feb 19 03:13:32 PM PST 24
Peak memory 207900 kb
Host smart-18430b87-d8af-4ee1-a26b-39dc179ac8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969444863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.969444863
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.448624650
Short name T382
Test name
Test status
Simulation time 137702152 ps
CPU time 2.21 seconds
Started Feb 19 03:13:26 PM PST 24
Finished Feb 19 03:13:32 PM PST 24
Peak memory 206804 kb
Host smart-97e14032-4196-4d82-8e5a-2a52bfd6bfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448624650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.448624650
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3789800700
Short name T785
Test name
Test status
Simulation time 228866780 ps
CPU time 9.38 seconds
Started Feb 19 03:13:26 PM PST 24
Finished Feb 19 03:13:38 PM PST 24
Peak memory 214924 kb
Host smart-7bdcfe4b-2978-46de-b2a1-ebad0315eed5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789800700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3789800700
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2195336028
Short name T867
Test name
Test status
Simulation time 201292931 ps
CPU time 5.39 seconds
Started Feb 19 03:13:32 PM PST 24
Finished Feb 19 03:13:47 PM PST 24
Peak memory 222836 kb
Host smart-94a888c1-abf4-4a44-8de3-8e6884abce25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195336028 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2195336028
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3764152255
Short name T346
Test name
Test status
Simulation time 105555973 ps
CPU time 5.38 seconds
Started Feb 19 03:13:28 PM PST 24
Finished Feb 19 03:13:37 PM PST 24
Peak memory 208928 kb
Host smart-19238b77-b42c-4740-9b9e-649698d472b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764152255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3764152255
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1088627471
Short name T391
Test name
Test status
Simulation time 211724609 ps
CPU time 2.85 seconds
Started Feb 19 03:13:23 PM PST 24
Finished Feb 19 03:13:30 PM PST 24
Peak memory 209984 kb
Host smart-8ec87d25-6f87-4d29-83e2-82dd60803255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088627471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1088627471
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3413504702
Short name T886
Test name
Test status
Simulation time 27059626 ps
CPU time 0.95 seconds
Started Feb 19 03:13:32 PM PST 24
Finished Feb 19 03:13:44 PM PST 24
Peak memory 206036 kb
Host smart-796d6b64-f2f0-4f4f-b8af-9d893a241a69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413504702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3413504702
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1984458303
Short name T907
Test name
Test status
Simulation time 154247721 ps
CPU time 2.54 seconds
Started Feb 19 03:13:32 PM PST 24
Finished Feb 19 03:13:45 PM PST 24
Peak memory 217468 kb
Host smart-459a6bac-0041-45f7-bf7b-0e165c48dc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984458303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1984458303
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.581284701
Short name T921
Test name
Test status
Simulation time 1171594188 ps
CPU time 3.2 seconds
Started Feb 19 03:13:28 PM PST 24
Finished Feb 19 03:13:35 PM PST 24
Peak memory 209640 kb
Host smart-97be97f1-82a8-4f38-b348-8cd952a2a201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581284701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.581284701
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3958506538
Short name T313
Test name
Test status
Simulation time 184080264 ps
CPU time 6.4 seconds
Started Feb 19 03:13:31 PM PST 24
Finished Feb 19 03:13:47 PM PST 24
Peak memory 214384 kb
Host smart-43903766-17f1-458c-ba98-1c2d3d2e72c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958506538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3958506538
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1596108641
Short name T819
Test name
Test status
Simulation time 370449472 ps
CPU time 11 seconds
Started Feb 19 03:13:39 PM PST 24
Finished Feb 19 03:14:03 PM PST 24
Peak memory 211760 kb
Host smart-437adbc6-f053-411d-a942-92e3803a3698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596108641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1596108641
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1544238403
Short name T182
Test name
Test status
Simulation time 114059875 ps
CPU time 4.83 seconds
Started Feb 19 03:13:34 PM PST 24
Finished Feb 19 03:13:50 PM PST 24
Peak memory 210180 kb
Host smart-0496c441-5328-4655-bf3d-ac50f09083a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544238403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1544238403
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2505249144
Short name T848
Test name
Test status
Simulation time 304410177 ps
CPU time 10.54 seconds
Started Feb 19 03:13:31 PM PST 24
Finished Feb 19 03:13:50 PM PST 24
Peak memory 214312 kb
Host smart-0df7373e-8bca-4683-badd-6c0838942a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505249144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2505249144
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2611553354
Short name T756
Test name
Test status
Simulation time 457266810 ps
CPU time 4.04 seconds
Started Feb 19 03:13:29 PM PST 24
Finished Feb 19 03:13:39 PM PST 24
Peak memory 208428 kb
Host smart-ff7d5d6b-c95f-4d01-befb-88bdcea3af19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611553354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2611553354
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1915379523
Short name T991
Test name
Test status
Simulation time 66260467 ps
CPU time 3.19 seconds
Started Feb 19 03:13:31 PM PST 24
Finished Feb 19 03:13:43 PM PST 24
Peak memory 208920 kb
Host smart-36036485-6a8c-46ff-a357-a4d8e67b475e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915379523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1915379523
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3903588228
Short name T355
Test name
Test status
Simulation time 1945283422 ps
CPU time 20.8 seconds
Started Feb 19 03:13:33 PM PST 24
Finished Feb 19 03:14:04 PM PST 24
Peak memory 208948 kb
Host smart-7f9ce94b-3abc-49b2-ba14-6000beb5008e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903588228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3903588228
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.499715706
Short name T1051
Test name
Test status
Simulation time 163195364 ps
CPU time 4.26 seconds
Started Feb 19 03:13:29 PM PST 24
Finished Feb 19 03:13:38 PM PST 24
Peak memory 208812 kb
Host smart-bc526ad1-8aa1-4db9-8ff9-c8256c1e2331
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499715706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.499715706
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.493579899
Short name T735
Test name
Test status
Simulation time 1202456094 ps
CPU time 8.24 seconds
Started Feb 19 03:13:39 PM PST 24
Finished Feb 19 03:14:00 PM PST 24
Peak memory 209152 kb
Host smart-8f489eb4-6dc1-4136-9247-e2c558a9e327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493579899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.493579899
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3559182959
Short name T97
Test name
Test status
Simulation time 25702097 ps
CPU time 1.86 seconds
Started Feb 19 03:13:32 PM PST 24
Finished Feb 19 03:13:44 PM PST 24
Peak memory 206716 kb
Host smart-e9598800-ed49-4195-9451-a954c48d7cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559182959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3559182959
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3039185659
Short name T62
Test name
Test status
Simulation time 1401723870 ps
CPU time 54.47 seconds
Started Feb 19 03:13:31 PM PST 24
Finished Feb 19 03:14:35 PM PST 24
Peak memory 216424 kb
Host smart-9c7641b0-e54b-4e2b-b564-c955fdf2c53e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039185659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3039185659
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.2456714951
Short name T770
Test name
Test status
Simulation time 84420761 ps
CPU time 2.92 seconds
Started Feb 19 03:13:31 PM PST 24
Finished Feb 19 03:13:43 PM PST 24
Peak memory 222604 kb
Host smart-8ba75d11-4364-4017-83f7-55c60a5b62ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456714951 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.2456714951
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3405618913
Short name T580
Test name
Test status
Simulation time 94079760 ps
CPU time 3.32 seconds
Started Feb 19 03:13:34 PM PST 24
Finished Feb 19 03:13:48 PM PST 24
Peak memory 206896 kb
Host smart-a5b1f4f7-a8f1-47eb-868f-71358b23f692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405618913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3405618913
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2680332519
Short name T1068
Test name
Test status
Simulation time 246457444 ps
CPU time 2.05 seconds
Started Feb 19 03:13:31 PM PST 24
Finished Feb 19 03:13:40 PM PST 24
Peak memory 209836 kb
Host smart-70896c89-32b9-4a9e-9750-e6008c16b37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680332519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2680332519
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2903725014
Short name T672
Test name
Test status
Simulation time 10514743 ps
CPU time 0.75 seconds
Started Feb 19 03:13:37 PM PST 24
Finished Feb 19 03:13:50 PM PST 24
Peak memory 205796 kb
Host smart-297597de-a79a-443c-9e22-5ea8cfa8bbb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903725014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2903725014
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3614002558
Short name T705
Test name
Test status
Simulation time 2033556490 ps
CPU time 12.67 seconds
Started Feb 19 03:13:39 PM PST 24
Finished Feb 19 03:14:04 PM PST 24
Peak memory 209004 kb
Host smart-c22fd18b-d615-4871-b7aa-081b82189ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614002558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3614002558
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3077647882
Short name T853
Test name
Test status
Simulation time 82638191 ps
CPU time 3.72 seconds
Started Feb 19 03:13:39 PM PST 24
Finished Feb 19 03:13:56 PM PST 24
Peak memory 208424 kb
Host smart-29963a50-c485-4bc3-b67a-0e03bc34f8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077647882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3077647882
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.831645641
Short name T34
Test name
Test status
Simulation time 311914813 ps
CPU time 3.7 seconds
Started Feb 19 03:13:36 PM PST 24
Finished Feb 19 03:13:52 PM PST 24
Peak memory 208832 kb
Host smart-0c84949e-e423-483a-8fa4-8178b370af81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831645641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.831645641
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.4287700934
Short name T48
Test name
Test status
Simulation time 2026238410 ps
CPU time 3.58 seconds
Started Feb 19 03:13:32 PM PST 24
Finished Feb 19 03:13:45 PM PST 24
Peak memory 219752 kb
Host smart-e9e37785-4a60-48dd-9351-c050814277ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287700934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.4287700934
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1569782442
Short name T571
Test name
Test status
Simulation time 269508178 ps
CPU time 8.35 seconds
Started Feb 19 03:13:32 PM PST 24
Finished Feb 19 03:13:50 PM PST 24
Peak memory 207944 kb
Host smart-43f08e68-5d02-463c-9123-652a66089e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569782442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1569782442
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.4083686767
Short name T771
Test name
Test status
Simulation time 777805256 ps
CPU time 6.15 seconds
Started Feb 19 03:13:39 PM PST 24
Finished Feb 19 03:13:58 PM PST 24
Peak memory 206800 kb
Host smart-aaaf302b-e87c-47e0-8f09-4dd8ee8bcf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083686767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.4083686767
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1798041924
Short name T174
Test name
Test status
Simulation time 2598139196 ps
CPU time 33 seconds
Started Feb 19 03:13:32 PM PST 24
Finished Feb 19 03:14:13 PM PST 24
Peak memory 208392 kb
Host smart-9ab322fe-edb9-4357-a049-f426ad510e18
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798041924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1798041924
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3843709886
Short name T1010
Test name
Test status
Simulation time 177241668 ps
CPU time 2.83 seconds
Started Feb 19 03:13:33 PM PST 24
Finished Feb 19 03:13:46 PM PST 24
Peak memory 206888 kb
Host smart-d01efc9c-beb4-4a31-9fc2-f5e7c360c77b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843709886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3843709886
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1851095807
Short name T827
Test name
Test status
Simulation time 80300884 ps
CPU time 2.92 seconds
Started Feb 19 03:13:31 PM PST 24
Finished Feb 19 03:13:41 PM PST 24
Peak memory 208940 kb
Host smart-39a3a82e-59a5-4aa0-a632-35bd9c6cb015
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851095807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1851095807
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.935548460
Short name T757
Test name
Test status
Simulation time 128320226 ps
CPU time 1.89 seconds
Started Feb 19 03:13:37 PM PST 24
Finished Feb 19 03:13:51 PM PST 24
Peak memory 207204 kb
Host smart-ce2ec927-1682-4f86-91a4-24b7bdbdc8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935548460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.935548460
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2276134026
Short name T1007
Test name
Test status
Simulation time 50272731 ps
CPU time 2.68 seconds
Started Feb 19 03:13:38 PM PST 24
Finished Feb 19 03:13:54 PM PST 24
Peak memory 207348 kb
Host smart-c151788f-7c9f-43c1-87eb-854f3055431f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276134026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2276134026
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.970308307
Short name T303
Test name
Test status
Simulation time 3857697286 ps
CPU time 91.44 seconds
Started Feb 19 03:13:36 PM PST 24
Finished Feb 19 03:15:20 PM PST 24
Peak memory 222504 kb
Host smart-80c33155-fb82-42b5-a596-78b4f718f416
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970308307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.970308307
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.579812857
Short name T787
Test name
Test status
Simulation time 540792998 ps
CPU time 6.22 seconds
Started Feb 19 03:13:39 PM PST 24
Finished Feb 19 03:13:59 PM PST 24
Peak memory 222624 kb
Host smart-62e6818f-7f0c-46ea-9404-4a988b893a43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579812857 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.579812857
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.4241113371
Short name T259
Test name
Test status
Simulation time 98437191 ps
CPU time 4.38 seconds
Started Feb 19 03:13:29 PM PST 24
Finished Feb 19 03:13:39 PM PST 24
Peak memory 208980 kb
Host smart-0eb425db-f8c2-4649-9688-86a068f6d547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241113371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.4241113371
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3001668787
Short name T1064
Test name
Test status
Simulation time 90649464 ps
CPU time 2.54 seconds
Started Feb 19 03:13:33 PM PST 24
Finished Feb 19 03:13:46 PM PST 24
Peak memory 210268 kb
Host smart-4456acb7-c4a1-4ffd-815f-fd6b1f55ad73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001668787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3001668787
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.3550458393
Short name T586
Test name
Test status
Simulation time 13178049 ps
CPU time 0.92 seconds
Started Feb 19 03:13:41 PM PST 24
Finished Feb 19 03:13:55 PM PST 24
Peak memory 205996 kb
Host smart-b765c925-470a-4069-be2e-04a71122f46b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550458393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.3550458393
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3842300298
Short name T404
Test name
Test status
Simulation time 1166031282 ps
CPU time 58.12 seconds
Started Feb 19 03:13:39 PM PST 24
Finished Feb 19 03:14:50 PM PST 24
Peak memory 214236 kb
Host smart-50f31595-0b08-4b57-a51f-f94699993d48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3842300298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3842300298
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.898889071
Short name T36
Test name
Test status
Simulation time 415930755 ps
CPU time 3.61 seconds
Started Feb 19 03:13:42 PM PST 24
Finished Feb 19 03:13:58 PM PST 24
Peak memory 208900 kb
Host smart-72f813af-345c-4936-b918-d3f0c0016a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898889071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.898889071
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2180661242
Short name T1028
Test name
Test status
Simulation time 185596800 ps
CPU time 4.23 seconds
Started Feb 19 03:13:39 PM PST 24
Finished Feb 19 03:13:56 PM PST 24
Peak memory 209024 kb
Host smart-72a09689-76ea-4962-8fe9-624cc99c99cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180661242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2180661242
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3751684775
Short name T73
Test name
Test status
Simulation time 89889451 ps
CPU time 4.46 seconds
Started Feb 19 03:13:34 PM PST 24
Finished Feb 19 03:13:49 PM PST 24
Peak memory 219344 kb
Host smart-3b8d63a7-e44f-40ba-9ef1-9c8cfdfa44d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751684775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3751684775
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.4055146324
Short name T810
Test name
Test status
Simulation time 410811344 ps
CPU time 5.49 seconds
Started Feb 19 03:13:32 PM PST 24
Finished Feb 19 03:13:48 PM PST 24
Peak memory 210540 kb
Host smart-87293709-723e-4ee0-bf8c-f0cf04e2ec32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055146324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.4055146324
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1412610979
Short name T200
Test name
Test status
Simulation time 198356690 ps
CPU time 6.02 seconds
Started Feb 19 03:13:36 PM PST 24
Finished Feb 19 03:13:55 PM PST 24
Peak memory 218576 kb
Host smart-7f90d5a2-d3aa-4b47-9b21-8248d4d451c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412610979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1412610979
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3152645498
Short name T738
Test name
Test status
Simulation time 331785316 ps
CPU time 4.86 seconds
Started Feb 19 03:13:33 PM PST 24
Finished Feb 19 03:13:49 PM PST 24
Peak memory 209312 kb
Host smart-bcbfd6e6-c9e9-4e8f-ac1e-d13f0a7d7705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152645498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3152645498
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2238945100
Short name T219
Test name
Test status
Simulation time 313128829 ps
CPU time 3.47 seconds
Started Feb 19 03:13:34 PM PST 24
Finished Feb 19 03:13:48 PM PST 24
Peak memory 208504 kb
Host smart-4f5c7492-2547-4c31-b55f-03573ed4f4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238945100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2238945100
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2433821423
Short name T709
Test name
Test status
Simulation time 576081180 ps
CPU time 7.23 seconds
Started Feb 19 03:13:32 PM PST 24
Finished Feb 19 03:13:48 PM PST 24
Peak memory 208376 kb
Host smart-60a10a4d-033c-44b5-b917-3bdcd809fbfa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433821423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2433821423
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.491027009
Short name T809
Test name
Test status
Simulation time 94820202 ps
CPU time 3.37 seconds
Started Feb 19 03:13:39 PM PST 24
Finished Feb 19 03:13:55 PM PST 24
Peak memory 206820 kb
Host smart-1f8a9d19-3de1-4982-9cba-d0a3df71680f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491027009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.491027009
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.340502052
Short name T32
Test name
Test status
Simulation time 102584819 ps
CPU time 3.03 seconds
Started Feb 19 03:13:34 PM PST 24
Finished Feb 19 03:13:48 PM PST 24
Peak memory 208652 kb
Host smart-d08649bb-ec2a-40cb-acb1-7e47f524552c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340502052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.340502052
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2975504238
Short name T999
Test name
Test status
Simulation time 334927246 ps
CPU time 2.11 seconds
Started Feb 19 03:13:33 PM PST 24
Finished Feb 19 03:13:45 PM PST 24
Peak memory 209056 kb
Host smart-c38e51c3-9248-4507-b557-33cb597c6734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975504238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2975504238
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3536792670
Short name T777
Test name
Test status
Simulation time 40687650 ps
CPU time 1.83 seconds
Started Feb 19 03:13:33 PM PST 24
Finished Feb 19 03:13:44 PM PST 24
Peak memory 206772 kb
Host smart-2f6335ed-52c4-4634-99f6-2ea03e030bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536792670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3536792670
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2452887372
Short name T772
Test name
Test status
Simulation time 782119896 ps
CPU time 8.51 seconds
Started Feb 19 03:13:32 PM PST 24
Finished Feb 19 03:13:51 PM PST 24
Peak memory 222576 kb
Host smart-c8d59b8d-8e16-4fe8-bbd6-0ce7710b0b82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452887372 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2452887372
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.4282207979
Short name T964
Test name
Test status
Simulation time 1978653762 ps
CPU time 11.52 seconds
Started Feb 19 03:13:34 PM PST 24
Finished Feb 19 03:13:56 PM PST 24
Peak memory 214308 kb
Host smart-d14367e2-2311-444f-94f0-fce2c5eee917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282207979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.4282207979
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2959028751
Short name T814
Test name
Test status
Simulation time 645298503 ps
CPU time 8.52 seconds
Started Feb 19 03:13:34 PM PST 24
Finished Feb 19 03:13:53 PM PST 24
Peak memory 210520 kb
Host smart-814aa5b9-0a61-47fd-9447-bb516d219b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959028751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2959028751
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1032062447
Short name T1058
Test name
Test status
Simulation time 75294322 ps
CPU time 0.87 seconds
Started Feb 19 03:13:42 PM PST 24
Finished Feb 19 03:13:55 PM PST 24
Peak memory 205856 kb
Host smart-3a39a859-de96-4724-be94-c133a14e1156
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032062447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1032062447
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.890359761
Short name T980
Test name
Test status
Simulation time 328284190 ps
CPU time 3.76 seconds
Started Feb 19 03:13:42 PM PST 24
Finished Feb 19 03:13:58 PM PST 24
Peak memory 220052 kb
Host smart-f3f2cb2e-d733-4b4e-bc7c-c9bb99bbc5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890359761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.890359761
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.752310610
Short name T817
Test name
Test status
Simulation time 79088298 ps
CPU time 3.19 seconds
Started Feb 19 03:13:38 PM PST 24
Finished Feb 19 03:13:53 PM PST 24
Peak memory 218016 kb
Host smart-0bca535b-4340-42d1-a491-f86e2b7a8013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752310610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.752310610
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3265986101
Short name T375
Test name
Test status
Simulation time 47355493 ps
CPU time 3.08 seconds
Started Feb 19 03:13:38 PM PST 24
Finished Feb 19 03:13:53 PM PST 24
Peak memory 214272 kb
Host smart-f1a0fe66-8df3-4b54-9290-056627dd80c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265986101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3265986101
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.482821413
Short name T906
Test name
Test status
Simulation time 4486996245 ps
CPU time 36.72 seconds
Started Feb 19 03:13:39 PM PST 24
Finished Feb 19 03:14:29 PM PST 24
Peak memory 216476 kb
Host smart-68ff9f02-ca4d-4b6e-a01e-e58d7cdedc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482821413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.482821413
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2105768862
Short name T618
Test name
Test status
Simulation time 58238337 ps
CPU time 2.84 seconds
Started Feb 19 03:13:40 PM PST 24
Finished Feb 19 03:13:56 PM PST 24
Peak memory 218720 kb
Host smart-7321e67c-7e65-4bf7-92a0-1091bd11680a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105768862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2105768862
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1806815899
Short name T979
Test name
Test status
Simulation time 383373869 ps
CPU time 4.14 seconds
Started Feb 19 03:13:39 PM PST 24
Finished Feb 19 03:13:56 PM PST 24
Peak memory 214332 kb
Host smart-a802e526-36c1-4dfc-9940-cf8fa00d3286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806815899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1806815899
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1673472923
Short name T627
Test name
Test status
Simulation time 122294378 ps
CPU time 4.15 seconds
Started Feb 19 03:13:33 PM PST 24
Finished Feb 19 03:13:48 PM PST 24
Peak memory 207172 kb
Host smart-d4ad724b-cdab-4178-a0b2-bbc4ef8dee2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673472923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1673472923
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2162250377
Short name T711
Test name
Test status
Simulation time 1006974372 ps
CPU time 27.9 seconds
Started Feb 19 03:13:33 PM PST 24
Finished Feb 19 03:14:11 PM PST 24
Peak memory 208764 kb
Host smart-0144b73b-204d-4fe2-a573-6bd81f943be3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162250377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2162250377
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2897707043
Short name T750
Test name
Test status
Simulation time 58833377 ps
CPU time 3.26 seconds
Started Feb 19 03:13:34 PM PST 24
Finished Feb 19 03:13:48 PM PST 24
Peak memory 206772 kb
Host smart-c9dc31bc-9ba7-44b8-a9d4-1e81ce06c962
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897707043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2897707043
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.21367657
Short name T846
Test name
Test status
Simulation time 237722472 ps
CPU time 4.16 seconds
Started Feb 19 03:13:37 PM PST 24
Finished Feb 19 03:13:54 PM PST 24
Peak memory 208660 kb
Host smart-aa2cfdf2-fcf7-4a98-803b-6730bdd495b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21367657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.21367657
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3663096169
Short name T648
Test name
Test status
Simulation time 232002754 ps
CPU time 2.88 seconds
Started Feb 19 03:13:40 PM PST 24
Finished Feb 19 03:13:57 PM PST 24
Peak memory 209044 kb
Host smart-00b53758-da96-4f32-b44c-edde9dea7a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663096169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3663096169
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1496797419
Short name T992
Test name
Test status
Simulation time 399747539 ps
CPU time 2.67 seconds
Started Feb 19 03:13:33 PM PST 24
Finished Feb 19 03:13:46 PM PST 24
Peak memory 207100 kb
Host smart-9dd78499-eaaa-4957-9ab3-49342b3b6342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496797419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1496797419
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1692438861
Short name T1052
Test name
Test status
Simulation time 2127688434 ps
CPU time 22.61 seconds
Started Feb 19 03:13:40 PM PST 24
Finished Feb 19 03:14:16 PM PST 24
Peak memory 214956 kb
Host smart-00c55e89-77a8-47d9-bd0e-45d8e6b59553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692438861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1692438861
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3175026941
Short name T726
Test name
Test status
Simulation time 114930093 ps
CPU time 5.66 seconds
Started Feb 19 03:13:46 PM PST 24
Finished Feb 19 03:14:03 PM PST 24
Peak memory 222636 kb
Host smart-748cb4c3-6778-4da7-afea-31b99d2dcf8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175026941 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3175026941
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4004024919
Short name T661
Test name
Test status
Simulation time 37783992 ps
CPU time 2.77 seconds
Started Feb 19 03:13:37 PM PST 24
Finished Feb 19 03:13:52 PM PST 24
Peak memory 207528 kb
Host smart-0e3a5004-a713-4100-b619-d9711af9eccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004024919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4004024919
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3948602010
Short name T841
Test name
Test status
Simulation time 13470260 ps
CPU time 0.78 seconds
Started Feb 19 03:13:44 PM PST 24
Finished Feb 19 03:13:56 PM PST 24
Peak memory 205828 kb
Host smart-7827fcb6-b231-47b9-8bd4-0f4f7d7f82a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948602010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3948602010
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.4185023980
Short name T225
Test name
Test status
Simulation time 257541814 ps
CPU time 14.1 seconds
Started Feb 19 03:13:43 PM PST 24
Finished Feb 19 03:14:09 PM PST 24
Peak memory 214308 kb
Host smart-be61bfe3-4ae3-43a3-b2c4-3d93029f4ee2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185023980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.4185023980
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.134491159
Short name T707
Test name
Test status
Simulation time 35806746 ps
CPU time 2.46 seconds
Started Feb 19 03:13:43 PM PST 24
Finished Feb 19 03:13:58 PM PST 24
Peak memory 206988 kb
Host smart-6315a6a8-e7c2-4c16-91b7-ce12b1e07c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134491159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.134491159
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3882987075
Short name T95
Test name
Test status
Simulation time 1991294994 ps
CPU time 12.44 seconds
Started Feb 19 03:13:44 PM PST 24
Finished Feb 19 03:14:08 PM PST 24
Peak memory 208804 kb
Host smart-d704acba-05a4-4ea6-a752-4b7805b2b29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882987075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3882987075
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1426429455
Short name T69
Test name
Test status
Simulation time 6724200217 ps
CPU time 58.61 seconds
Started Feb 19 03:13:41 PM PST 24
Finished Feb 19 03:14:53 PM PST 24
Peak memory 226396 kb
Host smart-2766a765-4d02-4ca4-8716-8a05b99d9473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426429455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1426429455
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2185571401
Short name T703
Test name
Test status
Simulation time 264992270 ps
CPU time 4.11 seconds
Started Feb 19 03:13:43 PM PST 24
Finished Feb 19 03:14:00 PM PST 24
Peak memory 207576 kb
Host smart-7bb097f2-7acd-4023-b7e6-8c30d781750f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185571401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2185571401
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3294084767
Short name T171
Test name
Test status
Simulation time 894504820 ps
CPU time 4.31 seconds
Started Feb 19 03:13:44 PM PST 24
Finished Feb 19 03:14:00 PM PST 24
Peak memory 209900 kb
Host smart-e39879d7-cccc-4641-81b7-c00a835a3ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294084767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3294084767
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.189960498
Short name T387
Test name
Test status
Simulation time 684880091 ps
CPU time 3.16 seconds
Started Feb 19 03:13:40 PM PST 24
Finished Feb 19 03:13:57 PM PST 24
Peak memory 206536 kb
Host smart-56617c85-51ad-455a-9d72-64b5891fac18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189960498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.189960498
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.784357070
Short name T754
Test name
Test status
Simulation time 88445580 ps
CPU time 2.77 seconds
Started Feb 19 03:13:43 PM PST 24
Finished Feb 19 03:13:58 PM PST 24
Peak memory 208588 kb
Host smart-5845969f-5064-4c15-a18e-e1c833f5180a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784357070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.784357070
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1362354157
Short name T802
Test name
Test status
Simulation time 1742892661 ps
CPU time 25.19 seconds
Started Feb 19 03:13:43 PM PST 24
Finished Feb 19 03:14:20 PM PST 24
Peak memory 208380 kb
Host smart-aee40b81-63b3-4956-8bf3-72a2b175a9a3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362354157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1362354157
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3350388669
Short name T658
Test name
Test status
Simulation time 61371814 ps
CPU time 2.68 seconds
Started Feb 19 03:13:38 PM PST 24
Finished Feb 19 03:13:54 PM PST 24
Peak memory 207064 kb
Host smart-636aaa62-e9ab-4ffb-9e16-9cafa5ddc0c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350388669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3350388669
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2442242994
Short name T843
Test name
Test status
Simulation time 23820982 ps
CPU time 1.63 seconds
Started Feb 19 03:13:44 PM PST 24
Finished Feb 19 03:13:58 PM PST 24
Peak memory 207592 kb
Host smart-2856fb2f-76ee-436c-bdc2-a303da51c2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442242994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2442242994
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3176702632
Short name T782
Test name
Test status
Simulation time 202538655 ps
CPU time 2.81 seconds
Started Feb 19 03:13:43 PM PST 24
Finished Feb 19 03:13:58 PM PST 24
Peak memory 206792 kb
Host smart-cc2062d8-18eb-49b7-8f3d-10607048ae80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176702632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3176702632
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2144417498
Short name T744
Test name
Test status
Simulation time 378370526 ps
CPU time 6 seconds
Started Feb 19 03:13:45 PM PST 24
Finished Feb 19 03:14:03 PM PST 24
Peak memory 208632 kb
Host smart-ffb0b686-0733-4be5-b2de-e04afa7d8e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144417498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2144417498
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1501938252
Short name T386
Test name
Test status
Simulation time 39485463 ps
CPU time 2.27 seconds
Started Feb 19 03:13:44 PM PST 24
Finished Feb 19 03:13:58 PM PST 24
Peak memory 210208 kb
Host smart-3161c84c-ea75-428e-b510-bab2e1c3e4da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501938252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1501938252
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3650870067
Short name T889
Test name
Test status
Simulation time 47654351 ps
CPU time 0.88 seconds
Started Feb 19 03:13:47 PM PST 24
Finished Feb 19 03:13:58 PM PST 24
Peak memory 205880 kb
Host smart-55c87d9c-b4a7-4723-a944-c454f5a433a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650870067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3650870067
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1756343150
Short name T37
Test name
Test status
Simulation time 147405519 ps
CPU time 2.47 seconds
Started Feb 19 03:13:44 PM PST 24
Finished Feb 19 03:13:59 PM PST 24
Peak memory 210392 kb
Host smart-ff81db9d-73ed-490f-88e5-f891e4dd2f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756343150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1756343150
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3580469352
Short name T713
Test name
Test status
Simulation time 216775530 ps
CPU time 2.86 seconds
Started Feb 19 03:13:49 PM PST 24
Finished Feb 19 03:14:01 PM PST 24
Peak memory 207860 kb
Host smart-45bf8fff-304c-4a5d-9fbb-6da8a54f8a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580469352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3580469352
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.434973344
Short name T955
Test name
Test status
Simulation time 302865002 ps
CPU time 4.54 seconds
Started Feb 19 03:13:45 PM PST 24
Finished Feb 19 03:14:01 PM PST 24
Peak memory 208716 kb
Host smart-50bbbef7-399c-466a-86f3-4f8d6c960f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434973344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.434973344
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1826807560
Short name T742
Test name
Test status
Simulation time 1075703113 ps
CPU time 12.63 seconds
Started Feb 19 03:13:45 PM PST 24
Finished Feb 19 03:14:09 PM PST 24
Peak memory 214168 kb
Host smart-31501e6c-6bc8-4027-b016-6a8420548733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826807560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1826807560
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_random.1579299213
Short name T363
Test name
Test status
Simulation time 1039140307 ps
CPU time 8.78 seconds
Started Feb 19 03:13:45 PM PST 24
Finished Feb 19 03:14:06 PM PST 24
Peak memory 208648 kb
Host smart-ccb59281-59a3-49e6-b197-b828d2196ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579299213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1579299213
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3835811923
Short name T177
Test name
Test status
Simulation time 1749297795 ps
CPU time 5.86 seconds
Started Feb 19 03:13:43 PM PST 24
Finished Feb 19 03:14:01 PM PST 24
Peak memory 208340 kb
Host smart-54039cff-6467-4d98-87c5-90c739f19b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835811923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3835811923
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3829409304
Short name T926
Test name
Test status
Simulation time 261133372 ps
CPU time 2.74 seconds
Started Feb 19 03:13:49 PM PST 24
Finished Feb 19 03:14:01 PM PST 24
Peak memory 208764 kb
Host smart-23781b53-0290-43cb-a0ce-31e698e86be5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829409304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3829409304
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3825025579
Short name T582
Test name
Test status
Simulation time 753839926 ps
CPU time 8.18 seconds
Started Feb 19 03:13:41 PM PST 24
Finished Feb 19 03:14:03 PM PST 24
Peak memory 208584 kb
Host smart-4604db63-bc0b-4963-b8a0-96638840338a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825025579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3825025579
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2553334962
Short name T344
Test name
Test status
Simulation time 137860166 ps
CPU time 2.69 seconds
Started Feb 19 03:13:43 PM PST 24
Finished Feb 19 03:13:58 PM PST 24
Peak memory 206908 kb
Host smart-c075c149-a70a-4a48-b30b-a2374ab80a28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553334962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2553334962
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1426292800
Short name T780
Test name
Test status
Simulation time 312002886 ps
CPU time 4.03 seconds
Started Feb 19 03:13:46 PM PST 24
Finished Feb 19 03:14:01 PM PST 24
Peak memory 215876 kb
Host smart-b566bd42-456f-4f1a-8fec-f129f55354e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426292800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1426292800
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.473315288
Short name T728
Test name
Test status
Simulation time 5139523831 ps
CPU time 28.08 seconds
Started Feb 19 03:13:50 PM PST 24
Finished Feb 19 03:14:27 PM PST 24
Peak memory 208436 kb
Host smart-e434c68f-9aca-44d8-a664-9dd1305f6e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473315288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.473315288
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2885372211
Short name T207
Test name
Test status
Simulation time 32365287382 ps
CPU time 973.73 seconds
Started Feb 19 03:13:45 PM PST 24
Finished Feb 19 03:30:11 PM PST 24
Peak memory 230660 kb
Host smart-31aaa60c-a260-4a9f-a777-d8cc6a56912e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885372211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2885372211
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1345909974
Short name T849
Test name
Test status
Simulation time 260726600 ps
CPU time 4.99 seconds
Started Feb 19 03:13:45 PM PST 24
Finished Feb 19 03:14:02 PM PST 24
Peak memory 223060 kb
Host smart-d35f404e-bbae-43ed-bda1-908822d62114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345909974 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1345909974
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1906145830
Short name T825
Test name
Test status
Simulation time 267009402 ps
CPU time 4.76 seconds
Started Feb 19 03:13:45 PM PST 24
Finished Feb 19 03:14:02 PM PST 24
Peak memory 210040 kb
Host smart-2be16f96-1077-45c2-9ef1-656084895e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906145830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1906145830
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3423326344
Short name T585
Test name
Test status
Simulation time 3527847795 ps
CPU time 16.72 seconds
Started Feb 19 03:13:50 PM PST 24
Finished Feb 19 03:14:16 PM PST 24
Peak memory 222288 kb
Host smart-3bb3860b-d1ec-4b72-8bbd-f6165cad1e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423326344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3423326344
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.987655042
Short name T858
Test name
Test status
Simulation time 74010446 ps
CPU time 0.78 seconds
Started Feb 19 03:09:40 PM PST 24
Finished Feb 19 03:09:42 PM PST 24
Peak memory 205820 kb
Host smart-45537ffd-5f23-439c-abc4-8a684319f0df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987655042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.987655042
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.451263154
Short name T409
Test name
Test status
Simulation time 60712097 ps
CPU time 3.99 seconds
Started Feb 19 03:09:33 PM PST 24
Finished Feb 19 03:09:42 PM PST 24
Peak memory 215856 kb
Host smart-bf684038-9a43-46a7-8b6c-c06173bd1f87
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=451263154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.451263154
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.485821282
Short name T829
Test name
Test status
Simulation time 925058935 ps
CPU time 12.59 seconds
Started Feb 19 03:09:41 PM PST 24
Finished Feb 19 03:09:55 PM PST 24
Peak memory 214628 kb
Host smart-72a73f81-bae7-4730-bf00-e13662a903ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485821282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.485821282
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3222991777
Short name T230
Test name
Test status
Simulation time 242282041 ps
CPU time 3.2 seconds
Started Feb 19 03:09:32 PM PST 24
Finished Feb 19 03:09:42 PM PST 24
Peak memory 219620 kb
Host smart-bb4acdbe-b729-4c89-9c43-58d71bfd0a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222991777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3222991777
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.4116124326
Short name T78
Test name
Test status
Simulation time 93215515 ps
CPU time 4.37 seconds
Started Feb 19 03:09:32 PM PST 24
Finished Feb 19 03:09:43 PM PST 24
Peak memory 220656 kb
Host smart-11826484-e6db-425c-a8a6-2bb17329c51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116124326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.4116124326
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.36901523
Short name T601
Test name
Test status
Simulation time 946232741 ps
CPU time 8.85 seconds
Started Feb 19 03:09:37 PM PST 24
Finished Feb 19 03:09:48 PM PST 24
Peak memory 222656 kb
Host smart-9f95d30b-5f4f-414d-a16a-f45ef25d28a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36901523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.36901523
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.4275583721
Short name T862
Test name
Test status
Simulation time 133731451 ps
CPU time 4.26 seconds
Started Feb 19 03:09:33 PM PST 24
Finished Feb 19 03:09:43 PM PST 24
Peak memory 209852 kb
Host smart-303bdd08-0bb4-4184-ac4d-9014fc8a3c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275583721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.4275583721
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3626703051
Short name T577
Test name
Test status
Simulation time 1415231381 ps
CPU time 43.12 seconds
Started Feb 19 03:09:32 PM PST 24
Finished Feb 19 03:10:21 PM PST 24
Peak memory 214312 kb
Host smart-855316c0-9d57-4d67-adbc-57db89ec31a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626703051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3626703051
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4242619753
Short name T217
Test name
Test status
Simulation time 1030448844 ps
CPU time 7.93 seconds
Started Feb 19 03:09:30 PM PST 24
Finished Feb 19 03:09:46 PM PST 24
Peak memory 207924 kb
Host smart-b7fde856-21d3-4555-a1bf-29d8209709ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242619753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4242619753
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1711212475
Short name T1038
Test name
Test status
Simulation time 153157430 ps
CPU time 2.37 seconds
Started Feb 19 03:09:27 PM PST 24
Finished Feb 19 03:09:40 PM PST 24
Peak memory 206920 kb
Host smart-b68f45a2-de99-4b9e-9adc-8e10b9020e18
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711212475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1711212475
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.405098602
Short name T774
Test name
Test status
Simulation time 313948449 ps
CPU time 3.96 seconds
Started Feb 19 03:09:29 PM PST 24
Finished Feb 19 03:09:42 PM PST 24
Peak memory 208788 kb
Host smart-5091b5fd-d619-49c2-b226-38cc40b447b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405098602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.405098602
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2507911412
Short name T1044
Test name
Test status
Simulation time 184564419 ps
CPU time 2.88 seconds
Started Feb 19 03:09:32 PM PST 24
Finished Feb 19 03:09:41 PM PST 24
Peak memory 206836 kb
Host smart-ffbd2380-717d-42bf-917e-e65a2c6a4060
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507911412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2507911412
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1501803225
Short name T647
Test name
Test status
Simulation time 124290520 ps
CPU time 3.24 seconds
Started Feb 19 03:09:40 PM PST 24
Finished Feb 19 03:09:44 PM PST 24
Peak memory 208124 kb
Host smart-57f9ec2c-1833-4f43-a9f2-76b1416ffc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501803225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1501803225
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1753089685
Short name T847
Test name
Test status
Simulation time 121339272 ps
CPU time 2.45 seconds
Started Feb 19 03:09:30 PM PST 24
Finished Feb 19 03:09:40 PM PST 24
Peak memory 208464 kb
Host smart-7c4f666b-9bf2-4edd-92b3-1682ae65551b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753089685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1753089685
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1596898061
Short name T1040
Test name
Test status
Simulation time 823326635 ps
CPU time 18.03 seconds
Started Feb 19 03:09:40 PM PST 24
Finished Feb 19 03:09:59 PM PST 24
Peak memory 215012 kb
Host smart-e66aab52-972a-4422-b2e6-fde6e3f103f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596898061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1596898061
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2124616477
Short name T675
Test name
Test status
Simulation time 472640622 ps
CPU time 7.43 seconds
Started Feb 19 03:09:39 PM PST 24
Finished Feb 19 03:09:48 PM PST 24
Peak memory 222796 kb
Host smart-02f2b53c-3fa9-4e6d-92a4-534046e8ace8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124616477 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2124616477
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.479629319
Short name T916
Test name
Test status
Simulation time 87034467 ps
CPU time 3.84 seconds
Started Feb 19 03:09:35 PM PST 24
Finished Feb 19 03:09:43 PM PST 24
Peak memory 209192 kb
Host smart-cb0d19b1-1f5c-4756-b122-3f341474d551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479629319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.479629319
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2347896295
Short name T589
Test name
Test status
Simulation time 125916843 ps
CPU time 3.2 seconds
Started Feb 19 03:09:41 PM PST 24
Finished Feb 19 03:09:46 PM PST 24
Peak memory 209848 kb
Host smart-8a8c6c29-401e-4496-bca1-e9ab76ad0d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347896295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2347896295
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1574054334
Short name T856
Test name
Test status
Simulation time 16010820 ps
CPU time 0.96 seconds
Started Feb 19 03:09:44 PM PST 24
Finished Feb 19 03:09:46 PM PST 24
Peak memory 205896 kb
Host smart-7eb4f1bf-861b-40cf-9b60-f80d99c690a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574054334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1574054334
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3602711032
Short name T939
Test name
Test status
Simulation time 1016231885 ps
CPU time 20.24 seconds
Started Feb 19 03:09:50 PM PST 24
Finished Feb 19 03:10:12 PM PST 24
Peak memory 221120 kb
Host smart-b242e195-8977-4a5e-8488-cb40264b9a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602711032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3602711032
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3410625742
Short name T59
Test name
Test status
Simulation time 31939938 ps
CPU time 2.1 seconds
Started Feb 19 03:09:43 PM PST 24
Finished Feb 19 03:09:47 PM PST 24
Peak memory 214384 kb
Host smart-c47e6a38-ab8b-420a-b025-054f0ec006fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410625742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3410625742
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3593552288
Short name T80
Test name
Test status
Simulation time 340603038 ps
CPU time 3.91 seconds
Started Feb 19 03:09:42 PM PST 24
Finished Feb 19 03:09:48 PM PST 24
Peak memory 214308 kb
Host smart-80992a74-98ff-45db-b8b3-b1279980bc25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593552288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3593552288
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3146497887
Short name T779
Test name
Test status
Simulation time 65660112 ps
CPU time 2.42 seconds
Started Feb 19 03:09:50 PM PST 24
Finished Feb 19 03:09:54 PM PST 24
Peak memory 213232 kb
Host smart-adaa35a0-d5b7-43f6-8031-36b8344cf96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146497887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3146497887
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2117216501
Short name T277
Test name
Test status
Simulation time 2123872839 ps
CPU time 9.92 seconds
Started Feb 19 03:09:42 PM PST 24
Finished Feb 19 03:09:53 PM PST 24
Peak memory 214268 kb
Host smart-389f9d48-b24e-4785-9d93-0edfc74699ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117216501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2117216501
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3517249833
Short name T765
Test name
Test status
Simulation time 180065619 ps
CPU time 4.99 seconds
Started Feb 19 03:09:42 PM PST 24
Finished Feb 19 03:09:49 PM PST 24
Peak memory 208532 kb
Host smart-7676ce86-7bdd-4032-8f17-461dcb476fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517249833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3517249833
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1680339478
Short name T826
Test name
Test status
Simulation time 807769406 ps
CPU time 3.63 seconds
Started Feb 19 03:09:40 PM PST 24
Finished Feb 19 03:09:45 PM PST 24
Peak memory 208864 kb
Host smart-d61cebe5-2620-4d5d-8f32-1ab1add81570
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680339478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1680339478
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3744584999
Short name T828
Test name
Test status
Simulation time 64127389 ps
CPU time 2.83 seconds
Started Feb 19 03:09:41 PM PST 24
Finished Feb 19 03:09:45 PM PST 24
Peak memory 208704 kb
Host smart-3b3711ae-4f58-4e8d-92f0-b036bcfbdd4b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744584999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3744584999
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2072944060
Short name T794
Test name
Test status
Simulation time 98663356 ps
CPU time 3.83 seconds
Started Feb 19 03:09:45 PM PST 24
Finished Feb 19 03:09:54 PM PST 24
Peak memory 207444 kb
Host smart-c20393e6-415f-4263-9edb-53533c0a92c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072944060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2072944060
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2727583257
Short name T812
Test name
Test status
Simulation time 143136776 ps
CPU time 3.38 seconds
Started Feb 19 03:09:42 PM PST 24
Finished Feb 19 03:09:47 PM PST 24
Peak memory 209052 kb
Host smart-76f1f5e8-7da4-4922-83a3-96527f17464c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727583257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2727583257
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2443898873
Short name T1065
Test name
Test status
Simulation time 4767312943 ps
CPU time 10.14 seconds
Started Feb 19 03:09:40 PM PST 24
Finished Feb 19 03:09:51 PM PST 24
Peak memory 208488 kb
Host smart-d1291675-e580-4bf5-ab21-549b5af0b5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443898873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2443898873
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1031788294
Short name T63
Test name
Test status
Simulation time 942674370 ps
CPU time 13.49 seconds
Started Feb 19 03:09:45 PM PST 24
Finished Feb 19 03:10:04 PM PST 24
Peak memory 219948 kb
Host smart-761c17ce-e0f1-4506-b325-07990108a612
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031788294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1031788294
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2435234731
Short name T694
Test name
Test status
Simulation time 869621743 ps
CPU time 5.28 seconds
Started Feb 19 03:09:50 PM PST 24
Finished Feb 19 03:09:57 PM PST 24
Peak memory 222200 kb
Host smart-5d092378-6501-48eb-9bd7-468fa40dad15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435234731 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2435234731
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2928276584
Short name T325
Test name
Test status
Simulation time 317563228 ps
CPU time 6.39 seconds
Started Feb 19 03:09:45 PM PST 24
Finished Feb 19 03:09:57 PM PST 24
Peak memory 218116 kb
Host smart-5ac20022-8f35-4f55-b9b4-3966257e0e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928276584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2928276584
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2398258047
Short name T682
Test name
Test status
Simulation time 31913569 ps
CPU time 2.07 seconds
Started Feb 19 03:09:50 PM PST 24
Finished Feb 19 03:09:54 PM PST 24
Peak memory 209924 kb
Host smart-c0e7984b-3287-4059-8b15-21da005e0f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398258047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2398258047
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.182599584
Short name T859
Test name
Test status
Simulation time 50790426 ps
CPU time 0.77 seconds
Started Feb 19 03:09:55 PM PST 24
Finished Feb 19 03:09:57 PM PST 24
Peak memory 205816 kb
Host smart-909f102e-d162-43a1-9b14-78664885f24b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182599584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.182599584
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.438709895
Short name T358
Test name
Test status
Simulation time 3704244700 ps
CPU time 52.6 seconds
Started Feb 19 03:09:44 PM PST 24
Finished Feb 19 03:10:38 PM PST 24
Peak memory 214824 kb
Host smart-ffc1ac43-7c88-4b76-a60c-d472974137e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=438709895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.438709895
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3094906180
Short name T35
Test name
Test status
Simulation time 89873589 ps
CPU time 2.99 seconds
Started Feb 19 03:09:53 PM PST 24
Finished Feb 19 03:09:57 PM PST 24
Peak memory 214320 kb
Host smart-7bbd7ee6-bf82-468d-893b-0e461735283a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094906180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3094906180
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1459831005
Short name T64
Test name
Test status
Simulation time 59683652 ps
CPU time 2.6 seconds
Started Feb 19 03:09:45 PM PST 24
Finished Feb 19 03:09:53 PM PST 24
Peak memory 209324 kb
Host smart-66a222b1-0ddb-4e2a-8eba-2d7b1272fc74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459831005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1459831005
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3657585966
Short name T873
Test name
Test status
Simulation time 263198186 ps
CPU time 9.82 seconds
Started Feb 19 03:09:51 PM PST 24
Finished Feb 19 03:10:03 PM PST 24
Peak memory 214292 kb
Host smart-5f2ad743-d951-4f72-a140-5549be0dae93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657585966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3657585966
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3256551039
Short name T246
Test name
Test status
Simulation time 206279115 ps
CPU time 5.4 seconds
Started Feb 19 03:09:57 PM PST 24
Finished Feb 19 03:10:03 PM PST 24
Peak memory 210212 kb
Host smart-6243e491-7f1a-4cbe-a74b-ce75a7fbacb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256551039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3256551039
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1461861159
Short name T609
Test name
Test status
Simulation time 156417760 ps
CPU time 6.73 seconds
Started Feb 19 03:09:48 PM PST 24
Finished Feb 19 03:09:58 PM PST 24
Peak memory 210188 kb
Host smart-fc50c5af-8f87-49c8-920c-7a825a631d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461861159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1461861159
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2041852826
Short name T1045
Test name
Test status
Simulation time 755319820 ps
CPU time 8.02 seconds
Started Feb 19 03:09:44 PM PST 24
Finished Feb 19 03:09:53 PM PST 24
Peak memory 208932 kb
Host smart-74ad629b-9ca3-42bf-83e6-1f176b485ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041852826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2041852826
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3155458095
Short name T337
Test name
Test status
Simulation time 852781581 ps
CPU time 25.5 seconds
Started Feb 19 03:09:50 PM PST 24
Finished Feb 19 03:10:17 PM PST 24
Peak memory 206280 kb
Host smart-a3dc2159-95d0-4dd3-b39e-be7d08023bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155458095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3155458095
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3753101143
Short name T642
Test name
Test status
Simulation time 99744997 ps
CPU time 3.96 seconds
Started Feb 19 03:09:45 PM PST 24
Finished Feb 19 03:09:51 PM PST 24
Peak memory 206968 kb
Host smart-142e0d90-ea03-4dd2-a473-22fabfaee56a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753101143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3753101143
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2778417573
Short name T831
Test name
Test status
Simulation time 125778218 ps
CPU time 3.25 seconds
Started Feb 19 03:09:44 PM PST 24
Finished Feb 19 03:09:48 PM PST 24
Peak memory 206808 kb
Host smart-d7da0571-4eaa-4fcf-ba95-b16bf00eae2d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778417573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2778417573
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2979329787
Short name T625
Test name
Test status
Simulation time 334875589 ps
CPU time 3.52 seconds
Started Feb 19 03:09:45 PM PST 24
Finished Feb 19 03:09:53 PM PST 24
Peak memory 206920 kb
Host smart-cce907a6-8465-4935-8391-e326f3af125b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979329787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2979329787
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3732603491
Short name T170
Test name
Test status
Simulation time 790627480 ps
CPU time 6.75 seconds
Started Feb 19 03:09:55 PM PST 24
Finished Feb 19 03:10:02 PM PST 24
Peak memory 218460 kb
Host smart-6ec96e5f-47ba-47b6-a3ba-8cfb8e1a233e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732603491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3732603491
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.813056588
Short name T870
Test name
Test status
Simulation time 51197978 ps
CPU time 2.66 seconds
Started Feb 19 03:09:45 PM PST 24
Finished Feb 19 03:09:53 PM PST 24
Peak memory 208484 kb
Host smart-b5175f0a-7197-4edb-b75a-e8afa881f6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813056588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.813056588
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2535229257
Short name T368
Test name
Test status
Simulation time 1193771432 ps
CPU time 39.04 seconds
Started Feb 19 03:09:53 PM PST 24
Finished Feb 19 03:10:33 PM PST 24
Peak memory 222428 kb
Host smart-44980259-0446-48bd-902a-c7f56bdc99a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535229257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2535229257
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.225728130
Short name T188
Test name
Test status
Simulation time 3570212761 ps
CPU time 7.74 seconds
Started Feb 19 03:09:53 PM PST 24
Finished Feb 19 03:10:02 PM PST 24
Peak memory 222672 kb
Host smart-7f21e50c-c664-46cb-8f56-a6eae22acadd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225728130 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.225728130
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3935652424
Short name T27
Test name
Test status
Simulation time 113956259 ps
CPU time 5.65 seconds
Started Feb 19 03:09:50 PM PST 24
Finished Feb 19 03:09:57 PM PST 24
Peak memory 210412 kb
Host smart-892599fb-3153-42f7-b872-8ae1ad7813cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935652424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3935652424
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2286931149
Short name T749
Test name
Test status
Simulation time 60296013 ps
CPU time 2.43 seconds
Started Feb 19 03:09:55 PM PST 24
Finished Feb 19 03:09:58 PM PST 24
Peak memory 209676 kb
Host smart-075530fc-cfa3-464f-ad16-c453db896714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286931149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2286931149
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1518821676
Short name T549
Test name
Test status
Simulation time 16585184 ps
CPU time 0.94 seconds
Started Feb 19 03:09:59 PM PST 24
Finished Feb 19 03:10:00 PM PST 24
Peak memory 205992 kb
Host smart-19d86823-4d3d-4703-864d-6c719288a3a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518821676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1518821676
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.4095141958
Short name T681
Test name
Test status
Simulation time 644520122 ps
CPU time 4.36 seconds
Started Feb 19 03:09:57 PM PST 24
Finished Feb 19 03:10:02 PM PST 24
Peak memory 214312 kb
Host smart-2c953257-92d4-4f8b-a9c4-385217d95229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095141958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.4095141958
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2152359201
Short name T1027
Test name
Test status
Simulation time 570969446 ps
CPU time 4.51 seconds
Started Feb 19 03:10:02 PM PST 24
Finished Feb 19 03:10:07 PM PST 24
Peak memory 210212 kb
Host smart-73274bf6-11ab-40f9-a9d3-ea1351ecf87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152359201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2152359201
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.4229398773
Short name T369
Test name
Test status
Simulation time 118611854 ps
CPU time 5.62 seconds
Started Feb 19 03:09:59 PM PST 24
Finished Feb 19 03:10:05 PM PST 24
Peak memory 214192 kb
Host smart-2ce552af-39cd-4d1f-8ade-7f4e2c5bc529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229398773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.4229398773
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.4192156568
Short name T181
Test name
Test status
Simulation time 353865422 ps
CPU time 3.67 seconds
Started Feb 19 03:10:04 PM PST 24
Finished Feb 19 03:10:08 PM PST 24
Peak memory 214372 kb
Host smart-d42d4483-89f2-4cf6-bddd-da49ccb728a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192156568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.4192156568
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.4020595965
Short name T274
Test name
Test status
Simulation time 791757629 ps
CPU time 6.62 seconds
Started Feb 19 03:09:54 PM PST 24
Finished Feb 19 03:10:01 PM PST 24
Peak memory 208848 kb
Host smart-d1cab857-457c-4085-a85d-6169ec15c041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020595965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4020595965
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2552126970
Short name T868
Test name
Test status
Simulation time 987065269 ps
CPU time 13.88 seconds
Started Feb 19 03:09:55 PM PST 24
Finished Feb 19 03:10:10 PM PST 24
Peak memory 208420 kb
Host smart-2c18648d-d16d-4768-9f9d-993fe94fa6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552126970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2552126970
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2366625939
Short name T969
Test name
Test status
Simulation time 134221032 ps
CPU time 2.64 seconds
Started Feb 19 03:09:54 PM PST 24
Finished Feb 19 03:09:57 PM PST 24
Peak memory 208712 kb
Host smart-57982bc4-c049-4ca8-96be-42a0af094210
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366625939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2366625939
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.4187889973
Short name T884
Test name
Test status
Simulation time 143134323 ps
CPU time 3.5 seconds
Started Feb 19 03:09:53 PM PST 24
Finished Feb 19 03:09:58 PM PST 24
Peak memory 208312 kb
Host smart-40ec70b4-12f2-43b7-8eab-20979e3e2c33
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187889973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.4187889973
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2628406151
Short name T904
Test name
Test status
Simulation time 69427049 ps
CPU time 2.66 seconds
Started Feb 19 03:09:52 PM PST 24
Finished Feb 19 03:09:57 PM PST 24
Peak memory 208740 kb
Host smart-e7c04d10-a0e4-4038-9468-c06045f60b03
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628406151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2628406151
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.4035430778
Short name T941
Test name
Test status
Simulation time 6900741799 ps
CPU time 17 seconds
Started Feb 19 03:10:05 PM PST 24
Finished Feb 19 03:10:23 PM PST 24
Peak memory 210384 kb
Host smart-8ab67462-93b8-41c5-990f-2545905eac30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035430778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.4035430778
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1739545705
Short name T932
Test name
Test status
Simulation time 2192462409 ps
CPU time 11.14 seconds
Started Feb 19 03:09:55 PM PST 24
Finished Feb 19 03:10:07 PM PST 24
Peak memory 208028 kb
Host smart-c787514d-17c1-4681-bd34-f68039001d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739545705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1739545705
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.4094734434
Short name T1042
Test name
Test status
Simulation time 1111961964 ps
CPU time 24.22 seconds
Started Feb 19 03:09:58 PM PST 24
Finished Feb 19 03:10:23 PM PST 24
Peak memory 214944 kb
Host smart-76f775a0-5593-4db1-88bd-21d346cadc92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094734434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.4094734434
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3004732771
Short name T574
Test name
Test status
Simulation time 241001230 ps
CPU time 5.49 seconds
Started Feb 19 03:09:58 PM PST 24
Finished Feb 19 03:10:04 PM PST 24
Peak memory 222612 kb
Host smart-6cbcbb60-9396-47d2-a069-e141bfdfd956
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004732771 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3004732771
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2556883160
Short name T1029
Test name
Test status
Simulation time 786518598 ps
CPU time 11.39 seconds
Started Feb 19 03:09:58 PM PST 24
Finished Feb 19 03:10:10 PM PST 24
Peak memory 208788 kb
Host smart-4b82b253-6adc-4044-8207-d8061dce051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556883160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2556883160
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2309749836
Short name T44
Test name
Test status
Simulation time 2020822765 ps
CPU time 13.53 seconds
Started Feb 19 03:09:58 PM PST 24
Finished Feb 19 03:10:12 PM PST 24
Peak memory 211148 kb
Host smart-8c8e7804-b7b8-4ff1-9617-441c60252bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309749836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2309749836
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2898383987
Short name T575
Test name
Test status
Simulation time 17558018 ps
CPU time 0.84 seconds
Started Feb 19 03:10:14 PM PST 24
Finished Feb 19 03:10:18 PM PST 24
Peak memory 205824 kb
Host smart-bcdf4c69-827c-47ee-af38-e12e581080a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898383987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2898383987
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3556921262
Short name T131
Test name
Test status
Simulation time 135470398 ps
CPU time 5.35 seconds
Started Feb 19 03:10:04 PM PST 24
Finished Feb 19 03:10:10 PM PST 24
Peak memory 215484 kb
Host smart-0d2cd3d7-87f6-4070-91bd-844fe21b43a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556921262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3556921262
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2944329952
Short name T901
Test name
Test status
Simulation time 133051046 ps
CPU time 5.87 seconds
Started Feb 19 03:10:14 PM PST 24
Finished Feb 19 03:10:24 PM PST 24
Peak memory 221748 kb
Host smart-81a36fc3-e1ec-4020-a889-8050c4423a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944329952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2944329952
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.4016914378
Short name T836
Test name
Test status
Simulation time 1264372708 ps
CPU time 8.42 seconds
Started Feb 19 03:10:04 PM PST 24
Finished Feb 19 03:10:14 PM PST 24
Peak memory 208568 kb
Host smart-5acdbb2f-9d3d-4793-bb32-c1f4a8bcae6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016914378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4016914378
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2504244065
Short name T86
Test name
Test status
Simulation time 92397308 ps
CPU time 3.88 seconds
Started Feb 19 03:10:09 PM PST 24
Finished Feb 19 03:10:14 PM PST 24
Peak memory 208888 kb
Host smart-c99fdaac-00d8-4e28-b36f-32d88dfabf03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504244065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2504244065
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1210083031
Short name T248
Test name
Test status
Simulation time 1200907309 ps
CPU time 4.86 seconds
Started Feb 19 03:10:15 PM PST 24
Finished Feb 19 03:10:22 PM PST 24
Peak memory 214248 kb
Host smart-d97f414e-4f8c-44bf-865a-f98cbcb65b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210083031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1210083031
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3594246879
Short name T588
Test name
Test status
Simulation time 103172613 ps
CPU time 5.21 seconds
Started Feb 19 03:10:10 PM PST 24
Finished Feb 19 03:10:17 PM PST 24
Peak memory 222252 kb
Host smart-c0f806fa-ed40-4e4a-969e-7209420dfe08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594246879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3594246879
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2224642811
Short name T295
Test name
Test status
Simulation time 85553946 ps
CPU time 2.93 seconds
Started Feb 19 03:10:03 PM PST 24
Finished Feb 19 03:10:07 PM PST 24
Peak memory 208088 kb
Host smart-b4d78213-64d8-4a38-b824-433d3f2f7e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224642811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2224642811
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3455849327
Short name T967
Test name
Test status
Simulation time 537832769 ps
CPU time 3.95 seconds
Started Feb 19 03:10:02 PM PST 24
Finished Feb 19 03:10:07 PM PST 24
Peak memory 206672 kb
Host smart-68c70874-45b5-4ac5-90a6-4a7b7a09b6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455849327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3455849327
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1932819850
Short name T1049
Test name
Test status
Simulation time 881382273 ps
CPU time 31.3 seconds
Started Feb 19 03:10:02 PM PST 24
Finished Feb 19 03:10:34 PM PST 24
Peak memory 208800 kb
Host smart-758b026d-8c66-47af-96b2-c7f5effba8b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932819850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1932819850
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3047881324
Short name T583
Test name
Test status
Simulation time 3574443595 ps
CPU time 36.8 seconds
Started Feb 19 03:10:04 PM PST 24
Finished Feb 19 03:10:42 PM PST 24
Peak memory 208000 kb
Host smart-edf9bc10-9f23-440f-9a53-dc639c21dd64
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047881324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3047881324
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2951592519
Short name T667
Test name
Test status
Simulation time 570743077 ps
CPU time 7.22 seconds
Started Feb 19 03:10:02 PM PST 24
Finished Feb 19 03:10:10 PM PST 24
Peak memory 206888 kb
Host smart-3190308f-334f-46bb-8f78-bcedc59cfd12
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951592519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2951592519
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2708733274
Short name T1001
Test name
Test status
Simulation time 199416300 ps
CPU time 7.1 seconds
Started Feb 19 03:10:15 PM PST 24
Finished Feb 19 03:10:25 PM PST 24
Peak memory 208528 kb
Host smart-e8426284-8a71-4796-a400-5f2d5665e3c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708733274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2708733274
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.4009690031
Short name T556
Test name
Test status
Simulation time 58898917 ps
CPU time 2.7 seconds
Started Feb 19 03:09:58 PM PST 24
Finished Feb 19 03:10:01 PM PST 24
Peak memory 206856 kb
Host smart-42edff2a-0a74-4e1e-a734-81bee9224fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009690031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.4009690031
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3588053423
Short name T747
Test name
Test status
Simulation time 97879927 ps
CPU time 3.37 seconds
Started Feb 19 03:10:19 PM PST 24
Finished Feb 19 03:10:24 PM PST 24
Peak memory 222644 kb
Host smart-ab523c82-5266-4fc9-9b2f-41af0546f6e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588053423 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3588053423
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.433053770
Short name T101
Test name
Test status
Simulation time 550222622 ps
CPU time 4.96 seconds
Started Feb 19 03:10:06 PM PST 24
Finished Feb 19 03:10:13 PM PST 24
Peak memory 208132 kb
Host smart-72e3f2cd-a925-45f2-820e-b668e85d84d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433053770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.433053770
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.525786021
Short name T390
Test name
Test status
Simulation time 513174713 ps
CPU time 2.31 seconds
Started Feb 19 03:10:15 PM PST 24
Finished Feb 19 03:10:20 PM PST 24
Peak memory 210520 kb
Host smart-2f9b86e3-9af8-45ce-8add-4659df776472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525786021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.525786021
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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