Summary for Variable cp_intr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
1 |
0 |
1 |
100.00 |
User Defined Bins for cp_intr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
all_values[0] |
52469 |
1 |
|
|
T1 |
218 |
|
T2 |
65 |
|
T3 |
33 |
Summary for Variable cp_intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_en
Bins
| | | | | | | | | | | | |
auto[0] |
30781 |
1 |
|
|
T1 |
93 |
|
T2 |
2 |
|
T3 |
33 |
auto[1] |
21688 |
1 |
|
|
T1 |
125 |
|
T2 |
63 |
|
T4 |
212 |
Summary for Variable cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_intr_state
Bins
| | | | | | | | | | | | |
auto[0] |
26065 |
1 |
|
|
T1 |
111 |
|
T2 |
34 |
|
T3 |
17 |
auto[1] |
26404 |
1 |
|
|
T1 |
107 |
|
T2 |
31 |
|
T3 |
16 |
Summary for Cross intr_cg_cc
Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for intr_cg_cc
Bins
| | | | | | | | | | | | | | |
all_values[0] |
auto[0] |
auto[0] |
15236 |
1 |
|
|
T1 |
47 |
|
T2 |
2 |
|
T3 |
17 |
all_values[0] |
auto[0] |
auto[1] |
15545 |
1 |
|
|
T1 |
46 |
|
T3 |
16 |
|
T4 |
107 |
all_values[0] |
auto[1] |
auto[0] |
10829 |
1 |
|
|
T1 |
64 |
|
T2 |
32 |
|
T4 |
110 |
all_values[0] |
auto[1] |
auto[1] |
10859 |
1 |
|
|
T1 |
61 |
|
T2 |
31 |
|
T4 |
102 |