Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11003

1

T1

45

T2

10

T3

2

auto[Attestation]

7435

1

T1

38

T2

13

T3

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2651	1			T1	12		T2	2		T4	26
auto[Aes]	3355	1			T1	12		T2	6		T3	8
auto[Kmac]	3393	1			T1	17		T2	2		T4	14
auto[Otbn]	3354	1			T1	11		T2	4		T4	19

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7406	1			T1	24		T2	8		T3	8
auto[OpGenId]	5685	1			T1	31		T2	9		T4	58
auto[OpGenSwOut]	5760	1			T1	22		T2	9		T4	50
auto[OpGenHwOut]	6993	1			T1	30		T2	5		T3	8
auto[OpDisable]	128	1			T43	1		T44	1		T45	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9725

1

T1

33

T2

13

T3

8

auto[OpDoneFail]

16247

1

T1

74

T2

18

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6146	1			T1	19		T2	1		T3	1
auto[StInit]	3980	1			T1	14		T2	5		T3	2
auto[StCreatorRootKey]	2867	1			T1	11		T2	4		T3	2
auto[StOwnerIntKey]	2562	1			T1	16		T2	4		T3	2
auto[StOwnerKey]	2203	1			T1	6		T2	3		T3	2
auto[StDisabled]	7147	1			T1	41		T2	14		T3	7
auto[StInvalid]	1067	1			T37	16		T180	28		T181	22

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	317	1			T4	3		T13	1		T14	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	102	1			T2	1		T4	1		T32	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	79	1			T4	5		T38	1		T127	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	76	1			T44	2		T47	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	49	1			T127	1		T139	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	184	1			T1	2		T4	4		T182	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	40	1			T180	1		T23	1		T183	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	315	1			T13	1		T14	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	118	1			T1	1		T4	1		T8	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	63	1			T4	1		T15	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	59	1			T1	1		T184	1		T123	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	47	1			T1	1		T182	1		T125	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	184	1			T2	1		T4	1		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	32	1			T37	1		T180	1		T181	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	313	1			T1	1		T4	2		T13	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	111	1			T1	1		T4	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	80	1			T4	1		T32	1		T185	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	70	1			T2	1		T4	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	62	1			T4	1		T186	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	199	1			T1	3		T14	1		T182	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	33	1			T23	2		T187	2		T188	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	301	1			T1	1		T4	3		T13	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	100	1			T16	2		T45	1		T189	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T6	3		T190	1		T191	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	62	1			T1	1		T44	1		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	50	1			T47	1		T6	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	199	1			T4	3		T14	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	29	1			T180	1		T181	1		T193	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	70	1			T4	3		T47	5		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	105	1			T124	1		T108	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T15	1		T82	2		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	62	1			T1	2		T45	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T4	1		T125	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	203	1			T1	1		T4	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	34	1			T181	1		T194	1		T195	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	44	1			T4	3		T47	2		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	123	1			T4	3		T43	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	82	1			T84	1		T82	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	70	1			T2	1		T4	1		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	49	1			T4	1		T108	1		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	199	1			T1	1		T2	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	25	1			T37	1		T23	1		T193	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	73	1			T1	1		T4	3		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	106	1			T1	2		T84	1		T127	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	78	1			T197	1		T60	1		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	50	1			T84	1		T108	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	53	1			T4	1		T17	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	186	1			T1	2		T2	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	35	1			T180	1		T23	2		T194	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	58	1			T4	2		T47	2		T6	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	115	1			T1	1		T16	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T2	1		T15	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T82	1		T108	1		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	54	1			T2	1		T186	1		T125	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	203	1			T2	1		T4	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	42	1			T180	3		T23	2		T183	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	250	1			T1	1		T4	2		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	97	1			T1	1		T4	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	71	1			T1	1		T4	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	54	1			T4	1		T84	1		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	42	1			T196	3		T47	2		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	161	1			T2	1		T43	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	26	1			T180	1		T181	1		T194	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	491	1			T1	1		T4	2		T13	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	156	1			T198	1		T189	1		T185	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	87	1			T1	1		T32	1		T198	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	90	1			T1	1		T2	1		T3	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	73	1			T3	1		T14	1		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	268	1			T1	2		T2	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	35	1			T181	1		T193	2		T183	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	492	1			T1	1		T4	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	122	1			T31	1		T39	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T39	1		T84	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T39	1		T34	1		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	84	1			T4	1		T39	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	283	1			T1	3		T4	1		T39	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	33	1			T180	1		T23	1		T193	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	465	1			T1	2		T4	3		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	138	1			T1	2		T8	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	116	1			T83	1		T199	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	98	1			T1	1		T16	1		T84	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	95	1			T83	1		T47	1		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	231	1			T4	1		T82	1		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	40	1			T37	1		T180	2		T181	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	46	1			T4	1		T47	1		T54	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	97	1			T4	1		T55	2		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	70	1			T196	1		T59	1		T201	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	54	1			T55	1		T47	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	41	1			T4	1		T200	1		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	160	1			T1	4		T108	1		T125	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	32	1			T37	2		T180	1		T181	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	63	1			T54	1		T6	1		T202	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	124	1			T3	1		T16	1		T31	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	92	1			T3	1		T14	1		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	98	1			T4	1		T33	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	87	1			T204	1		T198	1		T205	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	255	1			T1	3		T2	1		T3	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	26	1			T180	1		T193	1		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	54	1			T1	1		T47	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	121	1			T84	1		T17	1		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T44	1		T182	1		T108	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T1	1		T84	1		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	96	1			T184	1		T182	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	254	1			T1	1		T39	2		T108	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	24	1			T181	1		T23	2		T193	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	50	1			T47	2		T6	3		T101	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	127	1			T1	1		T8	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	101	1			T1	1		T45	1		T184	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	90	1			T84	1		T199	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	69	1			T16	2		T199	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	261	1			T1	1		T2	1		T4	6
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	22	1			T180	1		T181	1		T23	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	196	1			T4	5		T44	2		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	651	1			T1	2		T2	1		T4	8
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	157	1			T1	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	661	1			T1	2		T2	1		T4	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	199	1			T2	1		T4	3		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	669	1			T1	5		T4	3		T13	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	183	1			T44	1		T82	1		T186	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	643	1			T1	2		T4	6		T13	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	183	1			T1	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	420	1			T1	2		T4	4		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	187	1			T2	1		T4	1		T84	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	405	1			T1	1		T2	1		T4	8
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	166	1			T4	1		T84	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	415	1			T1	5		T2	1		T4	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	197	1			T2	2		T15	1		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	428	1			T1	1		T2	1		T4	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	160	1			T4	2		T84	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	541	1			T1	3		T2	1		T4	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	239	1			T1	2		T2	1		T3	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	961	1			T1	3		T2	1		T4	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	259	1			T4	1		T39	3		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	943	1			T1	4		T4	2		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	294	1			T16	1		T84	2		T83	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	889	1			T1	5		T4	4		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	151	1			T4	1		T55	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	349	1			T1	4		T4	2		T55	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	268	1			T3	1		T4	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	477	1			T1	3		T2	1		T3	5
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	275	1			T84	1		T44	1		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	467	1			T1	3		T39	2		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	247	1			T1	1		T16	2		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	473	1			T1	2		T2	1		T4	6