Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29793

1

T1

121

T2

36

T3

22

auto[1]

325

1

T108

7

T125

8

T139

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	29803	1			T1	121		T2	36		T3	22
auto[134217728:268435455]	9	1			T139	1		T81	1		T373	2
auto[268435456:402653183]	5	1			T108	1		T174	1		T422	1
auto[402653184:536870911]	8	1			T81	1		T373	1		T258	1
auto[536870912:671088639]	13	1			T233	2		T373	1		T258	1
auto[671088640:805306367]	11	1			T108	1		T139	1		T174	1
auto[805306368:939524095]	13	1			T125	1		T233	2		T346	1
auto[939524096:1073741823]	8	1			T125	1		T232	1		T229	1
auto[1073741824:1207959551]	10	1			T108	1		T81	3		T423	1
auto[1207959552:1342177279]	5	1			T174	1		T233	1		T298	1
auto[1342177280:1476395007]	14	1			T108	1		T355	1		T236	1
auto[1476395008:1610612735]	12	1			T174	1		T232	2		T346	1
auto[1610612736:1744830463]	7	1			T139	1		T81	1		T236	1
auto[1744830464:1879048191]	9	1			T174	1		T232	1		T245	1
auto[1879048192:2013265919]	15	1			T125	1		T139	1		T232	1
auto[2013265920:2147483647]	7	1			T174	1		T81	1		T373	1
auto[2147483648:2281701375]	7	1			T423	3		T230	1		T424	1
auto[2281701376:2415919103]	11	1			T108	1		T139	1		T302	1
auto[2415919104:2550136831]	8	1			T125	1		T228	1		T425	3
auto[2550136832:2684354559]	14	1			T139	1		T81	1		T258	1
auto[2684354560:2818572287]	12	1			T108	1		T190	1		T236	2
auto[2818572288:2952790015]	9	1			T125	1		T236	1		T423	1
auto[2952790016:3087007743]	8	1			T232	1		T373	2		T298	1
auto[3087007744:3221225471]	17	1			T125	1		T190	1		T232	1
auto[3221225472:3355443199]	12	1			T81	1		T233	1		T236	1
auto[3355443200:3489660927]	8	1			T232	1		T426	1		T259	1
auto[3489660928:3623878655]	12	1			T174	1		T355	1		T233	2
auto[3623878656:3758096383]	13	1			T125	2		T174	1		T236	2
auto[3758096384:3892314111]	8	1			T139	1		T302	2		T427	1
auto[3892314112:4026531839]	6	1			T190	2		T245	1		T229	1
auto[4026531840:4160749567]	12	1			T233	1		T236	1		T302	1
auto[4160749568:4294967295]	12	1			T81	1		T236	1		T302	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	29793	1			T1	121		T2	36		T3	22
auto[0:134217727]	auto[1]	10	1			T108	1		T190	1		T81	1
auto[134217728:268435455]	auto[1]	9	1			T139	1		T81	1		T373	2
auto[268435456:402653183]	auto[1]	5	1			T108	1		T174	1		T422	1
auto[402653184:536870911]	auto[1]	8	1			T81	1		T373	1		T258	1
auto[536870912:671088639]	auto[1]	13	1			T233	2		T373	1		T258	1
auto[671088640:805306367]	auto[1]	11	1			T108	1		T139	1		T174	1
auto[805306368:939524095]	auto[1]	13	1			T125	1		T233	2		T346	1
auto[939524096:1073741823]	auto[1]	8	1			T125	1		T232	1		T229	1
auto[1073741824:1207959551]	auto[1]	10	1			T108	1		T81	3		T423	1
auto[1207959552:1342177279]	auto[1]	5	1			T174	1		T233	1		T298	1
auto[1342177280:1476395007]	auto[1]	14	1			T108	1		T355	1		T236	1
auto[1476395008:1610612735]	auto[1]	12	1			T174	1		T232	2		T346	1
auto[1610612736:1744830463]	auto[1]	7	1			T139	1		T81	1		T236	1
auto[1744830464:1879048191]	auto[1]	9	1			T174	1		T232	1		T245	1
auto[1879048192:2013265919]	auto[1]	15	1			T125	1		T139	1		T232	1
auto[2013265920:2147483647]	auto[1]	7	1			T174	1		T81	1		T373	1
auto[2147483648:2281701375]	auto[1]	7	1			T423	3		T230	1		T424	1
auto[2281701376:2415919103]	auto[1]	11	1			T108	1		T139	1		T302	1
auto[2415919104:2550136831]	auto[1]	8	1			T125	1		T228	1		T425	3
auto[2550136832:2684354559]	auto[1]	14	1			T139	1		T81	1		T258	1
auto[2684354560:2818572287]	auto[1]	12	1			T108	1		T190	1		T236	2
auto[2818572288:2952790015]	auto[1]	9	1			T125	1		T236	1		T423	1
auto[2952790016:3087007743]	auto[1]	8	1			T232	1		T373	2		T298	1
auto[3087007744:3221225471]	auto[1]	17	1			T125	1		T190	1		T232	1
auto[3221225472:3355443199]	auto[1]	12	1			T81	1		T233	1		T236	1
auto[3355443200:3489660927]	auto[1]	8	1			T232	1		T426	1		T259	1
auto[3489660928:3623878655]	auto[1]	12	1			T174	1		T355	1		T233	2
auto[3623878656:3758096383]	auto[1]	13	1			T125	2		T174	1		T236	2
auto[3758096384:3892314111]	auto[1]	8	1			T139	1		T302	2		T427	1
auto[3892314112:4026531839]	auto[1]	6	1			T190	2		T245	1		T229	1
auto[4026531840:4160749567]	auto[1]	12	1			T233	1		T236	1		T302	1
auto[4160749568:4294967295]	auto[1]	12	1			T81	1		T236	1		T302	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1433

1

T1

3

T2

1

T4

10

auto[1]

1644

1

T1

9

T2

3

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T1	2		T4	1		T8	1
auto[134217728:268435455]	99	1			T182	1		T196	1		T52	1
auto[268435456:402653183]	97	1			T1	1		T16	1		T17	1
auto[402653184:536870911]	73	1			T14	1		T37	1		T108	1
auto[536870912:671088639]	109	1			T1	1		T4	2		T184	1
auto[671088640:805306367]	113	1			T4	1		T189	1		T40	1
auto[805306368:939524095]	101	1			T1	1		T4	1		T82	1
auto[939524096:1073741823]	93	1			T43	1		T82	1		T24	1
auto[1073741824:1207959551]	95	1			T1	1		T15	1		T43	1
auto[1207959552:1342177279]	91	1			T4	1		T14	1		T182	1
auto[1342177280:1476395007]	94	1			T182	1		T48	1		T47	1
auto[1476395008:1610612735]	102	1			T4	1		T15	1		T48	1
auto[1610612736:1744830463]	100	1			T1	1		T184	2		T55	1
auto[1744830464:1879048191]	90	1			T2	1		T4	1		T13	1
auto[1879048192:2013265919]	96	1			T186	1		T108	1		T47	3
auto[2013265920:2147483647]	95	1			T14	1		T45	1		T60	1
auto[2147483648:2281701375]	88	1			T44	1		T186	1		T200	1
auto[2281701376:2415919103]	113	1			T14	1		T84	1		T43	1
auto[2415919104:2550136831]	101	1			T13	1		T127	1		T181	1
auto[2550136832:2684354559]	93	1			T24	1		T37	1		T108	1
auto[2684354560:2818572287]	95	1			T1	1		T2	1		T14	1
auto[2818572288:2952790015]	84	1			T1	1		T16	1		T17	1
auto[2952790016:3087007743]	107	1			T1	1		T15	1		T44	1
auto[3087007744:3221225471]	101	1			T2	1		T4	1		T40	2
auto[3221225472:3355443199]	90	1			T4	1		T14	1		T6	2
auto[3355443200:3489660927]	94	1			T8	1		T47	1		T6	1
auto[3489660928:3623878655]	105	1			T2	1		T14	1		T184	2
auto[3623878656:3758096383]	104	1			T4	1		T16	2		T34	1
auto[3758096384:3892314111]	94	1			T1	1		T44	1		T60	1
auto[3892314112:4026531839]	106	1			T16	2		T55	1		T47	1
auto[4026531840:4160749567]	75	1			T1	1		T13	1		T184	1
auto[4160749568:4294967295]	87	1			T4	1		T82	1		T60	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T4	1		T52	1		T6	1
auto[0:134217727]	auto[1]	45	1			T1	2		T8	1		T47	1
auto[134217728:268435455]	auto[0]	45	1			T182	1		T6	2		T23	1
auto[134217728:268435455]	auto[1]	54	1			T196	1		T52	1		T6	1
auto[268435456:402653183]	auto[0]	47	1			T16	1		T17	1		T28	1
auto[268435456:402653183]	auto[1]	50	1			T1	1		T45	1		T47	1
auto[402653184:536870911]	auto[0]	41	1			T6	1		T257	1		T90	1
auto[402653184:536870911]	auto[1]	32	1			T14	1		T37	1		T108	1
auto[536870912:671088639]	auto[0]	51	1			T1	1		T4	1		T26	1
auto[536870912:671088639]	auto[1]	58	1			T4	1		T184	1		T52	1
auto[671088640:805306367]	auto[0]	56	1			T4	1		T40	1		T202	1
auto[671088640:805306367]	auto[1]	57	1			T189	1		T6	2		T166	1
auto[805306368:939524095]	auto[0]	52	1			T4	1		T82	1		T6	1
auto[805306368:939524095]	auto[1]	49	1			T1	1		T6	2		T50	1
auto[939524096:1073741823]	auto[0]	40	1			T82	1		T24	1		T202	1
auto[939524096:1073741823]	auto[1]	53	1			T43	1		T47	1		T6	1
auto[1073741824:1207959551]	auto[0]	41	1			T43	1		T34	1		T184	1
auto[1073741824:1207959551]	auto[1]	54	1			T1	1		T15	1		T82	1
auto[1207959552:1342177279]	auto[0]	47	1			T4	1		T182	1		T6	1
auto[1207959552:1342177279]	auto[1]	44	1			T14	1		T40	1		T6	1
auto[1342177280:1476395007]	auto[0]	44	1			T47	1		T6	1		T57	1
auto[1342177280:1476395007]	auto[1]	50	1			T182	1		T48	1		T57	1
auto[1476395008:1610612735]	auto[0]	50	1			T4	1		T15	1		T47	1
auto[1476395008:1610612735]	auto[1]	52	1			T48	1		T47	1		T6	1
auto[1610612736:1744830463]	auto[0]	39	1			T127	1		T49	1		T7	1
auto[1610612736:1744830463]	auto[1]	61	1			T1	1		T184	2		T55	1
auto[1744830464:1879048191]	auto[0]	42	1			T4	1		T82	1		T185	1
auto[1744830464:1879048191]	auto[1]	48	1			T2	1		T13	1		T182	1
auto[1879048192:2013265919]	auto[0]	45	1			T108	1		T47	1		T174	1
auto[1879048192:2013265919]	auto[1]	51	1			T186	1		T47	2		T6	3
auto[2013265920:2147483647]	auto[0]	41	1			T45	1		T60	1		T52	1
auto[2013265920:2147483647]	auto[1]	54	1			T14	1		T186	1		T51	1
auto[2147483648:2281701375]	auto[0]	42	1			T186	1		T200	1		T139	1
auto[2147483648:2281701375]	auto[1]	46	1			T44	1		T180	1		T22	1
auto[2281701376:2415919103]	auto[0]	49	1			T84	1		T60	1		T40	1
auto[2281701376:2415919103]	auto[1]	64	1			T14	1		T43	1		T196	1
auto[2415919104:2550136831]	auto[0]	43	1			T181	1		T57	1		T242	1
auto[2415919104:2550136831]	auto[1]	58	1			T13	1		T127	1		T246	1
auto[2550136832:2684354559]	auto[0]	43	1			T24	1		T108	1		T257	1
auto[2550136832:2684354559]	auto[1]	50	1			T37	1		T201	1		T239	1
auto[2684354560:2818572287]	auto[0]	50	1			T14	1		T202	1		T89	1
auto[2684354560:2818572287]	auto[1]	45	1			T1	1		T2	1		T6	1
auto[2818572288:2952790015]	auto[0]	38	1			T1	1		T16	1		T17	1
auto[2818572288:2952790015]	auto[1]	46	1			T46	1		T47	1		T54	1
auto[2952790016:3087007743]	auto[0]	60	1			T125	1		T289	1		T6	1
auto[2952790016:3087007743]	auto[1]	47	1			T1	1		T15	1		T44	1
auto[3087007744:3221225471]	auto[0]	37	1			T4	1		T40	1		T6	2
auto[3087007744:3221225471]	auto[1]	64	1			T2	1		T40	1		T41	1
auto[3221225472:3355443199]	auto[0]	40	1			T14	1		T6	2		T174	1
auto[3221225472:3355443199]	auto[1]	50	1			T4	1		T7	1		T263	1
auto[3355443200:3489660927]	auto[0]	50	1			T8	1		T47	1		T57	1
auto[3355443200:3489660927]	auto[1]	44	1			T6	1		T49	1		T194	1
auto[3489660928:3623878655]	auto[0]	45	1			T2	1		T184	1		T127	2
auto[3489660928:3623878655]	auto[1]	60	1			T14	1		T184	1		T182	1
auto[3623878656:3758096383]	auto[0]	54	1			T4	1		T16	1		T182	1
auto[3623878656:3758096383]	auto[1]	50	1			T16	1		T34	1		T186	1
auto[3758096384:3892314111]	auto[0]	32	1			T60	1		T51	1		T6	1
auto[3758096384:3892314111]	auto[1]	62	1			T1	1		T44	1		T125	2
auto[3892314112:4026531839]	auto[0]	51	1			T16	2		T55	1		T21	1
auto[3892314112:4026531839]	auto[1]	55	1			T47	1		T6	2		T64	1
auto[4026531840:4160749567]	auto[0]	29	1			T1	1		T139	1		T6	1
auto[4026531840:4160749567]	auto[1]	46	1			T13	1		T184	1		T182	2
auto[4160749568:4294967295]	auto[0]	42	1			T4	1		T82	1		T37	1
auto[4160749568:4294967295]	auto[1]	45	1			T60	1		T41	1		T21	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1446

1

T1

3

T2

1

T4

10

auto[1]

1634

1

T1

9

T2

3

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	86	1			T34	1		T60	1		T186	1
auto[134217728:268435455]	80	1			T4	1		T37	1		T125	1
auto[268435456:402653183]	115	1			T13	1		T43	1		T48	1
auto[402653184:536870911]	105	1			T4	1		T17	1		T108	1
auto[536870912:671088639]	96	1			T4	1		T8	1		T44	1
auto[671088640:805306367]	93	1			T14	1		T45	1		T139	1
auto[805306368:939524095]	79	1			T14	1		T125	1		T52	1
auto[939524096:1073741823]	108	1			T14	1		T17	1		T24	1
auto[1073741824:1207959551]	109	1			T182	1		T185	1		T40	1
auto[1207959552:1342177279]	103	1			T1	1		T4	2		T16	1
auto[1342177280:1476395007]	103	1			T4	1		T14	1		T82	1
auto[1476395008:1610612735]	89	1			T1	1		T82	1		T186	1
auto[1610612736:1744830463]	93	1			T82	1		T184	1		T182	1
auto[1744830464:1879048191]	78	1			T184	1		T139	1		T6	1
auto[1879048192:2013265919]	94	1			T82	1		T40	1		T174	1
auto[2013265920:2147483647]	94	1			T14	1		T24	1		T182	1
auto[2147483648:2281701375]	92	1			T4	2		T184	1		T47	2
auto[2281701376:2415919103]	97	1			T1	2		T40	1		T41	1
auto[2415919104:2550136831]	95	1			T1	1		T2	1		T16	1
auto[2550136832:2684354559]	110	1			T16	1		T28	1		T52	1
auto[2684354560:2818572287]	103	1			T14	1		T182	1		T125	1
auto[2818572288:2952790015]	90	1			T4	1		T15	1		T16	1
auto[2952790016:3087007743]	87	1			T13	1		T44	1		T60	1
auto[3087007744:3221225471]	103	1			T1	1		T184	1		T186	1
auto[3221225472:3355443199]	117	1			T1	1		T2	1		T16	2
auto[3355443200:3489660927]	102	1			T1	1		T14	1		T139	1
auto[3489660928:3623878655]	91	1			T1	1		T2	1		T8	1
auto[3623878656:3758096383]	100	1			T13	1		T15	1		T84	1
auto[3758096384:3892314111]	92	1			T1	1		T2	1		T184	1
auto[3892314112:4026531839]	106	1			T4	2		T43	1		T184	1
auto[4026531840:4160749567]	92	1			T1	1		T47	1		T139	1
auto[4160749568:4294967295]	78	1			T1	1		T4	1		T55	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	39	1			T186	1		T6	2		T180	1
auto[0:134217727]	auto[1]	47	1			T34	1		T60	1		T52	1
auto[134217728:268435455]	auto[0]	31	1			T4	1		T6	1		T181	1
auto[134217728:268435455]	auto[1]	49	1			T37	1		T125	1		T57	1
auto[268435456:402653183]	auto[0]	63	1			T108	1		T47	1		T6	1
auto[268435456:402653183]	auto[1]	52	1			T13	1		T43	1		T48	1
auto[402653184:536870911]	auto[0]	53	1			T4	1		T17	1		T196	1
auto[402653184:536870911]	auto[1]	52	1			T108	1		T47	1		T54	1
auto[536870912:671088639]	auto[0]	45	1			T4	1		T6	2		T89	1
auto[536870912:671088639]	auto[1]	51	1			T8	1		T44	1		T184	1
auto[671088640:805306367]	auto[0]	46	1			T14	1		T139	1		T6	3
auto[671088640:805306367]	auto[1]	47	1			T45	1		T6	1		T50	1
auto[805306368:939524095]	auto[0]	41	1			T14	1		T125	1		T114	1
auto[805306368:939524095]	auto[1]	38	1			T52	1		T242	1		T234	1
auto[939524096:1073741823]	auto[0]	48	1			T14	1		T17	1		T24	1
auto[939524096:1073741823]	auto[1]	60	1			T55	1		T46	1		T127	1
auto[1073741824:1207959551]	auto[0]	50	1			T182	1		T51	1		T139	1
auto[1073741824:1207959551]	auto[1]	59	1			T185	1		T40	1		T51	1
auto[1207959552:1342177279]	auto[0]	51	1			T4	2		T16	1		T127	1
auto[1207959552:1342177279]	auto[1]	52	1			T1	1		T49	1		T236	2
auto[1342177280:1476395007]	auto[0]	50	1			T4	1		T82	1		T182	1
auto[1342177280:1476395007]	auto[1]	53	1			T14	1		T48	1		T47	1
auto[1476395008:1610612735]	auto[0]	37	1			T185	1		T127	1		T195	1
auto[1476395008:1610612735]	auto[1]	52	1			T1	1		T82	1		T186	1
auto[1610612736:1744830463]	auto[0]	53	1			T82	1		T60	1		T47	1
auto[1610612736:1744830463]	auto[1]	40	1			T184	1		T182	1		T139	1
auto[1744830464:1879048191]	auto[0]	32	1			T184	1		T236	1		T309	1
auto[1744830464:1879048191]	auto[1]	46	1			T139	1		T6	1		T166	1
auto[1879048192:2013265919]	auto[0]	44	1			T82	1		T40	1		T50	1
auto[1879048192:2013265919]	auto[1]	50	1			T174	1		T23	1		T67	1
auto[2013265920:2147483647]	auto[0]	49	1			T24	1		T182	1		T6	1
auto[2013265920:2147483647]	auto[1]	45	1			T14	1		T201	1		T252	1
auto[2147483648:2281701375]	auto[0]	42	1			T4	1		T184	1		T47	1
auto[2147483648:2281701375]	auto[1]	50	1			T4	1		T47	1		T231	1
auto[2281701376:2415919103]	auto[0]	47	1			T40	1		T6	1		T101	1
auto[2281701376:2415919103]	auto[1]	50	1			T1	2		T41	1		T25	1
auto[2415919104:2550136831]	auto[0]	42	1			T1	1		T16	1		T37	1
auto[2415919104:2550136831]	auto[1]	53	1			T2	1		T196	1		T47	2
auto[2550136832:2684354559]	auto[0]	54	1			T28	1		T52	1		T6	1
auto[2550136832:2684354559]	auto[1]	56	1			T16	1		T6	2		T114	1
auto[2684354560:2818572287]	auto[0]	39	1			T47	1		T289	1		T6	1
auto[2684354560:2818572287]	auto[1]	64	1			T14	1		T182	1		T125	1
auto[2818572288:2952790015]	auto[0]	35	1			T4	1		T15	1		T16	1
auto[2818572288:2952790015]	auto[1]	55	1			T43	1		T182	1		T37	1
auto[2952790016:3087007743]	auto[0]	42	1			T60	1		T242	1		T49	1
auto[2952790016:3087007743]	auto[1]	45	1			T13	1		T44	1		T41	1
auto[3087007744:3221225471]	auto[0]	59	1			T6	2		T174	1		T183	1
auto[3087007744:3221225471]	auto[1]	44	1			T1	1		T184	1		T186	1
auto[3221225472:3355443199]	auto[0]	46	1			T2	1		T16	2		T45	1
auto[3221225472:3355443199]	auto[1]	71	1			T1	1		T182	1		T189	1
auto[3355443200:3489660927]	auto[0]	48	1			T114	1		T233	1		T428	2
auto[3355443200:3489660927]	auto[1]	54	1			T1	1		T14	1		T139	1
auto[3489660928:3623878655]	auto[0]	40	1			T1	1		T8	1		T15	1
auto[3489660928:3623878655]	auto[1]	51	1			T2	1		T44	1		T34	1
auto[3623878656:3758096383]	auto[0]	51	1			T183	1		T89	1		T7	1
auto[3623878656:3758096383]	auto[1]	49	1			T13	1		T15	1		T84	1
auto[3758096384:3892314111]	auto[0]	44	1			T184	1		T6	2		T181	1
auto[3758096384:3892314111]	auto[1]	48	1			T1	1		T2	1		T182	1
auto[3892314112:4026531839]	auto[0]	44	1			T4	1		T108	1		T6	1
auto[3892314112:4026531839]	auto[1]	62	1			T4	1		T43	1		T184	1
auto[4026531840:4160749567]	auto[0]	40	1			T6	1		T428	1		T409	1
auto[4026531840:4160749567]	auto[1]	52	1			T1	1		T47	1		T139	1
auto[4160749568:4294967295]	auto[0]	41	1			T1	1		T4	1		T55	1
auto[4160749568:4294967295]	auto[1]	37	1			T186	1		T242	1		T193	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1438

1

T1

3

T4

10

T8

2

auto[1]

1641

1

T1

9

T2

4

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T184	1		T48	1		T185	1
auto[134217728:268435455]	88	1			T8	1		T47	1		T6	1
auto[268435456:402653183]	96	1			T16	1		T43	1		T82	1
auto[402653184:536870911]	100	1			T1	1		T47	1		T28	1
auto[536870912:671088639]	95	1			T4	1		T40	1		T125	2
auto[671088640:805306367]	97	1			T1	1		T43	1		T125	1
auto[805306368:939524095]	94	1			T8	1		T82	1		T60	1
auto[939524096:1073741823]	119	1			T16	1		T44	1		T17	1
auto[1073741824:1207959551]	95	1			T1	1		T47	1		T52	1
auto[1207959552:1342177279]	119	1			T4	1		T16	1		T55	1
auto[1342177280:1476395007]	111	1			T14	1		T15	1		T44	2
auto[1476395008:1610612735]	94	1			T14	1		T45	1		T47	1
auto[1610612736:1744830463]	101	1			T14	2		T184	1		T24	1
auto[1744830464:1879048191]	97	1			T15	1		T184	1		T182	1
auto[1879048192:2013265919]	109	1			T2	1		T189	1		T51	1
auto[2013265920:2147483647]	98	1			T4	2		T45	1		T60	1
auto[2147483648:2281701375]	93	1			T4	1		T127	1		T47	1
auto[2281701376:2415919103]	87	1			T4	1		T13	1		T34	1
auto[2415919104:2550136831]	78	1			T1	2		T2	1		T184	1
auto[2550136832:2684354559]	76	1			T43	1		T60	1		T6	2
auto[2684354560:2818572287]	87	1			T14	1		T16	1		T82	2
auto[2818572288:2952790015]	87	1			T47	1		T6	1		T242	1
auto[2952790016:3087007743]	87	1			T37	1		T47	1		T41	1
auto[3087007744:3221225471]	89	1			T13	1		T182	1		T108	1
auto[3221225472:3355443199]	99	1			T1	1		T4	1		T182	1
auto[3355443200:3489660927]	91	1			T1	1		T4	2		T13	1
auto[3489660928:3623878655]	94	1			T2	1		T4	1		T15	1
auto[3623878656:3758096383]	80	1			T1	1		T2	1		T14	1
auto[3758096384:3892314111]	108	1			T1	2		T14	1		T55	1
auto[3892314112:4026531839]	105	1			T1	2		T82	1		T182	2
auto[4026531840:4160749567]	102	1			T16	1		T17	1		T186	1
auto[4160749568:4294967295]	95	1			T4	2		T84	1		T127	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T184	1		T185	1		T40	1
auto[0:134217727]	auto[1]	59	1			T48	1		T127	1		T54	1
auto[134217728:268435455]	auto[0]	41	1			T8	1		T114	1		T242	1
auto[134217728:268435455]	auto[1]	47	1			T47	1		T6	1		T194	1
auto[268435456:402653183]	auto[0]	43	1			T16	1		T6	1		T23	1
auto[268435456:402653183]	auto[1]	53	1			T43	1		T82	1		T196	1
auto[402653184:536870911]	auto[0]	43	1			T1	1		T28	1		T6	1
auto[402653184:536870911]	auto[1]	57	1			T47	1		T139	1		T239	1
auto[536870912:671088639]	auto[0]	47	1			T4	1		T47	1		T139	1
auto[536870912:671088639]	auto[1]	48	1			T40	1		T125	2		T114	1
auto[671088640:805306367]	auto[0]	44	1			T125	1		T6	1		T202	1
auto[671088640:805306367]	auto[1]	53	1			T1	1		T43	1		T26	1
auto[805306368:939524095]	auto[0]	47	1			T8	1		T82	1		T60	1
auto[805306368:939524095]	auto[1]	47	1			T41	1		T6	2		T183	1
auto[939524096:1073741823]	auto[0]	61	1			T16	1		T17	1		T24	1
auto[939524096:1073741823]	auto[1]	58	1			T44	1		T34	1		T184	2
auto[1073741824:1207959551]	auto[0]	55	1			T1	1		T52	1		T6	3
auto[1073741824:1207959551]	auto[1]	40	1			T47	1		T263	1		T97	1
auto[1207959552:1342177279]	auto[0]	61	1			T4	1		T16	1		T6	1
auto[1207959552:1342177279]	auto[1]	58	1			T55	1		T47	2		T289	1
auto[1342177280:1476395007]	auto[0]	53	1			T15	1		T182	1		T6	3
auto[1342177280:1476395007]	auto[1]	58	1			T14	1		T44	2		T48	1
auto[1476395008:1610612735]	auto[0]	38	1			T14	1		T45	1		T101	1
auto[1476395008:1610612735]	auto[1]	56	1			T47	1		T139	1		T6	1
auto[1610612736:1744830463]	auto[0]	49	1			T14	2		T24	1		T37	1
auto[1610612736:1744830463]	auto[1]	52	1			T184	1		T66	1		T193	2
auto[1744830464:1879048191]	auto[0]	41	1			T182	1		T289	1		T57	2
auto[1744830464:1879048191]	auto[1]	56	1			T15	1		T184	1		T186	1
auto[1879048192:2013265919]	auto[0]	47	1			T51	1		T180	1		T23	1
auto[1879048192:2013265919]	auto[1]	62	1			T2	1		T189	1		T47	1
auto[2013265920:2147483647]	auto[0]	49	1			T4	2		T45	1		T60	1
auto[2013265920:2147483647]	auto[1]	49	1			T108	1		T185	1		T180	1
auto[2147483648:2281701375]	auto[0]	38	1			T4	1		T6	2		T202	1
auto[2147483648:2281701375]	auto[1]	55	1			T127	1		T47	1		T52	1
auto[2281701376:2415919103]	auto[0]	44	1			T4	1		T34	1		T40	1
auto[2281701376:2415919103]	auto[1]	43	1			T13	1		T41	1		T54	1
auto[2415919104:2550136831]	auto[0]	34	1			T238	1		T50	1		T234	1
auto[2415919104:2550136831]	auto[1]	44	1			T1	2		T2	1		T184	1
auto[2550136832:2684354559]	auto[0]	34	1			T43	1		T6	1		T238	1
auto[2550136832:2684354559]	auto[1]	42	1			T60	1		T6	1		T246	1
auto[2684354560:2818572287]	auto[0]	42	1			T16	1		T82	2		T6	1
auto[2684354560:2818572287]	auto[1]	45	1			T14	1		T52	1		T6	3
auto[2818572288:2952790015]	auto[0]	34	1			T242	1		T81	1		T293	1
auto[2818572288:2952790015]	auto[1]	53	1			T47	1		T6	1		T252	1
auto[2952790016:3087007743]	auto[0]	39	1			T21	1		T23	1		T183	1
auto[2952790016:3087007743]	auto[1]	48	1			T37	1		T47	1		T41	1
auto[3087007744:3221225471]	auto[0]	43	1			T108	1		T47	1		T417	1
auto[3087007744:3221225471]	auto[1]	46	1			T13	1		T182	1		T59	1
auto[3221225472:3355443199]	auto[0]	49	1			T182	1		T60	1		T108	1
auto[3221225472:3355443199]	auto[1]	50	1			T1	1		T4	1		T46	1
auto[3355443200:3489660927]	auto[0]	44	1			T4	2		T127	1		T47	1
auto[3355443200:3489660927]	auto[1]	47	1			T1	1		T13	1		T182	1
auto[3489660928:3623878655]	auto[0]	42	1			T184	1		T127	1		T6	2
auto[3489660928:3623878655]	auto[1]	52	1			T2	1		T4	1		T15	1
auto[3623878656:3758096383]	auto[0]	41	1			T16	1		T51	1		T200	1
auto[3623878656:3758096383]	auto[1]	39	1			T1	1		T2	1		T14	1
auto[3758096384:3892314111]	auto[0]	50	1			T1	1		T55	1		T186	1
auto[3758096384:3892314111]	auto[1]	58	1			T1	1		T14	1		T182	2
auto[3892314112:4026531839]	auto[0]	41	1			T182	1		T6	3		T181	2
auto[3892314112:4026531839]	auto[1]	64	1			T1	2		T82	1		T182	1
auto[4026531840:4160749567]	auto[0]	48	1			T16	1		T17	1		T257	1
auto[4026531840:4160749567]	auto[1]	54	1			T186	1		T41	1		T139	1
auto[4160749568:4294967295]	auto[0]	47	1			T4	2		T84	1		T127	1
auto[4160749568:4294967295]	auto[1]	48	1			T51	1		T47	1		T6	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1421

1

T1

3

T2

2

T4

10

auto[1]

1656

1

T1

9

T2

2

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T1	1		T2	1		T14	1
auto[134217728:268435455]	97	1			T13	1		T40	1		T54	1
auto[268435456:402653183]	96	1			T2	1		T4	1		T8	1
auto[402653184:536870911]	90	1			T4	2		T44	1		T17	1
auto[536870912:671088639]	111	1			T4	1		T45	1		T184	1
auto[671088640:805306367]	93	1			T1	1		T4	1		T14	1
auto[805306368:939524095]	106	1			T15	1		T82	1		T45	1
auto[939524096:1073741823]	104	1			T196	1		T185	1		T41	1
auto[1073741824:1207959551]	87	1			T184	1		T182	1		T108	1
auto[1207959552:1342177279]	105	1			T43	1		T40	1		T51	1
auto[1342177280:1476395007]	94	1			T4	1		T13	1		T14	1
auto[1476395008:1610612735]	73	1			T2	1		T4	1		T14	1
auto[1610612736:1744830463]	93	1			T17	1		T182	1		T6	2
auto[1744830464:1879048191]	107	1			T16	1		T47	1		T21	1
auto[1879048192:2013265919]	103	1			T14	1		T16	1		T47	1
auto[2013265920:2147483647]	93	1			T1	1		T44	1		T60	1
auto[2147483648:2281701375]	91	1			T1	1		T60	1		T127	1
auto[2281701376:2415919103]	110	1			T44	1		T182	2		T189	1
auto[2415919104:2550136831]	81	1			T4	1		T82	1		T184	1
auto[2550136832:2684354559]	86	1			T1	1		T4	1		T34	1
auto[2684354560:2818572287]	102	1			T1	1		T43	1		T186	1
auto[2818572288:2952790015]	97	1			T1	1		T184	1		T125	1
auto[2952790016:3087007743]	111	1			T1	1		T84	1		T82	1
auto[3087007744:3221225471]	98	1			T1	1		T2	1		T4	1
auto[3221225472:3355443199]	92	1			T4	1		T43	1		T76	1
auto[3355443200:3489660927]	100	1			T184	1		T47	2		T28	1
auto[3489660928:3623878655]	98	1			T1	1		T13	1		T184	1
auto[3623878656:3758096383]	88	1			T1	1		T14	1		T60	1
auto[3758096384:3892314111]	83	1			T8	1		T15	1		T16	1
auto[3892314112:4026531839]	93	1			T16	1		T108	1		T127	1
auto[4026531840:4160749567]	100	1			T1	1		T4	1		T186	1
auto[4160749568:4294967295]	98	1			T16	1		T182	1		T47	1