Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2677

1

T1

12

T2

4

T4

8

auto[1]

328

1

T108

8

T125

8

T139

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	86	1			T1	1		T14	1		T82	1
auto[134217728:268435455]	95	1			T60	1		T40	1		T47	2
auto[268435456:402653183]	84	1			T2	1		T125	1		T6	1
auto[402653184:536870911]	102	1			T139	1		T6	2		T57	1
auto[536870912:671088639]	88	1			T1	1		T4	1		T16	1
auto[671088640:805306367]	86	1			T48	1		T186	1		T47	1
auto[805306368:939524095]	99	1			T13	1		T37	1		T125	1
auto[939524096:1073741823]	96	1			T1	2		T4	1		T14	1
auto[1073741824:1207959551]	87	1			T2	1		T44	1		T34	1
auto[1207959552:1342177279]	89	1			T13	1		T14	1		T182	1
auto[1342177280:1476395007]	86	1			T184	2		T26	1		T59	1
auto[1476395008:1610612735]	107	1			T4	1		T15	1		T55	1
auto[1610612736:1744830463]	99	1			T108	2		T125	2		T127	1
auto[1744830464:1879048191]	77	1			T1	1		T45	1		T184	1
auto[1879048192:2013265919]	91	1			T14	1		T189	1		T6	2
auto[2013265920:2147483647]	109	1			T14	1		T43	1		T82	1
auto[2147483648:2281701375]	89	1			T4	1		T15	1		T44	1
auto[2281701376:2415919103]	109	1			T1	1		T2	1		T14	1
auto[2415919104:2550136831]	103	1			T1	1		T4	1		T108	1
auto[2550136832:2684354559]	112	1			T1	1		T16	1		T43	1
auto[2684354560:2818572287]	94	1			T196	1		T185	1		T21	2
auto[2818572288:2952790015]	99	1			T1	1		T82	1		T182	1
auto[2952790016:3087007743]	89	1			T8	1		T182	3		T108	1
auto[3087007744:3221225471]	96	1			T14	1		T16	2		T43	1
auto[3221225472:3355443199]	93	1			T4	1		T108	1		T289	1
auto[3355443200:3489660927]	93	1			T1	1		T45	1		T127	1
auto[3489660928:3623878655]	87	1			T1	1		T82	1		T37	2
auto[3623878656:3758096383]	86	1			T13	1		T16	1		T17	1
auto[3758096384:3892314111]	83	1			T1	1		T34	1		T108	1
auto[3892314112:4026531839]	110	1			T4	1		T16	1		T127	1
auto[4026531840:4160749567]	89	1			T37	1		T127	1		T6	2
auto[4160749568:4294967295]	92	1			T2	1		T4	1		T84	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	78	1			T1	1		T14	1		T82	1
auto[0:134217727]	auto[1]	8	1			T81	1		T236	1		T346	1
auto[134217728:268435455]	auto[0]	89	1			T60	1		T40	1		T47	2
auto[134217728:268435455]	auto[1]	6	1			T139	2		T373	1		T258	1
auto[268435456:402653183]	auto[0]	73	1			T2	1		T125	1		T6	1
auto[268435456:402653183]	auto[1]	11	1			T190	1		T81	1		T232	1
auto[402653184:536870911]	auto[0]	85	1			T139	1		T6	2		T57	1
auto[402653184:536870911]	auto[1]	17	1			T355	1		T81	1		T233	1
auto[536870912:671088639]	auto[0]	83	1			T1	1		T4	1		T16	1
auto[536870912:671088639]	auto[1]	5	1			T174	1		T373	1		T423	1
auto[671088640:805306367]	auto[0]	78	1			T48	1		T186	1		T47	1
auto[671088640:805306367]	auto[1]	8	1			T190	1		T245	1		T423	2
auto[805306368:939524095]	auto[0]	83	1			T13	1		T37	1		T51	1
auto[805306368:939524095]	auto[1]	16	1			T125	1		T190	1		T236	2
auto[939524096:1073741823]	auto[0]	89	1			T1	2		T4	1		T14	1
auto[939524096:1073741823]	auto[1]	7	1			T108	1		T229	1		T381	1
auto[1073741824:1207959551]	auto[0]	80	1			T2	1		T44	1		T34	1
auto[1073741824:1207959551]	auto[1]	7	1			T108	2		T435	2		T381	1
auto[1207959552:1342177279]	auto[0]	78	1			T13	1		T14	1		T182	1
auto[1207959552:1342177279]	auto[1]	11	1			T139	1		T355	1		T233	1
auto[1342177280:1476395007]	auto[0]	73	1			T184	2		T26	1		T59	1
auto[1342177280:1476395007]	auto[1]	13	1			T302	1		T423	1		T258	1
auto[1476395008:1610612735]	auto[0]	96	1			T4	1		T15	1		T55	1
auto[1476395008:1610612735]	auto[1]	11	1			T355	1		T81	1		T232	1
auto[1610612736:1744830463]	auto[0]	91	1			T108	2		T125	1		T127	1
auto[1610612736:1744830463]	auto[1]	8	1			T125	1		T298	1		T241	1
auto[1744830464:1879048191]	auto[0]	67	1			T1	1		T45	1		T184	1
auto[1744830464:1879048191]	auto[1]	10	1			T108	2		T232	1		T236	1
auto[1879048192:2013265919]	auto[0]	81	1			T14	1		T189	1		T6	2
auto[1879048192:2013265919]	auto[1]	10	1			T355	1		T232	1		T373	1
auto[2013265920:2147483647]	auto[0]	96	1			T14	1		T43	1		T82	1
auto[2013265920:2147483647]	auto[1]	13	1			T125	1		T139	1		T355	1
auto[2147483648:2281701375]	auto[0]	75	1			T4	1		T15	1		T44	1
auto[2147483648:2281701375]	auto[1]	14	1			T125	1		T174	1		T355	1
auto[2281701376:2415919103]	auto[0]	100	1			T1	1		T2	1		T14	1
auto[2281701376:2415919103]	auto[1]	9	1			T232	2		T423	1		T258	1
auto[2415919104:2550136831]	auto[0]	93	1			T1	1		T4	1		T47	1
auto[2415919104:2550136831]	auto[1]	10	1			T108	1		T174	1		T373	1
auto[2550136832:2684354559]	auto[0]	99	1			T1	1		T16	1		T43	1
auto[2550136832:2684354559]	auto[1]	13	1			T190	1		T355	1		T236	1
auto[2684354560:2818572287]	auto[0]	90	1			T196	1		T185	1		T21	2
auto[2684354560:2818572287]	auto[1]	4	1			T423	1		T280	1		T259	1
auto[2818572288:2952790015]	auto[0]	88	1			T1	1		T82	1		T182	1
auto[2818572288:2952790015]	auto[1]	11	1			T125	1		T298	1		T259	1
auto[2952790016:3087007743]	auto[0]	78	1			T8	1		T182	3		T125	1
auto[2952790016:3087007743]	auto[1]	11	1			T108	1		T125	1		T373	1
auto[3087007744:3221225471]	auto[0]	84	1			T14	1		T16	2		T43	1
auto[3087007744:3221225471]	auto[1]	12	1			T125	1		T232	1		T228	1
auto[3221225472:3355443199]	auto[0]	81	1			T4	1		T289	1		T139	2
auto[3221225472:3355443199]	auto[1]	12	1			T108	1		T174	1		T232	1
auto[3355443200:3489660927]	auto[0]	88	1			T1	1		T45	1		T127	1
auto[3355443200:3489660927]	auto[1]	5	1			T245	1		T229	1		T230	1
auto[3489660928:3623878655]	auto[0]	77	1			T1	1		T82	1		T37	2
auto[3489660928:3623878655]	auto[1]	10	1			T228	1		T259	1		T434	1
auto[3623878656:3758096383]	auto[0]	75	1			T13	1		T16	1		T17	1
auto[3623878656:3758096383]	auto[1]	11	1			T125	1		T232	1		T346	1
auto[3758096384:3892314111]	auto[0]	76	1			T1	1		T34	1		T108	1
auto[3758096384:3892314111]	auto[1]	7	1			T355	1		T233	1		T245	1
auto[3892314112:4026531839]	auto[0]	102	1			T4	1		T16	1		T127	1
auto[3892314112:4026531839]	auto[1]	8	1			T236	1		T373	2		T280	2
auto[4026531840:4160749567]	auto[0]	75	1			T37	1		T127	1		T6	2
auto[4026531840:4160749567]	auto[1]	14	1			T174	1		T81	1		T232	1
auto[4160749568:4294967295]	auto[0]	76	1			T2	1		T4	1		T84	1
auto[4160749568:4294967295]	auto[1]	16	1			T245	2		T228	1		T373	1