Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4167

1

T1

16

T4

20

T13

4

auto[1]

1992

1

T1

8

T2

8

T4

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	198	1			T1	2		T184	2		T182	4
auto[134217728:268435455]	164	1			T47	2		T6	4		T181	2
auto[268435456:402653183]	196	1			T1	2		T13	2		T14	2
auto[402653184:536870911]	176	1			T4	4		T14	2		T17	2
auto[536870912:671088639]	182	1			T44	2		T40	2		T6	2
auto[671088640:805306367]	200	1			T127	2		T47	2		T139	4
auto[805306368:939524095]	218	1			T2	2		T34	2		T182	2
auto[939524096:1073741823]	166	1			T1	2		T2	2		T186	2
auto[1073741824:1207959551]	215	1			T8	2		T16	2		T84	2
auto[1207959552:1342177279]	208	1			T1	2		T14	2		T16	4
auto[1342177280:1476395007]	192	1			T2	2		T13	2		T82	4
auto[1476395008:1610612735]	192	1			T4	2		T13	2		T184	2
auto[1610612736:1744830463]	150	1			T184	2		T182	2		T37	2
auto[1744830464:1879048191]	184	1			T4	2		T44	2		T55	2
auto[1879048192:2013265919]	206	1			T16	2		T182	4		T48	2
auto[2013265920:2147483647]	226	1			T1	2		T4	2		T14	2
auto[2147483648:2281701375]	180	1			T4	2		T34	2		T60	2
auto[2281701376:2415919103]	208	1			T14	2		T186	2		T54	2
auto[2415919104:2550136831]	224	1			T2	2		T4	2		T16	2
auto[2550136832:2684354559]	186	1			T1	2		T14	2		T82	2
auto[2684354560:2818572287]	194	1			T15	2		T44	2		T184	2
auto[2818572288:2952790015]	218	1			T1	2		T4	2		T184	2
auto[2952790016:3087007743]	170	1			T1	4		T8	2		T43	2
auto[3087007744:3221225471]	170	1			T1	2		T186	2		T47	2
auto[3221225472:3355443199]	174	1			T139	4		T6	4		T180	2
auto[3355443200:3489660927]	204	1			T108	2		T185	2		T47	4
auto[3489660928:3623878655]	172	1			T4	2		T43	2		T127	2
auto[3623878656:3758096383]	180	1			T1	2		T15	4		T52	2
auto[3758096384:3892314111]	192	1			T4	2		T14	2		T24	2
auto[3892314112:4026531839]	208	1			T4	4		T16	2		T181	2
auto[4026531840:4160749567]	190	1			T82	2		T47	2		T6	2
auto[4160749568:4294967295]	216	1			T1	2		T45	2		T189	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	128	1			T1	2		T184	2		T182	4
auto[0:134217727]	auto[1]	70	1			T60	2		T6	4		T50	2
auto[134217728:268435455]	auto[0]	112	1			T47	2		T6	2		T242	4
auto[134217728:268435455]	auto[1]	52	1			T6	2		T181	2		T114	2
auto[268435456:402653183]	auto[0]	96	1			T13	2		T14	2		T108	2
auto[268435456:402653183]	auto[1]	100	1			T1	2		T43	2		T82	2
auto[402653184:536870911]	auto[0]	128	1			T4	4		T14	2		T17	2
auto[402653184:536870911]	auto[1]	48	1			T200	2		T193	2		T89	2
auto[536870912:671088639]	auto[0]	122	1			T40	2		T6	2		T202	2
auto[536870912:671088639]	auto[1]	60	1			T44	2		T89	2		T70	2
auto[671088640:805306367]	auto[0]	140	1			T127	2		T47	2		T139	4
auto[671088640:805306367]	auto[1]	60	1			T246	2		T238	2		T61	2
auto[805306368:939524095]	auto[0]	150	1			T182	2		T108	2		T125	2
auto[805306368:939524095]	auto[1]	68	1			T2	2		T34	2		T6	4
auto[939524096:1073741823]	auto[0]	102	1			T186	2		T47	2		T41	2
auto[939524096:1073741823]	auto[1]	64	1			T1	2		T2	2		T51	2
auto[1073741824:1207959551]	auto[0]	149	1			T8	2		T16	2		T84	2
auto[1073741824:1207959551]	auto[1]	66	1			T41	2		T244	2		T249	2
auto[1207959552:1342177279]	auto[0]	142	1			T1	2		T14	2		T16	2
auto[1207959552:1342177279]	auto[1]	66	1			T16	2		T47	2		T101	2
auto[1342177280:1476395007]	auto[0]	132	1			T13	2		T82	2		T184	2
auto[1342177280:1476395007]	auto[1]	60	1			T2	2		T82	2		T60	2
auto[1476395008:1610612735]	auto[0]	122	1			T4	2		T184	2		T6	6
auto[1476395008:1610612735]	auto[1]	70	1			T13	2		T40	2		T127	2
auto[1610612736:1744830463]	auto[0]	112	1			T184	2		T182	2		T37	2
auto[1610612736:1744830463]	auto[1]	38	1			T35	2		T232	2		T293	2
auto[1744830464:1879048191]	auto[0]	118	1			T55	2		T47	2		T6	6
auto[1744830464:1879048191]	auto[1]	66	1			T4	2		T44	2		T6	2
auto[1879048192:2013265919]	auto[0]	140	1			T16	2		T182	4		T48	2
auto[1879048192:2013265919]	auto[1]	66	1			T37	2		T181	2		T201	2
auto[2013265920:2147483647]	auto[0]	140	1			T1	2		T4	2		T14	2
auto[2013265920:2147483647]	auto[1]	86	1			T6	4		T181	2		T114	2
auto[2147483648:2281701375]	auto[0]	118	1			T125	2		T47	2		T6	4
auto[2147483648:2281701375]	auto[1]	62	1			T4	2		T34	2		T60	2
auto[2281701376:2415919103]	auto[0]	150	1			T14	2		T186	2		T6	4
auto[2281701376:2415919103]	auto[1]	58	1			T54	2		T139	2		T239	2
auto[2415919104:2550136831]	auto[0]	148	1			T4	2		T127	2		T47	2
auto[2415919104:2550136831]	auto[1]	76	1			T2	2		T16	2		T182	2
auto[2550136832:2684354559]	auto[0]	130	1			T14	2		T127	2		T180	4
auto[2550136832:2684354559]	auto[1]	56	1			T1	2		T82	2		T185	2
auto[2684354560:2818572287]	auto[0]	132	1			T184	2		T182	2		T41	2
auto[2684354560:2818572287]	auto[1]	62	1			T15	2		T44	2		T24	2
auto[2818572288:2952790015]	auto[0]	150	1			T1	2		T4	2		T184	2
auto[2818572288:2952790015]	auto[1]	68	1			T55	2		T308	2		T61	2
auto[2952790016:3087007743]	auto[0]	90	1			T1	2		T184	2		T50	2
auto[2952790016:3087007743]	auto[1]	80	1			T1	2		T8	2		T43	2
auto[3087007744:3221225471]	auto[0]	124	1			T1	2		T186	2		T47	2
auto[3087007744:3221225471]	auto[1]	46	1			T67	2		T35	2		T237	2
auto[3221225472:3355443199]	auto[0]	122	1			T139	4		T6	2		T180	2
auto[3221225472:3355443199]	auto[1]	52	1			T6	2		T25	2		T35	2
auto[3355443200:3489660927]	auto[0]	138	1			T47	2		T28	2		T6	2
auto[3355443200:3489660927]	auto[1]	66	1			T108	2		T185	2		T47	2
auto[3489660928:3623878655]	auto[0]	132	1			T4	2		T43	2		T127	2
auto[3489660928:3623878655]	auto[1]	40	1			T47	2		T26	2		T321	2
auto[3623878656:3758096383]	auto[0]	126	1			T1	2		T52	2		T289	2
auto[3623878656:3758096383]	auto[1]	54	1			T15	4		T238	2		T195	2
auto[3758096384:3892314111]	auto[0]	146	1			T4	2		T14	2		T60	2
auto[3758096384:3892314111]	auto[1]	46	1			T24	2		T47	2		T234	2
auto[3892314112:4026531839]	auto[0]	136	1			T4	4		T16	2		T201	2
auto[3892314112:4026531839]	auto[1]	72	1			T181	2		T321	2		T294	2
auto[4026531840:4160749567]	auto[0]	128	1			T47	2		T6	2		T242	4
auto[4026531840:4160749567]	auto[1]	62	1			T82	2		T190	2		T66	2
auto[4160749568:4294967295]	auto[0]	164	1			T1	2		T196	2		T125	2
auto[4160749568:4294967295]	auto[1]	52	1			T45	2		T189	2		T239	2