Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.83 99.10 97.91 98.64 100.00 99.11 98.41 91.61


Total test records in report: 1068
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T1008 /workspace/coverage/default/36.keymgr_cfg_regwen.967756226 Feb 22 01:08:14 PM PST 24 Feb 22 01:09:18 PM PST 24 4627318800 ps
T1009 /workspace/coverage/default/11.keymgr_lc_disable.3188173075 Feb 22 01:06:18 PM PST 24 Feb 22 01:06:24 PM PST 24 1052448213 ps
T1010 /workspace/coverage/default/2.keymgr_sideload.3688200825 Feb 22 01:05:32 PM PST 24 Feb 22 01:05:35 PM PST 24 49456133 ps
T1011 /workspace/coverage/default/37.keymgr_sideload.1526819580 Feb 22 01:08:14 PM PST 24 Feb 22 01:08:19 PM PST 24 403557668 ps
T1012 /workspace/coverage/default/5.keymgr_cfg_regwen.841745475 Feb 22 01:05:49 PM PST 24 Feb 22 01:06:04 PM PST 24 2941998036 ps
T1013 /workspace/coverage/default/6.keymgr_alert_test.3912566106 Feb 22 01:06:09 PM PST 24 Feb 22 01:06:11 PM PST 24 29621174 ps
T382 /workspace/coverage/default/7.keymgr_hwsw_invalid_input.961965056 Feb 22 01:06:17 PM PST 24 Feb 22 01:06:25 PM PST 24 396363536 ps
T1014 /workspace/coverage/default/21.keymgr_sideload_kmac.2726453494 Feb 22 01:07:10 PM PST 24 Feb 22 01:07:19 PM PST 24 438565112 ps
T1015 /workspace/coverage/default/29.keymgr_sideload_kmac.2663469233 Feb 22 01:07:38 PM PST 24 Feb 22 01:07:42 PM PST 24 466112154 ps
T1016 /workspace/coverage/default/15.keymgr_sideload_aes.2943741613 Feb 22 01:06:51 PM PST 24 Feb 22 01:07:59 PM PST 24 2266866720 ps
T1017 /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3475290626 Feb 22 01:07:23 PM PST 24 Feb 22 01:07:31 PM PST 24 572137934 ps
T1018 /workspace/coverage/default/11.keymgr_custom_cm.2925012010 Feb 22 01:06:17 PM PST 24 Feb 22 01:06:22 PM PST 24 223314501 ps
T1019 /workspace/coverage/default/26.keymgr_stress_all.1724501265 Feb 22 01:07:39 PM PST 24 Feb 22 01:07:53 PM PST 24 304691197 ps
T1020 /workspace/coverage/default/17.keymgr_sideload_kmac.3515052945 Feb 22 01:07:00 PM PST 24 Feb 22 01:08:01 PM PST 24 3204680716 ps
T1021 /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.914873958 Feb 22 01:07:08 PM PST 24 Feb 22 01:07:11 PM PST 24 182741992 ps
T1022 /workspace/coverage/default/38.keymgr_random.736088007 Feb 22 01:08:17 PM PST 24 Feb 22 01:08:20 PM PST 24 545791069 ps
T344 /workspace/coverage/default/10.keymgr_cfg_regwen.2899480526 Feb 22 01:06:16 PM PST 24 Feb 22 01:06:21 PM PST 24 153577380 ps
T160 /workspace/coverage/default/35.keymgr_custom_cm.3082304171 Feb 22 01:08:17 PM PST 24 Feb 22 01:08:20 PM PST 24 114327962 ps
T1023 /workspace/coverage/default/9.keymgr_custom_cm.3818687435 Feb 22 01:06:20 PM PST 24 Feb 22 01:06:24 PM PST 24 351923946 ps
T335 /workspace/coverage/default/33.keymgr_kmac_rsp_err.2528618306 Feb 22 01:08:12 PM PST 24 Feb 22 01:08:17 PM PST 24 841504813 ps
T1024 /workspace/coverage/default/0.keymgr_lc_disable.2687930974 Feb 22 01:05:18 PM PST 24 Feb 22 01:05:21 PM PST 24 301667346 ps
T1025 /workspace/coverage/default/39.keymgr_sw_invalid_input.1172215007 Feb 22 01:08:20 PM PST 24 Feb 22 01:08:29 PM PST 24 1441742263 ps
T1026 /workspace/coverage/default/43.keymgr_cfg_regwen.1556144667 Feb 22 01:08:40 PM PST 24 Feb 22 01:08:45 PM PST 24 318194124 ps
T1027 /workspace/coverage/default/18.keymgr_sideload_protect.819713184 Feb 22 01:07:12 PM PST 24 Feb 22 01:07:17 PM PST 24 144914417 ps
T1028 /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3111726369 Feb 22 01:08:20 PM PST 24 Feb 22 01:10:07 PM PST 24 11051716098 ps
T1029 /workspace/coverage/default/28.keymgr_smoke.1856187549 Feb 22 01:07:38 PM PST 24 Feb 22 01:07:40 PM PST 24 92450409 ps
T1030 /workspace/coverage/default/27.keymgr_sideload_otbn.1369763099 Feb 22 01:07:43 PM PST 24 Feb 22 01:07:48 PM PST 24 255716285 ps
T1031 /workspace/coverage/default/9.keymgr_random.338492178 Feb 22 01:06:13 PM PST 24 Feb 22 01:06:19 PM PST 24 117925654 ps
T1032 /workspace/coverage/default/20.keymgr_direct_to_disabled.2881036001 Feb 22 01:07:12 PM PST 24 Feb 22 01:07:17 PM PST 24 1318590375 ps
T1033 /workspace/coverage/default/14.keymgr_lc_disable.4121499744 Feb 22 01:06:51 PM PST 24 Feb 22 01:06:58 PM PST 24 100916518 ps
T365 /workspace/coverage/default/39.keymgr_random.411276539 Feb 22 01:08:27 PM PST 24 Feb 22 01:08:32 PM PST 24 315483583 ps
T1034 /workspace/coverage/default/42.keymgr_random.2335425393 Feb 22 01:08:28 PM PST 24 Feb 22 01:08:37 PM PST 24 195146631 ps
T75 /workspace/coverage/default/11.keymgr_direct_to_disabled.3172153981 Feb 22 01:06:16 PM PST 24 Feb 22 01:06:21 PM PST 24 131684732 ps
T1035 /workspace/coverage/default/48.keymgr_random.508057327 Feb 22 01:09:01 PM PST 24 Feb 22 01:09:05 PM PST 24 203295870 ps
T1036 /workspace/coverage/default/2.keymgr_lc_disable.1003085190 Feb 22 01:05:36 PM PST 24 Feb 22 01:05:38 PM PST 24 87727549 ps
T1037 /workspace/coverage/default/7.keymgr_smoke.3254503181 Feb 22 01:06:05 PM PST 24 Feb 22 01:06:07 PM PST 24 60432235 ps
T1038 /workspace/coverage/default/31.keymgr_sideload_aes.3729033257 Feb 22 01:07:53 PM PST 24 Feb 22 01:08:01 PM PST 24 2766701255 ps
T1039 /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1895926348 Feb 22 01:05:56 PM PST 24 Feb 22 01:06:08 PM PST 24 1283057816 ps
T1040 /workspace/coverage/default/11.keymgr_alert_test.76727739 Feb 22 01:06:20 PM PST 24 Feb 22 01:06:22 PM PST 24 39788490 ps
T220 /workspace/coverage/default/12.keymgr_stress_all.1544384506 Feb 22 01:06:49 PM PST 24 Feb 22 01:07:32 PM PST 24 5355895878 ps
T1041 /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3923663235 Feb 22 01:07:50 PM PST 24 Feb 22 01:07:53 PM PST 24 88963472 ps
T1042 /workspace/coverage/default/39.keymgr_stress_all.1852804052 Feb 22 01:08:15 PM PST 24 Feb 22 01:09:09 PM PST 24 2244517220 ps
T1043 /workspace/coverage/default/12.keymgr_alert_test.2249121920 Feb 22 01:06:47 PM PST 24 Feb 22 01:06:49 PM PST 24 9186521 ps
T1044 /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3356358559 Feb 22 01:08:46 PM PST 24 Feb 22 01:08:55 PM PST 24 1159480056 ps
T1045 /workspace/coverage/default/31.keymgr_alert_test.2405517830 Feb 22 01:07:49 PM PST 24 Feb 22 01:07:50 PM PST 24 18376834 ps
T1046 /workspace/coverage/default/37.keymgr_hwsw_invalid_input.4218608398 Feb 22 01:08:22 PM PST 24 Feb 22 01:08:31 PM PST 24 1279654367 ps
T1047 /workspace/coverage/default/47.keymgr_direct_to_disabled.3464571950 Feb 22 01:09:01 PM PST 24 Feb 22 01:09:04 PM PST 24 61983649 ps
T1048 /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3819874176 Feb 22 01:06:16 PM PST 24 Feb 22 01:06:20 PM PST 24 262558000 ps
T1049 /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.166825161 Feb 22 01:07:09 PM PST 24 Feb 22 01:07:22 PM PST 24 520665047 ps
T1050 /workspace/coverage/default/10.keymgr_lc_disable.1564431795 Feb 22 01:06:20 PM PST 24 Feb 22 01:06:26 PM PST 24 226702617 ps
T1051 /workspace/coverage/default/44.keymgr_smoke.1328522558 Feb 22 01:08:40 PM PST 24 Feb 22 01:08:42 PM PST 24 129971094 ps
T1052 /workspace/coverage/default/48.keymgr_stress_all.2004116455 Feb 22 01:09:12 PM PST 24 Feb 22 01:09:36 PM PST 24 2295975727 ps
T1053 /workspace/coverage/default/35.keymgr_smoke.4029892242 Feb 22 01:08:14 PM PST 24 Feb 22 01:08:17 PM PST 24 78963442 ps
T1054 /workspace/coverage/default/46.keymgr_sideload_protect.2393023841 Feb 22 01:08:48 PM PST 24 Feb 22 01:08:52 PM PST 24 126650018 ps
T1055 /workspace/coverage/default/7.keymgr_custom_cm.941325360 Feb 22 01:06:00 PM PST 24 Feb 22 01:06:06 PM PST 24 207589872 ps
T1056 /workspace/coverage/default/45.keymgr_stress_all.2068848689 Feb 22 01:08:44 PM PST 24 Feb 22 01:11:04 PM PST 24 21890759585 ps
T1057 /workspace/coverage/default/14.keymgr_sideload_otbn.1344353429 Feb 22 01:06:53 PM PST 24 Feb 22 01:07:00 PM PST 24 208165165 ps
T1058 /workspace/coverage/default/8.keymgr_smoke.1778886111 Feb 22 01:06:04 PM PST 24 Feb 22 01:06:27 PM PST 24 1252305612 ps
T1059 /workspace/coverage/default/32.keymgr_sync_async_fault_cross.4176447329 Feb 22 01:07:54 PM PST 24 Feb 22 01:08:02 PM PST 24 3785062640 ps
T1060 /workspace/coverage/default/26.keymgr_sync_async_fault_cross.4221528098 Feb 22 01:07:39 PM PST 24 Feb 22 01:07:42 PM PST 24 49714395 ps
T1061 /workspace/coverage/default/14.keymgr_smoke.2362748800 Feb 22 01:06:51 PM PST 24 Feb 22 01:07:30 PM PST 24 8388911126 ps
T1062 /workspace/coverage/default/2.keymgr_direct_to_disabled.3402315887 Feb 22 01:05:31 PM PST 24 Feb 22 01:05:46 PM PST 24 1222447585 ps
T1063 /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3117310101 Feb 22 01:05:55 PM PST 24 Feb 22 01:05:58 PM PST 24 863238647 ps
T1064 /workspace/coverage/default/0.keymgr_sync_async_fault_cross.728127358 Feb 22 01:05:35 PM PST 24 Feb 22 01:05:39 PM PST 24 105710390 ps
T1065 /workspace/coverage/default/20.keymgr_sw_invalid_input.4118410418 Feb 22 01:07:08 PM PST 24 Feb 22 01:07:14 PM PST 24 1129881763 ps
T1066 /workspace/coverage/default/32.keymgr_alert_test.3520367539 Feb 22 01:07:50 PM PST 24 Feb 22 01:07:52 PM PST 24 98062374 ps
T1067 /workspace/coverage/default/2.keymgr_sideload_protect.487357799 Feb 22 01:05:34 PM PST 24 Feb 22 01:05:37 PM PST 24 224971515 ps
T1068 /workspace/coverage/default/20.keymgr_smoke.855991586 Feb 22 01:07:11 PM PST 24 Feb 22 01:07:13 PM PST 24 25243334 ps

Test location /workspace/coverage/default/35.keymgr_stress_all.2560076503
Short name T4
Test name
Test status
Simulation time 712684396 ps
CPU time 27.79 seconds
Started Feb 22 01:08:15 PM PST 24
Finished Feb 22 01:08:43 PM PST 24
Peak memory 220652 kb
Host smart-dbe67d22-886f-41ff-b41f-00c14ea6caf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560076503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2560076503
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.991104481
Short name T6
Test name
Test status
Simulation time 3206661072 ps
CPU time 49.59 seconds
Started Feb 22 01:08:26 PM PST 24
Finished Feb 22 01:09:16 PM PST 24
Peak memory 215088 kb
Host smart-cacf366c-47b2-41dc-b0a3-cdb4c7f8e865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991104481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.991104481
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2724998251
Short name T5
Test name
Test status
Simulation time 877726122 ps
CPU time 9.94 seconds
Started Feb 22 01:05:54 PM PST 24
Finished Feb 22 01:06:05 PM PST 24
Peak memory 237824 kb
Host smart-6c837b38-ba82-4c47-9452-4614db8ce980
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724998251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2724998251
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3406087838
Short name T114
Test name
Test status
Simulation time 490630992 ps
CPU time 4 seconds
Started Feb 22 01:08:24 PM PST 24
Finished Feb 22 01:08:29 PM PST 24
Peak memory 222600 kb
Host smart-0e3afbb9-c236-4e50-a754-b3bb9d0177df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406087838 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3406087838
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2807250693
Short name T61
Test name
Test status
Simulation time 17341993059 ps
CPU time 103.69 seconds
Started Feb 22 01:05:58 PM PST 24
Finished Feb 22 01:07:42 PM PST 24
Peak memory 216208 kb
Host smart-83456d16-5a4b-4f86-b613-6b972393a99f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807250693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2807250693
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3247111333
Short name T8
Test name
Test status
Simulation time 64303627 ps
CPU time 3.09 seconds
Started Feb 22 01:08:53 PM PST 24
Finished Feb 22 01:08:56 PM PST 24
Peak memory 208548 kb
Host smart-cd1a3346-cddb-4ac0-bfad-032c19a8606d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247111333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3247111333
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1209655741
Short name T183
Test name
Test status
Simulation time 1548761362 ps
CPU time 54.2 seconds
Started Feb 22 01:08:46 PM PST 24
Finished Feb 22 01:09:40 PM PST 24
Peak memory 222376 kb
Host smart-19e6daca-90c2-47f9-b42e-d120a962a057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209655741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1209655741
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3115912741
Short name T108
Test name
Test status
Simulation time 239678851 ps
CPU time 13.19 seconds
Started Feb 22 01:06:02 PM PST 24
Finished Feb 22 01:06:17 PM PST 24
Peak memory 215116 kb
Host smart-806e5805-3d0e-4e54-a5f5-bbad272bc017
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3115912741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3115912741
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1597148899
Short name T34
Test name
Test status
Simulation time 156073519 ps
CPU time 4.24 seconds
Started Feb 22 01:06:02 PM PST 24
Finished Feb 22 01:06:08 PM PST 24
Peak memory 207860 kb
Host smart-2a6c1558-b3a7-436d-bdb4-aa104e6054b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597148899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1597148899
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.75001428
Short name T105
Test name
Test status
Simulation time 695710803 ps
CPU time 3.96 seconds
Started Feb 22 12:55:26 PM PST 24
Finished Feb 22 12:55:30 PM PST 24
Peak memory 221896 kb
Host smart-4c0ab053-4c7c-4f24-a85d-8403b688dc07
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75001428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_shadow_reg_errors_with_csr_rw.75001428
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1675199321
Short name T23
Test name
Test status
Simulation time 2173611199 ps
CPU time 10.9 seconds
Started Feb 22 01:08:15 PM PST 24
Finished Feb 22 01:08:27 PM PST 24
Peak memory 222512 kb
Host smart-9a1446e0-60f8-4ab0-9a84-c4334cf3c435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675199321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1675199321
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.293366250
Short name T298
Test name
Test status
Simulation time 3362511004 ps
CPU time 43.14 seconds
Started Feb 22 01:08:46 PM PST 24
Finished Feb 22 01:09:29 PM PST 24
Peak memory 214820 kb
Host smart-e183b269-d8e2-434a-bedb-927e18c872ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=293366250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.293366250
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.4217598224
Short name T50
Test name
Test status
Simulation time 79555857431 ps
CPU time 475.78 seconds
Started Feb 22 01:06:19 PM PST 24
Finished Feb 22 01:14:15 PM PST 24
Peak memory 224088 kb
Host smart-cbad7c80-7c5f-411e-87c9-cc288b21dab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217598224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.4217598224
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2522397669
Short name T125
Test name
Test status
Simulation time 97911373 ps
CPU time 5.59 seconds
Started Feb 22 01:07:06 PM PST 24
Finished Feb 22 01:07:12 PM PST 24
Peak memory 214456 kb
Host smart-5520f7ea-f787-49f3-8a91-72a5a90a6ce3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2522397669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2522397669
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2570763453
Short name T13
Test name
Test status
Simulation time 309086505 ps
CPU time 5.28 seconds
Started Feb 22 01:07:28 PM PST 24
Finished Feb 22 01:07:34 PM PST 24
Peak memory 222628 kb
Host smart-46d826fe-cac6-45fc-9175-d781cd94bfa1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570763453 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2570763453
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2420158799
Short name T280
Test name
Test status
Simulation time 858897352 ps
CPU time 12.67 seconds
Started Feb 22 01:06:04 PM PST 24
Finished Feb 22 01:06:18 PM PST 24
Peak memory 214292 kb
Host smart-3e7255e6-8c28-4035-82cb-aada54135d49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2420158799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2420158799
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.425083633
Short name T47
Test name
Test status
Simulation time 2068357382 ps
CPU time 64.27 seconds
Started Feb 22 01:06:48 PM PST 24
Finished Feb 22 01:07:56 PM PST 24
Peak memory 222420 kb
Host smart-61cb02e9-2ca7-4198-bdbd-9ff8f6bd9a77
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425083633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.425083633
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.4046521874
Short name T232
Test name
Test status
Simulation time 445297801 ps
CPU time 23.09 seconds
Started Feb 22 01:08:18 PM PST 24
Finished Feb 22 01:08:41 PM PST 24
Peak memory 214216 kb
Host smart-7303c76b-1003-452d-8d8f-8a4fa52adb67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046521874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.4046521874
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2099614353
Short name T113
Test name
Test status
Simulation time 219099069 ps
CPU time 3.71 seconds
Started Feb 22 12:54:19 PM PST 24
Finished Feb 22 12:54:23 PM PST 24
Peak memory 213792 kb
Host smart-abdf15fc-f2ea-4d94-a95b-9f6567b671f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099614353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2099614353
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1507233240
Short name T69
Test name
Test status
Simulation time 674973539 ps
CPU time 23.17 seconds
Started Feb 22 01:07:52 PM PST 24
Finished Feb 22 01:08:16 PM PST 24
Peak memory 216708 kb
Host smart-2a77efb7-b60d-4d17-9fa5-8f78b69bf5a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507233240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1507233240
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2059342060
Short name T139
Test name
Test status
Simulation time 54054451 ps
CPU time 3.77 seconds
Started Feb 22 01:05:49 PM PST 24
Finished Feb 22 01:05:53 PM PST 24
Peak memory 214744 kb
Host smart-e328a9b8-eadd-47cd-92f0-b2bba76be0ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2059342060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2059342060
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3022162493
Short name T207
Test name
Test status
Simulation time 3205625243 ps
CPU time 31.53 seconds
Started Feb 22 01:08:22 PM PST 24
Finished Feb 22 01:08:54 PM PST 24
Peak memory 214696 kb
Host smart-fbc140a8-c053-4934-a992-c83117bbe215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022162493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3022162493
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3034667211
Short name T85
Test name
Test status
Simulation time 407600050 ps
CPU time 5.18 seconds
Started Feb 22 01:07:15 PM PST 24
Finished Feb 22 01:07:21 PM PST 24
Peak memory 214280 kb
Host smart-64cbfaf9-c312-411e-9a42-d9135878c010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034667211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3034667211
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.894330743
Short name T142
Test name
Test status
Simulation time 8570717333 ps
CPU time 15.34 seconds
Started Feb 22 12:55:26 PM PST 24
Finished Feb 22 12:55:41 PM PST 24
Peak memory 208860 kb
Host smart-bdd276bd-856d-4b6a-a9cf-f845a9961a64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894330743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
894330743
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1704293584
Short name T190
Test name
Test status
Simulation time 54699551 ps
CPU time 3.91 seconds
Started Feb 22 01:07:03 PM PST 24
Finished Feb 22 01:07:08 PM PST 24
Peak memory 214336 kb
Host smart-a2603088-8520-4976-b1e1-f2e90882a366
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1704293584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1704293584
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.43976041
Short name T27
Test name
Test status
Simulation time 355657673 ps
CPU time 3.18 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:32 PM PST 24
Peak memory 214324 kb
Host smart-f2f8637b-7d2f-4abc-8618-d3e5a1186db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43976041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.43976041
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.344627624
Short name T166
Test name
Test status
Simulation time 97961135 ps
CPU time 4.85 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:43 PM PST 24
Peak memory 222632 kb
Host smart-f4fc7889-567c-48b8-a31d-42495052b809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344627624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.344627624
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3546906935
Short name T423
Test name
Test status
Simulation time 1615433681 ps
CPU time 83.76 seconds
Started Feb 22 01:06:51 PM PST 24
Finished Feb 22 01:08:17 PM PST 24
Peak memory 214352 kb
Host smart-49593a3e-d653-4237-98b0-ece634577045
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3546906935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3546906935
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1862407097
Short name T248
Test name
Test status
Simulation time 86068467 ps
CPU time 5.39 seconds
Started Feb 22 01:08:39 PM PST 24
Finished Feb 22 01:08:45 PM PST 24
Peak memory 214168 kb
Host smart-2650c743-71cb-46f3-8fcf-408457f3313e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862407097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1862407097
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.264535743
Short name T1
Test name
Test status
Simulation time 545637544 ps
CPU time 13.19 seconds
Started Feb 22 01:08:17 PM PST 24
Finished Feb 22 01:08:30 PM PST 24
Peak memory 219752 kb
Host smart-a915c404-deb4-498f-83e0-515030d298d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264535743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.264535743
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2394582425
Short name T95
Test name
Test status
Simulation time 102211681 ps
CPU time 4.17 seconds
Started Feb 22 01:07:19 PM PST 24
Finished Feb 22 01:07:24 PM PST 24
Peak memory 214280 kb
Host smart-81e05ca1-41b5-4e99-9b4b-d101d4e94410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394582425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2394582425
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.668896680
Short name T468
Test name
Test status
Simulation time 55744756 ps
CPU time 1.59 seconds
Started Feb 22 12:55:51 PM PST 24
Finished Feb 22 12:55:53 PM PST 24
Peak memory 213584 kb
Host smart-361ba8ba-f66a-482b-96c8-53db746727a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668896680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.668896680
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3178497972
Short name T62
Test name
Test status
Simulation time 3839476797 ps
CPU time 34 seconds
Started Feb 22 01:06:17 PM PST 24
Finished Feb 22 01:06:53 PM PST 24
Peak memory 216480 kb
Host smart-89f14626-2610-4da7-8e41-17938a180875
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178497972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3178497972
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2552521161
Short name T81
Test name
Test status
Simulation time 146719769 ps
CPU time 7.75 seconds
Started Feb 22 01:07:11 PM PST 24
Finished Feb 22 01:07:19 PM PST 24
Peak memory 214280 kb
Host smart-55f10bb1-a284-4510-89e4-4d37f0f29ce5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2552521161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2552521161
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3971580150
Short name T440
Test name
Test status
Simulation time 10452150 ps
CPU time 0.88 seconds
Started Feb 22 01:07:10 PM PST 24
Finished Feb 22 01:07:12 PM PST 24
Peak memory 205868 kb
Host smart-134a4796-da39-4f50-86ab-2db4f9f3b402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971580150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3971580150
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1983367519
Short name T229
Test name
Test status
Simulation time 668042086 ps
CPU time 11.08 seconds
Started Feb 22 01:08:22 PM PST 24
Finished Feb 22 01:08:33 PM PST 24
Peak memory 214248 kb
Host smart-040c57b0-438d-44fe-8f9e-a0c4e65c2f4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1983367519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1983367519
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.4155702848
Short name T17
Test name
Test status
Simulation time 403452900 ps
CPU time 5.08 seconds
Started Feb 22 01:05:33 PM PST 24
Finished Feb 22 01:05:39 PM PST 24
Peak memory 214540 kb
Host smart-19eaaea6-a396-4bb5-9b04-df7654af4e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155702848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.4155702848
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2212063601
Short name T916
Test name
Test status
Simulation time 756565598 ps
CPU time 19.6 seconds
Started Feb 22 01:08:26 PM PST 24
Finished Feb 22 01:08:47 PM PST 24
Peak memory 222408 kb
Host smart-a53cf6e7-6528-4206-9bcb-698426ba5d2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212063601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2212063601
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2825400642
Short name T57
Test name
Test status
Simulation time 282043112 ps
CPU time 3.71 seconds
Started Feb 22 01:05:54 PM PST 24
Finished Feb 22 01:05:58 PM PST 24
Peak memory 208256 kb
Host smart-8e4c11e5-bd95-48ce-af3c-f82829217fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825400642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2825400642
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2864759256
Short name T218
Test name
Test status
Simulation time 2769168044 ps
CPU time 65.7 seconds
Started Feb 22 01:07:08 PM PST 24
Finished Feb 22 01:08:14 PM PST 24
Peak memory 216784 kb
Host smart-f876fc60-93c1-4999-bd91-bf0ce37f3822
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864759256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2864759256
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3400260867
Short name T236
Test name
Test status
Simulation time 1911566738 ps
CPU time 26.09 seconds
Started Feb 22 01:07:54 PM PST 24
Finished Feb 22 01:08:20 PM PST 24
Peak memory 214960 kb
Host smart-8f4935c0-58cf-4da3-8d43-f01785c42cac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3400260867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3400260867
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3033121113
Short name T202
Test name
Test status
Simulation time 13026850722 ps
CPU time 130.57 seconds
Started Feb 22 01:08:50 PM PST 24
Finished Feb 22 01:11:01 PM PST 24
Peak memory 217736 kb
Host smart-d67fbaac-7b63-4006-b89c-887045057cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033121113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3033121113
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1952598859
Short name T37
Test name
Test status
Simulation time 126101203 ps
CPU time 4.96 seconds
Started Feb 22 01:07:50 PM PST 24
Finished Feb 22 01:07:56 PM PST 24
Peak memory 222348 kb
Host smart-aafb897c-e653-4069-85d1-31d062e55e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952598859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1952598859
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3930180476
Short name T60
Test name
Test status
Simulation time 280845844 ps
CPU time 4.54 seconds
Started Feb 22 01:06:51 PM PST 24
Finished Feb 22 01:06:58 PM PST 24
Peak memory 218392 kb
Host smart-cb77d2b8-0a3e-4f99-bd9d-2eab88444a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930180476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3930180476
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2444697254
Short name T141
Test name
Test status
Simulation time 2537812443 ps
CPU time 78.24 seconds
Started Feb 22 12:55:12 PM PST 24
Finished Feb 22 12:56:30 PM PST 24
Peak memory 223260 kb
Host smart-5f603685-fbf0-40e7-8125-e7661fa0418d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444697254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2444697254
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2228610606
Short name T250
Test name
Test status
Simulation time 264209914 ps
CPU time 4.53 seconds
Started Feb 22 01:07:11 PM PST 24
Finished Feb 22 01:07:16 PM PST 24
Peak memory 214316 kb
Host smart-5c6afd7f-fff4-4607-b73c-fe31b6421d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228610606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2228610606
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2166882185
Short name T422
Test name
Test status
Simulation time 509844546 ps
CPU time 13.76 seconds
Started Feb 22 01:07:04 PM PST 24
Finished Feb 22 01:07:18 PM PST 24
Peak memory 214384 kb
Host smart-c25f38d2-1a43-421b-8fd7-b13e63f08256
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2166882185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2166882185
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3528668052
Short name T256
Test name
Test status
Simulation time 7701565543 ps
CPU time 57.19 seconds
Started Feb 22 01:08:38 PM PST 24
Finished Feb 22 01:09:35 PM PST 24
Peak memory 222516 kb
Host smart-41e91ddf-deaf-46f4-8df6-19ce3859d01d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528668052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3528668052
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1727967893
Short name T70
Test name
Test status
Simulation time 1077141872 ps
CPU time 27.51 seconds
Started Feb 22 01:06:01 PM PST 24
Finished Feb 22 01:06:30 PM PST 24
Peak memory 215592 kb
Host smart-726c47f2-4037-4108-a01b-eeceec364347
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727967893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1727967893
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.183091244
Short name T19
Test name
Test status
Simulation time 63378887 ps
CPU time 1.85 seconds
Started Feb 22 01:07:15 PM PST 24
Finished Feb 22 01:07:17 PM PST 24
Peak memory 214632 kb
Host smart-e10abc29-57d6-4d3d-865a-4f605c76da8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183091244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.183091244
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3082304171
Short name T160
Test name
Test status
Simulation time 114327962 ps
CPU time 2.86 seconds
Started Feb 22 01:08:17 PM PST 24
Finished Feb 22 01:08:20 PM PST 24
Peak memory 222584 kb
Host smart-7a02ba25-801e-4383-aa10-3eef807f8ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082304171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3082304171
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.4248529307
Short name T310
Test name
Test status
Simulation time 6835618638 ps
CPU time 206.24 seconds
Started Feb 22 01:05:43 PM PST 24
Finished Feb 22 01:09:09 PM PST 24
Peak memory 217832 kb
Host smart-494ec17d-3107-4f5d-a273-6b1622896b3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248529307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.4248529307
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.525184950
Short name T87
Test name
Test status
Simulation time 213776663 ps
CPU time 7.37 seconds
Started Feb 22 01:07:10 PM PST 24
Finished Feb 22 01:07:18 PM PST 24
Peak memory 214280 kb
Host smart-3e74d443-9787-4fab-a2e0-e08029e8ea8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525184950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.525184950
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.900551904
Short name T110
Test name
Test status
Simulation time 302152475 ps
CPU time 3 seconds
Started Feb 22 12:55:18 PM PST 24
Finished Feb 22 12:55:21 PM PST 24
Peak memory 213788 kb
Host smart-c5312903-8e69-4ffc-9947-521ac3a0e0e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900551904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.900551904
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.109099068
Short name T148
Test name
Test status
Simulation time 757139813 ps
CPU time 5.6 seconds
Started Feb 22 12:54:58 PM PST 24
Finished Feb 22 12:55:05 PM PST 24
Peak memory 213500 kb
Host smart-85430270-0c77-4266-ba5a-18194ed1fae3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109099068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
109099068
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.880381402
Short name T158
Test name
Test status
Simulation time 284312359 ps
CPU time 3.67 seconds
Started Feb 22 01:06:41 PM PST 24
Finished Feb 22 01:06:45 PM PST 24
Peak memory 217572 kb
Host smart-4f9454f3-0ab6-4b5d-bd1b-b43af807e4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880381402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.880381402
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.383784099
Short name T162
Test name
Test status
Simulation time 58013164 ps
CPU time 2.99 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:41 PM PST 24
Peak memory 216856 kb
Host smart-a72f35d1-8a27-4b59-b579-42115ff42bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=383784099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.383784099
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1599217202
Short name T161
Test name
Test status
Simulation time 386688505 ps
CPU time 4.72 seconds
Started Feb 22 01:08:14 PM PST 24
Finished Feb 22 01:08:19 PM PST 24
Peak memory 218064 kb
Host smart-3f5c1f64-8bae-49e8-a472-e439270d13d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599217202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1599217202
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1786145380
Short name T275
Test name
Test status
Simulation time 1191351049 ps
CPU time 3.46 seconds
Started Feb 22 01:07:00 PM PST 24
Finished Feb 22 01:07:05 PM PST 24
Peak memory 208760 kb
Host smart-9da45182-9a11-4efe-9d3f-b46094a0ba1e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786145380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1786145380
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.618131397
Short name T187
Test name
Test status
Simulation time 4235012055 ps
CPU time 32.12 seconds
Started Feb 22 01:07:11 PM PST 24
Finished Feb 22 01:07:44 PM PST 24
Peak memory 214232 kb
Host smart-cd9f8092-2675-49b3-ae91-8902e70c6e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618131397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.618131397
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.963171916
Short name T209
Test name
Test status
Simulation time 3413672534 ps
CPU time 49.67 seconds
Started Feb 22 01:07:06 PM PST 24
Finished Feb 22 01:07:56 PM PST 24
Peak memory 216968 kb
Host smart-602ae127-cba3-46b5-817b-0b546c486a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963171916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.963171916
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2528618306
Short name T335
Test name
Test status
Simulation time 841504813 ps
CPU time 3.86 seconds
Started Feb 22 01:08:12 PM PST 24
Finished Feb 22 01:08:17 PM PST 24
Peak memory 222364 kb
Host smart-6c7a2c23-d2f6-413c-b0ff-279542166348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528618306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2528618306
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1876029495
Short name T227
Test name
Test status
Simulation time 894598848 ps
CPU time 32.15 seconds
Started Feb 22 01:08:17 PM PST 24
Finished Feb 22 01:08:50 PM PST 24
Peak memory 222476 kb
Host smart-8425883b-0695-488e-8740-146969e25468
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876029495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1876029495
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3868288265
Short name T97
Test name
Test status
Simulation time 313743409 ps
CPU time 6.5 seconds
Started Feb 22 01:08:21 PM PST 24
Finished Feb 22 01:08:28 PM PST 24
Peak memory 218452 kb
Host smart-01443661-886d-4cf0-a8d1-20dd758f513f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868288265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3868288265
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1127850699
Short name T146
Test name
Test status
Simulation time 2784168413 ps
CPU time 24.23 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:32 PM PST 24
Peak memory 211316 kb
Host smart-4510f038-e449-4ff9-ad5a-29f9f7e337d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127850699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1127850699
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.4166719669
Short name T156
Test name
Test status
Simulation time 89442286 ps
CPU time 2.91 seconds
Started Feb 22 01:08:12 PM PST 24
Finished Feb 22 01:08:15 PM PST 24
Peak memory 209908 kb
Host smart-9de9cb6b-b353-46a4-87eb-3dfd37fc85c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166719669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.4166719669
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2188999559
Short name T165
Test name
Test status
Simulation time 135276199 ps
CPU time 4.65 seconds
Started Feb 22 01:08:48 PM PST 24
Finished Feb 22 01:08:53 PM PST 24
Peak memory 222668 kb
Host smart-95ed0450-ff77-4350-a782-635f6dd9356c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188999559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2188999559
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.4289368377
Short name T159
Test name
Test status
Simulation time 33328008 ps
CPU time 2.62 seconds
Started Feb 22 01:06:48 PM PST 24
Finished Feb 22 01:06:51 PM PST 24
Peak memory 216840 kb
Host smart-59bdb714-e21b-4c46-b02e-9ce432407d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289368377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.4289368377
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2777860814
Short name T163
Test name
Test status
Simulation time 89106512 ps
CPU time 2.75 seconds
Started Feb 22 01:09:05 PM PST 24
Finished Feb 22 01:09:09 PM PST 24
Peak memory 222688 kb
Host smart-7e850f30-cce1-4322-92f3-73f97467eb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777860814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2777860814
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2291400607
Short name T54
Test name
Test status
Simulation time 823867174 ps
CPU time 9.75 seconds
Started Feb 22 01:05:30 PM PST 24
Finished Feb 22 01:05:40 PM PST 24
Peak memory 220560 kb
Host smart-a1c80691-1c8d-47dd-822f-abd03af17815
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291400607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2291400607
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2899480526
Short name T344
Test name
Test status
Simulation time 153577380 ps
CPU time 3.23 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:06:21 PM PST 24
Peak memory 215308 kb
Host smart-c2ae622c-1e06-459b-bf1e-3fdb133c8c45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899480526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2899480526
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.452895348
Short name T378
Test name
Test status
Simulation time 227112033 ps
CPU time 4.16 seconds
Started Feb 22 01:06:53 PM PST 24
Finished Feb 22 01:06:58 PM PST 24
Peak memory 214220 kb
Host smart-eb05abce-5ae0-4406-b52d-0232b5070e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452895348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.452895348
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3847215334
Short name T379
Test name
Test status
Simulation time 13545556171 ps
CPU time 57.42 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:08:10 PM PST 24
Peak memory 226308 kb
Host smart-dd6740ab-3a58-4720-b0e5-a174a87b7394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847215334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3847215334
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1830483019
Short name T235
Test name
Test status
Simulation time 976708755 ps
CPU time 12.66 seconds
Started Feb 22 01:05:55 PM PST 24
Finished Feb 22 01:06:08 PM PST 24
Peak memory 215104 kb
Host smart-c4b4e173-f1ab-4621-91df-8fd59fb84119
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830483019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1830483019
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3741164956
Short name T195
Test name
Test status
Simulation time 171280693 ps
CPU time 5.78 seconds
Started Feb 22 01:07:08 PM PST 24
Finished Feb 22 01:07:14 PM PST 24
Peak memory 211044 kb
Host smart-26a57781-6776-47de-ac09-8ef5e26b275e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741164956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3741164956
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3683646530
Short name T188
Test name
Test status
Simulation time 1190170089 ps
CPU time 8.82 seconds
Started Feb 22 01:05:50 PM PST 24
Finished Feb 22 01:05:59 PM PST 24
Peak memory 214224 kb
Host smart-117159b8-ccfa-42ad-8912-426dfed87cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683646530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3683646530
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2204883401
Short name T373
Test name
Test status
Simulation time 655920012 ps
CPU time 28.25 seconds
Started Feb 22 01:08:27 PM PST 24
Finished Feb 22 01:08:57 PM PST 24
Peak memory 213648 kb
Host smart-e66c239f-4e23-4f1d-9fd8-dc9aa47c8835
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204883401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2204883401
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2415224739
Short name T73
Test name
Test status
Simulation time 3228514204 ps
CPU time 104.55 seconds
Started Feb 22 01:08:44 PM PST 24
Finished Feb 22 01:10:29 PM PST 24
Peak memory 222532 kb
Host smart-ef7f33d6-ee71-4e84-993d-d81f2f9b5d4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415224739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2415224739
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3246808236
Short name T307
Test name
Test status
Simulation time 302611060 ps
CPU time 6.11 seconds
Started Feb 22 01:08:47 PM PST 24
Finished Feb 22 01:08:54 PM PST 24
Peak memory 214248 kb
Host smart-f136ffd5-bdef-4266-ae3e-b02c582b255c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246808236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3246808236
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2591836916
Short name T268
Test name
Test status
Simulation time 416549429 ps
CPU time 3.57 seconds
Started Feb 22 01:06:02 PM PST 24
Finished Feb 22 01:06:08 PM PST 24
Peak memory 214328 kb
Host smart-701d3a85-2c94-41b5-9095-1f9d791572e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591836916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2591836916
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2632699260
Short name T143
Test name
Test status
Simulation time 603235010 ps
CPU time 5.13 seconds
Started Feb 22 12:55:47 PM PST 24
Finished Feb 22 12:55:52 PM PST 24
Peak memory 209012 kb
Host smart-d715cc1f-4b59-44c8-87d8-f99a7725f42d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632699260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2632699260
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1280902178
Short name T151
Test name
Test status
Simulation time 62921504 ps
CPU time 3.42 seconds
Started Feb 22 12:55:53 PM PST 24
Finished Feb 22 12:55:56 PM PST 24
Peak memory 209024 kb
Host smart-428f06aa-d44c-4c59-b5b2-dbad69acc7d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280902178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1280902178
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1939903227
Short name T147
Test name
Test status
Simulation time 1426884210 ps
CPU time 14.27 seconds
Started Feb 22 12:56:03 PM PST 24
Finished Feb 22 12:56:18 PM PST 24
Peak memory 208972 kb
Host smart-f0595c41-ae11-48fd-9d32-a00bc009a21c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939903227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1939903227
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2597557633
Short name T154
Test name
Test status
Simulation time 938504865 ps
CPU time 2.94 seconds
Started Feb 22 12:54:59 PM PST 24
Finished Feb 22 12:55:02 PM PST 24
Peak memory 208564 kb
Host smart-a9a6f58d-ac63-4178-b335-b08f9e69242c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597557633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2597557633
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3456437182
Short name T150
Test name
Test status
Simulation time 217209170 ps
CPU time 2.67 seconds
Started Feb 22 01:07:35 PM PST 24
Finished Feb 22 01:07:38 PM PST 24
Peak memory 210324 kb
Host smart-daac60da-a27b-4796-bd2f-b030a0c8eb1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456437182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3456437182
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3131911007
Short name T115
Test name
Test status
Simulation time 109648140 ps
CPU time 3.14 seconds
Started Feb 22 12:55:27 PM PST 24
Finished Feb 22 12:55:30 PM PST 24
Peak memory 208572 kb
Host smart-e1053061-d304-43dc-b8d1-9f3910eed1d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131911007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3131911007
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.4272968378
Short name T362
Test name
Test status
Simulation time 906399694 ps
CPU time 6.91 seconds
Started Feb 22 01:05:40 PM PST 24
Finished Feb 22 01:05:47 PM PST 24
Peak memory 208872 kb
Host smart-7153edf3-be07-4d23-8b9f-9ce623dd3fb2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272968378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.4272968378
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2804103380
Short name T7
Test name
Test status
Simulation time 333999300 ps
CPU time 6.29 seconds
Started Feb 22 01:05:33 PM PST 24
Finished Feb 22 01:05:40 PM PST 24
Peak memory 222620 kb
Host smart-ac337814-35c1-4e0b-b4bf-4baa41d0109b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804103380 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2804103380
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1373000968
Short name T317
Test name
Test status
Simulation time 322324050 ps
CPU time 4.82 seconds
Started Feb 22 01:06:14 PM PST 24
Finished Feb 22 01:06:20 PM PST 24
Peak memory 214288 kb
Host smart-0005ef68-85e6-450a-84c2-d688b2ee0852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373000968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1373000968
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1894682049
Short name T174
Test name
Test status
Simulation time 321373757 ps
CPU time 16.29 seconds
Started Feb 22 01:06:15 PM PST 24
Finished Feb 22 01:06:32 PM PST 24
Peak memory 222380 kb
Host smart-cfdc689b-1528-47c1-805a-24e4860fbe5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1894682049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1894682049
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.4125893580
Short name T984
Test name
Test status
Simulation time 318022000 ps
CPU time 8.07 seconds
Started Feb 22 01:06:19 PM PST 24
Finished Feb 22 01:06:28 PM PST 24
Peak memory 222540 kb
Host smart-c17a7bd1-da19-401c-983e-bdef7f9c9370
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125893580 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.4125893580
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.457361920
Short name T31
Test name
Test status
Simulation time 128352895 ps
CPU time 1.91 seconds
Started Feb 22 01:06:18 PM PST 24
Finished Feb 22 01:06:21 PM PST 24
Peak memory 209708 kb
Host smart-9ea8b77f-4e71-433b-b120-552dc8ec036a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457361920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.457361920
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2112768540
Short name T340
Test name
Test status
Simulation time 4218795257 ps
CPU time 50.18 seconds
Started Feb 22 01:06:53 PM PST 24
Finished Feb 22 01:07:44 PM PST 24
Peak memory 222636 kb
Host smart-6bce6bad-8c49-43de-bf70-c6f0bbaab1a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112768540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2112768540
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3144239381
Short name T674
Test name
Test status
Simulation time 22964795 ps
CPU time 1.74 seconds
Started Feb 22 01:06:50 PM PST 24
Finished Feb 22 01:06:55 PM PST 24
Peak memory 206872 kb
Host smart-71cc2593-78a6-4def-8adc-e75e5947bf6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144239381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3144239381
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_random.1101061576
Short name T260
Test name
Test status
Simulation time 33356356 ps
CPU time 2.77 seconds
Started Feb 22 01:07:01 PM PST 24
Finished Feb 22 01:07:04 PM PST 24
Peak memory 207720 kb
Host smart-c2bdedbb-0539-4a6e-a0ef-020737ceb81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101061576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1101061576
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2386872826
Short name T225
Test name
Test status
Simulation time 852499594 ps
CPU time 6.75 seconds
Started Feb 22 01:07:02 PM PST 24
Finished Feb 22 01:07:09 PM PST 24
Peak memory 222612 kb
Host smart-62356a2b-de28-4743-811a-769c02b9b8a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386872826 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2386872826
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2738269216
Short name T221
Test name
Test status
Simulation time 257721547 ps
CPU time 4.59 seconds
Started Feb 22 01:07:06 PM PST 24
Finished Feb 22 01:07:11 PM PST 24
Peak memory 209640 kb
Host smart-42b70a23-18a8-4c5e-9e04-1555ee2160e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738269216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2738269216
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.42258116
Short name T288
Test name
Test status
Simulation time 2333751009 ps
CPU time 23.94 seconds
Started Feb 22 01:07:43 PM PST 24
Finished Feb 22 01:08:09 PM PST 24
Peak memory 209156 kb
Host smart-988823c2-1894-431b-ac61-57847bb19567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42258116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.42258116
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2017191748
Short name T91
Test name
Test status
Simulation time 108793907 ps
CPU time 5.4 seconds
Started Feb 22 01:05:51 PM PST 24
Finished Feb 22 01:05:56 PM PST 24
Peak memory 222596 kb
Host smart-a289f836-2c87-4be3-8861-44dea6eaf1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017191748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2017191748
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1612059523
Short name T400
Test name
Test status
Simulation time 341596814 ps
CPU time 5.65 seconds
Started Feb 22 01:07:58 PM PST 24
Finished Feb 22 01:08:04 PM PST 24
Peak memory 214300 kb
Host smart-4d5df7f3-e483-408d-91f9-cf8b06dac4d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612059523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1612059523
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3350218150
Short name T384
Test name
Test status
Simulation time 203873815 ps
CPU time 3.79 seconds
Started Feb 22 01:08:13 PM PST 24
Finished Feb 22 01:08:18 PM PST 24
Peak memory 214224 kb
Host smart-521385d1-c755-4da8-868a-4e8966ad04c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3350218150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3350218150
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.4025292727
Short name T350
Test name
Test status
Simulation time 419882464 ps
CPU time 3.05 seconds
Started Feb 22 01:08:43 PM PST 24
Finished Feb 22 01:08:46 PM PST 24
Peak memory 214356 kb
Host smart-6a425b18-b54e-49b2-ab22-9d2dfb97994c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4025292727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.4025292727
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1389915456
Short name T377
Test name
Test status
Simulation time 257839564 ps
CPU time 4 seconds
Started Feb 22 01:08:46 PM PST 24
Finished Feb 22 01:08:50 PM PST 24
Peak memory 222420 kb
Host smart-1249cec3-258b-4af9-bf21-ef288b6cb324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389915456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1389915456
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1930922577
Short name T381
Test name
Test status
Simulation time 4101004906 ps
CPU time 21.87 seconds
Started Feb 22 01:09:06 PM PST 24
Finished Feb 22 01:09:29 PM PST 24
Peak memory 215848 kb
Host smart-cddc63da-f9ca-439e-8392-fc5c108be0d6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1930922577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1930922577
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3227005014
Short name T518
Test name
Test status
Simulation time 377226792 ps
CPU time 13.82 seconds
Started Feb 22 12:54:33 PM PST 24
Finished Feb 22 12:54:47 PM PST 24
Peak memory 205124 kb
Host smart-941eb16a-3815-4840-a713-f101ddd51901
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227005014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
227005014
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.807495327
Short name T512
Test name
Test status
Simulation time 905123680 ps
CPU time 15.08 seconds
Started Feb 22 12:54:36 PM PST 24
Finished Feb 22 12:54:51 PM PST 24
Peak memory 205252 kb
Host smart-deee61dd-f9f2-4dbe-bbaf-86deff90a2b8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807495327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.807495327
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.921681942
Short name T175
Test name
Test status
Simulation time 75781939 ps
CPU time 0.92 seconds
Started Feb 22 12:54:37 PM PST 24
Finished Feb 22 12:54:38 PM PST 24
Peak memory 205160 kb
Host smart-1f2babeb-9957-4601-bbae-782c5bbc9b13
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921681942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.921681942
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1615575442
Short name T176
Test name
Test status
Simulation time 147559682 ps
CPU time 1.46 seconds
Started Feb 22 12:54:39 PM PST 24
Finished Feb 22 12:54:41 PM PST 24
Peak memory 213652 kb
Host smart-2d51606f-7984-4011-8f04-13417ca08d2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615575442 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1615575442
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.4260571968
Short name T480
Test name
Test status
Simulation time 30729914 ps
CPU time 1.13 seconds
Started Feb 22 12:54:36 PM PST 24
Finished Feb 22 12:54:37 PM PST 24
Peak memory 205176 kb
Host smart-bf6a02d4-9502-46d1-b3f8-cd3d86a496eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260571968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.4260571968
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2846113760
Short name T475
Test name
Test status
Simulation time 13074631 ps
CPU time 0.73 seconds
Started Feb 22 12:54:19 PM PST 24
Finished Feb 22 12:54:20 PM PST 24
Peak memory 205156 kb
Host smart-6bf5e8fe-a4b3-44dc-bda6-d9839e39c532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846113760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2846113760
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1364332334
Short name T494
Test name
Test status
Simulation time 151406329 ps
CPU time 2.67 seconds
Started Feb 22 12:54:33 PM PST 24
Finished Feb 22 12:54:36 PM PST 24
Peak memory 205208 kb
Host smart-f8d97a88-5df9-4e43-9029-20009115f97a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364332334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1364332334
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1057363086
Short name T547
Test name
Test status
Simulation time 114984465 ps
CPU time 3.35 seconds
Started Feb 22 12:54:20 PM PST 24
Finished Feb 22 12:54:24 PM PST 24
Peak memory 213504 kb
Host smart-09cc4ab7-254c-4c8f-ae32-1e48aae7bf56
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057363086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1057363086
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.4194663866
Short name T107
Test name
Test status
Simulation time 1052545170 ps
CPU time 32.64 seconds
Started Feb 22 12:54:20 PM PST 24
Finished Feb 22 12:54:52 PM PST 24
Peak memory 213560 kb
Host smart-9ba54cfb-3bd7-43d0-b2cf-594814c534cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194663866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.4194663866
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3252435913
Short name T553
Test name
Test status
Simulation time 466548769 ps
CPU time 6.19 seconds
Started Feb 22 12:54:33 PM PST 24
Finished Feb 22 12:54:39 PM PST 24
Peak memory 205180 kb
Host smart-f9e0e545-ccc7-49f7-9e94-b1ea38c1583d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252435913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
252435913
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1962872579
Short name T485
Test name
Test status
Simulation time 36429675 ps
CPU time 0.88 seconds
Started Feb 22 12:54:34 PM PST 24
Finished Feb 22 12:54:35 PM PST 24
Peak memory 205112 kb
Host smart-5ec1567b-1d83-4670-b268-0e47eb377471
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962872579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
962872579
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3290013466
Short name T564
Test name
Test status
Simulation time 11364492 ps
CPU time 0.87 seconds
Started Feb 22 12:54:36 PM PST 24
Finished Feb 22 12:54:37 PM PST 24
Peak memory 205188 kb
Host smart-134c0e6d-5cc3-4992-8f4f-687c1415b960
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290013466 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3290013466
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.1201860126
Short name T532
Test name
Test status
Simulation time 18112221 ps
CPU time 1.27 seconds
Started Feb 22 12:54:32 PM PST 24
Finished Feb 22 12:54:33 PM PST 24
Peak memory 205240 kb
Host smart-91384b63-1674-4fb5-97eb-5152766aadea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201860126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.1201860126
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.411184182
Short name T562
Test name
Test status
Simulation time 12824044 ps
CPU time 0.73 seconds
Started Feb 22 12:54:38 PM PST 24
Finished Feb 22 12:54:39 PM PST 24
Peak memory 205168 kb
Host smart-77a8c6d5-b561-4a28-a8dc-1099c5df1d18
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411184182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.411184182
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.9324733
Short name T548
Test name
Test status
Simulation time 82261697 ps
CPU time 2.15 seconds
Started Feb 22 12:54:35 PM PST 24
Finished Feb 22 12:54:37 PM PST 24
Peak memory 213908 kb
Host smart-cbec5804-ce49-4d87-bb11-78057d50f1ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9324733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_r
eg_errors.9324733
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.139737255
Short name T530
Test name
Test status
Simulation time 49088539 ps
CPU time 1.74 seconds
Started Feb 22 12:54:34 PM PST 24
Finished Feb 22 12:54:36 PM PST 24
Peak memory 215664 kb
Host smart-d2384875-3f32-466c-ad44-ebab5baa033f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139737255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.139737255
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.648803950
Short name T463
Test name
Test status
Simulation time 39540389 ps
CPU time 1.46 seconds
Started Feb 22 12:55:28 PM PST 24
Finished Feb 22 12:55:29 PM PST 24
Peak memory 221736 kb
Host smart-c395d4a0-415b-47aa-b119-c48deb901b87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648803950 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.648803950
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1972649881
Short name T501
Test name
Test status
Simulation time 65439885 ps
CPU time 1.06 seconds
Started Feb 22 12:55:28 PM PST 24
Finished Feb 22 12:55:29 PM PST 24
Peak memory 205228 kb
Host smart-2e85ac32-0a3b-4862-ab4c-9ddfb04ce120
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972649881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1972649881
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1701865106
Short name T556
Test name
Test status
Simulation time 52916780 ps
CPU time 0.76 seconds
Started Feb 22 12:55:26 PM PST 24
Finished Feb 22 12:55:27 PM PST 24
Peak memory 205104 kb
Host smart-c99d0c3b-e86c-442c-ae20-a862e91e1976
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701865106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1701865106
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1847402610
Short name T471
Test name
Test status
Simulation time 124245815 ps
CPU time 2.4 seconds
Started Feb 22 12:55:25 PM PST 24
Finished Feb 22 12:55:27 PM PST 24
Peak memory 205296 kb
Host smart-64d00626-13b3-408a-8144-5dbd099d492e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847402610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1847402610
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.4070139761
Short name T140
Test name
Test status
Simulation time 32000456 ps
CPU time 2.03 seconds
Started Feb 22 12:55:26 PM PST 24
Finished Feb 22 12:55:28 PM PST 24
Peak memory 215808 kb
Host smart-6938e9d0-a82b-43c1-8d83-2e4f2d8fc016
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070139761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.4070139761
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.755667471
Short name T145
Test name
Test status
Simulation time 224499135 ps
CPU time 6.94 seconds
Started Feb 22 12:55:26 PM PST 24
Finished Feb 22 12:55:33 PM PST 24
Peak memory 213564 kb
Host smart-4f9bc13d-291c-4f01-ac0d-d67e63875649
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755667471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.755667471
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1098563389
Short name T533
Test name
Test status
Simulation time 30647400 ps
CPU time 1.08 seconds
Started Feb 22 12:55:32 PM PST 24
Finished Feb 22 12:55:33 PM PST 24
Peak memory 205352 kb
Host smart-5e0f72be-4f51-4d69-85b1-c50d8a24c9ce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098563389 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1098563389
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2199703359
Short name T517
Test name
Test status
Simulation time 25878663 ps
CPU time 1.06 seconds
Started Feb 22 12:55:26 PM PST 24
Finished Feb 22 12:55:27 PM PST 24
Peak memory 205108 kb
Host smart-1ef82bde-5a12-4c7b-b7ae-cc5f0e46559e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199703359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2199703359
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1859312080
Short name T541
Test name
Test status
Simulation time 30931958 ps
CPU time 0.78 seconds
Started Feb 22 12:55:26 PM PST 24
Finished Feb 22 12:55:27 PM PST 24
Peak memory 205164 kb
Host smart-edb018be-41ec-4eff-a0d5-aaf8191d1291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859312080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1859312080
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2609332861
Short name T499
Test name
Test status
Simulation time 78168717 ps
CPU time 1.56 seconds
Started Feb 22 12:55:25 PM PST 24
Finished Feb 22 12:55:27 PM PST 24
Peak memory 205260 kb
Host smart-933329b4-81e1-4594-a92d-1b80fff017f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609332861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2609332861
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1546533071
Short name T111
Test name
Test status
Simulation time 95938040 ps
CPU time 3.12 seconds
Started Feb 22 12:55:28 PM PST 24
Finished Feb 22 12:55:31 PM PST 24
Peak memory 213708 kb
Host smart-5f6b19b6-cfe3-41e4-a72b-ef85a6e014a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546533071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1546533071
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1387037747
Short name T566
Test name
Test status
Simulation time 1205309334 ps
CPU time 6.02 seconds
Started Feb 22 12:55:26 PM PST 24
Finished Feb 22 12:55:32 PM PST 24
Peak memory 213732 kb
Host smart-1de8e515-9649-4334-92a2-6c14e6f92ba3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387037747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1387037747
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.937533309
Short name T470
Test name
Test status
Simulation time 51121583 ps
CPU time 3.73 seconds
Started Feb 22 12:55:24 PM PST 24
Finished Feb 22 12:55:29 PM PST 24
Peak memory 213464 kb
Host smart-26c55d27-d509-46e6-bccb-38c147fb758a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937533309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.937533309
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2136327760
Short name T528
Test name
Test status
Simulation time 25093059 ps
CPU time 1.1 seconds
Started Feb 22 12:55:51 PM PST 24
Finished Feb 22 12:55:53 PM PST 24
Peak memory 205220 kb
Host smart-716b9bd5-5e9a-4fa6-9edc-f28e0f2c454b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136327760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2136327760
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.356425696
Short name T445
Test name
Test status
Simulation time 16361817 ps
CPU time 0.79 seconds
Started Feb 22 12:55:54 PM PST 24
Finished Feb 22 12:55:55 PM PST 24
Peak memory 205100 kb
Host smart-3ab1df54-e103-48b7-8611-1ec152b16a06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356425696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.356425696
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3221664824
Short name T473
Test name
Test status
Simulation time 105239183 ps
CPU time 2.38 seconds
Started Feb 22 12:55:52 PM PST 24
Finished Feb 22 12:55:55 PM PST 24
Peak memory 205268 kb
Host smart-4abb06e2-2559-4c87-b83f-2f4f44b9c475
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221664824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3221664824
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3183700709
Short name T486
Test name
Test status
Simulation time 660635473 ps
CPU time 3.97 seconds
Started Feb 22 12:55:55 PM PST 24
Finished Feb 22 12:55:59 PM PST 24
Peak memory 221932 kb
Host smart-fa325444-d5a0-41c1-aa1c-2bd66ede0db9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183700709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3183700709
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.4208939281
Short name T118
Test name
Test status
Simulation time 22509097 ps
CPU time 1.11 seconds
Started Feb 22 12:55:53 PM PST 24
Finished Feb 22 12:55:54 PM PST 24
Peak memory 205388 kb
Host smart-8e7aac23-9019-4321-b321-9c00e5dbe876
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208939281 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.4208939281
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3543621584
Short name T457
Test name
Test status
Simulation time 15274070 ps
CPU time 0.74 seconds
Started Feb 22 12:55:53 PM PST 24
Finished Feb 22 12:55:54 PM PST 24
Peak memory 205160 kb
Host smart-dd1cb1bc-3efd-4d62-85d2-766682b78d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543621584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3543621584
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2891883225
Short name T106
Test name
Test status
Simulation time 895070937 ps
CPU time 7.81 seconds
Started Feb 22 12:55:52 PM PST 24
Finished Feb 22 12:56:00 PM PST 24
Peak memory 213812 kb
Host smart-ef25dbe6-6ca9-4354-875a-65e8c0f97f3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891883225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2891883225
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3554583826
Short name T520
Test name
Test status
Simulation time 2312603329 ps
CPU time 8.41 seconds
Started Feb 22 12:55:51 PM PST 24
Finished Feb 22 12:56:00 PM PST 24
Peak memory 213800 kb
Host smart-428c1332-cea1-4c24-a268-b0a58af91bfb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554583826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3554583826
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.506209724
Short name T482
Test name
Test status
Simulation time 38681421 ps
CPU time 2.23 seconds
Started Feb 22 12:55:52 PM PST 24
Finished Feb 22 12:55:54 PM PST 24
Peak memory 215604 kb
Host smart-5d2b6358-3866-4192-a9b5-5a8c182bd6b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506209724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.506209724
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.575231406
Short name T149
Test name
Test status
Simulation time 116861653 ps
CPU time 4.95 seconds
Started Feb 22 12:55:49 PM PST 24
Finished Feb 22 12:55:55 PM PST 24
Peak memory 213644 kb
Host smart-9e1ba407-0fbc-45f3-80e2-f99f4749e59c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575231406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.575231406
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1241660595
Short name T120
Test name
Test status
Simulation time 57743868 ps
CPU time 1.39 seconds
Started Feb 22 12:55:50 PM PST 24
Finished Feb 22 12:55:51 PM PST 24
Peak memory 213656 kb
Host smart-8767fe98-6999-4fef-be7b-edea77ba8b96
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241660595 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1241660595
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1583461102
Short name T505
Test name
Test status
Simulation time 21592351 ps
CPU time 0.95 seconds
Started Feb 22 12:55:50 PM PST 24
Finished Feb 22 12:55:51 PM PST 24
Peak memory 205152 kb
Host smart-387e9c0b-31b4-4c33-9eff-ae4eb0964a4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583461102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1583461102
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3508683404
Short name T535
Test name
Test status
Simulation time 53352299 ps
CPU time 0.7 seconds
Started Feb 22 12:55:53 PM PST 24
Finished Feb 22 12:55:55 PM PST 24
Peak memory 205180 kb
Host smart-2ed0efdf-153f-426f-b9e0-6caae984da94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508683404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3508683404
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.381407163
Short name T170
Test name
Test status
Simulation time 218440333 ps
CPU time 2.33 seconds
Started Feb 22 12:55:57 PM PST 24
Finished Feb 22 12:55:59 PM PST 24
Peak memory 205184 kb
Host smart-9ab56ea5-a8bf-4c16-a61f-d75a59bb1665
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381407163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.381407163
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3271919162
Short name T469
Test name
Test status
Simulation time 99622740 ps
CPU time 2.76 seconds
Started Feb 22 12:55:52 PM PST 24
Finished Feb 22 12:55:55 PM PST 24
Peak memory 213996 kb
Host smart-c6a43282-a3f6-4e17-87ec-cd6a9a3bc824
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271919162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3271919162
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1843189838
Short name T507
Test name
Test status
Simulation time 112204735 ps
CPU time 4.77 seconds
Started Feb 22 12:55:51 PM PST 24
Finished Feb 22 12:55:56 PM PST 24
Peak memory 213704 kb
Host smart-7c595479-3f4b-4fb7-90f9-2790b9db6fe7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843189838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1843189838
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3750581410
Short name T567
Test name
Test status
Simulation time 102438391 ps
CPU time 1.63 seconds
Started Feb 22 12:55:50 PM PST 24
Finished Feb 22 12:55:52 PM PST 24
Peak memory 213436 kb
Host smart-38787db3-8869-467d-b204-83f1894b4020
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750581410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3750581410
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1525467344
Short name T171
Test name
Test status
Simulation time 76070101 ps
CPU time 0.99 seconds
Started Feb 22 12:56:04 PM PST 24
Finished Feb 22 12:56:05 PM PST 24
Peak memory 205220 kb
Host smart-a7a65c09-2244-4fcc-a2ab-fc8671e766f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525467344 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1525467344
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3732747925
Short name T490
Test name
Test status
Simulation time 100931927 ps
CPU time 1.01 seconds
Started Feb 22 12:56:04 PM PST 24
Finished Feb 22 12:56:05 PM PST 24
Peak memory 205184 kb
Host smart-dc4d0f76-ddfb-4102-b569-1c22ffc02ba1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732747925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3732747925
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2572008569
Short name T131
Test name
Test status
Simulation time 42623232 ps
CPU time 0.84 seconds
Started Feb 22 12:55:52 PM PST 24
Finished Feb 22 12:55:53 PM PST 24
Peak memory 205132 kb
Host smart-ea8a3ef8-72a8-4ebc-9e3c-ae6d20097ef6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572008569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2572008569
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3591906916
Short name T455
Test name
Test status
Simulation time 83027921 ps
CPU time 2.49 seconds
Started Feb 22 12:56:02 PM PST 24
Finished Feb 22 12:56:05 PM PST 24
Peak memory 205256 kb
Host smart-ee83bffb-dc4f-4ea8-9da6-e451ec83b885
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591906916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3591906916
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1686341736
Short name T500
Test name
Test status
Simulation time 101630086 ps
CPU time 2.5 seconds
Started Feb 22 12:55:51 PM PST 24
Finished Feb 22 12:55:54 PM PST 24
Peak memory 213716 kb
Host smart-4e3288f4-1d72-4675-8169-dc47ad8bc714
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686341736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1686341736
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.385042037
Short name T514
Test name
Test status
Simulation time 106052093 ps
CPU time 1.96 seconds
Started Feb 22 12:55:52 PM PST 24
Finished Feb 22 12:55:55 PM PST 24
Peak memory 213548 kb
Host smart-702e7f4e-fe77-427f-829b-0b6e7f615768
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385042037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.385042037
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1804812613
Short name T396
Test name
Test status
Simulation time 192523085 ps
CPU time 5.14 seconds
Started Feb 22 12:55:54 PM PST 24
Finished Feb 22 12:56:00 PM PST 24
Peak memory 208512 kb
Host smart-c306ccb8-547f-4c1a-b2cc-48e7cc0eb7ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804812613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1804812613
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2907603112
Short name T483
Test name
Test status
Simulation time 23154833 ps
CPU time 1.74 seconds
Started Feb 22 12:56:06 PM PST 24
Finished Feb 22 12:56:08 PM PST 24
Peak memory 213512 kb
Host smart-c1a449bb-5eec-446d-b4dc-1dd83d3e54c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907603112 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2907603112
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2813759641
Short name T542
Test name
Test status
Simulation time 318517159 ps
CPU time 1.02 seconds
Started Feb 22 12:56:09 PM PST 24
Finished Feb 22 12:56:10 PM PST 24
Peak memory 205152 kb
Host smart-4212779a-6737-4f3f-9b07-8da16fde1edb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813759641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2813759641
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1210268945
Short name T178
Test name
Test status
Simulation time 10284099 ps
CPU time 0.79 seconds
Started Feb 22 12:56:02 PM PST 24
Finished Feb 22 12:56:03 PM PST 24
Peak memory 205316 kb
Host smart-8443c0c8-fc0c-4981-8152-8e1a3421b143
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210268945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1210268945
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3600178897
Short name T130
Test name
Test status
Simulation time 50067359 ps
CPU time 1.44 seconds
Started Feb 22 12:56:03 PM PST 24
Finished Feb 22 12:56:05 PM PST 24
Peak memory 205364 kb
Host smart-989dd070-3491-4a21-a2f6-ad85dfe6fa3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600178897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3600178897
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.4245538796
Short name T565
Test name
Test status
Simulation time 1384128135 ps
CPU time 8.12 seconds
Started Feb 22 12:56:05 PM PST 24
Finished Feb 22 12:56:14 PM PST 24
Peak memory 213808 kb
Host smart-ef749ba7-04f1-4bb9-9431-4ceaa8a7e9d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245538796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.4245538796
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1091860677
Short name T503
Test name
Test status
Simulation time 1605514947 ps
CPU time 15.11 seconds
Started Feb 22 12:56:03 PM PST 24
Finished Feb 22 12:56:18 PM PST 24
Peak memory 213636 kb
Host smart-d55a7f30-24a3-41a2-bb0d-29ceea8d2873
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091860677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1091860677
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1862025076
Short name T545
Test name
Test status
Simulation time 121501262 ps
CPU time 1.98 seconds
Started Feb 22 12:56:04 PM PST 24
Finished Feb 22 12:56:06 PM PST 24
Peak memory 213476 kb
Host smart-bfb08a7e-23d7-4e74-8cce-2fa4f04325f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862025076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1862025076
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2063658432
Short name T121
Test name
Test status
Simulation time 462041544 ps
CPU time 8.13 seconds
Started Feb 22 12:56:03 PM PST 24
Finished Feb 22 12:56:12 PM PST 24
Peak memory 208724 kb
Host smart-747bea26-b765-4151-ba68-ba3a5adc8737
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063658432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2063658432
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2749295159
Short name T523
Test name
Test status
Simulation time 14301279 ps
CPU time 0.95 seconds
Started Feb 22 12:56:04 PM PST 24
Finished Feb 22 12:56:05 PM PST 24
Peak memory 205192 kb
Host smart-781e1946-ab64-44ba-828b-1efcbf43c82d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749295159 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2749295159
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2371550016
Short name T508
Test name
Test status
Simulation time 35073933 ps
CPU time 1.27 seconds
Started Feb 22 12:56:09 PM PST 24
Finished Feb 22 12:56:11 PM PST 24
Peak memory 205240 kb
Host smart-30caf385-e464-44bc-87ef-1ed75d5fe7d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371550016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2371550016
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.316743630
Short name T479
Test name
Test status
Simulation time 21056003 ps
CPU time 0.82 seconds
Started Feb 22 12:56:05 PM PST 24
Finished Feb 22 12:56:06 PM PST 24
Peak memory 205036 kb
Host smart-bac1ac1c-cfb7-477e-9485-8c14dc2c5203
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316743630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.316743630
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1371642343
Short name T527
Test name
Test status
Simulation time 306754432 ps
CPU time 3.23 seconds
Started Feb 22 12:56:04 PM PST 24
Finished Feb 22 12:56:07 PM PST 24
Peak memory 213812 kb
Host smart-59fd13e3-7329-4bee-8505-6190eacf5ac2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371642343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1371642343
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2278020182
Short name T559
Test name
Test status
Simulation time 4531983975 ps
CPU time 10.93 seconds
Started Feb 22 12:56:05 PM PST 24
Finished Feb 22 12:56:16 PM PST 24
Peak memory 213680 kb
Host smart-5b145768-a737-43f2-b5f9-4f959db96db0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278020182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2278020182
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1116243714
Short name T561
Test name
Test status
Simulation time 399890555 ps
CPU time 2.02 seconds
Started Feb 22 12:56:05 PM PST 24
Finished Feb 22 12:56:07 PM PST 24
Peak memory 213656 kb
Host smart-152353c1-fd8a-46bb-8fd6-77785aa434e9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116243714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1116243714
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2139947275
Short name T557
Test name
Test status
Simulation time 20820759 ps
CPU time 1.47 seconds
Started Feb 22 12:56:05 PM PST 24
Finished Feb 22 12:56:07 PM PST 24
Peak memory 217664 kb
Host smart-05c80892-d656-4e72-957a-1daef7ed2e60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139947275 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2139947275
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1473112971
Short name T133
Test name
Test status
Simulation time 43469554 ps
CPU time 1.17 seconds
Started Feb 22 12:56:06 PM PST 24
Finished Feb 22 12:56:07 PM PST 24
Peak memory 205252 kb
Host smart-2870de8d-9077-4cd7-aa7d-70e58f9d7537
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473112971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1473112971
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2733230023
Short name T488
Test name
Test status
Simulation time 43021484 ps
CPU time 0.73 seconds
Started Feb 22 12:56:04 PM PST 24
Finished Feb 22 12:56:05 PM PST 24
Peak memory 205152 kb
Host smart-eb304f70-a148-4c12-b17f-f988b7aeecff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733230023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2733230023
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.835033046
Short name T477
Test name
Test status
Simulation time 47435173 ps
CPU time 1.65 seconds
Started Feb 22 12:56:06 PM PST 24
Finished Feb 22 12:56:08 PM PST 24
Peak memory 205316 kb
Host smart-516f6f7e-8a14-46ef-853c-23ea23c9adac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835033046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.835033046
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4257390278
Short name T502
Test name
Test status
Simulation time 185101183 ps
CPU time 3.44 seconds
Started Feb 22 12:56:05 PM PST 24
Finished Feb 22 12:56:09 PM PST 24
Peak memory 213736 kb
Host smart-1fa7083d-369a-40ef-b951-9cd6e52464a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257390278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.4257390278
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2052335463
Short name T112
Test name
Test status
Simulation time 302154527 ps
CPU time 9.46 seconds
Started Feb 22 12:56:02 PM PST 24
Finished Feb 22 12:56:12 PM PST 24
Peak memory 213828 kb
Host smart-d9062c93-9476-4b48-8649-c4ca5bce0f0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052335463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2052335463
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2212602456
Short name T119
Test name
Test status
Simulation time 618055257 ps
CPU time 4.44 seconds
Started Feb 22 12:56:04 PM PST 24
Finished Feb 22 12:56:08 PM PST 24
Peak memory 213576 kb
Host smart-dd31ae95-7b56-4103-8cfd-5b2629715523
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212602456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2212602456
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.65612580
Short name T552
Test name
Test status
Simulation time 313656179 ps
CPU time 7.53 seconds
Started Feb 22 12:56:02 PM PST 24
Finished Feb 22 12:56:10 PM PST 24
Peak memory 213596 kb
Host smart-5fb20127-427b-4816-870a-30959fd1b5ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65612580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.65612580
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.574511216
Short name T167
Test name
Test status
Simulation time 264036224 ps
CPU time 1.66 seconds
Started Feb 22 12:56:07 PM PST 24
Finished Feb 22 12:56:09 PM PST 24
Peak memory 213652 kb
Host smart-bf42146d-358e-42d4-bd7d-37ffbb7685da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574511216 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.574511216
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.710246864
Short name T476
Test name
Test status
Simulation time 13763307 ps
CPU time 0.87 seconds
Started Feb 22 12:56:04 PM PST 24
Finished Feb 22 12:56:05 PM PST 24
Peak memory 205056 kb
Host smart-60b4c592-d9f5-4d20-8315-c6584706d259
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710246864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.710246864
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.735369173
Short name T495
Test name
Test status
Simulation time 38112947 ps
CPU time 0.73 seconds
Started Feb 22 12:56:04 PM PST 24
Finished Feb 22 12:56:05 PM PST 24
Peak memory 205372 kb
Host smart-a00bd617-02bc-4998-b3ea-4cd93c325aa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735369173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.735369173
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1351807546
Short name T136
Test name
Test status
Simulation time 50995158 ps
CPU time 2.21 seconds
Started Feb 22 12:56:09 PM PST 24
Finished Feb 22 12:56:11 PM PST 24
Peak memory 205200 kb
Host smart-ef67733a-9060-42e4-b96e-8932dd9a748b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351807546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1351807546
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2451722247
Short name T546
Test name
Test status
Simulation time 101177257 ps
CPU time 3.12 seconds
Started Feb 22 12:56:06 PM PST 24
Finished Feb 22 12:56:09 PM PST 24
Peak memory 213808 kb
Host smart-c61a027c-e340-416b-8340-54a64afd38db
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451722247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2451722247
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1081916186
Short name T462
Test name
Test status
Simulation time 149172034 ps
CPU time 8.76 seconds
Started Feb 22 12:56:05 PM PST 24
Finished Feb 22 12:56:13 PM PST 24
Peak memory 219572 kb
Host smart-10f685f6-5af8-4d1e-86d2-7583a5cfa971
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081916186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1081916186
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1579889890
Short name T509
Test name
Test status
Simulation time 130505160 ps
CPU time 4.82 seconds
Started Feb 22 12:56:04 PM PST 24
Finished Feb 22 12:56:09 PM PST 24
Peak memory 213624 kb
Host smart-eec0d7d4-2a16-49f2-a13b-452cbfb4cc28
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579889890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1579889890
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3585000820
Short name T129
Test name
Test status
Simulation time 135521319 ps
CPU time 8.74 seconds
Started Feb 22 12:54:48 PM PST 24
Finished Feb 22 12:54:57 PM PST 24
Peak memory 205308 kb
Host smart-b001c00c-8c1d-4ae5-bf5a-fce95b2a3652
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585000820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
585000820
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.4127987646
Short name T510
Test name
Test status
Simulation time 4764777140 ps
CPU time 23.52 seconds
Started Feb 22 12:54:48 PM PST 24
Finished Feb 22 12:55:12 PM PST 24
Peak memory 205388 kb
Host smart-431d1789-699d-4ccc-bd6e-2cec70387480
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127987646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.4
127987646
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1278188117
Short name T525
Test name
Test status
Simulation time 57148868 ps
CPU time 0.99 seconds
Started Feb 22 12:54:43 PM PST 24
Finished Feb 22 12:54:44 PM PST 24
Peak memory 205100 kb
Host smart-062b2a2d-235b-4d67-a01f-892947f294e3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278188117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
278188117
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.4029519832
Short name T491
Test name
Test status
Simulation time 98287852 ps
CPU time 2.01 seconds
Started Feb 22 12:54:44 PM PST 24
Finished Feb 22 12:54:46 PM PST 24
Peak memory 213500 kb
Host smart-fdce1917-648a-40fb-8621-1ad7ca9c5a26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029519832 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.4029519832
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3217423927
Short name T128
Test name
Test status
Simulation time 30141414 ps
CPU time 1.12 seconds
Started Feb 22 12:54:44 PM PST 24
Finished Feb 22 12:54:46 PM PST 24
Peak memory 205152 kb
Host smart-df287d12-76f6-4b52-806c-654d30fd1a12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217423927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3217423927
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.929462171
Short name T521
Test name
Test status
Simulation time 36681443 ps
CPU time 0.74 seconds
Started Feb 22 12:54:45 PM PST 24
Finished Feb 22 12:54:46 PM PST 24
Peak memory 205148 kb
Host smart-85ab95a2-4126-418d-8d4a-4fb1642f0b65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929462171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.929462171
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.331312341
Short name T492
Test name
Test status
Simulation time 302695349 ps
CPU time 2.48 seconds
Started Feb 22 12:54:45 PM PST 24
Finished Feb 22 12:54:47 PM PST 24
Peak memory 205372 kb
Host smart-ee58c3e2-04af-4824-b6ab-f6cd749da67a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331312341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.331312341
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2140123855
Short name T157
Test name
Test status
Simulation time 107028268 ps
CPU time 3.39 seconds
Started Feb 22 12:54:45 PM PST 24
Finished Feb 22 12:54:48 PM PST 24
Peak memory 213704 kb
Host smart-b0a125be-6251-45c9-a175-fd97c6711546
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140123855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2140123855
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.4116563951
Short name T516
Test name
Test status
Simulation time 61524501 ps
CPU time 1.84 seconds
Started Feb 22 12:54:44 PM PST 24
Finished Feb 22 12:54:46 PM PST 24
Peak memory 213636 kb
Host smart-1a060d65-703d-4282-a588-afd1c9076cfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116563951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.4116563951
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1844718426
Short name T153
Test name
Test status
Simulation time 201409682 ps
CPU time 5.47 seconds
Started Feb 22 12:54:46 PM PST 24
Finished Feb 22 12:54:52 PM PST 24
Peak memory 209000 kb
Host smart-46f4278d-0a53-4dec-9694-a0862619a70f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844718426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1844718426
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3680464407
Short name T132
Test name
Test status
Simulation time 16510194 ps
CPU time 0.7 seconds
Started Feb 22 12:56:04 PM PST 24
Finished Feb 22 12:56:05 PM PST 24
Peak memory 205060 kb
Host smart-1ed93f91-4801-4c1a-a335-ac08ebb62bf0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680464407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3680464407
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3163108485
Short name T504
Test name
Test status
Simulation time 22544787 ps
CPU time 0.73 seconds
Started Feb 22 12:56:06 PM PST 24
Finished Feb 22 12:56:07 PM PST 24
Peak memory 205092 kb
Host smart-b6b97e87-c772-40af-b6b2-f3bed4b6330a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163108485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3163108485
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1311300802
Short name T536
Test name
Test status
Simulation time 21231584 ps
CPU time 0.79 seconds
Started Feb 22 12:56:04 PM PST 24
Finished Feb 22 12:56:05 PM PST 24
Peak memory 205092 kb
Host smart-a348fb8f-278d-4bef-a8ba-ed384106b5a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311300802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1311300802
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.4095055287
Short name T519
Test name
Test status
Simulation time 10588281 ps
CPU time 0.8 seconds
Started Feb 22 12:56:07 PM PST 24
Finished Feb 22 12:56:08 PM PST 24
Peak memory 205076 kb
Host smart-a411d589-46e2-482e-a15f-8488eee08577
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095055287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.4095055287
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.599155736
Short name T177
Test name
Test status
Simulation time 47610913 ps
CPU time 0.77 seconds
Started Feb 22 12:56:09 PM PST 24
Finished Feb 22 12:56:10 PM PST 24
Peak memory 204988 kb
Host smart-fd1fab98-8681-4070-9fd3-fd4b1f4919ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599155736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.599155736
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1706918365
Short name T506
Test name
Test status
Simulation time 11597273 ps
CPU time 0.84 seconds
Started Feb 22 12:56:08 PM PST 24
Finished Feb 22 12:56:10 PM PST 24
Peak memory 205100 kb
Host smart-0e58a066-a5f6-4c19-a076-1ff6efc599b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706918365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1706918365
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2752730227
Short name T563
Test name
Test status
Simulation time 23459131 ps
CPU time 0.71 seconds
Started Feb 22 12:56:05 PM PST 24
Finished Feb 22 12:56:06 PM PST 24
Peak memory 205076 kb
Host smart-7fc583cd-1c56-4491-bbd9-de3c5bfc3004
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752730227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2752730227
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3682468103
Short name T544
Test name
Test status
Simulation time 15034099 ps
CPU time 0.76 seconds
Started Feb 22 12:56:06 PM PST 24
Finished Feb 22 12:56:07 PM PST 24
Peak memory 205184 kb
Host smart-c68feeea-6824-476a-8952-9f63a4e09491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682468103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3682468103
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2222102846
Short name T454
Test name
Test status
Simulation time 67905757 ps
CPU time 0.77 seconds
Started Feb 22 12:56:07 PM PST 24
Finished Feb 22 12:56:08 PM PST 24
Peak memory 204244 kb
Host smart-d28f9e1d-77f3-43f0-8a02-fe63eba79642
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222102846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2222102846
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2026983544
Short name T451
Test name
Test status
Simulation time 11121433 ps
CPU time 0.68 seconds
Started Feb 22 12:56:06 PM PST 24
Finished Feb 22 12:56:07 PM PST 24
Peak memory 205088 kb
Host smart-31fc2d98-1b2f-4402-8929-93b96b8d8ac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026983544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2026983544
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1018150933
Short name T474
Test name
Test status
Simulation time 125739881 ps
CPU time 6.79 seconds
Started Feb 22 12:54:59 PM PST 24
Finished Feb 22 12:55:06 PM PST 24
Peak memory 205156 kb
Host smart-6c7e3ad0-6390-44e3-91e2-cbba43bf789e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018150933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
018150933
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3419970368
Short name T179
Test name
Test status
Simulation time 33518754 ps
CPU time 1.56 seconds
Started Feb 22 12:54:58 PM PST 24
Finished Feb 22 12:55:00 PM PST 24
Peak memory 205232 kb
Host smart-f9b9cacd-93b1-44ec-9b48-11592e68ab0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419970368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
419970368
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1678147194
Short name T464
Test name
Test status
Simulation time 47570206 ps
CPU time 1.92 seconds
Started Feb 22 12:54:58 PM PST 24
Finished Feb 22 12:55:00 PM PST 24
Peak memory 213576 kb
Host smart-bb85226f-2c05-4d2f-b179-ae27ec384c7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678147194 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1678147194
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1075721633
Short name T456
Test name
Test status
Simulation time 45145188 ps
CPU time 1.21 seconds
Started Feb 22 12:54:58 PM PST 24
Finished Feb 22 12:55:00 PM PST 24
Peak memory 205212 kb
Host smart-aacb11d6-f212-4cb4-8745-088e054a1c73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075721633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1075721633
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2719620478
Short name T522
Test name
Test status
Simulation time 12526046 ps
CPU time 0.74 seconds
Started Feb 22 12:54:47 PM PST 24
Finished Feb 22 12:54:47 PM PST 24
Peak memory 205120 kb
Host smart-8610fdd3-1ba4-41f5-8e0a-e3d18635f1f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719620478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2719620478
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1637027030
Short name T135
Test name
Test status
Simulation time 32465483 ps
CPU time 2.02 seconds
Started Feb 22 12:54:57 PM PST 24
Finished Feb 22 12:55:00 PM PST 24
Peak memory 213424 kb
Host smart-16217910-ff67-4f0a-b287-3f1438af8529
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637027030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1637027030
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1469822318
Short name T109
Test name
Test status
Simulation time 197985963 ps
CPU time 3.34 seconds
Started Feb 22 12:54:45 PM PST 24
Finished Feb 22 12:54:48 PM PST 24
Peak memory 221996 kb
Host smart-269bd7b1-ac5f-4001-9b15-73016ad5d250
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469822318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1469822318
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1236041967
Short name T538
Test name
Test status
Simulation time 476320305 ps
CPU time 11.57 seconds
Started Feb 22 12:54:44 PM PST 24
Finished Feb 22 12:54:56 PM PST 24
Peak memory 213752 kb
Host smart-43965246-558a-420e-a842-c47cd5da009e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236041967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1236041967
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3419584266
Short name T116
Test name
Test status
Simulation time 31864940 ps
CPU time 2.03 seconds
Started Feb 22 12:54:45 PM PST 24
Finished Feb 22 12:54:47 PM PST 24
Peak memory 213408 kb
Host smart-e388118b-4722-424c-9b2b-c51664971634
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419584266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3419584266
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3162407727
Short name T511
Test name
Test status
Simulation time 22234781 ps
CPU time 0.7 seconds
Started Feb 22 12:56:07 PM PST 24
Finished Feb 22 12:56:08 PM PST 24
Peak memory 204236 kb
Host smart-24c799f6-9350-4f02-80f0-5763fdf8f49f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162407727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3162407727
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2769336349
Short name T465
Test name
Test status
Simulation time 9559367 ps
CPU time 0.84 seconds
Started Feb 22 12:56:06 PM PST 24
Finished Feb 22 12:56:07 PM PST 24
Peak memory 205048 kb
Host smart-c355d401-1508-4ac8-a1c8-96239c203489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769336349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2769336349
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3240422432
Short name T447
Test name
Test status
Simulation time 15177280 ps
CPU time 0.71 seconds
Started Feb 22 12:56:06 PM PST 24
Finished Feb 22 12:56:07 PM PST 24
Peak memory 204972 kb
Host smart-38b1f3e4-c3c5-4575-b0cb-e3ed5087c849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240422432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3240422432
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1068199361
Short name T461
Test name
Test status
Simulation time 112724527 ps
CPU time 0.87 seconds
Started Feb 22 12:56:06 PM PST 24
Finished Feb 22 12:56:08 PM PST 24
Peak memory 205092 kb
Host smart-702d9fce-9c3d-4fc3-ab7f-b03b120228b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068199361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1068199361
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.639131407
Short name T458
Test name
Test status
Simulation time 14156650 ps
CPU time 0.71 seconds
Started Feb 22 12:56:08 PM PST 24
Finished Feb 22 12:56:10 PM PST 24
Peak memory 205124 kb
Host smart-cc010240-5f82-4082-bcf2-8bc994732964
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639131407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.639131407
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.516861354
Short name T537
Test name
Test status
Simulation time 15316921 ps
CPU time 0.74 seconds
Started Feb 22 12:56:08 PM PST 24
Finished Feb 22 12:56:10 PM PST 24
Peak memory 205120 kb
Host smart-5cca060b-963b-48cc-b52b-065449e6f8e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516861354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.516861354
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.739894316
Short name T397
Test name
Test status
Simulation time 26095404 ps
CPU time 0.7 seconds
Started Feb 22 12:56:23 PM PST 24
Finished Feb 22 12:56:25 PM PST 24
Peak memory 205136 kb
Host smart-f43e4067-bb60-4833-95bc-eb46f939589c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739894316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.739894316
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1807318740
Short name T446
Test name
Test status
Simulation time 12437023 ps
CPU time 0.71 seconds
Started Feb 22 12:56:22 PM PST 24
Finished Feb 22 12:56:24 PM PST 24
Peak memory 205096 kb
Host smart-6751ee3b-4f3d-4cc8-87a3-e214357ec702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807318740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1807318740
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1793794412
Short name T529
Test name
Test status
Simulation time 13336786 ps
CPU time 0.7 seconds
Started Feb 22 12:56:24 PM PST 24
Finished Feb 22 12:56:25 PM PST 24
Peak memory 205156 kb
Host smart-54750a9b-0af8-4c01-801b-6bd2c6c2a950
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793794412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1793794412
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3688733682
Short name T554
Test name
Test status
Simulation time 12322719 ps
CPU time 0.73 seconds
Started Feb 22 12:56:23 PM PST 24
Finished Feb 22 12:56:25 PM PST 24
Peak memory 205136 kb
Host smart-df813936-c854-45a8-a010-f87e8cf70404
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688733682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3688733682
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2054545181
Short name T453
Test name
Test status
Simulation time 544498323 ps
CPU time 7.62 seconds
Started Feb 22 12:54:56 PM PST 24
Finished Feb 22 12:55:04 PM PST 24
Peak memory 205140 kb
Host smart-1767fdb2-c888-4d24-9950-2c6db51bc058
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054545181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
054545181
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2467018446
Short name T524
Test name
Test status
Simulation time 96633466 ps
CPU time 0.98 seconds
Started Feb 22 12:54:57 PM PST 24
Finished Feb 22 12:54:58 PM PST 24
Peak memory 205164 kb
Host smart-f5b00120-b293-4ac1-bc0e-c9d318da0069
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467018446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
467018446
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.421163405
Short name T117
Test name
Test status
Simulation time 31716233 ps
CPU time 1.22 seconds
Started Feb 22 12:54:58 PM PST 24
Finished Feb 22 12:55:00 PM PST 24
Peak memory 213596 kb
Host smart-344063d3-f242-447d-83a8-1db85cc63fe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421163405 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.421163405
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1508027742
Short name T515
Test name
Test status
Simulation time 19475933 ps
CPU time 0.7 seconds
Started Feb 22 12:54:57 PM PST 24
Finished Feb 22 12:54:58 PM PST 24
Peak memory 205076 kb
Host smart-a90a06ad-e113-4294-b5e2-b25deb1b2f51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508027742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1508027742
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3519752788
Short name T137
Test name
Test status
Simulation time 323260895 ps
CPU time 2.69 seconds
Started Feb 22 12:54:59 PM PST 24
Finished Feb 22 12:55:03 PM PST 24
Peak memory 205300 kb
Host smart-182e8b29-19ed-48c1-8777-df1f615001f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519752788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3519752788
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2316848164
Short name T526
Test name
Test status
Simulation time 422119711 ps
CPU time 4.14 seconds
Started Feb 22 12:54:56 PM PST 24
Finished Feb 22 12:55:01 PM PST 24
Peak memory 213824 kb
Host smart-f20b462f-cd9e-4578-af08-e0902ffc2a27
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316848164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2316848164
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2522853535
Short name T481
Test name
Test status
Simulation time 274581295 ps
CPU time 5.42 seconds
Started Feb 22 12:54:59 PM PST 24
Finished Feb 22 12:55:05 PM PST 24
Peak memory 216576 kb
Host smart-979e86f3-f308-4d92-8e21-26985a551bae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522853535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2522853535
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3157930183
Short name T549
Test name
Test status
Simulation time 13295266 ps
CPU time 0.87 seconds
Started Feb 22 12:56:21 PM PST 24
Finished Feb 22 12:56:23 PM PST 24
Peak memory 205176 kb
Host smart-443d081c-ba98-4eed-996f-c262fffcb491
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157930183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3157930183
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1972652193
Short name T466
Test name
Test status
Simulation time 28580869 ps
CPU time 0.74 seconds
Started Feb 22 12:56:22 PM PST 24
Finished Feb 22 12:56:23 PM PST 24
Peak memory 205088 kb
Host smart-e6c975e6-e943-4340-a983-b2507bbb1114
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972652193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1972652193
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.1349672820
Short name T398
Test name
Test status
Simulation time 18472918 ps
CPU time 0.77 seconds
Started Feb 22 12:56:21 PM PST 24
Finished Feb 22 12:56:22 PM PST 24
Peak memory 205152 kb
Host smart-1d11a7d8-31db-429d-b326-073358ce502a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349672820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.1349672820
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3440999414
Short name T478
Test name
Test status
Simulation time 9477584 ps
CPU time 0.82 seconds
Started Feb 22 12:56:22 PM PST 24
Finished Feb 22 12:56:23 PM PST 24
Peak memory 205064 kb
Host smart-f753702c-cf73-482e-9b60-61b7aabf9edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440999414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3440999414
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2691728150
Short name T459
Test name
Test status
Simulation time 7528694 ps
CPU time 0.78 seconds
Started Feb 22 12:56:22 PM PST 24
Finished Feb 22 12:56:24 PM PST 24
Peak memory 204972 kb
Host smart-73439c15-cd3c-4e9b-aa20-15128f9f0a98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691728150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2691728150
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1492097542
Short name T543
Test name
Test status
Simulation time 44090313 ps
CPU time 0.83 seconds
Started Feb 22 12:56:24 PM PST 24
Finished Feb 22 12:56:25 PM PST 24
Peak memory 205092 kb
Host smart-281ab50b-774a-4e59-aa3c-91c524deb02d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492097542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1492097542
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2566201488
Short name T484
Test name
Test status
Simulation time 61502648 ps
CPU time 0.84 seconds
Started Feb 22 12:56:22 PM PST 24
Finished Feb 22 12:56:23 PM PST 24
Peak memory 205172 kb
Host smart-58136eab-ce57-40d9-8955-d4cce8cc8c5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566201488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2566201488
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3055555688
Short name T452
Test name
Test status
Simulation time 32750886 ps
CPU time 0.81 seconds
Started Feb 22 12:56:19 PM PST 24
Finished Feb 22 12:56:20 PM PST 24
Peak memory 205156 kb
Host smart-c0425c5c-965a-4e13-bc45-b4ff51131a60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055555688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3055555688
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.248718454
Short name T540
Test name
Test status
Simulation time 10731560 ps
CPU time 0.73 seconds
Started Feb 22 12:56:23 PM PST 24
Finished Feb 22 12:56:25 PM PST 24
Peak memory 205160 kb
Host smart-613c5c08-4b7a-4425-8496-3545e9d01501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248718454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.248718454
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3552632858
Short name T449
Test name
Test status
Simulation time 49324512 ps
CPU time 0.78 seconds
Started Feb 22 12:56:24 PM PST 24
Finished Feb 22 12:56:26 PM PST 24
Peak memory 205168 kb
Host smart-a687585c-1a2c-4747-aa38-e936d994eafb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552632858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3552632858
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2532689471
Short name T493
Test name
Test status
Simulation time 30243423 ps
CPU time 1.52 seconds
Started Feb 22 12:55:12 PM PST 24
Finished Feb 22 12:55:13 PM PST 24
Peak memory 213516 kb
Host smart-3a31acdd-431c-43f8-a30d-66c81e95795e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532689471 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2532689471
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2470540812
Short name T134
Test name
Test status
Simulation time 12543220 ps
CPU time 0.87 seconds
Started Feb 22 12:55:14 PM PST 24
Finished Feb 22 12:55:15 PM PST 24
Peak memory 205108 kb
Host smart-37c0529c-45b3-4dff-9e86-fe4a69d5bfb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470540812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2470540812
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2002086411
Short name T539
Test name
Test status
Simulation time 49542665 ps
CPU time 0.72 seconds
Started Feb 22 12:54:56 PM PST 24
Finished Feb 22 12:54:57 PM PST 24
Peak memory 205148 kb
Host smart-496ea310-8c6d-4287-b3e6-42581a3a0226
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002086411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2002086411
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.578842864
Short name T138
Test name
Test status
Simulation time 55859580 ps
CPU time 2.05 seconds
Started Feb 22 12:55:14 PM PST 24
Finished Feb 22 12:55:17 PM PST 24
Peak memory 205372 kb
Host smart-ab289c10-572c-4be0-bebb-227c66748848
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578842864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.578842864
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3890330906
Short name T550
Test name
Test status
Simulation time 257067129 ps
CPU time 6.05 seconds
Started Feb 22 12:54:58 PM PST 24
Finished Feb 22 12:55:04 PM PST 24
Peak memory 213740 kb
Host smart-c72a04b4-52c4-4dfa-8e48-b444e854808e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890330906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3890330906
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.885881803
Short name T472
Test name
Test status
Simulation time 115479532 ps
CPU time 5.85 seconds
Started Feb 22 12:55:00 PM PST 24
Finished Feb 22 12:55:06 PM PST 24
Peak memory 213688 kb
Host smart-c4294c2b-da53-4a56-961b-e930a0eda3b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885881803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.885881803
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3537789705
Short name T496
Test name
Test status
Simulation time 121995387 ps
CPU time 1.9 seconds
Started Feb 22 12:54:57 PM PST 24
Finished Feb 22 12:55:00 PM PST 24
Peak memory 215656 kb
Host smart-ba550ad4-87ac-4cf1-8519-40c4bc15909b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537789705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3537789705
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1265986872
Short name T551
Test name
Test status
Simulation time 40716717 ps
CPU time 1.09 seconds
Started Feb 22 12:55:13 PM PST 24
Finished Feb 22 12:55:15 PM PST 24
Peak memory 205152 kb
Host smart-22db554d-c91d-4293-8c57-7b22b4df6570
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265986872 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1265986872
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.4255078147
Short name T448
Test name
Test status
Simulation time 7655412 ps
CPU time 0.73 seconds
Started Feb 22 12:55:14 PM PST 24
Finished Feb 22 12:55:15 PM PST 24
Peak memory 205164 kb
Host smart-623a4568-df6e-4f7b-8ca2-3e6f663565ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255078147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.4255078147
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.759710281
Short name T560
Test name
Test status
Simulation time 681596201 ps
CPU time 13.64 seconds
Started Feb 22 12:55:14 PM PST 24
Finished Feb 22 12:55:28 PM PST 24
Peak memory 214816 kb
Host smart-4197805b-6d6c-4493-95ff-f427e1bf4635
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759710281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.759710281
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2936800453
Short name T513
Test name
Test status
Simulation time 37887583 ps
CPU time 2.37 seconds
Started Feb 22 12:55:14 PM PST 24
Finished Feb 22 12:55:17 PM PST 24
Peak memory 213640 kb
Host smart-6e33020b-ddc0-41eb-aba4-075f86c521c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936800453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2936800453
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4216736469
Short name T168
Test name
Test status
Simulation time 47335158 ps
CPU time 1.46 seconds
Started Feb 22 12:55:15 PM PST 24
Finished Feb 22 12:55:17 PM PST 24
Peak memory 213724 kb
Host smart-64708f65-2d94-4f24-9fc3-61b54eefe1c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216736469 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.4216736469
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.838898763
Short name T169
Test name
Test status
Simulation time 46707769 ps
CPU time 1.01 seconds
Started Feb 22 12:55:14 PM PST 24
Finished Feb 22 12:55:16 PM PST 24
Peak memory 205092 kb
Host smart-86efa166-9a79-4230-9c3d-943df4863a66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838898763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.838898763
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2580688715
Short name T460
Test name
Test status
Simulation time 53974291 ps
CPU time 0.69 seconds
Started Feb 22 12:55:13 PM PST 24
Finished Feb 22 12:55:14 PM PST 24
Peak memory 204928 kb
Host smart-f4a82bfc-e41f-406c-9181-4816019b10e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580688715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2580688715
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3557282896
Short name T104
Test name
Test status
Simulation time 342929295 ps
CPU time 2.96 seconds
Started Feb 22 12:55:15 PM PST 24
Finished Feb 22 12:55:18 PM PST 24
Peak memory 213876 kb
Host smart-8ba979b5-1ea7-4b6a-85d4-62ca88c1523d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557282896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3557282896
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3568205664
Short name T558
Test name
Test status
Simulation time 172621441 ps
CPU time 2.34 seconds
Started Feb 22 12:55:13 PM PST 24
Finished Feb 22 12:55:16 PM PST 24
Peak memory 216604 kb
Host smart-2e7715bb-a1ae-427f-8849-d6000b3567b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568205664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3568205664
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4140869794
Short name T497
Test name
Test status
Simulation time 36109426 ps
CPU time 1.06 seconds
Started Feb 22 12:55:26 PM PST 24
Finished Feb 22 12:55:27 PM PST 24
Peak memory 205552 kb
Host smart-ac27433b-a3f5-4e78-95c8-01e69b1c4223
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140869794 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.4140869794
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2998258802
Short name T531
Test name
Test status
Simulation time 49310654 ps
CPU time 0.73 seconds
Started Feb 22 12:55:29 PM PST 24
Finished Feb 22 12:55:30 PM PST 24
Peak memory 205172 kb
Host smart-3853a4fe-afe9-4ceb-8f1a-9acd45a6c55c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998258802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2998258802
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.987760010
Short name T555
Test name
Test status
Simulation time 23275095 ps
CPU time 1.31 seconds
Started Feb 22 12:55:25 PM PST 24
Finished Feb 22 12:55:26 PM PST 24
Peak memory 205156 kb
Host smart-619aa104-f803-46a9-a7e0-e2d02cdb7e21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987760010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.987760010
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3025332446
Short name T498
Test name
Test status
Simulation time 2544508237 ps
CPU time 12.76 seconds
Started Feb 22 12:55:15 PM PST 24
Finished Feb 22 12:55:28 PM PST 24
Peak memory 213864 kb
Host smart-1835b6aa-f6fc-43c9-9a48-5ebfa2a2dc15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025332446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3025332446
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2172314057
Short name T122
Test name
Test status
Simulation time 246596186 ps
CPU time 2.95 seconds
Started Feb 22 12:55:29 PM PST 24
Finished Feb 22 12:55:32 PM PST 24
Peak memory 213628 kb
Host smart-30a39064-f938-4f7b-a18c-32a59dc957ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172314057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2172314057
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3591981331
Short name T487
Test name
Test status
Simulation time 526974548 ps
CPU time 4.43 seconds
Started Feb 22 12:55:28 PM PST 24
Finished Feb 22 12:55:33 PM PST 24
Peak memory 208444 kb
Host smart-30a24172-23d5-4399-8fa4-7cec55affdf4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591981331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3591981331
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3143055149
Short name T489
Test name
Test status
Simulation time 22734425 ps
CPU time 1.47 seconds
Started Feb 22 12:55:27 PM PST 24
Finished Feb 22 12:55:29 PM PST 24
Peak memory 213560 kb
Host smart-536c1465-b9ee-4151-98e9-c836470a7456
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143055149 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3143055149
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.283380165
Short name T534
Test name
Test status
Simulation time 15535776 ps
CPU time 1.04 seconds
Started Feb 22 12:55:26 PM PST 24
Finished Feb 22 12:55:27 PM PST 24
Peak memory 205216 kb
Host smart-8ea21cc1-788d-44e9-b11c-5fb7da8ec224
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283380165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.283380165
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.354525270
Short name T450
Test name
Test status
Simulation time 9311929 ps
CPU time 0.72 seconds
Started Feb 22 12:55:24 PM PST 24
Finished Feb 22 12:55:26 PM PST 24
Peak memory 205156 kb
Host smart-d1f1b0f7-4cd6-49d0-94ad-66228413a058
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354525270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.354525270
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.447414575
Short name T467
Test name
Test status
Simulation time 196774853 ps
CPU time 6.01 seconds
Started Feb 22 12:55:28 PM PST 24
Finished Feb 22 12:55:34 PM PST 24
Peak memory 213756 kb
Host smart-da0b2191-bd00-4ad6-8748-999767882ca9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447414575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.447414575
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.884774553
Short name T144
Test name
Test status
Simulation time 159196921 ps
CPU time 4.97 seconds
Started Feb 22 12:55:28 PM PST 24
Finished Feb 22 12:55:33 PM PST 24
Peak memory 213448 kb
Host smart-c1c428ed-018a-41d3-9239-1cd71cce7ae8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884774553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.884774553
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.367377424
Short name T935
Test name
Test status
Simulation time 10116701 ps
CPU time 0.81 seconds
Started Feb 22 01:05:35 PM PST 24
Finished Feb 22 01:05:36 PM PST 24
Peak memory 205836 kb
Host smart-fbbf0aed-5e0d-47ce-b330-c27da9b45ba3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367377424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.367377424
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.738961211
Short name T241
Test name
Test status
Simulation time 307829246 ps
CPU time 15.5 seconds
Started Feb 22 01:05:30 PM PST 24
Finished Feb 22 01:05:45 PM PST 24
Peak memory 214744 kb
Host smart-b6616d80-94e6-447c-b236-ff9b04060274
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=738961211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.738961211
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3641213117
Short name T995
Test name
Test status
Simulation time 82112318 ps
CPU time 2.77 seconds
Started Feb 22 01:05:39 PM PST 24
Finished Feb 22 01:05:43 PM PST 24
Peak memory 214556 kb
Host smart-805f33f2-6ccf-45a5-b240-5d6150ace892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641213117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3641213117
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2987139879
Short name T345
Test name
Test status
Simulation time 193561619 ps
CPU time 3.35 seconds
Started Feb 22 01:05:23 PM PST 24
Finished Feb 22 01:05:27 PM PST 24
Peak memory 208900 kb
Host smart-5ae8b4bc-e320-4200-8717-18cf9a78e9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987139879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2987139879
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1121463715
Short name T624
Test name
Test status
Simulation time 60000752 ps
CPU time 2.1 seconds
Started Feb 22 01:05:42 PM PST 24
Finished Feb 22 01:05:45 PM PST 24
Peak memory 208556 kb
Host smart-bcfce565-a207-409e-b02d-2ccff5e4ddaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121463715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1121463715
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.4060558408
Short name T392
Test name
Test status
Simulation time 99847736 ps
CPU time 4.5 seconds
Started Feb 22 01:05:33 PM PST 24
Finished Feb 22 01:05:38 PM PST 24
Peak memory 214200 kb
Host smart-7f042c7f-01e0-409b-a168-0b292e2279a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060558408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.4060558408
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2687930974
Short name T1024
Test name
Test status
Simulation time 301667346 ps
CPU time 2.63 seconds
Started Feb 22 01:05:18 PM PST 24
Finished Feb 22 01:05:21 PM PST 24
Peak memory 214324 kb
Host smart-49909913-b58f-4555-ba64-e4d9a94329f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687930974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2687930974
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3245247895
Short name T798
Test name
Test status
Simulation time 142971367 ps
CPU time 2.94 seconds
Started Feb 22 01:05:19 PM PST 24
Finished Feb 22 01:05:22 PM PST 24
Peak memory 214716 kb
Host smart-345fd49c-ac5b-418a-8544-ee7d7b363012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245247895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3245247895
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3517993910
Short name T11
Test name
Test status
Simulation time 10476314732 ps
CPU time 44.86 seconds
Started Feb 22 01:05:34 PM PST 24
Finished Feb 22 01:06:19 PM PST 24
Peak memory 235760 kb
Host smart-1689af26-8c5a-4faa-87e0-a6d467c4170a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517993910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3517993910
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2461151154
Short name T590
Test name
Test status
Simulation time 86131455 ps
CPU time 3.33 seconds
Started Feb 22 01:05:23 PM PST 24
Finished Feb 22 01:05:26 PM PST 24
Peak memory 206700 kb
Host smart-c7a1e83d-58d2-409f-a1b5-641bbf5f6fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461151154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2461151154
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2437986174
Short name T845
Test name
Test status
Simulation time 8456984143 ps
CPU time 59.38 seconds
Started Feb 22 01:05:29 PM PST 24
Finished Feb 22 01:06:29 PM PST 24
Peak memory 209168 kb
Host smart-09065feb-d2eb-4f46-82a7-42524d08978a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437986174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2437986174
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.710029995
Short name T913
Test name
Test status
Simulation time 599205366 ps
CPU time 8.91 seconds
Started Feb 22 01:05:30 PM PST 24
Finished Feb 22 01:05:39 PM PST 24
Peak memory 207324 kb
Host smart-c9b49b14-e047-48db-895b-2cdec91f57bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710029995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.710029995
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.623547227
Short name T929
Test name
Test status
Simulation time 2594731126 ps
CPU time 30.8 seconds
Started Feb 22 01:05:30 PM PST 24
Finished Feb 22 01:06:01 PM PST 24
Peak memory 207796 kb
Host smart-fea84896-8645-4542-9ebb-6caba75371fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623547227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.623547227
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2992764564
Short name T728
Test name
Test status
Simulation time 31697113 ps
CPU time 2.19 seconds
Started Feb 22 01:05:43 PM PST 24
Finished Feb 22 01:05:46 PM PST 24
Peak memory 208404 kb
Host smart-288e2f21-a4e8-4256-a79b-706a61e896d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992764564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2992764564
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.4093546121
Short name T956
Test name
Test status
Simulation time 487409843 ps
CPU time 4.18 seconds
Started Feb 22 01:05:30 PM PST 24
Finished Feb 22 01:05:34 PM PST 24
Peak memory 208488 kb
Host smart-15a58550-d56f-49de-86f5-31a3925871fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093546121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.4093546121
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.777816410
Short name T860
Test name
Test status
Simulation time 219164253 ps
CPU time 4.92 seconds
Started Feb 22 01:05:24 PM PST 24
Finished Feb 22 01:05:29 PM PST 24
Peak memory 208116 kb
Host smart-1017d382-1254-4680-ab47-1abd142108db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777816410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.777816410
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.728127358
Short name T1064
Test name
Test status
Simulation time 105710390 ps
CPU time 3.57 seconds
Started Feb 22 01:05:35 PM PST 24
Finished Feb 22 01:05:39 PM PST 24
Peak memory 210660 kb
Host smart-d79f4398-03d1-4d5a-8388-9524906f82c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728127358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.728127358
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2038156649
Short name T721
Test name
Test status
Simulation time 14960768 ps
CPU time 0.94 seconds
Started Feb 22 01:05:34 PM PST 24
Finished Feb 22 01:05:35 PM PST 24
Peak memory 206008 kb
Host smart-60a6b89a-4c3d-4e29-ba9f-01df49f26139
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038156649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2038156649
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3525615872
Short name T432
Test name
Test status
Simulation time 102359010 ps
CPU time 2.41 seconds
Started Feb 22 01:05:41 PM PST 24
Finished Feb 22 01:05:44 PM PST 24
Peak memory 214308 kb
Host smart-bb87a9ae-0730-4a79-a38f-352d614f4bb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3525615872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3525615872
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1974718247
Short name T28
Test name
Test status
Simulation time 74914148 ps
CPU time 3.2 seconds
Started Feb 22 01:05:30 PM PST 24
Finished Feb 22 01:05:33 PM PST 24
Peak memory 221820 kb
Host smart-1051cab3-1575-4490-9663-fc4d3db1e621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974718247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1974718247
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3719495204
Short name T619
Test name
Test status
Simulation time 742134372 ps
CPU time 8.99 seconds
Started Feb 22 01:05:30 PM PST 24
Finished Feb 22 01:05:40 PM PST 24
Peak memory 208768 kb
Host smart-4ac613ba-2274-41bc-bb65-1c99a96e1ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719495204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3719495204
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.330626518
Short name T96
Test name
Test status
Simulation time 457033160 ps
CPU time 9.63 seconds
Started Feb 22 01:05:33 PM PST 24
Finished Feb 22 01:05:43 PM PST 24
Peak memory 222388 kb
Host smart-6f8bdfa4-3b22-4db5-8689-34101b7999e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330626518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.330626518
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1667269241
Short name T251
Test name
Test status
Simulation time 59370579 ps
CPU time 3.96 seconds
Started Feb 22 01:05:35 PM PST 24
Finished Feb 22 01:05:40 PM PST 24
Peak memory 209264 kb
Host smart-e74ceb2b-a0b0-49ba-99da-4412afaa2d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667269241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1667269241
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1496776337
Short name T944
Test name
Test status
Simulation time 82364965 ps
CPU time 3.24 seconds
Started Feb 22 01:05:31 PM PST 24
Finished Feb 22 01:05:35 PM PST 24
Peak memory 209388 kb
Host smart-f21ac7fd-0d5e-44df-b884-e32541c374e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496776337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1496776337
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2577038821
Short name T857
Test name
Test status
Simulation time 112011581 ps
CPU time 3.48 seconds
Started Feb 22 01:05:54 PM PST 24
Finished Feb 22 01:05:58 PM PST 24
Peak memory 208128 kb
Host smart-dba62260-5e54-4897-b016-d4f8bde180dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577038821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2577038821
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3660001231
Short name T102
Test name
Test status
Simulation time 1246841702 ps
CPU time 20.66 seconds
Started Feb 22 01:05:32 PM PST 24
Finished Feb 22 01:05:53 PM PST 24
Peak memory 234108 kb
Host smart-c5f14388-ddaf-49dc-bc64-1533ce36b695
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660001231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3660001231
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4258581316
Short name T281
Test name
Test status
Simulation time 51933433 ps
CPU time 2.78 seconds
Started Feb 22 01:05:32 PM PST 24
Finished Feb 22 01:05:35 PM PST 24
Peak memory 206824 kb
Host smart-c7e008d9-0d6e-4c05-bab5-bf04660408a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258581316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4258581316
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1160705065
Short name T867
Test name
Test status
Simulation time 197343703 ps
CPU time 4.78 seconds
Started Feb 22 01:05:33 PM PST 24
Finished Feb 22 01:05:38 PM PST 24
Peak memory 208468 kb
Host smart-199e3fd4-8074-470a-bf8f-c4005ca9e355
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160705065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1160705065
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1944761525
Short name T639
Test name
Test status
Simulation time 168111806 ps
CPU time 2.55 seconds
Started Feb 22 01:05:28 PM PST 24
Finished Feb 22 01:05:31 PM PST 24
Peak memory 208756 kb
Host smart-ce33eddf-0ba0-4362-968a-2a9d3961c99f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944761525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1944761525
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.563806945
Short name T858
Test name
Test status
Simulation time 28667050 ps
CPU time 1.67 seconds
Started Feb 22 01:05:34 PM PST 24
Finished Feb 22 01:05:36 PM PST 24
Peak memory 207016 kb
Host smart-94811585-d8d9-48ec-b36e-a0b1ad1af13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563806945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.563806945
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1177965161
Short name T600
Test name
Test status
Simulation time 255135323 ps
CPU time 3.03 seconds
Started Feb 22 01:05:33 PM PST 24
Finished Feb 22 01:05:37 PM PST 24
Peak memory 206764 kb
Host smart-78df3d36-fea4-4815-8bbe-5375cf27560c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177965161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1177965161
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.865249399
Short name T740
Test name
Test status
Simulation time 188178023 ps
CPU time 6.3 seconds
Started Feb 22 01:05:30 PM PST 24
Finished Feb 22 01:05:37 PM PST 24
Peak memory 209120 kb
Host smart-d21129ed-6b6a-47e1-961b-8899c96df397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865249399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.865249399
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3831844929
Short name T152
Test name
Test status
Simulation time 36618741 ps
CPU time 2.37 seconds
Started Feb 22 01:05:35 PM PST 24
Finished Feb 22 01:05:38 PM PST 24
Peak memory 210144 kb
Host smart-e8f59766-6736-4fbd-a21e-cb68f39c49f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831844929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3831844929
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3996706599
Short name T573
Test name
Test status
Simulation time 38519679 ps
CPU time 0.76 seconds
Started Feb 22 01:06:20 PM PST 24
Finished Feb 22 01:06:21 PM PST 24
Peak memory 205808 kb
Host smart-7be90122-6890-4e6b-9342-616565750be4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996706599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3996706599
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3476749069
Short name T10
Test name
Test status
Simulation time 706028126 ps
CPU time 5.85 seconds
Started Feb 22 01:06:18 PM PST 24
Finished Feb 22 01:06:25 PM PST 24
Peak memory 210616 kb
Host smart-524256e7-e370-41fd-a4e1-977c8ee8cffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476749069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3476749069
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1236422661
Short name T71
Test name
Test status
Simulation time 315154898 ps
CPU time 4.01 seconds
Started Feb 22 01:06:15 PM PST 24
Finished Feb 22 01:06:20 PM PST 24
Peak memory 208068 kb
Host smart-0d57eab8-866b-41d1-af02-028d26bb48f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236422661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1236422661
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.165213
Short name T336
Test name
Test status
Simulation time 92632605 ps
CPU time 4.34 seconds
Started Feb 22 01:06:14 PM PST 24
Finished Feb 22 01:06:20 PM PST 24
Peak memory 214112 kb
Host smart-267077af-e2ae-4376-adc3-ac7ea5939afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.165213
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1564431795
Short name T1050
Test name
Test status
Simulation time 226702617 ps
CPU time 4.79 seconds
Started Feb 22 01:06:20 PM PST 24
Finished Feb 22 01:06:26 PM PST 24
Peak memory 214272 kb
Host smart-60af6309-6795-4a2b-9564-919b8acb7c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564431795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1564431795
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.391306067
Short name T694
Test name
Test status
Simulation time 113201927 ps
CPU time 4.81 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:06:23 PM PST 24
Peak memory 218264 kb
Host smart-a36eecd2-8ccb-4876-aeb1-347a69c9f983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391306067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.391306067
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1428891432
Short name T311
Test name
Test status
Simulation time 243435440 ps
CPU time 6.62 seconds
Started Feb 22 01:06:13 PM PST 24
Finished Feb 22 01:06:20 PM PST 24
Peak memory 208556 kb
Host smart-5f7290f8-736a-4d33-a946-a2fac66f8fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428891432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1428891432
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2297195509
Short name T715
Test name
Test status
Simulation time 925347954 ps
CPU time 7.63 seconds
Started Feb 22 01:06:14 PM PST 24
Finished Feb 22 01:06:23 PM PST 24
Peak memory 207956 kb
Host smart-6faf676c-5f81-493d-99e7-eb6183680a0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297195509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2297195509
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.4219102197
Short name T859
Test name
Test status
Simulation time 52923719 ps
CPU time 2.26 seconds
Started Feb 22 01:06:27 PM PST 24
Finished Feb 22 01:06:30 PM PST 24
Peak memory 208816 kb
Host smart-f9f1300c-95c4-46c0-bb65-48656fd9b714
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219102197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.4219102197
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1345019724
Short name T338
Test name
Test status
Simulation time 45818158 ps
CPU time 2.88 seconds
Started Feb 22 01:06:13 PM PST 24
Finished Feb 22 01:06:17 PM PST 24
Peak memory 208752 kb
Host smart-450789c7-5a2c-4a6d-baad-dc7dc30b1c24
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345019724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1345019724
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1740463515
Short name T988
Test name
Test status
Simulation time 154589516 ps
CPU time 2.81 seconds
Started Feb 22 01:06:14 PM PST 24
Finished Feb 22 01:06:18 PM PST 24
Peak memory 215856 kb
Host smart-6169726c-9100-424c-af6a-9350b9dfd47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740463515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1740463515
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3738546401
Short name T191
Test name
Test status
Simulation time 94153299 ps
CPU time 3.08 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:06:22 PM PST 24
Peak memory 206732 kb
Host smart-dd1a8ecc-ba33-4116-a4ae-23603e775c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738546401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3738546401
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.893029225
Short name T842
Test name
Test status
Simulation time 5034838812 ps
CPU time 19.23 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:06:38 PM PST 24
Peak memory 216872 kb
Host smart-8773ed38-e023-4901-9fe8-b383d3819ff7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893029225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.893029225
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3719523383
Short name T1002
Test name
Test status
Simulation time 221523618 ps
CPU time 5.7 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:06:24 PM PST 24
Peak memory 222604 kb
Host smart-ebac3215-25a5-4213-9a7f-7810635ab75a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719523383 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3719523383
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.767294188
Short name T327
Test name
Test status
Simulation time 442399911 ps
CPU time 4.32 seconds
Started Feb 22 01:06:19 PM PST 24
Finished Feb 22 01:06:24 PM PST 24
Peak memory 206984 kb
Host smart-b153a5ec-a49d-44d2-b68f-92222d82a95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767294188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.767294188
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2533164968
Short name T794
Test name
Test status
Simulation time 58797111 ps
CPU time 1.09 seconds
Started Feb 22 01:06:18 PM PST 24
Finished Feb 22 01:06:20 PM PST 24
Peak memory 209652 kb
Host smart-2886e1e8-9c83-4b85-aaad-083c918131ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533164968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2533164968
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.76727739
Short name T1040
Test name
Test status
Simulation time 39788490 ps
CPU time 0.72 seconds
Started Feb 22 01:06:20 PM PST 24
Finished Feb 22 01:06:22 PM PST 24
Peak memory 205872 kb
Host smart-1a5741b8-3772-4f94-8e5e-0c93106d99ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76727739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.76727739
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2925012010
Short name T1018
Test name
Test status
Simulation time 223314501 ps
CPU time 3.54 seconds
Started Feb 22 01:06:17 PM PST 24
Finished Feb 22 01:06:22 PM PST 24
Peak memory 222784 kb
Host smart-89e49b8a-ca54-409d-a1b3-81a600d5ae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925012010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2925012010
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3172153981
Short name T75
Test name
Test status
Simulation time 131684732 ps
CPU time 2.13 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:06:21 PM PST 24
Peak memory 209112 kb
Host smart-8d4497b7-049f-48fd-bbf6-b81315d7289c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172153981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3172153981
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.690923407
Short name T86
Test name
Test status
Simulation time 1726536757 ps
CPU time 15.09 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:06:34 PM PST 24
Peak memory 208488 kb
Host smart-84fbc43b-0d56-4971-93ce-77fd9a53591b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690923407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.690923407
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3073753559
Short name T832
Test name
Test status
Simulation time 148632895 ps
CPU time 7.42 seconds
Started Feb 22 01:06:17 PM PST 24
Finished Feb 22 01:06:26 PM PST 24
Peak memory 210124 kb
Host smart-72545546-6f66-44d3-8f62-4f172a96b648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073753559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3073753559
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3188173075
Short name T1009
Test name
Test status
Simulation time 1052448213 ps
CPU time 5.33 seconds
Started Feb 22 01:06:18 PM PST 24
Finished Feb 22 01:06:24 PM PST 24
Peak memory 207928 kb
Host smart-ee6dcdaa-9e52-4c54-a23a-155ee027d5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188173075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3188173075
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1666820328
Short name T720
Test name
Test status
Simulation time 185806951 ps
CPU time 3.43 seconds
Started Feb 22 01:06:15 PM PST 24
Finished Feb 22 01:06:19 PM PST 24
Peak memory 218348 kb
Host smart-3c1ca62b-0e63-4aa2-b854-3457c0707026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666820328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1666820328
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2259292698
Short name T347
Test name
Test status
Simulation time 99188673 ps
CPU time 4.35 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:06:23 PM PST 24
Peak memory 208540 kb
Host smart-e697730c-c4ab-49b7-8455-f2f6201b87b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259292698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2259292698
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1281247689
Short name T992
Test name
Test status
Simulation time 1104183137 ps
CPU time 8.84 seconds
Started Feb 22 01:06:24 PM PST 24
Finished Feb 22 01:06:34 PM PST 24
Peak memory 207864 kb
Host smart-86bfe110-d788-43d9-8f96-347e79a012c8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281247689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1281247689
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1679581802
Short name T420
Test name
Test status
Simulation time 6916572453 ps
CPU time 89.8 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:07:49 PM PST 24
Peak memory 208696 kb
Host smart-dbb01106-3c8c-4d79-bc3f-972d11623d61
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679581802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1679581802
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.726699156
Short name T83
Test name
Test status
Simulation time 441330214 ps
CPU time 6.07 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:06:24 PM PST 24
Peak memory 208724 kb
Host smart-40fd65a1-9c06-41b9-af76-c0d3b3207276
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726699156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.726699156
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1727509502
Short name T389
Test name
Test status
Simulation time 231831938 ps
CPU time 3.02 seconds
Started Feb 22 01:06:18 PM PST 24
Finished Feb 22 01:06:22 PM PST 24
Peak memory 215472 kb
Host smart-916f88c5-5d57-4861-bd0d-64074825eb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727509502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1727509502
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1753008642
Short name T192
Test name
Test status
Simulation time 99695713 ps
CPU time 3.19 seconds
Started Feb 22 01:06:18 PM PST 24
Finished Feb 22 01:06:22 PM PST 24
Peak memory 208304 kb
Host smart-e06537c4-2b90-4cdb-ba8e-d38d812cee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753008642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1753008642
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.512782423
Short name T394
Test name
Test status
Simulation time 2209407799 ps
CPU time 6.35 seconds
Started Feb 22 01:06:15 PM PST 24
Finished Feb 22 01:06:24 PM PST 24
Peak memory 207276 kb
Host smart-19fd6889-9d9e-4ebf-978f-43b50d926643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512782423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.512782423
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2249121920
Short name T1043
Test name
Test status
Simulation time 9186521 ps
CPU time 0.7 seconds
Started Feb 22 01:06:47 PM PST 24
Finished Feb 22 01:06:49 PM PST 24
Peak memory 205900 kb
Host smart-8d896364-44be-4916-8b4e-abc5fb656051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249121920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2249121920
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.3471867193
Short name T425
Test name
Test status
Simulation time 139799578 ps
CPU time 7.75 seconds
Started Feb 22 01:06:50 PM PST 24
Finished Feb 22 01:07:01 PM PST 24
Peak memory 214244 kb
Host smart-2bcda67f-6473-4ddd-9c99-487ee63c3dc1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471867193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3471867193
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.4251667383
Short name T746
Test name
Test status
Simulation time 113731556 ps
CPU time 2.25 seconds
Started Feb 22 01:06:41 PM PST 24
Finished Feb 22 01:06:43 PM PST 24
Peak memory 218552 kb
Host smart-a1335d5a-f355-49c6-9975-0fd936542cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251667383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.4251667383
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3310939947
Short name T841
Test name
Test status
Simulation time 1131993022 ps
CPU time 7.53 seconds
Started Feb 22 01:06:41 PM PST 24
Finished Feb 22 01:06:49 PM PST 24
Peak memory 208320 kb
Host smart-49b111b8-6a4b-4eca-bfed-551cb08fc969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310939947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3310939947
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.4085210597
Short name T270
Test name
Test status
Simulation time 87454185 ps
CPU time 3.23 seconds
Started Feb 22 01:06:49 PM PST 24
Finished Feb 22 01:06:56 PM PST 24
Peak memory 210804 kb
Host smart-5e468296-b139-4a8c-90a1-80990db69a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085210597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.4085210597
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1144359790
Short name T904
Test name
Test status
Simulation time 257432090 ps
CPU time 2.16 seconds
Started Feb 22 01:06:47 PM PST 24
Finished Feb 22 01:06:50 PM PST 24
Peak memory 214264 kb
Host smart-2b38f129-0717-4788-b192-cac65dbdf628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144359790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1144359790
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1936103368
Short name T367
Test name
Test status
Simulation time 1582474302 ps
CPU time 10.58 seconds
Started Feb 22 01:06:39 PM PST 24
Finished Feb 22 01:06:50 PM PST 24
Peak memory 218596 kb
Host smart-c3495ed7-dc42-4e35-bd68-3cca66f8201e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936103368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1936103368
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1266191886
Short name T638
Test name
Test status
Simulation time 149113212 ps
CPU time 2.33 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:06:21 PM PST 24
Peak memory 206776 kb
Host smart-deed7071-9d07-42ae-99fa-be72aff6f9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266191886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1266191886
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.351176871
Short name T633
Test name
Test status
Simulation time 294571439 ps
CPU time 3.55 seconds
Started Feb 22 01:06:45 PM PST 24
Finished Feb 22 01:06:49 PM PST 24
Peak memory 209052 kb
Host smart-d1fb9f92-af75-4d8a-ba52-b3fc1f515abc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351176871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.351176871
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1481483794
Short name T240
Test name
Test status
Simulation time 58137738 ps
CPU time 3.06 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:06:22 PM PST 24
Peak memory 208360 kb
Host smart-5b96f162-ec35-4bbe-a58d-acff1fe47970
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481483794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1481483794
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.4058380804
Short name T719
Test name
Test status
Simulation time 1978991738 ps
CPU time 13.99 seconds
Started Feb 22 01:06:46 PM PST 24
Finished Feb 22 01:07:01 PM PST 24
Peak memory 208132 kb
Host smart-8ff40c52-cc93-4ca0-8cbe-a8586c66c066
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058380804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.4058380804
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2853103466
Short name T185
Test name
Test status
Simulation time 385836500 ps
CPU time 2.22 seconds
Started Feb 22 01:06:51 PM PST 24
Finished Feb 22 01:06:56 PM PST 24
Peak memory 214164 kb
Host smart-b22e3ebf-e2ed-43e3-8393-cf608e6bd87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853103466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2853103466
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3253993059
Short name T973
Test name
Test status
Simulation time 48575239 ps
CPU time 2.54 seconds
Started Feb 22 01:06:20 PM PST 24
Finished Feb 22 01:06:23 PM PST 24
Peak memory 208588 kb
Host smart-a7276545-5f07-4664-92b1-60351039427f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253993059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3253993059
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.1544384506
Short name T220
Test name
Test status
Simulation time 5355895878 ps
CPU time 39.09 seconds
Started Feb 22 01:06:49 PM PST 24
Finished Feb 22 01:07:32 PM PST 24
Peak memory 219800 kb
Host smart-bcd4b69b-f700-4c82-af15-8a65b51b0796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544384506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1544384506
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.632490335
Short name T72
Test name
Test status
Simulation time 210085360 ps
CPU time 12.17 seconds
Started Feb 22 01:06:49 PM PST 24
Finished Feb 22 01:07:05 PM PST 24
Peak memory 222632 kb
Host smart-edee0b5c-196b-41b2-9082-895521f17036
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632490335 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.632490335
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2610842017
Short name T765
Test name
Test status
Simulation time 544050407 ps
CPU time 6.12 seconds
Started Feb 22 01:06:48 PM PST 24
Finished Feb 22 01:06:54 PM PST 24
Peak memory 207288 kb
Host smart-6d9c0e77-a1ea-4e26-88f9-6393c68a4a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610842017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2610842017
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3258879403
Short name T570
Test name
Test status
Simulation time 30168962 ps
CPU time 1.92 seconds
Started Feb 22 01:06:42 PM PST 24
Finished Feb 22 01:06:44 PM PST 24
Peak memory 210084 kb
Host smart-96b52d59-59a5-4b3f-b941-e66787ce1ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258879403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3258879403
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3547971060
Short name T678
Test name
Test status
Simulation time 49232387 ps
CPU time 0.91 seconds
Started Feb 22 01:06:49 PM PST 24
Finished Feb 22 01:06:54 PM PST 24
Peak memory 205960 kb
Host smart-991b27b5-1df5-4a07-9dd9-4834ec647fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547971060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3547971060
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.247904955
Short name T346
Test name
Test status
Simulation time 71624201 ps
CPU time 4.7 seconds
Started Feb 22 01:06:46 PM PST 24
Finished Feb 22 01:06:53 PM PST 24
Peak memory 215340 kb
Host smart-e868ddcf-cd2f-406a-a094-1565d8311eac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=247904955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.247904955
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.966833457
Short name T847
Test name
Test status
Simulation time 306199107 ps
CPU time 3.92 seconds
Started Feb 22 01:06:51 PM PST 24
Finished Feb 22 01:06:57 PM PST 24
Peak memory 209692 kb
Host smart-c367a1de-519c-4a72-8c3a-739f47f93f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966833457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.966833457
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2917677639
Short name T614
Test name
Test status
Simulation time 176328661 ps
CPU time 2.62 seconds
Started Feb 22 01:06:45 PM PST 24
Finished Feb 22 01:06:48 PM PST 24
Peak memory 218244 kb
Host smart-88b9afb4-64f5-4822-9c4e-3b70a94e7b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917677639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2917677639
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1968495117
Short name T922
Test name
Test status
Simulation time 5427334192 ps
CPU time 56.56 seconds
Started Feb 22 01:06:50 PM PST 24
Finished Feb 22 01:07:50 PM PST 24
Peak memory 214312 kb
Host smart-d8d0b4db-ec54-4eec-9e4c-03bc4f158c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968495117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1968495117
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1691296211
Short name T180
Test name
Test status
Simulation time 193634673 ps
CPU time 7.65 seconds
Started Feb 22 01:06:51 PM PST 24
Finished Feb 22 01:07:01 PM PST 24
Peak memory 210900 kb
Host smart-19b54d07-4328-4ac2-a80e-d610ed2ed8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691296211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1691296211
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1701874926
Short name T703
Test name
Test status
Simulation time 92358818 ps
CPU time 2.91 seconds
Started Feb 22 01:06:47 PM PST 24
Finished Feb 22 01:06:51 PM PST 24
Peak memory 206116 kb
Host smart-1b761be7-83ad-49d8-9f2a-6d621f85e0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701874926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1701874926
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1045687519
Short name T608
Test name
Test status
Simulation time 1713955669 ps
CPU time 5.04 seconds
Started Feb 22 01:06:46 PM PST 24
Finished Feb 22 01:06:51 PM PST 24
Peak memory 207416 kb
Host smart-193268da-d801-468c-8a58-527ba894e579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045687519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1045687519
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2040176146
Short name T295
Test name
Test status
Simulation time 146548183 ps
CPU time 2.66 seconds
Started Feb 22 01:06:49 PM PST 24
Finished Feb 22 01:06:56 PM PST 24
Peak memory 207436 kb
Host smart-523878ab-7249-4e64-b9ab-afdd22fdb7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040176146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2040176146
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.951151680
Short name T747
Test name
Test status
Simulation time 102716393 ps
CPU time 2.8 seconds
Started Feb 22 01:06:46 PM PST 24
Finished Feb 22 01:06:51 PM PST 24
Peak memory 208396 kb
Host smart-784c3998-67a9-403f-afc8-d62ac8b54351
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951151680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.951151680
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2152472885
Short name T906
Test name
Test status
Simulation time 197100172 ps
CPU time 2.14 seconds
Started Feb 22 01:06:49 PM PST 24
Finished Feb 22 01:06:55 PM PST 24
Peak memory 208664 kb
Host smart-9e7c9c9e-9bcc-47ea-acf3-6f0b7b946873
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152472885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2152472885
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1133937719
Short name T826
Test name
Test status
Simulation time 843634032 ps
CPU time 22.83 seconds
Started Feb 22 01:06:44 PM PST 24
Finished Feb 22 01:07:07 PM PST 24
Peak memory 208552 kb
Host smart-eb00ea74-21c3-43b7-9e0f-49e788654d17
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133937719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1133937719
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3745832815
Short name T710
Test name
Test status
Simulation time 134031279 ps
CPU time 3.76 seconds
Started Feb 22 01:06:50 PM PST 24
Finished Feb 22 01:06:57 PM PST 24
Peak memory 208664 kb
Host smart-7a7ebd70-7075-4405-9d0e-0da310270ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745832815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3745832815
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1508876331
Short name T811
Test name
Test status
Simulation time 38521221 ps
CPU time 2.35 seconds
Started Feb 22 01:06:46 PM PST 24
Finished Feb 22 01:06:49 PM PST 24
Peak memory 207180 kb
Host smart-c27f7a6a-1714-4daa-8b2d-071fae19b596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508876331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1508876331
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.3820474991
Short name T430
Test name
Test status
Simulation time 860743974 ps
CPU time 4.19 seconds
Started Feb 22 01:06:51 PM PST 24
Finished Feb 22 01:06:58 PM PST 24
Peak memory 222592 kb
Host smart-877892d5-677d-45d1-a493-9330fca0611e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820474991 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.3820474991
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.4095403178
Short name T685
Test name
Test status
Simulation time 54151836 ps
CPU time 3.63 seconds
Started Feb 22 01:06:47 PM PST 24
Finished Feb 22 01:06:52 PM PST 24
Peak memory 210204 kb
Host smart-86a07e34-1e3d-4239-a77b-c9fbff8cb133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095403178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.4095403178
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3964070894
Short name T77
Test name
Test status
Simulation time 521101175 ps
CPU time 3.85 seconds
Started Feb 22 01:06:47 PM PST 24
Finished Feb 22 01:06:52 PM PST 24
Peak memory 210396 kb
Host smart-2dbec39b-6b4e-4fa8-8d5b-4c2a5e47be6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964070894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3964070894
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.768885527
Short name T581
Test name
Test status
Simulation time 39392737 ps
CPU time 0.81 seconds
Started Feb 22 01:06:49 PM PST 24
Finished Feb 22 01:06:54 PM PST 24
Peak memory 205828 kb
Host smart-83028245-5e18-4293-b65e-8bb7536c0b8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768885527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.768885527
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1421504374
Short name T909
Test name
Test status
Simulation time 59589735 ps
CPU time 2.73 seconds
Started Feb 22 01:06:54 PM PST 24
Finished Feb 22 01:06:57 PM PST 24
Peak memory 208688 kb
Host smart-1c83fc6a-1ed1-46f4-8f57-6045170bbaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421504374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1421504374
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.432384166
Short name T791
Test name
Test status
Simulation time 251781966 ps
CPU time 3.58 seconds
Started Feb 22 01:06:51 PM PST 24
Finished Feb 22 01:06:57 PM PST 24
Peak memory 207900 kb
Host smart-f36d2ef9-38af-4289-a877-15eb4a531baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432384166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.432384166
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.4121499744
Short name T1033
Test name
Test status
Simulation time 100916518 ps
CPU time 4.19 seconds
Started Feb 22 01:06:51 PM PST 24
Finished Feb 22 01:06:58 PM PST 24
Peak memory 216820 kb
Host smart-ce04d663-d908-44c4-a7a8-5e8219e1838b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121499744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.4121499744
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.4234070998
Short name T693
Test name
Test status
Simulation time 69997619 ps
CPU time 4.14 seconds
Started Feb 22 01:06:53 PM PST 24
Finished Feb 22 01:06:58 PM PST 24
Peak memory 219796 kb
Host smart-631e7a9f-2f39-454d-a469-69c7cb2ba6ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234070998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4234070998
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1233479781
Short name T802
Test name
Test status
Simulation time 56928495 ps
CPU time 3.04 seconds
Started Feb 22 01:06:50 PM PST 24
Finished Feb 22 01:06:56 PM PST 24
Peak memory 206812 kb
Host smart-63d216e5-0a92-4102-b867-e4b4396c1dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233479781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1233479781
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1426420752
Short name T907
Test name
Test status
Simulation time 348433548 ps
CPU time 2.73 seconds
Started Feb 22 01:06:47 PM PST 24
Finished Feb 22 01:06:51 PM PST 24
Peak memory 206968 kb
Host smart-0f05ccc2-abe2-44ad-9362-5ab127c22e6b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426420752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1426420752
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3596788411
Short name T173
Test name
Test status
Simulation time 452784066 ps
CPU time 15.64 seconds
Started Feb 22 01:06:53 PM PST 24
Finished Feb 22 01:07:10 PM PST 24
Peak memory 208616 kb
Host smart-29974cf1-e84a-44ff-a222-04879b8395c8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596788411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3596788411
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1344353429
Short name T1057
Test name
Test status
Simulation time 208165165 ps
CPU time 5.85 seconds
Started Feb 22 01:06:53 PM PST 24
Finished Feb 22 01:07:00 PM PST 24
Peak memory 208528 kb
Host smart-b4353f81-7c65-42e4-b968-3c8d301659de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344353429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1344353429
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.468433019
Short name T242
Test name
Test status
Simulation time 511318344 ps
CPU time 4.78 seconds
Started Feb 22 01:06:51 PM PST 24
Finished Feb 22 01:06:58 PM PST 24
Peak memory 222276 kb
Host smart-937b9cc4-8f0f-406e-b49e-05da026ceabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468433019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.468433019
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2362748800
Short name T1061
Test name
Test status
Simulation time 8388911126 ps
CPU time 36.54 seconds
Started Feb 22 01:06:51 PM PST 24
Finished Feb 22 01:07:30 PM PST 24
Peak memory 208368 kb
Host smart-37fadaf8-0d9c-4530-bc00-b79db5d095cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362748800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2362748800
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2155030540
Short name T670
Test name
Test status
Simulation time 118680430 ps
CPU time 5.66 seconds
Started Feb 22 01:06:52 PM PST 24
Finished Feb 22 01:06:59 PM PST 24
Peak memory 209496 kb
Host smart-0999099a-8f85-434f-bd34-6e995f5810e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155030540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2155030540
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.980748507
Short name T649
Test name
Test status
Simulation time 192293580 ps
CPU time 7.28 seconds
Started Feb 22 01:06:51 PM PST 24
Finished Feb 22 01:07:01 PM PST 24
Peak memory 210444 kb
Host smart-37ac8501-4f82-4587-95ce-f6a0939d3e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980748507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.980748507
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3500752911
Short name T589
Test name
Test status
Simulation time 42204361 ps
CPU time 1.01 seconds
Started Feb 22 01:06:49 PM PST 24
Finished Feb 22 01:06:54 PM PST 24
Peak memory 205916 kb
Host smart-e07361c5-075b-4e4a-bd67-0839c3da0a09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500752911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3500752911
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2649620013
Short name T245
Test name
Test status
Simulation time 242451075 ps
CPU time 13.23 seconds
Started Feb 22 01:06:52 PM PST 24
Finished Feb 22 01:07:07 PM PST 24
Peak memory 214284 kb
Host smart-9cb39103-1e83-46e3-b047-57bb1b916634
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2649620013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2649620013
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1817751733
Short name T631
Test name
Test status
Simulation time 43843763 ps
CPU time 2.23 seconds
Started Feb 22 01:06:53 PM PST 24
Finished Feb 22 01:06:56 PM PST 24
Peak memory 208084 kb
Host smart-3b2cf635-0631-47b8-96f6-bb9c35647213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817751733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1817751733
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3738882653
Short name T640
Test name
Test status
Simulation time 1292107880 ps
CPU time 23.87 seconds
Started Feb 22 01:06:49 PM PST 24
Finished Feb 22 01:07:17 PM PST 24
Peak memory 214304 kb
Host smart-ebb94688-d51b-4b65-bdf6-dbfef39ea18b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738882653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3738882653
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1915004232
Short name T272
Test name
Test status
Simulation time 213133206 ps
CPU time 3.2 seconds
Started Feb 22 01:06:53 PM PST 24
Finished Feb 22 01:06:57 PM PST 24
Peak memory 214372 kb
Host smart-9ba93aea-105a-4f5a-8d73-8c8621a706d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915004232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1915004232
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.40537098
Short name T753
Test name
Test status
Simulation time 79626779 ps
CPU time 3.99 seconds
Started Feb 22 01:06:53 PM PST 24
Finished Feb 22 01:06:58 PM PST 24
Peak memory 209292 kb
Host smart-30b22e72-58ab-44a4-8af6-2603f7699c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40537098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.40537098
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2660733434
Short name T725
Test name
Test status
Simulation time 27976315749 ps
CPU time 81.42 seconds
Started Feb 22 01:06:53 PM PST 24
Finished Feb 22 01:08:16 PM PST 24
Peak memory 218304 kb
Host smart-88f0a80f-43c8-46bf-8095-1fdc1c5ebf81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660733434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2660733434
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1064390512
Short name T810
Test name
Test status
Simulation time 463098355 ps
CPU time 5.01 seconds
Started Feb 22 01:06:53 PM PST 24
Finished Feb 22 01:06:59 PM PST 24
Peak memory 206604 kb
Host smart-dd0bcb0f-67c7-444e-9b44-2c5f94d07d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064390512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1064390512
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2943741613
Short name T1016
Test name
Test status
Simulation time 2266866720 ps
CPU time 66.13 seconds
Started Feb 22 01:06:51 PM PST 24
Finished Feb 22 01:07:59 PM PST 24
Peak memory 208516 kb
Host smart-dceb862c-3e7c-4a1c-9d8b-9f175a1a804f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943741613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2943741613
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1735750720
Short name T873
Test name
Test status
Simulation time 68840398 ps
CPU time 3.01 seconds
Started Feb 22 01:06:53 PM PST 24
Finished Feb 22 01:06:57 PM PST 24
Peak memory 206752 kb
Host smart-284f827f-2899-47d8-9c04-ca01c587428e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735750720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1735750720
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1013723435
Short name T754
Test name
Test status
Simulation time 199318711 ps
CPU time 2.64 seconds
Started Feb 22 01:06:44 PM PST 24
Finished Feb 22 01:06:47 PM PST 24
Peak memory 209608 kb
Host smart-8f95bf8d-af32-4f27-b3bf-56dfd219b99f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013723435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1013723435
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.534506942
Short name T925
Test name
Test status
Simulation time 55266038 ps
CPU time 2.77 seconds
Started Feb 22 01:06:52 PM PST 24
Finished Feb 22 01:06:56 PM PST 24
Peak memory 206640 kb
Host smart-84aa5e3a-5369-407f-900e-78d3fa2b8608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534506942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.534506942
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.4029119107
Short name T880
Test name
Test status
Simulation time 1593305317 ps
CPU time 21.83 seconds
Started Feb 22 01:06:48 PM PST 24
Finished Feb 22 01:07:10 PM PST 24
Peak memory 216000 kb
Host smart-c06f8ecf-740b-4282-8521-92bdefd56228
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029119107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.4029119107
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.914873958
Short name T1021
Test name
Test status
Simulation time 182741992 ps
CPU time 2.56 seconds
Started Feb 22 01:07:08 PM PST 24
Finished Feb 22 01:07:11 PM PST 24
Peak memory 219876 kb
Host smart-5c70ddae-b7ce-4f26-b803-3b91a15c48f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914873958 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.914873958
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3840952278
Short name T731
Test name
Test status
Simulation time 114076460 ps
CPU time 3.54 seconds
Started Feb 22 01:06:53 PM PST 24
Finished Feb 22 01:06:58 PM PST 24
Peak memory 207688 kb
Host smart-e98cb006-b339-4ea6-9301-44c0ae58ea16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840952278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3840952278
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2700802172
Short name T748
Test name
Test status
Simulation time 321924074 ps
CPU time 1.35 seconds
Started Feb 22 01:06:46 PM PST 24
Finished Feb 22 01:06:49 PM PST 24
Peak memory 209728 kb
Host smart-688208c8-bbf0-406e-8e9f-ba7a19198e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700802172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2700802172
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1569823539
Short name T612
Test name
Test status
Simulation time 53626635 ps
CPU time 0.76 seconds
Started Feb 22 01:07:02 PM PST 24
Finished Feb 22 01:07:03 PM PST 24
Peak memory 205780 kb
Host smart-b66c0546-c662-40b3-8a73-8ff771036fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569823539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1569823539
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.155670275
Short name T29
Test name
Test status
Simulation time 779053658 ps
CPU time 5.17 seconds
Started Feb 22 01:07:10 PM PST 24
Finished Feb 22 01:07:16 PM PST 24
Peak memory 210120 kb
Host smart-73ac2571-e7c6-4044-9027-5703e1ec93ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155670275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.155670275
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2913375301
Short name T322
Test name
Test status
Simulation time 24421104 ps
CPU time 1.93 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:09 PM PST 24
Peak memory 207284 kb
Host smart-ce8aa51d-0f5d-4215-a0c0-004107b217b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913375301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2913375301
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3982255116
Short name T92
Test name
Test status
Simulation time 138699584 ps
CPU time 4.31 seconds
Started Feb 22 01:07:03 PM PST 24
Finished Feb 22 01:07:08 PM PST 24
Peak memory 220080 kb
Host smart-31598306-ed7c-4a6c-be07-aeb5e1e38f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982255116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3982255116
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1329750490
Short name T827
Test name
Test status
Simulation time 94329562 ps
CPU time 4.73 seconds
Started Feb 22 01:06:59 PM PST 24
Finished Feb 22 01:07:05 PM PST 24
Peak memory 214252 kb
Host smart-3c30d8bb-6e17-402e-8cec-f2175f896da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329750490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1329750490
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1011414014
Short name T223
Test name
Test status
Simulation time 82829710 ps
CPU time 3.55 seconds
Started Feb 22 01:07:04 PM PST 24
Finished Feb 22 01:07:08 PM PST 24
Peak memory 220328 kb
Host smart-f09c191a-1368-4e17-bf50-b7a95567cfc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011414014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1011414014
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3520863145
Short name T780
Test name
Test status
Simulation time 209718426 ps
CPU time 3 seconds
Started Feb 22 01:07:05 PM PST 24
Finished Feb 22 01:07:08 PM PST 24
Peak memory 208156 kb
Host smart-39ca1f99-cbe0-48fb-9114-bf3458a40340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520863145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3520863145
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1477816168
Short name T872
Test name
Test status
Simulation time 4276551079 ps
CPU time 59.78 seconds
Started Feb 22 01:07:00 PM PST 24
Finished Feb 22 01:08:01 PM PST 24
Peak memory 209048 kb
Host smart-94ddd024-a96c-49ef-87ac-6fbd5bb88523
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477816168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1477816168
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1302048675
Short name T325
Test name
Test status
Simulation time 1126042812 ps
CPU time 31.08 seconds
Started Feb 22 01:07:05 PM PST 24
Finished Feb 22 01:07:36 PM PST 24
Peak memory 208816 kb
Host smart-f866b479-b244-4a0e-a90e-d35a3f1b44b2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302048675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1302048675
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3934422176
Short name T593
Test name
Test status
Simulation time 187775128 ps
CPU time 3.85 seconds
Started Feb 22 01:07:08 PM PST 24
Finished Feb 22 01:07:12 PM PST 24
Peak memory 215164 kb
Host smart-fcaa34d6-8b3c-4d4c-a91f-669a1237bcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934422176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3934422176
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3141163782
Short name T575
Test name
Test status
Simulation time 3570003154 ps
CPU time 12.07 seconds
Started Feb 22 01:06:46 PM PST 24
Finished Feb 22 01:07:00 PM PST 24
Peak memory 208568 kb
Host smart-1c3a2cbd-9c3c-4bac-98da-c9053a841dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141163782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3141163782
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2426907256
Short name T326
Test name
Test status
Simulation time 1142645369 ps
CPU time 22.23 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:35 PM PST 24
Peak memory 222548 kb
Host smart-1519ceb3-b586-4e57-8d8e-766ec90d7467
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426907256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2426907256
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.2915453793
Short name T673
Test name
Test status
Simulation time 660916355 ps
CPU time 6.63 seconds
Started Feb 22 01:07:04 PM PST 24
Finished Feb 22 01:07:12 PM PST 24
Peak memory 222660 kb
Host smart-eed8daf4-354e-4a96-8382-08b6ab35ea87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915453793 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.2915453793
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3354457315
Short name T675
Test name
Test status
Simulation time 782390557 ps
CPU time 4.04 seconds
Started Feb 22 01:07:00 PM PST 24
Finished Feb 22 01:07:05 PM PST 24
Peak memory 207604 kb
Host smart-3112fea6-1868-49fc-a95d-001ea2a4c01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354457315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3354457315
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.270533719
Short name T652
Test name
Test status
Simulation time 13804654 ps
CPU time 0.72 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:09 PM PST 24
Peak memory 205800 kb
Host smart-164cf255-3f58-4957-b6b6-08baff2c2a1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270533719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.270533719
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2247459077
Short name T66
Test name
Test status
Simulation time 886792293 ps
CPU time 18.1 seconds
Started Feb 22 01:07:10 PM PST 24
Finished Feb 22 01:07:29 PM PST 24
Peak memory 222780 kb
Host smart-1b147767-4483-459c-82d2-3d725166f955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247459077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2247459077
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1150250565
Short name T874
Test name
Test status
Simulation time 36437593 ps
CPU time 1.73 seconds
Started Feb 22 01:07:09 PM PST 24
Finished Feb 22 01:07:13 PM PST 24
Peak memory 207460 kb
Host smart-bbe540fd-b10f-4124-ba0d-4643b823ad0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150250565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1150250565
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3248623849
Short name T255
Test name
Test status
Simulation time 2252328623 ps
CPU time 27.35 seconds
Started Feb 22 01:07:09 PM PST 24
Finished Feb 22 01:07:38 PM PST 24
Peak memory 214352 kb
Host smart-01720944-90b1-4fbd-83a0-26ddc35f5103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248623849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3248623849
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3484644496
Short name T428
Test name
Test status
Simulation time 62349255 ps
CPU time 2.85 seconds
Started Feb 22 01:07:03 PM PST 24
Finished Feb 22 01:07:06 PM PST 24
Peak memory 209908 kb
Host smart-abe87ffd-e72c-4580-acd6-308b7347301c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484644496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3484644496
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.200382904
Short name T244
Test name
Test status
Simulation time 134651602 ps
CPU time 6.38 seconds
Started Feb 22 01:07:04 PM PST 24
Finished Feb 22 01:07:12 PM PST 24
Peak memory 218476 kb
Host smart-b795b9aa-8909-4b77-aa7f-f9d75a256963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200382904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.200382904
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.641120505
Short name T817
Test name
Test status
Simulation time 280296306 ps
CPU time 4.04 seconds
Started Feb 22 01:07:11 PM PST 24
Finished Feb 22 01:07:16 PM PST 24
Peak memory 206736 kb
Host smart-b9ee030d-35b7-4999-a130-43a7c7699354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641120505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.641120505
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.466487101
Short name T203
Test name
Test status
Simulation time 86933570 ps
CPU time 2.48 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:10 PM PST 24
Peak memory 208216 kb
Host smart-3ce71b92-d063-4cd8-bbb6-b75a06bd08f9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466487101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.466487101
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3515052945
Short name T1020
Test name
Test status
Simulation time 3204680716 ps
CPU time 59.9 seconds
Started Feb 22 01:07:00 PM PST 24
Finished Feb 22 01:08:01 PM PST 24
Peak memory 207872 kb
Host smart-b71070c6-5ea8-4366-80c2-6fbbe8b6228b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515052945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3515052945
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1784311263
Short name T724
Test name
Test status
Simulation time 20792017 ps
CPU time 1.85 seconds
Started Feb 22 01:07:04 PM PST 24
Finished Feb 22 01:07:06 PM PST 24
Peak memory 206896 kb
Host smart-c8da0b4c-eb95-4423-a3e6-71b663139b6c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784311263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1784311263
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3277262672
Short name T716
Test name
Test status
Simulation time 30989020 ps
CPU time 1.93 seconds
Started Feb 22 01:07:08 PM PST 24
Finished Feb 22 01:07:11 PM PST 24
Peak memory 217796 kb
Host smart-a282178d-4e42-42a2-9f12-ca7af9cff769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277262672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3277262672
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1712914714
Short name T609
Test name
Test status
Simulation time 237503518 ps
CPU time 3.18 seconds
Started Feb 22 01:07:04 PM PST 24
Finished Feb 22 01:07:08 PM PST 24
Peak memory 206632 kb
Host smart-18c8a338-a9ce-453f-8344-a28fbef0fc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712914714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1712914714
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.166825161
Short name T1049
Test name
Test status
Simulation time 520665047 ps
CPU time 11.33 seconds
Started Feb 22 01:07:09 PM PST 24
Finished Feb 22 01:07:22 PM PST 24
Peak memory 222616 kb
Host smart-be0df9d1-3d44-4427-b5e7-578c279b0dcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166825161 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.166825161
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.4751879
Short name T787
Test name
Test status
Simulation time 457970079 ps
CPU time 4.71 seconds
Started Feb 22 01:07:11 PM PST 24
Finished Feb 22 01:07:16 PM PST 24
Peak memory 208280 kb
Host smart-83f08d57-8934-4b12-995b-cb0b58fa6037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4751879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.4751879
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.4222226305
Short name T891
Test name
Test status
Simulation time 180362077 ps
CPU time 2.46 seconds
Started Feb 22 01:07:11 PM PST 24
Finished Feb 22 01:07:15 PM PST 24
Peak memory 210076 kb
Host smart-068328ca-620c-4530-8e56-54700ba50621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222226305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.4222226305
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2082228513
Short name T733
Test name
Test status
Simulation time 21144136 ps
CPU time 0.74 seconds
Started Feb 22 01:07:04 PM PST 24
Finished Feb 22 01:07:06 PM PST 24
Peak memory 205736 kb
Host smart-5da638cb-3906-4754-99bb-ef7185831250
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082228513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2082228513
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2084890262
Short name T628
Test name
Test status
Simulation time 1492428627 ps
CPU time 7.07 seconds
Started Feb 22 01:07:10 PM PST 24
Finished Feb 22 01:07:18 PM PST 24
Peak memory 209220 kb
Host smart-b2c4003d-317a-48f1-be9d-7624f3f0fcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084890262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2084890262
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3236780281
Short name T49
Test name
Test status
Simulation time 109038745 ps
CPU time 4.77 seconds
Started Feb 22 01:07:10 PM PST 24
Finished Feb 22 01:07:16 PM PST 24
Peak memory 217852 kb
Host smart-30303647-124d-4cd3-a6b2-98251d3eaeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236780281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3236780281
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1087135266
Short name T766
Test name
Test status
Simulation time 347965345 ps
CPU time 4.44 seconds
Started Feb 22 01:07:11 PM PST 24
Finished Feb 22 01:07:17 PM PST 24
Peak memory 208976 kb
Host smart-b4599122-aa28-4af1-a3b3-3fd0998fcc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087135266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1087135266
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1610014399
Short name T613
Test name
Test status
Simulation time 151256135 ps
CPU time 3.35 seconds
Started Feb 22 01:07:10 PM PST 24
Finished Feb 22 01:07:15 PM PST 24
Peak memory 208760 kb
Host smart-b8678264-5fb1-4294-92ca-fe07fb78b1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610014399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1610014399
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.781219477
Short name T629
Test name
Test status
Simulation time 267481618 ps
CPU time 3.19 seconds
Started Feb 22 01:07:08 PM PST 24
Finished Feb 22 01:07:12 PM PST 24
Peak memory 206888 kb
Host smart-ca81a57a-a982-48f6-a53f-a9ba07f63580
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781219477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.781219477
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.530972795
Short name T318
Test name
Test status
Simulation time 146925465 ps
CPU time 2.68 seconds
Started Feb 22 01:07:10 PM PST 24
Finished Feb 22 01:07:14 PM PST 24
Peak memory 208392 kb
Host smart-6dfaf9ba-4ac0-4dda-8a24-c46ef8b51a14
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530972795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.530972795
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.877155720
Short name T689
Test name
Test status
Simulation time 166138421 ps
CPU time 4.96 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:18 PM PST 24
Peak memory 208632 kb
Host smart-2795e37b-3a8e-4719-97ce-d45d3dd0985c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877155720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.877155720
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.819713184
Short name T1027
Test name
Test status
Simulation time 144914417 ps
CPU time 3.75 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:17 PM PST 24
Peak memory 208324 kb
Host smart-1500e1da-0a84-45e7-9558-1b9243c195a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819713184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.819713184
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2368637662
Short name T961
Test name
Test status
Simulation time 952479768 ps
CPU time 6.73 seconds
Started Feb 22 01:07:11 PM PST 24
Finished Feb 22 01:07:18 PM PST 24
Peak memory 206816 kb
Host smart-9290e998-0849-4f7d-aafb-04c38bd96b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368637662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2368637662
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3530734128
Short name T303
Test name
Test status
Simulation time 620854190 ps
CPU time 20.46 seconds
Started Feb 22 01:07:01 PM PST 24
Finished Feb 22 01:07:22 PM PST 24
Peak memory 215624 kb
Host smart-649725be-4cc0-4d4b-b2bd-95010c3882fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530734128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3530734128
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3016320704
Short name T786
Test name
Test status
Simulation time 1143831596 ps
CPU time 8.06 seconds
Started Feb 22 01:07:11 PM PST 24
Finished Feb 22 01:07:20 PM PST 24
Peak memory 208768 kb
Host smart-a73f870d-e0ca-41d9-a749-c3e798bfbb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3016320704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3016320704
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.395963934
Short name T579
Test name
Test status
Simulation time 151477926 ps
CPU time 4.79 seconds
Started Feb 22 01:07:05 PM PST 24
Finished Feb 22 01:07:10 PM PST 24
Peak memory 210604 kb
Host smart-bc7a4fae-d0e0-41bf-b3ac-25dd20cdf0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395963934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.395963934
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.4082342974
Short name T684
Test name
Test status
Simulation time 106756869 ps
CPU time 0.96 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:14 PM PST 24
Peak memory 206024 kb
Host smart-e3e5232c-fe50-4200-9f17-62ba11dc2594
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082342974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.4082342974
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1349434096
Short name T267
Test name
Test status
Simulation time 320577516 ps
CPU time 4.06 seconds
Started Feb 22 01:07:03 PM PST 24
Finished Feb 22 01:07:07 PM PST 24
Peak memory 218372 kb
Host smart-19822fe6-6df2-4d45-91a2-2b94ab7b0886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349434096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1349434096
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.898614877
Short name T94
Test name
Test status
Simulation time 335352685 ps
CPU time 4.28 seconds
Started Feb 22 01:07:09 PM PST 24
Finished Feb 22 01:07:15 PM PST 24
Peak memory 208824 kb
Host smart-96b8d0f1-42e8-48b8-9209-59dac29a176c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898614877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.898614877
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.4162108294
Short name T946
Test name
Test status
Simulation time 61120005 ps
CPU time 4.19 seconds
Started Feb 22 01:07:01 PM PST 24
Finished Feb 22 01:07:06 PM PST 24
Peak memory 219660 kb
Host smart-1b70cf64-dcb6-4d21-9d73-47cf693a972f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162108294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4162108294
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2073402059
Short name T409
Test name
Test status
Simulation time 499977721 ps
CPU time 3.52 seconds
Started Feb 22 01:07:08 PM PST 24
Finished Feb 22 01:07:12 PM PST 24
Peak memory 218452 kb
Host smart-2d81dd69-0b10-4ee9-8eae-fd90e173ab20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073402059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2073402059
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3412139530
Short name T243
Test name
Test status
Simulation time 535023013 ps
CPU time 4.58 seconds
Started Feb 22 01:07:15 PM PST 24
Finished Feb 22 01:07:20 PM PST 24
Peak memory 206760 kb
Host smart-6a1afc01-1c5a-4c4a-a324-f46c1a07379e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412139530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3412139530
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3253257889
Short name T965
Test name
Test status
Simulation time 43529603 ps
CPU time 2.05 seconds
Started Feb 22 01:07:02 PM PST 24
Finished Feb 22 01:07:04 PM PST 24
Peak memory 208592 kb
Host smart-88d76048-dec8-4b0c-aebb-990e12e502cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253257889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3253257889
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2935414896
Short name T888
Test name
Test status
Simulation time 307876244 ps
CPU time 4.83 seconds
Started Feb 22 01:07:04 PM PST 24
Finished Feb 22 01:07:09 PM PST 24
Peak memory 206892 kb
Host smart-44f14d13-94e7-45dc-975d-f494341631a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935414896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2935414896
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.4134686799
Short name T836
Test name
Test status
Simulation time 885863686 ps
CPU time 9.1 seconds
Started Feb 22 01:07:08 PM PST 24
Finished Feb 22 01:07:17 PM PST 24
Peak memory 207980 kb
Host smart-f66963fa-dca6-4043-a550-3cf1318e7540
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134686799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.4134686799
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2153508959
Short name T84
Test name
Test status
Simulation time 79841391 ps
CPU time 1.83 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:09 PM PST 24
Peak memory 215396 kb
Host smart-fdcc3434-99bd-4dd0-88c1-8e281e0d9e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153508959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2153508959
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3527843870
Short name T576
Test name
Test status
Simulation time 535498100 ps
CPU time 5.52 seconds
Started Feb 22 01:07:03 PM PST 24
Finished Feb 22 01:07:09 PM PST 24
Peak memory 208000 kb
Host smart-6ba8d440-fbab-4045-a1af-e411bdffab0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527843870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3527843870
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.4291624981
Short name T960
Test name
Test status
Simulation time 664259462 ps
CPU time 3.62 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:11 PM PST 24
Peak memory 218504 kb
Host smart-e67dcd4a-d592-41c8-b387-bb91cce56c47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291624981 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.4291624981
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3112890817
Short name T737
Test name
Test status
Simulation time 83155090 ps
CPU time 3.77 seconds
Started Feb 22 01:07:06 PM PST 24
Finished Feb 22 01:07:10 PM PST 24
Peak memory 207860 kb
Host smart-3488bc70-26a1-49a2-8c1a-93a9c31e5fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112890817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3112890817
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2374521496
Short name T421
Test name
Test status
Simulation time 1942972656 ps
CPU time 16.37 seconds
Started Feb 22 01:07:04 PM PST 24
Finished Feb 22 01:07:22 PM PST 24
Peak memory 210504 kb
Host smart-12339b6f-b1f1-47bb-85fd-936f85abd382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374521496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2374521496
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3806284895
Short name T896
Test name
Test status
Simulation time 16325891 ps
CPU time 0.77 seconds
Started Feb 22 01:05:54 PM PST 24
Finished Feb 22 01:05:55 PM PST 24
Peak memory 205840 kb
Host smart-2bbaec87-ba5f-4860-a5a2-0525e53da264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806284895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3806284895
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.18461933
Short name T230
Test name
Test status
Simulation time 563079906 ps
CPU time 14.89 seconds
Started Feb 22 01:05:35 PM PST 24
Finished Feb 22 01:05:51 PM PST 24
Peak memory 214316 kb
Host smart-899b327c-0d04-41c1-a28e-22ff21ec2650
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=18461933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.18461933
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3402315887
Short name T1062
Test name
Test status
Simulation time 1222447585 ps
CPU time 14.54 seconds
Started Feb 22 01:05:31 PM PST 24
Finished Feb 22 01:05:46 PM PST 24
Peak memory 209992 kb
Host smart-08cba945-270a-47fb-9c9d-8bfd9545a79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402315887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3402315887
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.500062370
Short name T314
Test name
Test status
Simulation time 177188098 ps
CPU time 3.16 seconds
Started Feb 22 01:05:32 PM PST 24
Finished Feb 22 01:05:35 PM PST 24
Peak memory 220524 kb
Host smart-89bc1481-b20e-417f-ad10-e91a494c85d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500062370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.500062370
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2855019605
Short name T247
Test name
Test status
Simulation time 880083004 ps
CPU time 8.18 seconds
Started Feb 22 01:05:34 PM PST 24
Finished Feb 22 01:05:42 PM PST 24
Peak memory 222620 kb
Host smart-35d848b8-6516-44bd-9e11-bb7ef92b9f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855019605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2855019605
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1003085190
Short name T1036
Test name
Test status
Simulation time 87727549 ps
CPU time 2.64 seconds
Started Feb 22 01:05:36 PM PST 24
Finished Feb 22 01:05:38 PM PST 24
Peak memory 220068 kb
Host smart-5744eb47-3a0c-4040-8561-a71fe73414f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003085190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1003085190
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3062875094
Short name T348
Test name
Test status
Simulation time 54069954 ps
CPU time 3.53 seconds
Started Feb 22 01:05:42 PM PST 24
Finished Feb 22 01:05:46 PM PST 24
Peak memory 207080 kb
Host smart-9b899f76-c713-49bf-9ed2-ea705527c713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062875094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3062875094
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1492724566
Short name T103
Test name
Test status
Simulation time 1276640388 ps
CPU time 22.51 seconds
Started Feb 22 01:05:57 PM PST 24
Finished Feb 22 01:06:20 PM PST 24
Peak memory 242568 kb
Host smart-e9e8a9fa-1a18-4015-82ee-4281d4ade3a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492724566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1492724566
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3688200825
Short name T1010
Test name
Test status
Simulation time 49456133 ps
CPU time 2.65 seconds
Started Feb 22 01:05:32 PM PST 24
Finished Feb 22 01:05:35 PM PST 24
Peak memory 206800 kb
Host smart-4e1425d3-0969-4eca-b30f-a027af223826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688200825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3688200825
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2223802024
Short name T681
Test name
Test status
Simulation time 63638923 ps
CPU time 3.32 seconds
Started Feb 22 01:05:34 PM PST 24
Finished Feb 22 01:05:37 PM PST 24
Peak memory 207128 kb
Host smart-9303216a-43c9-4233-8432-6e23ac524a85
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223802024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2223802024
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.195039243
Short name T419
Test name
Test status
Simulation time 551115300 ps
CPU time 4.26 seconds
Started Feb 22 01:05:33 PM PST 24
Finished Feb 22 01:05:37 PM PST 24
Peak memory 208948 kb
Host smart-cc9daa51-1abd-4f1d-ba69-e9bb2a17d884
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195039243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.195039243
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3284900445
Short name T691
Test name
Test status
Simulation time 3287527369 ps
CPU time 9.31 seconds
Started Feb 22 01:05:27 PM PST 24
Finished Feb 22 01:05:37 PM PST 24
Peak memory 208044 kb
Host smart-9230ff01-c910-41fe-996c-970ed380e4e0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284900445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3284900445
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.487357799
Short name T1067
Test name
Test status
Simulation time 224971515 ps
CPU time 3.05 seconds
Started Feb 22 01:05:34 PM PST 24
Finished Feb 22 01:05:37 PM PST 24
Peak memory 209148 kb
Host smart-40936e46-e089-4a63-8389-f172e386d194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487357799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.487357799
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1288393440
Short name T667
Test name
Test status
Simulation time 65478843 ps
CPU time 2.98 seconds
Started Feb 22 01:05:41 PM PST 24
Finished Feb 22 01:05:45 PM PST 24
Peak memory 206636 kb
Host smart-187828cc-99ac-4c63-b488-8866fbf78020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288393440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1288393440
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.248947868
Short name T577
Test name
Test status
Simulation time 139770996 ps
CPU time 5.66 seconds
Started Feb 22 01:05:51 PM PST 24
Finished Feb 22 01:05:57 PM PST 24
Peak memory 219672 kb
Host smart-d6451ba1-4f88-4d09-ad22-2fae26483fc4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248947868 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.248947868
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3726635098
Short name T391
Test name
Test status
Simulation time 38530303 ps
CPU time 2.43 seconds
Started Feb 22 01:05:42 PM PST 24
Finished Feb 22 01:05:45 PM PST 24
Peak memory 208020 kb
Host smart-08e4af2d-217f-4a45-898c-5a0cf206d87c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726635098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3726635098
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2097952536
Short name T406
Test name
Test status
Simulation time 79477284 ps
CPU time 2.94 seconds
Started Feb 22 01:05:41 PM PST 24
Finished Feb 22 01:05:45 PM PST 24
Peak memory 210236 kb
Host smart-e030d11c-ee9f-4e74-a9b8-93bc5fc20fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097952536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2097952536
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.25017532
Short name T634
Test name
Test status
Simulation time 14126814 ps
CPU time 0.75 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:14 PM PST 24
Peak memory 205860 kb
Host smart-e9efbba4-8f0f-4c2b-89e3-9494f4623c2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25017532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.25017532
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.4231861199
Short name T36
Test name
Test status
Simulation time 211157013 ps
CPU time 4.03 seconds
Started Feb 22 01:07:11 PM PST 24
Finished Feb 22 01:07:16 PM PST 24
Peak memory 210248 kb
Host smart-96f0c6cc-c466-4a68-9fd8-87d7a9335b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231861199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.4231861199
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2881036001
Short name T1032
Test name
Test status
Simulation time 1318590375 ps
CPU time 4.59 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:17 PM PST 24
Peak memory 215072 kb
Host smart-9b2b7355-4989-4828-8b27-8e4202b066bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881036001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2881036001
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1997233527
Short name T890
Test name
Test status
Simulation time 1126566648 ps
CPU time 29.18 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:37 PM PST 24
Peak memory 214244 kb
Host smart-c93cbb6d-ef4d-458a-9dec-7da25291408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997233527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1997233527
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.441539690
Short name T65
Test name
Test status
Simulation time 256814560 ps
CPU time 9.18 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:17 PM PST 24
Peak memory 214340 kb
Host smart-21313abf-8bf5-4387-998c-97c198043988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441539690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.441539690
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3826034676
Short name T263
Test name
Test status
Simulation time 2372127123 ps
CPU time 9.45 seconds
Started Feb 22 01:07:11 PM PST 24
Finished Feb 22 01:07:21 PM PST 24
Peak memory 214340 kb
Host smart-b4cace66-f1fa-46ea-8579-88049ec17171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826034676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3826034676
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2026664715
Short name T602
Test name
Test status
Simulation time 318458726 ps
CPU time 2.65 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:16 PM PST 24
Peak memory 208580 kb
Host smart-66e53788-a76d-444d-94ce-e6eacc6aa9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026664715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2026664715
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1052594196
Short name T822
Test name
Test status
Simulation time 85457950 ps
CPU time 1.75 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:09 PM PST 24
Peak memory 206792 kb
Host smart-9ecc10f5-8531-49f3-bdbb-e6bcdd80690f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052594196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1052594196
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1185556631
Short name T253
Test name
Test status
Simulation time 82885523 ps
CPU time 3.87 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:16 PM PST 24
Peak memory 208028 kb
Host smart-2e510eaf-8ef2-4bed-ba5f-87de457a6f91
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185556631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1185556631
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2653005308
Short name T823
Test name
Test status
Simulation time 204186909 ps
CPU time 3.41 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:16 PM PST 24
Peak memory 206248 kb
Host smart-ce68e69e-eb93-4cb9-b974-0c0a653bfcb3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653005308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2653005308
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2953295084
Short name T863
Test name
Test status
Simulation time 347984510 ps
CPU time 10.02 seconds
Started Feb 22 01:07:11 PM PST 24
Finished Feb 22 01:07:22 PM PST 24
Peak memory 218200 kb
Host smart-c5d8fd63-4c34-486b-ba29-7807dbb73fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953295084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2953295084
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.855991586
Short name T1068
Test name
Test status
Simulation time 25243334 ps
CPU time 1.86 seconds
Started Feb 22 01:07:11 PM PST 24
Finished Feb 22 01:07:13 PM PST 24
Peak memory 206800 kb
Host smart-e0ca8e70-076c-44a0-9edc-8c97e7f4f365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855991586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.855991586
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3268985568
Short name T402
Test name
Test status
Simulation time 372216315 ps
CPU time 10.57 seconds
Started Feb 22 01:07:04 PM PST 24
Finished Feb 22 01:07:15 PM PST 24
Peak memory 221612 kb
Host smart-91103f80-306a-4872-ba97-11b223bd405c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268985568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3268985568
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.1315429080
Short name T816
Test name
Test status
Simulation time 36023058 ps
CPU time 2.6 seconds
Started Feb 22 01:07:10 PM PST 24
Finished Feb 22 01:07:14 PM PST 24
Peak memory 218460 kb
Host smart-d9b1addf-512e-4613-9ebe-64e9723534e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315429080 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.1315429080
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.4118410418
Short name T1065
Test name
Test status
Simulation time 1129881763 ps
CPU time 5.79 seconds
Started Feb 22 01:07:08 PM PST 24
Finished Feb 22 01:07:14 PM PST 24
Peak memory 208744 kb
Host smart-b96f220c-429d-4b0d-b6f0-d0706e992f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118410418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.4118410418
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3324428503
Short name T596
Test name
Test status
Simulation time 39126252 ps
CPU time 1.41 seconds
Started Feb 22 01:07:10 PM PST 24
Finished Feb 22 01:07:12 PM PST 24
Peak memory 209624 kb
Host smart-28c064b9-0c3d-4200-b4ee-7707efa3acb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324428503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3324428503
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2764290847
Short name T588
Test name
Test status
Simulation time 24405829 ps
CPU time 0.95 seconds
Started Feb 22 01:07:09 PM PST 24
Finished Feb 22 01:07:12 PM PST 24
Peak memory 205828 kb
Host smart-ce9c435a-8c50-4bf6-936d-8aaa4f5d838d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764290847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2764290847
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.512450431
Short name T426
Test name
Test status
Simulation time 7763778285 ps
CPU time 99.22 seconds
Started Feb 22 01:07:11 PM PST 24
Finished Feb 22 01:08:51 PM PST 24
Peak memory 214392 kb
Host smart-f58fc643-ade6-4c44-b30c-d23bb63d893a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512450431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.512450431
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2155284489
Short name T20
Test name
Test status
Simulation time 156314334 ps
CPU time 2.17 seconds
Started Feb 22 01:07:09 PM PST 24
Finished Feb 22 01:07:13 PM PST 24
Peak memory 214596 kb
Host smart-e26f5491-99af-440d-974b-69504113547b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155284489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2155284489
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3543382450
Short name T885
Test name
Test status
Simulation time 170657779 ps
CPU time 2.01 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:15 PM PST 24
Peak memory 208860 kb
Host smart-47715362-9190-4ba1-8b0e-e0f5824f236b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543382450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3543382450
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1774721149
Short name T868
Test name
Test status
Simulation time 299276232 ps
CPU time 2.8 seconds
Started Feb 22 01:07:15 PM PST 24
Finished Feb 22 01:07:18 PM PST 24
Peak memory 208876 kb
Host smart-f90608ee-db88-4fdf-a31e-2247df5beeec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774721149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1774721149
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1430502609
Short name T264
Test name
Test status
Simulation time 884723019 ps
CPU time 6.64 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:19 PM PST 24
Peak memory 209216 kb
Host smart-b550bc5e-0086-4b38-b7dc-e1f80579fecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430502609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1430502609
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1870561932
Short name T742
Test name
Test status
Simulation time 152971007 ps
CPU time 3.7 seconds
Started Feb 22 01:07:06 PM PST 24
Finished Feb 22 01:07:10 PM PST 24
Peak memory 208808 kb
Host smart-fe1d8d75-d3da-4eca-8596-df2e4a8c72ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870561932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1870561932
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3899933369
Short name T296
Test name
Test status
Simulation time 84562726 ps
CPU time 3.75 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:16 PM PST 24
Peak memory 208772 kb
Host smart-663657ec-6753-4a92-9c0e-2b8a2540f42f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899933369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3899933369
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2726453494
Short name T1014
Test name
Test status
Simulation time 438565112 ps
CPU time 8.18 seconds
Started Feb 22 01:07:10 PM PST 24
Finished Feb 22 01:07:19 PM PST 24
Peak memory 207796 kb
Host smart-24ee453a-7b7e-4bac-9e88-0322c785a332
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726453494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2726453494
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1621041669
Short name T650
Test name
Test status
Simulation time 208969120 ps
CPU time 8.12 seconds
Started Feb 22 01:07:15 PM PST 24
Finished Feb 22 01:07:24 PM PST 24
Peak memory 208636 kb
Host smart-f421af0c-9515-47d5-af94-70a6b474a8db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621041669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1621041669
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.4149248788
Short name T735
Test name
Test status
Simulation time 145582958 ps
CPU time 3.17 seconds
Started Feb 22 01:07:05 PM PST 24
Finished Feb 22 01:07:09 PM PST 24
Peak memory 207324 kb
Host smart-50d11ebf-8c94-4ff3-aa68-2545ea5ed461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149248788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.4149248788
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3553482745
Short name T583
Test name
Test status
Simulation time 200685717 ps
CPU time 2.63 seconds
Started Feb 22 01:07:16 PM PST 24
Finished Feb 22 01:07:18 PM PST 24
Peak memory 206784 kb
Host smart-ceb37a4c-e723-4ebd-9556-0cae4ba12012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553482745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3553482745
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3036667684
Short name T40
Test name
Test status
Simulation time 1300884366 ps
CPU time 13.4 seconds
Started Feb 22 01:07:01 PM PST 24
Finished Feb 22 01:07:16 PM PST 24
Peak memory 222428 kb
Host smart-058615f7-e1dd-4939-8a1e-f1e8e44fd769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036667684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3036667684
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3106930450
Short name T213
Test name
Test status
Simulation time 341114805 ps
CPU time 5.59 seconds
Started Feb 22 01:07:02 PM PST 24
Finished Feb 22 01:07:08 PM PST 24
Peak memory 222584 kb
Host smart-30fe4969-c9ff-46a4-8180-04c40b411190
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106930450 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3106930450
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3549170398
Short name T370
Test name
Test status
Simulation time 188701594 ps
CPU time 6.97 seconds
Started Feb 22 01:07:04 PM PST 24
Finished Feb 22 01:07:11 PM PST 24
Peak memory 218388 kb
Host smart-b7c10419-8e90-41ac-9bdb-b02f11045f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549170398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3549170398
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.379522360
Short name T764
Test name
Test status
Simulation time 173994866 ps
CPU time 2.53 seconds
Started Feb 22 01:07:01 PM PST 24
Finished Feb 22 01:07:04 PM PST 24
Peak memory 210312 kb
Host smart-725a42d5-8a45-4407-9df1-b20431c33027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379522360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.379522360
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2864092558
Short name T371
Test name
Test status
Simulation time 129380630 ps
CPU time 3.07 seconds
Started Feb 22 01:07:06 PM PST 24
Finished Feb 22 01:07:09 PM PST 24
Peak memory 214400 kb
Host smart-dda4f5f5-d93c-4c2a-9559-83de3b6bfaf9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2864092558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2864092558
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.4083588461
Short name T886
Test name
Test status
Simulation time 1776981044 ps
CPU time 12.49 seconds
Started Feb 22 01:07:10 PM PST 24
Finished Feb 22 01:07:24 PM PST 24
Peak memory 219488 kb
Host smart-5e603348-bdde-4037-8ff2-12c598594bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083588461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.4083588461
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1473312418
Short name T46
Test name
Test status
Simulation time 21881291 ps
CPU time 1.48 seconds
Started Feb 22 01:07:05 PM PST 24
Finished Feb 22 01:07:07 PM PST 24
Peak memory 207536 kb
Host smart-adb40625-29a0-4573-bcd3-19b2dacbc5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473312418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1473312418
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2477217045
Short name T660
Test name
Test status
Simulation time 434062649 ps
CPU time 11.07 seconds
Started Feb 22 01:07:04 PM PST 24
Finished Feb 22 01:07:16 PM PST 24
Peak memory 214264 kb
Host smart-7907706e-f6e5-41d6-a791-31a09d75b933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477217045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2477217045
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1882823267
Short name T194
Test name
Test status
Simulation time 6392049807 ps
CPU time 38.64 seconds
Started Feb 22 01:07:04 PM PST 24
Finished Feb 22 01:07:44 PM PST 24
Peak memory 216752 kb
Host smart-eee532b6-56fd-4a3b-b3da-963f6ae30954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882823267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1882823267
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2317222906
Short name T844
Test name
Test status
Simulation time 203314276 ps
CPU time 5.4 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:13 PM PST 24
Peak memory 222364 kb
Host smart-85f7b1ff-f87d-4592-889c-3a35bba1b7de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317222906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2317222906
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2558565249
Short name T943
Test name
Test status
Simulation time 2759550119 ps
CPU time 7.25 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:15 PM PST 24
Peak memory 207980 kb
Host smart-9defed26-2ff8-42da-a260-c8a9f9ac3ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558565249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2558565249
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.228756783
Short name T707
Test name
Test status
Simulation time 1712207903 ps
CPU time 54.7 seconds
Started Feb 22 01:07:09 PM PST 24
Finished Feb 22 01:08:05 PM PST 24
Peak memory 208912 kb
Host smart-a3926820-8856-4a2e-8543-376b9b4c9a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228756783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.228756783
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.4002355849
Short name T846
Test name
Test status
Simulation time 455449914 ps
CPU time 5.94 seconds
Started Feb 22 01:07:04 PM PST 24
Finished Feb 22 01:07:11 PM PST 24
Peak memory 208776 kb
Host smart-56566397-15cd-4068-b2e0-46fb2f910ece
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002355849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.4002355849
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2322104553
Short name T671
Test name
Test status
Simulation time 150168351 ps
CPU time 2.42 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:10 PM PST 24
Peak memory 206880 kb
Host smart-947b0cb2-a102-4a67-b1d5-4b7710e01b8a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322104553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2322104553
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2534520696
Short name T751
Test name
Test status
Simulation time 69005440 ps
CPU time 3.23 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:11 PM PST 24
Peak memory 208720 kb
Host smart-987205ad-7828-4f3e-9e6e-70c0251cf60c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534520696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2534520696
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2805119049
Short name T323
Test name
Test status
Simulation time 290102767 ps
CPU time 6.06 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:18 PM PST 24
Peak memory 208780 kb
Host smart-d9f9f973-c804-4780-8caf-6249578fe07c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805119049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2805119049
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2008059106
Short name T587
Test name
Test status
Simulation time 37363244 ps
CPU time 2.28 seconds
Started Feb 22 01:07:09 PM PST 24
Finished Feb 22 01:07:13 PM PST 24
Peak memory 206880 kb
Host smart-a8823010-6302-4cf8-ae2d-d0ebfc4f849c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008059106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2008059106
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2129822583
Short name T359
Test name
Test status
Simulation time 10110275555 ps
CPU time 64.24 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:08:17 PM PST 24
Peak memory 222532 kb
Host smart-fd9517a9-ad71-44a4-ab76-20628f8bb00b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129822583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2129822583
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2471720373
Short name T934
Test name
Test status
Simulation time 1607534516 ps
CPU time 11.09 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:24 PM PST 24
Peak memory 220836 kb
Host smart-49543f99-0de0-4c20-808e-b4b1a9e18cfc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471720373 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2471720373
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2016051731
Short name T309
Test name
Test status
Simulation time 144518989 ps
CPU time 4.78 seconds
Started Feb 22 01:07:06 PM PST 24
Finished Feb 22 01:07:11 PM PST 24
Peak memory 210156 kb
Host smart-bb0435f2-c0ed-41b4-8e84-5f2e07cdbe81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016051731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2016051731
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2079167574
Short name T917
Test name
Test status
Simulation time 458616856 ps
CPU time 3.52 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:16 PM PST 24
Peak memory 210176 kb
Host smart-9164a326-9b66-4933-9954-221d09900f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079167574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2079167574
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2478955261
Short name T100
Test name
Test status
Simulation time 136328761 ps
CPU time 0.77 seconds
Started Feb 22 01:07:24 PM PST 24
Finished Feb 22 01:07:25 PM PST 24
Peak memory 205768 kb
Host smart-7c584f56-d8e8-46b3-b998-620631ca09d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478955261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2478955261
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3801199470
Short name T436
Test name
Test status
Simulation time 54099149 ps
CPU time 4.11 seconds
Started Feb 22 01:07:22 PM PST 24
Finished Feb 22 01:07:26 PM PST 24
Peak memory 214180 kb
Host smart-55f09763-b283-4469-9bd3-4e13fbe69de3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3801199470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3801199470
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1904971464
Short name T989
Test name
Test status
Simulation time 116041509 ps
CPU time 4.79 seconds
Started Feb 22 01:07:36 PM PST 24
Finished Feb 22 01:07:42 PM PST 24
Peak memory 219652 kb
Host smart-38091b38-3568-4040-b449-64cadef8a5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904971464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1904971464
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3133213638
Short name T278
Test name
Test status
Simulation time 660800178 ps
CPU time 4.92 seconds
Started Feb 22 01:07:25 PM PST 24
Finished Feb 22 01:07:30 PM PST 24
Peak memory 218144 kb
Host smart-70a2c5cb-68f3-4423-9c80-4c5ac4c116fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133213638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3133213638
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1733963832
Short name T358
Test name
Test status
Simulation time 407971135 ps
CPU time 7.02 seconds
Started Feb 22 01:07:20 PM PST 24
Finished Feb 22 01:07:27 PM PST 24
Peak memory 209936 kb
Host smart-633fce5a-cf58-452a-9dd8-f6cf39b51580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733963832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1733963832
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1335609062
Short name T824
Test name
Test status
Simulation time 916139477 ps
CPU time 3.72 seconds
Started Feb 22 01:07:35 PM PST 24
Finished Feb 22 01:07:39 PM PST 24
Peak memory 209756 kb
Host smart-877040a4-6c9a-443f-a70a-5568501e2a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335609062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1335609062
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.983670878
Short name T201
Test name
Test status
Simulation time 86259588 ps
CPU time 4.45 seconds
Started Feb 22 01:07:33 PM PST 24
Finished Feb 22 01:07:38 PM PST 24
Peak memory 218512 kb
Host smart-c7f21831-7b79-40fe-aa13-2c5ca1a5c8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983670878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.983670878
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1370074924
Short name T328
Test name
Test status
Simulation time 23855310 ps
CPU time 1.96 seconds
Started Feb 22 01:07:03 PM PST 24
Finished Feb 22 01:07:05 PM PST 24
Peak memory 208608 kb
Host smart-1bd2cec3-3b27-4ac2-8b62-cda68b2d49e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370074924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1370074924
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1817875729
Short name T799
Test name
Test status
Simulation time 106084928 ps
CPU time 2.63 seconds
Started Feb 22 01:07:10 PM PST 24
Finished Feb 22 01:07:14 PM PST 24
Peak memory 206872 kb
Host smart-1e64fc7e-9c6b-4a1b-af1d-201956c5d534
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817875729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1817875729
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2539153858
Short name T572
Test name
Test status
Simulation time 256199071 ps
CPU time 3.32 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:11 PM PST 24
Peak memory 207848 kb
Host smart-3f72b642-8835-4cf9-8122-0c90d4ec1806
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539153858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2539153858
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3749588286
Short name T983
Test name
Test status
Simulation time 179431913 ps
CPU time 3.63 seconds
Started Feb 22 01:07:12 PM PST 24
Finished Feb 22 01:07:16 PM PST 24
Peak memory 207032 kb
Host smart-41acdd97-b9ce-486a-b86f-2bd4552bdc72
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749588286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3749588286
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2981048998
Short name T231
Test name
Test status
Simulation time 80453291 ps
CPU time 2.31 seconds
Started Feb 22 01:07:31 PM PST 24
Finished Feb 22 01:07:34 PM PST 24
Peak memory 215868 kb
Host smart-8eb1ca32-e12e-4976-87bf-649e338734e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981048998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2981048998
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2357265557
Short name T594
Test name
Test status
Simulation time 2957207759 ps
CPU time 37.92 seconds
Started Feb 22 01:07:07 PM PST 24
Finished Feb 22 01:07:46 PM PST 24
Peak memory 208936 kb
Host smart-acb69e62-c5a9-466f-a191-985cbd0365b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357265557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2357265557
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3905644190
Short name T756
Test name
Test status
Simulation time 11461202579 ps
CPU time 25.8 seconds
Started Feb 22 01:07:32 PM PST 24
Finished Feb 22 01:07:59 PM PST 24
Peak memory 222536 kb
Host smart-adaf57b5-452b-445a-91e0-a5c7facbb443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905644190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3905644190
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2683285318
Short name T297
Test name
Test status
Simulation time 1641050646 ps
CPU time 5.04 seconds
Started Feb 22 01:07:31 PM PST 24
Finished Feb 22 01:07:36 PM PST 24
Peak memory 209224 kb
Host smart-59868732-a281-4ebc-a71d-82034e79f5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683285318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2683285318
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3648707038
Short name T921
Test name
Test status
Simulation time 95931475 ps
CPU time 1.91 seconds
Started Feb 22 01:07:36 PM PST 24
Finished Feb 22 01:07:39 PM PST 24
Peak memory 209792 kb
Host smart-d917ebb2-bdda-43a5-9039-20431d946651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648707038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3648707038
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3298862054
Short name T172
Test name
Test status
Simulation time 18098399 ps
CPU time 0.83 seconds
Started Feb 22 01:07:35 PM PST 24
Finished Feb 22 01:07:36 PM PST 24
Peak memory 205852 kb
Host smart-d7cc3b93-4a80-4292-993d-43654595673f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298862054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3298862054
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3624660010
Short name T948
Test name
Test status
Simulation time 378591594 ps
CPU time 2.73 seconds
Started Feb 22 01:07:35 PM PST 24
Finished Feb 22 01:07:38 PM PST 24
Peak memory 215260 kb
Host smart-88274636-1a0e-44e6-b821-19948d686442
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624660010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3624660010
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.4239174942
Short name T923
Test name
Test status
Simulation time 152983434 ps
CPU time 4.86 seconds
Started Feb 22 01:07:24 PM PST 24
Finished Feb 22 01:07:29 PM PST 24
Peak memory 210240 kb
Host smart-6906d8ec-9718-47ae-8ce7-e696af9eae65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239174942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.4239174942
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.664257157
Short name T44
Test name
Test status
Simulation time 2386043619 ps
CPU time 7.79 seconds
Started Feb 22 01:07:37 PM PST 24
Finished Feb 22 01:07:45 PM PST 24
Peak memory 209896 kb
Host smart-b6175a09-f827-48e7-a775-b5ffd565e9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664257157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.664257157
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.4210235721
Short name T21
Test name
Test status
Simulation time 111081957 ps
CPU time 4.05 seconds
Started Feb 22 01:07:34 PM PST 24
Finished Feb 22 01:07:39 PM PST 24
Peak memory 219792 kb
Host smart-356e1fb4-3a56-43fd-90c6-3649d58c09eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210235721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.4210235721
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1873858774
Short name T393
Test name
Test status
Simulation time 641180003 ps
CPU time 4.34 seconds
Started Feb 22 01:07:31 PM PST 24
Finished Feb 22 01:07:35 PM PST 24
Peak memory 222396 kb
Host smart-e2ef7cbf-6df2-4d31-9b3a-f0a494db9147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873858774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1873858774
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2260732068
Short name T819
Test name
Test status
Simulation time 182915237 ps
CPU time 4.25 seconds
Started Feb 22 01:07:31 PM PST 24
Finished Feb 22 01:07:36 PM PST 24
Peak memory 220076 kb
Host smart-4c8cf1b0-b55b-466a-9209-a4cab993ffbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260732068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2260732068
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1245972283
Short name T789
Test name
Test status
Simulation time 75314814 ps
CPU time 3.42 seconds
Started Feb 22 01:07:30 PM PST 24
Finished Feb 22 01:07:34 PM PST 24
Peak memory 209260 kb
Host smart-ae7a0c84-0de6-4d8a-a5a6-2e0eedbefb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245972283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1245972283
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2502377425
Short name T677
Test name
Test status
Simulation time 92215243 ps
CPU time 3.24 seconds
Started Feb 22 01:07:33 PM PST 24
Finished Feb 22 01:07:36 PM PST 24
Peak memory 207068 kb
Host smart-1c2ab044-b2bc-4718-961c-0310c801dab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502377425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2502377425
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1323811898
Short name T813
Test name
Test status
Simulation time 169847610 ps
CPU time 5.36 seconds
Started Feb 22 01:07:39 PM PST 24
Finished Feb 22 01:07:45 PM PST 24
Peak memory 207972 kb
Host smart-4c3b16e6-c36d-4ef5-b193-bafad47840fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323811898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1323811898
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.73106631
Short name T39
Test name
Test status
Simulation time 34281613 ps
CPU time 2.38 seconds
Started Feb 22 01:07:34 PM PST 24
Finished Feb 22 01:07:37 PM PST 24
Peak memory 206852 kb
Host smart-9f6b3494-0dd5-4565-8ed4-f7bf02c3431f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73106631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.73106631
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3176926216
Short name T697
Test name
Test status
Simulation time 80425518 ps
CPU time 3.06 seconds
Started Feb 22 01:07:34 PM PST 24
Finished Feb 22 01:07:38 PM PST 24
Peak memory 206824 kb
Host smart-ba18bbb4-ca4f-4dfb-bb6d-eebe51613f25
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176926216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3176926216
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.918908236
Short name T627
Test name
Test status
Simulation time 69580192 ps
CPU time 2.5 seconds
Started Feb 22 01:07:31 PM PST 24
Finished Feb 22 01:07:34 PM PST 24
Peak memory 207912 kb
Host smart-051e3db7-4917-4b2a-bb34-b2d8503779b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918908236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.918908236
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3330852674
Short name T80
Test name
Test status
Simulation time 203688709 ps
CPU time 2.53 seconds
Started Feb 22 01:07:36 PM PST 24
Finished Feb 22 01:07:39 PM PST 24
Peak memory 206052 kb
Host smart-a6613631-75f6-494c-8542-71eaa197234f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330852674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3330852674
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3519235729
Short name T214
Test name
Test status
Simulation time 3304844941 ps
CPU time 19.62 seconds
Started Feb 22 01:07:22 PM PST 24
Finished Feb 22 01:07:42 PM PST 24
Peak memory 222424 kb
Host smart-d6587f36-cf21-47db-bcb6-043c770f95f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519235729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3519235729
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3475290626
Short name T1017
Test name
Test status
Simulation time 572137934 ps
CPU time 6.91 seconds
Started Feb 22 01:07:23 PM PST 24
Finished Feb 22 01:07:31 PM PST 24
Peak memory 223168 kb
Host smart-a9c6670a-98a5-4474-9a3b-a6209b741705
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475290626 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3475290626
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.409265947
Short name T837
Test name
Test status
Simulation time 1047255187 ps
CPU time 14.27 seconds
Started Feb 22 01:07:35 PM PST 24
Finished Feb 22 01:07:49 PM PST 24
Peak memory 214280 kb
Host smart-6e8ac559-a6b8-45bb-9b5e-c2478199a71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409265947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.409265947
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.4032955297
Short name T781
Test name
Test status
Simulation time 71765633 ps
CPU time 2.31 seconds
Started Feb 22 01:07:34 PM PST 24
Finished Feb 22 01:07:37 PM PST 24
Peak memory 210100 kb
Host smart-01938849-546a-495a-8d61-ceb2e9db52f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032955297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.4032955297
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2995761024
Short name T669
Test name
Test status
Simulation time 310359520 ps
CPU time 0.89 seconds
Started Feb 22 01:07:33 PM PST 24
Finished Feb 22 01:07:34 PM PST 24
Peak memory 205876 kb
Host smart-d996441e-9a61-4238-8357-8d28837c798e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995761024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2995761024
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2803702572
Short name T424
Test name
Test status
Simulation time 53008306 ps
CPU time 3.49 seconds
Started Feb 22 01:07:34 PM PST 24
Finished Feb 22 01:07:38 PM PST 24
Peak memory 214292 kb
Host smart-dc661c32-6022-484b-a6d8-c047b7f27f6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2803702572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2803702572
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1633826405
Short name T15
Test name
Test status
Simulation time 110988043 ps
CPU time 5.64 seconds
Started Feb 22 01:07:36 PM PST 24
Finished Feb 22 01:07:42 PM PST 24
Peak memory 209224 kb
Host smart-7660d1b4-4e16-4cb2-adeb-ff91329ccc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633826405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1633826405
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1351820328
Short name T376
Test name
Test status
Simulation time 39676950 ps
CPU time 1.61 seconds
Started Feb 22 01:07:35 PM PST 24
Finished Feb 22 01:07:36 PM PST 24
Peak memory 208772 kb
Host smart-ff135481-6db8-4739-8b80-9cc64ecb5966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351820328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1351820328
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.209336275
Short name T838
Test name
Test status
Simulation time 462269293 ps
CPU time 3.77 seconds
Started Feb 22 01:07:32 PM PST 24
Finished Feb 22 01:07:37 PM PST 24
Peak memory 208552 kb
Host smart-00d25dac-4a06-4517-9c29-c07b9722e938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209336275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.209336275
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3873568567
Short name T818
Test name
Test status
Simulation time 104115022 ps
CPU time 1.91 seconds
Started Feb 22 01:07:23 PM PST 24
Finished Feb 22 01:07:25 PM PST 24
Peak memory 214284 kb
Host smart-7c34fd9c-8a0f-460e-a18b-be77d719ae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873568567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3873568567
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3470597209
Short name T182
Test name
Test status
Simulation time 1162017338 ps
CPU time 4.19 seconds
Started Feb 22 01:07:35 PM PST 24
Finished Feb 22 01:07:39 PM PST 24
Peak memory 209880 kb
Host smart-2c2410b2-830b-4fb4-9c15-d20206a7636a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470597209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3470597209
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2023225340
Short name T729
Test name
Test status
Simulation time 30792672 ps
CPU time 2.41 seconds
Started Feb 22 01:07:35 PM PST 24
Finished Feb 22 01:07:38 PM PST 24
Peak memory 207248 kb
Host smart-3a18e4fb-7994-42f3-9ba1-174491664f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023225340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2023225340
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.118080823
Short name T951
Test name
Test status
Simulation time 169914257 ps
CPU time 5.25 seconds
Started Feb 22 01:07:29 PM PST 24
Finished Feb 22 01:07:35 PM PST 24
Peak memory 208560 kb
Host smart-09654b30-9d50-4ba8-a532-9f4e36aeb762
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118080823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.118080823
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.996185561
Short name T976
Test name
Test status
Simulation time 641577476 ps
CPU time 6.29 seconds
Started Feb 22 01:07:35 PM PST 24
Finished Feb 22 01:07:42 PM PST 24
Peak memory 208716 kb
Host smart-c759d825-d647-449a-9b34-877c30389f12
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996185561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.996185561
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.786509037
Short name T582
Test name
Test status
Simulation time 101027731 ps
CPU time 4.04 seconds
Started Feb 22 01:07:32 PM PST 24
Finished Feb 22 01:07:36 PM PST 24
Peak memory 208192 kb
Host smart-6a5a9bfd-9b9c-4d7c-9a09-409ead2d608e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786509037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.786509037
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1844216459
Short name T978
Test name
Test status
Simulation time 324076308 ps
CPU time 3.75 seconds
Started Feb 22 01:07:39 PM PST 24
Finished Feb 22 01:07:43 PM PST 24
Peak memory 215840 kb
Host smart-b6da82d7-e6ce-4560-8c7d-58ca1bebd8d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844216459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1844216459
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2461181300
Short name T656
Test name
Test status
Simulation time 233945358 ps
CPU time 2.89 seconds
Started Feb 22 01:07:23 PM PST 24
Finished Feb 22 01:07:27 PM PST 24
Peak memory 206696 kb
Host smart-651c38ed-7417-46ed-a352-7851fdeef30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461181300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2461181300
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3709818024
Short name T918
Test name
Test status
Simulation time 3862523087 ps
CPU time 97.84 seconds
Started Feb 22 01:07:25 PM PST 24
Finished Feb 22 01:09:04 PM PST 24
Peak memory 222580 kb
Host smart-85ceb252-6651-4a1c-8221-097c73cb4d53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709818024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3709818024
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3392682415
Short name T412
Test name
Test status
Simulation time 336922989 ps
CPU time 3.65 seconds
Started Feb 22 01:07:39 PM PST 24
Finished Feb 22 01:07:43 PM PST 24
Peak memory 222512 kb
Host smart-730b04e3-9f00-44ed-b747-1979ed023dee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392682415 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3392682415
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.503506291
Short name T855
Test name
Test status
Simulation time 97431354 ps
CPU time 4.35 seconds
Started Feb 22 01:07:37 PM PST 24
Finished Feb 22 01:07:42 PM PST 24
Peak memory 215856 kb
Host smart-2efb72fd-c709-4818-a989-f24191643872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503506291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.503506291
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.444358768
Short name T637
Test name
Test status
Simulation time 14914908 ps
CPU time 0.8 seconds
Started Feb 22 01:07:37 PM PST 24
Finished Feb 22 01:07:39 PM PST 24
Peak memory 205856 kb
Host smart-d3b05c88-d184-4200-8219-5344e73fae65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444358768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.444358768
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2350550538
Short name T258
Test name
Test status
Simulation time 630642216 ps
CPU time 9.07 seconds
Started Feb 22 01:07:35 PM PST 24
Finished Feb 22 01:07:44 PM PST 24
Peak memory 215560 kb
Host smart-721c6d2a-336b-4d93-a101-ca004442e093
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2350550538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2350550538
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2841306068
Short name T9
Test name
Test status
Simulation time 4554979889 ps
CPU time 72.98 seconds
Started Feb 22 01:07:37 PM PST 24
Finished Feb 22 01:08:51 PM PST 24
Peak memory 233092 kb
Host smart-48f04fc2-b2b8-4756-be8e-b146c8fec616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841306068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2841306068
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.811553672
Short name T834
Test name
Test status
Simulation time 131211386 ps
CPU time 3.02 seconds
Started Feb 22 01:07:42 PM PST 24
Finished Feb 22 01:07:47 PM PST 24
Peak memory 208820 kb
Host smart-a8a4d928-7e90-4cd1-a309-112d3cda8257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811553672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.811553672
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3795724197
Short name T723
Test name
Test status
Simulation time 52989060 ps
CPU time 3.42 seconds
Started Feb 22 01:07:43 PM PST 24
Finished Feb 22 01:07:48 PM PST 24
Peak memory 214256 kb
Host smart-44a6411f-b12c-4293-97b7-893377102419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795724197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3795724197
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1012887355
Short name T305
Test name
Test status
Simulation time 113106374 ps
CPU time 5.05 seconds
Started Feb 22 01:07:42 PM PST 24
Finished Feb 22 01:07:48 PM PST 24
Peak memory 222356 kb
Host smart-9bd2ee17-ad41-436a-b4c9-974c7978c697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012887355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1012887355
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.335660585
Short name T903
Test name
Test status
Simulation time 98379298 ps
CPU time 3.11 seconds
Started Feb 22 01:07:29 PM PST 24
Finished Feb 22 01:07:33 PM PST 24
Peak memory 209000 kb
Host smart-58dd5916-66bd-421b-b3f8-59b4bf9e9d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335660585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.335660585
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1203073637
Short name T127
Test name
Test status
Simulation time 311175521 ps
CPU time 4.09 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:42 PM PST 24
Peak memory 218452 kb
Host smart-b498d717-17bb-40c7-bd20-3b0d65af1543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203073637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1203073637
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1063902020
Short name T266
Test name
Test status
Simulation time 183704064 ps
CPU time 2.57 seconds
Started Feb 22 01:07:30 PM PST 24
Finished Feb 22 01:07:34 PM PST 24
Peak memory 208624 kb
Host smart-ce0746e3-48db-4bc9-a2fc-61ee5ee09170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063902020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1063902020
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2783000696
Short name T262
Test name
Test status
Simulation time 59633672 ps
CPU time 2.84 seconds
Started Feb 22 01:07:32 PM PST 24
Finished Feb 22 01:07:35 PM PST 24
Peak memory 206764 kb
Host smart-5c4993e6-d077-4a07-bf1f-eba0b1a63063
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783000696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2783000696
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.607109422
Short name T901
Test name
Test status
Simulation time 1215453071 ps
CPU time 8.85 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:47 PM PST 24
Peak memory 208008 kb
Host smart-f3849e5b-0a83-420c-88c6-fcf3587ece83
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607109422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.607109422
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1804899475
Short name T625
Test name
Test status
Simulation time 122610071 ps
CPU time 3.1 seconds
Started Feb 22 01:07:37 PM PST 24
Finished Feb 22 01:07:41 PM PST 24
Peak memory 206764 kb
Host smart-33d09b38-8038-47e0-89f6-015caf87791f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804899475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1804899475
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.978758574
Short name T775
Test name
Test status
Simulation time 42122619 ps
CPU time 2.8 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:41 PM PST 24
Peak memory 218052 kb
Host smart-51ce0aaa-4ff4-468b-8437-f59c5ba31d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978758574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.978758574
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2517707292
Short name T767
Test name
Test status
Simulation time 79861252 ps
CPU time 2.12 seconds
Started Feb 22 01:07:36 PM PST 24
Finished Feb 22 01:07:38 PM PST 24
Peak memory 206636 kb
Host smart-0ae24914-c347-4bc1-9436-5deac3b9827f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517707292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2517707292
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1724501265
Short name T1019
Test name
Test status
Simulation time 304691197 ps
CPU time 13.01 seconds
Started Feb 22 01:07:39 PM PST 24
Finished Feb 22 01:07:53 PM PST 24
Peak memory 222448 kb
Host smart-3533f220-9911-4306-95a8-597909b02859
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724501265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1724501265
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1562963313
Short name T224
Test name
Test status
Simulation time 466637242 ps
CPU time 6.44 seconds
Started Feb 22 01:07:34 PM PST 24
Finished Feb 22 01:07:41 PM PST 24
Peak memory 220308 kb
Host smart-dc5f64c0-f4be-42fb-9cf6-2c488e22f468
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562963313 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1562963313
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.37789916
Short name T301
Test name
Test status
Simulation time 1801975051 ps
CPU time 9.87 seconds
Started Feb 22 01:07:37 PM PST 24
Finished Feb 22 01:07:48 PM PST 24
Peak memory 214108 kb
Host smart-22d7f64e-8e4f-4770-991c-255497f84d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37789916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.37789916
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.4221528098
Short name T1060
Test name
Test status
Simulation time 49714395 ps
CPU time 2.7 seconds
Started Feb 22 01:07:39 PM PST 24
Finished Feb 22 01:07:42 PM PST 24
Peak memory 210036 kb
Host smart-875a2b4a-0c10-4b03-b6b3-e7f633f17a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221528098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.4221528098
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1615739425
Short name T668
Test name
Test status
Simulation time 40291425 ps
CPU time 0.71 seconds
Started Feb 22 01:07:43 PM PST 24
Finished Feb 22 01:07:44 PM PST 24
Peak memory 205744 kb
Host smart-5b9ff3ab-98d9-4dc1-9450-a3ad7f910dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615739425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1615739425
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2358269565
Short name T433
Test name
Test status
Simulation time 192329702 ps
CPU time 4.03 seconds
Started Feb 22 01:07:41 PM PST 24
Finished Feb 22 01:07:46 PM PST 24
Peak memory 215336 kb
Host smart-5e51751a-1768-481d-908c-78a43d7da429
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2358269565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2358269565
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.762123409
Short name T26
Test name
Test status
Simulation time 663498284 ps
CPU time 5.56 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:44 PM PST 24
Peak memory 208544 kb
Host smart-69995dd6-fc41-4c27-a355-89c8bd113bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762123409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.762123409
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.642450975
Short name T290
Test name
Test status
Simulation time 59347040 ps
CPU time 2.86 seconds
Started Feb 22 01:07:42 PM PST 24
Finished Feb 22 01:07:45 PM PST 24
Peak memory 208596 kb
Host smart-1a770d66-05d1-4e15-933b-ead543fe92d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642450975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.642450975
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.431212826
Short name T312
Test name
Test status
Simulation time 364738737 ps
CPU time 9.37 seconds
Started Feb 22 01:07:41 PM PST 24
Finished Feb 22 01:07:50 PM PST 24
Peak memory 214256 kb
Host smart-10dbfb29-8f3a-4bfd-bc53-c0dd6107505b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431212826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.431212826
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3416408689
Short name T306
Test name
Test status
Simulation time 80594479 ps
CPU time 3.59 seconds
Started Feb 22 01:07:39 PM PST 24
Finished Feb 22 01:07:43 PM PST 24
Peak memory 210252 kb
Host smart-7b702068-6c77-4eeb-9512-2722563f131e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416408689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3416408689
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.709136925
Short name T41
Test name
Test status
Simulation time 100200775 ps
CPU time 4.59 seconds
Started Feb 22 01:07:40 PM PST 24
Finished Feb 22 01:07:45 PM PST 24
Peak memory 214540 kb
Host smart-b32fe6ca-9d81-428c-bfed-5ebca7ce56a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709136925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.709136925
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2187346431
Short name T369
Test name
Test status
Simulation time 459488326 ps
CPU time 3.59 seconds
Started Feb 22 01:07:40 PM PST 24
Finished Feb 22 01:07:44 PM PST 24
Peak memory 207200 kb
Host smart-0c08418a-301b-453c-98c4-7b996c17439d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187346431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2187346431
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3642328819
Short name T884
Test name
Test status
Simulation time 61449482 ps
CPU time 2.84 seconds
Started Feb 22 01:07:36 PM PST 24
Finished Feb 22 01:07:40 PM PST 24
Peak memory 208104 kb
Host smart-2e89b180-728f-498c-9330-bc06a48743c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642328819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3642328819
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3623152895
Short name T284
Test name
Test status
Simulation time 70277908 ps
CPU time 3.08 seconds
Started Feb 22 01:07:40 PM PST 24
Finished Feb 22 01:07:44 PM PST 24
Peak memory 206816 kb
Host smart-88e4d8e5-1bba-4e60-bc96-1a0d7eb52d77
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623152895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3623152895
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3723033584
Short name T777
Test name
Test status
Simulation time 475243654 ps
CPU time 7.64 seconds
Started Feb 22 01:07:40 PM PST 24
Finished Feb 22 01:07:48 PM PST 24
Peak memory 208696 kb
Host smart-51685b56-5038-4989-87c5-81b5ee01e1f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723033584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3723033584
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1369763099
Short name T1030
Test name
Test status
Simulation time 255716285 ps
CPU time 3.17 seconds
Started Feb 22 01:07:43 PM PST 24
Finished Feb 22 01:07:48 PM PST 24
Peak memory 208568 kb
Host smart-03aeedf2-6bce-4a1d-ad42-bcb884885ef3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369763099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1369763099
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3900575899
Short name T736
Test name
Test status
Simulation time 825947753 ps
CPU time 17.53 seconds
Started Feb 22 01:07:44 PM PST 24
Finished Feb 22 01:08:03 PM PST 24
Peak memory 220992 kb
Host smart-16e077eb-2ff2-44dc-b9a4-6065d422867d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900575899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3900575899
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3709551308
Short name T991
Test name
Test status
Simulation time 92053676 ps
CPU time 3.54 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:42 PM PST 24
Peak memory 208808 kb
Host smart-a90d140b-6c1b-4741-a191-abe9b93ace81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709551308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3709551308
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2609407314
Short name T368
Test name
Test status
Simulation time 5540329355 ps
CPU time 76.31 seconds
Started Feb 22 01:07:41 PM PST 24
Finished Feb 22 01:08:58 PM PST 24
Peak memory 216564 kb
Host smart-eca4ac59-ee5c-4264-8dc9-8a954f976b09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609407314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2609407314
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2349520941
Short name T807
Test name
Test status
Simulation time 109194962 ps
CPU time 3.38 seconds
Started Feb 22 01:07:37 PM PST 24
Finished Feb 22 01:07:41 PM PST 24
Peak memory 214416 kb
Host smart-60c2bfe0-5588-4843-82d7-2f1257c54c9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349520941 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2349520941
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1734166483
Short name T155
Test name
Test status
Simulation time 10667010481 ps
CPU time 11.04 seconds
Started Feb 22 01:07:44 PM PST 24
Finished Feb 22 01:07:56 PM PST 24
Peak memory 211096 kb
Host smart-b648af65-d10e-4c7a-8031-1dfcde3c04cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734166483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1734166483
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.134617879
Short name T444
Test name
Test status
Simulation time 46905032 ps
CPU time 0.94 seconds
Started Feb 22 01:07:37 PM PST 24
Finished Feb 22 01:07:39 PM PST 24
Peak memory 205992 kb
Host smart-1a78bb5d-afc2-4a21-8fc2-425f439ff884
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134617879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.134617879
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.193564607
Short name T869
Test name
Test status
Simulation time 781265073 ps
CPU time 10.72 seconds
Started Feb 22 01:07:39 PM PST 24
Finished Feb 22 01:07:50 PM PST 24
Peak memory 215508 kb
Host smart-04525ca6-3f19-4193-8b0c-22fcdf34ff53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=193564607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.193564607
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3889724039
Short name T915
Test name
Test status
Simulation time 22637596 ps
CPU time 1.6 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:40 PM PST 24
Peak memory 210212 kb
Host smart-3c6a2b9a-f752-458a-9a3a-793304a6bcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889724039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3889724039
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.506293262
Short name T717
Test name
Test status
Simulation time 445818113 ps
CPU time 6.15 seconds
Started Feb 22 01:07:37 PM PST 24
Finished Feb 22 01:07:44 PM PST 24
Peak memory 208520 kb
Host smart-fb07ad0d-21d5-4e6e-bdbe-aaabfc0ea97d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506293262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.506293262
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1531386496
Short name T357
Test name
Test status
Simulation time 213378361 ps
CPU time 4.25 seconds
Started Feb 22 01:07:37 PM PST 24
Finished Feb 22 01:07:42 PM PST 24
Peak memory 222712 kb
Host smart-1ad472ec-3d10-4b26-8c83-1cc1c9d96a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531386496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1531386496
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1534134953
Short name T413
Test name
Test status
Simulation time 306003000 ps
CPU time 9.27 seconds
Started Feb 22 01:07:40 PM PST 24
Finished Feb 22 01:07:50 PM PST 24
Peak memory 219020 kb
Host smart-402740ab-16fb-4c32-bc6b-1eeab57d8116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534134953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1534134953
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3076049313
Short name T252
Test name
Test status
Simulation time 156126290 ps
CPU time 3.11 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:41 PM PST 24
Peak memory 214612 kb
Host smart-3d2f991f-4594-4900-ac9f-36e5dd84dd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076049313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3076049313
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3557654326
Short name T342
Test name
Test status
Simulation time 171992176 ps
CPU time 3.99 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:42 PM PST 24
Peak memory 206552 kb
Host smart-776f19ad-2814-4fec-813f-5bdd3edc81a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557654326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3557654326
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2945637946
Short name T388
Test name
Test status
Simulation time 61315528 ps
CPU time 2.58 seconds
Started Feb 22 01:07:36 PM PST 24
Finished Feb 22 01:07:40 PM PST 24
Peak memory 208564 kb
Host smart-15e88b68-a871-4430-b204-ffca335940f1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945637946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2945637946
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2500297875
Short name T349
Test name
Test status
Simulation time 51845271 ps
CPU time 2.16 seconds
Started Feb 22 01:07:41 PM PST 24
Finished Feb 22 01:07:44 PM PST 24
Peak memory 208640 kb
Host smart-50ec5b91-b1d8-45e5-80ba-05ae61176afb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500297875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2500297875
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.23234092
Short name T911
Test name
Test status
Simulation time 4652361512 ps
CPU time 50.11 seconds
Started Feb 22 01:07:36 PM PST 24
Finished Feb 22 01:08:28 PM PST 24
Peak memory 209048 kb
Host smart-6dddd2d3-f540-436f-a1e3-3229ab6d2a6a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23234092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.23234092
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.741860968
Short name T299
Test name
Test status
Simulation time 113099008 ps
CPU time 4 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:42 PM PST 24
Peak memory 214296 kb
Host smart-490d5d22-de8a-435d-a8cc-57cfc235aa76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741860968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.741860968
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1856187549
Short name T1029
Test name
Test status
Simulation time 92450409 ps
CPU time 2.04 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:40 PM PST 24
Peak memory 208376 kb
Host smart-80c1be53-e17d-4603-b83c-2b2adb5449bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856187549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1856187549
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.50547992
Short name T654
Test name
Test status
Simulation time 120316094 ps
CPU time 4.09 seconds
Started Feb 22 01:07:39 PM PST 24
Finished Feb 22 01:07:44 PM PST 24
Peak memory 207156 kb
Host smart-fd1f8285-ab5b-400d-86ca-1e45ff8e03c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50547992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.50547992
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3635243378
Short name T821
Test name
Test status
Simulation time 139203367 ps
CPU time 5.48 seconds
Started Feb 22 01:07:43 PM PST 24
Finished Feb 22 01:07:50 PM PST 24
Peak memory 218448 kb
Host smart-41ba4eec-1219-434b-ad5c-2eb58c395ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635243378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3635243378
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.4019695832
Short name T32
Test name
Test status
Simulation time 126989793 ps
CPU time 2.67 seconds
Started Feb 22 01:07:39 PM PST 24
Finished Feb 22 01:07:41 PM PST 24
Peak memory 209732 kb
Host smart-13c3316f-04fe-403a-9476-3f0f9e8b6fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019695832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.4019695832
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.450570650
Short name T757
Test name
Test status
Simulation time 131813873 ps
CPU time 0.8 seconds
Started Feb 22 01:07:47 PM PST 24
Finished Feb 22 01:07:48 PM PST 24
Peak memory 205836 kb
Host smart-658654d5-ad9b-46b4-bc31-12ecc6e00176
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450570650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.450570650
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.91885855
Short name T427
Test name
Test status
Simulation time 151030435 ps
CPU time 6.92 seconds
Started Feb 22 01:07:37 PM PST 24
Finished Feb 22 01:07:44 PM PST 24
Peak memory 222540 kb
Host smart-a03f91c0-e171-4dd3-ab09-f04e1bc4007b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=91885855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.91885855
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2952241245
Short name T74
Test name
Test status
Simulation time 64323977 ps
CPU time 2.36 seconds
Started Feb 22 01:07:39 PM PST 24
Finished Feb 22 01:07:41 PM PST 24
Peak memory 207520 kb
Host smart-bef69d0c-242d-43da-94c5-27c2adc0e628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952241245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2952241245
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3657321983
Short name T383
Test name
Test status
Simulation time 156129754 ps
CPU time 3.57 seconds
Started Feb 22 01:08:11 PM PST 24
Finished Feb 22 01:08:15 PM PST 24
Peak memory 218292 kb
Host smart-abb48bab-eb7f-4246-9b8a-bc2b2fd2ba77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657321983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3657321983
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3866441401
Short name T333
Test name
Test status
Simulation time 667287651 ps
CPU time 5.61 seconds
Started Feb 22 01:07:43 PM PST 24
Finished Feb 22 01:07:50 PM PST 24
Peak memory 210348 kb
Host smart-db6ceae9-627a-4608-873c-e6792901339c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866441401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3866441401
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.524050709
Short name T64
Test name
Test status
Simulation time 118930242 ps
CPU time 3.16 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:42 PM PST 24
Peak memory 208564 kb
Host smart-7a392bab-ea5c-4f90-914c-f85cc21921b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524050709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.524050709
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1096518688
Short name T184
Test name
Test status
Simulation time 68460377 ps
CPU time 2.6 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:41 PM PST 24
Peak memory 218240 kb
Host smart-55c7b589-3ddb-4409-b7a2-c67fe56de9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096518688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1096518688
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.251026815
Short name T410
Test name
Test status
Simulation time 250682667 ps
CPU time 3.86 seconds
Started Feb 22 01:07:37 PM PST 24
Finished Feb 22 01:07:41 PM PST 24
Peak memory 206612 kb
Host smart-9233ebfd-bbba-4911-9712-d1789b77c86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251026815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.251026815
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1610259809
Short name T928
Test name
Test status
Simulation time 164452422 ps
CPU time 5.35 seconds
Started Feb 22 01:07:37 PM PST 24
Finished Feb 22 01:07:43 PM PST 24
Peak memory 206836 kb
Host smart-94b00ac5-5ea9-4302-ae05-afe5692c0273
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610259809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1610259809
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2663469233
Short name T1015
Test name
Test status
Simulation time 466112154 ps
CPU time 3.04 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:42 PM PST 24
Peak memory 206888 kb
Host smart-595c39f6-7292-4a9e-9f47-660f2b307d7e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663469233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2663469233
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.675388968
Short name T254
Test name
Test status
Simulation time 283181618 ps
CPU time 5.89 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:44 PM PST 24
Peak memory 208612 kb
Host smart-fd5deec5-d8e3-4957-af29-625062002a6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675388968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.675388968
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.556280138
Short name T892
Test name
Test status
Simulation time 1574837261 ps
CPU time 14.01 seconds
Started Feb 22 01:07:36 PM PST 24
Finished Feb 22 01:07:51 PM PST 24
Peak memory 209400 kb
Host smart-1e450dac-df4e-442a-b422-4767d6f51e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556280138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.556280138
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3917880229
Short name T666
Test name
Test status
Simulation time 319935282 ps
CPU time 2.51 seconds
Started Feb 22 01:07:38 PM PST 24
Finished Feb 22 01:07:41 PM PST 24
Peak memory 206064 kb
Host smart-d58b1fef-c600-4b61-9e63-1fc1598c0949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917880229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3917880229
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1902049410
Short name T56
Test name
Test status
Simulation time 3313691834 ps
CPU time 20.74 seconds
Started Feb 22 01:07:48 PM PST 24
Finished Feb 22 01:08:09 PM PST 24
Peak memory 215520 kb
Host smart-aa906e7d-09eb-4250-b150-e073c66d92ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902049410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1902049410
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.2103162704
Short name T416
Test name
Test status
Simulation time 83002337 ps
CPU time 3.85 seconds
Started Feb 22 01:07:53 PM PST 24
Finished Feb 22 01:07:57 PM PST 24
Peak memory 222620 kb
Host smart-313b0e12-d0cb-4c7a-94c3-67963bfdcce1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103162704 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.2103162704
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2053084133
Short name T793
Test name
Test status
Simulation time 1249651364 ps
CPU time 7.89 seconds
Started Feb 22 01:07:39 PM PST 24
Finished Feb 22 01:07:47 PM PST 24
Peak memory 208644 kb
Host smart-d22e4757-e33f-4151-8723-7d0338e1abe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053084133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2053084133
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3616787734
Short name T881
Test name
Test status
Simulation time 1118690337 ps
CPU time 6.68 seconds
Started Feb 22 01:07:48 PM PST 24
Finished Feb 22 01:07:55 PM PST 24
Peak memory 210996 kb
Host smart-de0d289f-244c-4fa6-8468-02ff7024f13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616787734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3616787734
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.4290988555
Short name T702
Test name
Test status
Simulation time 36228574 ps
CPU time 0.94 seconds
Started Feb 22 01:05:51 PM PST 24
Finished Feb 22 01:05:53 PM PST 24
Peak memory 205808 kb
Host smart-6d5c9b72-a72d-4166-af6e-357c6b3e21dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290988555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.4290988555
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2347412543
Short name T993
Test name
Test status
Simulation time 350954985 ps
CPU time 9.53 seconds
Started Feb 22 01:05:54 PM PST 24
Finished Feb 22 01:06:04 PM PST 24
Peak memory 214288 kb
Host smart-0770bc43-d6ef-43d8-9368-3dc7c5d4c67f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2347412543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2347412543
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3215053185
Short name T216
Test name
Test status
Simulation time 45132109 ps
CPU time 2.7 seconds
Started Feb 22 01:05:49 PM PST 24
Finished Feb 22 01:05:52 PM PST 24
Peak memory 217976 kb
Host smart-83aa2426-4ca8-4272-8ac2-73635b583d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215053185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3215053185
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.692885077
Short name T722
Test name
Test status
Simulation time 23739650 ps
CPU time 1.75 seconds
Started Feb 22 01:05:57 PM PST 24
Finished Feb 22 01:05:59 PM PST 24
Peak memory 207864 kb
Host smart-f18d9c46-55aa-438d-9bc4-4fefd7c1e102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692885077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.692885077
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.243614828
Short name T877
Test name
Test status
Simulation time 270316904 ps
CPU time 2.96 seconds
Started Feb 22 01:05:50 PM PST 24
Finished Feb 22 01:05:53 PM PST 24
Peak memory 214228 kb
Host smart-482e8e28-bd2d-4b3b-981b-63f68518cc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243614828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.243614828
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3113341604
Short name T339
Test name
Test status
Simulation time 84093515 ps
CPU time 3.7 seconds
Started Feb 22 01:05:54 PM PST 24
Finished Feb 22 01:05:58 PM PST 24
Peak memory 210192 kb
Host smart-319ed40e-ef8b-4f89-a7b8-a7d47e4e36fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113341604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3113341604
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3059816270
Short name T870
Test name
Test status
Simulation time 6394785169 ps
CPU time 35.46 seconds
Started Feb 22 01:05:59 PM PST 24
Finished Feb 22 01:06:35 PM PST 24
Peak memory 210612 kb
Host smart-657cc387-8af1-44dc-b855-32f51a547f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059816270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3059816270
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.646170398
Short name T773
Test name
Test status
Simulation time 172203989 ps
CPU time 4.22 seconds
Started Feb 22 01:05:58 PM PST 24
Finished Feb 22 01:06:03 PM PST 24
Peak memory 206640 kb
Host smart-ed1f6f18-95e7-4d4c-b62e-402f47dc44ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646170398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.646170398
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3631866316
Short name T980
Test name
Test status
Simulation time 9056421518 ps
CPU time 91.66 seconds
Started Feb 22 01:05:54 PM PST 24
Finished Feb 22 01:07:26 PM PST 24
Peak memory 209208 kb
Host smart-58cc189a-57ce-4e63-b919-5363bb1ac959
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631866316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3631866316
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2924489060
Short name T966
Test name
Test status
Simulation time 57572828 ps
CPU time 2.75 seconds
Started Feb 22 01:05:54 PM PST 24
Finished Feb 22 01:05:57 PM PST 24
Peak memory 208044 kb
Host smart-a34babde-c691-4c82-a1e2-dd7f3bc3831b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924489060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2924489060
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3026502597
Short name T770
Test name
Test status
Simulation time 135110650 ps
CPU time 3.6 seconds
Started Feb 22 01:05:51 PM PST 24
Finished Feb 22 01:05:55 PM PST 24
Peak memory 208624 kb
Host smart-8cbf1f32-76ac-47b8-a000-231b1c1dc9b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026502597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3026502597
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2346623539
Short name T806
Test name
Test status
Simulation time 97069471 ps
CPU time 2.93 seconds
Started Feb 22 01:05:52 PM PST 24
Finished Feb 22 01:05:55 PM PST 24
Peak memory 207972 kb
Host smart-38ec52dd-882b-438e-849e-b789fac0ae33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346623539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2346623539
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2571069057
Short name T407
Test name
Test status
Simulation time 161470116 ps
CPU time 3.78 seconds
Started Feb 22 01:05:56 PM PST 24
Finished Feb 22 01:06:00 PM PST 24
Peak memory 208212 kb
Host smart-1aefa07f-16bc-4ecb-9e6f-d4d391b8abc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571069057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2571069057
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2409195046
Short name T206
Test name
Test status
Simulation time 249897628 ps
CPU time 7.09 seconds
Started Feb 22 01:05:56 PM PST 24
Finished Feb 22 01:06:04 PM PST 24
Peak memory 222540 kb
Host smart-77d87515-1326-4578-99f6-08bbcbdfd1b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409195046 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2409195046
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1454792722
Short name T364
Test name
Test status
Simulation time 1670864060 ps
CPU time 10.28 seconds
Started Feb 22 01:05:55 PM PST 24
Finished Feb 22 01:06:06 PM PST 24
Peak memory 209048 kb
Host smart-c750b00c-3a6f-478f-9b07-b857706bc6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454792722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1454792722
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3465026991
Short name T617
Test name
Test status
Simulation time 243930691 ps
CPU time 2.84 seconds
Started Feb 22 01:05:55 PM PST 24
Finished Feb 22 01:05:58 PM PST 24
Peak memory 210148 kb
Host smart-b2a5ed43-18e4-4852-9f57-6f5387f33cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465026991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3465026991
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2690932103
Short name T441
Test name
Test status
Simulation time 14667752 ps
CPU time 0.79 seconds
Started Feb 22 01:07:53 PM PST 24
Finished Feb 22 01:07:54 PM PST 24
Peak memory 205868 kb
Host smart-ce0642d8-b9c8-444f-a8e0-56f5e42f1944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690932103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2690932103
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.633629623
Short name T434
Test name
Test status
Simulation time 374921586 ps
CPU time 10.45 seconds
Started Feb 22 01:07:49 PM PST 24
Finished Feb 22 01:07:59 PM PST 24
Peak memory 222424 kb
Host smart-2f65708d-d62b-4bc3-b65a-297b8a3f2076
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=633629623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.633629623
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.4186457563
Short name T18
Test name
Test status
Simulation time 135734036 ps
CPU time 1.77 seconds
Started Feb 22 01:07:51 PM PST 24
Finished Feb 22 01:07:53 PM PST 24
Peak memory 208692 kb
Host smart-377089e9-0722-4d99-8e26-d5af29233f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186457563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.4186457563
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3716806988
Short name T615
Test name
Test status
Simulation time 90488841 ps
CPU time 1.86 seconds
Started Feb 22 01:08:08 PM PST 24
Finished Feb 22 01:08:11 PM PST 24
Peak memory 207148 kb
Host smart-9a7d290e-4a33-4dc4-b151-cedddea374cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716806988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3716806988
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.4285988366
Short name T89
Test name
Test status
Simulation time 1908817461 ps
CPU time 40.43 seconds
Started Feb 22 01:07:51 PM PST 24
Finished Feb 22 01:08:32 PM PST 24
Peak memory 214236 kb
Host smart-ff882bee-9a7f-4e52-a61d-81caf733f3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285988366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.4285988366
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3146043403
Short name T304
Test name
Test status
Simulation time 589089141 ps
CPU time 22.59 seconds
Started Feb 22 01:07:46 PM PST 24
Finished Feb 22 01:08:09 PM PST 24
Peak memory 210644 kb
Host smart-1a1bfc00-6661-46b0-831d-190d7945c988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146043403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3146043403
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1711389365
Short name T234
Test name
Test status
Simulation time 45238893 ps
CPU time 2.83 seconds
Started Feb 22 01:07:56 PM PST 24
Finished Feb 22 01:07:59 PM PST 24
Peak memory 218944 kb
Host smart-2dc2289f-ed44-4657-9ba7-ba462998e462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711389365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1711389365
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3130469487
Short name T616
Test name
Test status
Simulation time 715532223 ps
CPU time 14.88 seconds
Started Feb 22 01:07:47 PM PST 24
Finished Feb 22 01:08:02 PM PST 24
Peak memory 208312 kb
Host smart-0831ab3c-e0b9-483e-a43a-68e3d2b993f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130469487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3130469487
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1561709255
Short name T958
Test name
Test status
Simulation time 159332478 ps
CPU time 2 seconds
Started Feb 22 01:07:52 PM PST 24
Finished Feb 22 01:07:55 PM PST 24
Peak memory 208456 kb
Host smart-1ff861a3-7f6d-463e-b298-d0cc11b16ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561709255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1561709255
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2347008416
Short name T418
Test name
Test status
Simulation time 83672315 ps
CPU time 2.61 seconds
Started Feb 22 01:07:49 PM PST 24
Finished Feb 22 01:07:52 PM PST 24
Peak memory 206904 kb
Host smart-332d5812-32d2-4460-840f-c8ec62eade1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347008416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2347008416
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.33843319
Short name T883
Test name
Test status
Simulation time 258123838 ps
CPU time 3.46 seconds
Started Feb 22 01:07:49 PM PST 24
Finished Feb 22 01:07:53 PM PST 24
Peak memory 208724 kb
Host smart-1be665b5-44ba-4358-8159-5863ad5ea218
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33843319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.33843319
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.892069167
Short name T606
Test name
Test status
Simulation time 75377792 ps
CPU time 3.54 seconds
Started Feb 22 01:07:48 PM PST 24
Finished Feb 22 01:07:51 PM PST 24
Peak memory 208516 kb
Host smart-7fd407d3-fa87-40de-a25f-f6344760d6be
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892069167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.892069167
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.358002896
Short name T758
Test name
Test status
Simulation time 93411177 ps
CPU time 3.83 seconds
Started Feb 22 01:07:48 PM PST 24
Finished Feb 22 01:07:52 PM PST 24
Peak memory 214284 kb
Host smart-2c682f86-bf02-4190-8d80-97d110f8b1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358002896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.358002896
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.975364178
Short name T741
Test name
Test status
Simulation time 340384055 ps
CPU time 4.64 seconds
Started Feb 22 01:07:54 PM PST 24
Finished Feb 22 01:07:59 PM PST 24
Peak memory 208536 kb
Host smart-c834ef6c-2f06-44d5-ad9c-0825d0e38623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975364178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.975364178
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.944034624
Short name T887
Test name
Test status
Simulation time 520377908 ps
CPU time 8.43 seconds
Started Feb 22 01:07:52 PM PST 24
Finished Feb 22 01:08:02 PM PST 24
Peak memory 220100 kb
Host smart-80f1101c-c3ad-46fc-8982-ad522de6fa98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944034624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.944034624
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3923663235
Short name T1041
Test name
Test status
Simulation time 88963472 ps
CPU time 2.42 seconds
Started Feb 22 01:07:50 PM PST 24
Finished Feb 22 01:07:53 PM PST 24
Peak memory 222576 kb
Host smart-6eae7659-0ece-47c8-83a2-c62007eade6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923663235 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.3923663235
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1295573047
Short name T768
Test name
Test status
Simulation time 331287190 ps
CPU time 4.08 seconds
Started Feb 22 01:07:53 PM PST 24
Finished Feb 22 01:07:58 PM PST 24
Peak memory 209420 kb
Host smart-4ab5d90a-5b9b-4d48-8a85-f0c2c6c0a9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295573047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1295573047
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.498683194
Short name T78
Test name
Test status
Simulation time 116548276 ps
CPU time 2.29 seconds
Started Feb 22 01:07:52 PM PST 24
Finished Feb 22 01:07:55 PM PST 24
Peak memory 209936 kb
Host smart-768978ac-1a32-4668-869c-2fd275a8e13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498683194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.498683194
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2405517830
Short name T1045
Test name
Test status
Simulation time 18376834 ps
CPU time 0.77 seconds
Started Feb 22 01:07:49 PM PST 24
Finished Feb 22 01:07:50 PM PST 24
Peak memory 205816 kb
Host smart-ecc3129a-c25a-4aab-926f-c9badd179996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405517830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2405517830
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2037844353
Short name T233
Test name
Test status
Simulation time 105296013 ps
CPU time 6.36 seconds
Started Feb 22 01:07:52 PM PST 24
Finished Feb 22 01:07:58 PM PST 24
Peak memory 214296 kb
Host smart-912b5d5e-1d30-4fc2-8e75-a527f3282dfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2037844353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2037844353
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.370321278
Short name T812
Test name
Test status
Simulation time 110638706 ps
CPU time 2.69 seconds
Started Feb 22 01:07:54 PM PST 24
Finished Feb 22 01:07:57 PM PST 24
Peak memory 208808 kb
Host smart-1e0d1b17-c5b0-4e2e-a15d-882f3ee079c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370321278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.370321278
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.418229019
Short name T894
Test name
Test status
Simulation time 763798372 ps
CPU time 5.09 seconds
Started Feb 22 01:07:55 PM PST 24
Finished Feb 22 01:08:00 PM PST 24
Peak memory 209076 kb
Host smart-590ac19c-c3ff-4e45-a86f-119fac3d818e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418229019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.418229019
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2253506775
Short name T865
Test name
Test status
Simulation time 397246519 ps
CPU time 6.7 seconds
Started Feb 22 01:07:52 PM PST 24
Finished Feb 22 01:07:59 PM PST 24
Peak memory 220772 kb
Host smart-08d45ddb-4d95-4281-9a1c-38b4c878a83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253506775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2253506775
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1935571428
Short name T417
Test name
Test status
Simulation time 413499936 ps
CPU time 1.68 seconds
Started Feb 22 01:07:50 PM PST 24
Finished Feb 22 01:07:53 PM PST 24
Peak memory 206124 kb
Host smart-3ca1eb32-afc1-4c14-a255-d76f9df37d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935571428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1935571428
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2192011469
Short name T919
Test name
Test status
Simulation time 103044519 ps
CPU time 3.35 seconds
Started Feb 22 01:07:52 PM PST 24
Finished Feb 22 01:07:57 PM PST 24
Peak memory 218572 kb
Host smart-99dc602c-cb52-4170-8e34-febad132e723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192011469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2192011469
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2038599630
Short name T990
Test name
Test status
Simulation time 140570612 ps
CPU time 5.61 seconds
Started Feb 22 01:07:56 PM PST 24
Finished Feb 22 01:08:02 PM PST 24
Peak memory 206696 kb
Host smart-38d04d4a-5cc5-4d7f-8516-b048a990faee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038599630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2038599630
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3729033257
Short name T1038
Test name
Test status
Simulation time 2766701255 ps
CPU time 7.45 seconds
Started Feb 22 01:07:53 PM PST 24
Finished Feb 22 01:08:01 PM PST 24
Peak memory 208100 kb
Host smart-b665bf92-2f5b-4e59-b641-81c2dc7b868e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729033257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3729033257
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2753606041
Short name T950
Test name
Test status
Simulation time 733992871 ps
CPU time 2.73 seconds
Started Feb 22 01:07:52 PM PST 24
Finished Feb 22 01:07:56 PM PST 24
Peak memory 208540 kb
Host smart-38f2fda5-52db-4f3c-ae6e-b4e701861e1b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753606041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2753606041
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.936791157
Short name T598
Test name
Test status
Simulation time 114122392 ps
CPU time 2.99 seconds
Started Feb 22 01:07:47 PM PST 24
Finished Feb 22 01:07:50 PM PST 24
Peak memory 206928 kb
Host smart-86d7638b-75a2-42bb-9105-f8de3123777e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936791157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.936791157
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.756481092
Short name T189
Test name
Test status
Simulation time 58788123 ps
CPU time 2.96 seconds
Started Feb 22 01:07:52 PM PST 24
Finished Feb 22 01:07:56 PM PST 24
Peak memory 209728 kb
Host smart-5ffa286b-cb23-4bff-afe5-900939fad1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756481092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.756481092
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2557851465
Short name T686
Test name
Test status
Simulation time 179305672 ps
CPU time 4.3 seconds
Started Feb 22 01:07:53 PM PST 24
Finished Feb 22 01:07:58 PM PST 24
Peak memory 208344 kb
Host smart-55f96bdb-5c88-4adc-8918-3fac8611d969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557851465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2557851465
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3584154936
Short name T968
Test name
Test status
Simulation time 601002242 ps
CPU time 4.89 seconds
Started Feb 22 01:07:52 PM PST 24
Finished Feb 22 01:07:58 PM PST 24
Peak memory 221708 kb
Host smart-6ee91416-8459-4556-b530-670566b66eb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584154936 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3584154936
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2228173918
Short name T239
Test name
Test status
Simulation time 130125023 ps
CPU time 5.2 seconds
Started Feb 22 01:07:51 PM PST 24
Finished Feb 22 01:07:57 PM PST 24
Peak memory 218480 kb
Host smart-b8e19f8b-79ba-48c2-afef-21c3027072e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228173918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2228173918
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3880381818
Short name T698
Test name
Test status
Simulation time 172407897 ps
CPU time 2.47 seconds
Started Feb 22 01:07:53 PM PST 24
Finished Feb 22 01:07:56 PM PST 24
Peak memory 210308 kb
Host smart-f71482cc-e55c-4fd6-b893-20a1c27c3739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880381818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3880381818
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3520367539
Short name T1066
Test name
Test status
Simulation time 98062374 ps
CPU time 0.78 seconds
Started Feb 22 01:07:50 PM PST 24
Finished Feb 22 01:07:52 PM PST 24
Peak memory 205840 kb
Host smart-c829c3ca-7520-421a-b000-57c2a8d9f39a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520367539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3520367539
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2230228103
Short name T435
Test name
Test status
Simulation time 54383397 ps
CPU time 4.23 seconds
Started Feb 22 01:07:53 PM PST 24
Finished Feb 22 01:07:58 PM PST 24
Peak memory 214260 kb
Host smart-a637ea78-80b1-437c-8fcd-f64c9be38c3b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230228103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2230228103
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2298769721
Short name T164
Test name
Test status
Simulation time 108208997 ps
CPU time 3.5 seconds
Started Feb 22 01:07:56 PM PST 24
Finished Feb 22 01:08:00 PM PST 24
Peak memory 217800 kb
Host smart-d4a1a1d6-16b0-48b6-97f4-ccd32002f7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298769721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2298769721
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.772233890
Short name T316
Test name
Test status
Simulation time 16286364671 ps
CPU time 62.13 seconds
Started Feb 22 01:07:47 PM PST 24
Finished Feb 22 01:08:49 PM PST 24
Peak memory 214436 kb
Host smart-6c20bcda-a6e4-4ef9-9687-117969e0163d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772233890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.772233890
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1656076916
Short name T334
Test name
Test status
Simulation time 526950227 ps
CPU time 5.2 seconds
Started Feb 22 01:07:53 PM PST 24
Finished Feb 22 01:07:59 PM PST 24
Peak memory 222384 kb
Host smart-1ec9441b-b97d-43bf-9ce4-04902f9f9fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656076916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1656076916
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3036294839
Short name T897
Test name
Test status
Simulation time 441226456 ps
CPU time 4.12 seconds
Started Feb 22 01:07:55 PM PST 24
Finished Feb 22 01:07:59 PM PST 24
Peak memory 214372 kb
Host smart-1f9cf89c-dc4a-4dd5-bc49-f51411f87549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036294839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3036294839
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1088203969
Short name T437
Test name
Test status
Simulation time 152674561 ps
CPU time 4.33 seconds
Started Feb 22 01:07:53 PM PST 24
Finished Feb 22 01:07:58 PM PST 24
Peak memory 209092 kb
Host smart-aa1289f3-fe1f-4f47-ad13-f026d7dcecf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088203969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1088203969
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4065862888
Short name T796
Test name
Test status
Simulation time 60858371 ps
CPU time 3.2 seconds
Started Feb 22 01:07:55 PM PST 24
Finished Feb 22 01:07:58 PM PST 24
Peak memory 206636 kb
Host smart-ca5a1848-9ad6-4090-b4a5-0cfe3db47335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065862888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4065862888
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1195213620
Short name T682
Test name
Test status
Simulation time 3146810392 ps
CPU time 58.79 seconds
Started Feb 22 01:07:54 PM PST 24
Finished Feb 22 01:08:53 PM PST 24
Peak memory 208772 kb
Host smart-8a8aec2d-cdfe-4e4f-8f53-dbd0f1a73e92
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195213620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1195213620
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3549216023
Short name T875
Test name
Test status
Simulation time 49053042 ps
CPU time 2.67 seconds
Started Feb 22 01:07:53 PM PST 24
Finished Feb 22 01:07:56 PM PST 24
Peak memory 207064 kb
Host smart-6c1ffe08-6a2b-4295-9094-893c58425dd2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549216023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3549216023
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.4010623428
Short name T360
Test name
Test status
Simulation time 234276439 ps
CPU time 4.22 seconds
Started Feb 22 01:07:52 PM PST 24
Finished Feb 22 01:07:58 PM PST 24
Peak memory 208608 kb
Host smart-c9f5f0f9-a5b6-44a4-aca3-5b0f108f4dbe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010623428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.4010623428
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3539810735
Short name T830
Test name
Test status
Simulation time 192674419 ps
CPU time 4.32 seconds
Started Feb 22 01:07:53 PM PST 24
Finished Feb 22 01:07:58 PM PST 24
Peak memory 210004 kb
Host smart-aefa6fd3-1144-40f5-bfd8-449cb435d2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539810735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3539810735
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2464645624
Short name T568
Test name
Test status
Simulation time 530397225 ps
CPU time 4.03 seconds
Started Feb 22 01:07:50 PM PST 24
Finished Feb 22 01:07:54 PM PST 24
Peak memory 206680 kb
Host smart-96d75008-75b7-42ff-8443-356605d7c554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464645624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2464645624
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3566364770
Short name T403
Test name
Test status
Simulation time 318536909 ps
CPU time 6.86 seconds
Started Feb 22 01:07:59 PM PST 24
Finished Feb 22 01:08:08 PM PST 24
Peak memory 219024 kb
Host smart-bb18a050-7052-4ca9-8436-02c583a1f564
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566364770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3566364770
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.77341212
Short name T663
Test name
Test status
Simulation time 118197582 ps
CPU time 4.05 seconds
Started Feb 22 01:07:59 PM PST 24
Finished Feb 22 01:08:04 PM PST 24
Peak memory 218864 kb
Host smart-951ccaf7-249a-417f-baf8-f66d9a8ed79c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77341212 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.77341212
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.559610377
Short name T289
Test name
Test status
Simulation time 876269205 ps
CPU time 10.72 seconds
Started Feb 22 01:08:04 PM PST 24
Finished Feb 22 01:08:14 PM PST 24
Peak memory 208968 kb
Host smart-e7af158b-00da-4172-874c-e2986a70382c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559610377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.559610377
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.4176447329
Short name T1059
Test name
Test status
Simulation time 3785062640 ps
CPU time 7.54 seconds
Started Feb 22 01:07:54 PM PST 24
Finished Feb 22 01:08:02 PM PST 24
Peak memory 211420 kb
Host smart-892f9781-6968-4c49-afa4-91b99ca1bd2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176447329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.4176447329
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3120396988
Short name T98
Test name
Test status
Simulation time 22568282 ps
CPU time 0.81 seconds
Started Feb 22 01:08:19 PM PST 24
Finished Feb 22 01:08:20 PM PST 24
Peak memory 205856 kb
Host smart-e023f78f-feaa-4ff0-a8cf-105e3e522cb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120396988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3120396988
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3020084516
Short name T774
Test name
Test status
Simulation time 316558239 ps
CPU time 3.62 seconds
Started Feb 22 01:08:14 PM PST 24
Finished Feb 22 01:08:18 PM PST 24
Peak memory 221696 kb
Host smart-6ac0767f-c257-4132-8738-abbd3c133f19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020084516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3020084516
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2737751868
Short name T851
Test name
Test status
Simulation time 305548941 ps
CPU time 3.2 seconds
Started Feb 22 01:07:55 PM PST 24
Finished Feb 22 01:07:58 PM PST 24
Peak memory 207488 kb
Host smart-de6964d5-6802-4fe2-be27-7a95377f3074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737751868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2737751868
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2541636076
Short name T908
Test name
Test status
Simulation time 305250438 ps
CPU time 7.2 seconds
Started Feb 22 01:08:14 PM PST 24
Finished Feb 22 01:08:22 PM PST 24
Peak memory 219000 kb
Host smart-9f063151-0eba-4d80-bb2e-583b1e929154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541636076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2541636076
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.566777879
Short name T695
Test name
Test status
Simulation time 102754863 ps
CPU time 3.37 seconds
Started Feb 22 01:07:50 PM PST 24
Finished Feb 22 01:07:55 PM PST 24
Peak memory 208264 kb
Host smart-5575bae5-0f38-4f07-9cbf-e2ead7b2e5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566777879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.566777879
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.478413368
Short name T286
Test name
Test status
Simulation time 73838599 ps
CPU time 3.61 seconds
Started Feb 22 01:07:55 PM PST 24
Finished Feb 22 01:07:58 PM PST 24
Peak memory 206832 kb
Host smart-92c60e8f-0a60-4d9d-848c-88a0d3921c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478413368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.478413368
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3150409555
Short name T833
Test name
Test status
Simulation time 42054046 ps
CPU time 2.31 seconds
Started Feb 22 01:07:53 PM PST 24
Finished Feb 22 01:07:56 PM PST 24
Peak memory 206796 kb
Host smart-08f61cb0-f20c-4976-9bd1-2ec7bf6aa0d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150409555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3150409555
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3354829790
Short name T658
Test name
Test status
Simulation time 290055288 ps
CPU time 7.61 seconds
Started Feb 22 01:07:54 PM PST 24
Finished Feb 22 01:08:02 PM PST 24
Peak memory 207924 kb
Host smart-b772abad-2734-4e8d-b2b4-2ea50e9a4d77
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354829790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3354829790
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2808029698
Short name T696
Test name
Test status
Simulation time 10948627684 ps
CPU time 33.98 seconds
Started Feb 22 01:07:56 PM PST 24
Finished Feb 22 01:08:30 PM PST 24
Peak memory 208144 kb
Host smart-0dc3f1d0-23ab-4cb5-84e7-581d96566277
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808029698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2808029698
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2632645633
Short name T414
Test name
Test status
Simulation time 1252427810 ps
CPU time 9.2 seconds
Started Feb 22 01:07:57 PM PST 24
Finished Feb 22 01:08:07 PM PST 24
Peak memory 207904 kb
Host smart-f5237817-0115-40f2-ae29-d33619a8f3ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632645633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2632645633
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1934299160
Short name T920
Test name
Test status
Simulation time 61600688 ps
CPU time 3.14 seconds
Started Feb 22 01:08:24 PM PST 24
Finished Feb 22 01:08:28 PM PST 24
Peak memory 215876 kb
Host smart-1177e242-2d56-4b91-8a98-3bc14a6e2075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934299160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1934299160
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1131228910
Short name T124
Test name
Test status
Simulation time 103596834 ps
CPU time 3.46 seconds
Started Feb 22 01:07:54 PM PST 24
Finished Feb 22 01:07:58 PM PST 24
Peak memory 208300 kb
Host smart-2ca07b0e-dd24-43ff-b47b-0acc0bbf6a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131228910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1131228910
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3690295997
Short name T690
Test name
Test status
Simulation time 441503142 ps
CPU time 11.46 seconds
Started Feb 22 01:08:12 PM PST 24
Finished Feb 22 01:08:24 PM PST 24
Peak memory 209684 kb
Host smart-237911f8-6059-4ef1-9243-c5587663a01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690295997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3690295997
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.4107265014
Short name T599
Test name
Test status
Simulation time 155060437 ps
CPU time 5.21 seconds
Started Feb 22 01:08:17 PM PST 24
Finished Feb 22 01:08:22 PM PST 24
Peak memory 210392 kb
Host smart-555527c9-74af-49ec-b9f7-e0ca8563197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107265014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.4107265014
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1186184059
Short name T828
Test name
Test status
Simulation time 41617269 ps
CPU time 0.74 seconds
Started Feb 22 01:08:18 PM PST 24
Finished Feb 22 01:08:20 PM PST 24
Peak memory 205856 kb
Host smart-e592d875-45fa-48de-ac7e-7cc9db89126b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186184059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1186184059
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.316279868
Short name T970
Test name
Test status
Simulation time 92038255 ps
CPU time 5.08 seconds
Started Feb 22 01:08:12 PM PST 24
Finished Feb 22 01:08:18 PM PST 24
Peak memory 214300 kb
Host smart-aaefe901-1202-4c86-a28b-7d5e3a93839a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=316279868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.316279868
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3001283096
Short name T67
Test name
Test status
Simulation time 391654196 ps
CPU time 2.54 seconds
Started Feb 22 01:08:13 PM PST 24
Finished Feb 22 01:08:17 PM PST 24
Peak memory 217784 kb
Host smart-2b53c672-5158-4915-822c-4e20bb6c78ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001283096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3001283096
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.625211832
Short name T88
Test name
Test status
Simulation time 188965725 ps
CPU time 5.23 seconds
Started Feb 22 01:08:22 PM PST 24
Finished Feb 22 01:08:28 PM PST 24
Peak memory 209840 kb
Host smart-54427578-b8ce-44f2-93ee-0a4f369e9f8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625211832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.625211832
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1041809314
Short name T291
Test name
Test status
Simulation time 279689997 ps
CPU time 5.05 seconds
Started Feb 22 01:08:22 PM PST 24
Finished Feb 22 01:08:28 PM PST 24
Peak memory 214188 kb
Host smart-e61023b0-f2e8-4fb8-94bf-b493a30b78ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041809314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1041809314
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.853342945
Short name T771
Test name
Test status
Simulation time 111719742 ps
CPU time 4.03 seconds
Started Feb 22 01:08:22 PM PST 24
Finished Feb 22 01:08:28 PM PST 24
Peak memory 214284 kb
Host smart-74a2261f-46d3-4a2a-86a5-0fdd69abcb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853342945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.853342945
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2487131323
Short name T829
Test name
Test status
Simulation time 68370215 ps
CPU time 3.28 seconds
Started Feb 22 01:08:14 PM PST 24
Finished Feb 22 01:08:18 PM PST 24
Peak memory 214520 kb
Host smart-56fea66b-a1ea-46c6-a40d-758523711e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487131323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2487131323
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2963549574
Short name T994
Test name
Test status
Simulation time 61985517 ps
CPU time 2.49 seconds
Started Feb 22 01:08:13 PM PST 24
Finished Feb 22 01:08:16 PM PST 24
Peak memory 206856 kb
Host smart-b4f15ce3-903c-417d-9796-fc8713d95f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963549574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2963549574
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1275634307
Short name T363
Test name
Test status
Simulation time 255059908 ps
CPU time 7.5 seconds
Started Feb 22 01:08:20 PM PST 24
Finished Feb 22 01:08:28 PM PST 24
Peak memory 208804 kb
Host smart-73fbba74-7c1a-43ae-ab8f-c799cc36ca30
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275634307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1275634307
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2431790193
Short name T972
Test name
Test status
Simulation time 221767077 ps
CPU time 3.94 seconds
Started Feb 22 01:08:26 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 208480 kb
Host smart-98f6be50-92be-42c5-8bdc-72e1ffb1ccb8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431790193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2431790193
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3144479202
Short name T630
Test name
Test status
Simulation time 189853416 ps
CPU time 6.92 seconds
Started Feb 22 01:08:13 PM PST 24
Finished Feb 22 01:08:21 PM PST 24
Peak memory 208528 kb
Host smart-cd527ee1-10d1-4f60-aed1-f554a16651c6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144479202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3144479202
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.573593494
Short name T997
Test name
Test status
Simulation time 195034050 ps
CPU time 2.5 seconds
Started Feb 22 01:08:23 PM PST 24
Finished Feb 22 01:08:26 PM PST 24
Peak memory 214220 kb
Host smart-fdd60a79-c884-4522-8ff6-6be90b0c7ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573593494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.573593494
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1187643321
Short name T714
Test name
Test status
Simulation time 406532275 ps
CPU time 3.58 seconds
Started Feb 22 01:08:17 PM PST 24
Finished Feb 22 01:08:22 PM PST 24
Peak memory 208436 kb
Host smart-d158ba7e-85a2-4132-9eba-02bf176a25dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187643321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1187643321
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1753178635
Short name T219
Test name
Test status
Simulation time 481372452 ps
CPU time 13.33 seconds
Started Feb 22 01:08:14 PM PST 24
Finished Feb 22 01:08:28 PM PST 24
Peak memory 215504 kb
Host smart-52aee2c2-efdf-4a9e-a449-f0f6437e114d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753178635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1753178635
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.353326387
Short name T974
Test name
Test status
Simulation time 193604235 ps
CPU time 4.99 seconds
Started Feb 22 01:08:22 PM PST 24
Finished Feb 22 01:08:28 PM PST 24
Peak memory 208276 kb
Host smart-e0788e27-753a-4f9c-966a-4075032bee1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353326387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.353326387
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3315097063
Short name T574
Test name
Test status
Simulation time 98611981 ps
CPU time 1.01 seconds
Started Feb 22 01:08:12 PM PST 24
Finished Feb 22 01:08:14 PM PST 24
Peak memory 206044 kb
Host smart-b9f9671a-7c93-49be-8dae-25c35f9a7c2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315097063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3315097063
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2338906084
Short name T337
Test name
Test status
Simulation time 1471111679 ps
CPU time 47.28 seconds
Started Feb 22 01:08:22 PM PST 24
Finished Feb 22 01:09:10 PM PST 24
Peak memory 214380 kb
Host smart-b6971d11-dc4d-4c50-9be0-de71149a5274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338906084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2338906084
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3111726369
Short name T1028
Test name
Test status
Simulation time 11051716098 ps
CPU time 106.31 seconds
Started Feb 22 01:08:20 PM PST 24
Finished Feb 22 01:10:07 PM PST 24
Peak memory 214348 kb
Host smart-389fb082-8fff-4c05-8ad0-afb777f1365c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111726369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3111726369
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3526361230
Short name T732
Test name
Test status
Simulation time 334971285 ps
CPU time 4.43 seconds
Started Feb 22 01:08:13 PM PST 24
Finished Feb 22 01:08:19 PM PST 24
Peak memory 210324 kb
Host smart-f046203d-7024-439b-a075-c4ac695082ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526361230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3526361230
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3095407345
Short name T226
Test name
Test status
Simulation time 501413597 ps
CPU time 5.54 seconds
Started Feb 22 01:08:20 PM PST 24
Finished Feb 22 01:08:26 PM PST 24
Peak memory 207928 kb
Host smart-452d5a62-5528-4334-bac5-07fb4c6412b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095407345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3095407345
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.4258579595
Short name T287
Test name
Test status
Simulation time 198461128 ps
CPU time 3.79 seconds
Started Feb 22 01:08:18 PM PST 24
Finished Feb 22 01:08:23 PM PST 24
Peak memory 210452 kb
Host smart-6373338b-54bd-4300-ab54-b2c152387add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258579595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.4258579595
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3967892909
Short name T804
Test name
Test status
Simulation time 719969059 ps
CPU time 5.22 seconds
Started Feb 22 01:08:17 PM PST 24
Finished Feb 22 01:08:23 PM PST 24
Peak memory 206920 kb
Host smart-33c3335e-7c80-4d62-8a49-38daae7d3b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967892909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3967892909
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2575766253
Short name T204
Test name
Test status
Simulation time 35663192 ps
CPU time 2.27 seconds
Started Feb 22 01:08:10 PM PST 24
Finished Feb 22 01:08:13 PM PST 24
Peak memory 206684 kb
Host smart-7ba9b495-04ab-405b-a26a-33c8802abb87
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575766253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2575766253
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1387942742
Short name T595
Test name
Test status
Simulation time 23588655 ps
CPU time 2.02 seconds
Started Feb 22 01:08:14 PM PST 24
Finished Feb 22 01:08:17 PM PST 24
Peak memory 208472 kb
Host smart-85b9c6b5-24be-4e8b-85f6-e46b39f96574
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387942742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1387942742
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.703012750
Short name T651
Test name
Test status
Simulation time 137836924 ps
CPU time 3.52 seconds
Started Feb 22 01:08:22 PM PST 24
Finished Feb 22 01:08:26 PM PST 24
Peak memory 208444 kb
Host smart-021f8f5f-7423-41c9-9986-ac936727c5c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703012750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.703012750
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3607986126
Short name T739
Test name
Test status
Simulation time 34849227 ps
CPU time 2.18 seconds
Started Feb 22 01:08:22 PM PST 24
Finished Feb 22 01:08:25 PM PST 24
Peak memory 215828 kb
Host smart-4fa9f862-2db0-47f6-8715-bf5b11dd8cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607986126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3607986126
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.4029892242
Short name T1053
Test name
Test status
Simulation time 78963442 ps
CPU time 2.35 seconds
Started Feb 22 01:08:14 PM PST 24
Finished Feb 22 01:08:17 PM PST 24
Peak memory 206940 kb
Host smart-b98ade52-ce57-4fad-8ca5-0bc53bc20da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029892242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.4029892242
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1652387588
Short name T750
Test name
Test status
Simulation time 98199246 ps
CPU time 3.76 seconds
Started Feb 22 01:08:26 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 219860 kb
Host smart-fb090cfd-e195-4548-88ae-ff9751ffe907
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652387588 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1652387588
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1141181450
Short name T279
Test name
Test status
Simulation time 227095163 ps
CPU time 3.14 seconds
Started Feb 22 01:08:12 PM PST 24
Finished Feb 22 01:08:16 PM PST 24
Peak memory 207932 kb
Host smart-000e9e56-45eb-4123-8538-f3a249520709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141181450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1141181450
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1812345491
Short name T825
Test name
Test status
Simulation time 43328297 ps
CPU time 2.35 seconds
Started Feb 22 01:08:17 PM PST 24
Finished Feb 22 01:08:20 PM PST 24
Peak memory 210112 kb
Host smart-27abe69b-a883-4230-923a-2e72ca99b1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812345491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1812345491
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3871339563
Short name T805
Test name
Test status
Simulation time 31873210 ps
CPU time 0.89 seconds
Started Feb 22 01:08:12 PM PST 24
Finished Feb 22 01:08:14 PM PST 24
Peak memory 205868 kb
Host smart-4eea7cc2-30e9-4cb1-8aac-9dd3f42b7661
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871339563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3871339563
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.967756226
Short name T1008
Test name
Test status
Simulation time 4627318800 ps
CPU time 63.43 seconds
Started Feb 22 01:08:14 PM PST 24
Finished Feb 22 01:09:18 PM PST 24
Peak memory 215316 kb
Host smart-1600f749-10fc-48bf-8de9-3869822986f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=967756226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.967756226
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2208035358
Short name T979
Test name
Test status
Simulation time 209197353 ps
CPU time 2.69 seconds
Started Feb 22 01:08:26 PM PST 24
Finished Feb 22 01:08:30 PM PST 24
Peak memory 220904 kb
Host smart-9703475d-9b72-49ac-9825-276ed106796f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208035358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2208035358
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.4223299081
Short name T246
Test name
Test status
Simulation time 272810641 ps
CPU time 1.82 seconds
Started Feb 22 01:08:18 PM PST 24
Finished Feb 22 01:08:20 PM PST 24
Peak memory 208920 kb
Host smart-902fa60d-441c-4e0c-99ac-31237a5a0032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223299081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.4223299081
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.291278211
Short name T861
Test name
Test status
Simulation time 200313243 ps
CPU time 3.34 seconds
Started Feb 22 01:08:13 PM PST 24
Finished Feb 22 01:08:17 PM PST 24
Peak memory 209168 kb
Host smart-cb00778b-e53a-497a-9ed1-3a637753e7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291278211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.291278211
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.4224675988
Short name T996
Test name
Test status
Simulation time 259403064 ps
CPU time 3.63 seconds
Started Feb 22 01:08:12 PM PST 24
Finished Feb 22 01:08:17 PM PST 24
Peak memory 210876 kb
Host smart-b26d6efd-294d-47ff-8220-88deae70a7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224675988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4224675988
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1539128466
Short name T692
Test name
Test status
Simulation time 137130765 ps
CPU time 2.93 seconds
Started Feb 22 01:08:23 PM PST 24
Finished Feb 22 01:08:26 PM PST 24
Peak memory 207384 kb
Host smart-3442354d-bbd9-4c79-9cbd-3c413e413db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539128466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1539128466
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.4262736423
Short name T840
Test name
Test status
Simulation time 91790830 ps
CPU time 3.46 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:32 PM PST 24
Peak memory 209780 kb
Host smart-1a746b9e-7484-4397-b868-af5d6da59777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262736423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.4262736423
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.492828574
Short name T79
Test name
Test status
Simulation time 148736088 ps
CPU time 3.16 seconds
Started Feb 22 01:08:26 PM PST 24
Finished Feb 22 01:08:30 PM PST 24
Peak memory 208412 kb
Host smart-1846aadb-a29c-49e6-a7e6-c500cbcda5d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492828574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.492828574
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1493533497
Short name T591
Test name
Test status
Simulation time 196712688 ps
CPU time 4.79 seconds
Started Feb 22 01:08:20 PM PST 24
Finished Feb 22 01:08:25 PM PST 24
Peak memory 208684 kb
Host smart-787920b2-8f84-43e9-924e-70d34504cceb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493533497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1493533497
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2565924000
Short name T610
Test name
Test status
Simulation time 80037253 ps
CPU time 1.87 seconds
Started Feb 22 01:08:21 PM PST 24
Finished Feb 22 01:08:23 PM PST 24
Peak memory 207288 kb
Host smart-edd14240-c69a-4982-b013-2626848b289d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565924000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2565924000
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.4259708255
Short name T839
Test name
Test status
Simulation time 2535947708 ps
CPU time 9.66 seconds
Started Feb 22 01:08:20 PM PST 24
Finished Feb 22 01:08:30 PM PST 24
Peak memory 207940 kb
Host smart-d9a80500-35cc-46a7-a828-872ee693207c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259708255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.4259708255
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.128855698
Short name T940
Test name
Test status
Simulation time 79547932 ps
CPU time 2.69 seconds
Started Feb 22 01:08:11 PM PST 24
Finished Feb 22 01:08:14 PM PST 24
Peak memory 210096 kb
Host smart-83ce9a09-2119-4c02-8ad8-3a879aabfa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128855698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.128855698
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2262373965
Short name T797
Test name
Test status
Simulation time 1511947902 ps
CPU time 4.07 seconds
Started Feb 22 01:08:19 PM PST 24
Finished Feb 22 01:08:24 PM PST 24
Peak memory 208460 kb
Host smart-ca8f15bc-14cd-4a17-a1a1-b81c06732884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262373965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2262373965
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3776717003
Short name T900
Test name
Test status
Simulation time 78852321 ps
CPU time 2.59 seconds
Started Feb 22 01:08:10 PM PST 24
Finished Feb 22 01:08:12 PM PST 24
Peak memory 222672 kb
Host smart-9ad6eaf6-8ae6-4bbb-be2a-20d847c7bc9f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776717003 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3776717003
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.888677985
Short name T763
Test name
Test status
Simulation time 110316409 ps
CPU time 4.99 seconds
Started Feb 22 01:08:19 PM PST 24
Finished Feb 22 01:08:25 PM PST 24
Peak memory 208956 kb
Host smart-db3ff055-9df9-48f5-9680-ec98863d4e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888677985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.888677985
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.160458763
Short name T734
Test name
Test status
Simulation time 4098704239 ps
CPU time 34.13 seconds
Started Feb 22 01:08:17 PM PST 24
Finished Feb 22 01:08:51 PM PST 24
Peak memory 211664 kb
Host smart-d5df244d-9c34-4e7e-a6c9-fff34296d258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160458763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.160458763
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.512031038
Short name T442
Test name
Test status
Simulation time 11227140 ps
CPU time 0.73 seconds
Started Feb 22 01:08:18 PM PST 24
Finished Feb 22 01:08:20 PM PST 24
Peak memory 205876 kb
Host smart-f126fab5-f76c-460e-915b-22de0dbb7a7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512031038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.512031038
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3084590735
Short name T953
Test name
Test status
Simulation time 423673319 ps
CPU time 2.67 seconds
Started Feb 22 01:08:20 PM PST 24
Finished Feb 22 01:08:24 PM PST 24
Peak memory 207024 kb
Host smart-3c595f19-8663-4e60-a8c4-f636d02c6f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084590735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3084590735
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.4218608398
Short name T1046
Test name
Test status
Simulation time 1279654367 ps
CPU time 8.81 seconds
Started Feb 22 01:08:22 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 214296 kb
Host smart-71e7d92b-3a85-415b-86c3-c8c2c9877cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218608398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.4218608398
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.738071788
Short name T815
Test name
Test status
Simulation time 1461684351 ps
CPU time 10.72 seconds
Started Feb 22 01:08:20 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 222384 kb
Host smart-ff5562ca-3a8c-46f2-9286-3ca37d088ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738071788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.738071788
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.4251986923
Short name T969
Test name
Test status
Simulation time 464591364 ps
CPU time 3.84 seconds
Started Feb 22 01:08:15 PM PST 24
Finished Feb 22 01:08:20 PM PST 24
Peak memory 214972 kb
Host smart-de3762df-90a3-457e-ae82-38b6b6e64738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251986923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.4251986923
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2935371451
Short name T1007
Test name
Test status
Simulation time 70308083 ps
CPU time 2.79 seconds
Started Feb 22 01:08:26 PM PST 24
Finished Feb 22 01:08:30 PM PST 24
Peak memory 209756 kb
Host smart-ff784477-9a52-400b-93fb-1ad4ac01d8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935371451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2935371451
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1526819580
Short name T1011
Test name
Test status
Simulation time 403557668 ps
CPU time 4.18 seconds
Started Feb 22 01:08:14 PM PST 24
Finished Feb 22 01:08:19 PM PST 24
Peak memory 206608 kb
Host smart-570adb56-cb57-423a-b67d-b0f271554ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526819580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1526819580
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1275662442
Short name T743
Test name
Test status
Simulation time 35972173 ps
CPU time 2.37 seconds
Started Feb 22 01:08:12 PM PST 24
Finished Feb 22 01:08:15 PM PST 24
Peak memory 206908 kb
Host smart-ef00e61c-13a1-44cd-9222-57f0005937dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275662442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1275662442
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3290339005
Short name T585
Test name
Test status
Simulation time 431421985 ps
CPU time 4.15 seconds
Started Feb 22 01:08:13 PM PST 24
Finished Feb 22 01:08:18 PM PST 24
Peak memory 207520 kb
Host smart-04bfabeb-e95e-41c8-8076-84378daa3bd1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290339005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3290339005
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1404055392
Short name T854
Test name
Test status
Simulation time 111340262 ps
CPU time 4.42 seconds
Started Feb 22 01:08:13 PM PST 24
Finished Feb 22 01:08:18 PM PST 24
Peak memory 208728 kb
Host smart-a7dbcd57-3703-42c6-b900-a34d7f4bc8f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404055392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1404055392
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1778221750
Short name T760
Test name
Test status
Simulation time 25424953 ps
CPU time 1.92 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:30 PM PST 24
Peak memory 207044 kb
Host smart-dae2a232-dc26-4d57-96e3-de498b13dc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778221750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1778221750
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1539951682
Short name T704
Test name
Test status
Simulation time 71054035 ps
CPU time 3.21 seconds
Started Feb 22 01:08:16 PM PST 24
Finished Feb 22 01:08:20 PM PST 24
Peak memory 208380 kb
Host smart-efc1e601-1470-4d98-a282-e9fc0185f881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539951682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1539951682
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3809717304
Short name T329
Test name
Test status
Simulation time 4073216697 ps
CPU time 16.97 seconds
Started Feb 22 01:08:27 PM PST 24
Finished Feb 22 01:08:45 PM PST 24
Peak memory 216624 kb
Host smart-5a661455-8cf6-4ec7-8bc7-655183d57d96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809717304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3809717304
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1007112908
Short name T893
Test name
Test status
Simulation time 323341320 ps
CPU time 7.1 seconds
Started Feb 22 01:08:12 PM PST 24
Finished Feb 22 01:08:20 PM PST 24
Peak memory 218412 kb
Host smart-c83a8cfd-1780-4646-b2df-905b73f3f40b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007112908 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1007112908
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.833211844
Short name T699
Test name
Test status
Simulation time 198067721 ps
CPU time 7.63 seconds
Started Feb 22 01:08:21 PM PST 24
Finished Feb 22 01:08:29 PM PST 24
Peak memory 209284 kb
Host smart-64d6cd04-8c67-45e1-8c4a-fdc4b738111b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833211844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.833211844
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3391049899
Short name T411
Test name
Test status
Simulation time 270337134 ps
CPU time 2.62 seconds
Started Feb 22 01:08:21 PM PST 24
Finished Feb 22 01:08:24 PM PST 24
Peak memory 209912 kb
Host smart-3346ff94-cf24-4af7-8b31-12c29c2f7252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391049899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3391049899
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1443468132
Short name T653
Test name
Test status
Simulation time 11985531 ps
CPU time 0.75 seconds
Started Feb 22 01:08:18 PM PST 24
Finished Feb 22 01:08:19 PM PST 24
Peak memory 205772 kb
Host smart-93bc2d49-a027-4aee-ae7b-7d0a15936748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443468132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1443468132
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1762841181
Short name T963
Test name
Test status
Simulation time 124088136 ps
CPU time 6.65 seconds
Started Feb 22 01:08:21 PM PST 24
Finished Feb 22 01:08:28 PM PST 24
Peak memory 215348 kb
Host smart-d786a189-89f2-4fa0-8bc8-5345f51d4524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762841181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1762841181
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.4082130786
Short name T24
Test name
Test status
Simulation time 181973727 ps
CPU time 4.19 seconds
Started Feb 22 01:08:22 PM PST 24
Finished Feb 22 01:08:27 PM PST 24
Peak memory 221640 kb
Host smart-bd00b845-48ec-4b01-8515-f1adf8e39dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082130786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.4082130786
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2141820350
Short name T982
Test name
Test status
Simulation time 4975709904 ps
CPU time 18.27 seconds
Started Feb 22 01:08:13 PM PST 24
Finished Feb 22 01:08:32 PM PST 24
Peak memory 218340 kb
Host smart-68802970-da95-463c-af93-5d4a7f2a45ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141820350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2141820350
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3546514271
Short name T332
Test name
Test status
Simulation time 1476483834 ps
CPU time 19.02 seconds
Started Feb 22 01:08:14 PM PST 24
Finished Feb 22 01:08:34 PM PST 24
Peak memory 209260 kb
Host smart-fbbdc9cf-db34-409f-bfb0-ec74f179959b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546514271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3546514271
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.598930749
Short name T1001
Test name
Test status
Simulation time 357918875 ps
CPU time 2.71 seconds
Started Feb 22 01:08:20 PM PST 24
Finished Feb 22 01:08:23 PM PST 24
Peak memory 209212 kb
Host smart-c48a5bca-c85f-4119-a430-7fad5413b37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598930749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.598930749
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.736088007
Short name T1022
Test name
Test status
Simulation time 545791069 ps
CPU time 2.55 seconds
Started Feb 22 01:08:17 PM PST 24
Finished Feb 22 01:08:20 PM PST 24
Peak memory 207772 kb
Host smart-0a57f20e-6192-401a-aad2-74bdea5d2cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736088007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.736088007
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3882402697
Short name T197
Test name
Test status
Simulation time 89236122 ps
CPU time 4.07 seconds
Started Feb 22 01:08:22 PM PST 24
Finished Feb 22 01:08:26 PM PST 24
Peak memory 208796 kb
Host smart-cdd8effa-d8ce-4be9-8970-e273d19a9193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882402697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3882402697
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.484977167
Short name T283
Test name
Test status
Simulation time 2104958944 ps
CPU time 22.77 seconds
Started Feb 22 01:08:15 PM PST 24
Finished Feb 22 01:08:38 PM PST 24
Peak memory 208628 kb
Host smart-c153f6a2-ca63-4a28-9843-586951562ddc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484977167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.484977167
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3372769490
Short name T353
Test name
Test status
Simulation time 230499968 ps
CPU time 7.51 seconds
Started Feb 22 01:08:13 PM PST 24
Finished Feb 22 01:08:21 PM PST 24
Peak memory 208552 kb
Host smart-96bf57e6-d1a7-4a33-ad27-7b272c983303
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372769490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3372769490
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.352882701
Short name T727
Test name
Test status
Simulation time 830297757 ps
CPU time 20.14 seconds
Started Feb 22 01:08:13 PM PST 24
Finished Feb 22 01:08:34 PM PST 24
Peak memory 208728 kb
Host smart-42d799f5-c45e-49eb-b83a-e75bc3d10999
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352882701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.352882701
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1375857189
Short name T964
Test name
Test status
Simulation time 229947198 ps
CPU time 3.22 seconds
Started Feb 22 01:08:26 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 208180 kb
Host smart-7797c44d-b938-40d3-b873-f8acc4b8ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375857189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1375857189
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1601527268
Short name T718
Test name
Test status
Simulation time 1049266462 ps
CPU time 10.88 seconds
Started Feb 22 01:08:29 PM PST 24
Finished Feb 22 01:08:40 PM PST 24
Peak memory 207672 kb
Host smart-3e5e0ccb-0125-458e-9b67-2d613a7d111c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601527268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1601527268
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.925141538
Short name T42
Test name
Test status
Simulation time 11089754533 ps
CPU time 73.21 seconds
Started Feb 22 01:08:14 PM PST 24
Finished Feb 22 01:09:28 PM PST 24
Peak memory 216132 kb
Host smart-a1a4bfb1-0aa8-4969-aff2-26f0d97470fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925141538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.925141538
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.810850608
Short name T762
Test name
Test status
Simulation time 772682110 ps
CPU time 6.11 seconds
Started Feb 22 01:08:21 PM PST 24
Finished Feb 22 01:08:28 PM PST 24
Peak memory 209768 kb
Host smart-cd367b32-2926-444e-8386-18c3131d56db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810850608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.810850608
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2712368672
Short name T708
Test name
Test status
Simulation time 281281049 ps
CPU time 3.06 seconds
Started Feb 22 01:08:13 PM PST 24
Finished Feb 22 01:08:17 PM PST 24
Peak memory 210596 kb
Host smart-739ad911-dcb7-429c-999e-94ebe7adca8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712368672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2712368672
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2411839817
Short name T620
Test name
Test status
Simulation time 33758538 ps
CPU time 0.79 seconds
Started Feb 22 01:08:24 PM PST 24
Finished Feb 22 01:08:26 PM PST 24
Peak memory 205832 kb
Host smart-05e99123-a711-4a0b-bcda-f999450b2bab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411839817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2411839817
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2438601489
Short name T705
Test name
Test status
Simulation time 171065952 ps
CPU time 1.79 seconds
Started Feb 22 01:08:27 PM PST 24
Finished Feb 22 01:08:29 PM PST 24
Peak memory 207000 kb
Host smart-08ac1ed9-8023-47f8-a965-08ec2d341ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438601489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2438601489
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.982182950
Short name T850
Test name
Test status
Simulation time 124296869 ps
CPU time 5.73 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:34 PM PST 24
Peak memory 214280 kb
Host smart-5882a2b5-f013-440d-8b0d-6b65120f925b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982182950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.982182950
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3695398223
Short name T687
Test name
Test status
Simulation time 107294032 ps
CPU time 2.15 seconds
Started Feb 22 01:08:20 PM PST 24
Finished Feb 22 01:08:22 PM PST 24
Peak memory 214820 kb
Host smart-f684ce05-e0f3-4efe-9aea-e9404b3eb7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695398223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3695398223
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.411276539
Short name T365
Test name
Test status
Simulation time 315483583 ps
CPU time 3.81 seconds
Started Feb 22 01:08:27 PM PST 24
Finished Feb 22 01:08:32 PM PST 24
Peak memory 209460 kb
Host smart-1b17784e-c9d9-43e1-91f7-b9d4e8b42e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411276539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.411276539
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3839480553
Short name T605
Test name
Test status
Simulation time 2943232853 ps
CPU time 30.65 seconds
Started Feb 22 01:08:22 PM PST 24
Finished Feb 22 01:08:53 PM PST 24
Peak memory 207852 kb
Host smart-ddfc0546-0244-4dc0-b03b-b5091319aec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839480553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3839480553
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.887280730
Short name T1000
Test name
Test status
Simulation time 337146099 ps
CPU time 3.28 seconds
Started Feb 22 01:08:14 PM PST 24
Finished Feb 22 01:08:18 PM PST 24
Peak memory 206744 kb
Host smart-423aa46f-ac42-4bd3-a517-ccf6910c2a59
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887280730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.887280730
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.429552619
Short name T285
Test name
Test status
Simulation time 158544235 ps
CPU time 2.31 seconds
Started Feb 22 01:08:22 PM PST 24
Finished Feb 22 01:08:25 PM PST 24
Peak memory 206928 kb
Host smart-76790798-0eb1-4163-88fb-8a66180d4717
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429552619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.429552619
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.4043088773
Short name T871
Test name
Test status
Simulation time 21825334471 ps
CPU time 68.55 seconds
Started Feb 22 01:08:21 PM PST 24
Finished Feb 22 01:09:30 PM PST 24
Peak memory 209272 kb
Host smart-91cb6e39-0230-4592-a045-6f662c73ff42
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043088773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.4043088773
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.680579652
Short name T341
Test name
Test status
Simulation time 100513437 ps
CPU time 2.79 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 209208 kb
Host smart-eda04f2b-c8c1-43bf-b39b-05c0f262637a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680579652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.680579652
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2247551006
Short name T636
Test name
Test status
Simulation time 63281826 ps
CPU time 3.06 seconds
Started Feb 22 01:08:13 PM PST 24
Finished Feb 22 01:08:16 PM PST 24
Peak memory 207896 kb
Host smart-587bf4d3-fa82-45b8-89c7-10e38d98354a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247551006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2247551006
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1852804052
Short name T1042
Test name
Test status
Simulation time 2244517220 ps
CPU time 52.36 seconds
Started Feb 22 01:08:15 PM PST 24
Finished Feb 22 01:09:09 PM PST 24
Peak memory 216688 kb
Host smart-7848f92d-36fa-441b-b40f-55ff060eddbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852804052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1852804052
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2040562887
Short name T211
Test name
Test status
Simulation time 184523990 ps
CPU time 5.03 seconds
Started Feb 22 01:08:15 PM PST 24
Finished Feb 22 01:08:21 PM PST 24
Peak memory 219244 kb
Host smart-d768c99b-ec6b-4c71-9e78-e65e13bc0588
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040562887 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2040562887
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1172215007
Short name T1025
Test name
Test status
Simulation time 1441742263 ps
CPU time 8.15 seconds
Started Feb 22 01:08:20 PM PST 24
Finished Feb 22 01:08:29 PM PST 24
Peak memory 218028 kb
Host smart-08a9ec57-80b9-4ccb-ab70-1d9c39b3afc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172215007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1172215007
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1214343571
Short name T949
Test name
Test status
Simulation time 199329973 ps
CPU time 2.17 seconds
Started Feb 22 01:08:15 PM PST 24
Finished Feb 22 01:08:18 PM PST 24
Peak memory 210056 kb
Host smart-f366a3c5-eea7-4b91-9277-e5373a6f7525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214343571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1214343571
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.720572712
Short name T99
Test name
Test status
Simulation time 45142159 ps
CPU time 0.77 seconds
Started Feb 22 01:05:52 PM PST 24
Finished Feb 22 01:05:53 PM PST 24
Peak memory 205896 kb
Host smart-b9b282e1-3a78-4670-b932-73e6d9a1c740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720572712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.720572712
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2358874506
Short name T814
Test name
Test status
Simulation time 37759637 ps
CPU time 1.89 seconds
Started Feb 22 01:05:54 PM PST 24
Finished Feb 22 01:05:57 PM PST 24
Peak memory 222776 kb
Host smart-03b46896-a647-45f2-95d6-7fa1551a8cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358874506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2358874506
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.382123033
Short name T655
Test name
Test status
Simulation time 299841421 ps
CPU time 3.88 seconds
Started Feb 22 01:05:49 PM PST 24
Finished Feb 22 01:05:53 PM PST 24
Peak memory 207720 kb
Host smart-9b97f6df-75ff-4d92-a62b-b8f314d4aaab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382123033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.382123033
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.650516759
Short name T90
Test name
Test status
Simulation time 146611741 ps
CPU time 2.74 seconds
Started Feb 22 01:05:57 PM PST 24
Finished Feb 22 01:06:00 PM PST 24
Peak memory 214284 kb
Host smart-e9bc77f2-07e8-4163-bd8f-6ec8fc4d068d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650516759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.650516759
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.4167156612
Short name T831
Test name
Test status
Simulation time 54996464 ps
CPU time 2.8 seconds
Started Feb 22 01:05:50 PM PST 24
Finished Feb 22 01:05:53 PM PST 24
Peak memory 219744 kb
Host smart-7d3df3dd-cdc0-4dc2-8018-eb58ca1e7960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167156612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.4167156612
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.753026474
Short name T343
Test name
Test status
Simulation time 1020758002 ps
CPU time 8.73 seconds
Started Feb 22 01:05:51 PM PST 24
Finished Feb 22 01:06:00 PM PST 24
Peak memory 218312 kb
Host smart-71cdf0a4-b0dc-463e-99a6-dd6a899a07f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753026474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.753026474
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.119955139
Short name T12
Test name
Test status
Simulation time 1024196087 ps
CPU time 28.67 seconds
Started Feb 22 01:05:56 PM PST 24
Finished Feb 22 01:06:25 PM PST 24
Peak memory 238272 kb
Host smart-2c6805f9-67ae-48a8-9b0f-648e4fe13eff
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119955139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.119955139
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3400117177
Short name T676
Test name
Test status
Simulation time 71146468 ps
CPU time 1.66 seconds
Started Feb 22 01:05:54 PM PST 24
Finished Feb 22 01:05:56 PM PST 24
Peak memory 206852 kb
Host smart-f061a6cc-559e-4fb4-806b-25cc0c25db02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400117177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3400117177
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.814900055
Short name T387
Test name
Test status
Simulation time 673248097 ps
CPU time 17.24 seconds
Started Feb 22 01:05:50 PM PST 24
Finished Feb 22 01:06:07 PM PST 24
Peak memory 208504 kb
Host smart-6e171c6f-1da0-449f-bedf-3601c7aeb74b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814900055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.814900055
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.604847410
Short name T644
Test name
Test status
Simulation time 276898263 ps
CPU time 8.12 seconds
Started Feb 22 01:05:53 PM PST 24
Finished Feb 22 01:06:01 PM PST 24
Peak memory 208692 kb
Host smart-794df4c9-ca0d-49cd-ab84-00605e23c163
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604847410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.604847410
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1140873761
Short name T809
Test name
Test status
Simulation time 37877917 ps
CPU time 2.35 seconds
Started Feb 22 01:05:52 PM PST 24
Finished Feb 22 01:05:54 PM PST 24
Peak memory 207024 kb
Host smart-70075402-9904-47fa-9c90-dceef6c8cbf8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140873761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1140873761
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.633657630
Short name T196
Test name
Test status
Simulation time 318986353 ps
CPU time 4.22 seconds
Started Feb 22 01:05:51 PM PST 24
Finished Feb 22 01:05:55 PM PST 24
Peak memory 208148 kb
Host smart-ac2c732c-66c3-488c-bbc8-c34a49e10770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633657630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.633657630
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.957308017
Short name T584
Test name
Test status
Simulation time 75072141 ps
CPU time 2.91 seconds
Started Feb 22 01:05:50 PM PST 24
Finished Feb 22 01:05:53 PM PST 24
Peak memory 208356 kb
Host smart-d2c0b2c5-652f-4803-bac6-46a53d7b7020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957308017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.957308017
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2754771771
Short name T937
Test name
Test status
Simulation time 1464948485 ps
CPU time 44.42 seconds
Started Feb 22 01:05:57 PM PST 24
Finished Feb 22 01:06:41 PM PST 24
Peak memory 222500 kb
Host smart-8c25b902-94bd-42a0-abb2-9a9fbe88d383
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754771771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2754771771
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1895926348
Short name T1039
Test name
Test status
Simulation time 1283057816 ps
CPU time 11.95 seconds
Started Feb 22 01:05:56 PM PST 24
Finished Feb 22 01:06:08 PM PST 24
Peak memory 222616 kb
Host smart-08c5c136-db29-48c5-afad-bcb0a82d69d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895926348 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1895926348
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3255483830
Short name T701
Test name
Test status
Simulation time 238671725 ps
CPU time 5.61 seconds
Started Feb 22 01:05:56 PM PST 24
Finished Feb 22 01:06:02 PM PST 24
Peak memory 218260 kb
Host smart-073f4081-f281-454e-9c6f-6af4b2163430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255483830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3255483830
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.4044031545
Short name T401
Test name
Test status
Simulation time 123442600 ps
CPU time 3.3 seconds
Started Feb 22 01:05:54 PM PST 24
Finished Feb 22 01:05:58 PM PST 24
Peak memory 210008 kb
Host smart-58c35408-a2b7-4cfe-9c33-1098ecfd3f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044031545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.4044031545
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1228279577
Short name T688
Test name
Test status
Simulation time 10832009 ps
CPU time 0.8 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:29 PM PST 24
Peak memory 205816 kb
Host smart-6cf1f067-60f2-4b08-9edd-fb167aea28c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228279577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1228279577
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1596418985
Short name T228
Test name
Test status
Simulation time 58480259 ps
CPU time 4.21 seconds
Started Feb 22 01:08:26 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 214272 kb
Host smart-7e5a2dd4-1218-4c85-837d-06824f92d94e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1596418985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1596418985
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1078144236
Short name T212
Test name
Test status
Simulation time 106617077 ps
CPU time 3.34 seconds
Started Feb 22 01:08:26 PM PST 24
Finished Feb 22 01:08:29 PM PST 24
Peak memory 221564 kb
Host smart-78bef97c-ee0a-4881-97aa-0299802bcce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078144236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1078144236
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1852948045
Short name T51
Test name
Test status
Simulation time 1024874367 ps
CPU time 10.51 seconds
Started Feb 22 01:08:20 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 209212 kb
Host smart-e79452e2-97d1-4a1a-b2a9-0368e6bb97e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852948045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1852948045
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2657316293
Short name T800
Test name
Test status
Simulation time 121279426 ps
CPU time 4.73 seconds
Started Feb 22 01:08:27 PM PST 24
Finished Feb 22 01:08:33 PM PST 24
Peak memory 209644 kb
Host smart-4c55612b-0921-4565-85d9-5262531dbdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657316293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2657316293
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2617477485
Short name T277
Test name
Test status
Simulation time 90217630 ps
CPU time 4.65 seconds
Started Feb 22 01:08:27 PM PST 24
Finished Feb 22 01:08:32 PM PST 24
Peak memory 211676 kb
Host smart-e0b9234a-f0c8-49e9-9cd6-480ee44f19c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617477485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2617477485
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3041252590
Short name T215
Test name
Test status
Simulation time 89177323 ps
CPU time 2.78 seconds
Started Feb 22 01:08:27 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 218360 kb
Host smart-e8e7baf0-4687-432a-8291-a77ca8f657e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041252590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3041252590
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.163603409
Short name T429
Test name
Test status
Simulation time 349245128 ps
CPU time 9.88 seconds
Started Feb 22 01:08:21 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 209308 kb
Host smart-bb54b422-3323-4f50-bc32-73defbab59a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163603409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.163603409
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3787066556
Short name T580
Test name
Test status
Simulation time 36803643 ps
CPU time 2.32 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 205996 kb
Host smart-db2a144b-87bd-41bc-a427-71965a0095f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787066556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3787066556
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.279072753
Short name T933
Test name
Test status
Simulation time 125565626 ps
CPU time 2.2 seconds
Started Feb 22 01:08:26 PM PST 24
Finished Feb 22 01:08:28 PM PST 24
Peak memory 206760 kb
Host smart-094740ce-594b-484b-b5ec-f3558b8c9102
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279072753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.279072753
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.347507934
Short name T801
Test name
Test status
Simulation time 77151887 ps
CPU time 3.83 seconds
Started Feb 22 01:08:30 PM PST 24
Finished Feb 22 01:08:34 PM PST 24
Peak memory 208468 kb
Host smart-77512ac5-0e50-4b37-bb93-1d85078f959e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347507934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.347507934
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1970496170
Short name T662
Test name
Test status
Simulation time 919217162 ps
CPU time 6.57 seconds
Started Feb 22 01:08:29 PM PST 24
Finished Feb 22 01:08:35 PM PST 24
Peak memory 207868 kb
Host smart-9855e133-1389-4f7b-82fd-aee7b7782817
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970496170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1970496170
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1085066301
Short name T635
Test name
Test status
Simulation time 39903246 ps
CPU time 1.97 seconds
Started Feb 22 01:08:26 PM PST 24
Finished Feb 22 01:08:30 PM PST 24
Peak memory 208604 kb
Host smart-e8180594-793f-4f08-8e17-07023962c257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085066301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1085066301
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2882965344
Short name T820
Test name
Test status
Simulation time 676133359 ps
CPU time 5.04 seconds
Started Feb 22 01:08:24 PM PST 24
Finished Feb 22 01:08:30 PM PST 24
Peak memory 208284 kb
Host smart-80ea5724-c2ad-445e-959a-c4ccb0d0ac0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882965344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2882965344
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2902842364
Short name T237
Test name
Test status
Simulation time 562807445 ps
CPU time 7.18 seconds
Started Feb 22 01:08:27 PM PST 24
Finished Feb 22 01:08:34 PM PST 24
Peak memory 222496 kb
Host smart-1d044809-751f-4b69-8abd-f4bb3d0b67ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902842364 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2902842364
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.936854345
Short name T438
Test name
Test status
Simulation time 410163113 ps
CPU time 4.59 seconds
Started Feb 22 01:08:23 PM PST 24
Finished Feb 22 01:08:28 PM PST 24
Peak memory 208944 kb
Host smart-bbe1d8e7-76e2-4335-a8e5-b1a929a566b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936854345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.936854345
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.891893162
Short name T712
Test name
Test status
Simulation time 101125518 ps
CPU time 2.02 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 210152 kb
Host smart-a6d1c5d1-27d0-423b-b4d1-ee17c93d2626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891893162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.891893162
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2446776152
Short name T957
Test name
Test status
Simulation time 36678339 ps
CPU time 0.82 seconds
Started Feb 22 01:08:29 PM PST 24
Finished Feb 22 01:08:30 PM PST 24
Peak memory 205836 kb
Host smart-4adc963a-b02f-400a-b229-a6a70a03a8c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446776152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2446776152
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.891743360
Short name T48
Test name
Test status
Simulation time 1305937603 ps
CPU time 6.97 seconds
Started Feb 22 01:08:24 PM PST 24
Finished Feb 22 01:08:32 PM PST 24
Peak memory 215908 kb
Host smart-ae263eae-8376-4547-99cb-7fab7b4232e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891743360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.891743360
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1637162245
Short name T59
Test name
Test status
Simulation time 149393383 ps
CPU time 2.44 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 206772 kb
Host smart-092a2956-9e55-4acc-a7af-654d95eb1813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637162245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1637162245
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3460820821
Short name T315
Test name
Test status
Simulation time 114656607 ps
CPU time 2.43 seconds
Started Feb 22 01:08:25 PM PST 24
Finished Feb 22 01:08:28 PM PST 24
Peak memory 208832 kb
Host smart-56f1bb84-c1a7-4c75-9a6f-7e69f03250ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460820821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3460820821
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2976585212
Short name T181
Test name
Test status
Simulation time 451760588 ps
CPU time 7.95 seconds
Started Feb 22 01:08:27 PM PST 24
Finished Feb 22 01:08:36 PM PST 24
Peak memory 219932 kb
Host smart-437afcda-e10f-476e-a749-c873dd9a7cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976585212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2976585212
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1886252417
Short name T261
Test name
Test status
Simulation time 82472244 ps
CPU time 3.77 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:32 PM PST 24
Peak memory 208212 kb
Host smart-8419fcb9-7216-4693-ab18-f2ca4df2d4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886252417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1886252417
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3619291327
Short name T985
Test name
Test status
Simulation time 91638987 ps
CPU time 4.21 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:33 PM PST 24
Peak memory 207536 kb
Host smart-54f3f330-3f19-4b06-a1af-98b1486d9dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619291327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3619291327
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.4226898220
Short name T1006
Test name
Test status
Simulation time 155132996 ps
CPU time 2.35 seconds
Started Feb 22 01:08:30 PM PST 24
Finished Feb 22 01:08:33 PM PST 24
Peak memory 206796 kb
Host smart-10f44b36-409a-4db5-9fa6-07976194093f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226898220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.4226898220
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3154347674
Short name T331
Test name
Test status
Simulation time 3260439118 ps
CPU time 37.24 seconds
Started Feb 22 01:08:29 PM PST 24
Finished Feb 22 01:09:06 PM PST 24
Peak memory 208960 kb
Host smart-ab4b60ab-84c4-40f3-98a2-eaad0d0f1824
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154347674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3154347674
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3013180556
Short name T647
Test name
Test status
Simulation time 85098821 ps
CPU time 3.51 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:32 PM PST 24
Peak memory 208580 kb
Host smart-9d16e344-d6a0-4bfd-8057-43d362f2ce20
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013180556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3013180556
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3851658544
Short name T895
Test name
Test status
Simulation time 175838191 ps
CPU time 3.2 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:32 PM PST 24
Peak memory 206988 kb
Host smart-946d7249-1ce2-4970-a237-b75664558b18
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851658544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3851658544
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2272927215
Short name T623
Test name
Test status
Simulation time 513740363 ps
CPU time 5.8 seconds
Started Feb 22 01:08:30 PM PST 24
Finished Feb 22 01:08:36 PM PST 24
Peak memory 214280 kb
Host smart-5be5cda1-3b47-46cb-8025-7da4e129ce36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272927215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2272927215
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1671568791
Short name T912
Test name
Test status
Simulation time 99134679 ps
CPU time 2.69 seconds
Started Feb 22 01:08:27 PM PST 24
Finished Feb 22 01:08:30 PM PST 24
Peak memory 206864 kb
Host smart-2c30e3be-dfee-4ac1-8eb7-aa66f96157d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671568791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1671568791
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1991306175
Short name T351
Test name
Test status
Simulation time 5043829720 ps
CPU time 24.56 seconds
Started Feb 22 01:08:29 PM PST 24
Finished Feb 22 01:08:54 PM PST 24
Peak memory 222492 kb
Host smart-4d75b90e-0197-4870-9961-e0c7a0a95492
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991306175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1991306175
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.479472461
Short name T744
Test name
Test status
Simulation time 199625853 ps
CPU time 7.47 seconds
Started Feb 22 01:08:25 PM PST 24
Finished Feb 22 01:08:33 PM PST 24
Peak memory 219560 kb
Host smart-8268f19d-7f18-4ef6-9bb5-2fe513440bf4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479472461 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.479472461
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.475077801
Short name T622
Test name
Test status
Simulation time 341695845 ps
CPU time 4.6 seconds
Started Feb 22 01:08:24 PM PST 24
Finished Feb 22 01:08:30 PM PST 24
Peak memory 206924 kb
Host smart-9356a8d7-5c92-4f8d-95c1-a0389ef5b2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475077801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.475077801
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1425352987
Short name T578
Test name
Test status
Simulation time 11090313 ps
CPU time 0.7 seconds
Started Feb 22 01:08:30 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 206012 kb
Host smart-a108fc99-09e4-434e-8a42-1b24dcbe723c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425352987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1425352987
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1750728236
Short name T302
Test name
Test status
Simulation time 1672450067 ps
CPU time 11.52 seconds
Started Feb 22 01:08:27 PM PST 24
Finished Feb 22 01:08:40 PM PST 24
Peak memory 214288 kb
Host smart-c01b6771-f9f7-4523-9a11-37d06b779d7c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1750728236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1750728236
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3541509787
Short name T601
Test name
Test status
Simulation time 439844016 ps
CPU time 12.73 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:41 PM PST 24
Peak memory 221680 kb
Host smart-f0815447-8bf4-43d5-8e8a-fcccaf5b8323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541509787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3541509787
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.285870197
Short name T68
Test name
Test status
Simulation time 94766718 ps
CPU time 2.94 seconds
Started Feb 22 01:08:23 PM PST 24
Finished Feb 22 01:08:27 PM PST 24
Peak memory 208780 kb
Host smart-25f0494f-a7e1-4177-9f75-55530643bb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285870197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.285870197
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.995457099
Short name T947
Test name
Test status
Simulation time 748935266 ps
CPU time 23.17 seconds
Started Feb 22 01:08:30 PM PST 24
Finished Feb 22 01:08:54 PM PST 24
Peak memory 214520 kb
Host smart-5c3127f2-cc76-40c6-a4d6-157ce1ba63e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995457099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.995457099
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3354017515
Short name T193
Test name
Test status
Simulation time 148903466 ps
CPU time 3.77 seconds
Started Feb 22 01:08:26 PM PST 24
Finished Feb 22 01:08:30 PM PST 24
Peak memory 209704 kb
Host smart-e6885905-f152-4e04-8be0-8986c4b6d7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354017515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3354017515
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2838604538
Short name T848
Test name
Test status
Simulation time 404296447 ps
CPU time 3.14 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:32 PM PST 24
Peak memory 220392 kb
Host smart-e23b53ea-4566-46ff-95be-bea0b41a62ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838604538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2838604538
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2335425393
Short name T1034
Test name
Test status
Simulation time 195146631 ps
CPU time 7.85 seconds
Started Feb 22 01:08:28 PM PST 24
Finished Feb 22 01:08:37 PM PST 24
Peak memory 218088 kb
Host smart-f542f787-a93c-40c6-b487-c89f19b6281d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335425393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2335425393
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3996987730
Short name T788
Test name
Test status
Simulation time 72755000 ps
CPU time 3.46 seconds
Started Feb 22 01:08:30 PM PST 24
Finished Feb 22 01:08:34 PM PST 24
Peak memory 208528 kb
Host smart-75247ded-1d73-4514-b1e8-a902427a7b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996987730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3996987730
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2829112056
Short name T785
Test name
Test status
Simulation time 135007512 ps
CPU time 4.86 seconds
Started Feb 22 01:08:29 PM PST 24
Finished Feb 22 01:08:34 PM PST 24
Peak memory 208584 kb
Host smart-21f68b8e-30c5-42ef-9c45-4fe5de588f51
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829112056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2829112056
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.946169218
Short name T643
Test name
Test status
Simulation time 102532601 ps
CPU time 3.61 seconds
Started Feb 22 01:08:26 PM PST 24
Finished Feb 22 01:08:30 PM PST 24
Peak memory 206796 kb
Host smart-203962bb-77cd-4232-96fb-22c103a75ea8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946169218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.946169218
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1985400942
Short name T642
Test name
Test status
Simulation time 398235160 ps
CPU time 3.52 seconds
Started Feb 22 01:08:25 PM PST 24
Finished Feb 22 01:08:29 PM PST 24
Peak memory 208696 kb
Host smart-bba7d385-3e95-418c-b249-23d438ebf05f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985400942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1985400942
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2023823202
Short name T308
Test name
Test status
Simulation time 61824599 ps
CPU time 2.75 seconds
Started Feb 22 01:08:30 PM PST 24
Finished Feb 22 01:08:33 PM PST 24
Peak memory 218736 kb
Host smart-3e181478-7d08-4116-9a3a-4c78bb92ca6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023823202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2023823202
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3017451942
Short name T123
Test name
Test status
Simulation time 103038975 ps
CPU time 1.75 seconds
Started Feb 22 01:08:29 PM PST 24
Finished Feb 22 01:08:31 PM PST 24
Peak memory 206076 kb
Host smart-31cf759c-68ff-4410-b647-f85ab845416b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017451942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3017451942
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2003685665
Short name T592
Test name
Test status
Simulation time 254418131 ps
CPU time 3.3 seconds
Started Feb 22 01:08:32 PM PST 24
Finished Feb 22 01:08:36 PM PST 24
Peak memory 222540 kb
Host smart-cb6f7d58-ab64-40e6-a961-ea67652c41fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003685665 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2003685665
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2472673246
Short name T1004
Test name
Test status
Simulation time 261892962 ps
CPU time 3.85 seconds
Started Feb 22 01:08:29 PM PST 24
Finished Feb 22 01:08:33 PM PST 24
Peak memory 208952 kb
Host smart-a5930402-9bed-4752-8a2c-9c170567b8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472673246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2472673246
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.876272707
Short name T38
Test name
Test status
Simulation time 804208915 ps
CPU time 3.2 seconds
Started Feb 22 01:08:30 PM PST 24
Finished Feb 22 01:08:34 PM PST 24
Peak memory 210088 kb
Host smart-c98e19fc-4467-44c7-bc71-2a2e29780740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876272707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.876272707
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2587432265
Short name T569
Test name
Test status
Simulation time 21247776 ps
CPU time 0.69 seconds
Started Feb 22 01:08:45 PM PST 24
Finished Feb 22 01:08:46 PM PST 24
Peak memory 205812 kb
Host smart-0dc24e68-cc07-48e9-b2d1-293899132cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587432265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2587432265
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1556144667
Short name T1026
Test name
Test status
Simulation time 318194124 ps
CPU time 4.65 seconds
Started Feb 22 01:08:40 PM PST 24
Finished Feb 22 01:08:45 PM PST 24
Peak memory 215364 kb
Host smart-0dbf6121-6e59-4053-bd6a-3f4ace6d85d2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1556144667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1556144667
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2033179615
Short name T30
Test name
Test status
Simulation time 85862322 ps
CPU time 3.84 seconds
Started Feb 22 01:08:44 PM PST 24
Finished Feb 22 01:08:48 PM PST 24
Peak memory 222796 kb
Host smart-a3706f11-0962-4706-a68a-3cca86d2ac28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033179615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2033179615
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.941325752
Short name T374
Test name
Test status
Simulation time 672645273 ps
CPU time 6.66 seconds
Started Feb 22 01:08:38 PM PST 24
Finished Feb 22 01:08:45 PM PST 24
Peak memory 209028 kb
Host smart-9bb3aad5-0e32-4796-b338-358367c0b446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941325752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.941325752
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.178884615
Short name T713
Test name
Test status
Simulation time 292954807 ps
CPU time 8.01 seconds
Started Feb 22 01:08:44 PM PST 24
Finished Feb 22 01:08:52 PM PST 24
Peak memory 214376 kb
Host smart-4c2f77ce-f25e-4e26-8975-12b7c9dd4ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178884615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.178884615
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1701770269
Short name T2
Test name
Test status
Simulation time 181878150 ps
CPU time 3.09 seconds
Started Feb 22 01:08:42 PM PST 24
Finished Feb 22 01:08:46 PM PST 24
Peak memory 208296 kb
Host smart-78fb4102-9452-4a2e-a888-95f775a3a3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701770269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1701770269
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2824994564
Short name T882
Test name
Test status
Simulation time 2857988175 ps
CPU time 67.09 seconds
Started Feb 22 01:08:43 PM PST 24
Finished Feb 22 01:09:51 PM PST 24
Peak memory 209388 kb
Host smart-41e094b0-54a0-4377-bb5c-57de336e0f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824994564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2824994564
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2419483350
Short name T862
Test name
Test status
Simulation time 1317435943 ps
CPU time 32.22 seconds
Started Feb 22 01:08:39 PM PST 24
Finished Feb 22 01:09:12 PM PST 24
Peak memory 208680 kb
Host smart-f9aa28de-3e47-4164-90cd-d243d759bd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419483350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2419483350
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3364464523
Short name T759
Test name
Test status
Simulation time 292283978 ps
CPU time 3.1 seconds
Started Feb 22 01:08:38 PM PST 24
Finished Feb 22 01:08:42 PM PST 24
Peak memory 208712 kb
Host smart-ee1b4aa5-9abe-4414-aa3d-988f9fdd1327
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364464523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3364464523
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2995130954
Short name T700
Test name
Test status
Simulation time 5273659301 ps
CPU time 34.97 seconds
Started Feb 22 01:08:43 PM PST 24
Finished Feb 22 01:09:18 PM PST 24
Peak memory 208032 kb
Host smart-76d67d44-5499-43e4-8e3b-73c686d595cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995130954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2995130954
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.961302599
Short name T938
Test name
Test status
Simulation time 134947755 ps
CPU time 2.87 seconds
Started Feb 22 01:08:46 PM PST 24
Finished Feb 22 01:08:49 PM PST 24
Peak memory 206904 kb
Host smart-da29104e-eb42-43f0-973d-f570e94f6f54
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961302599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.961302599
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.276872099
Short name T265
Test name
Test status
Simulation time 561598243 ps
CPU time 2.49 seconds
Started Feb 22 01:08:38 PM PST 24
Finished Feb 22 01:08:40 PM PST 24
Peak memory 218248 kb
Host smart-8495f5d7-2810-4656-b57c-4e79c3db26ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276872099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.276872099
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.257511528
Short name T945
Test name
Test status
Simulation time 90719978 ps
CPU time 2.69 seconds
Started Feb 22 01:08:38 PM PST 24
Finished Feb 22 01:08:41 PM PST 24
Peak memory 207228 kb
Host smart-796d398b-2df6-402a-8254-b03d439bb0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257511528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.257511528
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1249025012
Short name T380
Test name
Test status
Simulation time 284299554 ps
CPU time 8.36 seconds
Started Feb 22 01:08:42 PM PST 24
Finished Feb 22 01:08:51 PM PST 24
Peak memory 222580 kb
Host smart-31c2ecf1-39a3-4166-a871-e61926ab0cf9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249025012 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.1249025012
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3882185145
Short name T300
Test name
Test status
Simulation time 1353707187 ps
CPU time 10.54 seconds
Started Feb 22 01:08:36 PM PST 24
Finished Feb 22 01:08:47 PM PST 24
Peak memory 207944 kb
Host smart-58495fbf-e0a8-4778-b33b-6508311958e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882185145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3882185145
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1654011424
Short name T53
Test name
Test status
Simulation time 294573829 ps
CPU time 2.36 seconds
Started Feb 22 01:08:42 PM PST 24
Finished Feb 22 01:08:45 PM PST 24
Peak memory 210164 kb
Host smart-4cfbd326-79fc-4c56-99cc-880d4de53d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654011424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1654011424
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1360029356
Short name T607
Test name
Test status
Simulation time 14295848 ps
CPU time 0.76 seconds
Started Feb 22 01:08:48 PM PST 24
Finished Feb 22 01:08:48 PM PST 24
Peak memory 205812 kb
Host smart-3a7a8a08-02a3-41cb-ab37-bcc28d090c41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360029356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1360029356
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.4072284062
Short name T941
Test name
Test status
Simulation time 4795415431 ps
CPU time 6.19 seconds
Started Feb 22 01:08:48 PM PST 24
Finished Feb 22 01:08:54 PM PST 24
Peak memory 214264 kb
Host smart-01837755-bc9c-4aa2-9eda-73ef388aa0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072284062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.4072284062
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.4092722464
Short name T273
Test name
Test status
Simulation time 257229182 ps
CPU time 4.19 seconds
Started Feb 22 01:08:42 PM PST 24
Finished Feb 22 01:08:46 PM PST 24
Peak memory 218080 kb
Host smart-5757fb46-3852-4b50-89a4-a0076ae8ec86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092722464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.4092722464
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.4050456549
Short name T293
Test name
Test status
Simulation time 935360501 ps
CPU time 6.42 seconds
Started Feb 22 01:08:42 PM PST 24
Finished Feb 22 01:08:48 PM PST 24
Peak memory 219628 kb
Host smart-5e293001-7272-4348-a9d9-8f708498e963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050456549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.4050456549
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.855945093
Short name T853
Test name
Test status
Simulation time 40064687 ps
CPU time 2.31 seconds
Started Feb 22 01:08:39 PM PST 24
Finished Feb 22 01:08:41 PM PST 24
Peak memory 219760 kb
Host smart-342a17af-6e6c-4d3d-9992-a5424fdbb609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855945093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.855945093
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.887228360
Short name T971
Test name
Test status
Simulation time 152318047 ps
CPU time 4.05 seconds
Started Feb 22 01:08:42 PM PST 24
Finished Feb 22 01:08:46 PM PST 24
Peak memory 209296 kb
Host smart-e066c2d1-a35e-4d9e-b290-cf5653562cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887228360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.887228360
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.34385068
Short name T597
Test name
Test status
Simulation time 86862535 ps
CPU time 3.92 seconds
Started Feb 22 01:08:42 PM PST 24
Finished Feb 22 01:08:46 PM PST 24
Peak memory 208696 kb
Host smart-3ab0c296-8770-4421-997f-ca22953e807f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34385068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.34385068
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3811558121
Short name T661
Test name
Test status
Simulation time 307040091 ps
CPU time 8.67 seconds
Started Feb 22 01:08:41 PM PST 24
Finished Feb 22 01:08:50 PM PST 24
Peak memory 208332 kb
Host smart-56907713-e439-4b0f-85cc-08fae24fee69
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811558121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3811558121
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.34640125
Short name T899
Test name
Test status
Simulation time 189761229 ps
CPU time 2.79 seconds
Started Feb 22 01:08:44 PM PST 24
Finished Feb 22 01:08:47 PM PST 24
Peak memory 206892 kb
Host smart-15dc5243-1b69-4f1e-a205-6f5e3310c54b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34640125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.34640125
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.666636988
Short name T319
Test name
Test status
Simulation time 700599753 ps
CPU time 7.89 seconds
Started Feb 22 01:08:39 PM PST 24
Finished Feb 22 01:08:47 PM PST 24
Peak memory 208488 kb
Host smart-bc5101bb-5028-46e1-b7a8-ac90c797326a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666636988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.666636988
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.4086715344
Short name T200
Test name
Test status
Simulation time 379388464 ps
CPU time 5.68 seconds
Started Feb 22 01:08:43 PM PST 24
Finished Feb 22 01:08:49 PM PST 24
Peak memory 208128 kb
Host smart-bcf0a1dd-5c2a-4844-b12b-a08484cca1ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086715344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.4086715344
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1328522558
Short name T1051
Test name
Test status
Simulation time 129971094 ps
CPU time 2.37 seconds
Started Feb 22 01:08:40 PM PST 24
Finished Feb 22 01:08:42 PM PST 24
Peak memory 206620 kb
Host smart-6aa75f9c-7c53-42da-92de-cc0efc51a601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328522558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1328522558
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.4255693074
Short name T14
Test name
Test status
Simulation time 539381428 ps
CPU time 6.47 seconds
Started Feb 22 01:08:42 PM PST 24
Finished Feb 22 01:08:49 PM PST 24
Peak memory 218240 kb
Host smart-226284d9-d7c5-4882-aab5-4eed5d1cbda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255693074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.4255693074
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2980833289
Short name T932
Test name
Test status
Simulation time 41059759 ps
CPU time 2.11 seconds
Started Feb 22 01:09:05 PM PST 24
Finished Feb 22 01:09:08 PM PST 24
Peak memory 210120 kb
Host smart-e503dc8e-0e4b-4322-88a7-ef4429144765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980833289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2980833289
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.296798465
Short name T808
Test name
Test status
Simulation time 25474188 ps
CPU time 0.74 seconds
Started Feb 22 01:08:44 PM PST 24
Finished Feb 22 01:08:45 PM PST 24
Peak memory 205824 kb
Host smart-cc2d3528-0e4e-43b0-9e52-4af962455807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296798465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.296798465
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1660983401
Short name T355
Test name
Test status
Simulation time 120072448 ps
CPU time 4.09 seconds
Started Feb 22 01:08:45 PM PST 24
Finished Feb 22 01:08:49 PM PST 24
Peak memory 215184 kb
Host smart-cb46782c-aa7f-4a2b-936b-4b56355d1a53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1660983401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1660983401
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3629406160
Short name T730
Test name
Test status
Simulation time 71609339 ps
CPU time 2.96 seconds
Started Feb 22 01:08:47 PM PST 24
Finished Feb 22 01:08:50 PM PST 24
Peak memory 208452 kb
Host smart-48e2943c-04ff-4c47-8a12-1dea175c0464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629406160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3629406160
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.59274113
Short name T795
Test name
Test status
Simulation time 106847453 ps
CPU time 2.17 seconds
Started Feb 22 01:08:46 PM PST 24
Finished Feb 22 01:08:48 PM PST 24
Peak memory 208216 kb
Host smart-3e6ea077-8f2c-4a40-a7be-2b3a7d0ade1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59274113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.59274113
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.78788675
Short name T22
Test name
Test status
Simulation time 77632814 ps
CPU time 3.99 seconds
Started Feb 22 01:08:46 PM PST 24
Finished Feb 22 01:08:50 PM PST 24
Peak memory 208972 kb
Host smart-31454e43-54b5-43ec-9f40-1c872aa12d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78788675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.78788675
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1078297789
Short name T58
Test name
Test status
Simulation time 128153029 ps
CPU time 2.57 seconds
Started Feb 22 01:08:46 PM PST 24
Finished Feb 22 01:08:48 PM PST 24
Peak memory 207876 kb
Host smart-243396e1-f801-42b1-95db-bdeb6379edc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078297789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1078297789
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3332874591
Short name T238
Test name
Test status
Simulation time 390825933 ps
CPU time 5.85 seconds
Started Feb 22 01:08:46 PM PST 24
Finished Feb 22 01:08:52 PM PST 24
Peak memory 209292 kb
Host smart-7636a967-8662-4223-94c3-d561c69ceda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332874591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3332874591
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3311472850
Short name T866
Test name
Test status
Simulation time 687998651 ps
CPU time 6.75 seconds
Started Feb 22 01:08:44 PM PST 24
Finished Feb 22 01:08:51 PM PST 24
Peak memory 208524 kb
Host smart-3ea47b32-1c58-46b2-bad7-4fe1085792b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311472850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3311472850
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3374628673
Short name T924
Test name
Test status
Simulation time 138489524 ps
CPU time 4.27 seconds
Started Feb 22 01:08:45 PM PST 24
Finished Feb 22 01:08:49 PM PST 24
Peak memory 206952 kb
Host smart-f2acf292-40d0-453d-ac2a-71c8c8581813
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374628673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3374628673
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2234969372
Short name T959
Test name
Test status
Simulation time 54029698 ps
CPU time 2.91 seconds
Started Feb 22 01:08:42 PM PST 24
Finished Feb 22 01:08:45 PM PST 24
Peak memory 208556 kb
Host smart-c8f3033c-0bad-4f9f-9d20-84c7b7d66731
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234969372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2234969372
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2008362353
Short name T755
Test name
Test status
Simulation time 255401952 ps
CPU time 6.23 seconds
Started Feb 22 01:08:46 PM PST 24
Finished Feb 22 01:08:52 PM PST 24
Peak memory 208548 kb
Host smart-7d7310b7-92c4-4976-9c86-b7c125bccc5a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008362353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2008362353
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1022047211
Short name T320
Test name
Test status
Simulation time 39693428 ps
CPU time 2.27 seconds
Started Feb 22 01:08:41 PM PST 24
Finished Feb 22 01:08:43 PM PST 24
Peak memory 215376 kb
Host smart-ff659ef6-e824-4e2e-bf94-d9d2181441bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022047211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1022047211
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.156260428
Short name T443
Test name
Test status
Simulation time 1992264094 ps
CPU time 17.2 seconds
Started Feb 22 01:08:47 PM PST 24
Finished Feb 22 01:09:05 PM PST 24
Peak memory 207808 kb
Host smart-cc083c40-8e89-4e50-81fd-f5f3a371c21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156260428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.156260428
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2068848689
Short name T1056
Test name
Test status
Simulation time 21890759585 ps
CPU time 139.26 seconds
Started Feb 22 01:08:44 PM PST 24
Finished Feb 22 01:11:04 PM PST 24
Peak memory 215048 kb
Host smart-f18386bf-415d-437d-b0d3-395fde298ae7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068848689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2068848689
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3907242425
Short name T954
Test name
Test status
Simulation time 699421591 ps
CPU time 3.95 seconds
Started Feb 22 01:08:51 PM PST 24
Finished Feb 22 01:08:57 PM PST 24
Peak memory 218096 kb
Host smart-ba7aef7a-5b92-4700-8cfc-a61e2d0de5d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907242425 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3907242425
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.289329520
Short name T975
Test name
Test status
Simulation time 8740989014 ps
CPU time 35.95 seconds
Started Feb 22 01:08:44 PM PST 24
Finished Feb 22 01:09:21 PM PST 24
Peak memory 209596 kb
Host smart-a76f434b-531b-4adc-a153-9adde61df938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289329520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.289329520
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3356358559
Short name T1044
Test name
Test status
Simulation time 1159480056 ps
CPU time 8.93 seconds
Started Feb 22 01:08:46 PM PST 24
Finished Feb 22 01:08:55 PM PST 24
Peak memory 210236 kb
Host smart-4c8317b2-4d15-4b04-8587-175493633ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356358559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3356358559
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2482305259
Short name T986
Test name
Test status
Simulation time 7865899 ps
CPU time 0.72 seconds
Started Feb 22 01:08:47 PM PST 24
Finished Feb 22 01:08:48 PM PST 24
Peak memory 205864 kb
Host smart-4e6a93fb-d90c-40d2-a448-cedff6c69c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482305259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2482305259
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1661868955
Short name T43
Test name
Test status
Simulation time 173154480 ps
CPU time 3.86 seconds
Started Feb 22 01:08:44 PM PST 24
Finished Feb 22 01:08:48 PM PST 24
Peak memory 214272 kb
Host smart-5bfe369b-d245-4307-ae2c-bf168e166441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661868955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1661868955
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.798786327
Short name T93
Test name
Test status
Simulation time 688071050 ps
CPU time 5.85 seconds
Started Feb 22 01:08:50 PM PST 24
Finished Feb 22 01:08:56 PM PST 24
Peak memory 214284 kb
Host smart-557488ff-d6b9-41d0-883a-bbc8e6d52df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798786327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.798786327
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2695799712
Short name T879
Test name
Test status
Simulation time 72995325 ps
CPU time 3.69 seconds
Started Feb 22 01:08:48 PM PST 24
Finished Feb 22 01:08:52 PM PST 24
Peak memory 214368 kb
Host smart-83a56ca7-95f1-4dd7-afd5-25c78745a7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695799712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2695799712
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2567678269
Short name T276
Test name
Test status
Simulation time 567135551 ps
CPU time 4.86 seconds
Started Feb 22 01:08:44 PM PST 24
Finished Feb 22 01:08:49 PM PST 24
Peak memory 218424 kb
Host smart-edd26ac1-e881-4422-b93b-953c55b292e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567678269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2567678269
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2014892140
Short name T282
Test name
Test status
Simulation time 234576999 ps
CPU time 3.35 seconds
Started Feb 22 01:08:47 PM PST 24
Finished Feb 22 01:08:51 PM PST 24
Peak memory 208420 kb
Host smart-7f92e80d-b2de-4030-ad69-887f9ea296b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014892140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2014892140
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1313563374
Short name T408
Test name
Test status
Simulation time 51393113 ps
CPU time 2.8 seconds
Started Feb 22 01:08:48 PM PST 24
Finished Feb 22 01:08:51 PM PST 24
Peak memory 208892 kb
Host smart-e123a3bf-6e01-43f5-b33f-6733a090d85d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313563374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1313563374
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1695796308
Short name T571
Test name
Test status
Simulation time 130641514 ps
CPU time 4.31 seconds
Started Feb 22 01:08:49 PM PST 24
Finished Feb 22 01:08:53 PM PST 24
Peak memory 207956 kb
Host smart-fd30e471-d82e-43be-884e-cb12cad02cb3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695796308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1695796308
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2294369019
Short name T952
Test name
Test status
Simulation time 706150209 ps
CPU time 22.58 seconds
Started Feb 22 01:08:41 PM PST 24
Finished Feb 22 01:09:04 PM PST 24
Peak memory 208196 kb
Host smart-2c6a2aba-942d-4e3d-a64f-46a7c8a69762
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294369019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2294369019
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2393023841
Short name T1054
Test name
Test status
Simulation time 126650018 ps
CPU time 3.2 seconds
Started Feb 22 01:08:48 PM PST 24
Finished Feb 22 01:08:52 PM PST 24
Peak memory 209336 kb
Host smart-7afdb643-7529-43b8-ac86-d30e414af59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393023841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2393023841
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1774035715
Short name T706
Test name
Test status
Simulation time 280204086 ps
CPU time 2.89 seconds
Started Feb 22 01:08:46 PM PST 24
Finished Feb 22 01:08:49 PM PST 24
Peak memory 208388 kb
Host smart-167f188b-fca2-4332-81a1-afad464f189b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774035715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1774035715
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.4261834174
Short name T217
Test name
Test status
Simulation time 1348023725 ps
CPU time 45.77 seconds
Started Feb 22 01:08:48 PM PST 24
Finished Feb 22 01:09:34 PM PST 24
Peak memory 222540 kb
Host smart-14bd04bd-d359-4f0d-bf52-5aa1ff7d9260
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261834174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.4261834174
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3324223573
Short name T294
Test name
Test status
Simulation time 350175303 ps
CPU time 6.18 seconds
Started Feb 22 01:08:48 PM PST 24
Finished Feb 22 01:08:55 PM PST 24
Peak memory 219980 kb
Host smart-10381b51-d553-41d9-8df5-eb68fc20495d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324223573 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3324223573
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3893571858
Short name T967
Test name
Test status
Simulation time 3505227940 ps
CPU time 36.26 seconds
Started Feb 22 01:08:45 PM PST 24
Finished Feb 22 01:09:21 PM PST 24
Peak memory 214324 kb
Host smart-5bcf632e-e21b-4536-a1fe-7c0069239518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893571858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3893571858
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3141322491
Short name T930
Test name
Test status
Simulation time 241240125 ps
CPU time 2.63 seconds
Started Feb 22 01:08:46 PM PST 24
Finished Feb 22 01:08:48 PM PST 24
Peak memory 209996 kb
Host smart-eb91a4cf-c6c3-4fb2-88f7-38f129d0857a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141322491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3141322491
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3598356699
Short name T680
Test name
Test status
Simulation time 47296352 ps
CPU time 0.83 seconds
Started Feb 22 01:09:03 PM PST 24
Finished Feb 22 01:09:04 PM PST 24
Peak memory 205764 kb
Host smart-b5b015ce-aa7d-4261-9202-4c4562c55b18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598356699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3598356699
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1757150644
Short name T372
Test name
Test status
Simulation time 86303310 ps
CPU time 3.58 seconds
Started Feb 22 01:08:58 PM PST 24
Finished Feb 22 01:09:02 PM PST 24
Peak memory 214316 kb
Host smart-e947d45e-e6a4-432c-9ab9-040a8babc4c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1757150644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1757150644
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3464571950
Short name T1047
Test name
Test status
Simulation time 61983649 ps
CPU time 2.95 seconds
Started Feb 22 01:09:01 PM PST 24
Finished Feb 22 01:09:04 PM PST 24
Peak memory 210500 kb
Host smart-2ffafa4a-4737-4235-9720-7fd52d183d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464571950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3464571950
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2191816825
Short name T856
Test name
Test status
Simulation time 54544402 ps
CPU time 2.4 seconds
Started Feb 22 01:08:55 PM PST 24
Finished Feb 22 01:08:59 PM PST 24
Peak memory 214500 kb
Host smart-c11302b3-c2d5-4b64-8893-c74176422dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191816825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2191816825
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2265126757
Short name T208
Test name
Test status
Simulation time 208293739 ps
CPU time 5.7 seconds
Started Feb 22 01:08:55 PM PST 24
Finished Feb 22 01:09:02 PM PST 24
Peak memory 220444 kb
Host smart-7e5450d6-3460-46bc-9b7f-42d2e499db76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265126757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2265126757
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3483018329
Short name T82
Test name
Test status
Simulation time 118666415 ps
CPU time 2.5 seconds
Started Feb 22 01:08:51 PM PST 24
Finished Feb 22 01:08:54 PM PST 24
Peak memory 206940 kb
Host smart-eda32e1b-499a-4411-a512-6381aee1ce46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483018329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3483018329
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1996051779
Short name T782
Test name
Test status
Simulation time 10815807346 ps
CPU time 28.26 seconds
Started Feb 22 01:08:48 PM PST 24
Finished Feb 22 01:09:16 PM PST 24
Peak memory 208932 kb
Host smart-e6e99602-ec33-4e57-8d46-ea0220d0938f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996051779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1996051779
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1204267776
Short name T998
Test name
Test status
Simulation time 151509237 ps
CPU time 6.14 seconds
Started Feb 22 01:08:48 PM PST 24
Finished Feb 22 01:08:54 PM PST 24
Peak memory 208892 kb
Host smart-061e3325-8add-471f-9f65-38c4439fa6ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204267776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1204267776
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.269270644
Short name T586
Test name
Test status
Simulation time 130871120 ps
CPU time 4.67 seconds
Started Feb 22 01:08:55 PM PST 24
Finished Feb 22 01:09:01 PM PST 24
Peak memory 207016 kb
Host smart-4bf737bc-d81d-4393-b313-9d16ce006a5b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269270644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.269270644
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1833986669
Short name T761
Test name
Test status
Simulation time 683265168 ps
CPU time 8.41 seconds
Started Feb 22 01:08:52 PM PST 24
Finished Feb 22 01:09:01 PM PST 24
Peak memory 208724 kb
Host smart-75906b46-8453-4596-8080-2a45dbf96aa6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833986669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1833986669
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.710175285
Short name T439
Test name
Test status
Simulation time 521353357 ps
CPU time 3.27 seconds
Started Feb 22 01:08:55 PM PST 24
Finished Feb 22 01:09:00 PM PST 24
Peak memory 209696 kb
Host smart-afa22ced-62c9-4e68-b1cb-db5b5725f94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710175285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.710175285
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2425325414
Short name T664
Test name
Test status
Simulation time 260161604 ps
CPU time 6.58 seconds
Started Feb 22 01:08:48 PM PST 24
Finished Feb 22 01:08:54 PM PST 24
Peak memory 207916 kb
Host smart-583529d3-9954-4595-a3b4-89c9ab02b2c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425325414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2425325414
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1389255708
Short name T101
Test name
Test status
Simulation time 208707174 ps
CPU time 8.41 seconds
Started Feb 22 01:08:46 PM PST 24
Finished Feb 22 01:08:54 PM PST 24
Peak memory 222500 kb
Host smart-880b6d25-727d-422e-ba31-d02187af2c31
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389255708 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1389255708
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2331163463
Short name T902
Test name
Test status
Simulation time 450686665 ps
CPU time 4.04 seconds
Started Feb 22 01:08:55 PM PST 24
Finished Feb 22 01:09:01 PM PST 24
Peak memory 218276 kb
Host smart-a1851327-7b93-49c4-83d6-136b8d00d034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331163463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2331163463
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2805803675
Short name T33
Test name
Test status
Simulation time 134902006 ps
CPU time 2.53 seconds
Started Feb 22 01:08:49 PM PST 24
Finished Feb 22 01:08:52 PM PST 24
Peak memory 210112 kb
Host smart-8a44155f-f3c2-4b57-aeef-64885ba7e630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805803675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2805803675
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.658009817
Short name T779
Test name
Test status
Simulation time 15429939 ps
CPU time 0.93 seconds
Started Feb 22 01:09:10 PM PST 24
Finished Feb 22 01:09:13 PM PST 24
Peak memory 205888 kb
Host smart-03de1715-6b10-45fc-bb06-9f46a97461c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658009817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.658009817
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.234517424
Short name T259
Test name
Test status
Simulation time 1249089111 ps
CPU time 18.43 seconds
Started Feb 22 01:09:13 PM PST 24
Finished Feb 22 01:09:33 PM PST 24
Peak memory 215328 kb
Host smart-c0d6ead2-d9cb-4863-bd99-748112a60280
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=234517424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.234517424
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.4226532526
Short name T55
Test name
Test status
Simulation time 69988679 ps
CPU time 1.62 seconds
Started Feb 22 01:09:10 PM PST 24
Finished Feb 22 01:09:14 PM PST 24
Peak memory 207944 kb
Host smart-7d84b1ce-809e-4877-a9b5-192cd3333741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226532526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4226532526
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1695639982
Short name T910
Test name
Test status
Simulation time 2744207334 ps
CPU time 18.8 seconds
Started Feb 22 01:09:13 PM PST 24
Finished Feb 22 01:09:33 PM PST 24
Peak memory 214560 kb
Host smart-e68584f2-79fa-4056-9644-716a9f74aaa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695639982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1695639982
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1662963569
Short name T356
Test name
Test status
Simulation time 171221154 ps
CPU time 5.31 seconds
Started Feb 22 01:09:04 PM PST 24
Finished Feb 22 01:09:11 PM PST 24
Peak memory 214252 kb
Host smart-110c4cdd-48f4-4b4e-95a3-8abce307ff34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662963569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1662963569
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1873989651
Short name T955
Test name
Test status
Simulation time 34830658 ps
CPU time 2.04 seconds
Started Feb 22 01:09:08 PM PST 24
Finished Feb 22 01:09:11 PM PST 24
Peak memory 219868 kb
Host smart-7f0c99ca-3b62-4565-b4d0-0dd8fbc25ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873989651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1873989651
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.508057327
Short name T1035
Test name
Test status
Simulation time 203295870 ps
CPU time 3.88 seconds
Started Feb 22 01:09:01 PM PST 24
Finished Feb 22 01:09:05 PM PST 24
Peak memory 209728 kb
Host smart-addde94b-8cdd-4505-96d1-8646951e1308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508057327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.508057327
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1588160868
Short name T999
Test name
Test status
Simulation time 54977265 ps
CPU time 2.89 seconds
Started Feb 22 01:08:51 PM PST 24
Finished Feb 22 01:08:54 PM PST 24
Peak memory 208228 kb
Host smart-e2de79e6-e52e-4d6a-ae12-127c0d4f8c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588160868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1588160868
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.108522036
Short name T3
Test name
Test status
Simulation time 598371272 ps
CPU time 10.46 seconds
Started Feb 22 01:08:50 PM PST 24
Finished Feb 22 01:09:00 PM PST 24
Peak memory 207908 kb
Host smart-a7a987b4-2795-49ef-9e90-ca8fe2d4222f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108522036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.108522036
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.553830808
Short name T784
Test name
Test status
Simulation time 338827474 ps
CPU time 5.52 seconds
Started Feb 22 01:08:39 PM PST 24
Finished Feb 22 01:08:45 PM PST 24
Peak memory 208692 kb
Host smart-9997ad6d-799c-4764-84f0-35f3835945ed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553830808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.553830808
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2370235645
Short name T375
Test name
Test status
Simulation time 161564913 ps
CPU time 5.21 seconds
Started Feb 22 01:08:44 PM PST 24
Finished Feb 22 01:08:50 PM PST 24
Peak memory 208480 kb
Host smart-de2ef48a-ce29-4d91-8156-19c96c623234
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370235645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2370235645
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3066455657
Short name T849
Test name
Test status
Simulation time 97645557 ps
CPU time 2.21 seconds
Started Feb 22 01:09:06 PM PST 24
Finished Feb 22 01:09:09 PM PST 24
Peak memory 218400 kb
Host smart-2057857f-8b69-4175-ae79-9f13d888a0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066455657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3066455657
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2063377847
Short name T745
Test name
Test status
Simulation time 165552911 ps
CPU time 2.54 seconds
Started Feb 22 01:08:48 PM PST 24
Finished Feb 22 01:08:51 PM PST 24
Peak memory 206780 kb
Host smart-1554cad3-10fc-476c-af97-de32bc2f665f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063377847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2063377847
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2004116455
Short name T1052
Test name
Test status
Simulation time 2295975727 ps
CPU time 22.64 seconds
Started Feb 22 01:09:12 PM PST 24
Finished Feb 22 01:09:36 PM PST 24
Peak memory 216320 kb
Host smart-06efbcb8-5bda-4bf0-aaaf-c24182c1aaf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004116455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2004116455
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1628624570
Short name T210
Test name
Test status
Simulation time 615439004 ps
CPU time 4.99 seconds
Started Feb 22 01:09:08 PM PST 24
Finished Feb 22 01:09:14 PM PST 24
Peak memory 220340 kb
Host smart-7ea98f92-270b-49e6-8349-8549a404e9e8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628624570 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1628624570
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1471495267
Short name T752
Test name
Test status
Simulation time 54054072 ps
CPU time 3.57 seconds
Started Feb 22 01:09:05 PM PST 24
Finished Feb 22 01:09:09 PM PST 24
Peak memory 207900 kb
Host smart-c9ba0480-9599-4d3d-ba13-ab6bd9d5c8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471495267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1471495267
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3841242183
Short name T648
Test name
Test status
Simulation time 1687359679 ps
CPU time 5.72 seconds
Started Feb 22 01:09:04 PM PST 24
Finished Feb 22 01:09:10 PM PST 24
Peak memory 210700 kb
Host smart-af355b24-61e5-4a69-b566-8fffebddec66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841242183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3841242183
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3598788553
Short name T632
Test name
Test status
Simulation time 88679362 ps
CPU time 0.74 seconds
Started Feb 22 01:09:13 PM PST 24
Finished Feb 22 01:09:15 PM PST 24
Peak memory 205864 kb
Host smart-705365a1-ab53-446b-ba25-f1fdb9bb395b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598788553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3598788553
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.4146659195
Short name T926
Test name
Test status
Simulation time 1378121432 ps
CPU time 10.11 seconds
Started Feb 22 01:09:05 PM PST 24
Finished Feb 22 01:09:16 PM PST 24
Peak memory 214308 kb
Host smart-57152c43-f020-461d-9697-96ddfc0411ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146659195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4146659195
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.364611650
Short name T657
Test name
Test status
Simulation time 590551494 ps
CPU time 5.15 seconds
Started Feb 22 01:09:05 PM PST 24
Finished Feb 22 01:09:12 PM PST 24
Peak memory 218064 kb
Host smart-8bb2101b-b8f3-4d5c-9c7c-0d6a7bfb4958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364611650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.364611650
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3032049380
Short name T399
Test name
Test status
Simulation time 307825545 ps
CPU time 8.64 seconds
Started Feb 22 01:09:12 PM PST 24
Finished Feb 22 01:09:22 PM PST 24
Peak memory 214400 kb
Host smart-781284fc-6c77-4d92-9488-3d1f4661e4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032049380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3032049380
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1842377872
Short name T679
Test name
Test status
Simulation time 189548725 ps
CPU time 9.83 seconds
Started Feb 22 01:09:13 PM PST 24
Finished Feb 22 01:09:24 PM PST 24
Peak memory 209888 kb
Host smart-be0a65ce-2ec8-4079-89e0-c263399097db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842377872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1842377872
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2713398726
Short name T749
Test name
Test status
Simulation time 233610870 ps
CPU time 8.5 seconds
Started Feb 22 01:09:05 PM PST 24
Finished Feb 22 01:09:15 PM PST 24
Peak memory 207480 kb
Host smart-06312e2c-d367-4fd5-aa8b-1f9996d4d46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713398726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2713398726
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.21450471
Short name T711
Test name
Test status
Simulation time 120878596 ps
CPU time 2.01 seconds
Started Feb 22 01:09:04 PM PST 24
Finished Feb 22 01:09:07 PM PST 24
Peak memory 208532 kb
Host smart-56d74c5f-201a-43c6-b358-37c816483058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21450471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.21450471
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2768439421
Short name T726
Test name
Test status
Simulation time 1446531220 ps
CPU time 40.85 seconds
Started Feb 22 01:09:03 PM PST 24
Finished Feb 22 01:09:44 PM PST 24
Peak memory 208980 kb
Host smart-9d8a7f83-3ce0-487d-a1f3-f70515a76adc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768439421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2768439421
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3158484811
Short name T987
Test name
Test status
Simulation time 112679486 ps
CPU time 2.75 seconds
Started Feb 22 01:09:05 PM PST 24
Finished Feb 22 01:09:09 PM PST 24
Peak memory 206868 kb
Host smart-b04cb681-5440-40e1-a4e7-40067dc8f4e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158484811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3158484811
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3114977245
Short name T778
Test name
Test status
Simulation time 7787266493 ps
CPU time 83.09 seconds
Started Feb 22 01:09:07 PM PST 24
Finished Feb 22 01:10:32 PM PST 24
Peak memory 209084 kb
Host smart-832e3b0d-c463-4f56-b6df-17dad870a028
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114977245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3114977245
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2966650850
Short name T313
Test name
Test status
Simulation time 110857227 ps
CPU time 3.56 seconds
Started Feb 22 01:09:08 PM PST 24
Finished Feb 22 01:09:13 PM PST 24
Peak memory 217968 kb
Host smart-8b1cbeba-59a3-4860-ab43-af80d5f0acbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966650850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2966650850
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.154575135
Short name T683
Test name
Test status
Simulation time 359607937 ps
CPU time 6.73 seconds
Started Feb 22 01:09:03 PM PST 24
Finished Feb 22 01:09:11 PM PST 24
Peak memory 208324 kb
Host smart-fd070505-8e23-49ca-85d7-6893e59d31cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154575135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.154575135
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2925441075
Short name T354
Test name
Test status
Simulation time 8104254659 ps
CPU time 49.21 seconds
Started Feb 22 01:09:03 PM PST 24
Finished Feb 22 01:09:52 PM PST 24
Peak memory 216900 kb
Host smart-d0c12b77-80d8-48f5-ad93-e0c31192b757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925441075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2925441075
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.4099674961
Short name T665
Test name
Test status
Simulation time 333357550 ps
CPU time 3.4 seconds
Started Feb 22 01:09:05 PM PST 24
Finished Feb 22 01:09:09 PM PST 24
Peak memory 217960 kb
Host smart-3a2e3eb9-5062-4809-9c05-be117478feda
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099674961 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.4099674961
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1619227549
Short name T321
Test name
Test status
Simulation time 58404875 ps
CPU time 3.71 seconds
Started Feb 22 01:09:12 PM PST 24
Finished Feb 22 01:09:17 PM PST 24
Peak memory 214308 kb
Host smart-624f16ed-03cd-4dbe-a807-e8226891b20c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619227549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1619227549
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3508242664
Short name T981
Test name
Test status
Simulation time 77638441 ps
CPU time 2.43 seconds
Started Feb 22 01:09:04 PM PST 24
Finished Feb 22 01:09:08 PM PST 24
Peak memory 209952 kb
Host smart-c2d66c9c-c707-4f02-8061-c0a0c164d609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508242664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3508242664
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1210903591
Short name T942
Test name
Test status
Simulation time 131426879 ps
CPU time 0.79 seconds
Started Feb 22 01:06:01 PM PST 24
Finished Feb 22 01:06:04 PM PST 24
Peak memory 205832 kb
Host smart-2a3113dc-5be3-4884-8783-c78dde118fbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210903591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1210903591
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.841745475
Short name T1012
Test name
Test status
Simulation time 2941998036 ps
CPU time 14.95 seconds
Started Feb 22 01:05:49 PM PST 24
Finished Feb 22 01:06:04 PM PST 24
Peak memory 215360 kb
Host smart-cf4c5567-1406-44de-9bbf-8dbd06c6a802
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=841745475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.841745475
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.4250281594
Short name T35
Test name
Test status
Simulation time 222216756 ps
CPU time 3.68 seconds
Started Feb 22 01:06:00 PM PST 24
Finished Feb 22 01:06:05 PM PST 24
Peak memory 209144 kb
Host smart-8d97ef43-535d-4132-bbbe-e2e95f8e66b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250281594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.4250281594
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1164102012
Short name T1005
Test name
Test status
Simulation time 18955216 ps
CPU time 1.49 seconds
Started Feb 22 01:05:50 PM PST 24
Finished Feb 22 01:05:52 PM PST 24
Peak memory 207808 kb
Host smart-c403ea13-6097-4770-bc01-41d5462b2519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164102012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1164102012
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3453304920
Short name T16
Test name
Test status
Simulation time 211714340 ps
CPU time 4.69 seconds
Started Feb 22 01:05:55 PM PST 24
Finished Feb 22 01:06:00 PM PST 24
Peak memory 220328 kb
Host smart-1f034cf9-11e2-468d-a9d0-e39a76084b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453304920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3453304920
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.991220319
Short name T876
Test name
Test status
Simulation time 439702197 ps
CPU time 5.01 seconds
Started Feb 22 01:05:56 PM PST 24
Finished Feb 22 01:06:02 PM PST 24
Peak memory 211356 kb
Host smart-5e0228fe-df1c-4d19-86b4-c622bfad29c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991220319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.991220319
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_random.179155373
Short name T772
Test name
Test status
Simulation time 6164740623 ps
CPU time 40.46 seconds
Started Feb 22 01:05:54 PM PST 24
Finished Feb 22 01:06:35 PM PST 24
Peak memory 209120 kb
Host smart-68602af8-9b11-4559-8464-71d33ff6de81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179155373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.179155373
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4293868933
Short name T274
Test name
Test status
Simulation time 60160512 ps
CPU time 2.97 seconds
Started Feb 22 01:05:56 PM PST 24
Finished Feb 22 01:05:59 PM PST 24
Peak memory 208632 kb
Host smart-4f913e58-e797-42a1-b46c-a300f5f83c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293868933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4293868933
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2448953374
Short name T659
Test name
Test status
Simulation time 57757408 ps
CPU time 3.1 seconds
Started Feb 22 01:05:55 PM PST 24
Finished Feb 22 01:05:58 PM PST 24
Peak memory 208780 kb
Host smart-11e8341b-7ebb-47ed-81bb-de0ef866c1c4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448953374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2448953374
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3465782971
Short name T626
Test name
Test status
Simulation time 136784837 ps
CPU time 5.45 seconds
Started Feb 22 01:05:55 PM PST 24
Finished Feb 22 01:06:01 PM PST 24
Peak memory 208604 kb
Host smart-9b13bb1a-9193-4a65-9b53-685f13b91738
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465782971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3465782971
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2511815014
Short name T199
Test name
Test status
Simulation time 71311118 ps
CPU time 3.47 seconds
Started Feb 22 01:05:51 PM PST 24
Finished Feb 22 01:05:55 PM PST 24
Peak memory 208736 kb
Host smart-d63b72a3-5580-4b71-87f7-035feee580a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511815014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2511815014
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3820652155
Short name T618
Test name
Test status
Simulation time 23614808 ps
CPU time 1.63 seconds
Started Feb 22 01:05:56 PM PST 24
Finished Feb 22 01:05:58 PM PST 24
Peak memory 214364 kb
Host smart-a723f386-dc47-4e8f-85c6-559dd2043e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820652155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3820652155
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.619239974
Short name T914
Test name
Test status
Simulation time 716752478 ps
CPU time 4.61 seconds
Started Feb 22 01:05:56 PM PST 24
Finished Feb 22 01:06:01 PM PST 24
Peak memory 206652 kb
Host smart-b3aea55e-7f02-49ee-b427-e3c2c29ff568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619239974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.619239974
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1241268224
Short name T222
Test name
Test status
Simulation time 6025912242 ps
CPU time 44.03 seconds
Started Feb 22 01:05:59 PM PST 24
Finished Feb 22 01:06:43 PM PST 24
Peak memory 216960 kb
Host smart-03386acd-bc5e-4849-a2d6-0897d65a7538
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241268224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1241268224
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2694181321
Short name T931
Test name
Test status
Simulation time 69804653 ps
CPU time 2.23 seconds
Started Feb 22 01:06:01 PM PST 24
Finished Feb 22 01:06:05 PM PST 24
Peak memory 217760 kb
Host smart-81b72117-b304-4f9a-9b0e-0bbacc258971
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694181321 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2694181321
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.4135127653
Short name T672
Test name
Test status
Simulation time 190433587 ps
CPU time 5.82 seconds
Started Feb 22 01:05:51 PM PST 24
Finished Feb 22 01:05:57 PM PST 24
Peak memory 214280 kb
Host smart-20f6db0d-9a71-455c-a755-29c7b362dbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135127653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.4135127653
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3117310101
Short name T1063
Test name
Test status
Simulation time 863238647 ps
CPU time 2.81 seconds
Started Feb 22 01:05:55 PM PST 24
Finished Feb 22 01:05:58 PM PST 24
Peak memory 209920 kb
Host smart-d4bef2ee-3781-4acd-bf2a-53b5159b33f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117310101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3117310101
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3912566106
Short name T1013
Test name
Test status
Simulation time 29621174 ps
CPU time 0.75 seconds
Started Feb 22 01:06:09 PM PST 24
Finished Feb 22 01:06:11 PM PST 24
Peak memory 205776 kb
Host smart-5a6109d2-3e6f-4ad9-b225-510c637d7e53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912566106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3912566106
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3432081775
Short name T324
Test name
Test status
Simulation time 93731577 ps
CPU time 4.72 seconds
Started Feb 22 01:06:07 PM PST 24
Finished Feb 22 01:06:12 PM PST 24
Peak memory 210408 kb
Host smart-c82eb5b3-e2fc-408b-90db-712ab03cd1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432081775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3432081775
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3509025168
Short name T878
Test name
Test status
Simulation time 125673714 ps
CPU time 4.33 seconds
Started Feb 22 01:06:09 PM PST 24
Finished Feb 22 01:06:14 PM PST 24
Peak memory 214204 kb
Host smart-dfb495af-1779-43f4-902c-2020f7319d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509025168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3509025168
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.172949491
Short name T269
Test name
Test status
Simulation time 48358078 ps
CPU time 3.43 seconds
Started Feb 22 01:06:02 PM PST 24
Finished Feb 22 01:06:08 PM PST 24
Peak memory 222420 kb
Host smart-05a6f300-48c2-4394-a1a7-62e24adb0a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172949491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.172949491
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2665127025
Short name T898
Test name
Test status
Simulation time 341776954 ps
CPU time 9.97 seconds
Started Feb 22 01:06:01 PM PST 24
Finished Feb 22 01:06:13 PM PST 24
Peak memory 214268 kb
Host smart-6283b1dd-d79d-4866-96a1-16451403b044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665127025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2665127025
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.541710335
Short name T905
Test name
Test status
Simulation time 122893543 ps
CPU time 4.73 seconds
Started Feb 22 01:05:59 PM PST 24
Finished Feb 22 01:06:05 PM PST 24
Peak memory 209568 kb
Host smart-c22408f9-a2e3-45e1-a929-27c518ddfe7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541710335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.541710335
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.4089948235
Short name T936
Test name
Test status
Simulation time 235158557 ps
CPU time 3.11 seconds
Started Feb 22 01:05:59 PM PST 24
Finished Feb 22 01:06:03 PM PST 24
Peak memory 206832 kb
Host smart-ea500e37-052e-4959-b705-bd5e06d06fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089948235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.4089948235
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2036023616
Short name T646
Test name
Test status
Simulation time 496898616 ps
CPU time 7.02 seconds
Started Feb 22 01:06:01 PM PST 24
Finished Feb 22 01:06:10 PM PST 24
Peak memory 208296 kb
Host smart-7b48bc95-f676-4042-82ee-8ebfb85d7bec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036023616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2036023616
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3673864427
Short name T738
Test name
Test status
Simulation time 74268189 ps
CPU time 3.49 seconds
Started Feb 22 01:05:59 PM PST 24
Finished Feb 22 01:06:02 PM PST 24
Peak memory 208600 kb
Host smart-3df61ab5-0351-4f54-9a6a-6e9a8ca6fd8e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673864427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3673864427
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3680184465
Short name T330
Test name
Test status
Simulation time 1370838079 ps
CPU time 3.31 seconds
Started Feb 22 01:06:02 PM PST 24
Finished Feb 22 01:06:08 PM PST 24
Peak memory 207776 kb
Host smart-ef673453-6691-4a1b-89de-d18a43b67e83
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680184465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3680184465
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1477056459
Short name T366
Test name
Test status
Simulation time 231319472 ps
CPU time 3.16 seconds
Started Feb 22 01:06:07 PM PST 24
Finished Feb 22 01:06:10 PM PST 24
Peak memory 214260 kb
Host smart-23da2ebe-c77d-4a72-833c-24fe1b1d9640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477056459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1477056459
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.946538741
Short name T611
Test name
Test status
Simulation time 261024680 ps
CPU time 6.75 seconds
Started Feb 22 01:05:57 PM PST 24
Finished Feb 22 01:06:04 PM PST 24
Peak memory 206800 kb
Host smart-be8ec8f0-6f99-4ad1-8fbe-754f8eea898b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946538741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.946538741
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2490780648
Short name T404
Test name
Test status
Simulation time 145224860 ps
CPU time 5.16 seconds
Started Feb 22 01:06:09 PM PST 24
Finished Feb 22 01:06:15 PM PST 24
Peak memory 222568 kb
Host smart-1ec8558d-c244-47bf-ad93-fb0012e9affa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490780648 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2490780648
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3676224444
Short name T792
Test name
Test status
Simulation time 461888147 ps
CPU time 5.94 seconds
Started Feb 22 01:06:04 PM PST 24
Finished Feb 22 01:06:11 PM PST 24
Peak memory 218100 kb
Host smart-9e8e76a1-d4d5-4810-abaa-fac2ce30337c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676224444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3676224444
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.274481460
Short name T604
Test name
Test status
Simulation time 35720115 ps
CPU time 2.17 seconds
Started Feb 22 01:06:01 PM PST 24
Finished Feb 22 01:06:05 PM PST 24
Peak memory 209928 kb
Host smart-f97f38a3-43f1-48e0-998d-25b75b2a57fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274481460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.274481460
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2330684696
Short name T1003
Test name
Test status
Simulation time 26115791 ps
CPU time 0.89 seconds
Started Feb 22 01:06:04 PM PST 24
Finished Feb 22 01:06:06 PM PST 24
Peak memory 205804 kb
Host smart-0c11e446-8a51-4504-88f7-f49235be0946
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330684696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2330684696
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.941325360
Short name T1055
Test name
Test status
Simulation time 207589872 ps
CPU time 3.9 seconds
Started Feb 22 01:06:00 PM PST 24
Finished Feb 22 01:06:06 PM PST 24
Peak memory 221944 kb
Host smart-94cb414a-30c6-417b-b5bc-237b9a5ab3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941325360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.941325360
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.961965056
Short name T382
Test name
Test status
Simulation time 396363536 ps
CPU time 5.97 seconds
Started Feb 22 01:06:17 PM PST 24
Finished Feb 22 01:06:25 PM PST 24
Peak memory 214456 kb
Host smart-e2c7fc29-e6a6-4114-9d0a-83d3285543cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961965056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.961965056
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2938674808
Short name T271
Test name
Test status
Simulation time 189615672 ps
CPU time 5.66 seconds
Started Feb 22 01:06:02 PM PST 24
Finished Feb 22 01:06:09 PM PST 24
Peak memory 210784 kb
Host smart-ee74ad6b-0b36-400a-a165-09a0ebc7f892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938674808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2938674808
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.103934967
Short name T63
Test name
Test status
Simulation time 763773585 ps
CPU time 4.29 seconds
Started Feb 22 01:06:09 PM PST 24
Finished Feb 22 01:06:15 PM PST 24
Peak memory 209520 kb
Host smart-e339c4d7-4aa9-41d4-8efe-bb9488c3ab09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103934967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.103934967
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1729088826
Short name T186
Test name
Test status
Simulation time 1774443470 ps
CPU time 58.44 seconds
Started Feb 22 01:06:02 PM PST 24
Finished Feb 22 01:07:02 PM PST 24
Peak memory 207952 kb
Host smart-d1ddf51e-cb21-438f-9b24-b0a59e2de9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729088826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1729088826
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.209246968
Short name T927
Test name
Test status
Simulation time 3650337384 ps
CPU time 65.15 seconds
Started Feb 22 01:06:06 PM PST 24
Finished Feb 22 01:07:11 PM PST 24
Peak memory 209076 kb
Host smart-8e90d616-7ff2-4c70-966e-d3dba208be8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209246968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.209246968
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1711590071
Short name T198
Test name
Test status
Simulation time 1771658737 ps
CPU time 9.52 seconds
Started Feb 22 01:06:01 PM PST 24
Finished Feb 22 01:06:13 PM PST 24
Peak memory 209116 kb
Host smart-76521a80-e8c4-4506-b2c3-1db3eed16bc2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711590071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1711590071
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.67592353
Short name T645
Test name
Test status
Simulation time 1263228902 ps
CPU time 18.06 seconds
Started Feb 22 01:06:02 PM PST 24
Finished Feb 22 01:06:22 PM PST 24
Peak memory 208732 kb
Host smart-b1578a09-4f4f-4844-8d11-5f76a66ccead
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67592353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.67592353
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.394282056
Short name T864
Test name
Test status
Simulation time 448976043 ps
CPU time 4.03 seconds
Started Feb 22 01:06:01 PM PST 24
Finished Feb 22 01:06:07 PM PST 24
Peak memory 208508 kb
Host smart-a5f436a2-3809-41b1-93cf-9131bf86b032
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394282056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.394282056
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.4053310943
Short name T603
Test name
Test status
Simulation time 423855662 ps
CPU time 2.16 seconds
Started Feb 22 01:06:03 PM PST 24
Finished Feb 22 01:06:07 PM PST 24
Peak memory 207464 kb
Host smart-e46ed9f6-c4c5-44e9-9138-5a46ddedfe02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053310943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4053310943
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3254503181
Short name T1037
Test name
Test status
Simulation time 60432235 ps
CPU time 1.67 seconds
Started Feb 22 01:06:05 PM PST 24
Finished Feb 22 01:06:07 PM PST 24
Peak memory 206700 kb
Host smart-0a621e23-9643-4729-a930-845b8ed991b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254503181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3254503181
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.352527548
Short name T386
Test name
Test status
Simulation time 532076329 ps
CPU time 25.88 seconds
Started Feb 22 01:06:02 PM PST 24
Finished Feb 22 01:06:30 PM PST 24
Peak memory 222456 kb
Host smart-48fd8749-8669-42a8-8d36-955ae71cc588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352527548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.352527548
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.2777206536
Short name T843
Test name
Test status
Simulation time 65987301 ps
CPU time 5.03 seconds
Started Feb 22 01:06:03 PM PST 24
Finished Feb 22 01:06:10 PM PST 24
Peak memory 222632 kb
Host smart-7520260f-80ab-4044-8ed6-a4d5b16d33d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777206536 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.2777206536
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3880175194
Short name T962
Test name
Test status
Simulation time 381250059 ps
CPU time 3.51 seconds
Started Feb 22 01:06:07 PM PST 24
Finished Feb 22 01:06:11 PM PST 24
Peak memory 208148 kb
Host smart-7618d8fc-e6cf-46a9-8347-d76a613c89d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880175194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3880175194
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3809182380
Short name T769
Test name
Test status
Simulation time 30874024 ps
CPU time 1.89 seconds
Started Feb 22 01:06:10 PM PST 24
Finished Feb 22 01:06:13 PM PST 24
Peak memory 209788 kb
Host smart-f9f3d298-09c4-4f25-a59b-63f54bcb9279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809182380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3809182380
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1553212297
Short name T852
Test name
Test status
Simulation time 43973690 ps
CPU time 0.77 seconds
Started Feb 22 01:06:22 PM PST 24
Finished Feb 22 01:06:23 PM PST 24
Peak memory 205884 kb
Host smart-eeedaf7f-67b5-4494-a095-5b4e41a2aaf8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553212297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1553212297
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1883117163
Short name T385
Test name
Test status
Simulation time 1745322459 ps
CPU time 24.4 seconds
Started Feb 22 01:06:04 PM PST 24
Finished Feb 22 01:06:29 PM PST 24
Peak memory 214896 kb
Host smart-8bb5b003-0282-4448-a060-1f120b9c6e95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1883117163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1883117163
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.312651085
Short name T25
Test name
Test status
Simulation time 1221828757 ps
CPU time 4.08 seconds
Started Feb 22 01:06:05 PM PST 24
Finished Feb 22 01:06:10 PM PST 24
Peak memory 214580 kb
Host smart-bccf3827-fca8-47e5-82b1-ffca395f33db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312651085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.312651085
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.133095338
Short name T45
Test name
Test status
Simulation time 142107703 ps
CPU time 2.56 seconds
Started Feb 22 01:06:01 PM PST 24
Finished Feb 22 01:06:05 PM PST 24
Peak memory 208192 kb
Host smart-33e57be5-02a6-454b-a11c-4c5cd60e7c6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133095338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.133095338
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.487642774
Short name T390
Test name
Test status
Simulation time 411554371 ps
CPU time 9.01 seconds
Started Feb 22 01:06:06 PM PST 24
Finished Feb 22 01:06:15 PM PST 24
Peak memory 208380 kb
Host smart-7747db80-fad1-40bd-9895-5cfbf4f3f153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487642774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.487642774
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2313705487
Short name T292
Test name
Test status
Simulation time 136829026 ps
CPU time 6.68 seconds
Started Feb 22 01:06:03 PM PST 24
Finished Feb 22 01:06:11 PM PST 24
Peak memory 222312 kb
Host smart-7bf6f061-b491-4da0-baf0-9c9f4864af17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313705487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2313705487
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.4013505293
Short name T803
Test name
Test status
Simulation time 197795145 ps
CPU time 5.89 seconds
Started Feb 22 01:06:07 PM PST 24
Finished Feb 22 01:06:13 PM PST 24
Peak memory 209096 kb
Host smart-92467521-603c-444f-a783-02449275974c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013505293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.4013505293
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1558705967
Short name T361
Test name
Test status
Simulation time 168712842 ps
CPU time 4.52 seconds
Started Feb 22 01:06:07 PM PST 24
Finished Feb 22 01:06:12 PM PST 24
Peak memory 210356 kb
Host smart-c47c1a1e-03c0-4483-afdd-34516a7191bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558705967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1558705967
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.747130440
Short name T776
Test name
Test status
Simulation time 783816578 ps
CPU time 4.45 seconds
Started Feb 22 01:06:04 PM PST 24
Finished Feb 22 01:06:09 PM PST 24
Peak memory 206748 kb
Host smart-78f1ae90-8648-40c8-913f-be3d12efc7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747130440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.747130440
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1029293661
Short name T641
Test name
Test status
Simulation time 62639388 ps
CPU time 3.1 seconds
Started Feb 22 01:06:05 PM PST 24
Finished Feb 22 01:06:08 PM PST 24
Peak memory 206864 kb
Host smart-c394d4e2-12cc-4113-905a-75b31b38755c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029293661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1029293661
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.632482018
Short name T977
Test name
Test status
Simulation time 81996552 ps
CPU time 3.2 seconds
Started Feb 22 01:06:09 PM PST 24
Finished Feb 22 01:06:14 PM PST 24
Peak memory 207372 kb
Host smart-501c64b8-78b4-442b-a9f7-599eafe9fb2c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632482018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.632482018
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1720399689
Short name T709
Test name
Test status
Simulation time 39318222 ps
CPU time 2.5 seconds
Started Feb 22 01:06:09 PM PST 24
Finished Feb 22 01:06:12 PM PST 24
Peak memory 206868 kb
Host smart-efb7486e-7d3d-4e48-9ef2-fe47fae0149c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720399689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1720399689
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.127990804
Short name T889
Test name
Test status
Simulation time 94480426 ps
CPU time 2.17 seconds
Started Feb 22 01:06:15 PM PST 24
Finished Feb 22 01:06:18 PM PST 24
Peak memory 209060 kb
Host smart-69ae44f3-91ca-442b-8105-f45a6cfb7458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127990804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.127990804
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1778886111
Short name T1058
Test name
Test status
Simulation time 1252305612 ps
CPU time 21.86 seconds
Started Feb 22 01:06:04 PM PST 24
Finished Feb 22 01:06:27 PM PST 24
Peak memory 208772 kb
Host smart-b79864bb-5201-4b30-99ad-9d240090ef78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778886111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1778886111
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1194390752
Short name T352
Test name
Test status
Simulation time 90253949 ps
CPU time 4.28 seconds
Started Feb 22 01:06:05 PM PST 24
Finished Feb 22 01:06:10 PM PST 24
Peak memory 207520 kb
Host smart-df94b81d-ecb5-4d71-958b-d1aee2e766ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194390752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1194390752
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3819874176
Short name T1048
Test name
Test status
Simulation time 262558000 ps
CPU time 1.71 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:06:20 PM PST 24
Peak memory 209696 kb
Host smart-1c2b0e60-fe72-44ae-9813-845825da1969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819874176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3819874176
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3301403709
Short name T939
Test name
Test status
Simulation time 20377746 ps
CPU time 0.67 seconds
Started Feb 22 01:06:13 PM PST 24
Finished Feb 22 01:06:14 PM PST 24
Peak memory 205856 kb
Host smart-fbe63dca-283e-43e2-9e05-b0361bf85955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301403709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3301403709
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3989012313
Short name T431
Test name
Test status
Simulation time 209202066 ps
CPU time 10.8 seconds
Started Feb 22 01:06:19 PM PST 24
Finished Feb 22 01:06:31 PM PST 24
Peak memory 214348 kb
Host smart-61e0e836-29ac-442a-b60a-58df4cb48cc5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3989012313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3989012313
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3818687435
Short name T1023
Test name
Test status
Simulation time 351923946 ps
CPU time 2.88 seconds
Started Feb 22 01:06:20 PM PST 24
Finished Feb 22 01:06:24 PM PST 24
Peak memory 214280 kb
Host smart-c860fafe-ee57-4f69-923f-1d86f7b36a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818687435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3818687435
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2822242040
Short name T395
Test name
Test status
Simulation time 258440485 ps
CPU time 6.48 seconds
Started Feb 22 01:06:26 PM PST 24
Finished Feb 22 01:06:34 PM PST 24
Peak memory 214212 kb
Host smart-94f55cf6-8c2d-40ed-9a1a-db6d92ae3f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822242040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2822242040
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.107542447
Short name T257
Test name
Test status
Simulation time 116583933 ps
CPU time 4.4 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:06:22 PM PST 24
Peak memory 214348 kb
Host smart-fc6ad34a-0d62-4ab8-9bb6-58b4f5af58dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107542447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.107542447
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2694343635
Short name T249
Test name
Test status
Simulation time 4298128511 ps
CPU time 38.22 seconds
Started Feb 22 01:06:21 PM PST 24
Finished Feb 22 01:07:00 PM PST 24
Peak memory 214252 kb
Host smart-173d1c70-5a2f-479d-a419-7e1c276a0c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694343635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2694343635
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.39307276
Short name T52
Test name
Test status
Simulation time 467863720 ps
CPU time 13.16 seconds
Started Feb 22 01:06:14 PM PST 24
Finished Feb 22 01:06:28 PM PST 24
Peak memory 214340 kb
Host smart-23250a8c-08b7-42cb-901b-e3be11fe4fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39307276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.39307276
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.338492178
Short name T1031
Test name
Test status
Simulation time 117925654 ps
CPU time 5.28 seconds
Started Feb 22 01:06:13 PM PST 24
Finished Feb 22 01:06:19 PM PST 24
Peak memory 218368 kb
Host smart-698ea6f5-8d25-4555-9f45-9cee20777838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338492178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.338492178
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3657518020
Short name T205
Test name
Test status
Simulation time 287533171 ps
CPU time 8.08 seconds
Started Feb 22 01:06:16 PM PST 24
Finished Feb 22 01:06:27 PM PST 24
Peak memory 208216 kb
Host smart-af197f76-5bcd-4a08-8554-05db66519d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657518020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3657518020
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.454155644
Short name T126
Test name
Test status
Simulation time 116405544 ps
CPU time 3.17 seconds
Started Feb 22 01:06:14 PM PST 24
Finished Feb 22 01:06:19 PM PST 24
Peak memory 206708 kb
Host smart-91275a1e-5e61-44d5-a3e6-26e6d85b8fec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454155644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.454155644
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.669478550
Short name T405
Test name
Test status
Simulation time 1831486499 ps
CPU time 47.66 seconds
Started Feb 22 01:06:18 PM PST 24
Finished Feb 22 01:07:06 PM PST 24
Peak memory 208280 kb
Host smart-ab87bdc5-e71a-41aa-8134-7c1dd5cce6a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669478550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.669478550
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1292047483
Short name T415
Test name
Test status
Simulation time 210617564 ps
CPU time 2.28 seconds
Started Feb 22 01:06:27 PM PST 24
Finished Feb 22 01:06:30 PM PST 24
Peak memory 206772 kb
Host smart-43acae01-25da-42a7-a685-2a62be71edb1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292047483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1292047483
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1819085542
Short name T621
Test name
Test status
Simulation time 381850167 ps
CPU time 5.04 seconds
Started Feb 22 01:06:15 PM PST 24
Finished Feb 22 01:06:21 PM PST 24
Peak memory 208084 kb
Host smart-d8506cc4-7c5d-4deb-a2e4-50f4713c6efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819085542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1819085542
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3359629660
Short name T790
Test name
Test status
Simulation time 73547977 ps
CPU time 3.32 seconds
Started Feb 22 01:06:13 PM PST 24
Finished Feb 22 01:06:17 PM PST 24
Peak memory 208460 kb
Host smart-f6df29bd-b609-46ef-a3a4-339d7cf2db9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359629660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3359629660
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3826978147
Short name T76
Test name
Test status
Simulation time 291039940 ps
CPU time 2.89 seconds
Started Feb 22 01:06:17 PM PST 24
Finished Feb 22 01:06:22 PM PST 24
Peak memory 222616 kb
Host smart-211cd513-3bc5-4a6f-8ac9-6ea02832eeae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826978147 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3826978147
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1975938866
Short name T783
Test name
Test status
Simulation time 699323920 ps
CPU time 9.37 seconds
Started Feb 22 01:06:14 PM PST 24
Finished Feb 22 01:06:24 PM PST 24
Peak memory 208100 kb
Host smart-97d53851-8522-4195-bc76-ee9631fe6e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975938866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1975938866
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.99798606
Short name T835
Test name
Test status
Simulation time 158875490 ps
CPU time 2.44 seconds
Started Feb 22 01:06:14 PM PST 24
Finished Feb 22 01:06:18 PM PST 24
Peak memory 210104 kb
Host smart-8ae025d4-80b9-4b34-a063-09160dc762aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99798606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.99798606
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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