Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11788

1

T1

61

T2

15

T3

2

auto[Attestation]

7879

1

T1

54

T2

6

T3

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2938	1			T1	19		T2	4		T16	1
auto[Aes]	3561	1			T1	25		T2	3		T14	9
auto[Kmac]	3541	1			T1	16		T2	4		T3	1
auto[Otbn]	3452	1			T1	11		T2	3		T3	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7628	1			T1	60		T2	4		T3	2
auto[OpGenId]	6175	1			T1	44		T2	7		T3	3
auto[OpGenSwOut]	6220	1			T1	34		T2	7		T13	1
auto[OpGenHwOut]	7272	1			T1	37		T2	7		T3	2
auto[OpDisable]	139	1			T1	1		T32	4		T39	3

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10064

1

T1

72

T2

12

T3

3

auto[OpDoneFail]

17370

1

T1

104

T2

13

T3

4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6702	1			T1	34		T2	12		T3	1
auto[StInit]	4429	1			T1	20		T2	3		T3	5
auto[StCreatorRootKey]	3003	1			T1	23		T2	3		T3	1
auto[StOwnerIntKey]	2673	1			T1	17		T2	3		T12	2
auto[StOwnerKey]	2245	1			T1	19		T2	4		T12	2
auto[StDisabled]	7314	1			T1	63		T12	7		T17	7
auto[StInvalid]	1068	1			T33	22		T34	33		T43	30

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	352	1			T1	2		T2	1		T32	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	129	1			T21	1		T22	2		T39	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	76	1			T2	1		T32	1		T97	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	69	1			T164	1		T82	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	56	1			T32	2		T39	2		T49	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	218	1			T1	4		T32	2		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	32	1			T34	1		T81	1		T77	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	365	1			T1	1		T2	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	142	1			T1	1		T14	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	93	1			T16	1		T76	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	82	1			T131	1		T39	4		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	61	1			T1	1		T103	1		T115	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	193	1			T1	1		T18	1		T32	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	31	1			T34	3		T43	1		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	312	1			T1	1		T2	1		T18	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	126	1			T14	1		T32	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	87	1			T32	1		T38	1		T103	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	73	1			T115	1		T173	1		T174	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	67	1			T32	2		T38	1		T131	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	213	1			T1	3		T32	1		T175	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	31	1			T34	1		T43	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	352	1			T1	2		T2	2		T32	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	123	1			T14	1		T32	1		T21	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	65	1			T76	1		T50	1		T49	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	64	1			T1	1		T97	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	68	1			T176	1		T116	1		T173	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	223	1			T32	1		T103	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	30	1			T34	1		T43	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	64	1			T1	1		T32	2		T39	5
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	129	1			T1	2		T2	1		T32	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	79	1			T18	1		T131	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	57	1			T32	3		T59	1		T173	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	59	1			T104	1		T132	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	200	1			T1	2		T32	4		T177	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	44	1			T33	2		T43	2		T79	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	80	1			T1	1		T32	2		T39	7
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	135	1			T1	1		T14	2		T21	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	75	1			T1	1		T88	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	72	1			T177	1		T39	1		T176	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	56	1			T1	1		T39	2		T116	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	185	1			T32	4		T115	1		T177	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	30	1			T43	2		T79	1		T81	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	77	1			T1	3		T32	3		T39	6
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	125	1			T14	2		T32	2		T21	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	71	1			T45	2		T177	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	58	1			T18	1		T39	2		T49	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	52	1			T32	1		T132	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	209	1			T1	1		T32	3		T103	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	23	1			T33	2		T34	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	71	1			T32	3		T39	7		T109	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	116	1			T13	1		T18	1		T32	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	76	1			T1	2		T76	1		T132	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	57	1			T16	1		T32	1		T132	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	46	1			T1	1		T176	1		T173	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	207	1			T1	1		T18	1		T32	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	34	1			T43	1		T81	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	313	1			T2	1		T32	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	114	1			T1	1		T32	1		T21	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	64	1			T32	1		T38	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	69	1			T1	2		T32	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	39	1			T167	1		T49	1		T178	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	174	1			T1	2		T104	1		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	33	1			T33	1		T34	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	483	1			T1	5		T2	1		T17	9
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	144	1			T1	1		T14	3		T21	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	115	1			T1	3		T115	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	98	1			T179	1		T164	1		T166	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	83	1			T1	1		T2	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	259	1			T1	2		T17	4		T32	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	24	1			T34	1		T43	1		T79	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	537	1			T1	1		T2	1		T32	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	139	1			T3	1		T14	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T1	1		T32	1		T74	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	82	1			T180	1		T181	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	74	1			T1	2		T74	1		T76	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	260	1			T1	1		T32	3		T74	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	35	1			T33	2		T34	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	469	1			T32	2		T34	1		T182	7
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	129	1			T14	1		T32	1		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	93	1			T1	1		T72	1		T75	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	106	1			T12	1		T183	1		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	80	1			T12	1		T72	1		T75	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	249	1			T1	2		T12	3		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	30	1			T34	2		T77	1		T185	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	62	1			T1	1		T16	1		T39	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	120	1			T21	1		T34	1		T103	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	61	1			T32	1		T39	1		T186	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	64	1			T32	1		T39	1		T176	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	43	1			T32	1		T39	1		T116	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	183	1			T1	2		T32	1		T103	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	35	1			T33	1		T34	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	57	1			T39	2		T98	2		T187	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	149	1			T1	1		T14	3		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	115	1			T1	1		T17	1		T175	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	93	1			T1	1		T17	1		T39	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	74	1			T17	1		T188	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	238	1			T1	2		T32	1		T103	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	29	1			T34	2		T43	1		T79	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	57	1			T1	1		T39	3		T109	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	146	1			T21	2		T74	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	110	1			T2	1		T32	1		T103	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	96	1			T32	1		T74	1		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	80	1			T2	1		T32	1		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	273	1			T1	2		T32	4		T180	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	37	1			T43	1		T79	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	69	1			T39	1		T191	1		T187	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	135	1			T12	1		T32	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	102	1			T3	1		T12	1		T32	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	97	1			T2	1		T72	1		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	76	1			T32	2		T76	1		T182	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	246	1			T1	1		T12	1		T32	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	39	1			T43	2		T79	2		T81	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	184	1			T2	1		T32	3		T97	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	748	1			T1	6		T2	1		T32	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	223	1			T1	1		T16	1		T76	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	744	1			T1	3		T2	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	211	1			T32	3		T38	2		T103	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	698	1			T1	4		T2	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	182	1			T1	1		T76	1		T97	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	743	1			T1	2		T2	2		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	180	1			T18	1		T32	3		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	452	1			T1	5		T2	1		T32	8
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	190	1			T1	2		T177	1		T39	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	443	1			T1	2		T14	2		T32	6
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	168	1			T18	1		T32	1		T45	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	447	1			T1	4		T14	2		T32	8
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	171	1			T1	3		T16	1		T32	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	436	1			T1	1		T13	1		T18	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	159	1			T1	2		T32	2		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	647	1			T1	3		T2	1		T32	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	280	1			T1	4		T2	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	926	1			T1	8		T2	1		T14	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	226	1			T1	1		T32	1		T74	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	992	1			T1	4		T2	1		T3	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	260	1			T12	2		T72	2		T75	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	896	1			T1	3		T12	3		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	157	1			T32	3		T39	3		T176	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	411	1			T1	3		T16	1		T32	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	276	1			T1	2		T17	3		T175	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	479	1			T1	3		T14	3		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	264	1			T2	2		T32	3		T74	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	535	1			T1	3		T32	4		T21	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	257	1			T2	1		T3	1		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	507	1			T1	1		T12	2		T32	3