Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31432

1

T1

212

T2

27

T3

9

auto[1]

360

1

T103

8

T104

8

T115

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31437	1			T1	212		T2	27		T3	9
auto[134217728:268435455]	7	1			T232	1		T214	1		T283	1
auto[268435456:402653183]	7	1			T93	1		T243	2		T283	1
auto[402653184:536870911]	15	1			T103	1		T104	1		T220	1
auto[536870912:671088639]	18	1			T131	1		T132	2		T116	1
auto[671088640:805306367]	17	1			T103	1		T104	1		T131	1
auto[805306368:939524095]	10	1			T103	1		T104	1		T115	1
auto[939524096:1073741823]	10	1			T131	1		T218	1		T232	1
auto[1073741824:1207959551]	9	1			T131	1		T257	2		T243	1
auto[1207959552:1342177279]	11	1			T115	2		T132	1		T93	1
auto[1342177280:1476395007]	7	1			T103	1		T220	1		T257	2
auto[1476395008:1610612735]	7	1			T131	1		T232	1		T295	2
auto[1610612736:1744830463]	5	1			T116	1		T93	1		T287	1
auto[1744830464:1879048191]	11	1			T104	1		T116	1		T220	1
auto[1879048192:2013265919]	20	1			T104	1		T115	2		T93	1
auto[2013265920:2147483647]	12	1			T131	1		T116	2		T217	1
auto[2147483648:2281701375]	18	1			T104	1		T131	1		T116	1
auto[2281701376:2415919103]	11	1			T132	3		T93	1		T291	1
auto[2415919104:2550136831]	7	1			T220	1		T291	1		T232	1
auto[2550136832:2684354559]	10	1			T273	1		T317	2		T394	1
auto[2684354560:2818572287]	9	1			T115	1		T131	1		T295	1
auto[2818572288:2952790015]	15	1			T131	1		T220	1		T257	1
auto[2952790016:3087007743]	7	1			T257	1		T232	1		T304	1
auto[3087007744:3221225471]	9	1			T131	1		T257	1		T232	1
auto[3221225472:3355443199]	15	1			T103	1		T132	1		T93	1
auto[3355443200:3489660927]	12	1			T104	1		T220	1		T217	1
auto[3489660928:3623878655]	17	1			T131	1		T116	1		T220	1
auto[3623878656:3758096383]	11	1			T131	1		T116	1		T93	1
auto[3758096384:3892314111]	11	1			T131	1		T116	1		T370	1
auto[3892314112:4026531839]	12	1			T104	1		T257	2		T218	2
auto[4026531840:4160749567]	10	1			T103	1		T115	1		T220	1
auto[4160749568:4294967295]	15	1			T103	1		T132	1		T220	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31432	1			T1	212		T2	27		T3	9
auto[0:134217727]	auto[1]	5	1			T103	1		T257	1		T216	1
auto[134217728:268435455]	auto[1]	7	1			T232	1		T214	1		T283	1
auto[268435456:402653183]	auto[1]	7	1			T93	1		T243	2		T283	1
auto[402653184:536870911]	auto[1]	15	1			T103	1		T104	1		T220	1
auto[536870912:671088639]	auto[1]	18	1			T131	1		T132	2		T116	1
auto[671088640:805306367]	auto[1]	17	1			T103	1		T104	1		T131	1
auto[805306368:939524095]	auto[1]	10	1			T103	1		T104	1		T115	1
auto[939524096:1073741823]	auto[1]	10	1			T131	1		T218	1		T232	1
auto[1073741824:1207959551]	auto[1]	9	1			T131	1		T257	2		T243	1
auto[1207959552:1342177279]	auto[1]	11	1			T115	2		T132	1		T93	1
auto[1342177280:1476395007]	auto[1]	7	1			T103	1		T220	1		T257	2
auto[1476395008:1610612735]	auto[1]	7	1			T131	1		T232	1		T295	2
auto[1610612736:1744830463]	auto[1]	5	1			T116	1		T93	1		T287	1
auto[1744830464:1879048191]	auto[1]	11	1			T104	1		T116	1		T220	1
auto[1879048192:2013265919]	auto[1]	20	1			T104	1		T115	2		T93	1
auto[2013265920:2147483647]	auto[1]	12	1			T131	1		T116	2		T217	1
auto[2147483648:2281701375]	auto[1]	18	1			T104	1		T131	1		T116	1
auto[2281701376:2415919103]	auto[1]	11	1			T132	3		T93	1		T291	1
auto[2415919104:2550136831]	auto[1]	7	1			T220	1		T291	1		T232	1
auto[2550136832:2684354559]	auto[1]	10	1			T273	1		T317	2		T394	1
auto[2684354560:2818572287]	auto[1]	9	1			T115	1		T131	1		T295	1
auto[2818572288:2952790015]	auto[1]	15	1			T131	1		T220	1		T257	1
auto[2952790016:3087007743]	auto[1]	7	1			T257	1		T232	1		T304	1
auto[3087007744:3221225471]	auto[1]	9	1			T131	1		T257	1		T232	1
auto[3221225472:3355443199]	auto[1]	15	1			T103	1		T132	1		T93	1
auto[3355443200:3489660927]	auto[1]	12	1			T104	1		T220	1		T217	1
auto[3489660928:3623878655]	auto[1]	17	1			T131	1		T116	1		T220	1
auto[3623878656:3758096383]	auto[1]	11	1			T131	1		T116	1		T93	1
auto[3758096384:3892314111]	auto[1]	11	1			T131	1		T116	1		T370	1
auto[3892314112:4026531839]	auto[1]	12	1			T104	1		T257	2		T218	2
auto[4026531840:4160749567]	auto[1]	10	1			T103	1		T115	1		T220	1
auto[4160749568:4294967295]	auto[1]	15	1			T103	1		T132	1		T220	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1542

1

T1

7

T3

3

T32

12

auto[1]

1742

1

T1

12

T13

2

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T3	1		T33	1		T103	1
auto[134217728:268435455]	95	1			T14	1		T32	1		T22	1
auto[268435456:402653183]	96	1			T1	1		T16	1		T32	1
auto[402653184:536870911]	102	1			T3	1		T32	1		T115	1
auto[536870912:671088639]	91	1			T32	1		T34	1		T76	1
auto[671088640:805306367]	104	1			T1	1		T32	1		T22	2
auto[805306368:939524095]	104	1			T1	1		T32	2		T21	1
auto[939524096:1073741823]	111	1			T1	1		T32	1		T104	1
auto[1073741824:1207959551]	110	1			T1	1		T32	1		T33	1
auto[1207959552:1342177279]	110	1			T1	1		T13	1		T115	1
auto[1342177280:1476395007]	103	1			T1	2		T14	1		T32	2
auto[1476395008:1610612735]	103	1			T1	2		T76	1		T43	1
auto[1610612736:1744830463]	92	1			T32	1		T177	1		T39	2
auto[1744830464:1879048191]	106	1			T1	1		T32	2		T21	1
auto[1879048192:2013265919]	100	1			T1	1		T32	2		T79	2
auto[2013265920:2147483647]	111	1			T34	1		T103	1		T177	2
auto[2147483648:2281701375]	89	1			T32	1		T103	1		T39	3
auto[2281701376:2415919103]	103	1			T22	1		T79	1		T39	1
auto[2415919104:2550136831]	108	1			T1	1		T34	1		T39	3
auto[2550136832:2684354559]	113	1			T38	1		T43	1		T115	1
auto[2684354560:2818572287]	99	1			T1	1		T3	1		T32	2
auto[2818572288:2952790015]	113	1			T21	1		T34	1		T43	1
auto[2952790016:3087007743]	100	1			T1	1		T39	1		T81	1
auto[3087007744:3221225471]	107	1			T1	1		T32	2		T39	1
auto[3221225472:3355443199]	103	1			T103	1		T104	2		T115	1
auto[3355443200:3489660927]	96	1			T1	1		T32	2		T43	1
auto[3489660928:3623878655]	89	1			T32	1		T34	1		T39	2
auto[3623878656:3758096383]	111	1			T32	1		T33	1		T39	2
auto[3758096384:3892314111]	97	1			T32	1		T38	1		T34	1
auto[3892314112:4026531839]	92	1			T1	1		T32	1		T76	1
auto[4026531840:4160749567]	121	1			T103	1		T104	1		T22	1
auto[4160749568:4294967295]	97	1			T1	1		T13	1		T32	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	59	1			T3	1		T48	1		T95	1
auto[0:134217727]	auto[1]	49	1			T33	1		T103	1		T176	1
auto[134217728:268435455]	auto[0]	45	1			T32	1		T39	2		T55	1
auto[134217728:268435455]	auto[1]	50	1			T14	1		T22	1		T39	1
auto[268435456:402653183]	auto[0]	35	1			T1	1		T32	1		T33	1
auto[268435456:402653183]	auto[1]	61	1			T16	1		T103	1		T115	1
auto[402653184:536870911]	auto[0]	46	1			T3	1		T32	1		T39	1
auto[402653184:536870911]	auto[1]	56	1			T115	1		T39	2		T176	1
auto[536870912:671088639]	auto[0]	42	1			T32	1		T34	1		T116	1
auto[536870912:671088639]	auto[1]	49	1			T76	1		T39	1		T220	1
auto[671088640:805306367]	auto[0]	54	1			T1	1		T22	1		T116	1
auto[671088640:805306367]	auto[1]	50	1			T32	1		T22	1		T39	1
auto[805306368:939524095]	auto[0]	34	1			T32	1		T49	1		T35	1
auto[805306368:939524095]	auto[1]	70	1			T1	1		T32	1		T21	1
auto[939524096:1073741823]	auto[0]	45	1			T39	1		T82	1		T296	1
auto[939524096:1073741823]	auto[1]	66	1			T1	1		T32	1		T104	1
auto[1073741824:1207959551]	auto[0]	51	1			T1	1		T32	1		T33	1
auto[1073741824:1207959551]	auto[1]	59	1			T34	1		T79	1		T39	1
auto[1207959552:1342177279]	auto[0]	50	1			T115	1		T39	1		T50	1
auto[1207959552:1342177279]	auto[1]	60	1			T1	1		T13	1		T131	1
auto[1342177280:1476395007]	auto[0]	44	1			T1	1		T32	2		T34	1
auto[1342177280:1476395007]	auto[1]	59	1			T1	1		T14	1		T39	1
auto[1476395008:1610612735]	auto[0]	50	1			T56	1		T48	1		T40	1
auto[1476395008:1610612735]	auto[1]	53	1			T1	2		T76	1		T43	1
auto[1610612736:1744830463]	auto[0]	44	1			T177	1		T39	1		T191	1
auto[1610612736:1744830463]	auto[1]	48	1			T32	1		T39	1		T176	1
auto[1744830464:1879048191]	auto[0]	53	1			T1	1		T21	1		T88	1
auto[1744830464:1879048191]	auto[1]	53	1			T32	2		T22	1		T176	1
auto[1879048192:2013265919]	auto[0]	60	1			T79	2		T39	1		T59	1
auto[1879048192:2013265919]	auto[1]	40	1			T1	1		T32	2		T39	1
auto[2013265920:2147483647]	auto[0]	54	1			T34	1		T177	1		T39	1
auto[2013265920:2147483647]	auto[1]	57	1			T103	1		T177	1		T167	1
auto[2147483648:2281701375]	auto[0]	39	1			T32	1		T103	1		T174	1
auto[2147483648:2281701375]	auto[1]	50	1			T39	3		T250	1		T49	1
auto[2281701376:2415919103]	auto[0]	48	1			T22	1		T79	1		T39	1
auto[2281701376:2415919103]	auto[1]	55	1			T176	1		T42	1		T110	1
auto[2415919104:2550136831]	auto[0]	56	1			T34	1		T39	2		T81	1
auto[2415919104:2550136831]	auto[1]	52	1			T1	1		T39	1		T56	1
auto[2550136832:2684354559]	auto[0]	54	1			T38	1		T39	2		T56	1
auto[2550136832:2684354559]	auto[1]	59	1			T43	1		T115	1		T39	1
auto[2684354560:2818572287]	auto[0]	53	1			T3	1		T32	1		T115	1
auto[2684354560:2818572287]	auto[1]	46	1			T1	1		T32	1		T48	1
auto[2818572288:2952790015]	auto[0]	51	1			T21	1		T34	1		T43	1
auto[2818572288:2952790015]	auto[1]	62	1			T104	1		T39	1		T59	1
auto[2952790016:3087007743]	auto[0]	44	1			T1	1		T81	1		T189	1
auto[2952790016:3087007743]	auto[1]	56	1			T39	1		T77	1		T49	1
auto[3087007744:3221225471]	auto[0]	50	1			T1	1		T39	1		T77	1
auto[3087007744:3221225471]	auto[1]	57	1			T32	2		T56	1		T110	1
auto[3221225472:3355443199]	auto[0]	45	1			T115	1		T39	2		T296	1
auto[3221225472:3355443199]	auto[1]	58	1			T103	1		T104	2		T39	2
auto[3355443200:3489660927]	auto[0]	48	1			T43	1		T39	2		T189	1
auto[3355443200:3489660927]	auto[1]	48	1			T1	1		T32	2		T217	1
auto[3489660928:3623878655]	auto[0]	39	1			T39	1		T81	1		T174	1
auto[3489660928:3623878655]	auto[1]	50	1			T32	1		T34	1		T39	1
auto[3623878656:3758096383]	auto[0]	51	1			T33	1		T189	1		T56	1
auto[3623878656:3758096383]	auto[1]	60	1			T32	1		T39	2		T189	1
auto[3758096384:3892314111]	auto[0]	57	1			T32	1		T38	1		T34	1
auto[3758096384:3892314111]	auto[1]	40	1			T56	1		T110	1		T93	1
auto[3892314112:4026531839]	auto[0]	38	1			T115	1		T59	1		T91	1
auto[3892314112:4026531839]	auto[1]	54	1			T1	1		T32	1		T76	1
auto[4026531840:4160749567]	auto[0]	61	1			T103	1		T22	1		T56	1
auto[4026531840:4160749567]	auto[1]	60	1			T104	1		T259	1		T191	1
auto[4160749568:4294967295]	auto[0]	42	1			T32	1		T79	1		T63	1
auto[4160749568:4294967295]	auto[1]	55	1			T1	1		T13	1		T34	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1538

1

T1

6

T3

2

T32

14

auto[1]

1748

1

T1

13

T3

1

T13

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	120	1			T1	2		T32	1		T21	1
auto[134217728:268435455]	102	1			T1	1		T34	1		T103	1
auto[268435456:402653183]	103	1			T177	1		T39	1		T173	1
auto[402653184:536870911]	97	1			T43	1		T39	3		T56	1
auto[536870912:671088639]	112	1			T1	1		T131	1		T81	1
auto[671088640:805306367]	109	1			T34	1		T76	1		T103	1
auto[805306368:939524095]	118	1			T33	1		T43	1		T104	1
auto[939524096:1073741823]	90	1			T1	2		T32	1		T34	1
auto[1073741824:1207959551]	112	1			T1	2		T3	1		T32	2
auto[1207959552:1342177279]	106	1			T1	1		T32	3		T34	1
auto[1342177280:1476395007]	99	1			T1	1		T14	1		T32	1
auto[1476395008:1610612735]	111	1			T1	2		T3	1		T13	1
auto[1610612736:1744830463]	121	1			T33	1		T104	2		T22	2
auto[1744830464:1879048191]	118	1			T32	1		T34	1		T131	1
auto[1879048192:2013265919]	112	1			T1	1		T104	1		T115	1
auto[2013265920:2147483647]	104	1			T39	1		T189	1		T77	1
auto[2147483648:2281701375]	107	1			T34	1		T115	1		T39	1
auto[2281701376:2415919103]	122	1			T1	2		T76	2		T104	2
auto[2415919104:2550136831]	108	1			T14	1		T16	1		T32	3
auto[2550136832:2684354559]	99	1			T21	1		T43	1		T39	2
auto[2684354560:2818572287]	86	1			T79	1		T39	2		T176	1
auto[2818572288:2952790015]	89	1			T13	1		T32	2		T177	1
auto[2952790016:3087007743]	100	1			T1	1		T32	2		T115	1
auto[3087007744:3221225471]	99	1			T1	2		T32	1		T76	1
auto[3221225472:3355443199]	92	1			T3	1		T32	2		T22	1
auto[3355443200:3489660927]	87	1			T32	1		T38	1		T22	1
auto[3489660928:3623878655]	85	1			T32	2		T34	1		T79	1
auto[3623878656:3758096383]	86	1			T32	1		T34	1		T39	3
auto[3758096384:3892314111]	92	1			T33	1		T43	2		T115	1
auto[3892314112:4026531839]	112	1			T32	1		T21	1		T39	1
auto[4026531840:4160749567]	100	1			T32	1		T38	1		T39	1
auto[4160749568:4294967295]	88	1			T1	1		T32	2		T103	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T1	1		T103	1		T43	1
auto[0:134217727]	auto[1]	69	1			T1	1		T32	1		T21	1
auto[134217728:268435455]	auto[0]	46	1			T103	1		T39	1		T116	1
auto[134217728:268435455]	auto[1]	56	1			T1	1		T34	1		T177	1
auto[268435456:402653183]	auto[0]	47	1			T177	1		T39	1		T250	1
auto[268435456:402653183]	auto[1]	56	1			T173	1		T220	1		T47	1
auto[402653184:536870911]	auto[0]	38	1			T49	1		T395	1		T356	1
auto[402653184:536870911]	auto[1]	59	1			T43	1		T39	3		T56	1
auto[536870912:671088639]	auto[0]	60	1			T186	1		T48	1		T49	2
auto[536870912:671088639]	auto[1]	52	1			T1	1		T131	1		T81	1
auto[671088640:805306367]	auto[0]	53	1			T34	1		T39	1		T81	1
auto[671088640:805306367]	auto[1]	56	1			T76	1		T103	1		T39	1
auto[805306368:939524095]	auto[0]	52	1			T33	1		T43	1		T177	1
auto[805306368:939524095]	auto[1]	66	1			T104	1		T176	1		T88	1
auto[939524096:1073741823]	auto[0]	40	1			T1	1		T34	1		T39	1
auto[939524096:1073741823]	auto[1]	50	1			T1	1		T32	1		T103	1
auto[1073741824:1207959551]	auto[0]	48	1			T32	1		T79	1		T39	2
auto[1073741824:1207959551]	auto[1]	64	1			T1	2		T3	1		T32	1
auto[1207959552:1342177279]	auto[0]	50	1			T32	1		T39	1		T88	1
auto[1207959552:1342177279]	auto[1]	56	1			T1	1		T32	2		T34	1
auto[1342177280:1476395007]	auto[0]	36	1			T1	1		T39	1		T116	1
auto[1342177280:1476395007]	auto[1]	63	1			T14	1		T32	1		T22	1
auto[1476395008:1610612735]	auto[0]	44	1			T3	1		T32	1		T33	1
auto[1476395008:1610612735]	auto[1]	67	1			T1	2		T13	1		T115	1
auto[1610612736:1744830463]	auto[0]	52	1			T33	1		T22	1		T59	1
auto[1610612736:1744830463]	auto[1]	69	1			T104	2		T22	1		T39	2
auto[1744830464:1879048191]	auto[0]	62	1			T34	1		T116	1		T186	1
auto[1744830464:1879048191]	auto[1]	56	1			T32	1		T131	1		T39	1
auto[1879048192:2013265919]	auto[0]	50	1			T1	1		T79	2		T49	1
auto[1879048192:2013265919]	auto[1]	62	1			T104	1		T115	1		T39	1
auto[2013265920:2147483647]	auto[0]	43	1			T56	1		T48	1		T187	2
auto[2013265920:2147483647]	auto[1]	61	1			T39	1		T189	1		T77	1
auto[2147483648:2281701375]	auto[0]	57	1			T34	1		T115	1		T39	1
auto[2147483648:2281701375]	auto[1]	50	1			T56	1		T93	1		T191	1
auto[2281701376:2415919103]	auto[0]	52	1			T1	1		T115	1		T22	2
auto[2281701376:2415919103]	auto[1]	70	1			T1	1		T76	2		T104	2
auto[2415919104:2550136831]	auto[0]	62	1			T32	1		T77	1		T49	1
auto[2415919104:2550136831]	auto[1]	46	1			T14	1		T16	1		T32	2
auto[2550136832:2684354559]	auto[0]	51	1			T21	1		T43	1		T39	1
auto[2550136832:2684354559]	auto[1]	48	1			T39	1		T56	1		T95	1
auto[2684354560:2818572287]	auto[0]	36	1			T79	1		T39	1		T116	1
auto[2684354560:2818572287]	auto[1]	50	1			T39	1		T176	1		T174	1
auto[2818572288:2952790015]	auto[0]	37	1			T32	1		T79	1		T44	1
auto[2818572288:2952790015]	auto[1]	52	1			T13	1		T32	1		T177	1
auto[2952790016:3087007743]	auto[0]	49	1			T32	2		T115	1		T189	1
auto[2952790016:3087007743]	auto[1]	51	1			T1	1		T56	1		T82	1
auto[3087007744:3221225471]	auto[0]	58	1			T1	1		T32	1		T39	2
auto[3087007744:3221225471]	auto[1]	41	1			T1	1		T76	1		T39	1
auto[3221225472:3355443199]	auto[0]	41	1			T3	1		T32	1		T22	1
auto[3221225472:3355443199]	auto[1]	51	1			T32	1		T176	1		T189	1
auto[3355443200:3489660927]	auto[0]	44	1			T32	1		T38	1		T189	1
auto[3355443200:3489660927]	auto[1]	43	1			T22	1		T94	1		T5	1
auto[3489660928:3623878655]	auto[0]	33	1			T32	1		T79	1		T93	1
auto[3489660928:3623878655]	auto[1]	52	1			T32	1		T34	1		T42	1
auto[3623878656:3758096383]	auto[0]	38	1			T32	1		T34	1		T39	1
auto[3623878656:3758096383]	auto[1]	48	1			T39	2		T173	1		T164	1
auto[3758096384:3892314111]	auto[0]	51	1			T33	1		T115	1		T39	1
auto[3758096384:3892314111]	auto[1]	41	1			T43	2		T296	1		T191	1
auto[3892314112:4026531839]	auto[0]	64	1			T32	1		T21	1		T81	1
auto[3892314112:4026531839]	auto[1]	48	1			T39	1		T93	1		T49	1
auto[4026531840:4160749567]	auto[0]	53	1			T32	1		T38	1		T39	1
auto[4026531840:4160749567]	auto[1]	47	1			T49	1		T191	1		T40	1
auto[4160749568:4294967295]	auto[0]	40	1			T39	1		T42	1		T187	1
auto[4160749568:4294967295]	auto[1]	48	1			T1	1		T32	2		T103	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1519

1

T1

7

T3

3

T32

10

auto[1]

1763

1

T1

12

T13

2

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	83	1			T1	1		T3	1		T43	1
auto[134217728:268435455]	103	1			T32	1		T34	1		T177	1
auto[268435456:402653183]	93	1			T13	1		T34	2		T76	1
auto[402653184:536870911]	94	1			T32	2		T39	2		T42	1
auto[536870912:671088639]	105	1			T38	1		T34	1		T115	1
auto[671088640:805306367]	115	1			T1	1		T13	1		T14	1
auto[805306368:939524095]	94	1			T1	1		T32	1		T43	1
auto[939524096:1073741823]	109	1			T1	1		T14	1		T32	1
auto[1073741824:1207959551]	99	1			T43	1		T39	4		T77	1
auto[1207959552:1342177279]	116	1			T1	3		T32	1		T81	1
auto[1342177280:1476395007]	81	1			T38	1		T76	1		T39	2
auto[1476395008:1610612735]	115	1			T32	2		T21	2		T177	1
auto[1610612736:1744830463]	107	1			T32	1		T104	1		T115	1
auto[1744830464:1879048191]	105	1			T1	1		T33	1		T115	1
auto[1879048192:2013265919]	101	1			T32	1		T103	1		T59	1
auto[2013265920:2147483647]	104	1			T34	1		T115	1		T39	1
auto[2147483648:2281701375]	100	1			T103	1		T43	1		T22	1
auto[2281701376:2415919103]	94	1			T32	1		T33	1		T21	1
auto[2415919104:2550136831]	116	1			T1	1		T32	3		T39	1
auto[2550136832:2684354559]	94	1			T3	1		T32	1		T103	1
auto[2684354560:2818572287]	105	1			T1	1		T3	1		T32	2
auto[2818572288:2952790015]	117	1			T1	1		T104	1		T22	1
auto[2952790016:3087007743]	101	1			T1	1		T32	2		T34	1
auto[3087007744:3221225471]	100	1			T1	1		T32	1		T104	1
auto[3221225472:3355443199]	106	1			T1	1		T32	1		T43	1
auto[3355443200:3489660927]	122	1			T33	1		T34	1		T76	1
auto[3489660928:3623878655]	115	1			T1	1		T32	3		T115	1
auto[3623878656:3758096383]	113	1			T76	1		T115	1		T22	2
auto[3758096384:3892314111]	98	1			T1	1		T132	1		T39	1
auto[3892314112:4026531839]	88	1			T1	2		T33	1		T43	1
auto[4026531840:4160749567]	92	1			T32	1		T39	2		T59	1
auto[4160749568:4294967295]	97	1			T1	1		T32	1		T103	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	35	1			T3	1		T43	1		T39	1
auto[0:134217727]	auto[1]	48	1			T1	1		T39	1		T189	1
auto[134217728:268435455]	auto[0]	44	1			T32	1		T296	1		T6	1
auto[134217728:268435455]	auto[1]	59	1			T34	1		T177	1		T39	1
auto[268435456:402653183]	auto[0]	44	1			T34	2		T39	1		T94	1
auto[268435456:402653183]	auto[1]	49	1			T13	1		T76	1		T104	1
auto[402653184:536870911]	auto[0]	44	1			T44	1		T6	1		T187	1
auto[402653184:536870911]	auto[1]	50	1			T32	2		T39	2		T42	1
auto[536870912:671088639]	auto[0]	62	1			T38	1		T34	1		T115	1
auto[536870912:671088639]	auto[1]	43	1			T238	1		T49	2		T369	1
auto[671088640:805306367]	auto[0]	47	1			T32	1		T88	1		T56	2
auto[671088640:805306367]	auto[1]	68	1			T1	1		T13	1		T14	1
auto[805306368:939524095]	auto[0]	44	1			T32	1		T115	1		T39	1
auto[805306368:939524095]	auto[1]	50	1			T1	1		T43	1		T104	1
auto[939524096:1073741823]	auto[0]	51	1			T34	1		T250	1		T44	1
auto[939524096:1073741823]	auto[1]	58	1			T1	1		T14	1		T32	1
auto[1073741824:1207959551]	auto[0]	39	1			T43	1		T39	2		T77	1
auto[1073741824:1207959551]	auto[1]	60	1			T39	2		T56	1		T111	1
auto[1207959552:1342177279]	auto[0]	63	1			T1	2		T81	1		T189	1
auto[1207959552:1342177279]	auto[1]	53	1			T1	1		T32	1		T250	1
auto[1342177280:1476395007]	auto[0]	41	1			T38	1		T39	1		T40	1
auto[1342177280:1476395007]	auto[1]	40	1			T76	1		T39	1		T48	1
auto[1476395008:1610612735]	auto[0]	50	1			T21	1		T177	1		T39	2
auto[1476395008:1610612735]	auto[1]	65	1			T32	2		T21	1		T39	4
auto[1610612736:1744830463]	auto[0]	43	1			T42	1		T56	1		T44	1
auto[1610612736:1744830463]	auto[1]	64	1			T32	1		T104	1		T115	1
auto[1744830464:1879048191]	auto[0]	52	1			T33	1		T115	1		T116	1
auto[1744830464:1879048191]	auto[1]	53	1			T1	1		T173	1		T164	2
auto[1879048192:2013265919]	auto[0]	47	1			T103	1		T59	1		T81	1
auto[1879048192:2013265919]	auto[1]	54	1			T32	1		T56	1		T47	1
auto[2013265920:2147483647]	auto[0]	52	1			T34	1		T189	1		T50	1
auto[2013265920:2147483647]	auto[1]	52	1			T115	1		T39	1		T176	1
auto[2147483648:2281701375]	auto[0]	43	1			T43	1		T174	1		T35	1
auto[2147483648:2281701375]	auto[1]	57	1			T103	1		T22	1		T49	1
auto[2281701376:2415919103]	auto[0]	43	1			T32	1		T33	1		T21	1
auto[2281701376:2415919103]	auto[1]	51	1			T56	1		T49	1		T259	1
auto[2415919104:2550136831]	auto[0]	48	1			T56	1		T49	1		T227	1
auto[2415919104:2550136831]	auto[1]	68	1			T1	1		T32	3		T39	1
auto[2550136832:2684354559]	auto[0]	56	1			T3	1		T32	1		T22	1
auto[2550136832:2684354559]	auto[1]	38	1			T103	1		T39	1		T82	1
auto[2684354560:2818572287]	auto[0]	40	1			T3	1		T32	2		T34	1
auto[2684354560:2818572287]	auto[1]	65	1			T1	1		T116	1		T173	1
auto[2818572288:2952790015]	auto[0]	58	1			T22	1		T79	2		T39	1
auto[2818572288:2952790015]	auto[1]	59	1			T1	1		T104	1		T39	1
auto[2952790016:3087007743]	auto[0]	47	1			T1	1		T191	1		T227	1
auto[2952790016:3087007743]	auto[1]	54	1			T32	2		T34	1		T103	1
auto[3087007744:3221225471]	auto[0]	51	1			T39	2		T238	1		T49	1
auto[3087007744:3221225471]	auto[1]	49	1			T1	1		T32	1		T104	1
auto[3221225472:3355443199]	auto[0]	46	1			T32	1		T35	1		T296	1
auto[3221225472:3355443199]	auto[1]	60	1			T1	1		T43	1		T39	1
auto[3355443200:3489660927]	auto[0]	47	1			T33	1		T34	1		T115	1
auto[3355443200:3489660927]	auto[1]	75	1			T76	1		T103	1		T104	1
auto[3489660928:3623878655]	auto[0]	47	1			T1	1		T32	1		T115	1
auto[3489660928:3623878655]	auto[1]	68	1			T32	2		T79	1		T39	1
auto[3623878656:3758096383]	auto[0]	50	1			T115	1		T22	2		T79	1
auto[3623878656:3758096383]	auto[1]	63	1			T76	1		T39	2		T176	1
auto[3758096384:3892314111]	auto[0]	46	1			T39	1		T59	1		T116	1
auto[3758096384:3892314111]	auto[1]	52	1			T1	1		T132	1		T173	1
auto[3892314112:4026531839]	auto[0]	42	1			T1	2		T43	1		T56	1
auto[3892314112:4026531839]	auto[1]	46	1			T33	1		T22	1		T131	2
auto[4026531840:4160749567]	auto[0]	48	1			T32	1		T39	1		T189	1
auto[4026531840:4160749567]	auto[1]	44	1			T39	1		T59	1		T91	1
auto[4160749568:4294967295]	auto[0]	49	1			T1	1		T189	1		T174	1
auto[4160749568:4294967295]	auto[1]	48	1			T32	1		T103	1		T257	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1516

1

T1

6

T3

2

T32

12

auto[1]

1773

1

T1

13

T3

1

T13

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	113	1			T32	1		T34	1		T76	1
auto[134217728:268435455]	123	1			T1	1		T32	1		T33	1
auto[268435456:402653183]	108	1			T1	1		T34	1		T76	1
auto[402653184:536870911]	115	1			T1	2		T32	2		T39	1
auto[536870912:671088639]	101	1			T3	1		T32	1		T43	1
auto[671088640:805306367]	104	1			T1	1		T115	1		T22	2
auto[805306368:939524095]	95	1			T32	3		T104	2		T39	1
auto[939524096:1073741823]	93	1			T1	1		T115	1		T131	1
auto[1073741824:1207959551]	118	1			T1	2		T32	1		T103	1
auto[1207959552:1342177279]	95	1			T13	1		T32	1		T34	1
auto[1342177280:1476395007]	109	1			T115	1		T131	1		T59	1
auto[1476395008:1610612735]	106	1			T1	2		T32	1		T103	1
auto[1610612736:1744830463]	102	1			T76	1		T39	1		T176	1
auto[1744830464:1879048191]	107	1			T32	1		T33	1		T21	1
auto[1879048192:2013265919]	91	1			T1	1		T32	2		T34	1
auto[2013265920:2147483647]	113	1			T1	1		T33	1		T21	1
auto[2147483648:2281701375]	98	1			T14	1		T32	1		T43	1
auto[2281701376:2415919103]	93	1			T1	1		T32	1		T34	1
auto[2415919104:2550136831]	88	1			T32	1		T104	1		T39	2
auto[2550136832:2684354559]	100	1			T13	1		T32	1		T22	2
auto[2684354560:2818572287]	95	1			T1	2		T32	2		T22	1
auto[2818572288:2952790015]	122	1			T3	1		T32	1		T33	1
auto[2952790016:3087007743]	110	1			T1	2		T34	1		T39	1
auto[3087007744:3221225471]	103	1			T38	1		T39	2		T81	1
auto[3221225472:3355443199]	92	1			T1	1		T14	1		T32	1
auto[3355443200:3489660927]	108	1			T32	1		T104	1		T39	2
auto[3489660928:3623878655]	92	1			T1	1		T16	1		T39	1
auto[3623878656:3758096383]	97	1			T32	1		T34	1		T43	1
auto[3758096384:3892314111]	82	1			T32	2		T21	1		T79	1
auto[3892314112:4026531839]	94	1			T3	1		T34	1		T43	1
auto[4026531840:4160749567]	108	1			T32	2		T76	1		T115	1
auto[4160749568:4294967295]	114	1			T131	1		T39	2		T167	1