Unified Coverage Report :: Group Instance : sealing_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1509

1

T1

7

T3

2

T32

10

auto[1]

1771

1

T1

12

T3

1

T13

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T1	1		T104	1		T22	1
auto[134217728:268435455]	88	1			T32	1		T34	1		T115	1
auto[268435456:402653183]	106	1			T32	1		T39	2		T189	1
auto[402653184:536870911]	103	1			T32	1		T21	1		T104	1
auto[536870912:671088639]	102	1			T32	1		T39	3		T176	1
auto[671088640:805306367]	97	1			T250	1		T56	2		T195	1
auto[805306368:939524095]	116	1			T1	2		T103	1		T43	1
auto[939524096:1073741823]	118	1			T1	2		T21	1		T76	1
auto[1073741824:1207959551]	98	1			T14	1		T32	3		T34	1
auto[1207959552:1342177279]	100	1			T1	1		T32	3		T34	1
auto[1342177280:1476395007]	101	1			T32	1		T76	1		T43	2
auto[1476395008:1610612735]	97	1			T32	1		T76	1		T115	2
auto[1610612736:1744830463]	96	1			T1	1		T3	1		T32	1
auto[1744830464:1879048191]	122	1			T32	2		T34	1		T115	1
auto[1879048192:2013265919]	86	1			T1	1		T177	1		T55	1
auto[2013265920:2147483647]	89	1			T1	1		T104	1		T116	1
auto[2147483648:2281701375]	102	1			T32	1		T33	1		T177	1
auto[2281701376:2415919103]	109	1			T32	1		T22	1		T39	1
auto[2415919104:2550136831]	104	1			T32	3		T177	1		T79	1
auto[2550136832:2684354559]	99	1			T1	1		T33	1		T38	1
auto[2684354560:2818572287]	111	1			T1	1		T38	1		T76	1
auto[2818572288:2952790015]	110	1			T32	3		T103	1		T79	1
auto[2952790016:3087007743]	120	1			T3	1		T32	1		T34	1
auto[3087007744:3221225471]	87	1			T32	1		T34	1		T39	4
auto[3221225472:3355443199]	98	1			T13	1		T32	1		T103	1
auto[3355443200:3489660927]	97	1			T1	1		T21	1		T43	1
auto[3489660928:3623878655]	111	1			T1	3		T32	1		T33	1
auto[3623878656:3758096383]	98	1			T1	1		T34	1		T189	1
auto[3758096384:3892314111]	90	1			T1	1		T13	1		T22	2
auto[3892314112:4026531839]	104	1			T14	1		T34	1		T103	1
auto[4026531840:4160749567]	126	1			T1	1		T3	1		T33	1
auto[4160749568:4294967295]	103	1			T1	1		T32	1		T103	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T22	1		T79	1		T81	1
auto[0:134217727]	auto[1]	50	1			T1	1		T104	1		T39	2
auto[134217728:268435455]	auto[0]	46	1			T32	1		T34	1		T115	1
auto[134217728:268435455]	auto[1]	42	1			T186	1		T6	1		T408	1
auto[268435456:402653183]	auto[0]	42	1			T39	1		T49	1		T241	1
auto[268435456:402653183]	auto[1]	64	1			T32	1		T39	1		T189	1
auto[402653184:536870911]	auto[0]	43	1			T21	1		T59	1		T56	1
auto[402653184:536870911]	auto[1]	60	1			T32	1		T104	1		T131	1
auto[536870912:671088639]	auto[0]	50	1			T32	1		T39	1		T238	1
auto[536870912:671088639]	auto[1]	52	1			T39	2		T176	1		T173	1
auto[671088640:805306367]	auto[0]	47	1			T195	1		T178	1		T78	1
auto[671088640:805306367]	auto[1]	50	1			T250	1		T56	2		T187	1
auto[805306368:939524095]	auto[0]	51	1			T132	1		T39	1		T56	1
auto[805306368:939524095]	auto[1]	65	1			T1	2		T103	1		T43	1
auto[939524096:1073741823]	auto[0]	55	1			T21	1		T115	1		T177	1
auto[939524096:1073741823]	auto[1]	63	1			T1	2		T76	1		T39	4
auto[1073741824:1207959551]	auto[0]	31	1			T191	1		T227	1		T187	1
auto[1073741824:1207959551]	auto[1]	67	1			T14	1		T32	3		T34	1
auto[1207959552:1342177279]	auto[0]	49	1			T34	1		T79	1		T39	2
auto[1207959552:1342177279]	auto[1]	51	1			T1	1		T32	3		T131	1
auto[1342177280:1476395007]	auto[0]	52	1			T43	1		T94	1		T187	1
auto[1342177280:1476395007]	auto[1]	49	1			T32	1		T76	1		T43	1
auto[1476395008:1610612735]	auto[0]	46	1			T115	1		T39	1		T189	2
auto[1476395008:1610612735]	auto[1]	51	1			T32	1		T76	1		T115	1
auto[1610612736:1744830463]	auto[0]	45	1			T1	1		T3	1		T32	1
auto[1610612736:1744830463]	auto[1]	51	1			T34	1		T103	1		T39	1
auto[1744830464:1879048191]	auto[0]	55	1			T34	1		T39	1		T174	1
auto[1744830464:1879048191]	auto[1]	67	1			T32	2		T115	1		T39	3
auto[1879048192:2013265919]	auto[0]	40	1			T167	1		T187	1		T40	1
auto[1879048192:2013265919]	auto[1]	46	1			T1	1		T177	1		T55	1
auto[2013265920:2147483647]	auto[0]	44	1			T1	1		T116	1		T77	1
auto[2013265920:2147483647]	auto[1]	45	1			T104	1		T95	3		T49	1
auto[2147483648:2281701375]	auto[0]	44	1			T32	1		T39	1		T35	1
auto[2147483648:2281701375]	auto[1]	58	1			T33	1		T177	1		T39	2
auto[2281701376:2415919103]	auto[0]	47	1			T22	1		T59	1		T44	1
auto[2281701376:2415919103]	auto[1]	62	1			T32	1		T39	1		T189	1
auto[2415919104:2550136831]	auto[0]	49	1			T32	1		T177	1		T79	1
auto[2415919104:2550136831]	auto[1]	55	1			T32	2		T88	1		T56	2
auto[2550136832:2684354559]	auto[0]	43	1			T33	1		T38	1		T177	1
auto[2550136832:2684354559]	auto[1]	56	1			T1	1		T131	1		T164	1
auto[2684354560:2818572287]	auto[0]	57	1			T1	1		T38	1		T76	1
auto[2684354560:2818572287]	auto[1]	54	1			T39	1		T56	1		T259	1
auto[2818572288:2952790015]	auto[0]	47	1			T32	1		T79	1		T56	1
auto[2818572288:2952790015]	auto[1]	63	1			T32	2		T103	1		T39	2
auto[2952790016:3087007743]	auto[0]	56	1			T32	1		T43	1		T79	1
auto[2952790016:3087007743]	auto[1]	64	1			T3	1		T34	1		T39	1
auto[3087007744:3221225471]	auto[0]	43	1			T34	1		T39	2		T82	1
auto[3087007744:3221225471]	auto[1]	44	1			T32	1		T39	2		T56	1
auto[3221225472:3355443199]	auto[0]	45	1			T32	1		T103	1		T50	1
auto[3221225472:3355443199]	auto[1]	53	1			T13	1		T39	1		T59	1
auto[3355443200:3489660927]	auto[0]	44	1			T21	1		T43	1		T39	1
auto[3355443200:3489660927]	auto[1]	53	1			T1	1		T104	1		T22	1
auto[3489660928:3623878655]	auto[0]	45	1			T1	2		T32	1		T33	1
auto[3489660928:3623878655]	auto[1]	66	1			T1	1		T39	2		T173	1
auto[3623878656:3758096383]	auto[0]	53	1			T1	1		T34	1		T189	1
auto[3623878656:3758096383]	auto[1]	45	1			T56	1		T49	1		T187	1
auto[3758096384:3892314111]	auto[0]	38	1			T82	1		T187	1		T40	1
auto[3758096384:3892314111]	auto[1]	52	1			T1	1		T13	1		T22	2
auto[3892314112:4026531839]	auto[0]	46	1			T34	1		T39	1		T56	1
auto[3892314112:4026531839]	auto[1]	58	1			T14	1		T103	1		T250	1
auto[4026531840:4160749567]	auto[0]	62	1			T1	1		T3	1		T33	1
auto[4026531840:4160749567]	auto[1]	64	1			T174	1		T250	1		T259	1
auto[4160749568:4294967295]	auto[0]	52	1			T32	1		T103	1		T39	1
auto[4160749568:4294967295]	auto[1]	51	1			T1	1		T115	1		T39	1