Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6798

1

T1

49

T3

3

T13

2

auto[1]

342

1

T103

8

T104

13

T115

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2903	1			T1	19		T3	1		T13	1
auto[134217728:268435455]	136	1			T1	2		T34	1		T76	1
auto[268435456:402653183]	174	1			T1	1		T14	1		T32	2
auto[402653184:536870911]	140	1			T1	1		T104	1		T131	1
auto[536870912:671088639]	141	1			T39	2		T88	1		T164	1
auto[671088640:805306367]	154	1			T1	2		T38	1		T39	2
auto[805306368:939524095]	144	1			T34	1		T104	1		T132	1
auto[939524096:1073741823]	122	1			T14	1		T32	2		T22	1
auto[1073741824:1207959551]	131	1			T1	2		T32	1		T34	1
auto[1207959552:1342177279]	150	1			T1	2		T13	1		T32	1
auto[1342177280:1476395007]	126	1			T1	1		T32	4		T103	1
auto[1476395008:1610612735]	150	1			T33	1		T21	1		T104	1
auto[1610612736:1744830463]	146	1			T14	1		T32	2		T76	1
auto[1744830464:1879048191]	134	1			T1	1		T32	2		T104	1
auto[1879048192:2013265919]	141	1			T1	1		T34	1		T103	1
auto[2013265920:2147483647]	130	1			T1	3		T32	1		T115	2
auto[2147483648:2281701375]	113	1			T1	1		T76	1		T43	1
auto[2281701376:2415919103]	140	1			T1	3		T32	1		T103	1
auto[2415919104:2550136831]	151	1			T14	1		T32	3		T103	1
auto[2550136832:2684354559]	128	1			T103	1		T104	1		T115	2
auto[2684354560:2818572287]	111	1			T1	1		T32	1		T43	1
auto[2818572288:2952790015]	132	1			T1	2		T32	1		T34	1
auto[2952790016:3087007743]	141	1			T1	1		T14	1		T32	1
auto[3087007744:3221225471]	111	1			T1	2		T33	1		T21	1
auto[3221225472:3355443199]	117	1			T1	1		T104	1		T22	1
auto[3355443200:3489660927]	149	1			T104	2		T39	2		T116	2
auto[3489660928:3623878655]	129	1			T1	2		T3	1		T32	2
auto[3623878656:3758096383]	133	1			T1	1		T32	2		T34	2
auto[3758096384:3892314111]	139	1			T32	1		T34	1		T103	2
auto[3892314112:4026531839]	133	1			T3	1		T32	1		T21	1
auto[4026531840:4160749567]	148	1			T32	1		T34	3		T76	1
auto[4160749568:4294967295]	143	1			T32	1		T132	1		T39	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2888	1			T1	19		T3	1		T13	1
auto[0:134217727]	auto[1]	15	1			T104	1		T131	1		T257	1
auto[134217728:268435455]	auto[0]	132	1			T1	2		T34	1		T76	1
auto[134217728:268435455]	auto[1]	4	1			T217	1		T232	1		T214	1
auto[268435456:402653183]	auto[0]	158	1			T1	1		T14	1		T32	2
auto[268435456:402653183]	auto[1]	16	1			T103	2		T104	1		T115	1
auto[402653184:536870911]	auto[0]	128	1			T1	1		T39	1		T88	1
auto[402653184:536870911]	auto[1]	12	1			T104	1		T131	1		T132	1
auto[536870912:671088639]	auto[0]	132	1			T39	2		T88	1		T164	1
auto[536870912:671088639]	auto[1]	9	1			T257	1		T273	2		T291	1
auto[671088640:805306367]	auto[0]	140	1			T1	2		T38	1		T39	2
auto[671088640:805306367]	auto[1]	14	1			T218	1		T317	1		T216	1
auto[805306368:939524095]	auto[0]	133	1			T34	1		T104	1		T39	1
auto[805306368:939524095]	auto[1]	11	1			T132	1		T259	1		T257	1
auto[939524096:1073741823]	auto[0]	111	1			T14	1		T32	2		T22	1
auto[939524096:1073741823]	auto[1]	11	1			T217	1		T232	3		T258	1
auto[1073741824:1207959551]	auto[0]	124	1			T1	2		T32	1		T34	1
auto[1073741824:1207959551]	auto[1]	7	1			T104	1		T217	1		T292	1
auto[1207959552:1342177279]	auto[0]	141	1			T1	2		T13	1		T32	1
auto[1207959552:1342177279]	auto[1]	9	1			T131	1		T257	1		T243	1
auto[1342177280:1476395007]	auto[0]	111	1			T1	1		T32	4		T176	1
auto[1342177280:1476395007]	auto[1]	15	1			T103	1		T104	1		T93	1
auto[1476395008:1610612735]	auto[0]	137	1			T33	1		T21	1		T22	1
auto[1476395008:1610612735]	auto[1]	13	1			T104	1		T257	1		T217	1
auto[1610612736:1744830463]	auto[0]	131	1			T14	1		T32	2		T76	1
auto[1610612736:1744830463]	auto[1]	15	1			T103	2		T104	1		T116	1
auto[1744830464:1879048191]	auto[0]	128	1			T1	1		T32	2		T104	1
auto[1744830464:1879048191]	auto[1]	6	1			T131	1		T273	1		T300	1
auto[1879048192:2013265919]	auto[0]	133	1			T1	1		T34	1		T103	1
auto[1879048192:2013265919]	auto[1]	8	1			T217	1		T273	1		T214	1
auto[2013265920:2147483647]	auto[0]	118	1			T1	3		T32	1		T115	2
auto[2013265920:2147483647]	auto[1]	12	1			T131	1		T257	2		T218	2
auto[2147483648:2281701375]	auto[0]	104	1			T1	1		T76	1		T43	1
auto[2147483648:2281701375]	auto[1]	9	1			T232	1		T287	1		T258	1
auto[2281701376:2415919103]	auto[0]	126	1			T1	3		T32	1		T79	1
auto[2281701376:2415919103]	auto[1]	14	1			T103	1		T257	1		T273	1
auto[2415919104:2550136831]	auto[0]	142	1			T14	1		T32	3		T79	2
auto[2415919104:2550136831]	auto[1]	9	1			T103	1		T131	1		T220	1
auto[2550136832:2684354559]	auto[0]	121	1			T103	1		T115	1		T39	3
auto[2550136832:2684354559]	auto[1]	7	1			T104	1		T115	1		T131	1
auto[2684354560:2818572287]	auto[0]	102	1			T1	1		T32	1		T43	1
auto[2684354560:2818572287]	auto[1]	9	1			T217	1		T232	1		T214	1
auto[2818572288:2952790015]	auto[0]	121	1			T1	2		T32	1		T34	1
auto[2818572288:2952790015]	auto[1]	11	1			T104	1		T115	1		T131	1
auto[2952790016:3087007743]	auto[0]	132	1			T1	1		T14	1		T32	1
auto[2952790016:3087007743]	auto[1]	9	1			T93	1		T216	1		T292	1
auto[3087007744:3221225471]	auto[0]	103	1			T1	2		T33	1		T21	1
auto[3087007744:3221225471]	auto[1]	8	1			T104	1		T132	1		T257	1
auto[3221225472:3355443199]	auto[0]	106	1			T1	1		T22	1		T177	1
auto[3221225472:3355443199]	auto[1]	11	1			T104	1		T131	1		T217	1
auto[3355443200:3489660927]	auto[0]	133	1			T39	2		T116	1		T48	1
auto[3355443200:3489660927]	auto[1]	16	1			T104	2		T116	1		T93	1
auto[3489660928:3623878655]	auto[0]	119	1			T1	2		T3	1		T32	2
auto[3489660928:3623878655]	auto[1]	10	1			T103	1		T131	1		T217	1
auto[3623878656:3758096383]	auto[0]	124	1			T1	1		T32	2		T34	2
auto[3623878656:3758096383]	auto[1]	9	1			T132	1		T218	1		T232	1
auto[3758096384:3892314111]	auto[0]	128	1			T32	1		T34	1		T103	2
auto[3758096384:3892314111]	auto[1]	11	1			T93	1		T220	1		T257	2
auto[3892314112:4026531839]	auto[0]	123	1			T3	1		T32	1		T21	1
auto[3892314112:4026531839]	auto[1]	10	1			T131	1		T325	1		T291	1
auto[4026531840:4160749567]	auto[0]	137	1			T32	1		T34	3		T76	1
auto[4026531840:4160749567]	auto[1]	11	1			T132	1		T93	1		T257	1
auto[4160749568:4294967295]	auto[0]	132	1			T32	1		T39	2		T81	1
auto[4160749568:4294967295]	auto[1]	11	1			T132	1		T217	1		T273	1