Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4487

1

T1

32

T13

4

T14

2

auto[1]

2078

1

T1

6

T3

6

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	212	1			T13	2		T32	2		T21	2
auto[134217728:268435455]	276	1			T3	2		T32	2		T34	4
auto[268435456:402653183]	188	1			T1	2		T34	2		T76	2
auto[402653184:536870911]	210	1			T3	2		T103	2		T131	2
auto[536870912:671088639]	188	1			T39	2		T88	2		T77	2
auto[671088640:805306367]	191	1			T1	2		T76	2		T132	2
auto[805306368:939524095]	182	1			T1	2		T32	4		T34	2
auto[939524096:1073741823]	214	1			T79	2		T39	2		T50	4
auto[1073741824:1207959551]	184	1			T1	4		T32	4		T39	2
auto[1207959552:1342177279]	216	1			T32	4		T22	2		T177	2
auto[1342177280:1476395007]	208	1			T1	4		T21	2		T115	2
auto[1476395008:1610612735]	170	1			T33	4		T103	2		T104	2
auto[1610612736:1744830463]	196	1			T1	2		T3	2		T32	2
auto[1744830464:1879048191]	220	1			T1	2		T76	2		T115	2
auto[1879048192:2013265919]	198	1			T32	2		T33	2		T21	2
auto[2013265920:2147483647]	242	1			T1	2		T38	2		T34	4
auto[2147483648:2281701375]	204	1			T1	2		T32	2		T76	2
auto[2281701376:2415919103]	142	1			T14	2		T32	4		T43	2
auto[2415919104:2550136831]	234	1			T1	2		T32	6		T43	2
auto[2550136832:2684354559]	218	1			T32	2		T43	2		T115	2
auto[2684354560:2818572287]	206	1			T32	2		T34	2		T39	4
auto[2818572288:2952790015]	210	1			T14	2		T16	2		T34	2
auto[2952790016:3087007743]	216	1			T1	2		T32	2		T39	8
auto[3087007744:3221225471]	222	1			T32	2		T34	2		T131	2
auto[3221225472:3355443199]	196	1			T32	4		T176	2		T110	2
auto[3355443200:3489660927]	222	1			T1	2		T13	2		T32	4
auto[3489660928:3623878655]	216	1			T1	4		T115	4		T39	4
auto[3623878656:3758096383]	212	1			T115	2		T177	2		T39	4
auto[3758096384:3892314111]	234	1			T1	2		T32	2		T103	2
auto[3892314112:4026531839]	164	1			T1	4		T104	2		T39	2
auto[4026531840:4160749567]	186	1			T32	2		T33	2		T103	2
auto[4160749568:4294967295]	188	1			T32	4		T38	2		T104	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	170	1			T13	2		T32	2		T21	2
auto[0:134217727]	auto[1]	42	1			T49	2		T201	2		T286	2
auto[134217728:268435455]	auto[0]	178	1			T32	2		T34	4		T43	2
auto[134217728:268435455]	auto[1]	98	1			T3	2		T131	2		T39	2
auto[268435456:402653183]	auto[0]	136	1			T1	2		T34	2		T76	2
auto[268435456:402653183]	auto[1]	52	1			T42	2		T250	2		T6	2
auto[402653184:536870911]	auto[0]	132	1			T103	2		T131	2		T79	2
auto[402653184:536870911]	auto[1]	78	1			T3	2		T56	2		T111	2
auto[536870912:671088639]	auto[0]	140	1			T39	2		T77	2		T56	4
auto[536870912:671088639]	auto[1]	48	1			T88	2		T5	2		T296	2
auto[671088640:805306367]	auto[0]	129	1			T39	2		T189	2		T42	2
auto[671088640:805306367]	auto[1]	62	1			T1	2		T76	2		T132	2
auto[805306368:939524095]	auto[0]	122	1			T1	2		T32	2		T34	2
auto[805306368:939524095]	auto[1]	60	1			T32	2		T40	2		T278	2
auto[939524096:1073741823]	auto[0]	148	1			T50	2		T56	2		T48	2
auto[939524096:1073741823]	auto[1]	66	1			T79	2		T39	2		T50	2
auto[1073741824:1207959551]	auto[0]	124	1			T1	4		T39	2		T164	2
auto[1073741824:1207959551]	auto[1]	60	1			T32	4		T44	2		T35	2
auto[1207959552:1342177279]	auto[0]	148	1			T32	2		T177	2		T39	4
auto[1207959552:1342177279]	auto[1]	68	1			T32	2		T22	2		T94	2
auto[1342177280:1476395007]	auto[0]	146	1			T1	4		T21	2		T22	2
auto[1342177280:1476395007]	auto[1]	62	1			T115	2		T49	4		T187	2
auto[1476395008:1610612735]	auto[0]	110	1			T103	2		T104	2		T39	4
auto[1476395008:1610612735]	auto[1]	60	1			T33	4		T77	2		T56	4
auto[1610612736:1744830463]	auto[0]	148	1			T1	2		T32	2		T43	2
auto[1610612736:1744830463]	auto[1]	48	1			T3	2		T245	2		T398	2
auto[1744830464:1879048191]	auto[0]	152	1			T76	2		T39	6		T173	2
auto[1744830464:1879048191]	auto[1]	68	1			T1	2		T115	2		T176	2
auto[1879048192:2013265919]	auto[0]	124	1			T32	2		T21	2		T49	2
auto[1879048192:2013265919]	auto[1]	74	1			T33	2		T177	2		T39	2
auto[2013265920:2147483647]	auto[0]	180	1			T1	2		T34	4		T103	2
auto[2013265920:2147483647]	auto[1]	62	1			T38	2		T174	2		T250	2
auto[2147483648:2281701375]	auto[0]	144	1			T32	2		T76	2		T22	2
auto[2147483648:2281701375]	auto[1]	60	1			T1	2		T88	2		T178	2
auto[2281701376:2415919103]	auto[0]	88	1			T32	2		T43	2		T110	2
auto[2281701376:2415919103]	auto[1]	54	1			T14	2		T32	2		T42	2
auto[2415919104:2550136831]	auto[0]	154	1			T1	2		T32	2		T43	2
auto[2415919104:2550136831]	auto[1]	80	1			T32	4		T93	2		T220	2
auto[2550136832:2684354559]	auto[0]	138	1			T32	2		T115	2		T39	2
auto[2550136832:2684354559]	auto[1]	80	1			T43	2		T42	2		T56	2
auto[2684354560:2818572287]	auto[0]	140	1			T39	2		T164	2		T167	2
auto[2684354560:2818572287]	auto[1]	66	1			T32	2		T34	2		T39	2
auto[2818572288:2952790015]	auto[0]	128	1			T14	2		T34	2		T39	2
auto[2818572288:2952790015]	auto[1]	82	1			T16	2		T174	2		T111	2
auto[2952790016:3087007743]	auto[0]	148	1			T1	2		T32	2		T39	8
auto[2952790016:3087007743]	auto[1]	68	1			T56	2		T191	2		T187	2
auto[3087007744:3221225471]	auto[0]	144	1			T34	2		T39	2		T189	2
auto[3087007744:3221225471]	auto[1]	78	1			T32	2		T131	2		T49	2
auto[3221225472:3355443199]	auto[0]	126	1			T32	4		T176	2		T49	2
auto[3221225472:3355443199]	auto[1]	70	1			T110	2		T93	2		T178	2
auto[3355443200:3489660927]	auto[0]	140	1			T1	2		T13	2		T32	4
auto[3355443200:3489660927]	auto[1]	82	1			T40	2		T27	2		T178	2
auto[3489660928:3623878655]	auto[0]	160	1			T1	4		T115	4		T39	2
auto[3489660928:3623878655]	auto[1]	56	1			T39	2		T88	2		T116	2
auto[3623878656:3758096383]	auto[0]	154	1			T115	2		T177	2		T39	4
auto[3623878656:3758096383]	auto[1]	58	1			T259	2		T199	2		T61	2
auto[3758096384:3892314111]	auto[0]	170	1			T1	2		T103	2		T104	4
auto[3758096384:3892314111]	auto[1]	64	1			T32	2		T49	2		T195	2
auto[3892314112:4026531839]	auto[0]	120	1			T1	4		T104	2		T39	2
auto[3892314112:4026531839]	auto[1]	44	1			T185	2		T80	2		T53	2
auto[4026531840:4160749567]	auto[0]	120	1			T103	2		T50	2		T95	2
auto[4026531840:4160749567]	auto[1]	66	1			T32	2		T33	2		T81	2
auto[4160749568:4294967295]	auto[0]	126	1			T32	2		T38	2		T104	2
auto[4160749568:4294967295]	auto[1]	62	1			T32	2		T115	2		T39	2