Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 7 0 7 100.00
Crosses 6 0 6 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr 1 0 1 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=0}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 6 0 6 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 872 1 T1 14 T32 7 T39 11


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 467 1 T1 10 T32 5 T39 5
auto[1] 405 1 T1 4 T32 2 T39 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 339 1 T1 7 T32 5 T39 3
auto[1] 533 1 T1 7 T32 2 T39 8


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 512 1 T1 9 T32 5 T39 6
auto[1] 360 1 T1 5 T32 2 T39 5


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   MISSING   
TOTAL 6 0 6 100.00
Automatically Generated Cross Bins 6 0 6 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intr   cp_intr_test   cp_intr_en   cp_intr_state   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_values[0] auto[0] auto[0] auto[0] 187 1 T1 4 T32 4 T39 1
all_values[0] auto[0] auto[0] auto[1] 86 1 T1 1 T39 1 T88 2
all_values[0] auto[0] auto[1] auto[0] 152 1 T1 3 T32 1 T39 2
all_values[0] auto[0] auto[1] auto[1] 87 1 T1 1 T39 2 T88 2
all_values[0] auto[1] auto[0] auto[1] 194 1 T1 5 T32 1 T39 3
all_values[0] auto[1] auto[1] auto[1] 166 1 T32 1 T39 2 T88 3


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal