Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.86 99.10 97.95 98.68 100.00 99.11 98.41 91.76


Total test records in report: 1067
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T1006 /workspace/coverage/default/19.keymgr_sideload_kmac.999837991 Mar 02 12:41:06 PM PST 24 Mar 02 12:41:11 PM PST 24 1137348227 ps
T1007 /workspace/coverage/default/23.keymgr_sideload_otbn.737507303 Mar 02 12:41:35 PM PST 24 Mar 02 12:41:40 PM PST 24 291889233 ps
T1008 /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3557016252 Mar 02 12:39:44 PM PST 24 Mar 02 12:39:50 PM PST 24 251858996 ps
T1009 /workspace/coverage/default/41.keymgr_custom_cm.4021980023 Mar 02 12:42:53 PM PST 24 Mar 02 12:42:58 PM PST 24 143525883 ps
T1010 /workspace/coverage/default/4.keymgr_sw_invalid_input.3015890501 Mar 02 12:39:59 PM PST 24 Mar 02 12:40:08 PM PST 24 403878522 ps
T1011 /workspace/coverage/default/44.keymgr_sideload_kmac.3281050883 Mar 02 12:42:49 PM PST 24 Mar 02 12:42:53 PM PST 24 233182374 ps
T1012 /workspace/coverage/default/29.keymgr_sideload_otbn.624511174 Mar 02 12:41:55 PM PST 24 Mar 02 12:42:09 PM PST 24 2222173470 ps
T1013 /workspace/coverage/default/45.keymgr_alert_test.2299850974 Mar 02 12:42:55 PM PST 24 Mar 02 12:42:56 PM PST 24 28790608 ps
T1014 /workspace/coverage/default/44.keymgr_smoke.2974080015 Mar 02 12:42:47 PM PST 24 Mar 02 12:42:54 PM PST 24 182522605 ps
T1015 /workspace/coverage/default/44.keymgr_sideload_aes.3749009432 Mar 02 12:42:51 PM PST 24 Mar 02 12:42:53 PM PST 24 67455194 ps
T1016 /workspace/coverage/default/0.keymgr_sideload_aes.2017514787 Mar 02 12:39:17 PM PST 24 Mar 02 12:39:20 PM PST 24 54155281 ps
T1017 /workspace/coverage/default/7.keymgr_sideload_otbn.3872996986 Mar 02 12:40:09 PM PST 24 Mar 02 12:40:14 PM PST 24 413660688 ps
T1018 /workspace/coverage/default/14.keymgr_alert_test.1601690437 Mar 02 12:40:56 PM PST 24 Mar 02 12:40:57 PM PST 24 52061250 ps
T1019 /workspace/coverage/default/20.keymgr_sw_invalid_input.1919798171 Mar 02 12:41:27 PM PST 24 Mar 02 12:41:33 PM PST 24 242633490 ps
T1020 /workspace/coverage/default/14.keymgr_sideload.870768831 Mar 02 12:40:55 PM PST 24 Mar 02 12:41:01 PM PST 24 1476910550 ps
T1021 /workspace/coverage/default/10.keymgr_cfg_regwen.2801662752 Mar 02 12:40:27 PM PST 24 Mar 02 12:40:32 PM PST 24 146245318 ps
T1022 /workspace/coverage/default/4.keymgr_sideload.2980103185 Mar 02 12:39:57 PM PST 24 Mar 02 12:40:06 PM PST 24 253249725 ps
T329 /workspace/coverage/default/4.keymgr_kmac_rsp_err.898233789 Mar 02 12:39:56 PM PST 24 Mar 02 12:40:11 PM PST 24 2795483813 ps
T1023 /workspace/coverage/default/4.keymgr_stress_all.3428722671 Mar 02 12:39:57 PM PST 24 Mar 02 12:42:02 PM PST 24 5798622651 ps
T1024 /workspace/coverage/default/41.keymgr_sync_async_fault_cross.4131479852 Mar 02 12:42:49 PM PST 24 Mar 02 12:42:52 PM PST 24 71554995 ps
T1025 /workspace/coverage/default/18.keymgr_sideload_kmac.1693171982 Mar 02 12:41:07 PM PST 24 Mar 02 12:41:12 PM PST 24 115265430 ps
T146 /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2448809658 Mar 02 12:42:22 PM PST 24 Mar 02 12:42:25 PM PST 24 60879813 ps
T1026 /workspace/coverage/default/12.keymgr_sideload.705633196 Mar 02 12:40:45 PM PST 24 Mar 02 12:40:59 PM PST 24 1148204687 ps
T1027 /workspace/coverage/default/27.keymgr_sw_invalid_input.772356470 Mar 02 12:41:47 PM PST 24 Mar 02 12:41:58 PM PST 24 259123408 ps
T1028 /workspace/coverage/default/47.keymgr_alert_test.2970595210 Mar 02 12:43:04 PM PST 24 Mar 02 12:43:05 PM PST 24 30750266 ps
T1029 /workspace/coverage/default/35.keymgr_alert_test.399973171 Mar 02 12:42:21 PM PST 24 Mar 02 12:42:22 PM PST 24 25308649 ps
T1030 /workspace/coverage/default/22.keymgr_sw_invalid_input.2966582918 Mar 02 12:41:29 PM PST 24 Mar 02 12:41:35 PM PST 24 1022196357 ps
T1031 /workspace/coverage/default/29.keymgr_kmac_rsp_err.3879054946 Mar 02 12:41:59 PM PST 24 Mar 02 12:42:03 PM PST 24 85066552 ps
T1032 /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3234630331 Mar 02 12:42:28 PM PST 24 Mar 02 12:42:30 PM PST 24 179250215 ps
T1033 /workspace/coverage/default/21.keymgr_lc_disable.3558649882 Mar 02 12:41:19 PM PST 24 Mar 02 12:41:22 PM PST 24 493657222 ps
T1034 /workspace/coverage/default/14.keymgr_sideload_kmac.2310706449 Mar 02 12:40:56 PM PST 24 Mar 02 12:40:59 PM PST 24 200325645 ps
T1035 /workspace/coverage/default/41.keymgr_direct_to_disabled.844089703 Mar 02 12:42:53 PM PST 24 Mar 02 12:42:57 PM PST 24 63046129 ps
T1036 /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1742055378 Mar 02 12:41:48 PM PST 24 Mar 02 12:41:51 PM PST 24 267077194 ps
T1037 /workspace/coverage/default/43.keymgr_smoke.900981270 Mar 02 12:42:53 PM PST 24 Mar 02 12:42:55 PM PST 24 247353769 ps
T1038 /workspace/coverage/default/27.keymgr_sideload_protect.2673358118 Mar 02 12:41:47 PM PST 24 Mar 02 12:41:52 PM PST 24 243225136 ps
T1039 /workspace/coverage/default/26.keymgr_kmac_rsp_err.875828532 Mar 02 12:41:46 PM PST 24 Mar 02 12:42:04 PM PST 24 683225182 ps
T1040 /workspace/coverage/default/42.keymgr_sideload_kmac.286421012 Mar 02 12:42:52 PM PST 24 Mar 02 12:43:24 PM PST 24 1768357120 ps
T1041 /workspace/coverage/default/21.keymgr_sideload.3507146006 Mar 02 12:41:22 PM PST 24 Mar 02 12:41:32 PM PST 24 522529333 ps
T1042 /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3542889628 Mar 02 12:43:07 PM PST 24 Mar 02 12:43:11 PM PST 24 191891814 ps
T207 /workspace/coverage/default/42.keymgr_lc_disable.723268114 Mar 02 12:42:47 PM PST 24 Mar 02 12:43:14 PM PST 24 1000517157 ps
T1043 /workspace/coverage/default/16.keymgr_sw_invalid_input.453991351 Mar 02 12:41:09 PM PST 24 Mar 02 12:41:25 PM PST 24 496680908 ps
T1044 /workspace/coverage/default/47.keymgr_sideload_protect.3788135299 Mar 02 12:43:00 PM PST 24 Mar 02 12:43:37 PM PST 24 3952148022 ps
T348 /workspace/coverage/default/33.keymgr_kmac_rsp_err.920245202 Mar 02 12:42:11 PM PST 24 Mar 02 12:42:20 PM PST 24 898818803 ps
T1045 /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.801859455 Mar 02 12:41:46 PM PST 24 Mar 02 12:41:54 PM PST 24 147932968 ps
T1046 /workspace/coverage/default/27.keymgr_sideload_aes.1832777867 Mar 02 12:41:46 PM PST 24 Mar 02 12:41:50 PM PST 24 32565263 ps
T1047 /workspace/coverage/default/22.keymgr_random.2106263894 Mar 02 12:41:23 PM PST 24 Mar 02 12:41:28 PM PST 24 273278566 ps
T1048 /workspace/coverage/default/37.keymgr_sw_invalid_input.2875475558 Mar 02 12:42:28 PM PST 24 Mar 02 12:42:42 PM PST 24 639273212 ps
T1049 /workspace/coverage/default/32.keymgr_sideload_aes.3067736022 Mar 02 12:42:02 PM PST 24 Mar 02 12:42:20 PM PST 24 668769376 ps
T1050 /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3246624198 Mar 02 12:40:57 PM PST 24 Mar 02 12:41:04 PM PST 24 238644832 ps
T1051 /workspace/coverage/default/23.keymgr_sw_invalid_input.386372302 Mar 02 12:41:32 PM PST 24 Mar 02 12:41:39 PM PST 24 654012275 ps
T1052 /workspace/coverage/default/13.keymgr_random.2232091247 Mar 02 12:40:47 PM PST 24 Mar 02 12:40:56 PM PST 24 265008819 ps
T1053 /workspace/coverage/default/48.keymgr_custom_cm.3246366339 Mar 02 12:43:04 PM PST 24 Mar 02 12:43:12 PM PST 24 592572168 ps
T1054 /workspace/coverage/default/1.keymgr_random.741991372 Mar 02 12:39:32 PM PST 24 Mar 02 12:40:00 PM PST 24 8502606619 ps
T1055 /workspace/coverage/default/9.keymgr_sw_invalid_input.4050672680 Mar 02 12:40:15 PM PST 24 Mar 02 12:40:20 PM PST 24 111769090 ps
T1056 /workspace/coverage/default/4.keymgr_sideload_protect.4140687927 Mar 02 12:39:55 PM PST 24 Mar 02 12:40:03 PM PST 24 252918197 ps
T301 /workspace/coverage/default/25.keymgr_kmac_rsp_err.666270940 Mar 02 12:41:44 PM PST 24 Mar 02 12:41:49 PM PST 24 62138279 ps
T1057 /workspace/coverage/default/1.keymgr_alert_test.2705370390 Mar 02 12:39:48 PM PST 24 Mar 02 12:39:49 PM PST 24 46942546 ps
T1058 /workspace/coverage/default/38.keymgr_lc_disable.1977234305 Mar 02 12:42:32 PM PST 24 Mar 02 12:42:35 PM PST 24 231640636 ps
T1059 /workspace/coverage/default/2.keymgr_sideload.1000064004 Mar 02 12:39:43 PM PST 24 Mar 02 12:39:46 PM PST 24 148234465 ps
T1060 /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1944341027 Mar 02 12:41:24 PM PST 24 Mar 02 12:41:27 PM PST 24 66667525 ps
T1061 /workspace/coverage/default/15.keymgr_cfg_regwen.1600794358 Mar 02 12:40:59 PM PST 24 Mar 02 12:41:53 PM PST 24 4508557120 ps
T1062 /workspace/coverage/default/14.keymgr_sideload_otbn.438256514 Mar 02 12:41:00 PM PST 24 Mar 02 12:41:18 PM PST 24 747447430 ps
T1063 /workspace/coverage/default/32.keymgr_random.365237258 Mar 02 12:42:04 PM PST 24 Mar 02 12:42:07 PM PST 24 95782330 ps
T1064 /workspace/coverage/default/3.keymgr_sideload_protect.3127600070 Mar 02 12:39:57 PM PST 24 Mar 02 12:40:00 PM PST 24 67625795 ps
T1065 /workspace/coverage/default/2.keymgr_sw_invalid_input.4047827094 Mar 02 12:39:45 PM PST 24 Mar 02 12:39:51 PM PST 24 154041306 ps
T1066 /workspace/coverage/default/20.keymgr_cfg_regwen.2142825060 Mar 02 12:41:19 PM PST 24 Mar 02 12:41:24 PM PST 24 324620543 ps
T1067 /workspace/coverage/default/33.keymgr_cfg_regwen.3199123342 Mar 02 12:42:08 PM PST 24 Mar 02 12:43:05 PM PST 24 4434327450 ps

Test location /workspace/coverage/default/2.keymgr_stress_all.2394648502
Short name T1
Test name
Test status
Simulation time 477167579 ps
CPU time 12.33 seconds
Started Mar 02 12:39:45 PM PST 24
Finished Mar 02 12:39:57 PM PST 24
Peak memory 214424 kb
Host smart-779931da-ce6c-42f2-ac74-e6484bd0566d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394648502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2394648502
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.221915560
Short name T39
Test name
Test status
Simulation time 989085635 ps
CPU time 36.59 seconds
Started Mar 02 12:42:11 PM PST 24
Finished Mar 02 12:42:47 PM PST 24
Peak memory 215628 kb
Host smart-d49e4ea6-4212-4723-8907-b780b9964e11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221915560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.221915560
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.429351549
Short name T3
Test name
Test status
Simulation time 193977993 ps
CPU time 3.15 seconds
Started Mar 02 12:42:51 PM PST 24
Finished Mar 02 12:42:55 PM PST 24
Peak memory 216336 kb
Host smart-1a5e4f97-13f8-4cc6-af21-1ecaa873e1d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429351549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.429351549
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.287160063
Short name T4
Test name
Test status
Simulation time 853811634 ps
CPU time 7.74 seconds
Started Mar 02 12:39:23 PM PST 24
Finished Mar 02 12:39:30 PM PST 24
Peak memory 230308 kb
Host smart-4fe1cab6-fd56-4509-95bd-835ac3c68a0c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287160063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.287160063
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.4140770255
Short name T42
Test name
Test status
Simulation time 512404572 ps
CPU time 7.56 seconds
Started Mar 02 12:42:14 PM PST 24
Finished Mar 02 12:42:21 PM PST 24
Peak memory 223144 kb
Host smart-b224368c-9375-4411-99bd-b3ff4504a89e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140770255 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.4140770255
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3967289977
Short name T187
Test name
Test status
Simulation time 1485277416 ps
CPU time 52.14 seconds
Started Mar 02 12:41:50 PM PST 24
Finished Mar 02 12:42:42 PM PST 24
Peak memory 216956 kb
Host smart-2014ea7d-17aa-4154-ad6f-a22fd26a2f02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967289977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3967289977
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.501358428
Short name T53
Test name
Test status
Simulation time 5488177856 ps
CPU time 67.96 seconds
Started Mar 02 12:40:25 PM PST 24
Finished Mar 02 12:41:33 PM PST 24
Peak memory 222268 kb
Host smart-28d7dca2-2a81-453a-a22f-2e3f336f8883
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501358428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.501358428
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2004991101
Short name T131
Test name
Test status
Simulation time 1247845320 ps
CPU time 17.13 seconds
Started Mar 02 12:40:43 PM PST 24
Finished Mar 02 12:41:00 PM PST 24
Peak memory 214076 kb
Host smart-4011b8e3-15bb-47f0-b516-d3560cf833b0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2004991101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2004991101
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3347319681
Short name T99
Test name
Test status
Simulation time 2404913572 ps
CPU time 10.66 seconds
Started Mar 02 01:19:14 PM PST 24
Finished Mar 02 01:19:25 PM PST 24
Peak memory 220124 kb
Host smart-d2debec4-e163-419b-b552-8403a0a6d75f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347319681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3347319681
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.793189810
Short name T32
Test name
Test status
Simulation time 2831128685 ps
CPU time 63.25 seconds
Started Mar 02 12:41:01 PM PST 24
Finished Mar 02 12:42:04 PM PST 24
Peak memory 221584 kb
Host smart-964ab2b9-7a56-45ad-818c-a14cd16dc1c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793189810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.793189810
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.156757249
Short name T891
Test name
Test status
Simulation time 276234968 ps
CPU time 5.29 seconds
Started Mar 02 12:42:33 PM PST 24
Finished Mar 02 12:42:39 PM PST 24
Peak memory 210168 kb
Host smart-8f34032f-ebc6-43b9-b6e4-9c5a97513357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156757249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.156757249
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2034893973
Short name T34
Test name
Test status
Simulation time 585875073 ps
CPU time 6.61 seconds
Started Mar 02 12:42:30 PM PST 24
Finished Mar 02 12:42:37 PM PST 24
Peak memory 222520 kb
Host smart-0740e561-6079-4bc3-8db7-21f12f95f10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034893973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2034893973
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2633385734
Short name T22
Test name
Test status
Simulation time 240898279 ps
CPU time 5.89 seconds
Started Mar 02 12:40:25 PM PST 24
Finished Mar 02 12:40:31 PM PST 24
Peak memory 222452 kb
Host smart-3733ccc4-3427-4e8f-807d-011d7b50f577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633385734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2633385734
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.232443881
Short name T232
Test name
Test status
Simulation time 1491921635 ps
CPU time 80.24 seconds
Started Mar 02 12:39:45 PM PST 24
Finished Mar 02 12:41:06 PM PST 24
Peak memory 215496 kb
Host smart-67b089ca-2766-42f5-a255-09057c0c1a8b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=232443881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.232443881
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3887307804
Short name T178
Test name
Test status
Simulation time 13088294944 ps
CPU time 38.02 seconds
Started Mar 02 12:43:03 PM PST 24
Finished Mar 02 12:43:41 PM PST 24
Peak memory 215520 kb
Host smart-ca22bd63-f483-4bf4-8f4f-511c204ba550
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887307804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3887307804
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1840252407
Short name T292
Test name
Test status
Simulation time 4807485023 ps
CPU time 52.74 seconds
Started Mar 02 12:42:51 PM PST 24
Finished Mar 02 12:43:44 PM PST 24
Peak memory 214336 kb
Host smart-c3daa47a-664b-4ff2-80c9-26c49cac5dce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1840252407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1840252407
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.519821718
Short name T121
Test name
Test status
Simulation time 470430020 ps
CPU time 3.32 seconds
Started Mar 02 01:19:28 PM PST 24
Finished Mar 02 01:19:34 PM PST 24
Peak memory 213692 kb
Host smart-6f88908c-c592-4cb5-b0c2-4f7e426279e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519821718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.519821718
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.634768011
Short name T317
Test name
Test status
Simulation time 419883754 ps
CPU time 22.04 seconds
Started Mar 02 12:42:16 PM PST 24
Finished Mar 02 12:42:38 PM PST 24
Peak memory 214924 kb
Host smart-e823db2e-ec17-4a59-9ae6-50a1dc92821b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634768011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.634768011
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3250823039
Short name T49
Test name
Test status
Simulation time 2151830101 ps
CPU time 64.49 seconds
Started Mar 02 12:40:45 PM PST 24
Finished Mar 02 12:41:50 PM PST 24
Peak memory 222424 kb
Host smart-32876949-8230-4e0d-8a98-1d896358d57c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250823039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3250823039
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.4068568763
Short name T218
Test name
Test status
Simulation time 926824059 ps
CPU time 12.2 seconds
Started Mar 02 12:42:59 PM PST 24
Finished Mar 02 12:43:11 PM PST 24
Peak memory 215420 kb
Host smart-ba97e059-69cd-4293-b953-504515f824f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4068568763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.4068568763
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3850819860
Short name T107
Test name
Test status
Simulation time 1363168331 ps
CPU time 6.14 seconds
Started Mar 02 01:19:09 PM PST 24
Finished Mar 02 01:19:15 PM PST 24
Peak memory 213836 kb
Host smart-d1f24c4e-27a7-4a1b-8753-2988d1804f32
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850819860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3850819860
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1774712678
Short name T35
Test name
Test status
Simulation time 62710969 ps
CPU time 3.55 seconds
Started Mar 02 12:39:58 PM PST 24
Finished Mar 02 12:40:02 PM PST 24
Peak memory 221212 kb
Host smart-b21db7df-b78d-46c0-b05d-c32c7c6c97f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774712678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1774712678
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2609545732
Short name T19
Test name
Test status
Simulation time 176550964 ps
CPU time 3.06 seconds
Started Mar 02 12:40:45 PM PST 24
Finished Mar 02 12:40:48 PM PST 24
Peak memory 219380 kb
Host smart-8ed184be-1791-48ca-9ea1-079c99fbdc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609545732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2609545732
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3309245250
Short name T402
Test name
Test status
Simulation time 91011037 ps
CPU time 4.96 seconds
Started Mar 02 12:41:48 PM PST 24
Finished Mar 02 12:41:54 PM PST 24
Peak memory 215344 kb
Host smart-f58794ef-30d1-4656-85d9-1ac194d27654
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3309245250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3309245250
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.949685529
Short name T40
Test name
Test status
Simulation time 1546234138 ps
CPU time 55.75 seconds
Started Mar 02 12:42:21 PM PST 24
Finished Mar 02 12:43:17 PM PST 24
Peak memory 215804 kb
Host smart-83a08432-0283-4af5-b37c-2f3fab73031d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949685529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.949685529
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3545668132
Short name T152
Test name
Test status
Simulation time 4336766323 ps
CPU time 41.02 seconds
Started Mar 02 12:40:29 PM PST 24
Finished Mar 02 12:41:10 PM PST 24
Peak memory 222740 kb
Host smart-6e914566-61a8-4d75-b979-c6beb1f0009b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545668132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3545668132
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3252061421
Short name T120
Test name
Test status
Simulation time 4243652153 ps
CPU time 39.58 seconds
Started Mar 02 01:19:21 PM PST 24
Finished Mar 02 01:20:03 PM PST 24
Peak memory 213656 kb
Host smart-c05e463b-a5b2-46d8-bf4a-bfcd52a7907c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252061421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3252061421
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3527502508
Short name T304
Test name
Test status
Simulation time 2546221534 ps
CPU time 7.55 seconds
Started Mar 02 12:41:54 PM PST 24
Finished Mar 02 12:42:02 PM PST 24
Peak memory 214620 kb
Host smart-2875d4d1-10a1-448b-ab7f-f6ab721d8d6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3527502508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3527502508
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1711023661
Short name T24
Test name
Test status
Simulation time 23677857 ps
CPU time 1.65 seconds
Started Mar 02 12:39:35 PM PST 24
Finished Mar 02 12:39:37 PM PST 24
Peak memory 214396 kb
Host smart-0f35454b-eac8-4a51-b722-40d7ba586082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711023661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1711023661
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1057070261
Short name T222
Test name
Test status
Simulation time 5562915636 ps
CPU time 38.5 seconds
Started Mar 02 12:42:00 PM PST 24
Finished Mar 02 12:42:39 PM PST 24
Peak memory 215800 kb
Host smart-c7ce7211-3a74-42a5-9f88-4f81092a3a40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057070261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1057070261
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2852064472
Short name T43
Test name
Test status
Simulation time 140958049 ps
CPU time 6.39 seconds
Started Mar 02 12:42:47 PM PST 24
Finished Mar 02 12:42:56 PM PST 24
Peak memory 214200 kb
Host smart-4358855a-a0a5-4e25-a55b-745324756a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852064472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2852064472
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.920551783
Short name T87
Test name
Test status
Simulation time 27383964 ps
CPU time 0.78 seconds
Started Mar 02 12:39:21 PM PST 24
Finished Mar 02 12:39:22 PM PST 24
Peak memory 205784 kb
Host smart-d5729a9b-6890-4d0d-a2ea-9e1a8116b870
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920551783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.920551783
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.4092638733
Short name T311
Test name
Test status
Simulation time 5409375863 ps
CPU time 47.42 seconds
Started Mar 02 12:39:21 PM PST 24
Finished Mar 02 12:40:10 PM PST 24
Peak memory 222332 kb
Host smart-1bda4a71-df4d-4627-bf43-3b74b77b829f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092638733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.4092638733
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3166148432
Short name T226
Test name
Test status
Simulation time 108623042 ps
CPU time 4.89 seconds
Started Mar 02 12:42:09 PM PST 24
Finished Mar 02 12:42:14 PM PST 24
Peak memory 214180 kb
Host smart-c60d2e8d-8293-45d2-9298-1685530d6313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166148432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3166148432
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3599998798
Short name T47
Test name
Test status
Simulation time 189766689 ps
CPU time 5.08 seconds
Started Mar 02 12:40:54 PM PST 24
Finished Mar 02 12:40:59 PM PST 24
Peak memory 218336 kb
Host smart-46dce349-45a3-4ea1-b1a6-94ea67feb330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599998798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3599998798
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2216937567
Short name T221
Test name
Test status
Simulation time 5478502160 ps
CPU time 42.5 seconds
Started Mar 02 12:41:04 PM PST 24
Finished Mar 02 12:41:47 PM PST 24
Peak memory 222464 kb
Host smart-1746679a-d956-43a6-be9b-07b2ac50db10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216937567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2216937567
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2609100255
Short name T287
Test name
Test status
Simulation time 472773484 ps
CPU time 4.62 seconds
Started Mar 02 12:41:09 PM PST 24
Finished Mar 02 12:41:14 PM PST 24
Peak memory 214268 kb
Host smart-67a1fd58-e3af-4979-b03c-ec1d19c5dec7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2609100255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2609100255
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1972527635
Short name T258
Test name
Test status
Simulation time 1068831374 ps
CPU time 6.23 seconds
Started Mar 02 12:39:45 PM PST 24
Finished Mar 02 12:39:52 PM PST 24
Peak memory 214332 kb
Host smart-058b57da-95e0-4e19-acef-d8396be481ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1972527635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1972527635
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3427287773
Short name T240
Test name
Test status
Simulation time 9168177031 ps
CPU time 102.84 seconds
Started Mar 02 12:42:35 PM PST 24
Finished Mar 02 12:44:18 PM PST 24
Peak memory 220368 kb
Host smart-757004d9-095e-4ec8-8f17-c455e7a92427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427287773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3427287773
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.741742891
Short name T139
Test name
Test status
Simulation time 402680305 ps
CPU time 9.78 seconds
Started Mar 02 01:19:14 PM PST 24
Finished Mar 02 01:19:24 PM PST 24
Peak memory 219396 kb
Host smart-64e2a3b3-7b77-4800-99f5-c6664a6935eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741742891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.741742891
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.828963456
Short name T142
Test name
Test status
Simulation time 121200252 ps
CPU time 5.36 seconds
Started Mar 02 01:19:23 PM PST 24
Finished Mar 02 01:19:34 PM PST 24
Peak memory 213620 kb
Host smart-a5b982f7-7bbe-4930-a43c-3c3eec1c2e4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828963456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.828963456
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2573827027
Short name T155
Test name
Test status
Simulation time 333942785 ps
CPU time 5.58 seconds
Started Mar 02 12:42:15 PM PST 24
Finished Mar 02 12:42:20 PM PST 24
Peak memory 217772 kb
Host smart-ba91ff9c-37eb-4d97-9ea3-70f882d26d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573827027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2573827027
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2457180363
Short name T345
Test name
Test status
Simulation time 1946497403 ps
CPU time 13.06 seconds
Started Mar 02 12:41:45 PM PST 24
Finished Mar 02 12:42:00 PM PST 24
Peak memory 214332 kb
Host smart-19a77113-243d-4d57-8130-ee846ec0faca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457180363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2457180363
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2031824781
Short name T194
Test name
Test status
Simulation time 481040057 ps
CPU time 13.81 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:16 PM PST 24
Peak memory 220984 kb
Host smart-51698062-24d8-43ba-8563-f2627a4b2e05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031824781 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2031824781
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3531035886
Short name T29
Test name
Test status
Simulation time 91583214 ps
CPU time 4.26 seconds
Started Mar 02 12:41:09 PM PST 24
Finished Mar 02 12:41:14 PM PST 24
Peak memory 209828 kb
Host smart-583085d4-b534-49f4-b965-2f767a5f9554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531035886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3531035886
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2838587432
Short name T135
Test name
Test status
Simulation time 264937064 ps
CPU time 9.74 seconds
Started Mar 02 01:19:17 PM PST 24
Finished Mar 02 01:19:27 PM PST 24
Peak memory 213608 kb
Host smart-ebaff547-3d4d-4f6b-b033-2ba4b89604e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838587432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2838587432
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1623114439
Short name T157
Test name
Test status
Simulation time 118383563 ps
CPU time 3.55 seconds
Started Mar 02 12:40:59 PM PST 24
Finished Mar 02 12:41:02 PM PST 24
Peak memory 222664 kb
Host smart-67f0e073-d25e-4c01-90db-d03c6fcaa4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623114439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1623114439
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3904014362
Short name T154
Test name
Test status
Simulation time 286635348 ps
CPU time 7.35 seconds
Started Mar 02 12:41:05 PM PST 24
Finished Mar 02 12:41:13 PM PST 24
Peak memory 222576 kb
Host smart-d18c64c9-e868-48a1-a3e2-662d3d9acd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904014362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3904014362
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3383355019
Short name T216
Test name
Test status
Simulation time 849300764 ps
CPU time 12.36 seconds
Started Mar 02 12:40:44 PM PST 24
Finished Mar 02 12:40:56 PM PST 24
Peak memory 214308 kb
Host smart-bccc381a-cafb-44a8-863c-e068d0881f4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3383355019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3383355019
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3616990020
Short name T270
Test name
Test status
Simulation time 10981166667 ps
CPU time 75.78 seconds
Started Mar 02 12:40:56 PM PST 24
Finished Mar 02 12:42:12 PM PST 24
Peak memory 225072 kb
Host smart-4c61c061-a064-44e9-b5d7-4aa87d685910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616990020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3616990020
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1309588544
Short name T17
Test name
Test status
Simulation time 118555108 ps
CPU time 3.94 seconds
Started Mar 02 12:41:03 PM PST 24
Finished Mar 02 12:41:07 PM PST 24
Peak memory 208444 kb
Host smart-85ea9bc6-5cc0-4277-be99-967a0ddc8ba1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309588544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1309588544
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.323689280
Short name T236
Test name
Test status
Simulation time 5589526554 ps
CPU time 50.97 seconds
Started Mar 02 12:41:06 PM PST 24
Finished Mar 02 12:41:57 PM PST 24
Peak memory 216356 kb
Host smart-fed33a27-e02b-413d-9cd4-807eeb65b49d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323689280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.323689280
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2773547461
Short name T285
Test name
Test status
Simulation time 2795541996 ps
CPU time 13.45 seconds
Started Mar 02 12:40:59 PM PST 24
Finished Mar 02 12:41:13 PM PST 24
Peak memory 222372 kb
Host smart-5d20a116-738b-48ff-b43a-99cf6bf5ffbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773547461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2773547461
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3440072474
Short name T137
Test name
Test status
Simulation time 5986303796 ps
CPU time 40.99 seconds
Started Mar 02 01:19:09 PM PST 24
Finished Mar 02 01:19:50 PM PST 24
Peak memory 213652 kb
Host smart-29a52c1e-8dd3-4796-b80e-9aac40d9d686
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440072474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3440072474
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2446742800
Short name T331
Test name
Test status
Simulation time 393371474 ps
CPU time 5.59 seconds
Started Mar 02 12:41:02 PM PST 24
Finished Mar 02 12:41:08 PM PST 24
Peak memory 214236 kb
Host smart-cd5886c8-71be-4822-9e3e-22c120771af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446742800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2446742800
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2142825060
Short name T1066
Test name
Test status
Simulation time 324620543 ps
CPU time 5.15 seconds
Started Mar 02 12:41:19 PM PST 24
Finished Mar 02 12:41:24 PM PST 24
Peak memory 214248 kb
Host smart-dc329272-f0e1-4e21-bd92-f99a0e2613c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2142825060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2142825060
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3119092794
Short name T79
Test name
Test status
Simulation time 127176955 ps
CPU time 5.64 seconds
Started Mar 02 12:41:55 PM PST 24
Finished Mar 02 12:42:01 PM PST 24
Peak memory 214240 kb
Host smart-2a169c42-a6a7-4863-add6-0d4d285f8c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119092794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3119092794
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.680505441
Short name T86
Test name
Test status
Simulation time 61564797 ps
CPU time 3.31 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:06 PM PST 24
Peak memory 214384 kb
Host smart-5575d816-3dd8-43cb-bfb8-79c934312d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680505441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.680505441
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.4037122336
Short name T295
Test name
Test status
Simulation time 55279199 ps
CPU time 4.09 seconds
Started Mar 02 12:43:08 PM PST 24
Finished Mar 02 12:43:12 PM PST 24
Peak memory 214972 kb
Host smart-312fbfd2-204c-48bb-9520-feede5729afb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4037122336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.4037122336
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.401051372
Short name T51
Test name
Test status
Simulation time 135160294 ps
CPU time 2.81 seconds
Started Mar 02 12:40:08 PM PST 24
Finished Mar 02 12:40:11 PM PST 24
Peak memory 209940 kb
Host smart-a00b96a9-8c0a-4f64-b590-4044aa402f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401051372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.401051372
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1430111005
Short name T159
Test name
Test status
Simulation time 279083724 ps
CPU time 3.16 seconds
Started Mar 02 12:42:50 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 217444 kb
Host smart-60ed7a82-8674-4ae5-bcb5-3a4115e3fb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430111005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1430111005
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3099682492
Short name T156
Test name
Test status
Simulation time 49086768 ps
CPU time 2.51 seconds
Started Mar 02 12:40:15 PM PST 24
Finished Mar 02 12:40:18 PM PST 24
Peak memory 216520 kb
Host smart-7fb712b9-6d60-4e6b-8d76-ae15ce794bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099682492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3099682492
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1785317675
Short name T185
Test name
Test status
Simulation time 111967603 ps
CPU time 5.65 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:40:51 PM PST 24
Peak memory 210612 kb
Host smart-f1db1745-2348-47eb-96b5-579626038481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785317675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1785317675
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3187610732
Short name T268
Test name
Test status
Simulation time 262423314 ps
CPU time 7.42 seconds
Started Mar 02 12:41:07 PM PST 24
Finished Mar 02 12:41:15 PM PST 24
Peak memory 222460 kb
Host smart-2ca7f4ea-1296-4ac0-bddf-c07d91f884e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187610732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3187610732
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2649884594
Short name T340
Test name
Test status
Simulation time 15913981168 ps
CPU time 103.75 seconds
Started Mar 02 12:41:10 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 215900 kb
Host smart-7913fccd-9d0a-4979-9c98-cdf233f5bee8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649884594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2649884594
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2467391727
Short name T392
Test name
Test status
Simulation time 125765141 ps
CPU time 1.48 seconds
Started Mar 02 12:39:46 PM PST 24
Finished Mar 02 12:39:48 PM PST 24
Peak memory 209928 kb
Host smart-76674a60-8800-4c48-a862-2c8e1d39b181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467391727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2467391727
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.554585565
Short name T213
Test name
Test status
Simulation time 7727577502 ps
CPU time 58.32 seconds
Started Mar 02 12:41:16 PM PST 24
Finished Mar 02 12:42:15 PM PST 24
Peak memory 222504 kb
Host smart-1c0b3209-1d6d-442f-8e77-cfed5cb2a7c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554585565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.554585565
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3199123342
Short name T1067
Test name
Test status
Simulation time 4434327450 ps
CPU time 56.56 seconds
Started Mar 02 12:42:08 PM PST 24
Finished Mar 02 12:43:05 PM PST 24
Peak memory 216416 kb
Host smart-d1403cd4-999b-49d2-87b5-efcc87f88207
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3199123342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3199123342
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.41989338
Short name T271
Test name
Test status
Simulation time 90715146 ps
CPU time 3.53 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:26 PM PST 24
Peak memory 222468 kb
Host smart-2f9fdafe-d03a-4c7c-ba94-9e81a9f24755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41989338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.41989338
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3604330989
Short name T210
Test name
Test status
Simulation time 499764694 ps
CPU time 14.74 seconds
Started Mar 02 12:42:36 PM PST 24
Finished Mar 02 12:42:51 PM PST 24
Peak memory 216428 kb
Host smart-b7619538-57b1-4c22-944c-a83b8ad7da96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604330989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3604330989
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1920790729
Short name T337
Test name
Test status
Simulation time 2752152339 ps
CPU time 45.06 seconds
Started Mar 02 12:40:07 PM PST 24
Finished Mar 02 12:40:52 PM PST 24
Peak memory 208784 kb
Host smart-1551fb00-553b-4560-9e28-bf58ae5bfeb5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920790729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1920790729
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.398772986
Short name T169
Test name
Test status
Simulation time 103417682 ps
CPU time 2.7 seconds
Started Mar 02 01:18:57 PM PST 24
Finished Mar 02 01:19:00 PM PST 24
Peak memory 215896 kb
Host smart-05fc1d7c-e40d-49b7-bb09-44b53ea79a19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398772986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.398772986
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2225791056
Short name T147
Test name
Test status
Simulation time 155605916 ps
CPU time 6.54 seconds
Started Mar 02 01:19:21 PM PST 24
Finished Mar 02 01:19:28 PM PST 24
Peak memory 209072 kb
Host smart-6ca145fa-93db-4239-bf67-7bd051ca7269
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225791056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2225791056
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.876282384
Short name T148
Test name
Test status
Simulation time 360514766 ps
CPU time 6.98 seconds
Started Mar 02 01:19:09 PM PST 24
Finished Mar 02 01:19:16 PM PST 24
Peak memory 208904 kb
Host smart-4074b0d7-dd1e-476d-9de3-3945be7283d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876282384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
876282384
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2448809658
Short name T146
Test name
Test status
Simulation time 60879813 ps
CPU time 2.77 seconds
Started Mar 02 12:42:22 PM PST 24
Finished Mar 02 12:42:25 PM PST 24
Peak memory 209996 kb
Host smart-d338bbfe-1269-4662-bef9-f06ef02a03d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448809658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2448809658
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3496458993
Short name T158
Test name
Test status
Simulation time 225213507 ps
CPU time 2.23 seconds
Started Mar 02 12:42:14 PM PST 24
Finished Mar 02 12:42:16 PM PST 24
Peak memory 222644 kb
Host smart-1780007f-8d4b-4ff9-9038-15634dd7f3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496458993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3496458993
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.4018493959
Short name T153
Test name
Test status
Simulation time 188243595 ps
CPU time 5.96 seconds
Started Mar 02 12:41:05 PM PST 24
Finished Mar 02 12:41:11 PM PST 24
Peak memory 217528 kb
Host smart-2e0b70c9-c6c1-4733-bad7-88410be2bc4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018493959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.4018493959
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_random.3580937513
Short name T354
Test name
Test status
Simulation time 8872552893 ps
CPU time 61.89 seconds
Started Mar 02 12:39:13 PM PST 24
Finished Mar 02 12:40:15 PM PST 24
Peak memory 220568 kb
Host smart-e87c783d-cdeb-462c-a208-eef5bad47d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580937513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3580937513
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3904494073
Short name T406
Test name
Test status
Simulation time 618550316 ps
CPU time 20.71 seconds
Started Mar 02 12:39:35 PM PST 24
Finished Mar 02 12:39:55 PM PST 24
Peak memory 222396 kb
Host smart-7c8f4363-29dd-48c7-85ca-15266be56005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3904494073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3904494073
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.543883779
Short name T914
Test name
Test status
Simulation time 408278929 ps
CPU time 6.2 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:40:53 PM PST 24
Peak memory 207812 kb
Host smart-49c2e67b-ea7c-490a-85db-3b889cb1b2a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543883779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.543883779
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3621980259
Short name T54
Test name
Test status
Simulation time 1318176791 ps
CPU time 18.32 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:41:04 PM PST 24
Peak memory 220672 kb
Host smart-abeb9435-dff4-4407-b794-7e8e71a69c3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621980259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3621980259
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.344400129
Short name T205
Test name
Test status
Simulation time 1676452514 ps
CPU time 9.22 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:40:55 PM PST 24
Peak memory 222444 kb
Host smart-af6d9b54-3c60-40fe-966c-685e19d02853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344400129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.344400129
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2543139757
Short name T206
Test name
Test status
Simulation time 5378932548 ps
CPU time 53.15 seconds
Started Mar 02 12:40:57 PM PST 24
Finished Mar 02 12:41:50 PM PST 24
Peak memory 222436 kb
Host smart-408d0696-73ba-4715-ab19-5c9556247770
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543139757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2543139757
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3925504041
Short name T288
Test name
Test status
Simulation time 8388169546 ps
CPU time 19.26 seconds
Started Mar 02 12:41:00 PM PST 24
Finished Mar 02 12:41:19 PM PST 24
Peak memory 214364 kb
Host smart-c882ddc3-0826-4591-942c-c83938da15d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925504041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3925504041
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1129098695
Short name T998
Test name
Test status
Simulation time 38487774 ps
CPU time 2.95 seconds
Started Mar 02 12:41:11 PM PST 24
Finished Mar 02 12:41:14 PM PST 24
Peak memory 214260 kb
Host smart-0ee47b5b-4e4b-4599-9d92-3bed721980f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129098695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1129098695
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1376305087
Short name T374
Test name
Test status
Simulation time 356934537 ps
CPU time 7.39 seconds
Started Mar 02 12:39:46 PM PST 24
Finished Mar 02 12:39:54 PM PST 24
Peak memory 209312 kb
Host smart-2847e6a3-d307-4296-9362-d9537cae3f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376305087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1376305087
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1160159580
Short name T342
Test name
Test status
Simulation time 153096930 ps
CPU time 2.3 seconds
Started Mar 02 12:39:51 PM PST 24
Finished Mar 02 12:39:54 PM PST 24
Peak memory 206724 kb
Host smart-4cf7e09c-5644-40ba-9ece-f7ad4c963e91
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160159580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1160159580
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1527039485
Short name T227
Test name
Test status
Simulation time 979702050 ps
CPU time 8.35 seconds
Started Mar 02 12:41:30 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 210396 kb
Host smart-072f1ae0-e3f6-4705-867b-80ea54a785b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527039485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1527039485
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2261205701
Short name T66
Test name
Test status
Simulation time 1668399015 ps
CPU time 38.52 seconds
Started Mar 02 12:41:29 PM PST 24
Finished Mar 02 12:42:08 PM PST 24
Peak memory 221464 kb
Host smart-7146c918-5199-4ce7-87cf-7df88557f854
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261205701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2261205701
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.897618936
Short name T197
Test name
Test status
Simulation time 647693068 ps
CPU time 11.99 seconds
Started Mar 02 12:41:34 PM PST 24
Finished Mar 02 12:41:46 PM PST 24
Peak memory 222644 kb
Host smart-d0d41513-5952-4705-a58a-c1ba12b54081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897618936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.897618936
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1812059831
Short name T366
Test name
Test status
Simulation time 21468928 ps
CPU time 1.6 seconds
Started Mar 02 12:41:54 PM PST 24
Finished Mar 02 12:41:56 PM PST 24
Peak memory 207648 kb
Host smart-484238c4-33eb-4e17-8f01-5997e662f6fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812059831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1812059831
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.349756412
Short name T56
Test name
Test status
Simulation time 26787676414 ps
CPU time 181.51 seconds
Started Mar 02 12:39:57 PM PST 24
Finished Mar 02 12:42:59 PM PST 24
Peak memory 222528 kb
Host smart-73fdfe71-edb6-455b-819c-7a96d963995e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349756412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.349756412
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.90963369
Short name T208
Test name
Test status
Simulation time 2500552147 ps
CPU time 31.03 seconds
Started Mar 02 12:42:02 PM PST 24
Finished Mar 02 12:42:33 PM PST 24
Peak memory 209648 kb
Host smart-1c45a924-081b-4a98-a5d5-086aab72d1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90963369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.90963369
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3278111706
Short name T225
Test name
Test status
Simulation time 152768153 ps
CPU time 3.45 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:06 PM PST 24
Peak memory 209188 kb
Host smart-4a97d848-ab33-4f1a-9a9c-8eaf1ffc7d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278111706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3278111706
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1484491451
Short name T204
Test name
Test status
Simulation time 270897344 ps
CPU time 7.24 seconds
Started Mar 02 12:40:08 PM PST 24
Finished Mar 02 12:40:15 PM PST 24
Peak memory 210436 kb
Host smart-bb064c90-b41d-4cb0-95d3-357674a38500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484491451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1484491451
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.4029346757
Short name T349
Test name
Test status
Simulation time 661499370 ps
CPU time 10.84 seconds
Started Mar 02 12:40:14 PM PST 24
Finished Mar 02 12:40:24 PM PST 24
Peak memory 214192 kb
Host smart-732ef668-1975-44b7-9f49-7ba022b97ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029346757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.4029346757
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2340596221
Short name T303
Test name
Test status
Simulation time 161303657 ps
CPU time 4.78 seconds
Started Mar 02 12:40:16 PM PST 24
Finished Mar 02 12:40:21 PM PST 24
Peak memory 214236 kb
Host smart-03607e99-692e-40bf-b792-c26dd671b366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340596221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2340596221
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3430422816
Short name T503
Test name
Test status
Simulation time 360449225 ps
CPU time 14.18 seconds
Started Mar 02 01:19:00 PM PST 24
Finished Mar 02 01:19:14 PM PST 24
Peak memory 205268 kb
Host smart-cc5ed74b-c4a0-44c8-9f7b-7a39d4078abc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430422816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
430422816
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2581388211
Short name T160
Test name
Test status
Simulation time 22663528 ps
CPU time 0.96 seconds
Started Mar 02 01:19:02 PM PST 24
Finished Mar 02 01:19:03 PM PST 24
Peak memory 205136 kb
Host smart-cda120c3-4da5-4788-b81d-492c53e670c9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581388211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
581388211
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3228912775
Short name T435
Test name
Test status
Simulation time 21485512 ps
CPU time 1.03 seconds
Started Mar 02 01:18:59 PM PST 24
Finished Mar 02 01:19:00 PM PST 24
Peak memory 205244 kb
Host smart-73fb4356-aa53-4baa-a8bc-c03e4f854c71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228912775 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3228912775
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2544424887
Short name T524
Test name
Test status
Simulation time 424484938 ps
CPU time 1.09 seconds
Started Mar 02 01:19:00 PM PST 24
Finished Mar 02 01:19:01 PM PST 24
Peak memory 205372 kb
Host smart-f6d95159-8e16-4a83-a36c-d1f13043b1a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544424887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2544424887
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.454251971
Short name T522
Test name
Test status
Simulation time 16521939 ps
CPU time 0.73 seconds
Started Mar 02 01:19:05 PM PST 24
Finished Mar 02 01:19:05 PM PST 24
Peak memory 205208 kb
Host smart-443946ce-27a7-4a1c-bf60-eabe654f98e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454251971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.454251971
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3446820821
Short name T127
Test name
Test status
Simulation time 54466459 ps
CPU time 1.99 seconds
Started Mar 02 01:19:01 PM PST 24
Finished Mar 02 01:19:03 PM PST 24
Peak memory 205380 kb
Host smart-00a10f24-49d5-4213-ac88-b365c8eeb8da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446820821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3446820821
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1554896050
Short name T460
Test name
Test status
Simulation time 314897986 ps
CPU time 4.34 seconds
Started Mar 02 01:19:00 PM PST 24
Finished Mar 02 01:19:05 PM PST 24
Peak memory 213844 kb
Host smart-128b4749-c65c-4431-b69e-7e920b197217
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554896050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1554896050
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1994731556
Short name T101
Test name
Test status
Simulation time 252192619 ps
CPU time 8.9 seconds
Started Mar 02 01:19:04 PM PST 24
Finished Mar 02 01:19:13 PM PST 24
Peak memory 213792 kb
Host smart-2d8b5a87-80ae-4b1e-ad65-f96614412d2f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994731556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1994731556
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.543466813
Short name T133
Test name
Test status
Simulation time 1130880051 ps
CPU time 11.65 seconds
Started Mar 02 01:19:02 PM PST 24
Finished Mar 02 01:19:14 PM PST 24
Peak memory 205148 kb
Host smart-a8123eb1-9cfb-4111-bcf5-ea759a326b8d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543466813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.543466813
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.579795121
Short name T136
Test name
Test status
Simulation time 17914599 ps
CPU time 1.08 seconds
Started Mar 02 01:19:00 PM PST 24
Finished Mar 02 01:19:02 PM PST 24
Peak memory 205280 kb
Host smart-8a4a8f98-82a7-4592-8726-101a4aa808bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579795121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.579795121
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1261286351
Short name T498
Test name
Test status
Simulation time 32915272 ps
CPU time 1.83 seconds
Started Mar 02 01:19:00 PM PST 24
Finished Mar 02 01:19:02 PM PST 24
Peak memory 213560 kb
Host smart-06e24d29-6c7a-4488-b02e-2808b7277596
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261286351 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1261286351
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.4177510188
Short name T495
Test name
Test status
Simulation time 15296033 ps
CPU time 1.01 seconds
Started Mar 02 01:19:07 PM PST 24
Finished Mar 02 01:19:08 PM PST 24
Peak memory 205260 kb
Host smart-19a2e5c1-7caa-4f39-a891-8aa58fcfce07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177510188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.4177510188
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1782122128
Short name T427
Test name
Test status
Simulation time 44026257 ps
CPU time 0.73 seconds
Started Mar 02 01:19:01 PM PST 24
Finished Mar 02 01:19:02 PM PST 24
Peak memory 205204 kb
Host smart-a19d56f7-9af8-4d0a-9f4b-3861d1540352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782122128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1782122128
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.4075839740
Short name T436
Test name
Test status
Simulation time 43346320 ps
CPU time 2.44 seconds
Started Mar 02 01:19:05 PM PST 24
Finished Mar 02 01:19:07 PM PST 24
Peak memory 205420 kb
Host smart-e100c01b-9c25-4e63-a061-8037bbd32ce8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075839740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.4075839740
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1768618247
Short name T105
Test name
Test status
Simulation time 289152021 ps
CPU time 5.82 seconds
Started Mar 02 01:19:00 PM PST 24
Finished Mar 02 01:19:06 PM PST 24
Peak memory 213840 kb
Host smart-ad92a07c-9fcb-46a1-899a-b274349be696
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768618247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1768618247
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1156731252
Short name T423
Test name
Test status
Simulation time 96210937 ps
CPU time 3.26 seconds
Started Mar 02 01:19:06 PM PST 24
Finished Mar 02 01:19:09 PM PST 24
Peak memory 213632 kb
Host smart-8aeda345-1180-44fe-99ba-686d0f18d839
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156731252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1156731252
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.390377440
Short name T138
Test name
Test status
Simulation time 102730248 ps
CPU time 3.58 seconds
Started Mar 02 01:19:02 PM PST 24
Finished Mar 02 01:19:06 PM PST 24
Peak memory 208568 kb
Host smart-ccbaaddb-2f34-47b3-8fb2-41601b030109
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390377440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
390377440
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3866233048
Short name T170
Test name
Test status
Simulation time 28803334 ps
CPU time 0.95 seconds
Started Mar 02 01:19:16 PM PST 24
Finished Mar 02 01:19:17 PM PST 24
Peak memory 205264 kb
Host smart-a1329528-c101-4914-9175-b102100bbe7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866233048 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3866233048
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3979714281
Short name T510
Test name
Test status
Simulation time 272675453 ps
CPU time 0.91 seconds
Started Mar 02 01:19:26 PM PST 24
Finished Mar 02 01:19:31 PM PST 24
Peak memory 205196 kb
Host smart-bdaa912b-b43e-4720-b28a-60f9df9466e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979714281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3979714281
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2093340153
Short name T538
Test name
Test status
Simulation time 18386614 ps
CPU time 0.75 seconds
Started Mar 02 01:19:21 PM PST 24
Finished Mar 02 01:19:24 PM PST 24
Peak memory 205196 kb
Host smart-114eae5e-3cff-4e1f-8c11-54fff3130f8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093340153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2093340153
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.4137367103
Short name T507
Test name
Test status
Simulation time 102482388 ps
CPU time 1.65 seconds
Started Mar 02 01:19:23 PM PST 24
Finished Mar 02 01:19:28 PM PST 24
Peak memory 205320 kb
Host smart-9d6264fc-acb1-4b25-8332-8c30e2009373
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137367103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.4137367103
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3629096241
Short name T151
Test name
Test status
Simulation time 934602821 ps
CPU time 4.95 seconds
Started Mar 02 01:19:16 PM PST 24
Finished Mar 02 01:19:21 PM PST 24
Peak memory 213824 kb
Host smart-dcc6624b-7374-49d9-bda6-150f83c304eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629096241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3629096241
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3141298162
Short name T508
Test name
Test status
Simulation time 365330450 ps
CPU time 8.25 seconds
Started Mar 02 01:19:16 PM PST 24
Finished Mar 02 01:19:24 PM PST 24
Peak memory 213804 kb
Host smart-eed0ee3c-5846-46ec-a17e-7157aac45fff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141298162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3141298162
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.8207026
Short name T456
Test name
Test status
Simulation time 261112374 ps
CPU time 3.47 seconds
Started Mar 02 01:19:24 PM PST 24
Finished Mar 02 01:19:32 PM PST 24
Peak memory 213572 kb
Host smart-3f8daa2b-c667-4797-be59-753fcf7a8a93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8207026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.8207026
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3661755687
Short name T428
Test name
Test status
Simulation time 56783535 ps
CPU time 1.35 seconds
Started Mar 02 01:19:15 PM PST 24
Finished Mar 02 01:19:17 PM PST 24
Peak memory 213640 kb
Host smart-0a84f88b-b94f-4933-a89e-ea704a1cefb1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661755687 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3661755687
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3556771422
Short name T373
Test name
Test status
Simulation time 55140844 ps
CPU time 0.93 seconds
Started Mar 02 01:19:21 PM PST 24
Finished Mar 02 01:19:24 PM PST 24
Peak memory 205152 kb
Host smart-061db4b1-d5bb-4cf0-9dae-faf716790b4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556771422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3556771422
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1713156356
Short name T480
Test name
Test status
Simulation time 43517353 ps
CPU time 0.86 seconds
Started Mar 02 01:19:21 PM PST 24
Finished Mar 02 01:19:23 PM PST 24
Peak memory 205060 kb
Host smart-b5e5ebac-ba20-45fa-8d09-7cd8ca349927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713156356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1713156356
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.4193021131
Short name T520
Test name
Test status
Simulation time 310265613 ps
CPU time 3.25 seconds
Started Mar 02 01:19:14 PM PST 24
Finished Mar 02 01:19:17 PM PST 24
Peak memory 213844 kb
Host smart-5a534e17-4b94-478e-99cf-ab2a78a0ca69
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193021131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.4193021131
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1009149969
Short name T496
Test name
Test status
Simulation time 253774387 ps
CPU time 5.73 seconds
Started Mar 02 01:19:15 PM PST 24
Finished Mar 02 01:19:21 PM PST 24
Peak memory 213876 kb
Host smart-396aff88-694d-49ae-901f-3f63a8d34942
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009149969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1009149969
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.787909801
Short name T418
Test name
Test status
Simulation time 168724635 ps
CPU time 2.93 seconds
Started Mar 02 01:19:12 PM PST 24
Finished Mar 02 01:19:15 PM PST 24
Peak memory 213632 kb
Host smart-9a874b24-1349-4a5b-a3ea-d144a6e49640
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787909801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.787909801
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3743696035
Short name T513
Test name
Test status
Simulation time 13139691 ps
CPU time 0.98 seconds
Started Mar 02 01:19:15 PM PST 24
Finished Mar 02 01:19:16 PM PST 24
Peak memory 205416 kb
Host smart-a75bd64f-8267-4e3e-a09f-8e95ef3f7889
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743696035 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3743696035
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.157872471
Short name T484
Test name
Test status
Simulation time 37434083 ps
CPU time 0.71 seconds
Started Mar 02 01:19:17 PM PST 24
Finished Mar 02 01:19:18 PM PST 24
Peak memory 205056 kb
Host smart-02978be5-aa30-4a85-9407-a670296eb8e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157872471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.157872471
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3583786918
Short name T454
Test name
Test status
Simulation time 416621459 ps
CPU time 6.21 seconds
Started Mar 02 01:19:14 PM PST 24
Finished Mar 02 01:19:21 PM PST 24
Peak memory 213796 kb
Host smart-8298ebd0-31da-4b03-a3e4-2402d995099e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583786918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3583786918
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1373518480
Short name T529
Test name
Test status
Simulation time 516062491 ps
CPU time 7.92 seconds
Started Mar 02 01:19:17 PM PST 24
Finished Mar 02 01:19:26 PM PST 24
Peak memory 213872 kb
Host smart-3001adf0-51c7-4f39-9511-9f24f371fc73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373518480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1373518480
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2636984099
Short name T531
Test name
Test status
Simulation time 62432948 ps
CPU time 1.75 seconds
Started Mar 02 01:19:23 PM PST 24
Finished Mar 02 01:19:27 PM PST 24
Peak memory 214776 kb
Host smart-8a15498b-83b5-445d-9f62-60c0b54e2ba4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636984099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2636984099
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2925914535
Short name T422
Test name
Test status
Simulation time 28339867 ps
CPU time 1.03 seconds
Started Mar 02 01:19:21 PM PST 24
Finished Mar 02 01:19:23 PM PST 24
Peak memory 205420 kb
Host smart-e1aafaef-fc93-4b91-a529-0c75c3733a95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925914535 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2925914535
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3134479549
Short name T501
Test name
Test status
Simulation time 54313136 ps
CPU time 1.07 seconds
Started Mar 02 01:19:16 PM PST 24
Finished Mar 02 01:19:18 PM PST 24
Peak memory 205248 kb
Host smart-f86852f8-d396-432a-adca-55b1b350650c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134479549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3134479549
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.4152653769
Short name T415
Test name
Test status
Simulation time 9470140 ps
CPU time 0.7 seconds
Started Mar 02 01:19:20 PM PST 24
Finished Mar 02 01:19:21 PM PST 24
Peak memory 205212 kb
Host smart-002ed63b-591f-400c-958d-ce67d8c21fd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152653769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.4152653769
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.275316139
Short name T470
Test name
Test status
Simulation time 36502587 ps
CPU time 2.03 seconds
Started Mar 02 01:19:19 PM PST 24
Finished Mar 02 01:19:21 PM PST 24
Peak memory 205436 kb
Host smart-6253b97f-636c-4aa7-89c3-edfe54e235a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275316139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.275316139
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.999272983
Short name T163
Test name
Test status
Simulation time 117163658 ps
CPU time 3.73 seconds
Started Mar 02 01:19:19 PM PST 24
Finished Mar 02 01:19:23 PM PST 24
Peak memory 221980 kb
Host smart-d7207982-5def-4e4a-8103-6ba5b9dedc0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999272983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.999272983
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1427923884
Short name T112
Test name
Test status
Simulation time 167361404 ps
CPU time 2.16 seconds
Started Mar 02 01:19:16 PM PST 24
Finished Mar 02 01:19:18 PM PST 24
Peak memory 215860 kb
Host smart-3050e78b-fd00-4630-82ad-a98295ad8af9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427923884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1427923884
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2702982121
Short name T526
Test name
Test status
Simulation time 63792826 ps
CPU time 1.16 seconds
Started Mar 02 01:19:23 PM PST 24
Finished Mar 02 01:19:28 PM PST 24
Peak memory 205412 kb
Host smart-bc7692de-6643-4879-92b1-aa3a57d41dad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702982121 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2702982121
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2091421982
Short name T426
Test name
Test status
Simulation time 39348570 ps
CPU time 0.93 seconds
Started Mar 02 01:19:23 PM PST 24
Finished Mar 02 01:19:29 PM PST 24
Peak memory 205228 kb
Host smart-df0b4dad-ba6d-4e51-b92b-17b8b1859de1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091421982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2091421982
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2516248171
Short name T437
Test name
Test status
Simulation time 35558225 ps
CPU time 0.73 seconds
Started Mar 02 01:19:19 PM PST 24
Finished Mar 02 01:19:20 PM PST 24
Peak memory 205208 kb
Host smart-bd63d87a-8909-4033-84b4-f419f889404c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516248171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2516248171
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1724929598
Short name T444
Test name
Test status
Simulation time 328066008 ps
CPU time 2.26 seconds
Started Mar 02 01:19:24 PM PST 24
Finished Mar 02 01:19:31 PM PST 24
Peak memory 213864 kb
Host smart-94c4c993-1dc8-4a34-ad65-fc591ac3744d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724929598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1724929598
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.4247956619
Short name T123
Test name
Test status
Simulation time 51865239 ps
CPU time 1.69 seconds
Started Mar 02 01:19:21 PM PST 24
Finished Mar 02 01:19:23 PM PST 24
Peak memory 205448 kb
Host smart-123026fc-cfa0-46ea-8e10-764cd050f11b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247956619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.4247956619
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3689101972
Short name T171
Test name
Test status
Simulation time 29610667 ps
CPU time 1.62 seconds
Started Mar 02 01:19:19 PM PST 24
Finished Mar 02 01:19:20 PM PST 24
Peak memory 213520 kb
Host smart-c2bbd474-6649-4b7c-bcf9-474a8149b32a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689101972 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3689101972
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.624823350
Short name T434
Test name
Test status
Simulation time 15985558 ps
CPU time 1.03 seconds
Started Mar 02 01:19:22 PM PST 24
Finished Mar 02 01:19:24 PM PST 24
Peak memory 205116 kb
Host smart-0666f01b-cd72-4b2e-b9ec-b874ea693664
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624823350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.624823350
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3143411486
Short name T443
Test name
Test status
Simulation time 43622710 ps
CPU time 0.74 seconds
Started Mar 02 01:19:16 PM PST 24
Finished Mar 02 01:19:17 PM PST 24
Peak memory 205120 kb
Host smart-e18db535-00a0-4896-9acf-0dd37b9f6fd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143411486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3143411486
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.4025284903
Short name T128
Test name
Test status
Simulation time 51876860 ps
CPU time 1.75 seconds
Started Mar 02 01:19:21 PM PST 24
Finished Mar 02 01:19:24 PM PST 24
Peak memory 205208 kb
Host smart-37df7674-1c1b-4732-aaba-f4c923df9461
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025284903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.4025284903
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.144686453
Short name T473
Test name
Test status
Simulation time 1345817552 ps
CPU time 6.97 seconds
Started Mar 02 01:19:25 PM PST 24
Finished Mar 02 01:19:37 PM PST 24
Peak memory 213816 kb
Host smart-30d71cdb-13df-4de2-a6a8-9cecaaa2b18d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144686453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.144686453
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.4217131585
Short name T490
Test name
Test status
Simulation time 245236053 ps
CPU time 1.97 seconds
Started Mar 02 01:19:20 PM PST 24
Finished Mar 02 01:19:22 PM PST 24
Peak memory 216656 kb
Host smart-413aa1cb-6df8-4f54-84ef-3fc01dceac5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217131585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.4217131585
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1195185165
Short name T528
Test name
Test status
Simulation time 73267567 ps
CPU time 1.23 seconds
Started Mar 02 01:19:35 PM PST 24
Finished Mar 02 01:19:36 PM PST 24
Peak memory 205348 kb
Host smart-cea427b2-8b1c-4bbe-82cf-5d0b03a5e9f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195185165 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1195185165
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.352696807
Short name T449
Test name
Test status
Simulation time 33457702 ps
CPU time 1.16 seconds
Started Mar 02 01:19:30 PM PST 24
Finished Mar 02 01:19:32 PM PST 24
Peak memory 205116 kb
Host smart-0572b37c-1d22-4f8d-927e-469a0c50c311
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352696807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.352696807
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2992884430
Short name T442
Test name
Test status
Simulation time 30281130 ps
CPU time 0.71 seconds
Started Mar 02 01:19:29 PM PST 24
Finished Mar 02 01:19:35 PM PST 24
Peak memory 205224 kb
Host smart-66210515-768a-471c-a5eb-8ad7d015782b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992884430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2992884430
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1544249281
Short name T462
Test name
Test status
Simulation time 119392639 ps
CPU time 2.24 seconds
Started Mar 02 01:19:24 PM PST 24
Finished Mar 02 01:19:31 PM PST 24
Peak memory 205364 kb
Host smart-74369bce-9251-474c-8572-da0d3863c491
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544249281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1544249281
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3710388861
Short name T471
Test name
Test status
Simulation time 440451593 ps
CPU time 4.06 seconds
Started Mar 02 01:19:15 PM PST 24
Finished Mar 02 01:19:20 PM PST 24
Peak memory 218664 kb
Host smart-d98efd37-3126-49ed-b38a-8498f632014e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710388861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3710388861
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2159988879
Short name T497
Test name
Test status
Simulation time 387450411 ps
CPU time 2.6 seconds
Started Mar 02 01:19:25 PM PST 24
Finished Mar 02 01:19:32 PM PST 24
Peak memory 213568 kb
Host smart-96307c29-069b-4635-8f32-5f0ed447718a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159988879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2159988879
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.485167206
Short name T417
Test name
Test status
Simulation time 24421727 ps
CPU time 1.21 seconds
Started Mar 02 01:19:38 PM PST 24
Finished Mar 02 01:19:39 PM PST 24
Peak memory 213712 kb
Host smart-ed14f942-52ac-49eb-8651-65ff8d5064bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485167206 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.485167206
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3354553831
Short name T483
Test name
Test status
Simulation time 26379874 ps
CPU time 1.1 seconds
Started Mar 02 01:19:21 PM PST 24
Finished Mar 02 01:19:24 PM PST 24
Peak memory 205308 kb
Host smart-b7938fed-e376-4c04-b4dc-e5ebed8a82ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354553831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3354553831
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2408673964
Short name T477
Test name
Test status
Simulation time 13564546 ps
CPU time 0.77 seconds
Started Mar 02 01:19:23 PM PST 24
Finished Mar 02 01:19:29 PM PST 24
Peak memory 205176 kb
Host smart-262042ec-99cd-45e6-8518-22337b79414e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408673964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2408673964
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2354441551
Short name T515
Test name
Test status
Simulation time 45611181 ps
CPU time 1.97 seconds
Started Mar 02 01:19:36 PM PST 24
Finished Mar 02 01:19:39 PM PST 24
Peak memory 205300 kb
Host smart-28eb1a33-4a3a-42dd-85d7-ef2e20c1287a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354441551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2354441551
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.859103850
Short name T102
Test name
Test status
Simulation time 1152133067 ps
CPU time 3.63 seconds
Started Mar 02 01:19:35 PM PST 24
Finished Mar 02 01:19:39 PM PST 24
Peak memory 213760 kb
Host smart-466188c4-05df-4fd0-be42-8e5e65e18794
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859103850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.859103850
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2052381888
Short name T150
Test name
Test status
Simulation time 21361287 ps
CPU time 1.68 seconds
Started Mar 02 01:19:37 PM PST 24
Finished Mar 02 01:19:39 PM PST 24
Peak memory 215688 kb
Host smart-e2db3b0e-df8c-43fe-8969-f25612cc614a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052381888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2052381888
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2928612996
Short name T372
Test name
Test status
Simulation time 1874474270 ps
CPU time 39.78 seconds
Started Mar 02 01:19:40 PM PST 24
Finished Mar 02 01:20:19 PM PST 24
Peak memory 211340 kb
Host smart-f5826189-3f78-4dae-94ac-79818a0f90ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928612996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2928612996
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4197196863
Short name T499
Test name
Test status
Simulation time 21640903 ps
CPU time 1.19 seconds
Started Mar 02 01:19:22 PM PST 24
Finished Mar 02 01:19:27 PM PST 24
Peak memory 205472 kb
Host smart-9ef270c8-4f1e-4d9b-a019-f67601906108
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197196863 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.4197196863
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1250227777
Short name T448
Test name
Test status
Simulation time 45092060 ps
CPU time 0.87 seconds
Started Mar 02 01:19:26 PM PST 24
Finished Mar 02 01:19:32 PM PST 24
Peak memory 205132 kb
Host smart-2e7c32ec-0988-428e-b736-5bcab801a340
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250227777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1250227777
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1070256960
Short name T440
Test name
Test status
Simulation time 82407761 ps
CPU time 0.85 seconds
Started Mar 02 01:19:21 PM PST 24
Finished Mar 02 01:19:24 PM PST 24
Peak memory 205176 kb
Host smart-ec5af446-e443-4e11-a489-5cfe4b453d42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070256960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1070256960
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1507783682
Short name T467
Test name
Test status
Simulation time 33611986 ps
CPU time 2.36 seconds
Started Mar 02 01:19:31 PM PST 24
Finished Mar 02 01:19:34 PM PST 24
Peak memory 205332 kb
Host smart-b82af278-c982-45f2-94b0-2b5d5e137c29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507783682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1507783682
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.467420800
Short name T516
Test name
Test status
Simulation time 87728571 ps
CPU time 2.46 seconds
Started Mar 02 01:19:27 PM PST 24
Finished Mar 02 01:19:33 PM PST 24
Peak memory 213720 kb
Host smart-fd4bef24-a3c8-451e-a05f-8ec774dd0ebd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467420800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.467420800
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4172621502
Short name T493
Test name
Test status
Simulation time 409772782 ps
CPU time 11.06 seconds
Started Mar 02 01:19:33 PM PST 24
Finished Mar 02 01:19:45 PM PST 24
Peak memory 213804 kb
Host smart-ed252c27-58a9-49b9-b1bb-640a4e2b86b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172621502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.4172621502
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.4021041747
Short name T421
Test name
Test status
Simulation time 26581248 ps
CPU time 1.67 seconds
Started Mar 02 01:19:37 PM PST 24
Finished Mar 02 01:19:39 PM PST 24
Peak memory 213704 kb
Host smart-694c3f2a-7593-4655-9d86-fd7695e01003
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021041747 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.4021041747
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.219567612
Short name T469
Test name
Test status
Simulation time 44873880 ps
CPU time 1 seconds
Started Mar 02 01:19:28 PM PST 24
Finished Mar 02 01:19:32 PM PST 24
Peak memory 205200 kb
Host smart-ff246cb4-2309-440f-a857-9eb5a7234f62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219567612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.219567612
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.4038022166
Short name T482
Test name
Test status
Simulation time 33213129 ps
CPU time 0.75 seconds
Started Mar 02 01:19:23 PM PST 24
Finished Mar 02 01:19:26 PM PST 24
Peak memory 205096 kb
Host smart-4097bd09-04e3-4411-aaa4-6f14d17d4091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038022166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.4038022166
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3056646426
Short name T130
Test name
Test status
Simulation time 39740088 ps
CPU time 1.31 seconds
Started Mar 02 01:19:23 PM PST 24
Finished Mar 02 01:19:27 PM PST 24
Peak memory 205412 kb
Host smart-a93747a4-88b5-4e60-bafe-0b4093977ee9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056646426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3056646426
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3546612910
Short name T100
Test name
Test status
Simulation time 83859955 ps
CPU time 2.56 seconds
Started Mar 02 01:19:24 PM PST 24
Finished Mar 02 01:19:31 PM PST 24
Peak memory 222128 kb
Host smart-29b23b73-3287-4f2a-8301-5a393fe83117
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546612910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3546612910
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3691046003
Short name T478
Test name
Test status
Simulation time 1677853236 ps
CPU time 15.8 seconds
Started Mar 02 01:19:24 PM PST 24
Finished Mar 02 01:19:43 PM PST 24
Peak memory 213888 kb
Host smart-bbf85609-b6b9-40a8-b858-78e184a6b5ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691046003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3691046003
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.317165143
Short name T432
Test name
Test status
Simulation time 203502217 ps
CPU time 2.77 seconds
Started Mar 02 01:19:23 PM PST 24
Finished Mar 02 01:19:30 PM PST 24
Peak memory 213712 kb
Host smart-30dbccd7-88b8-45fe-8e41-52d932392cc9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317165143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.317165143
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3476917302
Short name T457
Test name
Test status
Simulation time 143234326 ps
CPU time 3.85 seconds
Started Mar 02 01:19:00 PM PST 24
Finished Mar 02 01:19:04 PM PST 24
Peak memory 205240 kb
Host smart-0cac085f-d9d8-4214-bec2-ad167da48dcb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476917302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
476917302
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2669888678
Short name T420
Test name
Test status
Simulation time 52377901 ps
CPU time 0.89 seconds
Started Mar 02 01:19:04 PM PST 24
Finished Mar 02 01:19:05 PM PST 24
Peak memory 205120 kb
Host smart-319633c8-4109-4c6e-94ac-043092c87860
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669888678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
669888678
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.4172599243
Short name T463
Test name
Test status
Simulation time 29653521 ps
CPU time 1.79 seconds
Started Mar 02 01:18:59 PM PST 24
Finished Mar 02 01:19:00 PM PST 24
Peak memory 213632 kb
Host smart-4ba4f138-0c79-465c-85ff-714c5e9f2f45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172599243 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.4172599243
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3571989433
Short name T125
Test name
Test status
Simulation time 10893947 ps
CPU time 0.88 seconds
Started Mar 02 01:19:00 PM PST 24
Finished Mar 02 01:19:01 PM PST 24
Peak memory 205212 kb
Host smart-ed8927bc-92cc-49d6-958d-4d99ea820daf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571989433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3571989433
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4157591392
Short name T521
Test name
Test status
Simulation time 19783260 ps
CPU time 0.78 seconds
Started Mar 02 01:19:04 PM PST 24
Finished Mar 02 01:19:05 PM PST 24
Peak memory 205136 kb
Host smart-a297dc85-7fca-4c59-b86e-83d50fea19ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157591392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4157591392
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.889797521
Short name T129
Test name
Test status
Simulation time 35146717 ps
CPU time 2.41 seconds
Started Mar 02 01:19:01 PM PST 24
Finished Mar 02 01:19:03 PM PST 24
Peak memory 205356 kb
Host smart-a2cfa7ec-6779-411a-9508-dc97a7627936
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889797521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.889797521
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2323775863
Short name T108
Test name
Test status
Simulation time 221360759 ps
CPU time 5.63 seconds
Started Mar 02 01:19:00 PM PST 24
Finished Mar 02 01:19:06 PM PST 24
Peak memory 213776 kb
Host smart-22967031-ca82-4a7b-9322-b2d7e7256af1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323775863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2323775863
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.430448919
Short name T452
Test name
Test status
Simulation time 415365064 ps
CPU time 4.55 seconds
Started Mar 02 01:19:02 PM PST 24
Finished Mar 02 01:19:06 PM PST 24
Peak memory 213864 kb
Host smart-56047fca-190c-4ecb-92a8-b82cb31e63b0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430448919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.430448919
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1259812187
Short name T114
Test name
Test status
Simulation time 30440202 ps
CPU time 1.47 seconds
Started Mar 02 01:19:04 PM PST 24
Finished Mar 02 01:19:06 PM PST 24
Peak memory 213604 kb
Host smart-4d9dbb17-62b2-4fa7-82a3-655a09f374cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259812187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1259812187
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.850561984
Short name T141
Test name
Test status
Simulation time 135678865 ps
CPU time 3.32 seconds
Started Mar 02 01:18:58 PM PST 24
Finished Mar 02 01:19:02 PM PST 24
Peak memory 213604 kb
Host smart-59c54da9-4b99-4a66-9a29-e34e2585d6d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850561984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
850561984
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3987420246
Short name T479
Test name
Test status
Simulation time 11521238 ps
CPU time 0.83 seconds
Started Mar 02 01:19:24 PM PST 24
Finished Mar 02 01:19:29 PM PST 24
Peak memory 205100 kb
Host smart-575dd284-36a7-4f2c-bd9a-fa1d911fe195
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987420246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3987420246
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.4113904593
Short name T517
Test name
Test status
Simulation time 49458532 ps
CPU time 0.9 seconds
Started Mar 02 01:19:38 PM PST 24
Finished Mar 02 01:19:39 PM PST 24
Peak memory 205200 kb
Host smart-6fa1e84d-734d-42cb-b6ac-87895c7a67eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113904593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.4113904593
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1523876887
Short name T424
Test name
Test status
Simulation time 19902580 ps
CPU time 0.83 seconds
Started Mar 02 01:19:29 PM PST 24
Finished Mar 02 01:19:32 PM PST 24
Peak memory 205216 kb
Host smart-30c1fd6d-e1a2-4f1a-9b21-7242a83cf402
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523876887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1523876887
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1858712198
Short name T500
Test name
Test status
Simulation time 8494943 ps
CPU time 0.68 seconds
Started Mar 02 01:19:23 PM PST 24
Finished Mar 02 01:19:31 PM PST 24
Peak memory 205216 kb
Host smart-5c50be37-9fdc-4f0d-9007-bcd9ee72097d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858712198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1858712198
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3338105719
Short name T512
Test name
Test status
Simulation time 11601855 ps
CPU time 0.87 seconds
Started Mar 02 01:19:36 PM PST 24
Finished Mar 02 01:19:37 PM PST 24
Peak memory 205136 kb
Host smart-1f12d6fb-8fca-439b-9cf4-91a28937214f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338105719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3338105719
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3298430563
Short name T453
Test name
Test status
Simulation time 19115002 ps
CPU time 0.72 seconds
Started Mar 02 01:19:29 PM PST 24
Finished Mar 02 01:19:32 PM PST 24
Peak memory 205200 kb
Host smart-9a0e4bc2-6add-448e-a992-cee782d52621
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298430563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3298430563
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1648758312
Short name T458
Test name
Test status
Simulation time 18552642 ps
CPU time 0.83 seconds
Started Mar 02 01:19:31 PM PST 24
Finished Mar 02 01:19:32 PM PST 24
Peak memory 205048 kb
Host smart-6f1c7871-125c-4942-9e60-4b1e841b2800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648758312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1648758312
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3546739734
Short name T465
Test name
Test status
Simulation time 11383657 ps
CPU time 0.73 seconds
Started Mar 02 01:19:30 PM PST 24
Finished Mar 02 01:19:32 PM PST 24
Peak memory 205220 kb
Host smart-e8797ccc-76b2-4655-a7b3-c4cacad6bae1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546739734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3546739734
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1709386899
Short name T419
Test name
Test status
Simulation time 12520433 ps
CPU time 0.89 seconds
Started Mar 02 01:19:35 PM PST 24
Finished Mar 02 01:19:36 PM PST 24
Peak memory 205120 kb
Host smart-98305549-4b8c-4f45-91a0-3b188deec6e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709386899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1709386899
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2934097293
Short name T446
Test name
Test status
Simulation time 14860986 ps
CPU time 0.75 seconds
Started Mar 02 01:19:21 PM PST 24
Finished Mar 02 01:19:24 PM PST 24
Peak memory 205204 kb
Host smart-c87e9803-89b4-44a3-bb53-6442e89601b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934097293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2934097293
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.148031907
Short name T537
Test name
Test status
Simulation time 134172541 ps
CPU time 7.22 seconds
Started Mar 02 01:19:02 PM PST 24
Finished Mar 02 01:19:09 PM PST 24
Peak memory 205240 kb
Host smart-4d4e7b87-38fe-4315-8041-9a65809f18fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148031907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.148031907
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1155214641
Short name T451
Test name
Test status
Simulation time 55339767 ps
CPU time 1.1 seconds
Started Mar 02 01:19:00 PM PST 24
Finished Mar 02 01:19:01 PM PST 24
Peak memory 205208 kb
Host smart-0219753c-dfd8-4707-b6ca-ecf8593d12bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155214641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
155214641
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.460663460
Short name T162
Test name
Test status
Simulation time 26642401 ps
CPU time 1.34 seconds
Started Mar 02 01:19:03 PM PST 24
Finished Mar 02 01:19:04 PM PST 24
Peak memory 213408 kb
Host smart-136726ed-9b02-40e2-b911-6ac3f2b94a34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460663460 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.460663460
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1991784901
Short name T172
Test name
Test status
Simulation time 10808875 ps
CPU time 0.72 seconds
Started Mar 02 01:19:03 PM PST 24
Finished Mar 02 01:19:04 PM PST 24
Peak memory 205096 kb
Host smart-73b6bb26-1839-40c2-bf91-e5337651d624
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991784901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1991784901
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2584590201
Short name T535
Test name
Test status
Simulation time 247402632 ps
CPU time 3.08 seconds
Started Mar 02 01:19:05 PM PST 24
Finished Mar 02 01:19:08 PM PST 24
Peak memory 213852 kb
Host smart-9a091d73-678f-40cb-a7e9-5dfa2504054c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584590201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2584590201
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.118772203
Short name T533
Test name
Test status
Simulation time 434289375 ps
CPU time 16.74 seconds
Started Mar 02 01:18:56 PM PST 24
Finished Mar 02 01:19:13 PM PST 24
Peak memory 213928 kb
Host smart-d6b2c584-38c4-4581-b211-0a8c5bfcb4e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118772203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.118772203
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2927706969
Short name T476
Test name
Test status
Simulation time 165188457 ps
CPU time 2.36 seconds
Started Mar 02 01:19:00 PM PST 24
Finished Mar 02 01:19:02 PM PST 24
Peak memory 213624 kb
Host smart-86a82c80-dec0-486c-805d-0b4a58e12326
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927706969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2927706969
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3758517154
Short name T371
Test name
Test status
Simulation time 329988882 ps
CPU time 3.78 seconds
Started Mar 02 01:19:02 PM PST 24
Finished Mar 02 01:19:06 PM PST 24
Peak memory 208368 kb
Host smart-c57c88f0-adeb-4d85-be30-ab5c7435fc78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758517154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3758517154
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3129443619
Short name T509
Test name
Test status
Simulation time 18984663 ps
CPU time 0.8 seconds
Started Mar 02 01:19:25 PM PST 24
Finished Mar 02 01:19:31 PM PST 24
Peak memory 205208 kb
Host smart-4d646c79-6eff-48e0-9b81-0bd40f2a515b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129443619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3129443619
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2181098973
Short name T119
Test name
Test status
Simulation time 14426633 ps
CPU time 0.87 seconds
Started Mar 02 01:19:35 PM PST 24
Finished Mar 02 01:19:36 PM PST 24
Peak memory 205224 kb
Host smart-1cf5f288-a551-43a6-a929-074161bde70f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181098973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2181098973
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3038255268
Short name T425
Test name
Test status
Simulation time 40473551 ps
CPU time 0.84 seconds
Started Mar 02 01:19:35 PM PST 24
Finished Mar 02 01:19:36 PM PST 24
Peak memory 205120 kb
Host smart-532237bc-615a-4d51-ab81-fb7b67ac6984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038255268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3038255268
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3227540046
Short name T445
Test name
Test status
Simulation time 13436365 ps
CPU time 0.88 seconds
Started Mar 02 01:19:30 PM PST 24
Finished Mar 02 01:19:32 PM PST 24
Peak memory 205212 kb
Host smart-81f94b84-a8b8-45c5-b63d-3aba805e8e80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227540046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3227540046
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1099503374
Short name T488
Test name
Test status
Simulation time 7967222 ps
CPU time 0.71 seconds
Started Mar 02 01:19:45 PM PST 24
Finished Mar 02 01:19:46 PM PST 24
Peak memory 205216 kb
Host smart-a099f10f-79e9-4ed9-bdca-094d37d7e264
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099503374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1099503374
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.4201646791
Short name T433
Test name
Test status
Simulation time 27186863 ps
CPU time 0.69 seconds
Started Mar 02 01:19:46 PM PST 24
Finished Mar 02 01:19:47 PM PST 24
Peak memory 205220 kb
Host smart-5d5bf97c-f9f2-49e6-870e-b2f1c83d1e9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201646791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.4201646791
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.4015818375
Short name T514
Test name
Test status
Simulation time 51083041 ps
CPU time 0.73 seconds
Started Mar 02 01:19:41 PM PST 24
Finished Mar 02 01:19:42 PM PST 24
Peak memory 205044 kb
Host smart-11c559d2-7ed9-4836-ac56-4321b172e02c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015818375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.4015818375
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.913261054
Short name T505
Test name
Test status
Simulation time 22516323 ps
CPU time 0.72 seconds
Started Mar 02 01:19:38 PM PST 24
Finished Mar 02 01:19:39 PM PST 24
Peak memory 205132 kb
Host smart-325fae9e-8997-46bc-8082-f0c8023a7645
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913261054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.913261054
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3264371582
Short name T472
Test name
Test status
Simulation time 25231787 ps
CPU time 0.75 seconds
Started Mar 02 01:19:37 PM PST 24
Finished Mar 02 01:19:38 PM PST 24
Peak memory 205136 kb
Host smart-81a8b474-39b6-4aaa-8b48-6e84c3b86f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264371582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3264371582
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3441751710
Short name T416
Test name
Test status
Simulation time 46129246 ps
CPU time 0.82 seconds
Started Mar 02 01:19:49 PM PST 24
Finished Mar 02 01:19:50 PM PST 24
Peak memory 205212 kb
Host smart-768c023c-9a1d-46b4-a115-d1649e5eb0e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441751710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3441751710
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1621729476
Short name T494
Test name
Test status
Simulation time 215252709 ps
CPU time 5.17 seconds
Started Mar 02 01:19:06 PM PST 24
Finished Mar 02 01:19:12 PM PST 24
Peak memory 205300 kb
Host smart-810a30c1-02a4-4ec6-81b4-01ea86fe018c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621729476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
621729476
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1893145268
Short name T506
Test name
Test status
Simulation time 33272580 ps
CPU time 1.12 seconds
Started Mar 02 01:19:11 PM PST 24
Finished Mar 02 01:19:12 PM PST 24
Peak memory 205288 kb
Host smart-20433ccf-a920-4f34-bea2-357d11509305
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893145268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
893145268
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.304794565
Short name T466
Test name
Test status
Simulation time 53391600 ps
CPU time 1.2 seconds
Started Mar 02 01:19:13 PM PST 24
Finished Mar 02 01:19:14 PM PST 24
Peak memory 213612 kb
Host smart-f30a6c1b-9b2c-4234-adca-be534ba59623
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304794565 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.304794565
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.4094004094
Short name T430
Test name
Test status
Simulation time 10963401 ps
CPU time 0.72 seconds
Started Mar 02 01:19:07 PM PST 24
Finished Mar 02 01:19:07 PM PST 24
Peak memory 205128 kb
Host smart-5ca0e318-ae5b-4e3a-b526-2bc6de6c9231
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094004094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.4094004094
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.404215906
Short name T106
Test name
Test status
Simulation time 326132998 ps
CPU time 3.93 seconds
Started Mar 02 01:19:01 PM PST 24
Finished Mar 02 01:19:05 PM PST 24
Peak memory 213528 kb
Host smart-adf56c93-6200-4f9e-a5d5-57c463441669
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404215906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.404215906
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2778025089
Short name T441
Test name
Test status
Simulation time 405553899 ps
CPU time 8.46 seconds
Started Mar 02 01:18:59 PM PST 24
Finished Mar 02 01:19:08 PM PST 24
Peak memory 219868 kb
Host smart-18598d2c-7142-41a9-9813-367e1d02679c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778025089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2778025089
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1327466395
Short name T140
Test name
Test status
Simulation time 20447323 ps
CPU time 1.38 seconds
Started Mar 02 01:19:05 PM PST 24
Finished Mar 02 01:19:06 PM PST 24
Peak memory 221700 kb
Host smart-6337ffce-e246-461b-a490-e7fadb0e4f73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327466395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1327466395
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.2942009483
Short name T124
Test name
Test status
Simulation time 41483246 ps
CPU time 0.77 seconds
Started Mar 02 01:19:40 PM PST 24
Finished Mar 02 01:19:41 PM PST 24
Peak memory 205140 kb
Host smart-c9d2be9e-2f34-498e-a7bf-2594665b19d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942009483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.2942009483
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.405796380
Short name T523
Test name
Test status
Simulation time 13957264 ps
CPU time 0.72 seconds
Started Mar 02 01:19:39 PM PST 24
Finished Mar 02 01:19:40 PM PST 24
Peak memory 205128 kb
Host smart-fbc4fdb0-2df5-4a60-86f5-14985054006a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405796380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.405796380
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4255604523
Short name T518
Test name
Test status
Simulation time 19893089 ps
CPU time 0.82 seconds
Started Mar 02 01:19:52 PM PST 24
Finished Mar 02 01:19:54 PM PST 24
Peak memory 205364 kb
Host smart-0a4f62c8-463c-418a-b77d-267bf52caede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255604523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.4255604523
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1214032254
Short name T530
Test name
Test status
Simulation time 12660254 ps
CPU time 0.78 seconds
Started Mar 02 01:19:39 PM PST 24
Finished Mar 02 01:19:40 PM PST 24
Peak memory 205180 kb
Host smart-0837f92d-ff86-461f-a3dd-e259b6e0a2f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214032254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1214032254
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2377314016
Short name T438
Test name
Test status
Simulation time 34625621 ps
CPU time 0.79 seconds
Started Mar 02 01:19:39 PM PST 24
Finished Mar 02 01:19:39 PM PST 24
Peak memory 205236 kb
Host smart-4e534c0a-f4a2-4ba7-b4a0-ca4519c2b714
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377314016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2377314016
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.973420770
Short name T468
Test name
Test status
Simulation time 12350486 ps
CPU time 0.79 seconds
Started Mar 02 01:19:41 PM PST 24
Finished Mar 02 01:19:42 PM PST 24
Peak memory 205136 kb
Host smart-8e8ac127-fa00-48d1-bf13-3b8cc062820a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973420770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.973420770
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.4108961397
Short name T461
Test name
Test status
Simulation time 33362324 ps
CPU time 0.72 seconds
Started Mar 02 01:19:47 PM PST 24
Finished Mar 02 01:19:48 PM PST 24
Peak memory 205232 kb
Host smart-0e34d587-5f8b-42c7-b3c5-a00340218f0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108961397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.4108961397
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1114101714
Short name T489
Test name
Test status
Simulation time 12170261 ps
CPU time 0.73 seconds
Started Mar 02 01:19:40 PM PST 24
Finished Mar 02 01:19:41 PM PST 24
Peak memory 205164 kb
Host smart-20c5761d-6d62-4d0f-9887-7b8303a1b947
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114101714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1114101714
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2842639381
Short name T532
Test name
Test status
Simulation time 41361036 ps
CPU time 0.8 seconds
Started Mar 02 01:19:36 PM PST 24
Finished Mar 02 01:19:37 PM PST 24
Peak memory 205176 kb
Host smart-00a21412-5c79-4a3d-9520-304bf0e419de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842639381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2842639381
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.562832302
Short name T485
Test name
Test status
Simulation time 37594418 ps
CPU time 0.84 seconds
Started Mar 02 01:19:38 PM PST 24
Finished Mar 02 01:19:39 PM PST 24
Peak memory 205208 kb
Host smart-3d5b1120-cfbf-4437-88f5-eaf365992c2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562832302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.562832302
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.177695425
Short name T455
Test name
Test status
Simulation time 95656261 ps
CPU time 1.92 seconds
Started Mar 02 01:19:08 PM PST 24
Finished Mar 02 01:19:10 PM PST 24
Peak memory 213556 kb
Host smart-7e3fccb0-7be8-472e-b62a-c4a7931646d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177695425 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.177695425
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1194550024
Short name T414
Test name
Test status
Simulation time 21878796 ps
CPU time 0.84 seconds
Started Mar 02 01:19:12 PM PST 24
Finished Mar 02 01:19:13 PM PST 24
Peak memory 205140 kb
Host smart-8b8ba2d9-b581-4af0-93da-97701fe9adcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194550024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1194550024
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3549252819
Short name T492
Test name
Test status
Simulation time 212943607 ps
CPU time 5.7 seconds
Started Mar 02 01:19:13 PM PST 24
Finished Mar 02 01:19:19 PM PST 24
Peak memory 213776 kb
Host smart-a8e661cf-94b7-4ad8-95fb-c79c17f14ea3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549252819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3549252819
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.1717874381
Short name T450
Test name
Test status
Simulation time 202894183 ps
CPU time 2.21 seconds
Started Mar 02 01:19:05 PM PST 24
Finished Mar 02 01:19:07 PM PST 24
Peak memory 213616 kb
Host smart-448a7a09-4c69-491e-97d8-90fe6f0c9e41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717874381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.1717874381
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2973048009
Short name T539
Test name
Test status
Simulation time 25458786 ps
CPU time 1.18 seconds
Started Mar 02 01:19:08 PM PST 24
Finished Mar 02 01:19:09 PM PST 24
Peak memory 205464 kb
Host smart-8b73d740-6fb9-4687-9ebb-a75f021c8f64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973048009 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2973048009
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.901479100
Short name T161
Test name
Test status
Simulation time 16990445 ps
CPU time 0.97 seconds
Started Mar 02 01:19:06 PM PST 24
Finished Mar 02 01:19:07 PM PST 24
Peak memory 205216 kb
Host smart-767c88f0-7369-4e68-be74-d900f084d57d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901479100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.901479100
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2301123326
Short name T525
Test name
Test status
Simulation time 14706510 ps
CPU time 0.79 seconds
Started Mar 02 01:19:11 PM PST 24
Finished Mar 02 01:19:12 PM PST 24
Peak memory 205212 kb
Host smart-1c7dbccc-7282-426e-b146-f62fc38c6323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301123326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2301123326
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.4093941081
Short name T117
Test name
Test status
Simulation time 46660655 ps
CPU time 1.46 seconds
Started Mar 02 01:19:08 PM PST 24
Finished Mar 02 01:19:10 PM PST 24
Peak memory 205300 kb
Host smart-a90bf42b-a397-4af5-b11d-5fc7d2b9ec23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093941081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.4093941081
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3453122702
Short name T536
Test name
Test status
Simulation time 165864872 ps
CPU time 6.31 seconds
Started Mar 02 01:19:15 PM PST 24
Finished Mar 02 01:19:22 PM PST 24
Peak memory 213724 kb
Host smart-f05dce19-e71a-41b0-a002-43e3c6e02abb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453122702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3453122702
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.148532029
Short name T475
Test name
Test status
Simulation time 48237931 ps
CPU time 2.12 seconds
Started Mar 02 01:19:10 PM PST 24
Finished Mar 02 01:19:12 PM PST 24
Peak memory 213616 kb
Host smart-24274dad-bb50-460f-8bd4-3b8a30c02a14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148532029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.148532029
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2741257685
Short name T122
Test name
Test status
Simulation time 88507362 ps
CPU time 1.14 seconds
Started Mar 02 01:19:14 PM PST 24
Finished Mar 02 01:19:15 PM PST 24
Peak memory 205260 kb
Host smart-98495a9e-d954-4b09-8760-776fcb1af25f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741257685 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2741257685
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1699183530
Short name T126
Test name
Test status
Simulation time 22141211 ps
CPU time 0.93 seconds
Started Mar 02 01:19:11 PM PST 24
Finished Mar 02 01:19:12 PM PST 24
Peak memory 205124 kb
Host smart-bee2905d-8632-458b-9acb-c4c21490a4c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699183530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1699183530
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.216909354
Short name T439
Test name
Test status
Simulation time 31466690 ps
CPU time 0.69 seconds
Started Mar 02 01:19:05 PM PST 24
Finished Mar 02 01:19:06 PM PST 24
Peak memory 205128 kb
Host smart-ec390808-d034-4852-9aa9-3169d8a2fb16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216909354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.216909354
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2473322104
Short name T504
Test name
Test status
Simulation time 108814519 ps
CPU time 3.75 seconds
Started Mar 02 01:19:07 PM PST 24
Finished Mar 02 01:19:11 PM PST 24
Peak memory 205508 kb
Host smart-766604c0-e7b2-4cb0-a3a4-bd7010036aa0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473322104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2473322104
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2109713674
Short name T486
Test name
Test status
Simulation time 1415351311 ps
CPU time 18.12 seconds
Started Mar 02 01:19:09 PM PST 24
Finished Mar 02 01:19:28 PM PST 24
Peak memory 222108 kb
Host smart-fe12a206-2c62-4147-9389-a6ddbd9fbba0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109713674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2109713674
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.196378565
Short name T464
Test name
Test status
Simulation time 1684188032 ps
CPU time 14.1 seconds
Started Mar 02 01:19:13 PM PST 24
Finished Mar 02 01:19:27 PM PST 24
Peak memory 213728 kb
Host smart-2ba0c473-15d6-4c67-b00f-757542273bf5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196378565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.196378565
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.742066172
Short name T429
Test name
Test status
Simulation time 70072806 ps
CPU time 2.25 seconds
Started Mar 02 01:19:12 PM PST 24
Finished Mar 02 01:19:15 PM PST 24
Peak memory 213564 kb
Host smart-989a6323-8844-4c0e-882b-cbb83db82643
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742066172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.742066172
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1659654630
Short name T113
Test name
Test status
Simulation time 97347623 ps
CPU time 1.76 seconds
Started Mar 02 01:19:15 PM PST 24
Finished Mar 02 01:19:17 PM PST 24
Peak memory 213552 kb
Host smart-31871431-b12d-4980-88be-5f607f19465a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659654630 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1659654630
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.242403641
Short name T447
Test name
Test status
Simulation time 55501357 ps
CPU time 1.09 seconds
Started Mar 02 01:19:09 PM PST 24
Finished Mar 02 01:19:10 PM PST 24
Peak memory 205240 kb
Host smart-47e27895-b6cd-42a7-b7df-f5b24d7bc9e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242403641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.242403641
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2009455527
Short name T527
Test name
Test status
Simulation time 21898289 ps
CPU time 0.69 seconds
Started Mar 02 01:19:15 PM PST 24
Finished Mar 02 01:19:16 PM PST 24
Peak memory 205224 kb
Host smart-d8cb7cd9-e795-4a56-a842-1735be3599f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009455527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2009455527
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.581686532
Short name T459
Test name
Test status
Simulation time 47028942 ps
CPU time 2.05 seconds
Started Mar 02 01:19:14 PM PST 24
Finished Mar 02 01:19:16 PM PST 24
Peak memory 205340 kb
Host smart-c86f88ad-da84-4f27-81ec-b85da725be9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581686532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.581686532
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1080850590
Short name T487
Test name
Test status
Simulation time 200112287 ps
CPU time 3.32 seconds
Started Mar 02 01:19:09 PM PST 24
Finished Mar 02 01:19:12 PM PST 24
Peak memory 213872 kb
Host smart-10ca052b-804b-45da-90a4-4b6be6eabe51
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080850590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1080850590
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4195432919
Short name T534
Test name
Test status
Simulation time 536872729 ps
CPU time 6.57 seconds
Started Mar 02 01:19:09 PM PST 24
Finished Mar 02 01:19:15 PM PST 24
Peak memory 219708 kb
Host smart-51b6c9b4-e38a-49e4-be4f-6e3a36325a4c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195432919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.4195432919
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1762552341
Short name T474
Test name
Test status
Simulation time 51903144 ps
CPU time 1.41 seconds
Started Mar 02 01:19:07 PM PST 24
Finished Mar 02 01:19:08 PM PST 24
Peak memory 213656 kb
Host smart-43b72260-67a1-4d6e-b468-5b11c200b1ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762552341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1762552341
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.241922138
Short name T143
Test name
Test status
Simulation time 4078200238 ps
CPU time 25.73 seconds
Started Mar 02 01:19:11 PM PST 24
Finished Mar 02 01:19:37 PM PST 24
Peak memory 213560 kb
Host smart-8eb4a5bc-391f-4620-8ba2-b9674de0c743
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241922138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
241922138
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1571789878
Short name T491
Test name
Test status
Simulation time 59863941 ps
CPU time 1.34 seconds
Started Mar 02 01:19:10 PM PST 24
Finished Mar 02 01:19:12 PM PST 24
Peak memory 205332 kb
Host smart-57c4937b-fd1f-4e1e-b121-f33b9a3d6f35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571789878 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1571789878
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3976743492
Short name T431
Test name
Test status
Simulation time 211418060 ps
CPU time 1.08 seconds
Started Mar 02 01:19:07 PM PST 24
Finished Mar 02 01:19:08 PM PST 24
Peak memory 205152 kb
Host smart-353516f5-b165-4784-a8d3-ec98f8fe7640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976743492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3976743492
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.684799382
Short name T511
Test name
Test status
Simulation time 10032650 ps
CPU time 0.72 seconds
Started Mar 02 01:19:12 PM PST 24
Finished Mar 02 01:19:13 PM PST 24
Peak memory 205172 kb
Host smart-9a7094ac-6d18-4c4a-ae63-48fd3f4cf1fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684799382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.684799382
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1466370279
Short name T118
Test name
Test status
Simulation time 26723320 ps
CPU time 1.78 seconds
Started Mar 02 01:19:07 PM PST 24
Finished Mar 02 01:19:09 PM PST 24
Peak memory 205292 kb
Host smart-f58d25ab-c455-4d4c-b190-37895ca139ac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466370279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1466370279
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.615602807
Short name T519
Test name
Test status
Simulation time 482297867 ps
CPU time 9.32 seconds
Started Mar 02 01:19:12 PM PST 24
Finished Mar 02 01:19:22 PM PST 24
Peak memory 213832 kb
Host smart-b8e4ccba-ecd3-42d3-bf95-6f8ed531a590
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615602807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.615602807
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1105782950
Short name T481
Test name
Test status
Simulation time 352844679 ps
CPU time 5.47 seconds
Started Mar 02 01:19:09 PM PST 24
Finished Mar 02 01:19:15 PM PST 24
Peak memory 213792 kb
Host smart-ca1decc9-9ea6-4071-96f3-300e833c2090
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105782950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1105782950
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.12173356
Short name T502
Test name
Test status
Simulation time 893532723 ps
CPU time 2.42 seconds
Started Mar 02 01:19:15 PM PST 24
Finished Mar 02 01:19:18 PM PST 24
Peak memory 215664 kb
Host smart-a8537be8-23a7-4333-bc47-463f85017cf3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12173356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.12173356
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3313194484
Short name T217
Test name
Test status
Simulation time 557068721 ps
CPU time 7.62 seconds
Started Mar 02 12:39:14 PM PST 24
Finished Mar 02 12:39:21 PM PST 24
Peak memory 222296 kb
Host smart-ffddf637-dab9-4815-bc7d-9d6350f6d4c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3313194484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3313194484
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.37752222
Short name T8
Test name
Test status
Simulation time 426582975 ps
CPU time 4.35 seconds
Started Mar 02 12:39:22 PM PST 24
Finished Mar 02 12:39:27 PM PST 24
Peak memory 221004 kb
Host smart-816a12dc-a637-4d87-957f-6784d94577fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37752222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.37752222
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2678408092
Short name T939
Test name
Test status
Simulation time 27821087 ps
CPU time 1.48 seconds
Started Mar 02 12:39:20 PM PST 24
Finished Mar 02 12:39:22 PM PST 24
Peak memory 208628 kb
Host smart-161f2615-becc-459a-8587-56b31042ffca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678408092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2678408092
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.560324204
Short name T286
Test name
Test status
Simulation time 2057602887 ps
CPU time 44.55 seconds
Started Mar 02 12:39:23 PM PST 24
Finished Mar 02 12:40:08 PM PST 24
Peak memory 219684 kb
Host smart-92d7c6fa-5456-42bf-b245-e294b82967fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560324204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.560324204
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3299796076
Short name T192
Test name
Test status
Simulation time 113655868 ps
CPU time 3.52 seconds
Started Mar 02 12:39:23 PM PST 24
Finished Mar 02 12:39:26 PM PST 24
Peak memory 222568 kb
Host smart-5e0f8bb0-cac7-4a2c-a271-583119b82bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299796076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3299796076
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_sideload.4125744427
Short name T930
Test name
Test status
Simulation time 80054307 ps
CPU time 3.32 seconds
Started Mar 02 12:39:14 PM PST 24
Finished Mar 02 12:39:17 PM PST 24
Peak memory 208196 kb
Host smart-c6aa1bd0-099e-4980-90af-7afbd5c295eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125744427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.4125744427
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2017514787
Short name T1016
Test name
Test status
Simulation time 54155281 ps
CPU time 2.97 seconds
Started Mar 02 12:39:17 PM PST 24
Finished Mar 02 12:39:20 PM PST 24
Peak memory 206864 kb
Host smart-c64ec862-cb33-4fcd-b8d4-5480330d9380
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017514787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2017514787
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.784540753
Short name T592
Test name
Test status
Simulation time 3615958447 ps
CPU time 8.22 seconds
Started Mar 02 12:39:17 PM PST 24
Finished Mar 02 12:39:25 PM PST 24
Peak memory 208608 kb
Host smart-558ee84b-5993-4fbd-907b-1fa2222479bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784540753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.784540753
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3625708818
Short name T664
Test name
Test status
Simulation time 447993221 ps
CPU time 3.81 seconds
Started Mar 02 12:39:16 PM PST 24
Finished Mar 02 12:39:20 PM PST 24
Peak memory 208452 kb
Host smart-28880f8a-3355-4d04-a7ed-9bec76e5f38e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625708818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3625708818
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.4200060274
Short name T775
Test name
Test status
Simulation time 453765595 ps
CPU time 4.65 seconds
Started Mar 02 12:39:20 PM PST 24
Finished Mar 02 12:39:24 PM PST 24
Peak memory 208704 kb
Host smart-54913468-7ad5-4fe5-8599-2d5da4c034a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200060274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.4200060274
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.146496655
Short name T782
Test name
Test status
Simulation time 715662076 ps
CPU time 5.13 seconds
Started Mar 02 12:39:13 PM PST 24
Finished Mar 02 12:39:18 PM PST 24
Peak memory 207188 kb
Host smart-29999a7e-68cf-422b-b91a-9a74bb6aa25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146496655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.146496655
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1343066259
Short name T951
Test name
Test status
Simulation time 211152757 ps
CPU time 3.3 seconds
Started Mar 02 12:39:20 PM PST 24
Finished Mar 02 12:39:24 PM PST 24
Peak memory 218140 kb
Host smart-055e3676-a3d6-4061-8c09-09948801fcc3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343066259 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1343066259
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2477162085
Short name T739
Test name
Test status
Simulation time 213907021 ps
CPU time 3.58 seconds
Started Mar 02 12:39:22 PM PST 24
Finished Mar 02 12:39:26 PM PST 24
Peak memory 209504 kb
Host smart-01d372af-f2d3-4966-a84d-4b3908c0b6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477162085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2477162085
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3948129489
Short name T569
Test name
Test status
Simulation time 75512052 ps
CPU time 2.76 seconds
Started Mar 02 12:39:23 PM PST 24
Finished Mar 02 12:39:25 PM PST 24
Peak memory 210252 kb
Host smart-4ebd8142-4cf9-4679-a7cb-1a5507e9bd82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948129489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3948129489
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2705370390
Short name T1057
Test name
Test status
Simulation time 46942546 ps
CPU time 0.75 seconds
Started Mar 02 12:39:48 PM PST 24
Finished Mar 02 12:39:49 PM PST 24
Peak memory 205852 kb
Host smart-60579bc5-4304-4c1c-8580-c4f94e4556f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705370390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2705370390
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.4057089525
Short name T760
Test name
Test status
Simulation time 89539294 ps
CPU time 2.57 seconds
Started Mar 02 12:39:34 PM PST 24
Finished Mar 02 12:39:37 PM PST 24
Peak memory 207908 kb
Host smart-67781367-398d-4c0a-b8eb-6f25848f9a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057089525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.4057089525
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3352512742
Short name T323
Test name
Test status
Simulation time 1138521653 ps
CPU time 29.62 seconds
Started Mar 02 12:39:36 PM PST 24
Finished Mar 02 12:40:09 PM PST 24
Peak memory 214392 kb
Host smart-deb34078-13e0-4d96-bac7-d695ec02d7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352512742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3352512742
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1964326651
Short name T81
Test name
Test status
Simulation time 535527689 ps
CPU time 6.41 seconds
Started Mar 02 12:39:34 PM PST 24
Finished Mar 02 12:39:41 PM PST 24
Peak memory 209884 kb
Host smart-869c83c0-b131-4c24-a564-227149bcb857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964326651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1964326651
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.61771305
Short name T885
Test name
Test status
Simulation time 284312964 ps
CPU time 5.39 seconds
Started Mar 02 12:39:34 PM PST 24
Finished Mar 02 12:39:40 PM PST 24
Peak memory 210180 kb
Host smart-e9890cb6-6234-4cd5-9475-a96dee86e35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61771305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.61771305
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.741991372
Short name T1054
Test name
Test status
Simulation time 8502606619 ps
CPU time 25.45 seconds
Started Mar 02 12:39:32 PM PST 24
Finished Mar 02 12:40:00 PM PST 24
Peak memory 208700 kb
Host smart-dbb8cdca-1138-481e-bc98-023e54c04523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741991372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.741991372
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2657899184
Short name T11
Test name
Test status
Simulation time 720841575 ps
CPU time 20.21 seconds
Started Mar 02 12:39:36 PM PST 24
Finished Mar 02 12:39:56 PM PST 24
Peak memory 238680 kb
Host smart-d634f961-44e9-4f74-b200-2b742065ae56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657899184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2657899184
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.553183314
Short name T822
Test name
Test status
Simulation time 44165123 ps
CPU time 2.41 seconds
Started Mar 02 12:39:21 PM PST 24
Finished Mar 02 12:39:25 PM PST 24
Peak memory 206564 kb
Host smart-327bf69f-76fa-4449-9eb1-1cfcae689f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553183314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.553183314
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3859925500
Short name T979
Test name
Test status
Simulation time 762393689 ps
CPU time 4.08 seconds
Started Mar 02 12:39:23 PM PST 24
Finished Mar 02 12:39:27 PM PST 24
Peak memory 208512 kb
Host smart-df15cd61-a9bd-4858-8c2f-7aa386be6415
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859925500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3859925500
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2494998356
Short name T279
Test name
Test status
Simulation time 127355947 ps
CPU time 2.89 seconds
Started Mar 02 12:39:22 PM PST 24
Finished Mar 02 12:39:25 PM PST 24
Peak memory 206912 kb
Host smart-86fbbec5-7b34-4935-8f96-50c42f0c774e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494998356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2494998356
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.517182608
Short name T679
Test name
Test status
Simulation time 192198599 ps
CPU time 3.15 seconds
Started Mar 02 12:39:36 PM PST 24
Finished Mar 02 12:39:42 PM PST 24
Peak memory 208688 kb
Host smart-84a703d9-a478-4171-a3da-305e1626e2b5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517182608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.517182608
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.591151262
Short name T167
Test name
Test status
Simulation time 453537152 ps
CPU time 3.07 seconds
Started Mar 02 12:39:35 PM PST 24
Finished Mar 02 12:39:39 PM PST 24
Peak memory 209208 kb
Host smart-c7f7d789-1f85-42b6-a301-01305bc1ee0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591151262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.591151262
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2574376917
Short name T558
Test name
Test status
Simulation time 153684376 ps
CPU time 5.77 seconds
Started Mar 02 12:39:23 PM PST 24
Finished Mar 02 12:39:29 PM PST 24
Peak memory 208680 kb
Host smart-922eb282-8114-4031-9171-6787fda86635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574376917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2574376917
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2995009738
Short name T239
Test name
Test status
Simulation time 844253112 ps
CPU time 13.06 seconds
Started Mar 02 12:39:36 PM PST 24
Finished Mar 02 12:39:49 PM PST 24
Peak memory 221444 kb
Host smart-e437428c-3730-4306-88d7-0695ad023ad0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995009738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2995009738
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3782138995
Short name T326
Test name
Test status
Simulation time 2045096383 ps
CPU time 9.05 seconds
Started Mar 02 12:39:34 PM PST 24
Finished Mar 02 12:39:44 PM PST 24
Peak memory 223368 kb
Host smart-01f25663-622a-4efa-a7ec-91f195544c5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782138995 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3782138995
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1665803026
Short name T762
Test name
Test status
Simulation time 254689215 ps
CPU time 7.12 seconds
Started Mar 02 12:39:36 PM PST 24
Finished Mar 02 12:39:46 PM PST 24
Peak memory 214392 kb
Host smart-dbfeea2e-82c2-4a59-b582-e09a1742c602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665803026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1665803026
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2571652771
Short name T973
Test name
Test status
Simulation time 184352866 ps
CPU time 5.15 seconds
Started Mar 02 12:39:35 PM PST 24
Finished Mar 02 12:39:41 PM PST 24
Peak memory 209828 kb
Host smart-8d17d69c-eebe-47d6-b948-29bf9449db88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571652771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2571652771
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.4291604814
Short name T837
Test name
Test status
Simulation time 27815083 ps
CPU time 0.81 seconds
Started Mar 02 12:40:45 PM PST 24
Finished Mar 02 12:40:46 PM PST 24
Peak memory 205808 kb
Host smart-49d50acd-8827-4b43-b767-b4db08c9dffd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291604814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.4291604814
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2801662752
Short name T1021
Test name
Test status
Simulation time 146245318 ps
CPU time 4.58 seconds
Started Mar 02 12:40:27 PM PST 24
Finished Mar 02 12:40:32 PM PST 24
Peak memory 214376 kb
Host smart-a076a6d8-ccc8-404a-bccb-f71866c11b84
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2801662752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2801662752
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.688110401
Short name T263
Test name
Test status
Simulation time 71921454 ps
CPU time 3.15 seconds
Started Mar 02 12:40:28 PM PST 24
Finished Mar 02 12:40:31 PM PST 24
Peak memory 209328 kb
Host smart-73fbe5ef-ed4a-4fbc-9d52-c3d1f6075e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688110401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.688110401
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1394742175
Short name T229
Test name
Test status
Simulation time 47731928 ps
CPU time 3.1 seconds
Started Mar 02 12:40:26 PM PST 24
Finished Mar 02 12:40:29 PM PST 24
Peak memory 214136 kb
Host smart-b850a39b-f0f4-416f-aec0-ad7b1d65f8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394742175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1394742175
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3480071886
Short name T277
Test name
Test status
Simulation time 169744084 ps
CPU time 4.37 seconds
Started Mar 02 12:40:25 PM PST 24
Finished Mar 02 12:40:30 PM PST 24
Peak memory 218500 kb
Host smart-8c45f194-09ab-480d-bbab-da2d067825ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480071886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3480071886
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2414644474
Short name T758
Test name
Test status
Simulation time 138845932 ps
CPU time 2.96 seconds
Started Mar 02 12:40:28 PM PST 24
Finished Mar 02 12:40:32 PM PST 24
Peak memory 218408 kb
Host smart-0c4c6bc6-f366-4bbb-b0ab-bd857f9ba7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414644474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2414644474
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2726470133
Short name T391
Test name
Test status
Simulation time 140940199 ps
CPU time 3.59 seconds
Started Mar 02 12:40:27 PM PST 24
Finished Mar 02 12:40:31 PM PST 24
Peak memory 208336 kb
Host smart-c64339c0-6cff-47f2-96f2-ce002d189db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726470133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2726470133
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2499157201
Short name T972
Test name
Test status
Simulation time 142554604 ps
CPU time 2.39 seconds
Started Mar 02 12:40:28 PM PST 24
Finished Mar 02 12:40:30 PM PST 24
Peak memory 206780 kb
Host smart-b66dae60-2532-4db0-b922-579244152c60
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499157201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2499157201
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1931752774
Short name T74
Test name
Test status
Simulation time 339338439 ps
CPU time 6.81 seconds
Started Mar 02 12:40:29 PM PST 24
Finished Mar 02 12:40:36 PM PST 24
Peak memory 207916 kb
Host smart-e0719649-1294-4424-bf1f-a0c22fa136f5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931752774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1931752774
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3517278427
Short name T859
Test name
Test status
Simulation time 3945010448 ps
CPU time 49.52 seconds
Started Mar 02 12:40:27 PM PST 24
Finished Mar 02 12:41:17 PM PST 24
Peak memory 208336 kb
Host smart-0c440adf-d812-42a5-8350-ef5324d9185f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517278427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3517278427
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.613012331
Short name T620
Test name
Test status
Simulation time 43815380 ps
CPU time 2.04 seconds
Started Mar 02 12:40:28 PM PST 24
Finished Mar 02 12:40:30 PM PST 24
Peak memory 208476 kb
Host smart-719c8076-e4c2-4496-8f7d-0f92027df72b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613012331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.613012331
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.903255411
Short name T744
Test name
Test status
Simulation time 264404625 ps
CPU time 1.78 seconds
Started Mar 02 12:40:27 PM PST 24
Finished Mar 02 12:40:29 PM PST 24
Peak memory 207232 kb
Host smart-d18f33af-68d9-48f2-a61e-3fea120697c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903255411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.903255411
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.479853218
Short name T68
Test name
Test status
Simulation time 1978581107 ps
CPU time 22.07 seconds
Started Mar 02 12:40:29 PM PST 24
Finished Mar 02 12:40:52 PM PST 24
Peak memory 214320 kb
Host smart-6c9f8711-ae5c-4a9e-89d0-ca7ab3a21c23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479853218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.479853218
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.427501059
Short name T16
Test name
Test status
Simulation time 68172991 ps
CPU time 3.57 seconds
Started Mar 02 12:40:29 PM PST 24
Finished Mar 02 12:40:33 PM PST 24
Peak memory 222516 kb
Host smart-98845c33-c25d-4166-9ed8-2a0edde9fb2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427501059 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.427501059
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.773379678
Short name T910
Test name
Test status
Simulation time 74559781 ps
CPU time 3.65 seconds
Started Mar 02 12:40:26 PM PST 24
Finished Mar 02 12:40:30 PM PST 24
Peak memory 209832 kb
Host smart-2c40d046-8a15-4e12-a099-7252ee5cccbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773379678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.773379678
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3245537828
Short name T659
Test name
Test status
Simulation time 102971066 ps
CPU time 3.59 seconds
Started Mar 02 12:40:27 PM PST 24
Finished Mar 02 12:40:31 PM PST 24
Peak memory 210964 kb
Host smart-e80c3107-430d-4c6f-a418-22ca4b99d721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245537828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3245537828
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.177390269
Short name T911
Test name
Test status
Simulation time 50648078 ps
CPU time 0.81 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:40:47 PM PST 24
Peak memory 205720 kb
Host smart-3ca2410b-f761-46df-9974-f0cc87a0019f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177390269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.177390269
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.481204371
Short name T57
Test name
Test status
Simulation time 58525752 ps
CPU time 3.96 seconds
Started Mar 02 12:40:45 PM PST 24
Finished Mar 02 12:40:50 PM PST 24
Peak memory 209840 kb
Host smart-dcd4dd9c-352b-4c72-8c0a-532f49978784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481204371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.481204371
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1038064752
Short name T677
Test name
Test status
Simulation time 197962779 ps
CPU time 2.79 seconds
Started Mar 02 12:40:47 PM PST 24
Finished Mar 02 12:40:50 PM PST 24
Peak memory 214296 kb
Host smart-09f5a54c-5bcd-43c1-9177-d495112c8a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038064752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1038064752
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.4470462
Short name T353
Test name
Test status
Simulation time 483186569 ps
CPU time 4.31 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:40:50 PM PST 24
Peak memory 208976 kb
Host smart-6b97f6c9-f533-4081-a8f5-eda6d134e6af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4470462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.4470462
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.854680865
Short name T696
Test name
Test status
Simulation time 101128106 ps
CPU time 4.53 seconds
Started Mar 02 12:40:47 PM PST 24
Finished Mar 02 12:40:52 PM PST 24
Peak memory 219640 kb
Host smart-d451ff0b-74ef-4680-9e13-b1848b08384b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854680865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.854680865
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.778281043
Short name T174
Test name
Test status
Simulation time 145403035 ps
CPU time 4.86 seconds
Started Mar 02 12:40:44 PM PST 24
Finished Mar 02 12:40:49 PM PST 24
Peak memory 207544 kb
Host smart-9fc1e1e7-e341-4e7a-b123-c4cdf4d9afa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778281043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.778281043
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.939476596
Short name T618
Test name
Test status
Simulation time 58334021 ps
CPU time 2.98 seconds
Started Mar 02 12:40:43 PM PST 24
Finished Mar 02 12:40:46 PM PST 24
Peak memory 208044 kb
Host smart-219a185f-e6b8-4c35-8278-d7a49a94343a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939476596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.939476596
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.640176751
Short name T579
Test name
Test status
Simulation time 123472087 ps
CPU time 4.23 seconds
Started Mar 02 12:40:47 PM PST 24
Finished Mar 02 12:40:51 PM PST 24
Peak memory 208136 kb
Host smart-63e00d85-6ca1-4063-887b-8f37b8fe84f8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640176751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.640176751
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1029577562
Short name T986
Test name
Test status
Simulation time 189511559 ps
CPU time 2.94 seconds
Started Mar 02 12:40:44 PM PST 24
Finished Mar 02 12:40:47 PM PST 24
Peak memory 206888 kb
Host smart-c928f107-9a4b-4c0b-9a13-65234b4e88f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029577562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1029577562
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2314825560
Short name T544
Test name
Test status
Simulation time 206929785 ps
CPU time 3.18 seconds
Started Mar 02 12:40:47 PM PST 24
Finished Mar 02 12:40:50 PM PST 24
Peak memory 206668 kb
Host smart-d200595e-805e-4340-9091-65ecab77cd70
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314825560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2314825560
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3355854174
Short name T944
Test name
Test status
Simulation time 35556444 ps
CPU time 2.13 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:40:48 PM PST 24
Peak memory 215592 kb
Host smart-6233a1ea-dfa5-4a29-945a-2e750a76a4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355854174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3355854174
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3716338797
Short name T381
Test name
Test status
Simulation time 6019534591 ps
CPU time 27.23 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:41:13 PM PST 24
Peak memory 208564 kb
Host smart-a315ca90-9851-4827-91ec-17adf1e4d591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716338797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3716338797
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1600223400
Short name T947
Test name
Test status
Simulation time 7102506002 ps
CPU time 95.6 seconds
Started Mar 02 12:40:45 PM PST 24
Finished Mar 02 12:42:21 PM PST 24
Peak memory 209808 kb
Host smart-b9919555-30b2-405c-9dce-37af105a3592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600223400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1600223400
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1496649660
Short name T682
Test name
Test status
Simulation time 180681231 ps
CPU time 2.55 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:40:49 PM PST 24
Peak memory 210684 kb
Host smart-19d36d36-cdef-42bf-8fc9-bf9c52cfc543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496649660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1496649660
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2475959013
Short name T959
Test name
Test status
Simulation time 32154991 ps
CPU time 0.74 seconds
Started Mar 02 12:40:44 PM PST 24
Finished Mar 02 12:40:44 PM PST 24
Peak memory 205816 kb
Host smart-504306b8-93bc-445a-91d7-60c8900b895f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475959013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2475959013
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.887489855
Short name T764
Test name
Test status
Simulation time 2451765178 ps
CPU time 37.65 seconds
Started Mar 02 12:40:47 PM PST 24
Finished Mar 02 12:41:25 PM PST 24
Peak memory 222112 kb
Host smart-0bc6b20a-41fa-469c-9ea7-ba053e67e8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887489855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.887489855
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1240212521
Short name T609
Test name
Test status
Simulation time 347924996 ps
CPU time 6.56 seconds
Started Mar 02 12:40:45 PM PST 24
Finished Mar 02 12:40:52 PM PST 24
Peak memory 209180 kb
Host smart-9a0d6c52-4ac4-4147-99c6-0e906cf052b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240212521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1240212521
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3684621917
Short name T603
Test name
Test status
Simulation time 68220188 ps
CPU time 3.21 seconds
Started Mar 02 12:40:45 PM PST 24
Finished Mar 02 12:40:49 PM PST 24
Peak memory 208760 kb
Host smart-11f95702-d780-4c80-9731-35ae7b9d52a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684621917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3684621917
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1598009339
Short name T80
Test name
Test status
Simulation time 486855394 ps
CPU time 8.3 seconds
Started Mar 02 12:40:42 PM PST 24
Finished Mar 02 12:40:50 PM PST 24
Peak memory 211132 kb
Host smart-9a54d89b-982c-44d1-9841-4d246e6400d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598009339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1598009339
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1147291783
Short name T607
Test name
Test status
Simulation time 609347123 ps
CPU time 4.59 seconds
Started Mar 02 12:40:47 PM PST 24
Finished Mar 02 12:40:52 PM PST 24
Peak memory 214312 kb
Host smart-acdfb6e5-638b-4ae5-b768-91210106f925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147291783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1147291783
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3909998169
Short name T567
Test name
Test status
Simulation time 1525715673 ps
CPU time 10.1 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:40:56 PM PST 24
Peak memory 208932 kb
Host smart-315d07ac-1279-4649-9ef0-b02b3865026d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909998169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3909998169
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.705633196
Short name T1026
Test name
Test status
Simulation time 1148204687 ps
CPU time 13.23 seconds
Started Mar 02 12:40:45 PM PST 24
Finished Mar 02 12:40:59 PM PST 24
Peak memory 207904 kb
Host smart-c5c8b1c6-e242-4af8-aac4-b45e0a45d0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705633196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.705633196
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2731386422
Short name T754
Test name
Test status
Simulation time 2502327765 ps
CPU time 16.72 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:41:03 PM PST 24
Peak memory 208620 kb
Host smart-e8e663c7-b6ec-464e-ada6-51ae1aa7bfe3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731386422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2731386422
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.480973340
Short name T672
Test name
Test status
Simulation time 3473004645 ps
CPU time 23.5 seconds
Started Mar 02 12:40:48 PM PST 24
Finished Mar 02 12:41:11 PM PST 24
Peak memory 208332 kb
Host smart-64052911-8a49-43f4-a1f5-f27b0cf9e09c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480973340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.480973340
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3790258765
Short name T769
Test name
Test status
Simulation time 615392881 ps
CPU time 4.71 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:40:50 PM PST 24
Peak memory 222448 kb
Host smart-12a5b9b4-8702-456a-a262-aba34830a6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790258765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3790258765
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.842874300
Short name T730
Test name
Test status
Simulation time 96426296 ps
CPU time 1.93 seconds
Started Mar 02 12:40:45 PM PST 24
Finished Mar 02 12:40:47 PM PST 24
Peak memory 206780 kb
Host smart-8f6bc747-120e-469d-b768-617f24f08589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842874300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.842874300
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.1943034031
Short name T735
Test name
Test status
Simulation time 103890857 ps
CPU time 5.69 seconds
Started Mar 02 12:40:44 PM PST 24
Finished Mar 02 12:40:49 PM PST 24
Peak memory 222492 kb
Host smart-707d73aa-2efe-4733-b9ba-a236090a8a34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943034031 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.1943034031
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1905301544
Short name T831
Test name
Test status
Simulation time 780040934 ps
CPU time 10.18 seconds
Started Mar 02 12:40:45 PM PST 24
Finished Mar 02 12:40:55 PM PST 24
Peak memory 208924 kb
Host smart-ae3cd304-c846-40f5-a847-d8bcb418c939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905301544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1905301544
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1898089224
Short name T554
Test name
Test status
Simulation time 36150149 ps
CPU time 2.27 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:40:48 PM PST 24
Peak memory 210088 kb
Host smart-aff4ec62-b22a-483c-b251-008bfad55464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898089224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1898089224
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.4171016361
Short name T965
Test name
Test status
Simulation time 15330131 ps
CPU time 0.77 seconds
Started Mar 02 12:40:58 PM PST 24
Finished Mar 02 12:40:59 PM PST 24
Peak memory 205852 kb
Host smart-95324dba-90d8-4a73-bf70-5728fbfa9897
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171016361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.4171016361
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3172041268
Short name T942
Test name
Test status
Simulation time 12286888014 ps
CPU time 115.14 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:42:41 PM PST 24
Peak memory 218576 kb
Host smart-e0c5e2e6-8736-48f4-9cee-01c9ceb265e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3172041268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3172041268
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.327534797
Short name T7
Test name
Test status
Simulation time 753891506 ps
CPU time 9.54 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:40:55 PM PST 24
Peak memory 222864 kb
Host smart-4844177a-d5b1-4bac-9a16-5ed56ddf056b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327534797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.327534797
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3672569623
Short name T647
Test name
Test status
Simulation time 58260793 ps
CPU time 1.7 seconds
Started Mar 02 12:40:44 PM PST 24
Finished Mar 02 12:40:46 PM PST 24
Peak memory 207780 kb
Host smart-2e5c97b8-70c0-4c99-bb78-c319cbaec46d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672569623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3672569623
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_random.2232091247
Short name T1052
Test name
Test status
Simulation time 265008819 ps
CPU time 8.78 seconds
Started Mar 02 12:40:47 PM PST 24
Finished Mar 02 12:40:56 PM PST 24
Peak memory 207340 kb
Host smart-65101feb-b495-4c55-95b0-753df428c8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232091247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2232091247
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.347462607
Short name T575
Test name
Test status
Simulation time 33281213 ps
CPU time 1.76 seconds
Started Mar 02 12:40:46 PM PST 24
Finished Mar 02 12:40:48 PM PST 24
Peak memory 206856 kb
Host smart-e5b74282-c255-42f0-8370-e875867b8c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347462607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.347462607
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.4169623263
Short name T719
Test name
Test status
Simulation time 926416252 ps
CPU time 19.63 seconds
Started Mar 02 12:40:44 PM PST 24
Finished Mar 02 12:41:04 PM PST 24
Peak memory 208588 kb
Host smart-acbd3400-6ab9-41ff-bded-564a3a22e227
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169623263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.4169623263
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3332375647
Short name T812
Test name
Test status
Simulation time 915974399 ps
CPU time 23.84 seconds
Started Mar 02 12:40:45 PM PST 24
Finished Mar 02 12:41:09 PM PST 24
Peak memory 208508 kb
Host smart-e393bf7d-8de9-4c35-b1b8-3b1f83c0c18f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332375647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3332375647
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1404570761
Short name T306
Test name
Test status
Simulation time 242960038 ps
CPU time 3.62 seconds
Started Mar 02 12:40:45 PM PST 24
Finished Mar 02 12:40:49 PM PST 24
Peak memory 208660 kb
Host smart-e1f85cf7-04b4-4665-b6e8-259c0d215c2a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404570761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1404570761
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3541423491
Short name T715
Test name
Test status
Simulation time 98779167 ps
CPU time 2.99 seconds
Started Mar 02 12:40:57 PM PST 24
Finished Mar 02 12:41:00 PM PST 24
Peak memory 214280 kb
Host smart-115fe7da-b31c-44ab-acf6-a84592036a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541423491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3541423491
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.4005975228
Short name T650
Test name
Test status
Simulation time 85171274 ps
CPU time 3.4 seconds
Started Mar 02 12:40:45 PM PST 24
Finished Mar 02 12:40:49 PM PST 24
Peak memory 208664 kb
Host smart-252a67b2-9767-4055-a911-475a7715f254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005975228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.4005975228
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.890644457
Short name T964
Test name
Test status
Simulation time 526843109 ps
CPU time 22.53 seconds
Started Mar 02 12:40:55 PM PST 24
Finished Mar 02 12:41:18 PM PST 24
Peak memory 215044 kb
Host smart-ef15ef20-1774-493e-8763-4f00c250cde9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890644457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.890644457
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2900665373
Short name T110
Test name
Test status
Simulation time 657161794 ps
CPU time 5.89 seconds
Started Mar 02 12:41:05 PM PST 24
Finished Mar 02 12:41:11 PM PST 24
Peak memory 220136 kb
Host smart-e78d623e-a457-4561-bf79-7036dd62a1ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900665373 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2900665373
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.4269650647
Short name T932
Test name
Test status
Simulation time 1333352110 ps
CPU time 5.18 seconds
Started Mar 02 12:40:45 PM PST 24
Finished Mar 02 12:40:51 PM PST 24
Peak memory 207560 kb
Host smart-1dff3707-3a34-4990-a6a9-d9a87cec7bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269650647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.4269650647
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.770251218
Short name T378
Test name
Test status
Simulation time 201783912 ps
CPU time 2.53 seconds
Started Mar 02 12:40:54 PM PST 24
Finished Mar 02 12:40:57 PM PST 24
Peak memory 209792 kb
Host smart-d8109d01-c9c3-4813-9c91-5c6c02879a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770251218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.770251218
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1601690437
Short name T1018
Test name
Test status
Simulation time 52061250 ps
CPU time 0.79 seconds
Started Mar 02 12:40:56 PM PST 24
Finished Mar 02 12:40:57 PM PST 24
Peak memory 205792 kb
Host smart-6aa39e8b-8b6b-4eb3-98f3-5f783b4d50b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601690437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1601690437
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2907078174
Short name T93
Test name
Test status
Simulation time 479724344 ps
CPU time 12.6 seconds
Started Mar 02 12:40:56 PM PST 24
Finished Mar 02 12:41:09 PM PST 24
Peak memory 214524 kb
Host smart-484cd25f-b231-4c52-8c98-86a051db8e7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2907078174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2907078174
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3051209546
Short name T890
Test name
Test status
Simulation time 868888460 ps
CPU time 17.75 seconds
Started Mar 02 12:40:59 PM PST 24
Finished Mar 02 12:41:16 PM PST 24
Peak memory 208072 kb
Host smart-d89446ff-de4b-4e29-b179-6d302dc2bc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051209546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3051209546
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3246624198
Short name T1050
Test name
Test status
Simulation time 238644832 ps
CPU time 6.89 seconds
Started Mar 02 12:40:57 PM PST 24
Finished Mar 02 12:41:04 PM PST 24
Peak memory 209692 kb
Host smart-81be7e9f-82f9-4e11-b058-d15cdbbcb791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246624198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3246624198
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3307340846
Short name T616
Test name
Test status
Simulation time 35535690 ps
CPU time 2.34 seconds
Started Mar 02 12:40:56 PM PST 24
Finished Mar 02 12:40:59 PM PST 24
Peak memory 208512 kb
Host smart-75110bfe-ceee-4027-a1de-de70adde3cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307340846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3307340846
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2659542269
Short name T816
Test name
Test status
Simulation time 175506123 ps
CPU time 3.04 seconds
Started Mar 02 12:40:58 PM PST 24
Finished Mar 02 12:41:01 PM PST 24
Peak memory 207104 kb
Host smart-fd91f9bf-d973-4e5e-bf0b-df85a0e813a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659542269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2659542269
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.870768831
Short name T1020
Test name
Test status
Simulation time 1476910550 ps
CPU time 5.8 seconds
Started Mar 02 12:40:55 PM PST 24
Finished Mar 02 12:41:01 PM PST 24
Peak memory 208584 kb
Host smart-3abc70e9-c2f6-496a-9386-92b2a25b5421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870768831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.870768831
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1689021594
Short name T759
Test name
Test status
Simulation time 48514332 ps
CPU time 1.95 seconds
Started Mar 02 12:40:58 PM PST 24
Finished Mar 02 12:41:00 PM PST 24
Peak memory 207468 kb
Host smart-443ed910-f862-43af-a2a7-4998f78138d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689021594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1689021594
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2310706449
Short name T1034
Test name
Test status
Simulation time 200325645 ps
CPU time 3 seconds
Started Mar 02 12:40:56 PM PST 24
Finished Mar 02 12:40:59 PM PST 24
Peak memory 206964 kb
Host smart-69a39eb1-f1d4-4c8c-8cb5-f5fa98ec30e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310706449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2310706449
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.438256514
Short name T1062
Test name
Test status
Simulation time 747447430 ps
CPU time 18.52 seconds
Started Mar 02 12:41:00 PM PST 24
Finished Mar 02 12:41:18 PM PST 24
Peak memory 207936 kb
Host smart-872abdbb-8d8c-41f7-b7b3-6038ba03e5b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438256514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.438256514
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.4154146482
Short name T935
Test name
Test status
Simulation time 2688320719 ps
CPU time 8.29 seconds
Started Mar 02 12:40:59 PM PST 24
Finished Mar 02 12:41:08 PM PST 24
Peak memory 214372 kb
Host smart-222bea3e-c001-4800-bd36-45650dba2323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154146482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.4154146482
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1439362756
Short name T1004
Test name
Test status
Simulation time 1062823688 ps
CPU time 3.89 seconds
Started Mar 02 12:40:58 PM PST 24
Finished Mar 02 12:41:02 PM PST 24
Peak memory 206096 kb
Host smart-5611e3a5-97f1-4508-add6-f9e840534c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439362756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1439362756
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.927118250
Short name T634
Test name
Test status
Simulation time 512225913 ps
CPU time 8.87 seconds
Started Mar 02 12:40:58 PM PST 24
Finished Mar 02 12:41:07 PM PST 24
Peak memory 220080 kb
Host smart-e0867edd-10c7-4b48-99df-2ca61a2469a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927118250 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.927118250
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.786107746
Short name T753
Test name
Test status
Simulation time 1398387955 ps
CPU time 12.43 seconds
Started Mar 02 12:40:55 PM PST 24
Finished Mar 02 12:41:07 PM PST 24
Peak memory 209176 kb
Host smart-da48767f-3f75-4e5c-90f7-63d786ebb9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786107746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.786107746
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.644260345
Short name T961
Test name
Test status
Simulation time 543241726 ps
CPU time 3.31 seconds
Started Mar 02 12:40:56 PM PST 24
Finished Mar 02 12:41:00 PM PST 24
Peak memory 210136 kb
Host smart-6523b309-33d4-40e4-a96d-df0109417c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644260345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.644260345
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3012386119
Short name T546
Test name
Test status
Simulation time 21816526 ps
CPU time 0.69 seconds
Started Mar 02 12:40:58 PM PST 24
Finished Mar 02 12:40:59 PM PST 24
Peak memory 205796 kb
Host smart-02e2c75f-1ae6-44e1-9f37-afd133638970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012386119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3012386119
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1600794358
Short name T1061
Test name
Test status
Simulation time 4508557120 ps
CPU time 53.61 seconds
Started Mar 02 12:40:59 PM PST 24
Finished Mar 02 12:41:53 PM PST 24
Peak memory 214308 kb
Host smart-336a405b-37ce-4d19-b5da-a3d3cda203ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1600794358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1600794358
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3369873843
Short name T851
Test name
Test status
Simulation time 418359551 ps
CPU time 8.71 seconds
Started Mar 02 12:41:00 PM PST 24
Finished Mar 02 12:41:09 PM PST 24
Peak memory 214316 kb
Host smart-67b0994b-3134-442b-80f1-a51ae4b8daa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369873843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3369873843
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3957804208
Short name T312
Test name
Test status
Simulation time 207901590 ps
CPU time 2.12 seconds
Started Mar 02 12:40:59 PM PST 24
Finished Mar 02 12:41:02 PM PST 24
Peak memory 207896 kb
Host smart-909a33fc-a008-4e18-b98f-4e7514e7a19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957804208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3957804208
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.381791907
Short name T248
Test name
Test status
Simulation time 986179783 ps
CPU time 10.03 seconds
Started Mar 02 12:41:06 PM PST 24
Finished Mar 02 12:41:16 PM PST 24
Peak memory 211316 kb
Host smart-6a6be1de-0506-4529-8640-acfd65fce849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381791907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.381791907
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3162357726
Short name T734
Test name
Test status
Simulation time 263271591 ps
CPU time 3.51 seconds
Started Mar 02 12:40:54 PM PST 24
Finished Mar 02 12:40:58 PM PST 24
Peak memory 216232 kb
Host smart-0d4e930e-5351-4052-a817-134def014347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162357726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3162357726
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3626595431
Short name T912
Test name
Test status
Simulation time 372304524 ps
CPU time 10.03 seconds
Started Mar 02 12:40:58 PM PST 24
Finished Mar 02 12:41:08 PM PST 24
Peak memory 209132 kb
Host smart-9266acd0-cfff-42f1-a6ce-075723d64ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626595431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3626595431
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1833995957
Short name T343
Test name
Test status
Simulation time 76069193 ps
CPU time 3.29 seconds
Started Mar 02 12:40:57 PM PST 24
Finished Mar 02 12:41:01 PM PST 24
Peak memory 206604 kb
Host smart-207dacf0-028a-496d-b3ee-288dd0b50543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1833995957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1833995957
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3477524015
Short name T849
Test name
Test status
Simulation time 625936796 ps
CPU time 3.24 seconds
Started Mar 02 12:40:58 PM PST 24
Finished Mar 02 12:41:02 PM PST 24
Peak memory 206728 kb
Host smart-035943ac-8d88-4276-b0d6-0a3f2683a5a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477524015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3477524015
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2148761947
Short name T862
Test name
Test status
Simulation time 2108173240 ps
CPU time 24.2 seconds
Started Mar 02 12:40:55 PM PST 24
Finished Mar 02 12:41:19 PM PST 24
Peak memory 208084 kb
Host smart-15e402b6-ca7e-477b-ac4d-313ccba9d5c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148761947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2148761947
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1433446294
Short name T657
Test name
Test status
Simulation time 268529769 ps
CPU time 7.41 seconds
Started Mar 02 12:40:57 PM PST 24
Finished Mar 02 12:41:04 PM PST 24
Peak memory 206924 kb
Host smart-724aaf48-e5d3-44cf-85c5-d1080926011d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433446294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1433446294
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2247182103
Short name T397
Test name
Test status
Simulation time 514942359 ps
CPU time 2.01 seconds
Started Mar 02 12:40:58 PM PST 24
Finished Mar 02 12:41:00 PM PST 24
Peak memory 209088 kb
Host smart-9bea9ef2-db82-4772-bff7-78c6a95c7c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247182103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2247182103
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2198694864
Short name T565
Test name
Test status
Simulation time 2811289213 ps
CPU time 16.21 seconds
Started Mar 02 12:40:54 PM PST 24
Finished Mar 02 12:41:11 PM PST 24
Peak memory 208236 kb
Host smart-411fd3c3-ee92-4c1f-b6b8-da2590b684ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198694864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2198694864
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.3426951790
Short name T721
Test name
Test status
Simulation time 246663884 ps
CPU time 10.19 seconds
Started Mar 02 12:40:55 PM PST 24
Finished Mar 02 12:41:05 PM PST 24
Peak memory 223688 kb
Host smart-3a6e7579-a2f8-45d3-b897-6ead5f8cc26c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426951790 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.3426951790
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.4037031976
Short name T281
Test name
Test status
Simulation time 1640943793 ps
CPU time 31.93 seconds
Started Mar 02 12:40:56 PM PST 24
Finished Mar 02 12:41:28 PM PST 24
Peak memory 209404 kb
Host smart-7ee8c1eb-0553-4b15-96eb-1f8216cc5445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037031976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.4037031976
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.253067151
Short name T990
Test name
Test status
Simulation time 146256157 ps
CPU time 1.38 seconds
Started Mar 02 12:40:56 PM PST 24
Finished Mar 02 12:40:58 PM PST 24
Peak memory 209648 kb
Host smart-6dd13f88-5571-45ae-adb2-69345061ba3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253067151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.253067151
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.845349871
Short name T572
Test name
Test status
Simulation time 16174950 ps
CPU time 0.8 seconds
Started Mar 02 12:40:55 PM PST 24
Finished Mar 02 12:40:56 PM PST 24
Peak memory 205872 kb
Host smart-d0ba01c8-0674-42d6-bde1-bc5c83797428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845349871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.845349871
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1586864250
Short name T403
Test name
Test status
Simulation time 10537807838 ps
CPU time 133.23 seconds
Started Mar 02 12:40:59 PM PST 24
Finished Mar 02 12:43:13 PM PST 24
Peak memory 215060 kb
Host smart-597531a1-3f42-4c1c-a318-8f74f8fa5582
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1586864250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1586864250
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.668859967
Short name T244
Test name
Test status
Simulation time 133416822 ps
CPU time 3.73 seconds
Started Mar 02 12:40:58 PM PST 24
Finished Mar 02 12:41:02 PM PST 24
Peak memory 214288 kb
Host smart-00079ad8-b885-4b1d-8e61-cec98d808b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668859967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.668859967
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2025934272
Short name T310
Test name
Test status
Simulation time 645227371 ps
CPU time 9.29 seconds
Started Mar 02 12:40:56 PM PST 24
Finished Mar 02 12:41:05 PM PST 24
Peak memory 214316 kb
Host smart-6e7e8930-00fb-4548-8cc2-17c56069bfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025934272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2025934272
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1744848181
Short name T196
Test name
Test status
Simulation time 2962997230 ps
CPU time 26 seconds
Started Mar 02 12:41:05 PM PST 24
Finished Mar 02 12:41:31 PM PST 24
Peak memory 209388 kb
Host smart-23089566-43dc-4fa6-9561-fe23576f067d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744848181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1744848181
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2177852646
Short name T800
Test name
Test status
Simulation time 279833168 ps
CPU time 10.1 seconds
Started Mar 02 12:40:58 PM PST 24
Finished Mar 02 12:41:08 PM PST 24
Peak memory 208292 kb
Host smart-99b3fb8e-ae0f-45d6-84ca-b02b80041771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177852646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2177852646
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.174962846
Short name T573
Test name
Test status
Simulation time 100469707 ps
CPU time 2.64 seconds
Started Mar 02 12:40:58 PM PST 24
Finished Mar 02 12:41:01 PM PST 24
Peak memory 206800 kb
Host smart-e0325f72-e3e4-428d-902e-1e05562f1fed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174962846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.174962846
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.736889506
Short name T920
Test name
Test status
Simulation time 93046933 ps
CPU time 2.76 seconds
Started Mar 02 12:40:57 PM PST 24
Finished Mar 02 12:40:59 PM PST 24
Peak memory 206764 kb
Host smart-d2f7c2f4-6208-4101-9c15-165e87631318
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736889506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.736889506
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2312848743
Short name T190
Test name
Test status
Simulation time 170802508 ps
CPU time 2.72 seconds
Started Mar 02 12:40:59 PM PST 24
Finished Mar 02 12:41:01 PM PST 24
Peak memory 206692 kb
Host smart-4ec0ee17-8119-4b63-988d-be12bd4e1adb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312848743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2312848743
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1694669759
Short name T72
Test name
Test status
Simulation time 74227831 ps
CPU time 3.27 seconds
Started Mar 02 12:40:58 PM PST 24
Finished Mar 02 12:41:01 PM PST 24
Peak memory 207908 kb
Host smart-03902810-599d-467f-8372-a1afa71567cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694669759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1694669759
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3513101974
Short name T260
Test name
Test status
Simulation time 281918825 ps
CPU time 3.44 seconds
Started Mar 02 12:40:58 PM PST 24
Finished Mar 02 12:41:02 PM PST 24
Peak memory 208032 kb
Host smart-14b6d306-58c8-4e70-b24f-5d8094bd633c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513101974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3513101974
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.570693193
Short name T649
Test name
Test status
Simulation time 523384853 ps
CPU time 7.07 seconds
Started Mar 02 12:40:59 PM PST 24
Finished Mar 02 12:41:06 PM PST 24
Peak memory 208664 kb
Host smart-2edec0d2-d05b-46a8-8c8f-ed24aab37bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570693193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.570693193
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3867499450
Short name T64
Test name
Test status
Simulation time 1544265460 ps
CPU time 37.39 seconds
Started Mar 02 12:41:02 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 222392 kb
Host smart-fc0b1870-0ab1-4513-8ff4-1aece893e9cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867499450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3867499450
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.178452012
Short name T111
Test name
Test status
Simulation time 615801326 ps
CPU time 4.77 seconds
Started Mar 02 12:41:01 PM PST 24
Finished Mar 02 12:41:06 PM PST 24
Peak memory 220064 kb
Host smart-bf43c48e-2d9b-44fb-86dc-a34147290002
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178452012 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.178452012
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.453991351
Short name T1043
Test name
Test status
Simulation time 496680908 ps
CPU time 16.26 seconds
Started Mar 02 12:41:09 PM PST 24
Finished Mar 02 12:41:25 PM PST 24
Peak memory 214364 kb
Host smart-a1e49e33-4e0c-4a64-9d27-1da39024dad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453991351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.453991351
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2743005022
Short name T736
Test name
Test status
Simulation time 127833356 ps
CPU time 1.61 seconds
Started Mar 02 12:40:59 PM PST 24
Finished Mar 02 12:41:00 PM PST 24
Peak memory 210080 kb
Host smart-1787c720-d952-40b2-ab83-f6d7f98f4c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743005022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2743005022
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2790697576
Short name T15
Test name
Test status
Simulation time 43175252 ps
CPU time 0.79 seconds
Started Mar 02 12:41:05 PM PST 24
Finished Mar 02 12:41:06 PM PST 24
Peak memory 205880 kb
Host smart-c8f7284c-bf2d-4fd7-b96b-63d76c38ab52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790697576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2790697576
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3609561613
Short name T243
Test name
Test status
Simulation time 125169781 ps
CPU time 4.41 seconds
Started Mar 02 12:41:02 PM PST 24
Finished Mar 02 12:41:06 PM PST 24
Peak memory 215128 kb
Host smart-12863c09-8248-4d4e-bd46-1c58a4d42061
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3609561613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3609561613
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3617689258
Short name T725
Test name
Test status
Simulation time 64754832 ps
CPU time 2.85 seconds
Started Mar 02 12:41:01 PM PST 24
Finished Mar 02 12:41:03 PM PST 24
Peak memory 208208 kb
Host smart-1d058d3c-0d62-48e5-b980-96fb88437de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617689258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3617689258
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3137472071
Short name T267
Test name
Test status
Simulation time 234693171 ps
CPU time 7.5 seconds
Started Mar 02 12:41:00 PM PST 24
Finished Mar 02 12:41:08 PM PST 24
Peak memory 210104 kb
Host smart-f70a472c-ebe9-44f3-a217-9dc3ea65d5f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137472071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3137472071
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2899790804
Short name T38
Test name
Test status
Simulation time 122673313 ps
CPU time 4.2 seconds
Started Mar 02 12:41:02 PM PST 24
Finished Mar 02 12:41:07 PM PST 24
Peak memory 209448 kb
Host smart-f49e4fc1-53e6-4efd-9bfd-be6d0b7476ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899790804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2899790804
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2994732323
Short name T692
Test name
Test status
Simulation time 147043516 ps
CPU time 5.17 seconds
Started Mar 02 12:40:59 PM PST 24
Finished Mar 02 12:41:04 PM PST 24
Peak memory 207764 kb
Host smart-2020d397-5bc6-4552-bf60-24256d68f2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994732323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2994732323
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1760142985
Short name T729
Test name
Test status
Simulation time 111952127 ps
CPU time 4.15 seconds
Started Mar 02 12:41:07 PM PST 24
Finished Mar 02 12:41:12 PM PST 24
Peak memory 206680 kb
Host smart-b979e6c4-916c-4809-8772-69c9a1a89dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760142985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1760142985
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2693511844
Short name T703
Test name
Test status
Simulation time 3017152864 ps
CPU time 37.98 seconds
Started Mar 02 12:41:06 PM PST 24
Finished Mar 02 12:41:44 PM PST 24
Peak memory 208996 kb
Host smart-b7acff3c-43b4-45de-bd18-b0904c723a75
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693511844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2693511844
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1784897780
Short name T810
Test name
Test status
Simulation time 1617559833 ps
CPU time 6.01 seconds
Started Mar 02 12:41:06 PM PST 24
Finished Mar 02 12:41:12 PM PST 24
Peak memory 208832 kb
Host smart-10fa79da-8298-4fd4-a0a0-d74588d9686e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784897780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1784897780
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3202214021
Short name T893
Test name
Test status
Simulation time 26061352 ps
CPU time 1.82 seconds
Started Mar 02 12:41:09 PM PST 24
Finished Mar 02 12:41:11 PM PST 24
Peak memory 209640 kb
Host smart-dfab3177-3dc0-46c4-83b9-23248c01bcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202214021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3202214021
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3209079467
Short name T985
Test name
Test status
Simulation time 306024670 ps
CPU time 7.98 seconds
Started Mar 02 12:41:02 PM PST 24
Finished Mar 02 12:41:10 PM PST 24
Peak memory 206712 kb
Host smart-2c6ae9a8-8ed0-40bb-ac74-2cd41558e162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209079467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3209079467
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.840062460
Short name T1002
Test name
Test status
Simulation time 38078428 ps
CPU time 3.33 seconds
Started Mar 02 12:41:06 PM PST 24
Finished Mar 02 12:41:09 PM PST 24
Peak memory 221288 kb
Host smart-f087cf77-e659-44ef-b06b-a9e0f8fd71bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840062460 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.840062460
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.4028624043
Short name T297
Test name
Test status
Simulation time 4798097541 ps
CPU time 49.06 seconds
Started Mar 02 12:41:00 PM PST 24
Finished Mar 02 12:41:49 PM PST 24
Peak memory 209108 kb
Host smart-ea7d89a8-b6ea-4845-b011-885d71a72710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028624043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.4028624043
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.691628487
Short name T52
Test name
Test status
Simulation time 3784730051 ps
CPU time 25.74 seconds
Started Mar 02 12:41:06 PM PST 24
Finished Mar 02 12:41:32 PM PST 24
Peak memory 211684 kb
Host smart-38138f69-3050-4bb3-9502-2d4223febc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691628487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.691628487
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3592276367
Short name T892
Test name
Test status
Simulation time 26145388 ps
CPU time 0.81 seconds
Started Mar 02 12:41:09 PM PST 24
Finished Mar 02 12:41:10 PM PST 24
Peak memory 205868 kb
Host smart-d47a9591-c297-4b4b-8298-ee96ca03d9d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592276367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3592276367
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3504693843
Short name T245
Test name
Test status
Simulation time 39821832 ps
CPU time 2.62 seconds
Started Mar 02 12:41:06 PM PST 24
Finished Mar 02 12:41:08 PM PST 24
Peak memory 209360 kb
Host smart-9d1e0157-9fc1-4d8e-9d4e-5334bce8fc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504693843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3504693843
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2728727045
Short name T332
Test name
Test status
Simulation time 8684479304 ps
CPU time 84.17 seconds
Started Mar 02 12:41:10 PM PST 24
Finished Mar 02 12:42:34 PM PST 24
Peak memory 214376 kb
Host smart-6b7d6b40-45a5-4a14-8196-2682597493d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728727045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2728727045
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1693767403
Short name T50
Test name
Test status
Simulation time 264070623 ps
CPU time 4.21 seconds
Started Mar 02 12:41:04 PM PST 24
Finished Mar 02 12:41:09 PM PST 24
Peak memory 211944 kb
Host smart-6435ef35-f5a6-45d6-9cda-e9940a1b36e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693767403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1693767403
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1187153506
Short name T55
Test name
Test status
Simulation time 577036896 ps
CPU time 3.69 seconds
Started Mar 02 12:41:09 PM PST 24
Finished Mar 02 12:41:13 PM PST 24
Peak memory 220372 kb
Host smart-f96a834b-d44d-455e-bfa3-9ea57f7eae63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187153506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1187153506
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3331069127
Short name T369
Test name
Test status
Simulation time 4142067983 ps
CPU time 32.26 seconds
Started Mar 02 12:41:07 PM PST 24
Finished Mar 02 12:41:40 PM PST 24
Peak memory 214300 kb
Host smart-6518388d-2f71-4cd5-beb3-1353431fe231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331069127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3331069127
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2062419836
Short name T888
Test name
Test status
Simulation time 36176798 ps
CPU time 2.29 seconds
Started Mar 02 12:41:10 PM PST 24
Finished Mar 02 12:41:12 PM PST 24
Peak memory 206776 kb
Host smart-d8ebebec-ca38-44b0-ab18-dd1c417f1883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062419836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2062419836
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3470741799
Short name T983
Test name
Test status
Simulation time 372287837 ps
CPU time 5.49 seconds
Started Mar 02 12:41:07 PM PST 24
Finished Mar 02 12:41:13 PM PST 24
Peak memory 208788 kb
Host smart-92c39215-e2e9-430a-90c7-129c95db4335
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470741799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3470741799
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1693171982
Short name T1025
Test name
Test status
Simulation time 115265430 ps
CPU time 4.61 seconds
Started Mar 02 12:41:07 PM PST 24
Finished Mar 02 12:41:12 PM PST 24
Peak memory 208988 kb
Host smart-570fc11a-ea26-4764-96a1-afadf95da1c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693171982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1693171982
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1101603297
Short name T882
Test name
Test status
Simulation time 1591108211 ps
CPU time 39.45 seconds
Started Mar 02 12:41:07 PM PST 24
Finished Mar 02 12:41:47 PM PST 24
Peak memory 208300 kb
Host smart-dc987d21-7529-4619-a8c5-1b8a2adc1b4b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101603297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1101603297
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2911134320
Short name T653
Test name
Test status
Simulation time 26131941 ps
CPU time 1.66 seconds
Started Mar 02 12:41:05 PM PST 24
Finished Mar 02 12:41:07 PM PST 24
Peak memory 207912 kb
Host smart-9009eceb-7794-45be-8635-113a81dd78f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911134320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2911134320
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.4099682042
Short name T571
Test name
Test status
Simulation time 855670215 ps
CPU time 5.63 seconds
Started Mar 02 12:41:09 PM PST 24
Finished Mar 02 12:41:14 PM PST 24
Peak memory 208664 kb
Host smart-54dcf3ec-7782-48fa-aa44-4890cf6b94b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099682042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.4099682042
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1228556895
Short name T991
Test name
Test status
Simulation time 1627581183 ps
CPU time 3.18 seconds
Started Mar 02 12:41:08 PM PST 24
Finished Mar 02 12:41:11 PM PST 24
Peak memory 222552 kb
Host smart-6136727e-47b9-419e-a0eb-34bbf5e66300
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228556895 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1228556895
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2318433952
Short name T615
Test name
Test status
Simulation time 77893143 ps
CPU time 2.84 seconds
Started Mar 02 12:41:09 PM PST 24
Finished Mar 02 12:41:12 PM PST 24
Peak memory 218552 kb
Host smart-1a249684-18db-41dd-8c2d-3e806517ec41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318433952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2318433952
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.544598217
Short name T390
Test name
Test status
Simulation time 113715901 ps
CPU time 2.18 seconds
Started Mar 02 12:41:07 PM PST 24
Finished Mar 02 12:41:10 PM PST 24
Peak memory 209992 kb
Host smart-9acb7941-e65c-4d31-967b-71f8b0d869ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544598217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.544598217
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.530644719
Short name T676
Test name
Test status
Simulation time 47634900 ps
CPU time 0.81 seconds
Started Mar 02 12:41:11 PM PST 24
Finished Mar 02 12:41:12 PM PST 24
Peak memory 205876 kb
Host smart-96bff1d2-41b5-49f9-ac5d-e6e4cbdae58d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530644719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.530644719
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.4141910607
Short name T838
Test name
Test status
Simulation time 32258459 ps
CPU time 1.93 seconds
Started Mar 02 12:41:08 PM PST 24
Finished Mar 02 12:41:10 PM PST 24
Peak memory 214308 kb
Host smart-86dddc6e-0bda-4fc2-9bb2-f646cbc49451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141910607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4141910607
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.69050964
Short name T20
Test name
Test status
Simulation time 106457838 ps
CPU time 4.97 seconds
Started Mar 02 12:41:05 PM PST 24
Finished Mar 02 12:41:10 PM PST 24
Peak memory 214304 kb
Host smart-cb8a3dd7-623e-4c2a-b33e-9e7d54ceefb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69050964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.69050964
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2764992328
Short name T685
Test name
Test status
Simulation time 51336913 ps
CPU time 2.41 seconds
Started Mar 02 12:41:11 PM PST 24
Finished Mar 02 12:41:14 PM PST 24
Peak memory 219612 kb
Host smart-8c150dd8-3207-40d2-8841-472e39b31b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764992328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2764992328
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3420660324
Short name T588
Test name
Test status
Simulation time 90220852 ps
CPU time 4.8 seconds
Started Mar 02 12:41:06 PM PST 24
Finished Mar 02 12:41:11 PM PST 24
Peak memory 214244 kb
Host smart-9e106cc2-60e1-4292-87d0-d47ff937994e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420660324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3420660324
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.4040644174
Short name T919
Test name
Test status
Simulation time 105184687 ps
CPU time 4.1 seconds
Started Mar 02 12:41:07 PM PST 24
Finished Mar 02 12:41:12 PM PST 24
Peak memory 208080 kb
Host smart-512a1c72-d6b0-4490-9ad4-c0ec2acbc020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040644174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.4040644174
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3892171301
Short name T307
Test name
Test status
Simulation time 2560033323 ps
CPU time 67.24 seconds
Started Mar 02 12:41:09 PM PST 24
Finished Mar 02 12:42:16 PM PST 24
Peak memory 209108 kb
Host smart-8d83e5fe-f31c-4bf4-a949-a9da103c18d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892171301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3892171301
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.999837991
Short name T1006
Test name
Test status
Simulation time 1137348227 ps
CPU time 4.76 seconds
Started Mar 02 12:41:06 PM PST 24
Finished Mar 02 12:41:11 PM PST 24
Peak memory 207400 kb
Host smart-8e06d684-74e4-4418-9456-8f0652553d40
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999837991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.999837991
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1684261332
Short name T827
Test name
Test status
Simulation time 114901009 ps
CPU time 2.96 seconds
Started Mar 02 12:41:08 PM PST 24
Finished Mar 02 12:41:11 PM PST 24
Peak memory 206872 kb
Host smart-5744dd3c-2c76-4dd4-9b3f-f5d21dcfb6a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684261332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1684261332
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.4228576827
Short name T956
Test name
Test status
Simulation time 51421873 ps
CPU time 2.31 seconds
Started Mar 02 12:41:09 PM PST 24
Finished Mar 02 12:41:12 PM PST 24
Peak memory 207868 kb
Host smart-49bd6d8f-161c-46c3-825e-678e99754c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228576827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.4228576827
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1541064023
Short name T542
Test name
Test status
Simulation time 82156317 ps
CPU time 3.32 seconds
Started Mar 02 12:41:07 PM PST 24
Finished Mar 02 12:41:11 PM PST 24
Peak memory 208272 kb
Host smart-080f0bf5-0488-4b71-b015-4b9ae028b9d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541064023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1541064023
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.729118943
Short name T200
Test name
Test status
Simulation time 564130461 ps
CPU time 10.39 seconds
Started Mar 02 12:41:10 PM PST 24
Finished Mar 02 12:41:21 PM PST 24
Peak memory 222608 kb
Host smart-d4021d08-1456-4542-a9c4-01912c435c7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729118943 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.729118943
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.485913140
Short name T597
Test name
Test status
Simulation time 1165393479 ps
CPU time 5.84 seconds
Started Mar 02 12:41:08 PM PST 24
Finished Mar 02 12:41:14 PM PST 24
Peak memory 214216 kb
Host smart-f6507daf-63a9-4059-a9e4-9fd123bf8ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485913140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.485913140
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1041307310
Short name T707
Test name
Test status
Simulation time 236725784 ps
CPU time 6.3 seconds
Started Mar 02 12:41:09 PM PST 24
Finished Mar 02 12:41:16 PM PST 24
Peak memory 211124 kb
Host smart-88c9a9e4-3549-4739-a00a-babaf8cdc0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041307310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1041307310
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.957914969
Short name T409
Test name
Test status
Simulation time 61189597 ps
CPU time 0.83 seconds
Started Mar 02 12:39:50 PM PST 24
Finished Mar 02 12:39:51 PM PST 24
Peak memory 205824 kb
Host smart-de73c954-2df0-4bcf-a4fd-3c1d36b69526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957914969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.957914969
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.347768597
Short name T982
Test name
Test status
Simulation time 257259659 ps
CPU time 5.35 seconds
Started Mar 02 12:39:48 PM PST 24
Finished Mar 02 12:39:54 PM PST 24
Peak memory 220992 kb
Host smart-cb035866-0bff-43e7-af39-1587ebcb2a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347768597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.347768597
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1127032538
Short name T858
Test name
Test status
Simulation time 52583491 ps
CPU time 1.43 seconds
Started Mar 02 12:39:47 PM PST 24
Finished Mar 02 12:39:49 PM PST 24
Peak memory 207792 kb
Host smart-2ee1d287-c461-4478-86c4-9dd0fd6da27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127032538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1127032538
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3727269456
Short name T984
Test name
Test status
Simulation time 645349622 ps
CPU time 8.09 seconds
Started Mar 02 12:39:49 PM PST 24
Finished Mar 02 12:39:57 PM PST 24
Peak memory 222348 kb
Host smart-2d09f38b-f698-4555-babc-975c9a0d9511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727269456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3727269456
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.4123147753
Short name T41
Test name
Test status
Simulation time 153008760 ps
CPU time 2.71 seconds
Started Mar 02 12:39:51 PM PST 24
Finished Mar 02 12:39:54 PM PST 24
Peak memory 214312 kb
Host smart-9b49b1ab-f902-4189-baa3-a1aa55013cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123147753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.4123147753
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2783309434
Short name T875
Test name
Test status
Simulation time 747509299 ps
CPU time 20.27 seconds
Started Mar 02 12:39:44 PM PST 24
Finished Mar 02 12:40:05 PM PST 24
Peak memory 222420 kb
Host smart-e665f072-955f-45c0-af44-ea384f081fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783309434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2783309434
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2054050814
Short name T89
Test name
Test status
Simulation time 679780640 ps
CPU time 10.95 seconds
Started Mar 02 12:39:52 PM PST 24
Finished Mar 02 12:40:03 PM PST 24
Peak memory 230748 kb
Host smart-8880e5a4-2b05-4a34-aa9e-57cd73c22b34
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054050814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2054050814
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1000064004
Short name T1059
Test name
Test status
Simulation time 148234465 ps
CPU time 2.16 seconds
Started Mar 02 12:39:43 PM PST 24
Finished Mar 02 12:39:46 PM PST 24
Peak memory 206800 kb
Host smart-11e75334-bbc9-4e7a-a29c-9f235dac02d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000064004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1000064004
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.342613760
Short name T963
Test name
Test status
Simulation time 151130575 ps
CPU time 3.06 seconds
Started Mar 02 12:39:45 PM PST 24
Finished Mar 02 12:39:49 PM PST 24
Peak memory 207420 kb
Host smart-150f76bd-968d-4dd3-bea7-76879b73fbc8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342613760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.342613760
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.291487201
Short name T901
Test name
Test status
Simulation time 251239148 ps
CPU time 3.25 seconds
Started Mar 02 12:39:45 PM PST 24
Finished Mar 02 12:39:48 PM PST 24
Peak memory 206776 kb
Host smart-0c0d2b6d-5d33-492b-8c1d-0d1b2d74286e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291487201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.291487201
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3912627705
Short name T673
Test name
Test status
Simulation time 13541647 ps
CPU time 1.3 seconds
Started Mar 02 12:39:45 PM PST 24
Finished Mar 02 12:39:47 PM PST 24
Peak memory 206936 kb
Host smart-df9a48c4-df12-440c-8e8d-24380ce9a84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912627705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3912627705
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3685292732
Short name T612
Test name
Test status
Simulation time 102324685 ps
CPU time 3.88 seconds
Started Mar 02 12:39:46 PM PST 24
Finished Mar 02 12:39:50 PM PST 24
Peak memory 206792 kb
Host smart-ddfc8b9e-65b5-45f1-8258-333240d0e8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685292732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3685292732
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1835356064
Short name T195
Test name
Test status
Simulation time 338509445 ps
CPU time 2.78 seconds
Started Mar 02 12:39:46 PM PST 24
Finished Mar 02 12:39:49 PM PST 24
Peak memory 222544 kb
Host smart-da57dcb8-40ab-46b9-837d-32cfe6f8b427
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835356064 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1835356064
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.4047827094
Short name T1065
Test name
Test status
Simulation time 154041306 ps
CPU time 5.66 seconds
Started Mar 02 12:39:45 PM PST 24
Finished Mar 02 12:39:51 PM PST 24
Peak memory 219472 kb
Host smart-9d81757c-cace-49f8-b129-53b460f704e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047827094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.4047827094
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.739804935
Short name T73
Test name
Test status
Simulation time 23050303 ps
CPU time 0.87 seconds
Started Mar 02 12:41:17 PM PST 24
Finished Mar 02 12:41:18 PM PST 24
Peak memory 205784 kb
Host smart-d7909bfb-e133-4e33-b58f-6e50cf52a213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739804935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.739804935
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.718737330
Short name T37
Test name
Test status
Simulation time 257137803 ps
CPU time 2.37 seconds
Started Mar 02 12:41:19 PM PST 24
Finished Mar 02 12:41:21 PM PST 24
Peak memory 209812 kb
Host smart-1fe3002a-3dc1-4a80-95e5-955dbe667ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718737330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.718737330
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3403600063
Short name T399
Test name
Test status
Simulation time 3180609443 ps
CPU time 13.48 seconds
Started Mar 02 12:41:29 PM PST 24
Finished Mar 02 12:41:43 PM PST 24
Peak memory 214388 kb
Host smart-013de930-d1a9-40bf-bbb1-d74f03bdba81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403600063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3403600063
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3567130173
Short name T880
Test name
Test status
Simulation time 918831277 ps
CPU time 10.53 seconds
Started Mar 02 12:41:20 PM PST 24
Finished Mar 02 12:41:31 PM PST 24
Peak memory 219508 kb
Host smart-1ee50852-dc27-4eb7-ae89-9e09ed915a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567130173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3567130173
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1950049645
Short name T269
Test name
Test status
Simulation time 415719261 ps
CPU time 8.62 seconds
Started Mar 02 12:41:27 PM PST 24
Finished Mar 02 12:41:36 PM PST 24
Peak memory 222392 kb
Host smart-0b1e94af-470f-40f6-b6e6-f3da96fb7523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950049645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1950049645
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2757102904
Short name T774
Test name
Test status
Simulation time 627528950 ps
CPU time 5.8 seconds
Started Mar 02 12:41:27 PM PST 24
Finished Mar 02 12:41:33 PM PST 24
Peak memory 219992 kb
Host smart-da179496-c1b6-4cd2-a1df-9d92bd368e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757102904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2757102904
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1931092972
Short name T598
Test name
Test status
Simulation time 186882977 ps
CPU time 3.19 seconds
Started Mar 02 12:41:16 PM PST 24
Finished Mar 02 12:41:20 PM PST 24
Peak memory 217884 kb
Host smart-d7ebedf6-173e-458e-a131-caedd769b57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931092972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1931092972
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2761030257
Short name T305
Test name
Test status
Simulation time 273804191 ps
CPU time 4.34 seconds
Started Mar 02 12:41:10 PM PST 24
Finished Mar 02 12:41:14 PM PST 24
Peak memory 208712 kb
Host smart-08a42e99-8c3f-481d-ba38-718990e32fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761030257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2761030257
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1459509157
Short name T608
Test name
Test status
Simulation time 199157351 ps
CPU time 6.84 seconds
Started Mar 02 12:41:27 PM PST 24
Finished Mar 02 12:41:34 PM PST 24
Peak memory 207888 kb
Host smart-27719cf3-d7ce-4171-b900-7888974322e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459509157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1459509157
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.4050800308
Short name T336
Test name
Test status
Simulation time 161532168 ps
CPU time 2.66 seconds
Started Mar 02 12:41:17 PM PST 24
Finished Mar 02 12:41:20 PM PST 24
Peak memory 207616 kb
Host smart-01829034-400f-4e0d-a553-0ecf64c7c27b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050800308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4050800308
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1624362960
Short name T747
Test name
Test status
Simulation time 413354095 ps
CPU time 4.84 seconds
Started Mar 02 12:41:22 PM PST 24
Finished Mar 02 12:41:27 PM PST 24
Peak memory 208576 kb
Host smart-33c5cb03-d3b4-4d14-affb-de91dde68e8d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624362960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1624362960
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2590317820
Short name T593
Test name
Test status
Simulation time 59539153 ps
CPU time 1.68 seconds
Started Mar 02 12:41:15 PM PST 24
Finished Mar 02 12:41:18 PM PST 24
Peak memory 208820 kb
Host smart-6dacec46-5629-4267-95c0-392994cfba97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590317820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2590317820
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2588849230
Short name T723
Test name
Test status
Simulation time 1209659830 ps
CPU time 14.41 seconds
Started Mar 02 12:41:10 PM PST 24
Finished Mar 02 12:41:25 PM PST 24
Peak memory 207872 kb
Host smart-72991ecd-64bd-466e-9b4f-c28a18a412b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588849230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2588849230
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.136993141
Short name T642
Test name
Test status
Simulation time 252786365 ps
CPU time 8.01 seconds
Started Mar 02 12:41:19 PM PST 24
Finished Mar 02 12:41:27 PM PST 24
Peak memory 222588 kb
Host smart-43aa38ce-5d28-4040-bc3b-d51129690ce2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136993141 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.136993141
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1919798171
Short name T1019
Test name
Test status
Simulation time 242633490 ps
CPU time 5.87 seconds
Started Mar 02 12:41:27 PM PST 24
Finished Mar 02 12:41:33 PM PST 24
Peak memory 208964 kb
Host smart-ebd17f43-45ee-4303-8aa6-5ab78b83bd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919798171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1919798171
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3056766522
Short name T970
Test name
Test status
Simulation time 4373797263 ps
CPU time 21.35 seconds
Started Mar 02 12:41:18 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 222660 kb
Host smart-6a3d54d1-1e8a-4200-83a4-5521f23b259b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056766522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3056766522
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3734761559
Short name T547
Test name
Test status
Simulation time 34501617 ps
CPU time 0.88 seconds
Started Mar 02 12:41:30 PM PST 24
Finished Mar 02 12:41:31 PM PST 24
Peak memory 205892 kb
Host smart-98224ab1-4594-4d2d-b8b2-3470e68862b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734761559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3734761559
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2083374739
Short name T273
Test name
Test status
Simulation time 1499575534 ps
CPU time 6.45 seconds
Started Mar 02 12:41:16 PM PST 24
Finished Mar 02 12:41:23 PM PST 24
Peak memory 214308 kb
Host smart-c64be949-aad1-4400-a8b0-df613690c294
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2083374739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2083374739
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1792470343
Short name T934
Test name
Test status
Simulation time 708236943 ps
CPU time 8.62 seconds
Started Mar 02 12:41:15 PM PST 24
Finished Mar 02 12:41:25 PM PST 24
Peak memory 222648 kb
Host smart-00f43df1-10f4-44a9-bbe5-e42c4bd6e51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792470343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1792470343
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1764869671
Short name T640
Test name
Test status
Simulation time 239577229 ps
CPU time 3.11 seconds
Started Mar 02 12:41:27 PM PST 24
Finished Mar 02 12:41:30 PM PST 24
Peak memory 206828 kb
Host smart-f494767b-c86b-460b-ba62-4c42ea027c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764869671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1764869671
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3143374169
Short name T252
Test name
Test status
Simulation time 272565109 ps
CPU time 5.67 seconds
Started Mar 02 12:41:30 PM PST 24
Finished Mar 02 12:41:36 PM PST 24
Peak memory 214184 kb
Host smart-65984c45-e9bd-4001-9e71-4679be46c73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143374169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3143374169
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1658212241
Short name T265
Test name
Test status
Simulation time 1287680688 ps
CPU time 9.59 seconds
Started Mar 02 12:41:27 PM PST 24
Finished Mar 02 12:41:36 PM PST 24
Peak memory 222448 kb
Host smart-798cbbd0-e8a6-44df-b7d4-ac9af2ba43b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658212241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1658212241
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3558649882
Short name T1033
Test name
Test status
Simulation time 493657222 ps
CPU time 3.39 seconds
Started Mar 02 12:41:19 PM PST 24
Finished Mar 02 12:41:22 PM PST 24
Peak memory 222552 kb
Host smart-0f20fc61-3e82-4fdb-aca4-6e6ae26faebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558649882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3558649882
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2593762359
Short name T967
Test name
Test status
Simulation time 814783455 ps
CPU time 11.64 seconds
Started Mar 02 12:41:18 PM PST 24
Finished Mar 02 12:41:29 PM PST 24
Peak memory 209716 kb
Host smart-0b217f9a-cb38-4b28-a384-e0d72fbee0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593762359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2593762359
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3507146006
Short name T1041
Test name
Test status
Simulation time 522529333 ps
CPU time 10.25 seconds
Started Mar 02 12:41:22 PM PST 24
Finished Mar 02 12:41:32 PM PST 24
Peak memory 207912 kb
Host smart-c884122b-f070-494f-ad13-ad5ade3b13ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507146006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3507146006
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3060423615
Short name T630
Test name
Test status
Simulation time 307924993 ps
CPU time 1.73 seconds
Started Mar 02 12:41:15 PM PST 24
Finished Mar 02 12:41:18 PM PST 24
Peak memory 206792 kb
Host smart-a067c085-0a17-40b4-936a-080d91cc1141
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060423615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3060423615
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2569582863
Short name T981
Test name
Test status
Simulation time 31939628 ps
CPU time 2.4 seconds
Started Mar 02 12:41:16 PM PST 24
Finished Mar 02 12:41:19 PM PST 24
Peak memory 207548 kb
Host smart-e8009a8f-fe0f-479c-9757-6202c0cfb211
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569582863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2569582863
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2230910971
Short name T918
Test name
Test status
Simulation time 911123607 ps
CPU time 7.47 seconds
Started Mar 02 12:41:30 PM PST 24
Finished Mar 02 12:41:38 PM PST 24
Peak memory 207888 kb
Host smart-2558c568-fefe-45ad-a4f2-c85a9bc5c371
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230910971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2230910971
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1287173446
Short name T742
Test name
Test status
Simulation time 330031435 ps
CPU time 3.93 seconds
Started Mar 02 12:41:30 PM PST 24
Finished Mar 02 12:41:34 PM PST 24
Peak memory 218268 kb
Host smart-d2a51044-6127-4deb-801c-7294daffa882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287173446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1287173446
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3023072979
Short name T557
Test name
Test status
Simulation time 22577111 ps
CPU time 1.89 seconds
Started Mar 02 12:41:22 PM PST 24
Finished Mar 02 12:41:24 PM PST 24
Peak memory 208496 kb
Host smart-22dcbd73-b4f9-46b2-be98-c754addf2aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023072979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3023072979
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3396022187
Short name T191
Test name
Test status
Simulation time 1084186170 ps
CPU time 22.72 seconds
Started Mar 02 12:41:22 PM PST 24
Finished Mar 02 12:41:45 PM PST 24
Peak memory 216308 kb
Host smart-36edbd98-3307-474b-87bd-3054b388b184
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396022187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3396022187
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2551155535
Short name T826
Test name
Test status
Simulation time 305720288 ps
CPU time 17.1 seconds
Started Mar 02 12:41:27 PM PST 24
Finished Mar 02 12:41:44 PM PST 24
Peak memory 222540 kb
Host smart-e266b5ff-0262-4c8d-9a02-d8679d46015b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551155535 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2551155535
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1647778064
Short name T899
Test name
Test status
Simulation time 202616036 ps
CPU time 3.65 seconds
Started Mar 02 12:41:18 PM PST 24
Finished Mar 02 12:41:21 PM PST 24
Peak memory 207792 kb
Host smart-e31bc2dd-4daf-4f35-afb8-30bd8d121f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647778064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1647778064
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.4102122982
Short name T145
Test name
Test status
Simulation time 305030691 ps
CPU time 10.74 seconds
Started Mar 02 12:41:22 PM PST 24
Finished Mar 02 12:41:33 PM PST 24
Peak memory 210948 kb
Host smart-855bff13-cbd2-4862-beaa-742a79d3112e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102122982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.4102122982
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1255015574
Short name T793
Test name
Test status
Simulation time 25547217 ps
CPU time 0.81 seconds
Started Mar 02 12:41:33 PM PST 24
Finished Mar 02 12:41:35 PM PST 24
Peak memory 205796 kb
Host smart-90fd7be7-4bdb-4c57-872f-30760f8de7e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255015574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1255015574
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1523196897
Short name T257
Test name
Test status
Simulation time 1686085187 ps
CPU time 85.45 seconds
Started Mar 02 12:41:23 PM PST 24
Finished Mar 02 12:42:49 PM PST 24
Peak memory 214164 kb
Host smart-38a957db-0c20-444d-a722-5ef7d0412a9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1523196897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1523196897
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1805196839
Short name T13
Test name
Test status
Simulation time 166636918 ps
CPU time 3.55 seconds
Started Mar 02 12:41:29 PM PST 24
Finished Mar 02 12:41:33 PM PST 24
Peak memory 209320 kb
Host smart-734811ab-b3ca-40a9-94fc-08460970815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1805196839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1805196839
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3225927716
Short name T765
Test name
Test status
Simulation time 91829526 ps
CPU time 1.78 seconds
Started Mar 02 12:41:30 PM PST 24
Finished Mar 02 12:41:32 PM PST 24
Peak memory 207024 kb
Host smart-317be5e9-c958-41d4-8eb0-41bf6530ed75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225927716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3225927716
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3685026326
Short name T78
Test name
Test status
Simulation time 186338904 ps
CPU time 4.39 seconds
Started Mar 02 12:41:24 PM PST 24
Finished Mar 02 12:41:28 PM PST 24
Peak memory 219100 kb
Host smart-ca5ec664-a46a-4e60-9554-44ae0dfe6aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685026326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3685026326
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.930911
Short name T59
Test name
Test status
Simulation time 45902831 ps
CPU time 2.77 seconds
Started Mar 02 12:41:24 PM PST 24
Finished Mar 02 12:41:27 PM PST 24
Peak memory 209332 kb
Host smart-d806e0a7-4bfb-4d42-b8b8-9b9e008e1ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.930911
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2106263894
Short name T1047
Test name
Test status
Simulation time 273278566 ps
CPU time 5.04 seconds
Started Mar 02 12:41:23 PM PST 24
Finished Mar 02 12:41:28 PM PST 24
Peak memory 208940 kb
Host smart-12657ebd-f5a9-4b58-bde1-ce9a4c745456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106263894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2106263894
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2071225415
Short name T820
Test name
Test status
Simulation time 2978633363 ps
CPU time 33.63 seconds
Started Mar 02 12:41:30 PM PST 24
Finished Mar 02 12:42:04 PM PST 24
Peak memory 208024 kb
Host smart-e218a5a3-8926-4e4f-8c96-41cb9660ef9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071225415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2071225415
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1410543169
Short name T299
Test name
Test status
Simulation time 556087685 ps
CPU time 2.93 seconds
Started Mar 02 12:41:23 PM PST 24
Finished Mar 02 12:41:26 PM PST 24
Peak memory 206964 kb
Host smart-c11af732-5ea4-41fc-abeb-88a66e0a112e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410543169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1410543169
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1011113356
Short name T180
Test name
Test status
Simulation time 994176865 ps
CPU time 22.24 seconds
Started Mar 02 12:41:23 PM PST 24
Finished Mar 02 12:41:46 PM PST 24
Peak memory 208880 kb
Host smart-f0f19b7e-97ac-4f00-a146-ae1b79dcac4c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011113356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1011113356
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.707270499
Short name T564
Test name
Test status
Simulation time 100943464 ps
CPU time 2.8 seconds
Started Mar 02 12:41:23 PM PST 24
Finished Mar 02 12:41:26 PM PST 24
Peak memory 206892 kb
Host smart-9111f41b-4667-4b5d-b74c-69a58ee420e4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707270499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.707270499
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3465865436
Short name T879
Test name
Test status
Simulation time 191611404 ps
CPU time 3.06 seconds
Started Mar 02 12:41:24 PM PST 24
Finished Mar 02 12:41:27 PM PST 24
Peak memory 218316 kb
Host smart-bc33922a-31e8-412c-9a4b-45e279deee7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465865436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3465865436
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.4012681743
Short name T709
Test name
Test status
Simulation time 142649996 ps
CPU time 2.53 seconds
Started Mar 02 12:41:23 PM PST 24
Finished Mar 02 12:41:25 PM PST 24
Peak memory 207408 kb
Host smart-76ba07b2-ab0c-4e01-98c6-807bf70ae3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4012681743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.4012681743
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.1203418568
Short name T379
Test name
Test status
Simulation time 709252758 ps
CPU time 5.85 seconds
Started Mar 02 12:41:33 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 222416 kb
Host smart-4f3ffeeb-991b-4784-a8dd-717c2e6ba0a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203418568 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.1203418568
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2966582918
Short name T1030
Test name
Test status
Simulation time 1022196357 ps
CPU time 6.25 seconds
Started Mar 02 12:41:29 PM PST 24
Finished Mar 02 12:41:35 PM PST 24
Peak memory 217996 kb
Host smart-dd937983-b499-4a0c-8e15-cb26ef8e3113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966582918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2966582918
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1944341027
Short name T1060
Test name
Test status
Simulation time 66667525 ps
CPU time 2.61 seconds
Started Mar 02 12:41:24 PM PST 24
Finished Mar 02 12:41:27 PM PST 24
Peak memory 210276 kb
Host smart-4d07a294-1851-4c42-8706-02ebabe24839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944341027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1944341027
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3178453777
Short name T591
Test name
Test status
Simulation time 49253520 ps
CPU time 0.73 seconds
Started Mar 02 12:41:35 PM PST 24
Finished Mar 02 12:41:36 PM PST 24
Peak memory 205864 kb
Host smart-5b06db21-cc1f-49ed-a32c-f9d59d7395fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178453777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3178453777
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.931466375
Short name T987
Test name
Test status
Simulation time 369283494 ps
CPU time 10.44 seconds
Started Mar 02 12:41:34 PM PST 24
Finished Mar 02 12:41:44 PM PST 24
Peak memory 222552 kb
Host smart-bcff36dd-0233-489a-8b18-b561589c762e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=931466375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.931466375
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3689810951
Short name T614
Test name
Test status
Simulation time 649453711 ps
CPU time 4.74 seconds
Started Mar 02 12:41:36 PM PST 24
Finished Mar 02 12:41:41 PM PST 24
Peak memory 222836 kb
Host smart-1a041bfb-0856-4466-9214-6396c6f55879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689810951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3689810951
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2667708123
Short name T389
Test name
Test status
Simulation time 600854125 ps
CPU time 3.41 seconds
Started Mar 02 12:41:35 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 207172 kb
Host smart-8e12a97f-3834-4068-9b2e-8fc4c26eeb01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667708123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2667708123
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.662132983
Short name T894
Test name
Test status
Simulation time 516647943 ps
CPU time 3.83 seconds
Started Mar 02 12:41:36 PM PST 24
Finished Mar 02 12:41:40 PM PST 24
Peak memory 209488 kb
Host smart-11c4f99a-ab77-4d78-8e50-2f3d062e48c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662132983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.662132983
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2064502776
Short name T853
Test name
Test status
Simulation time 1571780918 ps
CPU time 43.77 seconds
Started Mar 02 12:41:32 PM PST 24
Finished Mar 02 12:42:16 PM PST 24
Peak memory 222424 kb
Host smart-af30acc9-ae74-43af-be55-05e1ea7c9b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064502776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2064502776
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1899996412
Short name T832
Test name
Test status
Simulation time 95652661 ps
CPU time 3.4 seconds
Started Mar 02 12:41:35 PM PST 24
Finished Mar 02 12:41:38 PM PST 24
Peak memory 216556 kb
Host smart-f3d6a415-ff9a-425b-bd8c-04a309ebc300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899996412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1899996412
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2547426564
Short name T296
Test name
Test status
Simulation time 2755030307 ps
CPU time 36.37 seconds
Started Mar 02 12:41:36 PM PST 24
Finished Mar 02 12:42:12 PM PST 24
Peak memory 207968 kb
Host smart-21a61d40-c5fb-41f3-89f1-1c423e2796e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547426564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2547426564
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3449361246
Short name T629
Test name
Test status
Simulation time 51942100 ps
CPU time 2.56 seconds
Started Mar 02 12:41:37 PM PST 24
Finished Mar 02 12:41:40 PM PST 24
Peak memory 208004 kb
Host smart-26d902f1-dd51-430f-8dd5-42368ab34525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449361246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3449361246
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.262684350
Short name T680
Test name
Test status
Simulation time 53270265 ps
CPU time 2.95 seconds
Started Mar 02 12:41:35 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 208400 kb
Host smart-7f59c4f7-036d-4436-9331-ecb65cf9af81
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262684350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.262684350
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.4204144548
Short name T600
Test name
Test status
Simulation time 106792126 ps
CPU time 4.09 seconds
Started Mar 02 12:41:34 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 208448 kb
Host smart-14f84e97-51c1-4987-9ce5-78225aa91072
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204144548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.4204144548
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.737507303
Short name T1007
Test name
Test status
Simulation time 291889233 ps
CPU time 4.19 seconds
Started Mar 02 12:41:35 PM PST 24
Finished Mar 02 12:41:40 PM PST 24
Peak memory 208972 kb
Host smart-30b2f241-d326-42e2-a43c-5ac1216cf2f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737507303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.737507303
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1887532867
Short name T776
Test name
Test status
Simulation time 793807140 ps
CPU time 5.61 seconds
Started Mar 02 12:41:34 PM PST 24
Finished Mar 02 12:41:40 PM PST 24
Peak memory 207892 kb
Host smart-1c532f94-3cc9-496e-8812-37550d823da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887532867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1887532867
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2851847424
Short name T666
Test name
Test status
Simulation time 323042742 ps
CPU time 3.05 seconds
Started Mar 02 12:41:35 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 208420 kb
Host smart-5cc7cbea-cd5b-4a99-b1f8-b27acd7605cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851847424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2851847424
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1078805184
Short name T989
Test name
Test status
Simulation time 2315073337 ps
CPU time 41.78 seconds
Started Mar 02 12:41:33 PM PST 24
Finished Mar 02 12:42:15 PM PST 24
Peak memory 222508 kb
Host smart-7a6d93f8-e156-4ea5-b968-18b0e5e43d4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078805184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1078805184
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.575227474
Short name T109
Test name
Test status
Simulation time 164317690 ps
CPU time 4 seconds
Started Mar 02 12:41:34 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 222500 kb
Host smart-10d653d8-bbec-483e-bc15-46e78b14a0f2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575227474 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.575227474
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.386372302
Short name T1051
Test name
Test status
Simulation time 654012275 ps
CPU time 6.4 seconds
Started Mar 02 12:41:32 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 218368 kb
Host smart-b3bf30d8-d282-46b8-9024-a4b286501ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386372302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.386372302
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.622599660
Short name T916
Test name
Test status
Simulation time 128525814 ps
CPU time 2.94 seconds
Started Mar 02 12:41:35 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 210296 kb
Host smart-0d282562-d0af-4fbe-aaab-06d17c6c0e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622599660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.622599660
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2394704005
Short name T997
Test name
Test status
Simulation time 13607034 ps
CPU time 0.94 seconds
Started Mar 02 12:41:35 PM PST 24
Finished Mar 02 12:41:37 PM PST 24
Peak memory 205868 kb
Host smart-26ff3217-3dc6-4611-92cf-0db3179205ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394704005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2394704005
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2899096013
Short name T104
Test name
Test status
Simulation time 248158503 ps
CPU time 13.3 seconds
Started Mar 02 12:41:33 PM PST 24
Finished Mar 02 12:41:46 PM PST 24
Peak memory 215716 kb
Host smart-518dc5ff-996b-4bec-822c-8c64e06b03f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2899096013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2899096013
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3345698812
Short name T70
Test name
Test status
Simulation time 567039116 ps
CPU time 3.7 seconds
Started Mar 02 12:41:44 PM PST 24
Finished Mar 02 12:41:48 PM PST 24
Peak memory 210408 kb
Host smart-fa6524bc-3ff5-4eb2-9bb3-a45df4853441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345698812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3345698812
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1864560672
Short name T752
Test name
Test status
Simulation time 197456390 ps
CPU time 4.52 seconds
Started Mar 02 12:41:34 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 220676 kb
Host smart-df32a14d-4e25-4085-8dd9-f44ab2988686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864560672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1864560672
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3196003554
Short name T266
Test name
Test status
Simulation time 78111625 ps
CPU time 2.96 seconds
Started Mar 02 12:41:36 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 211552 kb
Host smart-eec2cadd-6f27-450d-b751-18bc70d265b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196003554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3196003554
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.722311896
Short name T613
Test name
Test status
Simulation time 1148737692 ps
CPU time 3.34 seconds
Started Mar 02 12:41:33 PM PST 24
Finished Mar 02 12:41:37 PM PST 24
Peak memory 209300 kb
Host smart-8b29deaa-7918-4077-bf16-2cdb3a536b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722311896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.722311896
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1070148758
Short name T408
Test name
Test status
Simulation time 489107759 ps
CPU time 4.62 seconds
Started Mar 02 12:41:37 PM PST 24
Finished Mar 02 12:41:42 PM PST 24
Peak memory 209944 kb
Host smart-60bdf828-b3ad-43a7-81b3-c81049f93975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070148758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1070148758
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.280698060
Short name T711
Test name
Test status
Simulation time 3579690911 ps
CPU time 37.25 seconds
Started Mar 02 12:41:36 PM PST 24
Finished Mar 02 12:42:13 PM PST 24
Peak memory 208796 kb
Host smart-81fa6a8f-bb2d-48ce-808c-559b61bf417b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280698060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.280698060
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2857503789
Short name T829
Test name
Test status
Simulation time 23620515 ps
CPU time 1.88 seconds
Started Mar 02 12:41:34 PM PST 24
Finished Mar 02 12:41:37 PM PST 24
Peak memory 206868 kb
Host smart-526d64c5-476b-4763-8c61-2c57d9b7532e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857503789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2857503789
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.486719198
Short name T316
Test name
Test status
Simulation time 464941959 ps
CPU time 4.36 seconds
Started Mar 02 12:41:34 PM PST 24
Finished Mar 02 12:41:38 PM PST 24
Peak memory 206924 kb
Host smart-9f4ce4c1-5c38-4e5c-8aa4-42296a70291b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486719198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.486719198
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.4156025820
Short name T691
Test name
Test status
Simulation time 114523245 ps
CPU time 3.17 seconds
Started Mar 02 12:41:34 PM PST 24
Finished Mar 02 12:41:38 PM PST 24
Peak memory 206832 kb
Host smart-410e47f7-2954-4560-9efd-8aa197577b31
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156025820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4156025820
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.4136212712
Short name T756
Test name
Test status
Simulation time 69884595 ps
CPU time 3.36 seconds
Started Mar 02 12:41:36 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 208752 kb
Host smart-bea172f5-673d-4a0e-8394-d9d26500992b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136212712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.4136212712
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1391652184
Short name T743
Test name
Test status
Simulation time 41287847 ps
CPU time 2.28 seconds
Started Mar 02 12:41:36 PM PST 24
Finished Mar 02 12:41:38 PM PST 24
Peak memory 207216 kb
Host smart-ad99a9e4-cdfe-4dae-b604-6197cffde4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391652184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1391652184
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2293464146
Short name T262
Test name
Test status
Simulation time 4466730095 ps
CPU time 42.96 seconds
Started Mar 02 12:41:35 PM PST 24
Finished Mar 02 12:42:18 PM PST 24
Peak memory 216380 kb
Host smart-a1a0df70-7393-43b4-a821-1e5a0c317f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293464146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2293464146
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2971116788
Short name T887
Test name
Test status
Simulation time 474459471 ps
CPU time 6.32 seconds
Started Mar 02 12:41:39 PM PST 24
Finished Mar 02 12:41:46 PM PST 24
Peak memory 222100 kb
Host smart-f1e32d63-ba2b-47b1-a78e-3cb09ca2544c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971116788 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2971116788
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1740236755
Short name T581
Test name
Test status
Simulation time 416252990 ps
CPU time 3.25 seconds
Started Mar 02 12:41:35 PM PST 24
Finished Mar 02 12:41:38 PM PST 24
Peak memory 207836 kb
Host smart-a83fc90a-fb82-495c-9c29-a9b6f0e70258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740236755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1740236755
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1307874662
Short name T380
Test name
Test status
Simulation time 53742288 ps
CPU time 2.69 seconds
Started Mar 02 12:41:36 PM PST 24
Finished Mar 02 12:41:39 PM PST 24
Peak memory 210136 kb
Host smart-3859986f-8557-4d15-90d5-ef07c622aac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307874662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1307874662
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1071993848
Short name T728
Test name
Test status
Simulation time 15582711 ps
CPU time 0.74 seconds
Started Mar 02 12:41:46 PM PST 24
Finished Mar 02 12:41:48 PM PST 24
Peak memory 205880 kb
Host smart-358d944a-d3de-471d-92f7-07d816b02174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071993848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1071993848
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.494125901
Short name T291
Test name
Test status
Simulation time 116927299 ps
CPU time 4.4 seconds
Started Mar 02 12:41:47 PM PST 24
Finished Mar 02 12:41:53 PM PST 24
Peak memory 214936 kb
Host smart-fdafddb3-7262-4cf5-8cb5-fcdffaca3ec1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=494125901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.494125901
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.4114965945
Short name T818
Test name
Test status
Simulation time 1505758985 ps
CPU time 3.82 seconds
Started Mar 02 12:41:47 PM PST 24
Finished Mar 02 12:41:52 PM PST 24
Peak memory 218180 kb
Host smart-568d20b7-47a7-45fe-a0de-9999d5079b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114965945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.4114965945
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2350257334
Short name T815
Test name
Test status
Simulation time 508846384 ps
CPU time 4.59 seconds
Started Mar 02 12:41:47 PM PST 24
Finished Mar 02 12:41:53 PM PST 24
Peak memory 207760 kb
Host smart-7a4afc22-4fcd-4069-9894-74716f6c7d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350257334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2350257334
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.666270940
Short name T301
Test name
Test status
Simulation time 62138279 ps
CPU time 3.57 seconds
Started Mar 02 12:41:44 PM PST 24
Finished Mar 02 12:41:49 PM PST 24
Peak memory 210660 kb
Host smart-27039a4f-e49f-425f-8a76-a7f6145970b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666270940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.666270940
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2883972920
Short name T661
Test name
Test status
Simulation time 319994123 ps
CPU time 3.55 seconds
Started Mar 02 12:41:49 PM PST 24
Finished Mar 02 12:41:53 PM PST 24
Peak memory 220112 kb
Host smart-f17b37f4-9a3e-4c34-ab80-79299b66fcf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883972920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2883972920
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1128333152
Short name T242
Test name
Test status
Simulation time 155017406 ps
CPU time 5.9 seconds
Started Mar 02 12:41:34 PM PST 24
Finished Mar 02 12:41:41 PM PST 24
Peak memory 209768 kb
Host smart-0efa9c32-ac9a-4173-a276-4bffadd094e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128333152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1128333152
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1513853887
Short name T693
Test name
Test status
Simulation time 503870306 ps
CPU time 5.77 seconds
Started Mar 02 12:41:35 PM PST 24
Finished Mar 02 12:41:41 PM PST 24
Peak memory 207164 kb
Host smart-7d3875de-8848-4748-9e66-d0929322a68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513853887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1513853887
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3046526749
Short name T886
Test name
Test status
Simulation time 40305479 ps
CPU time 2.67 seconds
Started Mar 02 12:41:36 PM PST 24
Finished Mar 02 12:41:38 PM PST 24
Peak memory 208436 kb
Host smart-c3512c3a-915c-42c6-87a1-60434a282f1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046526749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3046526749
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1857771023
Short name T705
Test name
Test status
Simulation time 122488889 ps
CPU time 4.96 seconds
Started Mar 02 12:41:32 PM PST 24
Finished Mar 02 12:41:38 PM PST 24
Peak memory 208584 kb
Host smart-c58ac2c5-3b14-423d-8214-b980a5a89461
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857771023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1857771023
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3441728990
Short name T933
Test name
Test status
Simulation time 1964017146 ps
CPU time 39.74 seconds
Started Mar 02 12:41:36 PM PST 24
Finished Mar 02 12:42:16 PM PST 24
Peak memory 208104 kb
Host smart-01b0e75c-21ff-4197-b267-5d2acedb72c3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441728990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3441728990
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.186108567
Short name T256
Test name
Test status
Simulation time 330234779 ps
CPU time 2.75 seconds
Started Mar 02 12:41:46 PM PST 24
Finished Mar 02 12:41:51 PM PST 24
Peak memory 210136 kb
Host smart-8ced59de-8a6d-4a51-a881-6df79044a1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186108567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.186108567
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2372285786
Short name T662
Test name
Test status
Simulation time 260651931 ps
CPU time 3.05 seconds
Started Mar 02 12:41:44 PM PST 24
Finished Mar 02 12:41:47 PM PST 24
Peak memory 208824 kb
Host smart-4eabe419-75d0-4aca-8149-1c60ef215c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372285786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2372285786
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1717122700
Short name T954
Test name
Test status
Simulation time 219298443 ps
CPU time 11.23 seconds
Started Mar 02 12:41:47 PM PST 24
Finished Mar 02 12:42:00 PM PST 24
Peak memory 215064 kb
Host smart-ff1d5f72-fea1-4c8b-9376-5751470dac2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717122700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1717122700
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1742055378
Short name T1036
Test name
Test status
Simulation time 267077194 ps
CPU time 2.3 seconds
Started Mar 02 12:41:48 PM PST 24
Finished Mar 02 12:41:51 PM PST 24
Peak memory 222556 kb
Host smart-bd609c6a-5183-40e3-a7bc-8aac2303dc43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742055378 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1742055378
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1123193577
Short name T757
Test name
Test status
Simulation time 1758656724 ps
CPU time 55.07 seconds
Started Mar 02 12:41:44 PM PST 24
Finished Mar 02 12:42:41 PM PST 24
Peak memory 214184 kb
Host smart-334f1233-ed1a-425c-9c6c-ea1c82af35ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123193577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1123193577
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.104662150
Short name T596
Test name
Test status
Simulation time 535488367 ps
CPU time 3.41 seconds
Started Mar 02 12:41:46 PM PST 24
Finished Mar 02 12:41:51 PM PST 24
Peak memory 210088 kb
Host smart-f528f631-0f60-414e-9208-88bd49dc8b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104662150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.104662150
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3330773329
Short name T643
Test name
Test status
Simulation time 33637306 ps
CPU time 0.76 seconds
Started Mar 02 12:41:44 PM PST 24
Finished Mar 02 12:41:46 PM PST 24
Peak memory 205792 kb
Host smart-70cd308d-57f5-4c17-817d-2defab283e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330773329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3330773329
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3989974755
Short name T103
Test name
Test status
Simulation time 166981475 ps
CPU time 8.99 seconds
Started Mar 02 12:41:45 PM PST 24
Finished Mar 02 12:41:55 PM PST 24
Peak memory 214748 kb
Host smart-40d32120-24c5-4ac8-a888-83e325c6f349
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3989974755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3989974755
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1506021525
Short name T924
Test name
Test status
Simulation time 729737088 ps
CPU time 9.37 seconds
Started Mar 02 12:41:45 PM PST 24
Finished Mar 02 12:41:56 PM PST 24
Peak memory 209444 kb
Host smart-10af2b41-b258-4426-94f4-599220f5e977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506021525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1506021525
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3957037876
Short name T733
Test name
Test status
Simulation time 3165286291 ps
CPU time 20.08 seconds
Started Mar 02 12:41:44 PM PST 24
Finished Mar 02 12:42:06 PM PST 24
Peak memory 209024 kb
Host smart-84157c7b-f6a4-438e-a90c-c56f5e1cef13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957037876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3957037876
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1992149048
Short name T14
Test name
Test status
Simulation time 1364777052 ps
CPU time 40.81 seconds
Started Mar 02 12:41:48 PM PST 24
Finished Mar 02 12:42:29 PM PST 24
Peak memory 209060 kb
Host smart-49a9b270-aeb8-41e4-a14e-417c3ba6f485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992149048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1992149048
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.875828532
Short name T1039
Test name
Test status
Simulation time 683225182 ps
CPU time 17.59 seconds
Started Mar 02 12:41:46 PM PST 24
Finished Mar 02 12:42:04 PM PST 24
Peak memory 222624 kb
Host smart-b2e29b69-4368-4aef-8edf-db5097dbffa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875828532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.875828532
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3480336669
Short name T953
Test name
Test status
Simulation time 116985215 ps
CPU time 2.55 seconds
Started Mar 02 12:41:48 PM PST 24
Finished Mar 02 12:41:51 PM PST 24
Peak memory 214312 kb
Host smart-e43e1829-9e75-4b93-ab81-2429c20fd736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480336669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3480336669
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3469872255
Short name T848
Test name
Test status
Simulation time 2301601972 ps
CPU time 14.27 seconds
Started Mar 02 12:41:43 PM PST 24
Finished Mar 02 12:41:57 PM PST 24
Peak memory 208096 kb
Host smart-0400614c-bc9a-4dad-a471-33ad6dddd7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469872255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3469872255
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1669921687
Short name T631
Test name
Test status
Simulation time 353598642 ps
CPU time 1.82 seconds
Started Mar 02 12:41:44 PM PST 24
Finished Mar 02 12:41:48 PM PST 24
Peak memory 206672 kb
Host smart-95fdad29-832c-44d4-a0c5-ca9b3e7295f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669921687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1669921687
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1299370026
Short name T872
Test name
Test status
Simulation time 207895979 ps
CPU time 3.71 seconds
Started Mar 02 12:41:46 PM PST 24
Finished Mar 02 12:41:51 PM PST 24
Peak memory 206816 kb
Host smart-8185c00f-50b0-463b-a029-5f38b4661167
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299370026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1299370026
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.894327979
Short name T284
Test name
Test status
Simulation time 1958691020 ps
CPU time 47.53 seconds
Started Mar 02 12:41:47 PM PST 24
Finished Mar 02 12:42:36 PM PST 24
Peak memory 207824 kb
Host smart-bf877cbc-9838-4e86-9cfc-0d24169e3991
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894327979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.894327979
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.859364876
Short name T740
Test name
Test status
Simulation time 734497606 ps
CPU time 7.77 seconds
Started Mar 02 12:41:47 PM PST 24
Finished Mar 02 12:41:56 PM PST 24
Peak memory 208432 kb
Host smart-91b4a6fd-b723-41f5-9bb1-a1d7e7df1184
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859364876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.859364876
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.946688042
Short name T605
Test name
Test status
Simulation time 74100301 ps
CPU time 2.18 seconds
Started Mar 02 12:41:44 PM PST 24
Finished Mar 02 12:41:48 PM PST 24
Peak memory 208836 kb
Host smart-ee536af7-0252-4588-a0ef-eaa9f5543926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946688042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.946688042
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.4254493290
Short name T411
Test name
Test status
Simulation time 24929396 ps
CPU time 1.79 seconds
Started Mar 02 12:41:45 PM PST 24
Finished Mar 02 12:41:48 PM PST 24
Peak memory 207072 kb
Host smart-f0233564-8698-4e91-aad8-5add6c92f9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254493290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.4254493290
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2430795338
Short name T377
Test name
Test status
Simulation time 506504188 ps
CPU time 13.12 seconds
Started Mar 02 12:41:47 PM PST 24
Finished Mar 02 12:42:01 PM PST 24
Peak memory 216944 kb
Host smart-38d0ce5f-b685-4803-9e4f-2c285ac0a934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430795338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2430795338
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.2803799302
Short name T668
Test name
Test status
Simulation time 225223248 ps
CPU time 3.73 seconds
Started Mar 02 12:41:45 PM PST 24
Finished Mar 02 12:41:50 PM PST 24
Peak memory 222632 kb
Host smart-5401b86a-ad24-473a-bc59-3b181311e626
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803799302 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.2803799302
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2538345511
Short name T811
Test name
Test status
Simulation time 338988000 ps
CPU time 7.32 seconds
Started Mar 02 12:41:46 PM PST 24
Finished Mar 02 12:41:54 PM PST 24
Peak memory 209824 kb
Host smart-1c9b731e-366b-484c-9cf0-cbfd87363849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538345511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2538345511
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.959074396
Short name T654
Test name
Test status
Simulation time 32122619 ps
CPU time 1.79 seconds
Started Mar 02 12:41:48 PM PST 24
Finished Mar 02 12:41:50 PM PST 24
Peak memory 209612 kb
Host smart-91c0011b-3cfa-4561-a080-3d8d9c65596f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959074396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.959074396
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.896732895
Short name T802
Test name
Test status
Simulation time 54108915 ps
CPU time 0.93 seconds
Started Mar 02 12:41:49 PM PST 24
Finished Mar 02 12:41:50 PM PST 24
Peak memory 206080 kb
Host smart-92e1a479-045a-4580-b98f-4e025bbf46f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896732895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.896732895
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1878772149
Short name T804
Test name
Test status
Simulation time 261339508 ps
CPU time 2.58 seconds
Started Mar 02 12:41:47 PM PST 24
Finished Mar 02 12:41:51 PM PST 24
Peak memory 209504 kb
Host smart-e0eaacfc-dcb9-477c-8e33-4f0cbbf421bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878772149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1878772149
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3261963439
Short name T823
Test name
Test status
Simulation time 42686888 ps
CPU time 2.7 seconds
Started Mar 02 12:41:46 PM PST 24
Finished Mar 02 12:41:50 PM PST 24
Peak memory 207596 kb
Host smart-dfb4bfad-ce0a-409c-b15a-4e2e003a71ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261963439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3261963439
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3714727017
Short name T376
Test name
Test status
Simulation time 6291364983 ps
CPU time 38.85 seconds
Started Mar 02 12:41:46 PM PST 24
Finished Mar 02 12:42:26 PM PST 24
Peak memory 222452 kb
Host smart-bc0e5b9b-1683-4513-a1c1-d7e64b0d6cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714727017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3714727017
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3233948196
Short name T577
Test name
Test status
Simulation time 410796611 ps
CPU time 12.23 seconds
Started Mar 02 12:41:48 PM PST 24
Finished Mar 02 12:42:01 PM PST 24
Peak memory 214216 kb
Host smart-6493cb4a-c804-488f-b158-d665b073ea62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233948196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3233948196
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.482980346
Short name T841
Test name
Test status
Simulation time 102990084 ps
CPU time 2.99 seconds
Started Mar 02 12:41:50 PM PST 24
Finished Mar 02 12:41:53 PM PST 24
Peak memory 208668 kb
Host smart-7d473e47-473d-40fc-a7e8-3c8644256e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482980346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.482980346
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1599937721
Short name T324
Test name
Test status
Simulation time 444269242 ps
CPU time 4.88 seconds
Started Mar 02 12:41:48 PM PST 24
Finished Mar 02 12:41:54 PM PST 24
Peak memory 214264 kb
Host smart-1ae63f32-4530-47dc-a0ad-ac435d3465f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599937721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1599937721
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2134996054
Short name T355
Test name
Test status
Simulation time 212367296 ps
CPU time 6.51 seconds
Started Mar 02 12:41:46 PM PST 24
Finished Mar 02 12:41:54 PM PST 24
Peak memory 207900 kb
Host smart-463b5356-6271-411e-a485-37d7fd0ce2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134996054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2134996054
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1832777867
Short name T1046
Test name
Test status
Simulation time 32565263 ps
CPU time 2.3 seconds
Started Mar 02 12:41:46 PM PST 24
Finished Mar 02 12:41:50 PM PST 24
Peak memory 206860 kb
Host smart-316b652a-b9d7-480b-9495-b46ee8034e2a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832777867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1832777867
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3012673618
Short name T165
Test name
Test status
Simulation time 137641331 ps
CPU time 2.56 seconds
Started Mar 02 12:41:45 PM PST 24
Finished Mar 02 12:41:49 PM PST 24
Peak memory 207224 kb
Host smart-549edf03-adae-42e7-8057-2345a34d3198
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012673618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3012673618
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2566354484
Short name T889
Test name
Test status
Simulation time 5957164670 ps
CPU time 44.36 seconds
Started Mar 02 12:41:46 PM PST 24
Finished Mar 02 12:42:32 PM PST 24
Peak memory 208816 kb
Host smart-b99f5232-4fa2-4f51-b318-25645ef319a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566354484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2566354484
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2673358118
Short name T1038
Test name
Test status
Simulation time 243225136 ps
CPU time 3.47 seconds
Started Mar 02 12:41:47 PM PST 24
Finished Mar 02 12:41:52 PM PST 24
Peak memory 215296 kb
Host smart-45b004e4-252a-4624-8143-88b9639b1a9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673358118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2673358118
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.617676700
Short name T949
Test name
Test status
Simulation time 48372051 ps
CPU time 2.7 seconds
Started Mar 02 12:41:44 PM PST 24
Finished Mar 02 12:41:48 PM PST 24
Peak memory 206816 kb
Host smart-229030b1-cdf6-4ba8-942a-0458de31c50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617676700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.617676700
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.801859455
Short name T1045
Test name
Test status
Simulation time 147932968 ps
CPU time 5.81 seconds
Started Mar 02 12:41:46 PM PST 24
Finished Mar 02 12:41:54 PM PST 24
Peak memory 219344 kb
Host smart-2c46f889-b5df-4752-8af3-7126e193783c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801859455 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.801859455
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.772356470
Short name T1027
Test name
Test status
Simulation time 259123408 ps
CPU time 9.13 seconds
Started Mar 02 12:41:47 PM PST 24
Finished Mar 02 12:41:58 PM PST 24
Peak memory 207764 kb
Host smart-c7cb9715-f92d-4075-89ce-263b188371f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772356470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.772356470
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.449287434
Short name T550
Test name
Test status
Simulation time 144545020 ps
CPU time 3.18 seconds
Started Mar 02 12:41:49 PM PST 24
Finished Mar 02 12:41:52 PM PST 24
Peak memory 210436 kb
Host smart-86766b6d-192c-49de-812b-f98834255a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449287434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.449287434
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2672158402
Short name T975
Test name
Test status
Simulation time 33977602 ps
CPU time 0.81 seconds
Started Mar 02 12:41:56 PM PST 24
Finished Mar 02 12:41:56 PM PST 24
Peak memory 205820 kb
Host smart-868e14a0-050f-494d-97e6-1d971cf8d3e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672158402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2672158402
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1445162961
Short name T116
Test name
Test status
Simulation time 220259359 ps
CPU time 4.35 seconds
Started Mar 02 12:41:56 PM PST 24
Finished Mar 02 12:42:00 PM PST 24
Peak memory 215336 kb
Host smart-7557a14f-25ba-4a52-afa2-06b59b780163
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1445162961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1445162961
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3679677702
Short name T25
Test name
Test status
Simulation time 1669505090 ps
CPU time 13.12 seconds
Started Mar 02 12:42:03 PM PST 24
Finished Mar 02 12:42:16 PM PST 24
Peak memory 219356 kb
Host smart-f6bc56f7-1dcf-41dc-9aa1-7b3d9e8a6415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679677702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3679677702
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3251464354
Short name T777
Test name
Test status
Simulation time 48421300 ps
CPU time 1.23 seconds
Started Mar 02 12:41:57 PM PST 24
Finished Mar 02 12:41:59 PM PST 24
Peak memory 206072 kb
Host smart-b489b412-c693-405d-ad87-c8d8a1b80217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251464354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3251464354
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2956265753
Short name T761
Test name
Test status
Simulation time 50302771 ps
CPU time 3.12 seconds
Started Mar 02 12:41:57 PM PST 24
Finished Mar 02 12:42:00 PM PST 24
Peak memory 214348 kb
Host smart-f4ce8a14-547c-498f-8a38-aa18f26b3493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956265753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2956265753
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3493219137
Short name T968
Test name
Test status
Simulation time 104529320 ps
CPU time 2.35 seconds
Started Mar 02 12:41:55 PM PST 24
Finished Mar 02 12:41:58 PM PST 24
Peak memory 207928 kb
Host smart-fce58da2-8124-4ea2-8a20-7ca61b5e4e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493219137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3493219137
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2575572081
Short name T298
Test name
Test status
Simulation time 1684404078 ps
CPU time 24.12 seconds
Started Mar 02 12:41:47 PM PST 24
Finished Mar 02 12:42:13 PM PST 24
Peak memory 209584 kb
Host smart-31f11866-3949-404b-a06b-7d318d275110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575572081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2575572081
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.251389478
Short name T635
Test name
Test status
Simulation time 97604755 ps
CPU time 2.77 seconds
Started Mar 02 12:41:49 PM PST 24
Finished Mar 02 12:41:52 PM PST 24
Peak memory 206112 kb
Host smart-302405b8-9576-4115-abde-a6eb1a02e6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251389478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.251389478
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.4187435342
Short name T541
Test name
Test status
Simulation time 601013112 ps
CPU time 6.82 seconds
Started Mar 02 12:41:46 PM PST 24
Finished Mar 02 12:41:55 PM PST 24
Peak memory 206888 kb
Host smart-7f9f6ef4-9ee3-41fd-9055-9e61a9abf65a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187435342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.4187435342
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.15465661
Short name T560
Test name
Test status
Simulation time 408937592 ps
CPU time 4.09 seconds
Started Mar 02 12:41:49 PM PST 24
Finished Mar 02 12:41:53 PM PST 24
Peak memory 208880 kb
Host smart-7002e512-0833-4cad-885b-fc4c8cdd8128
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15465661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.15465661
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2089588822
Short name T230
Test name
Test status
Simulation time 312684933 ps
CPU time 4.88 seconds
Started Mar 02 12:41:48 PM PST 24
Finished Mar 02 12:41:54 PM PST 24
Peak memory 208376 kb
Host smart-749a5bd3-e716-468f-9351-5d17ad03f52c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089588822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2089588822
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.818135776
Short name T667
Test name
Test status
Simulation time 162755195 ps
CPU time 1.76 seconds
Started Mar 02 12:41:53 PM PST 24
Finished Mar 02 12:41:55 PM PST 24
Peak memory 207060 kb
Host smart-e8277a26-8f09-421f-b50d-ae5e9fd1d179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818135776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.818135776
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2928325284
Short name T746
Test name
Test status
Simulation time 940427925 ps
CPU time 3.41 seconds
Started Mar 02 12:42:02 PM PST 24
Finished Mar 02 12:42:05 PM PST 24
Peak memory 207136 kb
Host smart-5db101a9-3c8b-4548-a221-f20e8fd8128b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928325284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2928325284
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3361501698
Short name T327
Test name
Test status
Simulation time 848080079 ps
CPU time 32.76 seconds
Started Mar 02 12:41:54 PM PST 24
Finished Mar 02 12:42:27 PM PST 24
Peak memory 217232 kb
Host smart-37b11ba6-206f-4a85-bd0b-b49a1d158906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361501698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3361501698
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2402408217
Short name T748
Test name
Test status
Simulation time 260285526 ps
CPU time 3.6 seconds
Started Mar 02 12:41:56 PM PST 24
Finished Mar 02 12:41:59 PM PST 24
Peak memory 222492 kb
Host smart-92930d82-6026-4214-862a-8cfc4111f4f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402408217 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2402408217
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1852390555
Short name T697
Test name
Test status
Simulation time 174894084 ps
CPU time 3.99 seconds
Started Mar 02 12:41:54 PM PST 24
Finished Mar 02 12:41:58 PM PST 24
Peak memory 209072 kb
Host smart-65b740de-030d-45a0-8ebd-63b806e63157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852390555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1852390555
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.867950377
Short name T574
Test name
Test status
Simulation time 117701814 ps
CPU time 1.99 seconds
Started Mar 02 12:41:58 PM PST 24
Finished Mar 02 12:42:00 PM PST 24
Peak memory 210268 kb
Host smart-0737a364-37c9-4d06-a48f-645de8907d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867950377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.867950377
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.966723953
Short name T844
Test name
Test status
Simulation time 14508425 ps
CPU time 0.75 seconds
Started Mar 02 12:41:59 PM PST 24
Finished Mar 02 12:42:00 PM PST 24
Peak memory 205880 kb
Host smart-f86739a9-0b81-45da-bc24-02177375fc0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966723953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.966723953
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.723817651
Short name T364
Test name
Test status
Simulation time 1077278190 ps
CPU time 15.58 seconds
Started Mar 02 12:41:54 PM PST 24
Finished Mar 02 12:42:10 PM PST 24
Peak memory 222484 kb
Host smart-1d975141-0026-4b5f-8048-83ca0f145c49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=723817651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.723817651
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1099518747
Short name T27
Test name
Test status
Simulation time 330530023 ps
CPU time 8.95 seconds
Started Mar 02 12:41:52 PM PST 24
Finished Mar 02 12:42:01 PM PST 24
Peak memory 222800 kb
Host smart-1db36343-800d-451f-9c53-d2c760d40d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099518747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1099518747
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2011244446
Short name T231
Test name
Test status
Simulation time 227087549 ps
CPU time 4.38 seconds
Started Mar 02 12:41:57 PM PST 24
Finished Mar 02 12:42:01 PM PST 24
Peak memory 208412 kb
Host smart-b22e62f9-b9da-4cf2-98d7-ffa8e3b3b426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011244446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2011244446
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3879054946
Short name T1031
Test name
Test status
Simulation time 85066552 ps
CPU time 3.65 seconds
Started Mar 02 12:41:59 PM PST 24
Finished Mar 02 12:42:03 PM PST 24
Peak memory 211680 kb
Host smart-9a28b0e4-f7d7-43a6-8bff-af4c5d36abfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879054946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3879054946
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1910530512
Short name T611
Test name
Test status
Simulation time 105739506 ps
CPU time 1.61 seconds
Started Mar 02 12:41:55 PM PST 24
Finished Mar 02 12:41:56 PM PST 24
Peak memory 206000 kb
Host smart-e5fee8af-c583-4219-bccb-bee3ae11aa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910530512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1910530512
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2700763757
Short name T627
Test name
Test status
Simulation time 284369002 ps
CPU time 3.87 seconds
Started Mar 02 12:42:01 PM PST 24
Finished Mar 02 12:42:05 PM PST 24
Peak memory 208944 kb
Host smart-07a0917c-4528-4ea5-be4c-304c6c016196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700763757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2700763757
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2278409999
Short name T344
Test name
Test status
Simulation time 787366077 ps
CPU time 27.34 seconds
Started Mar 02 12:41:57 PM PST 24
Finished Mar 02 12:42:25 PM PST 24
Peak memory 208572 kb
Host smart-abfab635-3e6b-4074-82a5-0dce176787f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278409999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2278409999
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2124059702
Short name T976
Test name
Test status
Simulation time 411281866 ps
CPU time 3.2 seconds
Started Mar 02 12:41:52 PM PST 24
Finished Mar 02 12:41:56 PM PST 24
Peak memory 206884 kb
Host smart-496bc451-4d7b-477f-abe7-ed738538b723
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124059702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2124059702
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2359527860
Short name T686
Test name
Test status
Simulation time 50975156 ps
CPU time 2.9 seconds
Started Mar 02 12:41:55 PM PST 24
Finished Mar 02 12:41:58 PM PST 24
Peak memory 208020 kb
Host smart-14f64c3f-b655-45f2-a17e-cce2733bdcb8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359527860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2359527860
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.624511174
Short name T1012
Test name
Test status
Simulation time 2222173470 ps
CPU time 13.58 seconds
Started Mar 02 12:41:55 PM PST 24
Finished Mar 02 12:42:09 PM PST 24
Peak memory 208048 kb
Host smart-d62d4e91-ed3a-4e26-a76d-eb5e7452909d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624511174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.624511174
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1568438893
Short name T794
Test name
Test status
Simulation time 49127281 ps
CPU time 1.99 seconds
Started Mar 02 12:42:00 PM PST 24
Finished Mar 02 12:42:02 PM PST 24
Peak memory 218136 kb
Host smart-08ea1e95-445a-4478-99fd-8cd43aa90bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568438893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1568438893
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3277903283
Short name T388
Test name
Test status
Simulation time 215839530 ps
CPU time 3.29 seconds
Started Mar 02 12:41:57 PM PST 24
Finished Mar 02 12:42:01 PM PST 24
Peak memory 208428 kb
Host smart-98f009fe-ecac-4b6f-884c-138fdc9c6892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277903283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3277903283
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1082547120
Short name T943
Test name
Test status
Simulation time 990184985 ps
CPU time 37.03 seconds
Started Mar 02 12:41:54 PM PST 24
Finished Mar 02 12:42:31 PM PST 24
Peak memory 216640 kb
Host smart-af05621e-dc65-4b7a-a944-d6bb05caebde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082547120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1082547120
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1941824598
Short name T741
Test name
Test status
Simulation time 99777803 ps
CPU time 3.81 seconds
Started Mar 02 12:42:02 PM PST 24
Finished Mar 02 12:42:06 PM PST 24
Peak memory 222548 kb
Host smart-defb7cca-556b-4a86-8db5-bab78522c4a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941824598 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1941824598
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3483606549
Short name T173
Test name
Test status
Simulation time 154072958 ps
CPU time 3.95 seconds
Started Mar 02 12:42:01 PM PST 24
Finished Mar 02 12:42:05 PM PST 24
Peak memory 207476 kb
Host smart-f3e294b7-82fd-46c0-a0be-1929c75f72c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483606549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3483606549
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3168951506
Short name T790
Test name
Test status
Simulation time 83776202 ps
CPU time 2.38 seconds
Started Mar 02 12:41:58 PM PST 24
Finished Mar 02 12:42:01 PM PST 24
Peak memory 209972 kb
Host smart-e45319dd-3579-43ce-a2b3-5afea2123430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168951506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3168951506
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3422781287
Short name T601
Test name
Test status
Simulation time 49449789 ps
CPU time 0.76 seconds
Started Mar 02 12:39:56 PM PST 24
Finished Mar 02 12:39:57 PM PST 24
Peak memory 205856 kb
Host smart-67789402-dce7-435e-a79c-4b591023f06c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422781287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3422781287
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.738387958
Short name T23
Test name
Test status
Simulation time 116156998 ps
CPU time 1.82 seconds
Started Mar 02 12:39:55 PM PST 24
Finished Mar 02 12:39:57 PM PST 24
Peak memory 209924 kb
Host smart-68c57d23-03f0-4425-84ae-212c1995507d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738387958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.738387958
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3417538344
Short name T808
Test name
Test status
Simulation time 752247373 ps
CPU time 16.16 seconds
Started Mar 02 12:39:48 PM PST 24
Finished Mar 02 12:40:04 PM PST 24
Peak memory 214300 kb
Host smart-5036c239-d08d-44b5-9df5-9ddecf1f43db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417538344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3417538344
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3557016252
Short name T1008
Test name
Test status
Simulation time 251858996 ps
CPU time 5.46 seconds
Started Mar 02 12:39:44 PM PST 24
Finished Mar 02 12:39:50 PM PST 24
Peak memory 219628 kb
Host smart-6376b94e-1ee5-4913-b4a8-54f8e30c591d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557016252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3557016252
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.697967815
Short name T830
Test name
Test status
Simulation time 444384302 ps
CPU time 5.47 seconds
Started Mar 02 12:39:42 PM PST 24
Finished Mar 02 12:39:48 PM PST 24
Peak memory 208712 kb
Host smart-1925af0d-0250-48f1-8f8f-b953dd3599bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697967815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.697967815
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.133381233
Short name T176
Test name
Test status
Simulation time 1910298475 ps
CPU time 17.68 seconds
Started Mar 02 12:39:45 PM PST 24
Finished Mar 02 12:40:03 PM PST 24
Peak memory 209140 kb
Host smart-70c0f125-de13-4daf-bc7c-cbfa05c06be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133381233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.133381233
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.4151457786
Short name T90
Test name
Test status
Simulation time 1281279844 ps
CPU time 31.69 seconds
Started Mar 02 12:39:58 PM PST 24
Finished Mar 02 12:40:30 PM PST 24
Peak memory 239812 kb
Host smart-a47e6953-9466-410c-bc6e-de6c8551bd08
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151457786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.4151457786
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.19009866
Short name T223
Test name
Test status
Simulation time 330344549 ps
CPU time 4.9 seconds
Started Mar 02 12:39:45 PM PST 24
Finished Mar 02 12:39:50 PM PST 24
Peak memory 206892 kb
Host smart-9d829ef9-7e5c-42bd-98a3-95d05841fb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19009866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.19009866
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.3495204859
Short name T294
Test name
Test status
Simulation time 1580005173 ps
CPU time 21.88 seconds
Started Mar 02 12:39:50 PM PST 24
Finished Mar 02 12:40:12 PM PST 24
Peak memory 208760 kb
Host smart-64afc2d0-a9bc-40ee-a890-4e4963b8fd1c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495204859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.3495204859
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.917491268
Short name T789
Test name
Test status
Simulation time 153820469 ps
CPU time 2.96 seconds
Started Mar 02 12:39:44 PM PST 24
Finished Mar 02 12:39:48 PM PST 24
Peak memory 207232 kb
Host smart-1b158409-5124-4916-a4e4-e7522a73be85
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917491268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.917491268
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2606466917
Short name T339
Test name
Test status
Simulation time 870598028 ps
CPU time 4.29 seconds
Started Mar 02 12:39:47 PM PST 24
Finished Mar 02 12:39:52 PM PST 24
Peak memory 208628 kb
Host smart-f1f383ed-ce14-4704-97e0-ea0ddb56fb65
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606466917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2606466917
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3127600070
Short name T1064
Test name
Test status
Simulation time 67625795 ps
CPU time 1.91 seconds
Started Mar 02 12:39:57 PM PST 24
Finished Mar 02 12:40:00 PM PST 24
Peak memory 207088 kb
Host smart-33fc939c-f1e7-4d54-956e-6f606b19be12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127600070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3127600070
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2328504090
Short name T908
Test name
Test status
Simulation time 1043370886 ps
CPU time 3.95 seconds
Started Mar 02 12:39:45 PM PST 24
Finished Mar 02 12:39:49 PM PST 24
Peak memory 206832 kb
Host smart-23dcddee-87c8-4117-8a20-34c06bc47bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328504090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2328504090
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3728382247
Short name T382
Test name
Test status
Simulation time 615315016 ps
CPU time 6.54 seconds
Started Mar 02 12:39:56 PM PST 24
Finished Mar 02 12:40:03 PM PST 24
Peak memory 222560 kb
Host smart-71a21a55-2051-44bc-b0a4-4b75c3667682
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728382247 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3728382247
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2802636832
Short name T895
Test name
Test status
Simulation time 74252033 ps
CPU time 3.73 seconds
Started Mar 02 12:39:45 PM PST 24
Finished Mar 02 12:39:49 PM PST 24
Peak memory 209472 kb
Host smart-c1719b34-79d4-46db-8410-dd6c1ef2b20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802636832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2802636832
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.821204410
Short name T727
Test name
Test status
Simulation time 80315625 ps
CPU time 1.61 seconds
Started Mar 02 12:40:01 PM PST 24
Finished Mar 02 12:40:03 PM PST 24
Peak memory 210024 kb
Host smart-dc878f89-8611-4446-8407-23fd525df06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821204410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.821204410
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3196395972
Short name T555
Test name
Test status
Simulation time 15551026 ps
CPU time 0.94 seconds
Started Mar 02 12:42:00 PM PST 24
Finished Mar 02 12:42:01 PM PST 24
Peak memory 205724 kb
Host smart-48636780-2b08-45ff-9084-8585f3c0f048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196395972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3196395972
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2543105794
Short name T36
Test name
Test status
Simulation time 268998807 ps
CPU time 3.5 seconds
Started Mar 02 12:42:01 PM PST 24
Finished Mar 02 12:42:05 PM PST 24
Peak memory 209356 kb
Host smart-320a59b4-236f-446e-adde-e9c61176a39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543105794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2543105794
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3030614842
Short name T246
Test name
Test status
Simulation time 264441036 ps
CPU time 2.4 seconds
Started Mar 02 12:41:56 PM PST 24
Finished Mar 02 12:41:59 PM PST 24
Peak memory 207492 kb
Host smart-7f49dc29-7bf1-4036-853b-7a6edad6aedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030614842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3030614842
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1797965567
Short name T698
Test name
Test status
Simulation time 331456766 ps
CPU time 9.59 seconds
Started Mar 02 12:41:57 PM PST 24
Finished Mar 02 12:42:06 PM PST 24
Peak memory 209264 kb
Host smart-415b9b67-8816-474f-a1e6-eb429c6782d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797965567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1797965567
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.4103608071
Short name T368
Test name
Test status
Simulation time 1384641044 ps
CPU time 12.66 seconds
Started Mar 02 12:42:02 PM PST 24
Finished Mar 02 12:42:15 PM PST 24
Peak memory 214200 kb
Host smart-0408429c-5db0-43e0-8cfb-49812b497af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103608071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.4103608071
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3220871422
Short name T211
Test name
Test status
Simulation time 343758960 ps
CPU time 3.24 seconds
Started Mar 02 12:41:58 PM PST 24
Finished Mar 02 12:42:01 PM PST 24
Peak memory 209188 kb
Host smart-359e3614-23b4-47f4-a190-ddfa47258d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220871422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3220871422
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1820837757
Short name T356
Test name
Test status
Simulation time 1711240150 ps
CPU time 10.37 seconds
Started Mar 02 12:42:00 PM PST 24
Finished Mar 02 12:42:10 PM PST 24
Peak memory 214260 kb
Host smart-8c884e3c-72b1-45e0-bbc4-5d4d5999f769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820837757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1820837757
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3873994956
Short name T290
Test name
Test status
Simulation time 189054557 ps
CPU time 3.32 seconds
Started Mar 02 12:41:53 PM PST 24
Finished Mar 02 12:41:57 PM PST 24
Peak memory 208540 kb
Host smart-94a587d4-cfe6-4428-ae32-ff5643536e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873994956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3873994956
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2295249920
Short name T868
Test name
Test status
Simulation time 39141068 ps
CPU time 2.39 seconds
Started Mar 02 12:41:53 PM PST 24
Finished Mar 02 12:41:56 PM PST 24
Peak memory 206892 kb
Host smart-bcc95d85-afdd-4447-9cc1-f87fd599e6fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295249920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2295249920
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.765568832
Short name T863
Test name
Test status
Simulation time 155624736 ps
CPU time 3.65 seconds
Started Mar 02 12:41:53 PM PST 24
Finished Mar 02 12:41:57 PM PST 24
Peak memory 206936 kb
Host smart-85d9a7a3-b9ce-4c7a-8b27-e088614bb494
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765568832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.765568832
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3190486159
Short name T847
Test name
Test status
Simulation time 277953643 ps
CPU time 7.24 seconds
Started Mar 02 12:41:53 PM PST 24
Finished Mar 02 12:42:01 PM PST 24
Peak memory 208444 kb
Host smart-9ac16ac8-1b78-4798-9515-7bdd6e9c5825
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190486159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3190486159
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.4085701504
Short name T795
Test name
Test status
Simulation time 173885548 ps
CPU time 3.66 seconds
Started Mar 02 12:41:54 PM PST 24
Finished Mar 02 12:41:58 PM PST 24
Peak memory 214416 kb
Host smart-429cfa0d-9d80-4796-94ca-faeaa1357949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085701504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.4085701504
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3400377360
Short name T881
Test name
Test status
Simulation time 107497747 ps
CPU time 2.46 seconds
Started Mar 02 12:41:59 PM PST 24
Finished Mar 02 12:42:01 PM PST 24
Peak memory 206768 kb
Host smart-a6cbd334-2585-40e2-83ff-10aea53d93ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400377360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3400377360
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.4011791121
Short name T209
Test name
Test status
Simulation time 2585164719 ps
CPU time 82.62 seconds
Started Mar 02 12:42:02 PM PST 24
Finished Mar 02 12:43:25 PM PST 24
Peak memory 222508 kb
Host smart-f1f7ed57-b16b-4c1f-81b4-76ba3b1f8e2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011791121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.4011791121
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1019537910
Short name T314
Test name
Test status
Simulation time 54456668 ps
CPU time 3.33 seconds
Started Mar 02 12:41:54 PM PST 24
Finished Mar 02 12:41:58 PM PST 24
Peak memory 214248 kb
Host smart-487e117b-b685-4feb-b9e1-eb273a8c85fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019537910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1019537910
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.749356605
Short name T97
Test name
Test status
Simulation time 349737495 ps
CPU time 3.66 seconds
Started Mar 02 12:41:59 PM PST 24
Finished Mar 02 12:42:03 PM PST 24
Peak memory 210424 kb
Host smart-69afe453-ca23-4eca-a124-65998fa5fdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749356605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.749356605
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2075092238
Short name T552
Test name
Test status
Simulation time 48016836 ps
CPU time 0.75 seconds
Started Mar 02 12:42:08 PM PST 24
Finished Mar 02 12:42:09 PM PST 24
Peak memory 205756 kb
Host smart-1afdae33-e351-4d2a-9046-33b56dac13ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075092238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2075092238
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3376757818
Short name T325
Test name
Test status
Simulation time 125402567 ps
CPU time 2.61 seconds
Started Mar 02 12:42:00 PM PST 24
Finished Mar 02 12:42:03 PM PST 24
Peak memory 214336 kb
Host smart-eb4bb836-6392-478a-81ea-9237ce171dd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3376757818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3376757818
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3617631793
Short name T30
Test name
Test status
Simulation time 61429087 ps
CPU time 2.59 seconds
Started Mar 02 12:42:00 PM PST 24
Finished Mar 02 12:42:03 PM PST 24
Peak memory 215556 kb
Host smart-00d97f13-bc55-420d-bb39-668b2460a302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617631793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3617631793
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.598794328
Short name T641
Test name
Test status
Simulation time 1458136825 ps
CPU time 19.53 seconds
Started Mar 02 12:42:02 PM PST 24
Finished Mar 02 12:42:21 PM PST 24
Peak memory 217712 kb
Host smart-a0922753-94a6-4b9a-a2f3-f43dbc134404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598794328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.598794328
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2187701060
Short name T663
Test name
Test status
Simulation time 5690932972 ps
CPU time 25.4 seconds
Started Mar 02 12:41:57 PM PST 24
Finished Mar 02 12:42:22 PM PST 24
Peak memory 214356 kb
Host smart-b10a3afa-8291-4037-a5cc-01a14968785e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187701060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2187701060
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1973996526
Short name T302
Test name
Test status
Simulation time 842419921 ps
CPU time 6.56 seconds
Started Mar 02 12:42:00 PM PST 24
Finished Mar 02 12:42:07 PM PST 24
Peak memory 214236 kb
Host smart-8e80fb44-da17-4594-930b-bb6c04a040ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973996526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1973996526
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_random.3888213653
Short name T280
Test name
Test status
Simulation time 11257412206 ps
CPU time 80.9 seconds
Started Mar 02 12:42:01 PM PST 24
Finished Mar 02 12:43:22 PM PST 24
Peak memory 209800 kb
Host smart-7dad31ff-71a2-47db-bfa4-e20a9c88c8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888213653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3888213653
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4176602959
Short name T694
Test name
Test status
Simulation time 254822461 ps
CPU time 2.95 seconds
Started Mar 02 12:41:57 PM PST 24
Finished Mar 02 12:42:00 PM PST 24
Peak memory 208584 kb
Host smart-0edbfcbc-69af-42dc-a9d8-28261c0ec9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176602959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4176602959
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3495145289
Short name T706
Test name
Test status
Simulation time 4939140197 ps
CPU time 65.52 seconds
Started Mar 02 12:42:05 PM PST 24
Finished Mar 02 12:43:10 PM PST 24
Peak memory 208976 kb
Host smart-8d17c66c-0dba-4d40-897d-c8c0c4ae2431
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495145289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3495145289
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1004698351
Short name T387
Test name
Test status
Simulation time 48909974 ps
CPU time 2.56 seconds
Started Mar 02 12:42:01 PM PST 24
Finished Mar 02 12:42:04 PM PST 24
Peak memory 208136 kb
Host smart-74818872-e39c-4518-9279-46408968ba34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004698351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1004698351
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1967213347
Short name T865
Test name
Test status
Simulation time 362337007 ps
CPU time 3.15 seconds
Started Mar 02 12:41:57 PM PST 24
Finished Mar 02 12:42:00 PM PST 24
Peak memory 208492 kb
Host smart-c63adc1b-71a6-403c-9059-b2372c0cf417
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967213347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1967213347
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.4258842173
Short name T821
Test name
Test status
Simulation time 491637335 ps
CPU time 10.39 seconds
Started Mar 02 12:41:57 PM PST 24
Finished Mar 02 12:42:08 PM PST 24
Peak memory 209804 kb
Host smart-30f73543-863c-493d-a5a7-7861c8fe6b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258842173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.4258842173
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.4264862997
Short name T846
Test name
Test status
Simulation time 101501202 ps
CPU time 2.14 seconds
Started Mar 02 12:42:01 PM PST 24
Finished Mar 02 12:42:03 PM PST 24
Peak memory 206052 kb
Host smart-def96ab7-cfed-4c1c-98f2-2f07ae1ce226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264862997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.4264862997
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1861546632
Short name T716
Test name
Test status
Simulation time 612646831 ps
CPU time 4.93 seconds
Started Mar 02 12:42:03 PM PST 24
Finished Mar 02 12:42:09 PM PST 24
Peak memory 222540 kb
Host smart-36abb528-9f0f-43c6-bf0a-ba8836d72fb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861546632 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1861546632
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3459869243
Short name T322
Test name
Test status
Simulation time 101676718 ps
CPU time 3.15 seconds
Started Mar 02 12:41:56 PM PST 24
Finished Mar 02 12:41:59 PM PST 24
Peak memory 208624 kb
Host smart-17d3e6f3-d4ff-407f-bace-c1c3db1ed241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459869243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3459869243
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1406991557
Short name T46
Test name
Test status
Simulation time 50440778 ps
CPU time 2.41 seconds
Started Mar 02 12:42:00 PM PST 24
Finished Mar 02 12:42:03 PM PST 24
Peak memory 209984 kb
Host smart-c96ef4cd-7251-416d-94a6-53be2254c117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406991557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1406991557
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1033914560
Short name T562
Test name
Test status
Simulation time 67902277 ps
CPU time 0.8 seconds
Started Mar 02 12:42:03 PM PST 24
Finished Mar 02 12:42:04 PM PST 24
Peak memory 205780 kb
Host smart-52b96451-7512-4f08-bcbd-62984a17ac90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033914560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1033914560
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3785828086
Short name T1001
Test name
Test status
Simulation time 955310413 ps
CPU time 12.31 seconds
Started Mar 02 12:42:04 PM PST 24
Finished Mar 02 12:42:16 PM PST 24
Peak memory 222400 kb
Host smart-38feaed5-d9cc-441d-ad6c-6aa24b59b0ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3785828086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3785828086
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3802739381
Short name T26
Test name
Test status
Simulation time 362952527 ps
CPU time 5.48 seconds
Started Mar 02 12:42:04 PM PST 24
Finished Mar 02 12:42:10 PM PST 24
Peak memory 218492 kb
Host smart-3b9c70be-2ce9-4a99-8e83-53015b55fcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802739381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3802739381
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.674643422
Short name T737
Test name
Test status
Simulation time 71148803 ps
CPU time 2.52 seconds
Started Mar 02 12:42:05 PM PST 24
Finished Mar 02 12:42:08 PM PST 24
Peak memory 208024 kb
Host smart-a8c40127-092b-44d8-a49c-c835a728fdda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674643422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.674643422
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3737542842
Short name T253
Test name
Test status
Simulation time 314087829 ps
CPU time 6.08 seconds
Started Mar 02 12:42:05 PM PST 24
Finished Mar 02 12:42:11 PM PST 24
Peak memory 214204 kb
Host smart-42f8dbf5-9712-491b-a739-f941fc980c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737542842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3737542842
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2708693893
Short name T60
Test name
Test status
Simulation time 234243931 ps
CPU time 4.02 seconds
Started Mar 02 12:42:04 PM PST 24
Finished Mar 02 12:42:08 PM PST 24
Peak memory 214332 kb
Host smart-c5d24dd6-045a-4c4d-a136-b103c40f505c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708693893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2708693893
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.365237258
Short name T1063
Test name
Test status
Simulation time 95782330 ps
CPU time 2.85 seconds
Started Mar 02 12:42:04 PM PST 24
Finished Mar 02 12:42:07 PM PST 24
Peak memory 207052 kb
Host smart-6cd42450-94f5-47d8-9627-131868f6761b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365237258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.365237258
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1507737037
Short name T219
Test name
Test status
Simulation time 100571545 ps
CPU time 2.29 seconds
Started Mar 02 12:42:03 PM PST 24
Finished Mar 02 12:42:05 PM PST 24
Peak memory 206904 kb
Host smart-6d469da3-e492-404d-91af-d6414cb8d50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507737037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1507737037
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3067736022
Short name T1049
Test name
Test status
Simulation time 668769376 ps
CPU time 17.37 seconds
Started Mar 02 12:42:02 PM PST 24
Finished Mar 02 12:42:20 PM PST 24
Peak memory 208036 kb
Host smart-70b6e043-6d16-411a-a501-80f3955f1fc7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067736022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3067736022
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2555409655
Short name T181
Test name
Test status
Simulation time 78901404 ps
CPU time 3.5 seconds
Started Mar 02 12:42:10 PM PST 24
Finished Mar 02 12:42:14 PM PST 24
Peak memory 208928 kb
Host smart-4ab359c9-2f7d-4ed5-9737-e57ec63f55af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555409655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2555409655
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1989445025
Short name T622
Test name
Test status
Simulation time 236642249 ps
CPU time 2.53 seconds
Started Mar 02 12:42:10 PM PST 24
Finished Mar 02 12:42:13 PM PST 24
Peak memory 206808 kb
Host smart-cac863f3-594e-4a9e-a931-041d53298db8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989445025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1989445025
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1202395586
Short name T813
Test name
Test status
Simulation time 163164531 ps
CPU time 4.7 seconds
Started Mar 02 12:42:03 PM PST 24
Finished Mar 02 12:42:08 PM PST 24
Peak memory 214300 kb
Host smart-297e6d19-84bc-49df-b2e2-db2979ea4000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202395586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1202395586
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.4219624678
Short name T385
Test name
Test status
Simulation time 100504946 ps
CPU time 3.81 seconds
Started Mar 02 12:42:05 PM PST 24
Finished Mar 02 12:42:09 PM PST 24
Peak memory 206884 kb
Host smart-8d89ce89-4674-4995-a282-f6cfd8fe492e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219624678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.4219624678
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1596726939
Short name T638
Test name
Test status
Simulation time 930987503 ps
CPU time 21.48 seconds
Started Mar 02 12:42:03 PM PST 24
Finished Mar 02 12:42:25 PM PST 24
Peak memory 215648 kb
Host smart-80cc4e82-bf0e-49d7-b610-7cd3035e1054
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596726939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1596726939
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2666158543
Short name T586
Test name
Test status
Simulation time 134015045 ps
CPU time 4.25 seconds
Started Mar 02 12:42:04 PM PST 24
Finished Mar 02 12:42:09 PM PST 24
Peak memory 222720 kb
Host smart-73f89497-a6c7-4b1c-bde4-26710cffad23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666158543 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2666158543
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2165291349
Short name T995
Test name
Test status
Simulation time 758491907 ps
CPU time 10.47 seconds
Started Mar 02 12:42:03 PM PST 24
Finished Mar 02 12:42:14 PM PST 24
Peak memory 208288 kb
Host smart-3dc83103-6093-41af-b0ca-b04e6091e6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165291349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2165291349
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3153285322
Short name T840
Test name
Test status
Simulation time 93438187 ps
CPU time 2.65 seconds
Started Mar 02 12:42:10 PM PST 24
Finished Mar 02 12:42:13 PM PST 24
Peak memory 209896 kb
Host smart-4a3b9b3d-f894-4990-9535-bc66d60302a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153285322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3153285322
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2850731442
Short name T688
Test name
Test status
Simulation time 67384571 ps
CPU time 0.73 seconds
Started Mar 02 12:42:13 PM PST 24
Finished Mar 02 12:42:14 PM PST 24
Peak memory 205716 kb
Host smart-3c646021-f292-49cc-9b23-c530024c94bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850731442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2850731442
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.134832778
Short name T871
Test name
Test status
Simulation time 70825355 ps
CPU time 3.19 seconds
Started Mar 02 12:42:11 PM PST 24
Finished Mar 02 12:42:14 PM PST 24
Peak memory 210012 kb
Host smart-f1aeb2ea-e016-48ac-b207-d8617a1e7433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134832778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.134832778
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1215313853
Short name T745
Test name
Test status
Simulation time 63357735 ps
CPU time 3.04 seconds
Started Mar 02 12:42:03 PM PST 24
Finished Mar 02 12:42:06 PM PST 24
Peak memory 214320 kb
Host smart-3a6a83ac-af54-4d70-8797-ad52ab773e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215313853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1215313853
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.920245202
Short name T348
Test name
Test status
Simulation time 898818803 ps
CPU time 9 seconds
Started Mar 02 12:42:11 PM PST 24
Finished Mar 02 12:42:20 PM PST 24
Peak memory 222340 kb
Host smart-b571dcf5-a308-4cff-85db-aba1b809c975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920245202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.920245202
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2886556591
Short name T814
Test name
Test status
Simulation time 61695484 ps
CPU time 2.96 seconds
Started Mar 02 12:42:03 PM PST 24
Finished Mar 02 12:42:06 PM PST 24
Peak memory 208260 kb
Host smart-42ff22e8-d83c-4351-9df9-baa77eff5cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886556591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2886556591
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1646784068
Short name T797
Test name
Test status
Simulation time 331917768 ps
CPU time 5.6 seconds
Started Mar 02 12:42:03 PM PST 24
Finished Mar 02 12:42:09 PM PST 24
Peak memory 217944 kb
Host smart-98750b29-9ff0-4e82-a060-13bcb8e79ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646784068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1646784068
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.289327752
Short name T289
Test name
Test status
Simulation time 534653666 ps
CPU time 4.79 seconds
Started Mar 02 12:42:01 PM PST 24
Finished Mar 02 12:42:07 PM PST 24
Peak memory 207024 kb
Host smart-8000351e-c21c-4caf-9233-125562e12ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289327752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.289327752
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4088373295
Short name T781
Test name
Test status
Simulation time 55677919 ps
CPU time 2.9 seconds
Started Mar 02 12:42:06 PM PST 24
Finished Mar 02 12:42:09 PM PST 24
Peak memory 208860 kb
Host smart-e3b5a810-cbc3-4f93-a37f-173da3ca116e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088373295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4088373295
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.453707719
Short name T938
Test name
Test status
Simulation time 229531014 ps
CPU time 3.17 seconds
Started Mar 02 12:42:01 PM PST 24
Finished Mar 02 12:42:04 PM PST 24
Peak memory 206844 kb
Host smart-42976c56-ec45-4e5e-9a20-6a31563ef203
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453707719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.453707719
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1509954906
Short name T594
Test name
Test status
Simulation time 1043492310 ps
CPU time 10.63 seconds
Started Mar 02 12:42:07 PM PST 24
Finished Mar 02 12:42:18 PM PST 24
Peak memory 208352 kb
Host smart-41fc26b8-ca02-4680-a3ef-8a470b2148f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509954906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1509954906
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2624744897
Short name T946
Test name
Test status
Simulation time 771005603 ps
CPU time 8.22 seconds
Started Mar 02 12:42:19 PM PST 24
Finished Mar 02 12:42:28 PM PST 24
Peak memory 218284 kb
Host smart-f9262c0f-cde9-4193-b592-88fe73ca1ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624744897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2624744897
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2364539466
Short name T945
Test name
Test status
Simulation time 68581350 ps
CPU time 2.85 seconds
Started Mar 02 12:42:10 PM PST 24
Finished Mar 02 12:42:13 PM PST 24
Peak memory 208280 kb
Host smart-2cf87864-161e-47c6-99f1-a457221e277a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364539466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2364539466
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.628454957
Short name T412
Test name
Test status
Simulation time 24368991 ps
CPU time 0.77 seconds
Started Mar 02 12:42:12 PM PST 24
Finished Mar 02 12:42:12 PM PST 24
Peak memory 205732 kb
Host smart-a1c931a4-3ea7-4d47-8c5f-cf310b303364
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628454957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.628454957
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1713568708
Short name T619
Test name
Test status
Simulation time 262896911 ps
CPU time 6.1 seconds
Started Mar 02 12:42:09 PM PST 24
Finished Mar 02 12:42:15 PM PST 24
Peak memory 209672 kb
Host smart-d30116e5-fce1-4b0c-8fd5-878243ec6bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713568708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1713568708
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2735970927
Short name T393
Test name
Test status
Simulation time 808967165 ps
CPU time 15.3 seconds
Started Mar 02 12:42:13 PM PST 24
Finished Mar 02 12:42:28 PM PST 24
Peak memory 211132 kb
Host smart-38eec2b3-c5d2-4a46-8b5b-3af5ad129c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735970927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2735970927
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1962976634
Short name T610
Test name
Test status
Simulation time 10997228 ps
CPU time 0.79 seconds
Started Mar 02 12:42:16 PM PST 24
Finished Mar 02 12:42:17 PM PST 24
Peak memory 205872 kb
Host smart-02a22c42-e31e-497a-930f-6834db4ed86c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962976634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1962976634
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1462629052
Short name T394
Test name
Test status
Simulation time 508443191 ps
CPU time 22.22 seconds
Started Mar 02 12:42:09 PM PST 24
Finished Mar 02 12:42:32 PM PST 24
Peak memory 215584 kb
Host smart-98f78435-72f8-4999-ac47-1fcb1dc4c17c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1462629052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1462629052
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.4143397205
Short name T351
Test name
Test status
Simulation time 1754596459 ps
CPU time 40.75 seconds
Started Mar 02 12:42:19 PM PST 24
Finished Mar 02 12:43:00 PM PST 24
Peak memory 218328 kb
Host smart-951bca05-8376-459b-86d7-5b8b917dc15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143397205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.4143397205
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3247104113
Short name T85
Test name
Test status
Simulation time 353603069 ps
CPU time 8.77 seconds
Started Mar 02 12:42:15 PM PST 24
Finished Mar 02 12:42:23 PM PST 24
Peak memory 220240 kb
Host smart-cc0715aa-5839-4fc7-8009-59f853fc5c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247104113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3247104113
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3511391589
Short name T77
Test name
Test status
Simulation time 174439735 ps
CPU time 4.5 seconds
Started Mar 02 12:42:13 PM PST 24
Finished Mar 02 12:42:18 PM PST 24
Peak memory 210608 kb
Host smart-9d3c8d61-820f-405b-8593-d562d19cd182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511391589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3511391589
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.157511261
Short name T199
Test name
Test status
Simulation time 136210491 ps
CPU time 4.61 seconds
Started Mar 02 12:42:11 PM PST 24
Finished Mar 02 12:42:16 PM PST 24
Peak memory 222372 kb
Host smart-1bdb4950-1a2b-4e10-a580-823db6eb4c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157511261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.157511261
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2551714438
Short name T189
Test name
Test status
Simulation time 211487424 ps
CPU time 7.91 seconds
Started Mar 02 12:42:16 PM PST 24
Finished Mar 02 12:42:24 PM PST 24
Peak memory 218208 kb
Host smart-9873ea90-d567-4011-a081-0a3aef5cf9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551714438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2551714438
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.208498241
Short name T805
Test name
Test status
Simulation time 206626137 ps
CPU time 5.42 seconds
Started Mar 02 12:42:11 PM PST 24
Finished Mar 02 12:42:17 PM PST 24
Peak memory 206760 kb
Host smart-992d87ec-4445-4387-8ef6-c18fd7766c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208498241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.208498241
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3564295242
Short name T166
Test name
Test status
Simulation time 205030517 ps
CPU time 2.38 seconds
Started Mar 02 12:42:16 PM PST 24
Finished Mar 02 12:42:18 PM PST 24
Peak memory 206932 kb
Host smart-0970c8dc-ea83-417f-a5d4-dc8cfd33e38b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564295242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3564295242
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.626331894
Short name T809
Test name
Test status
Simulation time 376300197 ps
CPU time 3.74 seconds
Started Mar 02 12:42:15 PM PST 24
Finished Mar 02 12:42:19 PM PST 24
Peak memory 208640 kb
Host smart-577b8c4a-2510-4497-bf21-ea0bd0be073d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626331894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.626331894
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2215474019
Short name T580
Test name
Test status
Simulation time 1267293850 ps
CPU time 3.5 seconds
Started Mar 02 12:42:16 PM PST 24
Finished Mar 02 12:42:19 PM PST 24
Peak memory 208916 kb
Host smart-8d64bbce-b63d-42e7-af47-99c00458ab8e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215474019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2215474019
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.133087123
Short name T628
Test name
Test status
Simulation time 371585491 ps
CPU time 3.13 seconds
Started Mar 02 12:42:14 PM PST 24
Finished Mar 02 12:42:17 PM PST 24
Peak memory 207936 kb
Host smart-7cfb5a89-8461-436a-b746-95bc7c805cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133087123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.133087123
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1041228784
Short name T583
Test name
Test status
Simulation time 1197268505 ps
CPU time 5.81 seconds
Started Mar 02 12:42:12 PM PST 24
Finished Mar 02 12:42:18 PM PST 24
Peak memory 206652 kb
Host smart-36a7f714-8df0-47c6-814d-22f1b24a43db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041228784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1041228784
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.2640740550
Short name T724
Test name
Test status
Simulation time 506945711 ps
CPU time 9.85 seconds
Started Mar 02 12:42:16 PM PST 24
Finished Mar 02 12:42:26 PM PST 24
Peak memory 222544 kb
Host smart-81124726-b92e-44d9-bd32-586327373eec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640740550 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.2640740550
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3549832266
Short name T825
Test name
Test status
Simulation time 2813700870 ps
CPU time 16.75 seconds
Started Mar 02 12:42:13 PM PST 24
Finished Mar 02 12:42:30 PM PST 24
Peak memory 208356 kb
Host smart-1c4785c6-0187-47bd-ab86-c67376cccbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549832266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3549832266
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2473976216
Short name T785
Test name
Test status
Simulation time 71487796 ps
CPU time 1.95 seconds
Started Mar 02 12:42:10 PM PST 24
Finished Mar 02 12:42:12 PM PST 24
Peak memory 209796 kb
Host smart-f5e843ec-cc65-4369-bde3-c146f5fd9890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473976216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2473976216
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.399973171
Short name T1029
Test name
Test status
Simulation time 25308649 ps
CPU time 0.81 seconds
Started Mar 02 12:42:21 PM PST 24
Finished Mar 02 12:42:22 PM PST 24
Peak memory 205684 kb
Host smart-96f12a81-194d-4402-88a6-1470fafde929
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399973171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.399973171
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.473937140
Short name T835
Test name
Test status
Simulation time 2302476847 ps
CPU time 34.56 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:57 PM PST 24
Peak memory 214300 kb
Host smart-1feca6c1-1340-4eba-9241-4152156a7f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473937140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.473937140
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3748692703
Short name T921
Test name
Test status
Simulation time 31466700 ps
CPU time 2.34 seconds
Started Mar 02 12:42:15 PM PST 24
Finished Mar 02 12:42:17 PM PST 24
Peak memory 208020 kb
Host smart-d8566bcf-f1c9-461e-992f-e127da81d4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748692703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3748692703
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2765332314
Short name T251
Test name
Test status
Simulation time 1363729666 ps
CPU time 7.81 seconds
Started Mar 02 12:42:24 PM PST 24
Finished Mar 02 12:42:32 PM PST 24
Peak memory 209700 kb
Host smart-c2827f83-bcfb-46e7-840e-c7273707b53f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765332314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2765332314
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1284717213
Short name T318
Test name
Test status
Simulation time 296015307 ps
CPU time 6.76 seconds
Started Mar 02 12:42:15 PM PST 24
Finished Mar 02 12:42:22 PM PST 24
Peak memory 218484 kb
Host smart-ba3a85c4-0d82-4fbf-b7ef-f2d2433447ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284717213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1284717213
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.836612919
Short name T877
Test name
Test status
Simulation time 219527987 ps
CPU time 7.5 seconds
Started Mar 02 12:42:19 PM PST 24
Finished Mar 02 12:42:27 PM PST 24
Peak memory 214184 kb
Host smart-c867aa0a-0daf-4f50-b5dc-faf6595d66b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836612919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.836612919
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3549093557
Short name T704
Test name
Test status
Simulation time 36795757 ps
CPU time 2.23 seconds
Started Mar 02 12:42:12 PM PST 24
Finished Mar 02 12:42:14 PM PST 24
Peak memory 206756 kb
Host smart-d03261d9-9bf2-4938-9a3f-586abc762acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549093557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3549093557
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3032113840
Short name T860
Test name
Test status
Simulation time 797390726 ps
CPU time 23.84 seconds
Started Mar 02 12:42:14 PM PST 24
Finished Mar 02 12:42:38 PM PST 24
Peak memory 208356 kb
Host smart-2b51756c-3486-4ade-b113-4644acea78f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032113840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3032113840
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.586692171
Short name T717
Test name
Test status
Simulation time 289340665 ps
CPU time 2.96 seconds
Started Mar 02 12:42:16 PM PST 24
Finished Mar 02 12:42:19 PM PST 24
Peak memory 206984 kb
Host smart-a9b2bd73-b563-437a-a12d-38ffff6a12ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586692171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.586692171
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1496302110
Short name T582
Test name
Test status
Simulation time 55495052 ps
CPU time 3.16 seconds
Started Mar 02 12:42:19 PM PST 24
Finished Mar 02 12:42:23 PM PST 24
Peak memory 206872 kb
Host smart-d9c6299a-df7c-4c5b-be53-803d7bd9abb3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496302110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1496302110
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.2373603794
Short name T937
Test name
Test status
Simulation time 111228417 ps
CPU time 3.43 seconds
Started Mar 02 12:42:22 PM PST 24
Finished Mar 02 12:42:25 PM PST 24
Peak memory 209952 kb
Host smart-30a17fd7-45f3-4a9e-ba39-5a051e455881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373603794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.2373603794
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3922229109
Short name T714
Test name
Test status
Simulation time 1095450214 ps
CPU time 7.95 seconds
Started Mar 02 12:42:11 PM PST 24
Finished Mar 02 12:42:19 PM PST 24
Peak memory 206804 kb
Host smart-db6884a6-9c66-4aad-917f-3f3074409fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922229109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3922229109
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3141956657
Short name T198
Test name
Test status
Simulation time 96038001 ps
CPU time 6.6 seconds
Started Mar 02 12:42:22 PM PST 24
Finished Mar 02 12:42:28 PM PST 24
Peak memory 222620 kb
Host smart-68d3a952-41b1-4d98-94c1-04c39d94cfe7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141956657 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3141956657
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1476762895
Short name T549
Test name
Test status
Simulation time 85098255 ps
CPU time 3.99 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:27 PM PST 24
Peak memory 209068 kb
Host smart-10839113-0d47-49ae-928e-3664ef2fdc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476762895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1476762895
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3234630331
Short name T1032
Test name
Test status
Simulation time 179250215 ps
CPU time 2.39 seconds
Started Mar 02 12:42:28 PM PST 24
Finished Mar 02 12:42:30 PM PST 24
Peak memory 209896 kb
Host smart-a52516da-3e73-4b9b-a542-203062af7b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234630331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3234630331
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3670608595
Short name T633
Test name
Test status
Simulation time 51169210 ps
CPU time 0.9 seconds
Started Mar 02 12:42:22 PM PST 24
Finished Mar 02 12:42:23 PM PST 24
Peak memory 205716 kb
Host smart-34e85db9-f094-47e1-899d-fc2fa9b37ad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670608595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3670608595
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2140548573
Short name T401
Test name
Test status
Simulation time 295986643 ps
CPU time 4.56 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:28 PM PST 24
Peak memory 214248 kb
Host smart-93232d42-8798-4283-be79-8900486dd0f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2140548573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2140548573
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2494527169
Short name T31
Test name
Test status
Simulation time 235917942 ps
CPU time 5.33 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:28 PM PST 24
Peak memory 221416 kb
Host smart-78e6afdc-52a3-4192-b474-988060869344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494527169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2494527169
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2136961393
Short name T996
Test name
Test status
Simulation time 52287240 ps
CPU time 2.71 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:26 PM PST 24
Peak memory 207752 kb
Host smart-86e073bb-2ed8-42c2-8ac8-f7c577896704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136961393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2136961393
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1590095918
Short name T665
Test name
Test status
Simulation time 159439595 ps
CPU time 3.24 seconds
Started Mar 02 12:42:21 PM PST 24
Finished Mar 02 12:42:25 PM PST 24
Peak memory 208808 kb
Host smart-38b64109-9fd9-4bd7-9001-5101efbfdfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590095918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1590095918
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3878929350
Short name T201
Test name
Test status
Simulation time 235923724 ps
CPU time 3.1 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:26 PM PST 24
Peak memory 214216 kb
Host smart-624a2482-5d2b-4514-8985-76ebb3151020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878929350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3878929350
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1136479408
Short name T177
Test name
Test status
Simulation time 224789935 ps
CPU time 5.33 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:28 PM PST 24
Peak memory 214404 kb
Host smart-fb8550d4-ba23-4410-abd2-d20790c2fb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136479408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1136479408
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1317787379
Short name T856
Test name
Test status
Simulation time 130412850 ps
CPU time 2.54 seconds
Started Mar 02 12:42:22 PM PST 24
Finished Mar 02 12:42:25 PM PST 24
Peak memory 207580 kb
Host smart-3f65579e-26b6-413c-8a0c-85cb1ae74571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317787379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1317787379
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1821124558
Short name T898
Test name
Test status
Simulation time 179113934 ps
CPU time 5.38 seconds
Started Mar 02 12:42:22 PM PST 24
Finished Mar 02 12:42:27 PM PST 24
Peak memory 208720 kb
Host smart-9bc2b187-46c4-4f15-b20e-4e58d8c0d3e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821124558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1821124558
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3632239369
Short name T639
Test name
Test status
Simulation time 69267606 ps
CPU time 2.44 seconds
Started Mar 02 12:42:28 PM PST 24
Finished Mar 02 12:42:30 PM PST 24
Peak memory 207152 kb
Host smart-ea0f6527-a482-47e5-ae06-cc62f0ec482f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632239369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3632239369
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3278233641
Short name T807
Test name
Test status
Simulation time 79976196 ps
CPU time 2.91 seconds
Started Mar 02 12:42:21 PM PST 24
Finished Mar 02 12:42:25 PM PST 24
Peak memory 206676 kb
Host smart-b0f1f68d-5129-48db-8943-7cfc1a53e6b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278233641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3278233641
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1935715165
Short name T624
Test name
Test status
Simulation time 161271533 ps
CPU time 3.79 seconds
Started Mar 02 12:42:20 PM PST 24
Finished Mar 02 12:42:24 PM PST 24
Peak memory 220508 kb
Host smart-9d32e19b-9935-46f3-98c9-4ea1f8016f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935715165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1935715165
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3164763925
Short name T556
Test name
Test status
Simulation time 4667778054 ps
CPU time 26.51 seconds
Started Mar 02 12:42:21 PM PST 24
Finished Mar 02 12:42:48 PM PST 24
Peak memory 208556 kb
Host smart-9e35997b-398e-4afc-b1a3-0e3c5c5c4933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164763925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3164763925
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.266564218
Short name T6
Test name
Test status
Simulation time 1156405587 ps
CPU time 13.32 seconds
Started Mar 02 12:42:24 PM PST 24
Finished Mar 02 12:42:37 PM PST 24
Peak memory 219912 kb
Host smart-1d091dd6-f776-493d-9fb2-056192ae84b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266564218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.266564218
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.53026173
Short name T193
Test name
Test status
Simulation time 100323726 ps
CPU time 5.2 seconds
Started Mar 02 12:42:25 PM PST 24
Finished Mar 02 12:42:31 PM PST 24
Peak memory 222456 kb
Host smart-98d94707-4560-4f5e-9048-6484aba00ce0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53026173 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.53026173
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1056113934
Short name T645
Test name
Test status
Simulation time 69936525 ps
CPU time 3.5 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:26 PM PST 24
Peak memory 207956 kb
Host smart-44137cfa-8435-4763-ac7d-cfe8895d8d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056113934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1056113934
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1196769466
Short name T922
Test name
Test status
Simulation time 47276321 ps
CPU time 0.81 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:24 PM PST 24
Peak memory 205820 kb
Host smart-6b1e6444-be8f-4e29-bf00-be479b203a30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196769466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1196769466
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1881147598
Short name T370
Test name
Test status
Simulation time 110436143 ps
CPU time 2.41 seconds
Started Mar 02 12:42:22 PM PST 24
Finished Mar 02 12:42:25 PM PST 24
Peak memory 214232 kb
Host smart-961e0b2d-110d-4289-a74a-643f554572cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1881147598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1881147598
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.651186611
Short name T28
Test name
Test status
Simulation time 139038279 ps
CPU time 2.92 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:26 PM PST 24
Peak memory 219116 kb
Host smart-e74fa5ac-41ea-444f-b467-101090ff3255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651186611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.651186611
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2763619286
Short name T44
Test name
Test status
Simulation time 206349630 ps
CPU time 3.86 seconds
Started Mar 02 12:42:22 PM PST 24
Finished Mar 02 12:42:26 PM PST 24
Peak memory 209812 kb
Host smart-47b63446-88eb-45e0-8bc2-3266c8883124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763619286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2763619286
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.501913482
Short name T84
Test name
Test status
Simulation time 371440420 ps
CPU time 4.73 seconds
Started Mar 02 12:42:36 PM PST 24
Finished Mar 02 12:42:41 PM PST 24
Peak memory 219192 kb
Host smart-7529bc11-1cb2-4610-9bb1-104c11cf8f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501913482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.501913482
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3057014711
Short name T228
Test name
Test status
Simulation time 314792501 ps
CPU time 3.68 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:26 PM PST 24
Peak memory 214056 kb
Host smart-3a0cbe24-dc47-4277-9b6c-8db159bf12a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057014711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3057014711
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.98452169
Short name T791
Test name
Test status
Simulation time 431894217 ps
CPU time 4.36 seconds
Started Mar 02 12:42:25 PM PST 24
Finished Mar 02 12:42:30 PM PST 24
Peak memory 220432 kb
Host smart-5ea171a9-2bff-411c-a3ce-d7a8b053bf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98452169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.98452169
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2337392209
Short name T278
Test name
Test status
Simulation time 101974256 ps
CPU time 5.17 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:28 PM PST 24
Peak memory 209600 kb
Host smart-60310b3f-997c-4f27-9cb9-1d87b071db2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337392209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2337392209
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3928439282
Short name T179
Test name
Test status
Simulation time 859725100 ps
CPU time 10.04 seconds
Started Mar 02 12:42:20 PM PST 24
Finished Mar 02 12:42:31 PM PST 24
Peak memory 206840 kb
Host smart-c81bb2ee-b10d-4e13-b7dc-baf94b48a3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928439282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3928439282
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.186262566
Short name T313
Test name
Test status
Simulation time 806466922 ps
CPU time 8.63 seconds
Started Mar 02 12:42:22 PM PST 24
Finished Mar 02 12:42:31 PM PST 24
Peak memory 208324 kb
Host smart-2f231e92-02e4-40ec-ad7f-296ef4602cae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186262566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.186262566
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1578305103
Short name T869
Test name
Test status
Simulation time 27524274 ps
CPU time 2.35 seconds
Started Mar 02 12:42:36 PM PST 24
Finished Mar 02 12:42:39 PM PST 24
Peak memory 208768 kb
Host smart-e2062b14-b54a-4db8-ad35-6b3c3af9d89b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578305103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1578305103
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.4283066864
Short name T566
Test name
Test status
Simulation time 100379367 ps
CPU time 2.74 seconds
Started Mar 02 12:42:24 PM PST 24
Finished Mar 02 12:42:27 PM PST 24
Peak memory 208716 kb
Host smart-c6d83863-bc09-47ad-ba16-82ff4a6030ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283066864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.4283066864
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.857257661
Short name T652
Test name
Test status
Simulation time 371046707 ps
CPU time 3.4 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:26 PM PST 24
Peak memory 218304 kb
Host smart-64fca072-89bb-4d11-80f3-df4f4db184f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857257661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.857257661
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.424563082
Short name T799
Test name
Test status
Simulation time 391710322 ps
CPU time 4.48 seconds
Started Mar 02 12:42:24 PM PST 24
Finished Mar 02 12:42:29 PM PST 24
Peak memory 206728 kb
Host smart-af34ffd7-7898-4ff6-880f-f5fdacbfb281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424563082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.424563082
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1464315307
Short name T845
Test name
Test status
Simulation time 501278793 ps
CPU time 5.07 seconds
Started Mar 02 12:42:25 PM PST 24
Finished Mar 02 12:42:31 PM PST 24
Peak memory 222640 kb
Host smart-e2934fd8-5fb2-4397-9d4c-5026b286524a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464315307 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1464315307
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2875475558
Short name T1048
Test name
Test status
Simulation time 639273212 ps
CPU time 13.99 seconds
Started Mar 02 12:42:28 PM PST 24
Finished Mar 02 12:42:42 PM PST 24
Peak memory 208696 kb
Host smart-abbf359e-59b1-457a-bdf0-80d3c08917db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875475558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2875475558
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3343491807
Short name T2
Test name
Test status
Simulation time 58922144 ps
CPU time 3.31 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:27 PM PST 24
Peak memory 209804 kb
Host smart-421c53b6-670b-460e-bc29-f1826ce134d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343491807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3343491807
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1066179139
Short name T625
Test name
Test status
Simulation time 9491213 ps
CPU time 0.81 seconds
Started Mar 02 12:42:31 PM PST 24
Finished Mar 02 12:42:32 PM PST 24
Peak memory 205880 kb
Host smart-176fcf81-1b1c-4abe-9744-83d77a0aa8f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066179139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1066179139
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2180495749
Short name T215
Test name
Test status
Simulation time 44362509 ps
CPU time 2.97 seconds
Started Mar 02 12:42:36 PM PST 24
Finished Mar 02 12:42:39 PM PST 24
Peak memory 214260 kb
Host smart-ac67ef3f-96ae-4a02-a0d1-8a4ca9f1df86
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2180495749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2180495749
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3274807320
Short name T62
Test name
Test status
Simulation time 1039610985 ps
CPU time 8.28 seconds
Started Mar 02 12:42:30 PM PST 24
Finished Mar 02 12:42:38 PM PST 24
Peak memory 222828 kb
Host smart-189e29a6-b7dc-4b78-a0d7-d0dd5bb0d28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274807320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3274807320
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.223518954
Short name T784
Test name
Test status
Simulation time 810482582 ps
CPU time 19.96 seconds
Started Mar 02 12:42:33 PM PST 24
Finished Mar 02 12:42:53 PM PST 24
Peak memory 214312 kb
Host smart-b6e78850-42cf-4830-8283-b45c084cd6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223518954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.223518954
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1935287453
Short name T980
Test name
Test status
Simulation time 301221693 ps
CPU time 3.83 seconds
Started Mar 02 12:42:34 PM PST 24
Finished Mar 02 12:42:38 PM PST 24
Peak memory 208392 kb
Host smart-784b104a-e324-4f02-9a11-b53d63779000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935287453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1935287453
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1977234305
Short name T1058
Test name
Test status
Simulation time 231640636 ps
CPU time 2.21 seconds
Started Mar 02 12:42:32 PM PST 24
Finished Mar 02 12:42:35 PM PST 24
Peak memory 214300 kb
Host smart-7df1e25c-2499-4dd2-9614-5a641c823ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977234305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1977234305
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3764326036
Short name T272
Test name
Test status
Simulation time 240601833 ps
CPU time 6.81 seconds
Started Mar 02 12:42:33 PM PST 24
Finished Mar 02 12:42:40 PM PST 24
Peak memory 210136 kb
Host smart-3af62def-2c2d-48e3-bb40-93433fa15baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764326036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3764326036
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.419974910
Short name T224
Test name
Test status
Simulation time 2328364123 ps
CPU time 9.4 seconds
Started Mar 02 12:42:23 PM PST 24
Finished Mar 02 12:42:32 PM PST 24
Peak memory 208688 kb
Host smart-290597cd-ad0b-4b8f-8457-9a1c2e4d014e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419974910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.419974910
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.50895586
Short name T648
Test name
Test status
Simulation time 54696004 ps
CPU time 3 seconds
Started Mar 02 12:42:33 PM PST 24
Finished Mar 02 12:42:36 PM PST 24
Peak memory 206816 kb
Host smart-fd0078fc-9331-41cf-84dc-4bf4d7098928
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50895586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.50895586
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.354255085
Short name T92
Test name
Test status
Simulation time 73035065 ps
CPU time 2.42 seconds
Started Mar 02 12:42:31 PM PST 24
Finished Mar 02 12:42:33 PM PST 24
Peak memory 206712 kb
Host smart-bc50bf5e-2de3-4e64-84ce-73319a631263
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354255085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.354255085
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2723203199
Short name T75
Test name
Test status
Simulation time 98776757 ps
CPU time 2.73 seconds
Started Mar 02 12:42:34 PM PST 24
Finished Mar 02 12:42:36 PM PST 24
Peak memory 206880 kb
Host smart-0ca57205-7d3d-4baa-9f66-5cf143290ca4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723203199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2723203199
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2069804638
Short name T76
Test name
Test status
Simulation time 195719386 ps
CPU time 7.01 seconds
Started Mar 02 12:42:31 PM PST 24
Finished Mar 02 12:42:38 PM PST 24
Peak memory 214180 kb
Host smart-d1dce49d-0ec0-47a9-8adb-4eb694989da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069804638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2069804638
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.445934097
Short name T806
Test name
Test status
Simulation time 32146246 ps
CPU time 2.22 seconds
Started Mar 02 12:42:28 PM PST 24
Finished Mar 02 12:42:30 PM PST 24
Peak memory 206616 kb
Host smart-3b7d8faa-6f56-47ab-9ba3-1665cb0092e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445934097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.445934097
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3788664480
Short name T241
Test name
Test status
Simulation time 123953538 ps
CPU time 5.24 seconds
Started Mar 02 12:42:36 PM PST 24
Finished Mar 02 12:42:42 PM PST 24
Peak memory 209780 kb
Host smart-a24539ce-996e-4b9e-9def-ed14bb5c89c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788664480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3788664480
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3643764930
Short name T913
Test name
Test status
Simulation time 47431997 ps
CPU time 2.44 seconds
Started Mar 02 12:42:33 PM PST 24
Finished Mar 02 12:42:36 PM PST 24
Peak memory 209952 kb
Host smart-a510ed0d-052a-4c68-8e77-ef038657d9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643764930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3643764930
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1637056177
Short name T660
Test name
Test status
Simulation time 14049724 ps
CPU time 0.98 seconds
Started Mar 02 12:42:34 PM PST 24
Finished Mar 02 12:42:35 PM PST 24
Peak memory 206052 kb
Host smart-275f1b92-07bc-4a84-b0f2-434edce707c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637056177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1637056177
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2579619815
Short name T276
Test name
Test status
Simulation time 65319720 ps
CPU time 4.42 seconds
Started Mar 02 12:42:31 PM PST 24
Finished Mar 02 12:42:36 PM PST 24
Peak memory 214228 kb
Host smart-a2f47d8e-d153-4015-b460-1981f3ab6b24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2579619815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2579619815
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1247442029
Short name T767
Test name
Test status
Simulation time 52841063 ps
CPU time 3.3 seconds
Started Mar 02 12:42:35 PM PST 24
Finished Mar 02 12:42:38 PM PST 24
Peak memory 222340 kb
Host smart-eb5ab3d4-4ac2-4ca4-ad27-daba4810da88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247442029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1247442029
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.318469087
Short name T346
Test name
Test status
Simulation time 117211653 ps
CPU time 3.19 seconds
Started Mar 02 12:42:41 PM PST 24
Finished Mar 02 12:42:44 PM PST 24
Peak memory 207912 kb
Host smart-b40b73ff-6bbe-4387-98e5-5e18d7a8af95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318469087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.318469087
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3807407451
Short name T948
Test name
Test status
Simulation time 540070081 ps
CPU time 5.74 seconds
Started Mar 02 12:42:33 PM PST 24
Finished Mar 02 12:42:38 PM PST 24
Peak memory 214148 kb
Host smart-b7487c30-4b1e-4c03-b665-1458e346e254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807407451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3807407451
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1632478651
Short name T367
Test name
Test status
Simulation time 307940602 ps
CPU time 9.72 seconds
Started Mar 02 12:42:30 PM PST 24
Finished Mar 02 12:42:40 PM PST 24
Peak memory 210956 kb
Host smart-f8aa3309-b8a8-4d3f-82e3-ccaf6fcc03b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632478651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1632478651
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.98428364
Short name T202
Test name
Test status
Simulation time 63896010 ps
CPU time 3.19 seconds
Started Mar 02 12:42:36 PM PST 24
Finished Mar 02 12:42:39 PM PST 24
Peak memory 209956 kb
Host smart-cbb51841-2bd9-480e-86a7-024607eddb05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98428364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.98428364
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3523637024
Short name T867
Test name
Test status
Simulation time 1219056229 ps
CPU time 40.78 seconds
Started Mar 02 12:42:36 PM PST 24
Finished Mar 02 12:43:16 PM PST 24
Peak memory 209224 kb
Host smart-3ee25f80-afa8-4289-b1e5-525f4a60768b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523637024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3523637024
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1112826504
Short name T335
Test name
Test status
Simulation time 369453462 ps
CPU time 4 seconds
Started Mar 02 12:42:33 PM PST 24
Finished Mar 02 12:42:37 PM PST 24
Peak memory 208920 kb
Host smart-aa864f7b-5732-4521-ad5a-0388916208f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112826504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1112826504
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.414590076
Short name T359
Test name
Test status
Simulation time 62992853 ps
CPU time 2.33 seconds
Started Mar 02 12:42:36 PM PST 24
Finished Mar 02 12:42:38 PM PST 24
Peak memory 207240 kb
Host smart-511cb3de-3dcd-4aa9-8663-bf414070aac8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414590076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.414590076
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3796254185
Short name T861
Test name
Test status
Simulation time 36704491 ps
CPU time 2.22 seconds
Started Mar 02 12:42:34 PM PST 24
Finished Mar 02 12:42:37 PM PST 24
Peak memory 206828 kb
Host smart-375e1a17-1e8d-48dc-bea4-474a041b22a7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796254185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3796254185
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2823729967
Short name T962
Test name
Test status
Simulation time 45754509 ps
CPU time 2.58 seconds
Started Mar 02 12:42:34 PM PST 24
Finished Mar 02 12:42:37 PM PST 24
Peak memory 208224 kb
Host smart-4171ae9d-e7a2-4117-aa88-7ebc48747175
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823729967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2823729967
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2450164165
Short name T915
Test name
Test status
Simulation time 1438130145 ps
CPU time 3.13 seconds
Started Mar 02 12:42:34 PM PST 24
Finished Mar 02 12:42:37 PM PST 24
Peak memory 215848 kb
Host smart-b7405def-fb98-4c52-ad79-e1304ce671f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450164165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2450164165
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2857002141
Short name T906
Test name
Test status
Simulation time 898140675 ps
CPU time 9.09 seconds
Started Mar 02 12:42:32 PM PST 24
Finished Mar 02 12:42:41 PM PST 24
Peak memory 207680 kb
Host smart-5a28d269-59eb-4f0c-a1f2-ec841c2a5d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857002141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2857002141
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.463622737
Short name T796
Test name
Test status
Simulation time 164121091 ps
CPU time 5.2 seconds
Started Mar 02 12:42:29 PM PST 24
Finished Mar 02 12:42:35 PM PST 24
Peak memory 219828 kb
Host smart-6c166d4e-95d6-46b9-a3ca-6e7c990c85ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463622737 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.463622737
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.4055728358
Short name T365
Test name
Test status
Simulation time 344838163 ps
CPU time 4.39 seconds
Started Mar 02 12:42:34 PM PST 24
Finished Mar 02 12:42:38 PM PST 24
Peak memory 214312 kb
Host smart-1bc3d794-1e80-437f-a68c-7bcfa732f616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055728358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.4055728358
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3019314063
Short name T149
Test name
Test status
Simulation time 44082281 ps
CPU time 2.61 seconds
Started Mar 02 12:42:32 PM PST 24
Finished Mar 02 12:42:35 PM PST 24
Peak memory 210352 kb
Host smart-67c6a4bc-f009-4501-8ccf-7363425d9f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019314063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3019314063
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3995411174
Short name T413
Test name
Test status
Simulation time 69191774 ps
CPU time 0.72 seconds
Started Mar 02 12:39:58 PM PST 24
Finished Mar 02 12:40:00 PM PST 24
Peak memory 205780 kb
Host smart-59d0cf5c-000c-4904-b1d6-7a02d91f0add
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995411174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3995411174
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1275202269
Short name T400
Test name
Test status
Simulation time 300355167 ps
CPU time 16.07 seconds
Started Mar 02 12:39:58 PM PST 24
Finished Mar 02 12:40:15 PM PST 24
Peak memory 215212 kb
Host smart-4168721f-70d2-40be-8f67-aecc706fb7c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1275202269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1275202269
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2481578657
Short name T69
Test name
Test status
Simulation time 189113139 ps
CPU time 3.64 seconds
Started Mar 02 12:39:57 PM PST 24
Finished Mar 02 12:40:01 PM PST 24
Peak memory 207356 kb
Host smart-125e43bb-71a1-4cb2-bc58-1709cacf026f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481578657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2481578657
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.4162067242
Short name T819
Test name
Test status
Simulation time 138933166 ps
CPU time 2.48 seconds
Started Mar 02 12:39:55 PM PST 24
Finished Mar 02 12:39:58 PM PST 24
Peak memory 219960 kb
Host smart-3bc00834-a4d8-4907-9acc-24fb74c4abae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162067242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.4162067242
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.898233789
Short name T329
Test name
Test status
Simulation time 2795483813 ps
CPU time 13.46 seconds
Started Mar 02 12:39:56 PM PST 24
Finished Mar 02 12:40:11 PM PST 24
Peak memory 214356 kb
Host smart-350b42de-630a-4688-9f5f-dd34b4df2037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898233789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.898233789
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2996065298
Short name T644
Test name
Test status
Simulation time 83172694 ps
CPU time 3.7 seconds
Started Mar 02 12:39:59 PM PST 24
Finished Mar 02 12:40:03 PM PST 24
Peak memory 222448 kb
Host smart-b20ce971-edbc-478c-b8ad-2a63ad3452f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996065298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2996065298
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.766839000
Short name T357
Test name
Test status
Simulation time 2117134174 ps
CPU time 7.75 seconds
Started Mar 02 12:39:57 PM PST 24
Finished Mar 02 12:40:05 PM PST 24
Peak memory 208540 kb
Host smart-2cebbde7-c3c8-4eec-8526-8c3269cda50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766839000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.766839000
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2669109879
Short name T10
Test name
Test status
Simulation time 2924393570 ps
CPU time 62.85 seconds
Started Mar 02 12:39:55 PM PST 24
Finished Mar 02 12:40:58 PM PST 24
Peak memory 235692 kb
Host smart-d05102d7-e242-429a-8c3f-c5f187e5c719
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669109879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2669109879
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2980103185
Short name T1022
Test name
Test status
Simulation time 253249725 ps
CPU time 7.69 seconds
Started Mar 02 12:39:57 PM PST 24
Finished Mar 02 12:40:06 PM PST 24
Peak memory 208364 kb
Host smart-e116d345-0b10-4c8f-964d-524177b62dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980103185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2980103185
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2413426076
Short name T718
Test name
Test status
Simulation time 1247275501 ps
CPU time 8.44 seconds
Started Mar 02 12:39:54 PM PST 24
Finished Mar 02 12:40:03 PM PST 24
Peak memory 208580 kb
Host smart-16b5c33d-25b9-4003-b758-401e213ebacf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413426076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2413426076
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2629387680
Short name T545
Test name
Test status
Simulation time 65115290 ps
CPU time 3.07 seconds
Started Mar 02 12:39:56 PM PST 24
Finished Mar 02 12:40:00 PM PST 24
Peak memory 206940 kb
Host smart-37667c4e-b079-4553-94f7-81e65aaff684
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629387680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2629387680
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3540227924
Short name T674
Test name
Test status
Simulation time 33404167 ps
CPU time 2.29 seconds
Started Mar 02 12:39:58 PM PST 24
Finished Mar 02 12:40:00 PM PST 24
Peak memory 207416 kb
Host smart-85a6723b-c31e-4898-88c5-aa53c0a1ad2a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540227924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3540227924
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.4140687927
Short name T1056
Test name
Test status
Simulation time 252918197 ps
CPU time 8.44 seconds
Started Mar 02 12:39:55 PM PST 24
Finished Mar 02 12:40:03 PM PST 24
Peak memory 209640 kb
Host smart-36657d17-08f2-4b44-9376-50cb16ec83c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140687927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.4140687927
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1528132558
Short name T18
Test name
Test status
Simulation time 7540135249 ps
CPU time 52.12 seconds
Started Mar 02 12:39:55 PM PST 24
Finished Mar 02 12:40:47 PM PST 24
Peak memory 208984 kb
Host smart-71d5bfae-7981-4b18-80fe-562ffd2368b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528132558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1528132558
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3428722671
Short name T1023
Test name
Test status
Simulation time 5798622651 ps
CPU time 124.64 seconds
Started Mar 02 12:39:57 PM PST 24
Finished Mar 02 12:42:02 PM PST 24
Peak memory 222400 kb
Host smart-6a4de412-dc21-4db1-8c5d-f52c423f8797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428722671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3428722671
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3015890501
Short name T1010
Test name
Test status
Simulation time 403878522 ps
CPU time 8.61 seconds
Started Mar 02 12:39:59 PM PST 24
Finished Mar 02 12:40:08 PM PST 24
Peak memory 214268 kb
Host smart-64a48827-8099-44fb-aa2f-74c54599dce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015890501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3015890501
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2206226212
Short name T576
Test name
Test status
Simulation time 99357928 ps
CPU time 1.81 seconds
Started Mar 02 12:39:54 PM PST 24
Finished Mar 02 12:39:56 PM PST 24
Peak memory 209684 kb
Host smart-d320b9c0-1d08-47af-8bb7-a9e173f0dd8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206226212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2206226212
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.120679322
Short name T559
Test name
Test status
Simulation time 10446426 ps
CPU time 0.75 seconds
Started Mar 02 12:42:36 PM PST 24
Finished Mar 02 12:42:36 PM PST 24
Peak memory 205808 kb
Host smart-63ba59b9-a249-4dbd-9489-465401c23084
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120679322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.120679322
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1129363324
Short name T259
Test name
Test status
Simulation time 3912374936 ps
CPU time 64.4 seconds
Started Mar 02 12:42:36 PM PST 24
Finished Mar 02 12:43:41 PM PST 24
Peak memory 222572 kb
Host smart-7f1e1437-a161-44de-8e83-23bc99806768
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129363324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1129363324
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1019768544
Short name T65
Test name
Test status
Simulation time 31452805 ps
CPU time 1.9 seconds
Started Mar 02 12:42:37 PM PST 24
Finished Mar 02 12:42:39 PM PST 24
Peak memory 208272 kb
Host smart-f0bc81eb-3bd8-4e71-b1ba-6dd22a59f8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019768544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1019768544
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.3156687908
Short name T82
Test name
Test status
Simulation time 510505777 ps
CPU time 6.02 seconds
Started Mar 02 12:42:33 PM PST 24
Finished Mar 02 12:42:39 PM PST 24
Peak memory 218636 kb
Host smart-3a521f80-ece7-41f0-b1c6-a636334ef553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156687908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.3156687908
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3701295347
Short name T731
Test name
Test status
Simulation time 180672356 ps
CPU time 2.89 seconds
Started Mar 02 12:42:35 PM PST 24
Finished Mar 02 12:42:38 PM PST 24
Peak memory 219884 kb
Host smart-0532ac36-45ba-45d5-821a-1b4f98ec3131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701295347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3701295347
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1457188844
Short name T842
Test name
Test status
Simulation time 35367519 ps
CPU time 2.53 seconds
Started Mar 02 12:42:34 PM PST 24
Finished Mar 02 12:42:37 PM PST 24
Peak memory 209400 kb
Host smart-c3eadbb0-fa41-429a-aabb-46d844e3f0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457188844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1457188844
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2977564395
Short name T958
Test name
Test status
Simulation time 905359911 ps
CPU time 7.81 seconds
Started Mar 02 12:42:37 PM PST 24
Finished Mar 02 12:42:44 PM PST 24
Peak memory 208404 kb
Host smart-e4cd1cd3-e967-4964-b61e-b3d75a37c8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977564395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2977564395
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.175729786
Short name T383
Test name
Test status
Simulation time 128909828 ps
CPU time 2.52 seconds
Started Mar 02 12:42:34 PM PST 24
Finished Mar 02 12:42:37 PM PST 24
Peak memory 207396 kb
Host smart-297cf052-6615-4b07-a73c-493387f34cdd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175729786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.175729786
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2563796160
Short name T646
Test name
Test status
Simulation time 822720441 ps
CPU time 6.67 seconds
Started Mar 02 12:42:36 PM PST 24
Finished Mar 02 12:42:42 PM PST 24
Peak memory 208932 kb
Host smart-c0242e8a-481d-4af7-ac9c-26daa538c42d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563796160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2563796160
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3750742318
Short name T817
Test name
Test status
Simulation time 135882715 ps
CPU time 2.5 seconds
Started Mar 02 12:42:33 PM PST 24
Finished Mar 02 12:42:35 PM PST 24
Peak memory 207240 kb
Host smart-3c1b80d0-b6e4-419e-96c4-2db79396088f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750742318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3750742318
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1195855360
Short name T675
Test name
Test status
Simulation time 65932231 ps
CPU time 3.18 seconds
Started Mar 02 12:42:35 PM PST 24
Finished Mar 02 12:42:38 PM PST 24
Peak memory 218372 kb
Host smart-b2610240-1344-4bae-9bd3-0ef918e5ccb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195855360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1195855360
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.4206306086
Short name T836
Test name
Test status
Simulation time 141814392 ps
CPU time 4.21 seconds
Started Mar 02 12:42:34 PM PST 24
Finished Mar 02 12:42:39 PM PST 24
Peak memory 206852 kb
Host smart-7c188c6d-e08b-4308-90c2-a5edc508ea6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206306086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.4206306086
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.907529593
Short name T363
Test name
Test status
Simulation time 4366854512 ps
CPU time 52.75 seconds
Started Mar 02 12:42:34 PM PST 24
Finished Mar 02 12:43:26 PM PST 24
Peak memory 222396 kb
Host smart-ea4d188a-34a5-440f-af60-61fea8a7de65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907529593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.907529593
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2268342396
Short name T95
Test name
Test status
Simulation time 624307719 ps
CPU time 19.17 seconds
Started Mar 02 12:42:35 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 207880 kb
Host smart-32640891-e659-4859-8d7d-bd1582aae4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268342396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2268342396
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1703510030
Short name T134
Test name
Test status
Simulation time 77301560 ps
CPU time 3.19 seconds
Started Mar 02 12:42:33 PM PST 24
Finished Mar 02 12:42:36 PM PST 24
Peak memory 209932 kb
Host smart-73a7012f-99ae-4be8-9140-2acbfe47ab86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703510030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1703510030
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1910285206
Short name T687
Test name
Test status
Simulation time 13882053 ps
CPU time 0.83 seconds
Started Mar 02 12:42:48 PM PST 24
Finished Mar 02 12:42:50 PM PST 24
Peak memory 205876 kb
Host smart-ac6b295a-84f5-43af-a461-94f1d5a8ad49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910285206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1910285206
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2317848894
Short name T254
Test name
Test status
Simulation time 1236218206 ps
CPU time 14.94 seconds
Started Mar 02 12:42:50 PM PST 24
Finished Mar 02 12:43:05 PM PST 24
Peak memory 215004 kb
Host smart-8081b60e-5a15-4697-a52a-5e1bddb74cad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2317848894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2317848894
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.4021980023
Short name T1009
Test name
Test status
Simulation time 143525883 ps
CPU time 5.09 seconds
Started Mar 02 12:42:53 PM PST 24
Finished Mar 02 12:42:58 PM PST 24
Peak memory 209820 kb
Host smart-541ca190-7ea1-46eb-9e21-ed823950e93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021980023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.4021980023
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.844089703
Short name T1035
Test name
Test status
Simulation time 63046129 ps
CPU time 3.09 seconds
Started Mar 02 12:42:53 PM PST 24
Finished Mar 02 12:42:57 PM PST 24
Peak memory 209304 kb
Host smart-90300394-507c-469f-882b-f54d959c637c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844089703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.844089703
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2974715289
Short name T352
Test name
Test status
Simulation time 290028495 ps
CPU time 5.49 seconds
Started Mar 02 12:42:54 PM PST 24
Finished Mar 02 12:43:00 PM PST 24
Peak memory 214272 kb
Host smart-623fbe30-eaeb-4bc1-89a9-3475a5dc62bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974715289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2974715289
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2988506935
Short name T341
Test name
Test status
Simulation time 246700383 ps
CPU time 3.23 seconds
Started Mar 02 12:42:51 PM PST 24
Finished Mar 02 12:42:55 PM PST 24
Peak memory 209804 kb
Host smart-852f9f82-bfa7-4dcf-a532-91a395d9fd87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988506935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2988506935
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3725477672
Short name T320
Test name
Test status
Simulation time 308133195 ps
CPU time 3.95 seconds
Started Mar 02 12:42:49 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 208132 kb
Host smart-a02e4273-acc5-499f-ab2a-da26dc76c3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725477672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3725477672
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.332388044
Short name T852
Test name
Test status
Simulation time 366114764 ps
CPU time 4.18 seconds
Started Mar 02 12:42:35 PM PST 24
Finished Mar 02 12:42:40 PM PST 24
Peak memory 208328 kb
Host smart-b41b00f0-0cf6-411a-9d46-382442c2c69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332388044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.332388044
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2931680174
Short name T360
Test name
Test status
Simulation time 8728029311 ps
CPU time 100.85 seconds
Started Mar 02 12:42:35 PM PST 24
Finished Mar 02 12:44:16 PM PST 24
Peak memory 208216 kb
Host smart-0b90e32c-a410-439e-9564-6ecd396eefa7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931680174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2931680174
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1604825753
Short name T690
Test name
Test status
Simulation time 310445275 ps
CPU time 3.57 seconds
Started Mar 02 12:42:34 PM PST 24
Finished Mar 02 12:42:37 PM PST 24
Peak memory 208780 kb
Host smart-6f77f6ab-eb53-4489-92f9-3f5db2ba118a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604825753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1604825753
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.20524517
Short name T917
Test name
Test status
Simulation time 341341519 ps
CPU time 3.57 seconds
Started Mar 02 12:42:50 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 208640 kb
Host smart-e2e7f601-b5ee-4fb4-8aa3-a862341baeb5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20524517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.20524517
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.4282868774
Short name T905
Test name
Test status
Simulation time 658683300 ps
CPU time 2.87 seconds
Started Mar 02 12:42:51 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 210340 kb
Host smart-dc9826b2-862b-42f9-98a9-50a74c4fbcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282868774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.4282868774
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2157202288
Short name T854
Test name
Test status
Simulation time 271404820 ps
CPU time 3.17 seconds
Started Mar 02 12:42:35 PM PST 24
Finished Mar 02 12:42:39 PM PST 24
Peak memory 208376 kb
Host smart-0a257f5b-6f63-475b-a1e6-e67d86f238c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157202288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2157202288
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2840947132
Short name T237
Test name
Test status
Simulation time 2705637399 ps
CPU time 21.26 seconds
Started Mar 02 12:42:50 PM PST 24
Finished Mar 02 12:43:12 PM PST 24
Peak memory 222412 kb
Host smart-e78d045c-2eaa-4b58-a8c7-c415be2c1a4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840947132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2840947132
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2402242852
Short name T398
Test name
Test status
Simulation time 454272586 ps
CPU time 10.48 seconds
Started Mar 02 12:42:48 PM PST 24
Finished Mar 02 12:43:00 PM PST 24
Peak memory 220524 kb
Host smart-88ef48bb-0d2b-4fbd-a87a-adc649471c3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402242852 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2402242852
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1178640071
Short name T234
Test name
Test status
Simulation time 535396291 ps
CPU time 6.08 seconds
Started Mar 02 12:42:48 PM PST 24
Finished Mar 02 12:42:55 PM PST 24
Peak memory 218700 kb
Host smart-e55033ad-c705-4078-abe3-56284e4d8484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178640071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1178640071
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.4131479852
Short name T1024
Test name
Test status
Simulation time 71554995 ps
CPU time 1.99 seconds
Started Mar 02 12:42:49 PM PST 24
Finished Mar 02 12:42:52 PM PST 24
Peak memory 209932 kb
Host smart-f025d3ec-1e78-4ec4-a869-9a40499ead50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131479852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.4131479852
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.4150812870
Short name T604
Test name
Test status
Simulation time 20200271 ps
CPU time 0.77 seconds
Started Mar 02 12:42:50 PM PST 24
Finished Mar 02 12:42:51 PM PST 24
Peak memory 205864 kb
Host smart-c586ba0a-4666-49bc-8ace-69801fd44f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150812870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.4150812870
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2176793252
Short name T404
Test name
Test status
Simulation time 63794169 ps
CPU time 4.28 seconds
Started Mar 02 12:42:49 PM PST 24
Finished Mar 02 12:42:55 PM PST 24
Peak memory 215016 kb
Host smart-7bdba2c0-6f4c-4be5-a71d-b9fa40d1b3a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2176793252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2176793252
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3044578119
Short name T63
Test name
Test status
Simulation time 29435110 ps
CPU time 1.69 seconds
Started Mar 02 12:42:48 PM PST 24
Finished Mar 02 12:42:52 PM PST 24
Peak memory 208592 kb
Host smart-ed379971-ef93-4c89-ad38-460a5184f77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044578119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3044578119
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.4101765729
Short name T21
Test name
Test status
Simulation time 62359790 ps
CPU time 3.73 seconds
Started Mar 02 12:42:49 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 209192 kb
Host smart-a31df8bd-24cc-4ca0-be13-c34ced723ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101765729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4101765729
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.4007489970
Short name T347
Test name
Test status
Simulation time 2016028679 ps
CPU time 22.87 seconds
Started Mar 02 12:42:50 PM PST 24
Finished Mar 02 12:43:13 PM PST 24
Peak memory 214256 kb
Host smart-a5fe1aab-14b5-4fa3-a0a2-606ebc51ebd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007489970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.4007489970
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.723268114
Short name T207
Test name
Test status
Simulation time 1000517157 ps
CPU time 27.03 seconds
Started Mar 02 12:42:47 PM PST 24
Finished Mar 02 12:43:14 PM PST 24
Peak memory 222436 kb
Host smart-9b5a2d12-e7b1-485e-8980-3a1ba00c800f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723268114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.723268114
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2173502790
Short name T350
Test name
Test status
Simulation time 6605697588 ps
CPU time 35.93 seconds
Started Mar 02 12:42:51 PM PST 24
Finished Mar 02 12:43:27 PM PST 24
Peak memory 209644 kb
Host smart-0f46c523-0d3e-4f7d-8f46-d4b25730ed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173502790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2173502790
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2673314810
Short name T876
Test name
Test status
Simulation time 736317158 ps
CPU time 2.38 seconds
Started Mar 02 12:42:53 PM PST 24
Finished Mar 02 12:42:56 PM PST 24
Peak memory 206672 kb
Host smart-8ca4b169-ede9-4c84-a80c-186754869407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673314810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2673314810
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1876833540
Short name T563
Test name
Test status
Simulation time 128452858 ps
CPU time 2.92 seconds
Started Mar 02 12:42:50 PM PST 24
Finished Mar 02 12:42:53 PM PST 24
Peak memory 208868 kb
Host smart-0b51bb39-54d2-46cd-b586-39d7dfca3a9b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876833540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1876833540
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.286421012
Short name T1040
Test name
Test status
Simulation time 1768357120 ps
CPU time 31.22 seconds
Started Mar 02 12:42:52 PM PST 24
Finished Mar 02 12:43:24 PM PST 24
Peak memory 208908 kb
Host smart-b14d79d5-396f-4dc2-a32b-5f7d4cb28c73
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286421012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.286421012
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3689857815
Short name T655
Test name
Test status
Simulation time 3088833146 ps
CPU time 41.19 seconds
Started Mar 02 12:42:48 PM PST 24
Finished Mar 02 12:43:31 PM PST 24
Peak memory 207884 kb
Host smart-e7bf3135-a1aa-45b4-8270-8ab06066f422
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689857815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3689857815
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.4086457424
Short name T952
Test name
Test status
Simulation time 59927016 ps
CPU time 1.45 seconds
Started Mar 02 12:42:51 PM PST 24
Finished Mar 02 12:42:53 PM PST 24
Peak memory 206836 kb
Host smart-aa15040a-d060-4a49-a83a-738e6393092d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086457424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.4086457424
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2371496558
Short name T950
Test name
Test status
Simulation time 34407899 ps
CPU time 2.25 seconds
Started Mar 02 12:42:49 PM PST 24
Finished Mar 02 12:42:53 PM PST 24
Peak memory 206748 kb
Host smart-c5503de1-2d6e-4089-8382-26d18ce3d3ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371496558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2371496558
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.719779214
Short name T212
Test name
Test status
Simulation time 714026472 ps
CPU time 15.35 seconds
Started Mar 02 12:42:49 PM PST 24
Finished Mar 02 12:43:06 PM PST 24
Peak memory 216092 kb
Host smart-59d0c7f6-911e-4b8a-a4bc-5c81698bc97b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719779214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.719779214
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2774856635
Short name T98
Test name
Test status
Simulation time 388598539 ps
CPU time 3.42 seconds
Started Mar 02 12:42:49 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 222544 kb
Host smart-d250de4c-69a6-48f6-a8c3-27a93cdf3707
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774856635 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2774856635
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.440269698
Short name T395
Test name
Test status
Simulation time 1203579977 ps
CPU time 13.01 seconds
Started Mar 02 12:42:51 PM PST 24
Finished Mar 02 12:43:04 PM PST 24
Peak memory 209484 kb
Host smart-add5b450-ca58-41a9-9543-084180f8f78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440269698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.440269698
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1738275160
Short name T543
Test name
Test status
Simulation time 319150396 ps
CPU time 3.28 seconds
Started Mar 02 12:42:51 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 209936 kb
Host smart-e8f6368d-b915-43e4-9f6a-88e4f2a2178b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738275160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1738275160
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2816019610
Short name T689
Test name
Test status
Simulation time 55524652 ps
CPU time 0.82 seconds
Started Mar 02 12:42:51 PM PST 24
Finished Mar 02 12:42:52 PM PST 24
Peak memory 205892 kb
Host smart-1e8da06d-5f33-4f80-8305-822bd27d7357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816019610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2816019610
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.862361335
Short name T214
Test name
Test status
Simulation time 361251458 ps
CPU time 4.56 seconds
Started Mar 02 12:42:50 PM PST 24
Finished Mar 02 12:42:55 PM PST 24
Peak memory 214288 kb
Host smart-862c53f8-64de-42e8-b0b3-57e526a774fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=862361335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.862361335
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3995744384
Short name T338
Test name
Test status
Simulation time 182475651 ps
CPU time 2.67 seconds
Started Mar 02 12:42:48 PM PST 24
Finished Mar 02 12:42:52 PM PST 24
Peak memory 209500 kb
Host smart-b353e658-ad60-4e8a-a3c0-2e3b9b952337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995744384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3995744384
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.4233666108
Short name T960
Test name
Test status
Simulation time 167048778 ps
CPU time 4.53 seconds
Started Mar 02 12:42:48 PM PST 24
Finished Mar 02 12:42:55 PM PST 24
Peak memory 209440 kb
Host smart-2f441c5b-466f-4bdf-993e-7a8dabdf5240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233666108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4233666108
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.607423298
Short name T247
Test name
Test status
Simulation time 128253398 ps
CPU time 5.51 seconds
Started Mar 02 12:42:53 PM PST 24
Finished Mar 02 12:42:59 PM PST 24
Peak memory 214296 kb
Host smart-ccf24067-7080-44f3-bd41-2537c0038f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607423298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.607423298
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3739735325
Short name T568
Test name
Test status
Simulation time 104208059 ps
CPU time 4.61 seconds
Started Mar 02 12:42:47 PM PST 24
Finished Mar 02 12:42:52 PM PST 24
Peak memory 214260 kb
Host smart-cf03e69e-351f-4762-a4e5-cc64e53de1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739735325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3739735325
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.758977585
Short name T361
Test name
Test status
Simulation time 212211006 ps
CPU time 3.78 seconds
Started Mar 02 12:42:48 PM PST 24
Finished Mar 02 12:42:53 PM PST 24
Peak memory 218372 kb
Host smart-367f9314-949b-4ef4-85d0-f4716576b2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758977585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.758977585
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2958930196
Short name T319
Test name
Test status
Simulation time 1204297517 ps
CPU time 6.03 seconds
Started Mar 02 12:42:52 PM PST 24
Finished Mar 02 12:42:58 PM PST 24
Peak memory 206768 kb
Host smart-c5958020-e8a8-4738-974c-573e3577712c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958930196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2958930196
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.4135766009
Short name T188
Test name
Test status
Simulation time 67818261 ps
CPU time 3.49 seconds
Started Mar 02 12:42:46 PM PST 24
Finished Mar 02 12:42:51 PM PST 24
Peak memory 206864 kb
Host smart-789b91b7-1063-46a1-952f-45456009f94c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135766009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4135766009
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3580215730
Short name T561
Test name
Test status
Simulation time 621498053 ps
CPU time 3.12 seconds
Started Mar 02 12:42:50 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 206708 kb
Host smart-8048aa94-814d-46c8-b498-5f6aa20c4986
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580215730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3580215730
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.979488285
Short name T763
Test name
Test status
Simulation time 258895954 ps
CPU time 2.98 seconds
Started Mar 02 12:42:48 PM PST 24
Finished Mar 02 12:42:53 PM PST 24
Peak memory 206928 kb
Host smart-71d29306-46fe-45bf-9549-dde3b8f69fd0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979488285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.979488285
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.267720490
Short name T678
Test name
Test status
Simulation time 159350415 ps
CPU time 3.8 seconds
Started Mar 02 12:42:50 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 214276 kb
Host smart-aa00f76f-70d9-4a7e-9fca-89f4d989a110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267720490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.267720490
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.900981270
Short name T1037
Test name
Test status
Simulation time 247353769 ps
CPU time 2.36 seconds
Started Mar 02 12:42:53 PM PST 24
Finished Mar 02 12:42:55 PM PST 24
Peak memory 208544 kb
Host smart-ed56aed1-8388-4b5a-8ea5-cc9c7fc8a2aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900981270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.900981270
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1886141518
Short name T606
Test name
Test status
Simulation time 204947981 ps
CPU time 2.75 seconds
Started Mar 02 12:42:49 PM PST 24
Finished Mar 02 12:42:53 PM PST 24
Peak memory 206952 kb
Host smart-7b833b4b-62f3-497e-9783-2d58f3412342
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886141518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1886141518
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.1826050863
Short name T904
Test name
Test status
Simulation time 95419805 ps
CPU time 3.15 seconds
Started Mar 02 12:42:49 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 218196 kb
Host smart-95b0414b-4153-4e5b-963f-b6f27e452f74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826050863 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.1826050863
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1978787233
Short name T928
Test name
Test status
Simulation time 46199039 ps
CPU time 3.13 seconds
Started Mar 02 12:42:52 PM PST 24
Finished Mar 02 12:42:55 PM PST 24
Peak memory 218260 kb
Host smart-1a3a5122-ed04-4a08-832f-0f7644ef6169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978787233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1978787233
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3587205104
Short name T585
Test name
Test status
Simulation time 199191784 ps
CPU time 1.88 seconds
Started Mar 02 12:42:50 PM PST 24
Finished Mar 02 12:42:52 PM PST 24
Peak memory 210172 kb
Host smart-ab6bd909-76cc-49e0-b58b-9cb596d69ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587205104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3587205104
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2286605666
Short name T595
Test name
Test status
Simulation time 13589273 ps
CPU time 0.92 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:03 PM PST 24
Peak memory 205788 kb
Host smart-13c2ec18-0bc7-455a-ac22-434fd434452d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286605666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2286605666
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.431100578
Short name T9
Test name
Test status
Simulation time 341518933 ps
CPU time 10.05 seconds
Started Mar 02 12:42:52 PM PST 24
Finished Mar 02 12:43:03 PM PST 24
Peak memory 216512 kb
Host smart-001e26a5-90a2-42d2-9075-57defd853e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431100578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.431100578
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.278042506
Short name T261
Test name
Test status
Simulation time 2144514497 ps
CPU time 23.49 seconds
Started Mar 02 12:42:50 PM PST 24
Finished Mar 02 12:43:14 PM PST 24
Peak memory 209436 kb
Host smart-985977d3-12d1-4e40-ba00-87bc8110cc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278042506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.278042506
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2916943997
Short name T993
Test name
Test status
Simulation time 1996301192 ps
CPU time 10.95 seconds
Started Mar 02 12:42:50 PM PST 24
Finished Mar 02 12:43:01 PM PST 24
Peak memory 211972 kb
Host smart-b543223e-e655-456f-aca4-3ccfd205c3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916943997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2916943997
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1125433104
Short name T48
Test name
Test status
Simulation time 325615124 ps
CPU time 8.93 seconds
Started Mar 02 12:42:47 PM PST 24
Finished Mar 02 12:42:57 PM PST 24
Peak memory 210412 kb
Host smart-4597a3f9-5aaf-4023-9905-7c70e22b81b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125433104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1125433104
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.4207990108
Short name T870
Test name
Test status
Simulation time 45920658 ps
CPU time 3.13 seconds
Started Mar 02 12:42:51 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 218452 kb
Host smart-44994dd8-d07d-4094-90a0-b5c6e8ace3e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207990108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.4207990108
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1472305811
Short name T570
Test name
Test status
Simulation time 117016993 ps
CPU time 2.95 seconds
Started Mar 02 12:42:51 PM PST 24
Finished Mar 02 12:42:55 PM PST 24
Peak memory 208256 kb
Host smart-53ef4a44-054b-4687-94d4-721092882223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472305811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1472305811
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3749009432
Short name T1015
Test name
Test status
Simulation time 67455194 ps
CPU time 1.96 seconds
Started Mar 02 12:42:51 PM PST 24
Finished Mar 02 12:42:53 PM PST 24
Peak memory 207496 kb
Host smart-c80ebfe8-9aab-4f92-8c2c-1a7e846d9f40
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749009432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3749009432
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3281050883
Short name T1011
Test name
Test status
Simulation time 233182374 ps
CPU time 2.56 seconds
Started Mar 02 12:42:49 PM PST 24
Finished Mar 02 12:42:53 PM PST 24
Peak memory 208712 kb
Host smart-54c506f1-5d5c-4100-860e-3db37b87566a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281050883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3281050883
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.946066482
Short name T873
Test name
Test status
Simulation time 7109678877 ps
CPU time 46.57 seconds
Started Mar 02 12:42:52 PM PST 24
Finished Mar 02 12:43:39 PM PST 24
Peak memory 207916 kb
Host smart-d589fb4c-c95f-4997-a24f-5fccd0188769
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946066482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.946066482
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.363997475
Short name T671
Test name
Test status
Simulation time 242562480 ps
CPU time 2.35 seconds
Started Mar 02 12:42:52 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 208956 kb
Host smart-504fe578-50b5-4cd8-a755-8f71c1af781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363997475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.363997475
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2974080015
Short name T1014
Test name
Test status
Simulation time 182522605 ps
CPU time 6.44 seconds
Started Mar 02 12:42:47 PM PST 24
Finished Mar 02 12:42:54 PM PST 24
Peak memory 208672 kb
Host smart-eb537913-f77a-471f-af0d-81069c84c228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974080015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2974080015
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2931691898
Short name T282
Test name
Test status
Simulation time 1819646694 ps
CPU time 35.02 seconds
Started Mar 02 12:42:56 PM PST 24
Finished Mar 02 12:43:31 PM PST 24
Peak memory 222412 kb
Host smart-29e1fc12-cc3d-435c-8b5a-db82f8d15817
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931691898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2931691898
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.2300066839
Short name T787
Test name
Test status
Simulation time 855705522 ps
CPU time 3.76 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:06 PM PST 24
Peak memory 222496 kb
Host smart-0a0bbcd5-5d29-4164-93b5-0265023375ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300066839 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.2300066839
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2464065860
Short name T923
Test name
Test status
Simulation time 659481978 ps
CPU time 9.46 seconds
Started Mar 02 12:42:50 PM PST 24
Finished Mar 02 12:43:00 PM PST 24
Peak memory 207992 kb
Host smart-5c00988f-1d26-4c61-ac76-3409d69fb8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464065860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2464065860
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3027329691
Short name T780
Test name
Test status
Simulation time 37996854 ps
CPU time 2.16 seconds
Started Mar 02 12:42:52 PM PST 24
Finished Mar 02 12:42:55 PM PST 24
Peak memory 209908 kb
Host smart-f5132f08-34a9-4d8d-ad23-8f1bf7e4b486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027329691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3027329691
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2299850974
Short name T1013
Test name
Test status
Simulation time 28790608 ps
CPU time 0.85 seconds
Started Mar 02 12:42:55 PM PST 24
Finished Mar 02 12:42:56 PM PST 24
Peak memory 205764 kb
Host smart-ee7f1faf-a1ef-45bf-9346-b2d1c7752c51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299850974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2299850974
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.485528263
Short name T283
Test name
Test status
Simulation time 189961467 ps
CPU time 7.01 seconds
Started Mar 02 12:42:56 PM PST 24
Finished Mar 02 12:43:03 PM PST 24
Peak memory 214304 kb
Host smart-3bb750b9-381c-4f9c-bb24-b551405eb9ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485528263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.485528263
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4140975821
Short name T994
Test name
Test status
Simulation time 1194824226 ps
CPU time 38.67 seconds
Started Mar 02 12:42:53 PM PST 24
Finished Mar 02 12:43:32 PM PST 24
Peak memory 209484 kb
Host smart-209e039d-3e4a-43a8-88bb-f40d017d873c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140975821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4140975821
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1517493745
Short name T878
Test name
Test status
Simulation time 186415448 ps
CPU time 2.29 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:04 PM PST 24
Peak memory 208164 kb
Host smart-9ed6c1e6-e78d-4645-8b2c-b767bace9cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517493745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1517493745
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3003052854
Short name T750
Test name
Test status
Simulation time 340291450 ps
CPU time 7.59 seconds
Started Mar 02 12:42:56 PM PST 24
Finished Mar 02 12:43:04 PM PST 24
Peak memory 214328 kb
Host smart-2cd66727-0667-4adb-807e-a43f989c4109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003052854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3003052854
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2662408361
Short name T249
Test name
Test status
Simulation time 496784860 ps
CPU time 7.34 seconds
Started Mar 02 12:42:57 PM PST 24
Finished Mar 02 12:43:04 PM PST 24
Peak memory 214244 kb
Host smart-0e57e376-a84a-44aa-9471-b2cc8c269dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662408361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2662408361
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3156231915
Short name T589
Test name
Test status
Simulation time 61627368 ps
CPU time 2.01 seconds
Started Mar 02 12:42:57 PM PST 24
Finished Mar 02 12:42:59 PM PST 24
Peak memory 205832 kb
Host smart-651b6e85-19a0-416d-ba04-33e8106ccce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156231915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3156231915
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2608137574
Short name T766
Test name
Test status
Simulation time 226299135 ps
CPU time 6.54 seconds
Started Mar 02 12:42:54 PM PST 24
Finished Mar 02 12:43:01 PM PST 24
Peak memory 217964 kb
Host smart-31ccd878-70d5-449b-a871-e62a176e6af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608137574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2608137574
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1825359796
Short name T599
Test name
Test status
Simulation time 63738652 ps
CPU time 3.14 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:05 PM PST 24
Peak memory 208060 kb
Host smart-b7a7ac5f-d2e0-4412-904c-a3da58832199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825359796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1825359796
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1005338902
Short name T235
Test name
Test status
Simulation time 862009320 ps
CPU time 5.48 seconds
Started Mar 02 12:42:57 PM PST 24
Finished Mar 02 12:43:03 PM PST 24
Peak memory 208428 kb
Host smart-43fe79f2-bc0b-4b47-80a7-ce4c658eb70d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005338902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1005338902
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1607749718
Short name T850
Test name
Test status
Simulation time 92852986 ps
CPU time 1.97 seconds
Started Mar 02 12:42:57 PM PST 24
Finished Mar 02 12:42:59 PM PST 24
Peak memory 206892 kb
Host smart-d65be0c4-342b-4261-93ad-04e856ba3418
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607749718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1607749718
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1095074456
Short name T720
Test name
Test status
Simulation time 2895519283 ps
CPU time 48.27 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:51 PM PST 24
Peak memory 208788 kb
Host smart-c49c208b-617f-4b18-bf79-8d49829fa6b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095074456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1095074456
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3497239732
Short name T358
Test name
Test status
Simulation time 456557504 ps
CPU time 10.23 seconds
Started Mar 02 12:42:57 PM PST 24
Finished Mar 02 12:43:07 PM PST 24
Peak memory 214216 kb
Host smart-106d8b61-fa99-424c-ad8a-68c25746f543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497239732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3497239732
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.4007708534
Short name T978
Test name
Test status
Simulation time 164542712 ps
CPU time 3.44 seconds
Started Mar 02 12:42:57 PM PST 24
Finished Mar 02 12:43:01 PM PST 24
Peak memory 208452 kb
Host smart-d96e9f85-c2d8-49bb-b6e2-799f469dc60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007708534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.4007708534
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.761669741
Short name T71
Test name
Test status
Simulation time 975212611 ps
CPU time 23.46 seconds
Started Mar 02 12:42:56 PM PST 24
Finished Mar 02 12:43:20 PM PST 24
Peak memory 222124 kb
Host smart-f75e4e8b-fb9e-4796-960b-df7850b0f8c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761669741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.761669741
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2327919977
Short name T250
Test name
Test status
Simulation time 1061461106 ps
CPU time 11.56 seconds
Started Mar 02 12:42:55 PM PST 24
Finished Mar 02 12:43:07 PM PST 24
Peak memory 214408 kb
Host smart-a569f9fa-6f08-4ed1-8dd4-48468f4c4428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327919977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2327919977
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3525703522
Short name T713
Test name
Test status
Simulation time 274157377 ps
CPU time 5.05 seconds
Started Mar 02 12:42:57 PM PST 24
Finished Mar 02 12:43:02 PM PST 24
Peak memory 210548 kb
Host smart-ed249784-8f76-4804-a244-787cde4b8f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525703522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3525703522
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2856934360
Short name T969
Test name
Test status
Simulation time 99831270 ps
CPU time 0.95 seconds
Started Mar 02 12:42:54 PM PST 24
Finished Mar 02 12:42:55 PM PST 24
Peak memory 205856 kb
Host smart-56c1b6f9-2518-4701-88b6-8e4c220db6dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856934360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2856934360
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.4148771039
Short name T722
Test name
Test status
Simulation time 1185994108 ps
CPU time 7.7 seconds
Started Mar 02 12:42:58 PM PST 24
Finished Mar 02 12:43:06 PM PST 24
Peak memory 209812 kb
Host smart-4bb63813-baa6-4d7a-9449-04fa3b61fb98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148771039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.4148771039
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.647381248
Short name T755
Test name
Test status
Simulation time 259867983 ps
CPU time 3.16 seconds
Started Mar 02 12:42:57 PM PST 24
Finished Mar 02 12:43:00 PM PST 24
Peak memory 208816 kb
Host smart-ba8a6342-6097-4a68-a019-8ce821524ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647381248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.647381248
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2744428070
Short name T779
Test name
Test status
Simulation time 1264729727 ps
CPU time 7.11 seconds
Started Mar 02 12:42:55 PM PST 24
Finished Mar 02 12:43:02 PM PST 24
Peak memory 208444 kb
Host smart-8889abae-787a-405c-8526-d7b959f41d26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744428070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2744428070
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.240233631
Short name T828
Test name
Test status
Simulation time 107377829 ps
CPU time 3.94 seconds
Started Mar 02 12:42:55 PM PST 24
Finished Mar 02 12:42:59 PM PST 24
Peak memory 220224 kb
Host smart-a749a5cf-2a35-4956-9334-79c7e010eb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240233631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.240233631
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2321200079
Short name T909
Test name
Test status
Simulation time 4746131655 ps
CPU time 53.38 seconds
Started Mar 02 12:42:58 PM PST 24
Finished Mar 02 12:43:51 PM PST 24
Peak memory 218572 kb
Host smart-6b474398-3d14-4fb2-b27d-71b1c7ab319c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321200079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2321200079
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2237147403
Short name T971
Test name
Test status
Simulation time 197055899 ps
CPU time 1.98 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:04 PM PST 24
Peak memory 208512 kb
Host smart-51ec7e84-0aff-4cff-91da-65fdfffe1e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237147403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2237147403
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.4128615832
Short name T926
Test name
Test status
Simulation time 210092309 ps
CPU time 6.91 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:09 PM PST 24
Peak memory 208336 kb
Host smart-7a01fd06-0c7f-46e1-a7d5-5980ae305f5d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128615832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.4128615832
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1347455333
Short name T275
Test name
Test status
Simulation time 587396392 ps
CPU time 6.03 seconds
Started Mar 02 12:42:55 PM PST 24
Finished Mar 02 12:43:02 PM PST 24
Peak memory 208624 kb
Host smart-d149cecb-1bf0-4d1d-bb89-58574b87416d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347455333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1347455333
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.883738766
Short name T12
Test name
Test status
Simulation time 318039431 ps
CPU time 3.22 seconds
Started Mar 02 12:43:06 PM PST 24
Finished Mar 02 12:43:09 PM PST 24
Peak memory 206872 kb
Host smart-49622be8-981a-4141-8cf7-4c749e0f6ac5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883738766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.883738766
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1899951450
Short name T833
Test name
Test status
Simulation time 322981340 ps
CPU time 6.41 seconds
Started Mar 02 12:43:00 PM PST 24
Finished Mar 02 12:43:06 PM PST 24
Peak memory 214220 kb
Host smart-068b2a08-ca2f-455a-8a8b-8c758a2ffe7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899951450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1899951450
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2046891481
Short name T999
Test name
Test status
Simulation time 212358323 ps
CPU time 4.55 seconds
Started Mar 02 12:42:56 PM PST 24
Finished Mar 02 12:43:01 PM PST 24
Peak memory 208424 kb
Host smart-5ea418b5-78f3-4e20-a834-57d0dfe70d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046891481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2046891481
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2468462371
Short name T623
Test name
Test status
Simulation time 1980206295 ps
CPU time 4.76 seconds
Started Mar 02 12:42:53 PM PST 24
Finished Mar 02 12:42:58 PM PST 24
Peak memory 218264 kb
Host smart-aef906e9-356d-4c62-b011-d5bb2983055e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468462371 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2468462371
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2513960558
Short name T96
Test name
Test status
Simulation time 1150012441 ps
CPU time 9.12 seconds
Started Mar 02 12:42:55 PM PST 24
Finished Mar 02 12:43:05 PM PST 24
Peak memory 208688 kb
Host smart-bc2210ff-1ebe-4881-8655-b5a28607d8ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513960558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2513960558
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.465881442
Short name T977
Test name
Test status
Simulation time 154817800 ps
CPU time 4.79 seconds
Started Mar 02 12:43:13 PM PST 24
Finished Mar 02 12:43:18 PM PST 24
Peak memory 210084 kb
Host smart-2c0150a6-e35a-4c61-b95f-16ca82f8f925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465881442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.465881442
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2970595210
Short name T1028
Test name
Test status
Simulation time 30750266 ps
CPU time 0.87 seconds
Started Mar 02 12:43:04 PM PST 24
Finished Mar 02 12:43:05 PM PST 24
Peak memory 205876 kb
Host smart-2cb7a73c-7c53-49f9-b468-60ff51620065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970595210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2970595210
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.213891768
Short name T220
Test name
Test status
Simulation time 1173042812 ps
CPU time 15.01 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:17 PM PST 24
Peak memory 215232 kb
Host smart-84b5f90c-051a-451a-a0f7-bf22492a7aee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=213891768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.213891768
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3325281562
Short name T772
Test name
Test status
Simulation time 81428681 ps
CPU time 4.41 seconds
Started Mar 02 12:42:58 PM PST 24
Finished Mar 02 12:43:03 PM PST 24
Peak memory 214260 kb
Host smart-5ba54c0a-d8ee-47d2-842d-9753e4deee65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325281562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3325281562
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.52568788
Short name T333
Test name
Test status
Simulation time 145205375 ps
CPU time 3.88 seconds
Started Mar 02 12:42:58 PM PST 24
Finished Mar 02 12:43:02 PM PST 24
Peak memory 218256 kb
Host smart-b3c6f407-944a-4882-93fe-62f371fa611b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52568788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.52568788
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.4030783866
Short name T33
Test name
Test status
Simulation time 479996648 ps
CPU time 5.22 seconds
Started Mar 02 12:43:13 PM PST 24
Finished Mar 02 12:43:19 PM PST 24
Peak memory 210672 kb
Host smart-f0cef689-c143-43c8-a83c-d6e223054cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030783866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.4030783866
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3713740387
Short name T396
Test name
Test status
Simulation time 87295801 ps
CPU time 2.62 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:05 PM PST 24
Peak memory 214116 kb
Host smart-48fc63c3-50db-4f02-be89-42696da95d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713740387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3713740387
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1202130153
Short name T783
Test name
Test status
Simulation time 131348378 ps
CPU time 4.37 seconds
Started Mar 02 12:42:59 PM PST 24
Finished Mar 02 12:43:03 PM PST 24
Peak memory 214260 kb
Host smart-e03d86b3-4024-45a7-b7f7-af723e27e162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202130153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1202130153
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.4088332975
Short name T362
Test name
Test status
Simulation time 40896273 ps
CPU time 2.85 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:05 PM PST 24
Peak memory 208712 kb
Host smart-bca7aeec-f283-4bd2-85d2-7c38e524f1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088332975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.4088332975
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1753938896
Short name T621
Test name
Test status
Simulation time 99463735 ps
CPU time 2.15 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:05 PM PST 24
Peak memory 208568 kb
Host smart-fa95c451-3f8c-4cca-aca9-5071a2c69ebb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753938896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1753938896
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1590259291
Short name T732
Test name
Test status
Simulation time 38714644 ps
CPU time 2.63 seconds
Started Mar 02 12:42:59 PM PST 24
Finished Mar 02 12:43:02 PM PST 24
Peak memory 208744 kb
Host smart-af584170-53d6-430f-9d08-d6ae6eb86e3c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590259291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1590259291
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2636445001
Short name T548
Test name
Test status
Simulation time 148883647 ps
CPU time 4.91 seconds
Started Mar 02 12:42:58 PM PST 24
Finished Mar 02 12:43:03 PM PST 24
Peak memory 208600 kb
Host smart-37b5247b-8a89-4bcc-b876-19c39fc4c12f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636445001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2636445001
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3788135299
Short name T1044
Test name
Test status
Simulation time 3952148022 ps
CPU time 36.99 seconds
Started Mar 02 12:43:00 PM PST 24
Finished Mar 02 12:43:37 PM PST 24
Peak memory 220856 kb
Host smart-cdf545a0-1603-4d97-a0f4-a05e39aa8dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788135299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3788135299
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2506274376
Short name T929
Test name
Test status
Simulation time 127718471 ps
CPU time 2.57 seconds
Started Mar 02 12:43:00 PM PST 24
Finished Mar 02 12:43:03 PM PST 24
Peak memory 206040 kb
Host smart-4be84ba1-4e8c-4d20-a397-c326d6657361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506274376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2506274376
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.371308478
Short name T903
Test name
Test status
Simulation time 1130422070 ps
CPU time 22.81 seconds
Started Mar 02 12:43:00 PM PST 24
Finished Mar 02 12:43:23 PM PST 24
Peak memory 215060 kb
Host smart-e211f3a6-b257-4228-be46-12beabe88566
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371308478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.371308478
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1010243611
Short name T751
Test name
Test status
Simulation time 122054051 ps
CPU time 2.69 seconds
Started Mar 02 12:42:58 PM PST 24
Finished Mar 02 12:43:01 PM PST 24
Peak memory 214528 kb
Host smart-0616a342-41d9-4d8b-9059-1a17e7b31808
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010243611 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1010243611
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1972122445
Short name T884
Test name
Test status
Simulation time 443498948 ps
CPU time 8.04 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:10 PM PST 24
Peak memory 214268 kb
Host smart-d3d6b40a-0d54-46c4-a405-c962c2b95e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972122445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1972122445
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3871876071
Short name T45
Test name
Test status
Simulation time 45061555 ps
CPU time 2.07 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:05 PM PST 24
Peak memory 209540 kb
Host smart-9fe1978a-fcae-4486-a7e4-0751118ad176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871876071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3871876071
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1657043925
Short name T927
Test name
Test status
Simulation time 77989302 ps
CPU time 0.88 seconds
Started Mar 02 12:43:04 PM PST 24
Finished Mar 02 12:43:05 PM PST 24
Peak memory 205788 kb
Host smart-a6bbb9de-acbb-42a2-a4ae-61ac3014f5b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657043925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1657043925
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2924621529
Short name T115
Test name
Test status
Simulation time 195920829 ps
CPU time 4.02 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:06 PM PST 24
Peak memory 215496 kb
Host smart-bb1e89ea-c574-4661-8fc2-28c15de7bac5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2924621529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2924621529
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3246366339
Short name T1053
Test name
Test status
Simulation time 592572168 ps
CPU time 7.94 seconds
Started Mar 02 12:43:04 PM PST 24
Finished Mar 02 12:43:12 PM PST 24
Peak memory 222792 kb
Host smart-090e0a64-8393-42ac-aa0d-d5748ffd3ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246366339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3246366339
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2738955994
Short name T966
Test name
Test status
Simulation time 876875521 ps
CPU time 3.53 seconds
Started Mar 02 12:43:03 PM PST 24
Finished Mar 02 12:43:07 PM PST 24
Peak memory 207360 kb
Host smart-6a4e2ff6-eaac-4450-9363-1cb1d2e813c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738955994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2738955994
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3085478627
Short name T786
Test name
Test status
Simulation time 519127781 ps
CPU time 6.62 seconds
Started Mar 02 12:43:04 PM PST 24
Finished Mar 02 12:43:11 PM PST 24
Peak memory 209560 kb
Host smart-6bbd9cd2-fa64-4293-8e3b-174a89f12de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085478627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3085478627
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.4247971193
Short name T328
Test name
Test status
Simulation time 597567437 ps
CPU time 7.74 seconds
Started Mar 02 12:43:04 PM PST 24
Finished Mar 02 12:43:12 PM PST 24
Peak memory 214528 kb
Host smart-ebb7069a-8d41-49f2-932f-853d53c28da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247971193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.4247971193
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.521146983
Short name T5
Test name
Test status
Simulation time 466008937 ps
CPU time 3.94 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:06 PM PST 24
Peak memory 219180 kb
Host smart-e4796cd6-17bc-4242-ac65-d2eef7d62fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521146983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.521146983
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.548465228
Short name T695
Test name
Test status
Simulation time 52657152 ps
CPU time 2.94 seconds
Started Mar 02 12:42:58 PM PST 24
Finished Mar 02 12:43:01 PM PST 24
Peak memory 208884 kb
Host smart-e1c8e79d-7462-4e98-a284-9a6e9223f23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548465228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.548465228
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.400321807
Short name T866
Test name
Test status
Simulation time 369926227 ps
CPU time 3.49 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:06 PM PST 24
Peak memory 206700 kb
Host smart-68c95a9f-c133-4b7e-8863-2414a3c9ba4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400321807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.400321807
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.1186156449
Short name T770
Test name
Test status
Simulation time 28055769 ps
CPU time 1.94 seconds
Started Mar 02 12:43:09 PM PST 24
Finished Mar 02 12:43:11 PM PST 24
Peak memory 208648 kb
Host smart-6159090e-c069-4be3-b446-1875e122b43a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186156449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.1186156449
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3596557978
Short name T683
Test name
Test status
Simulation time 370599006 ps
CPU time 4.63 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:07 PM PST 24
Peak memory 208768 kb
Host smart-4e9c68d9-f305-4a27-811f-7866fd0d4066
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596557978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3596557978
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.261630357
Short name T708
Test name
Test status
Simulation time 1529575327 ps
CPU time 48.48 seconds
Started Mar 02 12:42:58 PM PST 24
Finished Mar 02 12:43:47 PM PST 24
Peak memory 208436 kb
Host smart-2be6b9a6-ed60-4aea-835b-6e089a2c0bfe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261630357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.261630357
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1460236238
Short name T164
Test name
Test status
Simulation time 430445402 ps
CPU time 4.72 seconds
Started Mar 02 12:43:12 PM PST 24
Finished Mar 02 12:43:18 PM PST 24
Peak memory 210104 kb
Host smart-879a829b-3e97-406d-b320-ff360db6e210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460236238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1460236238
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.902047499
Short name T710
Test name
Test status
Simulation time 207563550 ps
CPU time 5.47 seconds
Started Mar 02 12:43:06 PM PST 24
Finished Mar 02 12:43:12 PM PST 24
Peak memory 208260 kb
Host smart-8eb4631f-57a9-44e7-ba3a-6be585f3efaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902047499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.902047499
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2827571258
Short name T321
Test name
Test status
Simulation time 1920842530 ps
CPU time 47.67 seconds
Started Mar 02 12:43:04 PM PST 24
Finished Mar 02 12:43:52 PM PST 24
Peak memory 220044 kb
Host smart-d770161c-35d0-4d13-80d2-21d4ca55b569
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827571258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2827571258
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3969141525
Short name T992
Test name
Test status
Simulation time 461602444 ps
CPU time 4.01 seconds
Started Mar 02 12:43:04 PM PST 24
Finished Mar 02 12:43:08 PM PST 24
Peak memory 218268 kb
Host smart-51302e92-2e74-4276-a7bc-3ee5c4c7c8f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969141525 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3969141525
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2399063867
Short name T94
Test name
Test status
Simulation time 1020663267 ps
CPU time 11.74 seconds
Started Mar 02 12:42:58 PM PST 24
Finished Mar 02 12:43:10 PM PST 24
Peak memory 214300 kb
Host smart-68a3eb6c-cbf5-40e6-9c80-793322053f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399063867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2399063867
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3542889628
Short name T1042
Test name
Test status
Simulation time 191891814 ps
CPU time 4.45 seconds
Started Mar 02 12:43:07 PM PST 24
Finished Mar 02 12:43:11 PM PST 24
Peak memory 211004 kb
Host smart-db576bb5-af9a-45cd-930f-194ba23925a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542889628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3542889628
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.855424216
Short name T587
Test name
Test status
Simulation time 8377388 ps
CPU time 0.71 seconds
Started Mar 02 12:43:03 PM PST 24
Finished Mar 02 12:43:03 PM PST 24
Peak memory 205876 kb
Host smart-6afd5d0c-cb43-42d4-8da7-1cdf1e77cde4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855424216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.855424216
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1922283254
Short name T58
Test name
Test status
Simulation time 850463525 ps
CPU time 5.55 seconds
Started Mar 02 12:43:06 PM PST 24
Finished Mar 02 12:43:11 PM PST 24
Peak memory 221488 kb
Host smart-7c585b40-33fd-4b0e-bc34-6222f58117db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922283254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1922283254
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.4178662004
Short name T602
Test name
Test status
Simulation time 3817021504 ps
CPU time 17.15 seconds
Started Mar 02 12:43:03 PM PST 24
Finished Mar 02 12:43:21 PM PST 24
Peak memory 214456 kb
Host smart-c3c6dd2f-b4da-44f2-8cb9-02779da3b308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178662004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.4178662004
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1586619809
Short name T824
Test name
Test status
Simulation time 738120002 ps
CPU time 10.08 seconds
Started Mar 02 12:43:08 PM PST 24
Finished Mar 02 12:43:18 PM PST 24
Peak memory 214272 kb
Host smart-955216f6-dfec-48f0-a9b5-5f5ba47de191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586619809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1586619809
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.988347179
Short name T925
Test name
Test status
Simulation time 175971018 ps
CPU time 7.26 seconds
Started Mar 02 12:43:07 PM PST 24
Finished Mar 02 12:43:14 PM PST 24
Peak memory 214132 kb
Host smart-b22b96cd-7302-443f-9a9f-b2866abc9a80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988347179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.988347179
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2587635903
Short name T330
Test name
Test status
Simulation time 657903122 ps
CPU time 3.83 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:06 PM PST 24
Peak memory 222340 kb
Host smart-dd0d1749-b92c-46ac-88c9-cd158daedcef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587635903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2587635903
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2084065095
Short name T857
Test name
Test status
Simulation time 1635990877 ps
CPU time 39.48 seconds
Started Mar 02 12:43:05 PM PST 24
Finished Mar 02 12:43:45 PM PST 24
Peak memory 218256 kb
Host smart-039e85b3-5cff-4e2a-9885-24924e910bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084065095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2084065095
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2554287259
Short name T551
Test name
Test status
Simulation time 129896158 ps
CPU time 3.42 seconds
Started Mar 02 12:43:04 PM PST 24
Finished Mar 02 12:43:08 PM PST 24
Peak memory 206692 kb
Host smart-642020c1-2fed-4caf-9635-d68ee8dd9f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554287259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2554287259
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1912773204
Short name T293
Test name
Test status
Simulation time 428115198 ps
CPU time 6.27 seconds
Started Mar 02 12:43:06 PM PST 24
Finished Mar 02 12:43:13 PM PST 24
Peak memory 208524 kb
Host smart-b88c0f9e-6dee-4f26-8ad9-0bf540a6787e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912773204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1912773204
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3754637193
Short name T974
Test name
Test status
Simulation time 8188271997 ps
CPU time 34.31 seconds
Started Mar 02 12:43:08 PM PST 24
Finished Mar 02 12:43:42 PM PST 24
Peak memory 208272 kb
Host smart-f80d8156-42fb-4321-af52-d6f39754a010
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754637193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3754637193
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2127031821
Short name T578
Test name
Test status
Simulation time 305858643 ps
CPU time 1.92 seconds
Started Mar 02 12:43:03 PM PST 24
Finished Mar 02 12:43:05 PM PST 24
Peak memory 207432 kb
Host smart-19128b1e-6cfe-4900-a75d-b11013cf464b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127031821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2127031821
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1302630504
Short name T855
Test name
Test status
Simulation time 470261945 ps
CPU time 14.11 seconds
Started Mar 02 12:43:09 PM PST 24
Finished Mar 02 12:43:23 PM PST 24
Peak memory 208628 kb
Host smart-402f4795-3d6c-47b8-acbf-56e08035bff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302630504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1302630504
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2464200734
Short name T540
Test name
Test status
Simulation time 76524634 ps
CPU time 2.95 seconds
Started Mar 02 12:43:04 PM PST 24
Finished Mar 02 12:43:08 PM PST 24
Peak memory 207040 kb
Host smart-8f146e42-c573-4b0a-8af4-d964c7bd98fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464200734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2464200734
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2950631865
Short name T1000
Test name
Test status
Simulation time 2290412087 ps
CPU time 20.44 seconds
Started Mar 02 12:43:03 PM PST 24
Finished Mar 02 12:43:24 PM PST 24
Peak memory 220708 kb
Host smart-15913889-5df9-474f-ac6b-8ad69311800a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950631865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2950631865
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.80906589
Short name T658
Test name
Test status
Simulation time 1443854743 ps
CPU time 8.63 seconds
Started Mar 02 12:43:02 PM PST 24
Finished Mar 02 12:43:11 PM PST 24
Peak memory 220572 kb
Host smart-978b0648-65ac-46d3-9c50-51138d46ca8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80906589 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.80906589
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2326054024
Short name T803
Test name
Test status
Simulation time 6482239978 ps
CPU time 36.78 seconds
Started Mar 02 12:43:04 PM PST 24
Finished Mar 02 12:43:41 PM PST 24
Peak memory 208852 kb
Host smart-d216c277-6515-420b-bee3-2de7dfb16cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326054024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2326054024
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2108061546
Short name T931
Test name
Test status
Simulation time 78352387 ps
CPU time 1.72 seconds
Started Mar 02 12:43:12 PM PST 24
Finished Mar 02 12:43:15 PM PST 24
Peak memory 209640 kb
Host smart-da061243-009d-48fd-aa34-c2d8a708c2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108061546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2108061546
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3026227538
Short name T656
Test name
Test status
Simulation time 14115553 ps
CPU time 0.75 seconds
Started Mar 02 12:40:08 PM PST 24
Finished Mar 02 12:40:09 PM PST 24
Peak memory 205872 kb
Host smart-3b5a482a-1ae4-489e-8f50-f5870cdb4e1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026227538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3026227538
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3852803793
Short name T407
Test name
Test status
Simulation time 41842396 ps
CPU time 2.92 seconds
Started Mar 02 12:40:06 PM PST 24
Finished Mar 02 12:40:09 PM PST 24
Peak memory 214408 kb
Host smart-e0526a22-3d18-4457-999c-696ee12d2647
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3852803793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3852803793
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3076350136
Short name T203
Test name
Test status
Simulation time 78746687 ps
CPU time 3.14 seconds
Started Mar 02 12:40:06 PM PST 24
Finished Mar 02 12:40:10 PM PST 24
Peak memory 209496 kb
Host smart-ab83aa3c-32ae-4903-84eb-8eb0aebd2880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076350136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3076350136
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.4272930103
Short name T712
Test name
Test status
Simulation time 39354864 ps
CPU time 1.91 seconds
Started Mar 02 12:40:05 PM PST 24
Finished Mar 02 12:40:07 PM PST 24
Peak memory 208480 kb
Host smart-feb5d133-d5f0-4d0d-9d70-b997d505e15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272930103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.4272930103
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2913497328
Short name T83
Test name
Test status
Simulation time 524768249 ps
CPU time 10.78 seconds
Started Mar 02 12:40:08 PM PST 24
Finished Mar 02 12:40:19 PM PST 24
Peak memory 214284 kb
Host smart-870a99f0-9573-42dd-af6a-04d1cc1b4868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913497328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2913497328
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.983582502
Short name T864
Test name
Test status
Simulation time 12174716341 ps
CPU time 41.59 seconds
Started Mar 02 12:40:06 PM PST 24
Finished Mar 02 12:40:48 PM PST 24
Peak memory 214244 kb
Host smart-633df0fe-6066-46c4-83be-3af89cc6f6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983582502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.983582502
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2226151086
Short name T788
Test name
Test status
Simulation time 1857612637 ps
CPU time 5.31 seconds
Started Mar 02 12:40:06 PM PST 24
Finished Mar 02 12:40:11 PM PST 24
Peak memory 222496 kb
Host smart-470ff539-5615-4fcb-a6d7-987750a33ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226151086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2226151086
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3173615398
Short name T255
Test name
Test status
Simulation time 1100783953 ps
CPU time 21.07 seconds
Started Mar 02 12:40:06 PM PST 24
Finished Mar 02 12:40:27 PM PST 24
Peak memory 208948 kb
Host smart-bb41ed08-9e38-4a76-8d87-e6fdfe16f827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173615398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3173615398
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.913831869
Short name T768
Test name
Test status
Simulation time 126917909 ps
CPU time 2.52 seconds
Started Mar 02 12:40:06 PM PST 24
Finished Mar 02 12:40:09 PM PST 24
Peak memory 208584 kb
Host smart-dbbb0f09-854e-4984-bb92-7836cd39c889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=913831869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.913831869
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1288074249
Short name T792
Test name
Test status
Simulation time 74292754 ps
CPU time 3.55 seconds
Started Mar 02 12:40:09 PM PST 24
Finished Mar 02 12:40:12 PM PST 24
Peak memory 208752 kb
Host smart-fa7163d8-d1d4-4899-b9cb-f88ea39f4f9f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288074249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1288074249
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2131331917
Short name T957
Test name
Test status
Simulation time 54355170 ps
CPU time 3.23 seconds
Started Mar 02 12:40:06 PM PST 24
Finished Mar 02 12:40:09 PM PST 24
Peak memory 208880 kb
Host smart-967ad9ae-10de-413e-ba2f-614834446f8b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131331917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2131331917
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1898337158
Short name T274
Test name
Test status
Simulation time 40296623 ps
CPU time 2.29 seconds
Started Mar 02 12:40:09 PM PST 24
Finished Mar 02 12:40:12 PM PST 24
Peak memory 210080 kb
Host smart-f1bf17e6-df85-42ac-b020-0fbc47e0f52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898337158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1898337158
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2901381530
Short name T874
Test name
Test status
Simulation time 180622047 ps
CPU time 4.82 seconds
Started Mar 02 12:40:08 PM PST 24
Finished Mar 02 12:40:13 PM PST 24
Peak memory 208020 kb
Host smart-ce553dc1-40cd-48ae-a7d9-e23ab32062de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901381530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2901381530
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.452118352
Short name T896
Test name
Test status
Simulation time 2432117536 ps
CPU time 47.87 seconds
Started Mar 02 12:40:09 PM PST 24
Finished Mar 02 12:40:57 PM PST 24
Peak memory 221628 kb
Host smart-032dae33-03b5-4f35-9e7d-8e89e0a75f5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452118352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.452118352
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3491930673
Short name T584
Test name
Test status
Simulation time 113306376 ps
CPU time 7.53 seconds
Started Mar 02 12:40:06 PM PST 24
Finished Mar 02 12:40:14 PM PST 24
Peak memory 222520 kb
Host smart-d64f7410-2e79-4893-8a42-480c21166831
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491930673 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3491930673
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1346323461
Short name T907
Test name
Test status
Simulation time 221696927 ps
CPU time 4.62 seconds
Started Mar 02 12:40:11 PM PST 24
Finished Mar 02 12:40:16 PM PST 24
Peak memory 213344 kb
Host smart-1a51ec0c-e6d5-48ab-a859-2b8295393c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346323461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1346323461
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1993196741
Short name T669
Test name
Test status
Simulation time 36627756 ps
CPU time 0.89 seconds
Started Mar 02 12:40:12 PM PST 24
Finished Mar 02 12:40:14 PM PST 24
Peak memory 205824 kb
Host smart-e3a84f19-be54-4bea-8374-9d2b5ac90591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993196741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1993196741
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3074289448
Short name T405
Test name
Test status
Simulation time 816513081 ps
CPU time 4.22 seconds
Started Mar 02 12:40:11 PM PST 24
Finished Mar 02 12:40:15 PM PST 24
Peak memory 213036 kb
Host smart-fc5e6943-9f61-4c4a-b72f-d41ed20695dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3074289448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3074289448
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2963223287
Short name T701
Test name
Test status
Simulation time 34999633 ps
CPU time 1.78 seconds
Started Mar 02 12:40:07 PM PST 24
Finished Mar 02 12:40:09 PM PST 24
Peak memory 208672 kb
Host smart-91474a20-9e09-4106-9907-5c6360bc0492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963223287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2963223287
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.427111608
Short name T955
Test name
Test status
Simulation time 388603291 ps
CPU time 10.15 seconds
Started Mar 02 12:40:07 PM PST 24
Finished Mar 02 12:40:17 PM PST 24
Peak memory 222452 kb
Host smart-f71653e2-2b61-43a1-845a-b01dff48ae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427111608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.427111608
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2557470064
Short name T590
Test name
Test status
Simulation time 67830805 ps
CPU time 2.67 seconds
Started Mar 02 12:40:09 PM PST 24
Finished Mar 02 12:40:12 PM PST 24
Peak memory 206052 kb
Host smart-bda42bd5-8d15-4647-a4f5-961a015ba30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557470064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2557470064
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.935750339
Short name T749
Test name
Test status
Simulation time 124961134 ps
CPU time 5.53 seconds
Started Mar 02 12:40:05 PM PST 24
Finished Mar 02 12:40:11 PM PST 24
Peak memory 209228 kb
Host smart-1a8cea0e-18bd-4d65-8a10-6c598ce55c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935750339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.935750339
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.4072738523
Short name T175
Test name
Test status
Simulation time 141372718 ps
CPU time 4.6 seconds
Started Mar 02 12:40:06 PM PST 24
Finished Mar 02 12:40:11 PM PST 24
Peak memory 207948 kb
Host smart-81d8ac6d-ec90-46a1-b1bd-343ab39ac50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072738523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.4072738523
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3685824890
Short name T773
Test name
Test status
Simulation time 2536853579 ps
CPU time 8.43 seconds
Started Mar 02 12:40:06 PM PST 24
Finished Mar 02 12:40:14 PM PST 24
Peak memory 206932 kb
Host smart-d3b1c822-7fa7-438b-92e4-0c6a187e0be2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685824890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3685824890
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3941645057
Short name T637
Test name
Test status
Simulation time 215312754 ps
CPU time 2.93 seconds
Started Mar 02 12:40:07 PM PST 24
Finished Mar 02 12:40:10 PM PST 24
Peak memory 208820 kb
Host smart-01dad682-44d3-47d8-8418-30d4ed9382fc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941645057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3941645057
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3158071307
Short name T184
Test name
Test status
Simulation time 1679433461 ps
CPU time 35.3 seconds
Started Mar 02 12:40:06 PM PST 24
Finished Mar 02 12:40:41 PM PST 24
Peak memory 207924 kb
Host smart-b77989ce-ba33-4c15-8c2d-5036cd2ea44d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158071307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3158071307
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2034957192
Short name T186
Test name
Test status
Simulation time 193020246 ps
CPU time 4.59 seconds
Started Mar 02 12:40:12 PM PST 24
Finished Mar 02 12:40:17 PM PST 24
Peak memory 209280 kb
Host smart-d127fd3e-a82b-47a0-91d4-1306ab9aea6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034957192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2034957192
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.64382773
Short name T834
Test name
Test status
Simulation time 1075566284 ps
CPU time 7.21 seconds
Started Mar 02 12:40:08 PM PST 24
Finished Mar 02 12:40:15 PM PST 24
Peak memory 207840 kb
Host smart-618761b0-d909-4cd9-aa05-2fb3b58f7023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64382773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.64382773
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3329317201
Short name T88
Test name
Test status
Simulation time 247864589 ps
CPU time 4.24 seconds
Started Mar 02 12:40:13 PM PST 24
Finished Mar 02 12:40:17 PM PST 24
Peak memory 222700 kb
Host smart-07d2a3cd-884d-4763-978c-e5a0aa072657
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329317201 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3329317201
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.579629972
Short name T941
Test name
Test status
Simulation time 122500734 ps
CPU time 5.24 seconds
Started Mar 02 12:40:08 PM PST 24
Finished Mar 02 12:40:13 PM PST 24
Peak memory 218296 kb
Host smart-b588513b-32a9-449b-9b47-826e5dffa1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579629972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.579629972
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4151325643
Short name T144
Test name
Test status
Simulation time 180529072 ps
CPU time 3.85 seconds
Started Mar 02 12:40:08 PM PST 24
Finished Mar 02 12:40:12 PM PST 24
Peak memory 210600 kb
Host smart-6b57732f-370d-42eb-a5b3-eeb93438a056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151325643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4151325643
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2493268711
Short name T940
Test name
Test status
Simulation time 28330196 ps
CPU time 0.76 seconds
Started Mar 02 12:40:14 PM PST 24
Finished Mar 02 12:40:15 PM PST 24
Peak memory 205804 kb
Host smart-4812d4d2-d9ce-4f3e-86e9-37039c77dd04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493268711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2493268711
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3543064601
Short name T308
Test name
Test status
Simulation time 177724579 ps
CPU time 9.58 seconds
Started Mar 02 12:40:13 PM PST 24
Finished Mar 02 12:40:23 PM PST 24
Peak memory 214724 kb
Host smart-6a82a266-0589-44fd-a0b8-92938794037f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3543064601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3543064601
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2064439137
Short name T1003
Test name
Test status
Simulation time 286969813 ps
CPU time 2.48 seconds
Started Mar 02 12:40:12 PM PST 24
Finished Mar 02 12:40:15 PM PST 24
Peak memory 208184 kb
Host smart-ddb1faf8-049e-4176-9509-345ccdbf034b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064439137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2064439137
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.423880787
Short name T334
Test name
Test status
Simulation time 21369522745 ps
CPU time 34.6 seconds
Started Mar 02 12:40:11 PM PST 24
Finished Mar 02 12:40:46 PM PST 24
Peak memory 214212 kb
Host smart-c9fc902e-09b0-4b7a-a533-8cea35736295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423880787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.423880787
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.815174691
Short name T843
Test name
Test status
Simulation time 61225693 ps
CPU time 1.95 seconds
Started Mar 02 12:40:09 PM PST 24
Finished Mar 02 12:40:11 PM PST 24
Peak memory 219680 kb
Host smart-bba1beae-199f-425b-91d2-f9f9d6585142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815174691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.815174691
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2727775371
Short name T700
Test name
Test status
Simulation time 159445697 ps
CPU time 3.98 seconds
Started Mar 02 12:40:12 PM PST 24
Finished Mar 02 12:40:16 PM PST 24
Peak memory 209852 kb
Host smart-e6b40529-4dbc-489c-ac4f-cbabdd0433bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727775371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2727775371
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1514322324
Short name T651
Test name
Test status
Simulation time 2850779285 ps
CPU time 54.49 seconds
Started Mar 02 12:40:12 PM PST 24
Finished Mar 02 12:41:07 PM PST 24
Peak memory 208936 kb
Host smart-c0da86f4-aa23-45ca-9a79-be1ede49e983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514322324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1514322324
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.4116598460
Short name T699
Test name
Test status
Simulation time 45940708 ps
CPU time 1.89 seconds
Started Mar 02 12:40:09 PM PST 24
Finished Mar 02 12:40:11 PM PST 24
Peak memory 206956 kb
Host smart-8a36f79d-f1fb-4a1c-9f05-1454262b6e71
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116598460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.4116598460
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1733960851
Short name T626
Test name
Test status
Simulation time 1038320784 ps
CPU time 4.72 seconds
Started Mar 02 12:40:12 PM PST 24
Finished Mar 02 12:40:18 PM PST 24
Peak memory 206832 kb
Host smart-08b88a20-f02a-4148-b938-6e4b29620bab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733960851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1733960851
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3872996986
Short name T1017
Test name
Test status
Simulation time 413660688 ps
CPU time 4.93 seconds
Started Mar 02 12:40:09 PM PST 24
Finished Mar 02 12:40:14 PM PST 24
Peak memory 208812 kb
Host smart-077d3bed-e616-4f95-a99b-62bf936a3a80
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872996986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3872996986
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1980981373
Short name T636
Test name
Test status
Simulation time 64594249 ps
CPU time 2.38 seconds
Started Mar 02 12:40:18 PM PST 24
Finished Mar 02 12:40:21 PM PST 24
Peak memory 208012 kb
Host smart-a3678f9d-79f5-43c2-9e25-2e1f607edce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980981373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1980981373
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1871463165
Short name T617
Test name
Test status
Simulation time 797388048 ps
CPU time 5.35 seconds
Started Mar 02 12:40:13 PM PST 24
Finished Mar 02 12:40:19 PM PST 24
Peak memory 206696 kb
Host smart-da85ccbf-933f-49e6-99fd-e100ffccf93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871463165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1871463165
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1120652017
Short name T936
Test name
Test status
Simulation time 451583577 ps
CPU time 8.77 seconds
Started Mar 02 12:40:15 PM PST 24
Finished Mar 02 12:40:24 PM PST 24
Peak memory 222460 kb
Host smart-57efb3da-db99-487a-b975-36ede76248e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120652017 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1120652017
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.736842135
Short name T238
Test name
Test status
Simulation time 3932350948 ps
CPU time 28.89 seconds
Started Mar 02 12:40:10 PM PST 24
Finished Mar 02 12:40:39 PM PST 24
Peak memory 209768 kb
Host smart-b5f9491f-a33d-4031-8375-ccb82211e339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736842135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.736842135
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3752080131
Short name T902
Test name
Test status
Simulation time 242069356 ps
CPU time 3.04 seconds
Started Mar 02 12:40:20 PM PST 24
Finished Mar 02 12:40:23 PM PST 24
Peak memory 210240 kb
Host smart-649e3fed-054f-41ac-b5cc-f52b74ff5d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752080131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3752080131
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1333074768
Short name T670
Test name
Test status
Simulation time 21584622 ps
CPU time 0.82 seconds
Started Mar 02 12:40:17 PM PST 24
Finished Mar 02 12:40:18 PM PST 24
Peak memory 205860 kb
Host smart-8fc96d17-7346-4344-8c68-101f46acf63e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333074768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1333074768
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.321208646
Short name T300
Test name
Test status
Simulation time 694020197 ps
CPU time 15.88 seconds
Started Mar 02 12:40:16 PM PST 24
Finished Mar 02 12:40:32 PM PST 24
Peak memory 215652 kb
Host smart-c1453343-8c6a-45b1-891b-d5b2f9c1be36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=321208646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.321208646
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1440647308
Short name T839
Test name
Test status
Simulation time 171127204 ps
CPU time 2.88 seconds
Started Mar 02 12:40:17 PM PST 24
Finished Mar 02 12:40:20 PM PST 24
Peak memory 221912 kb
Host smart-6083002b-5e7c-42d4-9a5f-68d0ed91e36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440647308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1440647308
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2856866679
Short name T315
Test name
Test status
Simulation time 883315356 ps
CPU time 5.83 seconds
Started Mar 02 12:40:18 PM PST 24
Finished Mar 02 12:40:24 PM PST 24
Peak memory 208940 kb
Host smart-cb1c33f4-f4e9-4cfa-8297-88cfa59213bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856866679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2856866679
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1470196066
Short name T309
Test name
Test status
Simulation time 1254086084 ps
CPU time 8.4 seconds
Started Mar 02 12:40:25 PM PST 24
Finished Mar 02 12:40:33 PM PST 24
Peak memory 219780 kb
Host smart-fd3141f7-b208-4a68-af0d-5219db64f60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470196066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1470196066
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.44529555
Short name T264
Test name
Test status
Simulation time 309787927 ps
CPU time 7.05 seconds
Started Mar 02 12:40:18 PM PST 24
Finished Mar 02 12:40:25 PM PST 24
Peak memory 214240 kb
Host smart-166d4fad-6a43-4f68-afc8-7b49cf1c0573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44529555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.44529555
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1458210641
Short name T632
Test name
Test status
Simulation time 84266980 ps
CPU time 2.64 seconds
Started Mar 02 12:40:20 PM PST 24
Finished Mar 02 12:40:23 PM PST 24
Peak memory 220784 kb
Host smart-629c4cf7-84f9-4658-826e-1abcfb8faadd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458210641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1458210641
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1249198177
Short name T1005
Test name
Test status
Simulation time 838938049 ps
CPU time 9.55 seconds
Started Mar 02 12:40:25 PM PST 24
Finished Mar 02 12:40:35 PM PST 24
Peak memory 208644 kb
Host smart-02afaf2e-491f-44ca-9629-b7a64994c7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249198177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1249198177
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1468893964
Short name T233
Test name
Test status
Simulation time 211193779 ps
CPU time 2.75 seconds
Started Mar 02 12:40:15 PM PST 24
Finished Mar 02 12:40:18 PM PST 24
Peak memory 208704 kb
Host smart-e0f36d86-9d5f-4bbd-9c66-1ebbe2de1f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468893964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1468893964
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1925775988
Short name T702
Test name
Test status
Simulation time 930251476 ps
CPU time 13.4 seconds
Started Mar 02 12:40:16 PM PST 24
Finished Mar 02 12:40:31 PM PST 24
Peak memory 208852 kb
Host smart-f08863ad-f903-412e-8668-b27f0cd080c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925775988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1925775988
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.465462982
Short name T771
Test name
Test status
Simulation time 625665591 ps
CPU time 3.31 seconds
Started Mar 02 12:40:14 PM PST 24
Finished Mar 02 12:40:18 PM PST 24
Peak memory 208236 kb
Host smart-95d910c2-c766-46eb-9a38-8103bf4b1455
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465462982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.465462982
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2798084326
Short name T182
Test name
Test status
Simulation time 524943412 ps
CPU time 6.18 seconds
Started Mar 02 12:40:16 PM PST 24
Finished Mar 02 12:40:24 PM PST 24
Peak memory 208516 kb
Host smart-47cc26d1-a633-460c-8748-e59c06de0726
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798084326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2798084326
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3897775341
Short name T91
Test name
Test status
Simulation time 778143385 ps
CPU time 9.21 seconds
Started Mar 02 12:40:19 PM PST 24
Finished Mar 02 12:40:29 PM PST 24
Peak memory 218440 kb
Host smart-e6bf859b-a979-4ab6-93f1-a139c545d58e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897775341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3897775341
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1336990882
Short name T410
Test name
Test status
Simulation time 281050234 ps
CPU time 3.28 seconds
Started Mar 02 12:40:15 PM PST 24
Finished Mar 02 12:40:18 PM PST 24
Peak memory 208716 kb
Host smart-da55796f-7fde-4ea0-83f7-07fa3263bdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336990882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1336990882
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.372673642
Short name T67
Test name
Test status
Simulation time 2128657823 ps
CPU time 28.38 seconds
Started Mar 02 12:40:25 PM PST 24
Finished Mar 02 12:40:54 PM PST 24
Peak memory 215952 kb
Host smart-f2a68678-f018-428e-934c-32f04a0e0121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372673642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.372673642
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2333783565
Short name T798
Test name
Test status
Simulation time 1144851521 ps
CPU time 9.08 seconds
Started Mar 02 12:40:20 PM PST 24
Finished Mar 02 12:40:29 PM PST 24
Peak memory 222632 kb
Host smart-1689d839-7c4f-458c-9ba6-fded1b183daf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333783565 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2333783565
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2217961374
Short name T883
Test name
Test status
Simulation time 387901726 ps
CPU time 3.66 seconds
Started Mar 02 12:40:15 PM PST 24
Finished Mar 02 12:40:19 PM PST 24
Peak memory 209108 kb
Host smart-7fb7ab8b-9833-48a0-950b-ed82d1f055e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217961374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2217961374
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.907220186
Short name T553
Test name
Test status
Simulation time 200801696 ps
CPU time 2.42 seconds
Started Mar 02 12:40:16 PM PST 24
Finished Mar 02 12:40:18 PM PST 24
Peak memory 210196 kb
Host smart-6821c7a4-20b0-4b03-903d-23cafae91506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907220186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.907220186
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.875161167
Short name T738
Test name
Test status
Simulation time 13676887 ps
CPU time 0.73 seconds
Started Mar 02 12:40:28 PM PST 24
Finished Mar 02 12:40:29 PM PST 24
Peak memory 205888 kb
Host smart-a7d225ec-f08d-4974-92e8-eeddcb3b12fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875161167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.875161167
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3779069223
Short name T132
Test name
Test status
Simulation time 2757256017 ps
CPU time 41.37 seconds
Started Mar 02 12:40:19 PM PST 24
Finished Mar 02 12:41:01 PM PST 24
Peak memory 214300 kb
Host smart-d0c5dfb4-5d97-4991-8a8f-61a045c344e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3779069223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3779069223
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1638805551
Short name T897
Test name
Test status
Simulation time 45664560 ps
CPU time 2.84 seconds
Started Mar 02 12:40:29 PM PST 24
Finished Mar 02 12:40:32 PM PST 24
Peak memory 208104 kb
Host smart-db64518a-1c67-4020-aa26-837ba7d302f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638805551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1638805551
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.983386239
Short name T801
Test name
Test status
Simulation time 781727959 ps
CPU time 8.12 seconds
Started Mar 02 12:40:16 PM PST 24
Finished Mar 02 12:40:24 PM PST 24
Peak memory 218148 kb
Host smart-baf4b7b7-fa7f-4575-8557-2751690c1c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983386239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.983386239
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.80264398
Short name T375
Test name
Test status
Simulation time 259091501 ps
CPU time 9 seconds
Started Mar 02 12:40:15 PM PST 24
Finished Mar 02 12:40:24 PM PST 24
Peak memory 214312 kb
Host smart-3f9e42b7-ad78-4afe-a2b7-5d71c2ceed45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80264398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.80264398
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.819518547
Short name T988
Test name
Test status
Simulation time 44116795 ps
CPU time 2.75 seconds
Started Mar 02 12:40:15 PM PST 24
Finished Mar 02 12:40:18 PM PST 24
Peak memory 220268 kb
Host smart-cc3dc592-8832-43dc-a916-942c6862c4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819518547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.819518547
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.4000407105
Short name T900
Test name
Test status
Simulation time 148465738 ps
CPU time 5.1 seconds
Started Mar 02 12:40:19 PM PST 24
Finished Mar 02 12:40:24 PM PST 24
Peak memory 208028 kb
Host smart-75cd9d7f-4cb6-4824-81bc-bb53a92779b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000407105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.4000407105
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.345896177
Short name T386
Test name
Test status
Simulation time 32910225 ps
CPU time 2.2 seconds
Started Mar 02 12:40:20 PM PST 24
Finished Mar 02 12:40:22 PM PST 24
Peak memory 206916 kb
Host smart-c300e6ce-ceda-454b-aa37-f442460ad9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345896177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.345896177
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2886103100
Short name T168
Test name
Test status
Simulation time 285727432 ps
CPU time 9.94 seconds
Started Mar 02 12:40:16 PM PST 24
Finished Mar 02 12:40:26 PM PST 24
Peak memory 208188 kb
Host smart-93268f68-6e5f-4ea7-b358-1f12c358cf44
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886103100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2886103100
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.4012489472
Short name T384
Test name
Test status
Simulation time 60983079 ps
CPU time 2.31 seconds
Started Mar 02 12:40:25 PM PST 24
Finished Mar 02 12:40:27 PM PST 24
Peak memory 206640 kb
Host smart-84535f9a-eb00-4a9e-94ce-11579d1991fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012489472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.4012489472
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3309325668
Short name T183
Test name
Test status
Simulation time 270492849 ps
CPU time 2.82 seconds
Started Mar 02 12:40:16 PM PST 24
Finished Mar 02 12:40:19 PM PST 24
Peak memory 208728 kb
Host smart-f7e89c5f-c84b-49b0-b83c-c0e7a3ad5962
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309325668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3309325668
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3919933678
Short name T684
Test name
Test status
Simulation time 145824786 ps
CPU time 4.92 seconds
Started Mar 02 12:40:25 PM PST 24
Finished Mar 02 12:40:31 PM PST 24
Peak memory 218496 kb
Host smart-5d4d0bc0-804e-4650-a82f-974830d24cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919933678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3919933678
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1468720985
Short name T681
Test name
Test status
Simulation time 109535644 ps
CPU time 2.06 seconds
Started Mar 02 12:40:15 PM PST 24
Finished Mar 02 12:40:18 PM PST 24
Peak memory 208624 kb
Host smart-17cc0300-397b-403d-9245-cf8856ccc500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468720985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1468720985
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.4119013417
Short name T61
Test name
Test status
Simulation time 856783396 ps
CPU time 22.32 seconds
Started Mar 02 12:40:26 PM PST 24
Finished Mar 02 12:40:49 PM PST 24
Peak memory 222468 kb
Host smart-c2d2c1ff-5da3-40c1-841e-09c5be9cc027
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119013417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.4119013417
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1732604883
Short name T726
Test name
Test status
Simulation time 329161283 ps
CPU time 4.33 seconds
Started Mar 02 12:40:27 PM PST 24
Finished Mar 02 12:40:32 PM PST 24
Peak memory 218864 kb
Host smart-0ea69342-cfc1-4b1e-9a1d-97efc2b1211c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732604883 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1732604883
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.4050672680
Short name T1055
Test name
Test status
Simulation time 111769090 ps
CPU time 3.92 seconds
Started Mar 02 12:40:15 PM PST 24
Finished Mar 02 12:40:20 PM PST 24
Peak memory 218132 kb
Host smart-18fde7e9-9d9d-424b-b29e-fdb907ef5603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050672680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.4050672680
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3832669099
Short name T778
Test name
Test status
Simulation time 1345652894 ps
CPU time 27.05 seconds
Started Mar 02 12:40:24 PM PST 24
Finished Mar 02 12:40:52 PM PST 24
Peak memory 210960 kb
Host smart-43866527-d345-49f9-aa3f-08c532711fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3832669099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3832669099
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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