Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10757

1

T1

3

T3

28

T4

20

auto[Attestation]

7281

1

T1

5

T3

8

T4

7

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2619	1			T3	8		T4	4		T13	2
auto[Aes]	3222	1			T3	7		T4	2		T13	4
auto[Kmac]	3321	1			T1	8		T3	6		T4	6
auto[Otbn]	3253	1			T3	3		T4	6		T13	5

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7180	1			T1	8		T2	1		T3	8
auto[OpGenId]	5623	1			T3	12		T4	9		T13	9
auto[OpGenSwOut]	5646	1			T3	8		T4	7		T13	7
auto[OpGenHwOut]	6769	1			T1	8		T3	16		T4	11
auto[OpDisable]	118	1			T41	1		T42	1		T43	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9264

1

T1

8

T2

1

T3

16

auto[OpDoneFail]

16072

1

T1

8

T3

28

T4

34

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6045	1			T1	1		T2	1		T3	12
auto[StInit]	4202	1			T1	2		T3	5		T4	3
auto[StCreatorRootKey]	2736	1			T1	2		T3	3		T13	6
auto[StOwnerIntKey]	2410	1			T1	2		T3	5		T13	2
auto[StOwnerKey]	2065	1			T1	2		T3	6		T13	5
auto[StDisabled]	6904	1			T1	7		T3	13		T13	16
auto[StInvalid]	974	1			T4	15		T18	15		T29	24

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	305	1			T3	1		T81	1		T85	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	125	1			T16	1		T41	2		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	75	1			T14	1		T41	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	48	1			T41	2		T38	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	49	1			T16	1		T77	1		T62	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	195	1			T3	1		T81	2		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	29	1			T188	1		T189	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	307	1			T16	1		T18	1		T99	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	125	1			T41	1		T182	1		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	65	1			T122	1		T62	1		T190	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	52	1			T15	1		T81	1		T124	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	49	1			T104	1		T191	1		T50	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	186	1			T13	1		T41	2		T99	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	38	1			T18	1		T33	1		T188	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	341	1			T3	2		T4	3		T16	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	118	1			T16	1		T82	1		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	74	1			T13	1		T14	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	69	1			T34	1		T85	1		T100	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	64	1			T13	1		T16	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	191	1			T41	2		T99	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	26	1			T33	1		T188	1		T184	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	317	1			T4	2		T16	1		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	120	1			T15	1		T16	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	64	1			T9	1		T41	1		T182	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	60	1			T3	1		T124	1		T38	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	45	1			T62	1		T39	2		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	197	1			T3	1		T13	1		T85	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	27	1			T29	1		T33	2		T188	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	54	1			T6	3		T193	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	110	1			T14	1		T16	1		T95	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	76	1			T82	1		T9	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	55	1			T62	2		T194	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	60	1			T195	1		T182	1		T183	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	193	1			T3	1		T82	2		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	26	1			T4	1		T33	1		T188	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	57	1			T95	1		T50	4		T62	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	129	1			T16	1		T20	1		T195	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	60	1			T8	1		T98	1		T123	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	65	1			T123	1		T38	1		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	45	1			T35	1		T98	1		T100	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	164	1			T82	1		T85	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	25	1			T18	1		T29	1		T33	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	64	1			T18	1		T95	1		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	119	1			T20	1		T41	2		T98	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T3	1		T35	1		T183	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	68	1			T41	1		T62	3		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	45	1			T13	1		T43	1		T38	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	181	1			T85	1		T41	3		T182	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	24	1			T4	1		T29	1		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	67	1			T18	3		T96	1		T50	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	110	1			T16	1		T20	1		T195	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T8	1		T98	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	69	1			T35	1		T41	2		T183	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	43	1			T103	1		T50	1		T194	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	182	1			T13	2		T82	1		T99	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	25	1			T18	1		T196	1		T188	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	271	1			T3	1		T4	2		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	94	1			T3	1		T14	1		T20	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	67	1			T38	1		T62	3		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	47	1			T95	1		T197	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	37	1			T3	1		T62	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	166	1			T3	1		T13	1		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	38	1			T4	1		T29	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	445	1			T3	2		T20	2		T36	9
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	129	1			T36	1		T49	1		T86	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	101	1			T3	1		T13	1		T14	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	82	1			T3	1		T43	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	92	1			T3	2		T13	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	257	1			T3	1		T84	4		T85	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	35	1			T33	1		T188	1		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	432	1			T83	3		T85	3		T191	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	119	1			T1	1		T4	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	95	1			T41	3		T50	2		T38	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T3	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	65	1			T1	1		T35	1		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	244	1			T1	1		T3	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	25	1			T4	1		T18	1		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	467	1			T4	3		T18	2		T85	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	150	1			T14	2		T16	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T14	1		T198	1		T95	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	95	1			T15	3		T198	1		T41	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	68	1			T82	1		T195	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	265	1			T13	1		T82	2		T198	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	24	1			T29	1		T196	1		T184	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	39	1			T96	1		T38	1		T62	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	106	1			T16	1		T41	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	48	1			T14	1		T100	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T3	1		T38	1		T190	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	48	1			T62	2		T39	1		T6	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	170	1			T13	1		T41	3		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	27	1			T188	1		T175	1		T189	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	52	1			T18	1		T38	1		T62	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	136	1			T4	1		T20	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	101	1			T41	1		T100	1		T38	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	73	1			T36	1		T84	1		T124	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	75	1			T35	1		T95	1		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	240	1			T13	1		T36	4		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	37	1			T4	1		T29	1		T188	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	67	1			T18	1		T50	1		T38	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	131	1			T3	1		T15	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	115	1			T1	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T1	1		T15	1		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	82	1			T83	1		T123	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	267	1			T1	3		T83	1		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	35	1			T18	1		T188	2		T91	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	64	1			T38	6		T62	6		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	113	1			T3	1		T18	2		T20	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	81	1			T35	1		T120	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	84	1			T41	1		T120	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	75	1			T195	1		T198	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	245	1			T13	1		T34	1		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	25	1			T4	1		T29	3		T196	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	163	1			T14	1		T41	2		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	663	1			T3	2		T16	2		T81	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	156	1			T15	1		T81	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	666	1			T13	1		T16	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	195	1			T13	2		T14	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	688	1			T3	2		T4	3		T16	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	156	1			T3	1		T9	1		T182	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	674	1			T3	1		T4	2		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	176	1			T9	1		T195	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	398	1			T3	1		T4	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	159	1			T35	1		T8	1		T98	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	386	1			T16	1		T18	1		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	187	1			T3	1		T13	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	398	1			T4	1		T18	1		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	189	1			T35	1		T8	1		T41	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	392	1			T13	2		T16	1		T18	4
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	142	1			T3	1		T95	1		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	578	1			T3	3		T4	3		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	258	1			T3	4		T13	2		T14	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	883	1			T3	3		T20	2		T36	10
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	240	1			T1	1		T3	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	832	1			T1	2		T3	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	234	1			T14	1		T15	3		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	921	1			T4	3		T13	1		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	141	1			T3	1		T14	1		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	358	1			T13	1		T16	1		T41	4
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	241	1			T36	1		T35	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	473	1			T4	2		T13	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	267	1			T1	2		T13	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	514	1			T1	3		T3	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	233	1			T35	1		T195	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	454	1			T3	1		T4	1		T13	1