Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29078

1

T1

21

T2

2

T3

48

auto[1]

276

1

T13

6

T77

2

T227

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	29086	1			T1	21		T2	2		T3	48
auto[134217728:268435455]	8	1			T227	1		T234	1		T341	2
auto[268435456:402653183]	10	1			T356	1		T375	1		T314	1
auto[402653184:536870911]	12	1			T13	1		T227	1		T268	2
auto[536870912:671088639]	8	1			T13	1		T396	2		T241	1
auto[671088640:805306367]	5	1			T268	1		T234	1		T397	1
auto[805306368:939524095]	9	1			T227	1		T268	1		T398	1
auto[939524096:1073741823]	6	1			T268	1		T375	1		T376	1
auto[1073741824:1207959551]	11	1			T341	1		T376	1		T342	1
auto[1207959552:1342177279]	9	1			T227	2		T376	1		T272	1
auto[1342177280:1476395007]	8	1			T347	1		T247	1		T228	1
auto[1476395008:1610612735]	8	1			T381	1		T376	1		T247	1
auto[1610612736:1744830463]	11	1			T227	1		T317	2		T234	1
auto[1744830464:1879048191]	12	1			T13	1		T227	1		T381	1
auto[1879048192:2013265919]	10	1			T341	1		T375	1		T397	1
auto[2013265920:2147483647]	7	1			T326	1		T397	1		T396	1
auto[2147483648:2281701375]	11	1			T326	1		T341	1		T375	2
auto[2281701376:2415919103]	9	1			T356	1		T326	1		T341	1
auto[2415919104:2550136831]	6	1			T341	1		T375	2		T399	1
auto[2550136832:2684354559]	12	1			T268	1		T317	1		T234	1
auto[2684354560:2818572287]	13	1			T268	2		T317	1		T341	1
auto[2818572288:2952790015]	5	1			T347	1		T342	1		T312	1
auto[2952790016:3087007743]	6	1			T398	1		T247	1		T314	2
auto[3087007744:3221225471]	11	1			T13	1		T234	1		T341	1
auto[3221225472:3355443199]	7	1			T341	1		T398	1		T314	1
auto[3355443200:3489660927]	13	1			T13	1		T77	1		T317	1
auto[3489660928:3623878655]	9	1			T77	1		T347	1		T397	1
auto[3623878656:3758096383]	6	1			T317	1		T347	1		T376	1
auto[3758096384:3892314111]	11	1			T326	1		T317	1		T341	1
auto[3892314112:4026531839]	3	1			T317	1		T342	1		T314	1
auto[4026531840:4160749567]	7	1			T13	1		T341	1		T370	1
auto[4160749568:4294967295]	5	1			T227	1		T317	1		T399	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	29078	1			T1	21		T2	2		T3	48
auto[0:134217727]	auto[1]	8	1			T268	1		T400	1		T272	1
auto[134217728:268435455]	auto[1]	8	1			T227	1		T234	1		T341	2
auto[268435456:402653183]	auto[1]	10	1			T356	1		T375	1		T314	1
auto[402653184:536870911]	auto[1]	12	1			T13	1		T227	1		T268	2
auto[536870912:671088639]	auto[1]	8	1			T13	1		T396	2		T241	1
auto[671088640:805306367]	auto[1]	5	1			T268	1		T234	1		T397	1
auto[805306368:939524095]	auto[1]	9	1			T227	1		T268	1		T398	1
auto[939524096:1073741823]	auto[1]	6	1			T268	1		T375	1		T376	1
auto[1073741824:1207959551]	auto[1]	11	1			T341	1		T376	1		T342	1
auto[1207959552:1342177279]	auto[1]	9	1			T227	2		T376	1		T272	1
auto[1342177280:1476395007]	auto[1]	8	1			T347	1		T247	1		T228	1
auto[1476395008:1610612735]	auto[1]	8	1			T381	1		T376	1		T247	1
auto[1610612736:1744830463]	auto[1]	11	1			T227	1		T317	2		T234	1
auto[1744830464:1879048191]	auto[1]	12	1			T13	1		T227	1		T381	1
auto[1879048192:2013265919]	auto[1]	10	1			T341	1		T375	1		T397	1
auto[2013265920:2147483647]	auto[1]	7	1			T326	1		T397	1		T396	1
auto[2147483648:2281701375]	auto[1]	11	1			T326	1		T341	1		T375	2
auto[2281701376:2415919103]	auto[1]	9	1			T356	1		T326	1		T341	1
auto[2415919104:2550136831]	auto[1]	6	1			T341	1		T375	2		T399	1
auto[2550136832:2684354559]	auto[1]	12	1			T268	1		T317	1		T234	1
auto[2684354560:2818572287]	auto[1]	13	1			T268	2		T317	1		T341	1
auto[2818572288:2952790015]	auto[1]	5	1			T347	1		T342	1		T312	1
auto[2952790016:3087007743]	auto[1]	6	1			T398	1		T247	1		T314	2
auto[3087007744:3221225471]	auto[1]	11	1			T13	1		T234	1		T341	1
auto[3221225472:3355443199]	auto[1]	7	1			T341	1		T398	1		T314	1
auto[3355443200:3489660927]	auto[1]	13	1			T13	1		T77	1		T317	1
auto[3489660928:3623878655]	auto[1]	9	1			T77	1		T347	1		T397	1
auto[3623878656:3758096383]	auto[1]	6	1			T317	1		T347	1		T376	1
auto[3758096384:3892314111]	auto[1]	11	1			T326	1		T317	1		T341	1
auto[3892314112:4026531839]	auto[1]	3	1			T317	1		T342	1		T314	1
auto[4026531840:4160749567]	auto[1]	7	1			T13	1		T341	1		T370	1
auto[4160749568:4294967295]	auto[1]	5	1			T227	1		T317	1		T399	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1466

1

T3

2

T4

8

T13

3

auto[1]

1690

1

T3

2

T4

3

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T35	1		T38	2		T62	2
auto[134217728:268435455]	124	1			T41	1		T49	1		T38	4
auto[268435456:402653183]	97	1			T41	1		T50	1		T62	3
auto[402653184:536870911]	113	1			T13	1		T18	1		T195	1
auto[536870912:671088639]	93	1			T13	1		T18	2		T85	1
auto[671088640:805306367]	94	1			T85	1		T41	1		T42	1
auto[805306368:939524095]	94	1			T195	1		T123	1		T38	1
auto[939524096:1073741823]	89	1			T4	2		T82	1		T41	1
auto[1073741824:1207959551]	95	1			T20	1		T35	1		T99	1
auto[1207959552:1342177279]	119	1			T4	2		T20	1		T95	1
auto[1342177280:1476395007]	93	1			T98	1		T100	1		T62	3
auto[1476395008:1610612735]	98	1			T3	1		T16	1		T9	1
auto[1610612736:1744830463]	109	1			T85	1		T41	1		T86	1
auto[1744830464:1879048191]	95	1			T4	2		T13	2		T16	1
auto[1879048192:2013265919]	83	1			T41	1		T33	1		T48	1
auto[2013265920:2147483647]	91	1			T9	1		T38	3		T62	1
auto[2147483648:2281701375]	87	1			T8	1		T48	1		T124	1
auto[2281701376:2415919103]	106	1			T85	1		T41	1		T29	1
auto[2415919104:2550136831]	97	1			T16	1		T82	1		T85	1
auto[2550136832:2684354559]	108	1			T3	1		T13	1		T20	1
auto[2684354560:2818572287]	102	1			T13	1		T15	1		T29	1
auto[2818572288:2952790015]	79	1			T99	1		T50	2		T38	1
auto[2952790016:3087007743]	79	1			T34	1		T41	1		T123	1
auto[3087007744:3221225471]	108	1			T48	1		T96	1		T50	1
auto[3221225472:3355443199]	104	1			T14	1		T16	1		T18	2
auto[3355443200:3489660927]	96	1			T15	1		T82	1		T29	1
auto[3489660928:3623878655]	94	1			T20	1		T82	3		T41	1
auto[3623878656:3758096383]	112	1			T4	2		T100	1		T38	2
auto[3758096384:3892314111]	95	1			T3	1		T4	2		T18	1
auto[3892314112:4026531839]	98	1			T4	1		T16	1		T28	1
auto[4026531840:4160749567]	106	1			T16	1		T18	1		T41	2
auto[4160749568:4294967295]	105	1			T3	1		T18	1		T20	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T35	1		T38	1		T62	2
auto[0:134217727]	auto[1]	47	1			T38	1		T172	1		T21	1
auto[134217728:268435455]	auto[0]	56	1			T38	2		T62	2		T184	1
auto[134217728:268435455]	auto[1]	68	1			T41	1		T49	1		T38	2
auto[268435456:402653183]	auto[0]	40	1			T62	2		T39	3		T186	1
auto[268435456:402653183]	auto[1]	57	1			T41	1		T50	1		T62	1
auto[402653184:536870911]	auto[0]	52	1			T13	1		T41	1		T98	1
auto[402653184:536870911]	auto[1]	61	1			T18	1		T195	1		T41	1
auto[536870912:671088639]	auto[0]	35	1			T18	2		T85	1		T99	2
auto[536870912:671088639]	auto[1]	58	1			T13	1		T100	2		T124	1
auto[671088640:805306367]	auto[0]	39	1			T196	1		T178	1		T47	1
auto[671088640:805306367]	auto[1]	55	1			T85	1		T41	1		T42	1
auto[805306368:939524095]	auto[0]	46	1			T195	1		T62	1		T196	1
auto[805306368:939524095]	auto[1]	48	1			T123	1		T38	1		T62	2
auto[939524096:1073741823]	auto[0]	44	1			T4	2		T41	1		T50	1
auto[939524096:1073741823]	auto[1]	45	1			T82	1		T49	1		T50	1
auto[1073741824:1207959551]	auto[0]	39	1			T20	1		T99	1		T86	1
auto[1073741824:1207959551]	auto[1]	56	1			T35	1		T123	1		T38	1
auto[1207959552:1342177279]	auto[0]	53	1			T4	1		T20	1		T48	1
auto[1207959552:1342177279]	auto[1]	66	1			T4	1		T95	1		T99	1
auto[1342177280:1476395007]	auto[0]	40	1			T98	1		T100	1		T62	2
auto[1342177280:1476395007]	auto[1]	53	1			T62	1		T184	1		T172	1
auto[1476395008:1610612735]	auto[0]	52	1			T3	1		T38	1		T62	1
auto[1476395008:1610612735]	auto[1]	46	1			T16	1		T9	1		T62	1
auto[1610612736:1744830463]	auto[0]	55	1			T85	1		T41	1		T38	2
auto[1610612736:1744830463]	auto[1]	54	1			T86	1		T62	4		T194	1
auto[1744830464:1879048191]	auto[0]	44	1			T4	2		T13	1		T16	1
auto[1744830464:1879048191]	auto[1]	51	1			T13	1		T39	1		T108	1
auto[1879048192:2013265919]	auto[0]	34	1			T41	1		T48	1		T62	1
auto[1879048192:2013265919]	auto[1]	49	1			T33	1		T50	1		T38	1
auto[2013265920:2147483647]	auto[0]	47	1			T62	1		T114	1		T319	1
auto[2013265920:2147483647]	auto[1]	44	1			T9	1		T38	3		T39	1
auto[2147483648:2281701375]	auto[0]	48	1			T48	1		T39	1		T237	1
auto[2147483648:2281701375]	auto[1]	39	1			T8	1		T124	1		T38	2
auto[2281701376:2415919103]	auto[0]	58	1			T85	1		T41	1		T100	1
auto[2281701376:2415919103]	auto[1]	48	1			T29	1		T123	1		T50	1
auto[2415919104:2550136831]	auto[0]	50	1			T16	1		T82	1		T85	1
auto[2415919104:2550136831]	auto[1]	47	1			T49	1		T124	1		T38	1
auto[2550136832:2684354559]	auto[0]	41	1			T13	1		T41	1		T38	1
auto[2550136832:2684354559]	auto[1]	67	1			T3	1		T20	1		T99	1
auto[2684354560:2818572287]	auto[0]	50	1			T38	1		T62	1		T196	1
auto[2684354560:2818572287]	auto[1]	52	1			T13	1		T15	1		T29	1
auto[2818572288:2952790015]	auto[0]	46	1			T50	1		T38	1		T196	1
auto[2818572288:2952790015]	auto[1]	33	1			T99	1		T50	1		T62	1
auto[2952790016:3087007743]	auto[0]	38	1			T41	1		T50	2		T62	1
auto[2952790016:3087007743]	auto[1]	41	1			T34	1		T123	1		T62	2
auto[3087007744:3221225471]	auto[0]	59	1			T48	1		T62	1		T186	1
auto[3087007744:3221225471]	auto[1]	49	1			T96	1		T50	1		T88	1
auto[3221225472:3355443199]	auto[0]	47	1			T16	1		T18	1		T48	1
auto[3221225472:3355443199]	auto[1]	57	1			T14	1		T18	1		T20	1
auto[3355443200:3489660927]	auto[0]	44	1			T50	1		T77	1		T62	1
auto[3355443200:3489660927]	auto[1]	52	1			T15	1		T82	1		T29	1
auto[3489660928:3623878655]	auto[0]	50	1			T20	1		T82	2		T41	1
auto[3489660928:3623878655]	auto[1]	44	1			T82	1		T86	1		T62	1
auto[3623878656:3758096383]	auto[0]	42	1			T4	1		T62	1		T184	1
auto[3623878656:3758096383]	auto[1]	70	1			T4	1		T100	1		T38	2
auto[3758096384:3892314111]	auto[0]	41	1			T3	1		T4	1		T18	1
auto[3758096384:3892314111]	auto[1]	54	1			T4	1		T41	1		T124	1
auto[3892314112:4026531839]	auto[0]	35	1			T4	1		T16	1		T43	1
auto[3892314112:4026531839]	auto[1]	63	1			T28	1		T96	1		T50	1
auto[4026531840:4160749567]	auto[0]	44	1			T16	1		T18	1		T41	2
auto[4026531840:4160749567]	auto[1]	62	1			T49	1		T38	2		T62	1
auto[4160749568:4294967295]	auto[0]	51	1			T41	1		T98	1		T38	1
auto[4160749568:4294967295]	auto[1]	54	1			T3	1		T18	1		T20	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1498

1

T3

2

T4

8

T13

3

auto[1]

1661

1

T3

2

T4

3

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T16	1		T41	1		T50	1
auto[134217728:268435455]	88	1			T3	1		T15	1		T20	1
auto[268435456:402653183]	85	1			T29	1		T100	1		T62	2
auto[402653184:536870911]	106	1			T13	2		T86	1		T124	1
auto[536870912:671088639]	96	1			T4	1		T18	1		T85	1
auto[671088640:805306367]	107	1			T4	1		T16	1		T18	1
auto[805306368:939524095]	80	1			T34	1		T41	1		T38	1
auto[939524096:1073741823]	91	1			T4	1		T13	1		T41	1
auto[1073741824:1207959551]	98	1			T3	1		T14	1		T9	1
auto[1207959552:1342177279]	96	1			T85	1		T99	1		T123	1
auto[1342177280:1476395007]	107	1			T4	1		T41	1		T50	1
auto[1476395008:1610612735]	89	1			T18	1		T43	1		T38	2
auto[1610612736:1744830463]	94	1			T4	1		T16	1		T18	2
auto[1744830464:1879048191]	92	1			T4	1		T48	1		T49	1
auto[1879048192:2013265919]	102	1			T82	1		T98	1		T100	1
auto[2013265920:2147483647]	112	1			T3	1		T4	1		T16	1
auto[2147483648:2281701375]	103	1			T3	1		T41	1		T86	1
auto[2281701376:2415919103]	99	1			T4	1		T15	1		T18	1
auto[2415919104:2550136831]	99	1			T18	1		T28	1		T38	1
auto[2550136832:2684354559]	110	1			T4	1		T20	2		T41	1
auto[2684354560:2818572287]	84	1			T16	1		T123	1		T38	1
auto[2818572288:2952790015]	104	1			T13	1		T85	1		T41	2
auto[2952790016:3087007743]	99	1			T9	1		T85	1		T41	2
auto[3087007744:3221225471]	106	1			T20	1		T195	1		T85	1
auto[3221225472:3355443199]	96	1			T82	1		T99	1		T96	1
auto[3355443200:3489660927]	100	1			T62	2		T87	1		T194	1
auto[3489660928:3623878655]	114	1			T18	1		T41	1		T99	1
auto[3623878656:3758096383]	95	1			T82	2		T99	1		T100	1
auto[3758096384:3892314111]	81	1			T4	1		T16	1		T20	1
auto[3892314112:4026531839]	87	1			T4	1		T13	1		T20	1
auto[4026531840:4160749567]	107	1			T13	1		T41	2		T124	1
auto[4160749568:4294967295]	118	1			T99	1		T38	1		T62	4

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T16	1		T50	1		T38	1
auto[0:134217727]	auto[1]	63	1			T41	1		T38	2		T62	2
auto[134217728:268435455]	auto[0]	46	1			T20	1		T62	1		T88	1
auto[134217728:268435455]	auto[1]	42	1			T3	1		T15	1		T49	1
auto[268435456:402653183]	auto[0]	40	1			T100	1		T62	2		T184	1
auto[268435456:402653183]	auto[1]	45	1			T29	1		T286	1		T6	1
auto[402653184:536870911]	auto[0]	51	1			T86	1		T184	1		T90	1
auto[402653184:536870911]	auto[1]	55	1			T13	2		T124	1		T50	1
auto[536870912:671088639]	auto[0]	50	1			T18	1		T85	1		T41	1
auto[536870912:671088639]	auto[1]	46	1			T4	1		T50	1		T77	1
auto[671088640:805306367]	auto[0]	64	1			T4	1		T16	1		T82	1
auto[671088640:805306367]	auto[1]	43	1			T18	1		T50	2		T62	3
auto[805306368:939524095]	auto[0]	35	1			T38	1		T62	2		T88	1
auto[805306368:939524095]	auto[1]	45	1			T34	1		T41	1		T62	3
auto[939524096:1073741823]	auto[0]	52	1			T4	1		T13	1		T48	1
auto[939524096:1073741823]	auto[1]	39	1			T41	1		T29	1		T25	2
auto[1073741824:1207959551]	auto[0]	49	1			T3	1		T195	1		T99	1
auto[1073741824:1207959551]	auto[1]	49	1			T14	1		T9	1		T62	2
auto[1207959552:1342177279]	auto[0]	44	1			T85	1		T99	1		T50	1
auto[1207959552:1342177279]	auto[1]	52	1			T123	1		T62	1		T194	1
auto[1342177280:1476395007]	auto[0]	50	1			T4	1		T41	1		T62	3
auto[1342177280:1476395007]	auto[1]	57	1			T50	1		T38	2		T62	2
auto[1476395008:1610612735]	auto[0]	46	1			T43	1		T38	2		T88	1
auto[1476395008:1610612735]	auto[1]	43	1			T18	1		T62	2		T88	1
auto[1610612736:1744830463]	auto[0]	37	1			T4	1		T16	1		T18	1
auto[1610612736:1744830463]	auto[1]	57	1			T18	1		T35	1		T38	3
auto[1744830464:1879048191]	auto[0]	39	1			T4	1		T48	1		T38	2
auto[1744830464:1879048191]	auto[1]	53	1			T49	1		T77	1		T38	2
auto[1879048192:2013265919]	auto[0]	57	1			T82	1		T98	1		T100	1
auto[1879048192:2013265919]	auto[1]	45	1			T49	1		T86	1		T50	2
auto[2013265920:2147483647]	auto[0]	45	1			T16	1		T62	2		T196	1
auto[2013265920:2147483647]	auto[1]	67	1			T3	1		T4	1		T195	1
auto[2147483648:2281701375]	auto[0]	59	1			T3	1		T41	1		T86	1
auto[2147483648:2281701375]	auto[1]	44	1			T77	1		T194	1		T190	1
auto[2281701376:2415919103]	auto[0]	49	1			T4	1		T18	1		T35	1
auto[2281701376:2415919103]	auto[1]	50	1			T15	1		T39	1		T184	1
auto[2415919104:2550136831]	auto[0]	42	1			T18	1		T90	1		T286	1
auto[2415919104:2550136831]	auto[1]	57	1			T28	1		T38	1		T62	1
auto[2550136832:2684354559]	auto[0]	45	1			T4	1		T20	1		T41	1
auto[2550136832:2684354559]	auto[1]	65	1			T20	1		T96	1		T62	1
auto[2684354560:2818572287]	auto[0]	44	1			T62	1		T39	2		T386	1
auto[2684354560:2818572287]	auto[1]	40	1			T16	1		T123	1		T38	1
auto[2818572288:2952790015]	auto[0]	48	1			T85	1		T41	1		T98	1
auto[2818572288:2952790015]	auto[1]	56	1			T13	1		T41	1		T100	1
auto[2952790016:3087007743]	auto[0]	50	1			T41	1		T98	1		T48	1
auto[2952790016:3087007743]	auto[1]	49	1			T9	1		T85	1		T41	1
auto[3087007744:3221225471]	auto[0]	39	1			T41	1		T99	1		T100	1
auto[3087007744:3221225471]	auto[1]	67	1			T20	1		T195	1		T85	1
auto[3221225472:3355443199]	auto[0]	42	1			T99	1		T257	1		T6	1
auto[3221225472:3355443199]	auto[1]	54	1			T82	1		T96	1		T123	1
auto[3355443200:3489660927]	auto[0]	49	1			T62	1		T87	1		T194	1
auto[3355443200:3489660927]	auto[1]	51	1			T62	1		T319	1		T346	1
auto[3489660928:3623878655]	auto[0]	57	1			T18	1		T62	1		T194	1
auto[3489660928:3623878655]	auto[1]	57	1			T41	1		T99	1		T86	1
auto[3623878656:3758096383]	auto[0]	40	1			T82	1		T99	1		T62	2
auto[3623878656:3758096383]	auto[1]	55	1			T82	1		T100	1		T43	1
auto[3758096384:3892314111]	auto[0]	44	1			T16	1		T20	1		T85	1
auto[3758096384:3892314111]	auto[1]	37	1			T4	1		T8	1		T49	1
auto[3892314112:4026531839]	auto[0]	40	1			T4	1		T13	1		T43	1
auto[3892314112:4026531839]	auto[1]	47	1			T20	1		T41	1		T123	1
auto[4026531840:4160749567]	auto[0]	47	1			T13	1		T62	1		T184	1
auto[4026531840:4160749567]	auto[1]	60	1			T41	2		T124	1		T38	2
auto[4160749568:4294967295]	auto[0]	47	1			T99	1		T62	3		T6	1
auto[4160749568:4294967295]	auto[1]	71	1			T38	1		T62	1		T39	3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1459

1

T3

2

T4

7

T13

2

auto[1]

1690

1

T3

2

T4

4

T13

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T4	1		T13	1		T16	1
auto[134217728:268435455]	93	1			T13	1		T9	1		T195	1
auto[268435456:402653183]	89	1			T41	1		T99	1		T50	1
auto[402653184:536870911]	97	1			T3	1		T20	1		T29	1
auto[536870912:671088639]	94	1			T18	1		T49	1		T62	1
auto[671088640:805306367]	101	1			T15	1		T18	1		T20	2
auto[805306368:939524095]	93	1			T8	1		T85	1		T48	1
auto[939524096:1073741823]	93	1			T4	1		T13	1		T20	1
auto[1073741824:1207959551]	100	1			T4	1		T18	1		T98	2
auto[1207959552:1342177279]	84	1			T4	1		T20	1		T48	1
auto[1342177280:1476395007]	91	1			T4	1		T13	1		T14	1
auto[1476395008:1610612735]	76	1			T4	2		T41	1		T50	1
auto[1610612736:1744830463]	110	1			T16	1		T35	1		T99	1
auto[1744830464:1879048191]	81	1			T18	1		T124	1		T38	1
auto[1879048192:2013265919]	106	1			T4	1		T8	1		T41	1
auto[2013265920:2147483647]	111	1			T13	1		T195	1		T100	1
auto[2147483648:2281701375]	113	1			T82	1		T99	1		T50	2
auto[2281701376:2415919103]	99	1			T3	1		T18	1		T82	1
auto[2415919104:2550136831]	99	1			T13	1		T85	1		T41	1
auto[2550136832:2684354559]	86	1			T16	1		T82	1		T41	1
auto[2684354560:2818572287]	103	1			T4	1		T35	1		T41	2
auto[2818572288:2952790015]	105	1			T20	1		T85	1		T38	5
auto[2952790016:3087007743]	102	1			T100	1		T33	1		T124	1
auto[3087007744:3221225471]	108	1			T50	2		T38	1		T62	3
auto[3221225472:3355443199]	98	1			T41	1		T43	1		T124	1
auto[3355443200:3489660927]	95	1			T3	1		T4	1		T82	1
auto[3489660928:3623878655]	115	1			T82	1		T85	1		T48	1
auto[3623878656:3758096383]	101	1			T16	1		T38	2		T62	1
auto[3758096384:3892314111]	124	1			T15	1		T18	2		T41	1
auto[3892314112:4026531839]	97	1			T41	1		T98	1		T49	1
auto[4026531840:4160749567]	89	1			T3	1		T41	1		T86	1
auto[4160749568:4294967295]	88	1			T4	1		T100	2		T50	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T4	1		T16	1		T62	3
auto[0:134217727]	auto[1]	57	1			T13	1		T82	1		T195	1
auto[134217728:268435455]	auto[0]	40	1			T195	1		T41	1		T38	2
auto[134217728:268435455]	auto[1]	53	1			T13	1		T9	1		T100	1
auto[268435456:402653183]	auto[0]	32	1			T41	1		T99	1		T62	1
auto[268435456:402653183]	auto[1]	57	1			T50	1		T62	1		T39	1
auto[402653184:536870911]	auto[0]	49	1			T20	1		T48	1		T38	1
auto[402653184:536870911]	auto[1]	48	1			T3	1		T29	1		T86	1
auto[536870912:671088639]	auto[0]	48	1			T386	1		T235	1		T268	1
auto[536870912:671088639]	auto[1]	46	1			T18	1		T49	1		T62	1
auto[671088640:805306367]	auto[0]	48	1			T38	1		T62	1		T88	1
auto[671088640:805306367]	auto[1]	53	1			T15	1		T18	1		T20	2
auto[805306368:939524095]	auto[0]	40	1			T62	2		T178	1		T64	1
auto[805306368:939524095]	auto[1]	53	1			T8	1		T85	1		T48	1
auto[939524096:1073741823]	auto[0]	50	1			T20	1		T85	1		T41	2
auto[939524096:1073741823]	auto[1]	43	1			T4	1		T13	1		T9	1
auto[1073741824:1207959551]	auto[0]	44	1			T4	1		T18	1		T98	1
auto[1073741824:1207959551]	auto[1]	56	1			T98	1		T123	1		T38	1
auto[1207959552:1342177279]	auto[0]	37	1			T20	1		T62	2		T39	1
auto[1207959552:1342177279]	auto[1]	47	1			T4	1		T48	1		T401	1
auto[1342177280:1476395007]	auto[0]	41	1			T4	1		T13	1		T16	1
auto[1342177280:1476395007]	auto[1]	50	1			T14	1		T16	1		T34	1
auto[1476395008:1610612735]	auto[0]	34	1			T4	1		T88	1		T39	1
auto[1476395008:1610612735]	auto[1]	42	1			T4	1		T41	1		T50	1
auto[1610612736:1744830463]	auto[0]	46	1			T16	1		T35	1		T86	1
auto[1610612736:1744830463]	auto[1]	64	1			T99	1		T49	2		T50	1
auto[1744830464:1879048191]	auto[0]	34	1			T38	1		T62	1		T196	2
auto[1744830464:1879048191]	auto[1]	47	1			T18	1		T124	1		T62	2
auto[1879048192:2013265919]	auto[0]	46	1			T4	1		T43	1		T50	1
auto[1879048192:2013265919]	auto[1]	60	1			T8	1		T41	1		T29	1
auto[2013265920:2147483647]	auto[0]	45	1			T13	1		T86	1		T38	1
auto[2013265920:2147483647]	auto[1]	66	1			T195	1		T100	1		T43	1
auto[2147483648:2281701375]	auto[0]	54	1			T82	1		T99	1		T50	1
auto[2147483648:2281701375]	auto[1]	59	1			T50	1		T38	3		T62	1
auto[2281701376:2415919103]	auto[0]	56	1			T3	1		T18	1		T82	1
auto[2281701376:2415919103]	auto[1]	43	1			T123	1		T38	1		T194	1
auto[2415919104:2550136831]	auto[0]	48	1			T99	1		T392	1		T80	1
auto[2415919104:2550136831]	auto[1]	51	1			T13	1		T85	1		T41	1
auto[2550136832:2684354559]	auto[0]	43	1			T16	1		T82	1		T62	3
auto[2550136832:2684354559]	auto[1]	43	1			T41	1		T96	1		T38	2
auto[2684354560:2818572287]	auto[0]	50	1			T35	1		T41	1		T50	1
auto[2684354560:2818572287]	auto[1]	53	1			T4	1		T41	1		T49	1
auto[2818572288:2952790015]	auto[0]	55	1			T85	1		T38	2		T62	5
auto[2818572288:2952790015]	auto[1]	50	1			T20	1		T38	3		T184	1
auto[2952790016:3087007743]	auto[0]	42	1			T100	1		T62	2		T39	1
auto[2952790016:3087007743]	auto[1]	60	1			T33	1		T124	1		T50	2
auto[3087007744:3221225471]	auto[0]	50	1			T62	2		T175	1		T178	1
auto[3087007744:3221225471]	auto[1]	58	1			T50	2		T38	1		T62	1
auto[3221225472:3355443199]	auto[0]	43	1			T38	1		T114	1		T175	1
auto[3221225472:3355443199]	auto[1]	55	1			T41	1		T43	1		T124	1
auto[3355443200:3489660927]	auto[0]	50	1			T3	1		T4	1		T82	1
auto[3355443200:3489660927]	auto[1]	45	1			T99	1		T62	1		T196	1
auto[3489660928:3623878655]	auto[0]	48	1			T85	1		T48	1		T38	1
auto[3489660928:3623878655]	auto[1]	67	1			T82	1		T123	1		T38	1
auto[3623878656:3758096383]	auto[0]	44	1			T16	1		T62	1		T196	1
auto[3623878656:3758096383]	auto[1]	57	1			T38	2		T190	1		T386	1
auto[3758096384:3892314111]	auto[0]	55	1			T18	2		T41	1		T38	1
auto[3758096384:3892314111]	auto[1]	69	1			T15	1		T124	1		T50	1
auto[3892314112:4026531839]	auto[0]	50	1			T98	1		T62	1		T39	2
auto[3892314112:4026531839]	auto[1]	47	1			T41	1		T49	1		T62	2
auto[4026531840:4160749567]	auto[0]	40	1			T41	1		T38	1		T62	1
auto[4026531840:4160749567]	auto[1]	49	1			T3	1		T86	1		T123	1
auto[4160749568:4294967295]	auto[0]	46	1			T4	1		T50	1		T38	2
auto[4160749568:4294967295]	auto[1]	42	1			T100	2		T50	1		T6	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1478

1

T3

1

T4

8

T13

3

auto[1]

1681

1

T3

3

T4

3

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T29	1		T98	2		T99	1
auto[134217728:268435455]	81	1			T13	1		T18	1		T195	1
auto[268435456:402653183]	92	1			T4	3		T85	1		T50	1
auto[402653184:536870911]	114	1			T16	1		T99	1		T96	1
auto[536870912:671088639]	106	1			T4	1		T41	1		T50	1
auto[671088640:805306367]	101	1			T13	1		T14	1		T18	1
auto[805306368:939524095]	90	1			T85	1		T43	1		T49	1
auto[939524096:1073741823]	85	1			T48	1		T38	1		T62	1
auto[1073741824:1207959551]	102	1			T15	1		T16	1		T41	2
auto[1207959552:1342177279]	105	1			T3	1		T20	1		T123	1
auto[1342177280:1476395007]	99	1			T4	1		T13	1		T41	1
auto[1476395008:1610612735]	93	1			T20	1		T82	1		T98	1
auto[1610612736:1744830463]	94	1			T4	1		T9	1		T195	1
auto[1744830464:1879048191]	94	1			T4	1		T16	1		T20	1
auto[1879048192:2013265919]	95	1			T3	1		T82	1		T41	2
auto[2013265920:2147483647]	103	1			T13	1		T18	1		T82	1
auto[2147483648:2281701375]	109	1			T35	1		T86	1		T123	1
auto[2281701376:2415919103]	89	1			T18	1		T29	1		T86	1
auto[2415919104:2550136831]	100	1			T85	1		T41	1		T49	1
auto[2550136832:2684354559]	110	1			T16	1		T41	2		T100	1
auto[2684354560:2818572287]	100	1			T13	1		T38	1		T62	1
auto[2818572288:2952790015]	106	1			T20	1		T34	1		T9	1
auto[2952790016:3087007743]	97	1			T123	1		T38	5		T62	2
auto[3087007744:3221225471]	99	1			T18	1		T82	1		T8	1
auto[3221225472:3355443199]	109	1			T16	1		T96	1		T38	5
auto[3355443200:3489660927]	86	1			T3	1		T4	1		T15	1
auto[3489660928:3623878655]	108	1			T3	1		T4	1		T13	1
auto[3623878656:3758096383]	102	1			T28	1		T33	1		T48	1
auto[3758096384:3892314111]	84	1			T4	1		T86	1		T123	1
auto[3892314112:4026531839]	102	1			T18	2		T82	1		T195	1
auto[4026531840:4160749567]	111	1			T4	1		T16	1		T41	1
auto[4160749568:4294967295]	97	1			T82	1		T49	1		T123	1