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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4272 1 T3 6 T4 12 T13 10
auto[1] 2049 1 T3 2 T4 10 T13 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 190 1 T13 2 T100 2 T50 4
auto[134217728:268435455] 168 1 T4 2 T82 2 T38 2
auto[268435456:402653183] 174 1 T35 2 T82 2 T195 2
auto[402653184:536870911] 201 1 T4 2 T41 2 T43 2
auto[536870912:671088639] 202 1 T20 2 T82 2 T195 2
auto[671088640:805306367] 216 1 T4 2 T85 2 T41 2
auto[805306368:939524095] 202 1 T18 2 T41 2 T99 2
auto[939524096:1073741823] 196 1 T48 2 T123 2 T50 2
auto[1073741824:1207959551] 246 1 T4 2 T15 2 T18 2
auto[1207959552:1342177279] 170 1 T4 2 T99 2 T43 2
auto[1342177280:1476395007] 190 1 T41 2 T62 6 T39 2
auto[1476395008:1610612735] 220 1 T3 2 T4 2 T9 2
auto[1610612736:1744830463] 180 1 T16 2 T38 2 T62 4
auto[1744830464:1879048191] 200 1 T4 2 T85 2 T96 2
auto[1879048192:2013265919] 176 1 T4 2 T20 2 T41 2
auto[2013265920:2147483647] 182 1 T18 2 T41 4 T38 6
auto[2147483648:2281701375] 186 1 T15 2 T9 2 T195 2
auto[2281701376:2415919103] 192 1 T3 2 T82 2 T100 2
auto[2415919104:2550136831] 224 1 T13 2 T16 2 T82 2
auto[2550136832:2684354559] 230 1 T16 4 T82 2 T29 2
auto[2684354560:2818572287] 174 1 T18 2 T98 2 T100 2
auto[2818572288:2952790015] 218 1 T50 2 T38 2 T62 14
auto[2952790016:3087007743] 178 1 T4 2 T13 2 T41 4
auto[3087007744:3221225471] 202 1 T85 2 T41 6 T100 2
auto[3221225472:3355443199] 218 1 T98 2 T86 2 T38 6
auto[3355443200:3489660927] 208 1 T18 2 T20 2 T41 2
auto[3489660928:3623878655] 206 1 T16 2 T41 2 T95 2
auto[3623878656:3758096383] 208 1 T4 2 T13 2 T18 2
auto[3758096384:3892314111] 216 1 T16 2 T18 2 T20 2
auto[3892314112:4026531839] 168 1 T3 2 T14 2 T35 2
auto[4026531840:4160749567] 188 1 T13 4 T20 2 T41 2
auto[4160749568:4294967295] 192 1 T3 2 T4 2 T18 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 134 1 T13 2 T100 2 T50 4
auto[0:134217727] auto[1] 56 1 T192 2 T235 2 T390 2
auto[134217728:268435455] auto[0] 114 1 T62 6 T39 6 T184 2
auto[134217728:268435455] auto[1] 54 1 T4 2 T82 2 T38 2
auto[268435456:402653183] auto[0] 124 1 T35 2 T82 2 T195 2
auto[268435456:402653183] auto[1] 50 1 T39 2 T135 2 T275 2
auto[402653184:536870911] auto[0] 144 1 T41 2 T43 2 T62 6
auto[402653184:536870911] auto[1] 57 1 T4 2 T62 6 T319 2
auto[536870912:671088639] auto[0] 134 1 T82 2 T85 2 T100 2
auto[536870912:671088639] auto[1] 68 1 T20 2 T195 2 T49 2
auto[671088640:805306367] auto[0] 152 1 T4 2 T85 2 T41 2
auto[671088640:805306367] auto[1] 64 1 T49 2 T86 2 T124 2
auto[805306368:939524095] auto[0] 142 1 T18 2 T99 2 T38 4
auto[805306368:939524095] auto[1] 60 1 T41 2 T172 2 T390 2
auto[939524096:1073741823] auto[0] 126 1 T123 2 T62 2 T196 2
auto[939524096:1073741823] auto[1] 70 1 T48 2 T50 2 T62 2
auto[1073741824:1207959551] auto[0] 164 1 T4 2 T18 2 T20 2
auto[1073741824:1207959551] auto[1] 82 1 T15 2 T85 2 T33 2
auto[1207959552:1342177279] auto[0] 110 1 T99 2 T43 2 T196 2
auto[1207959552:1342177279] auto[1] 60 1 T4 2 T62 2 T196 2
auto[1342177280:1476395007] auto[0] 124 1 T41 2 T62 4 T39 2
auto[1342177280:1476395007] auto[1] 66 1 T62 2 T190 2 T237 2
auto[1476395008:1610612735] auto[0] 148 1 T3 2 T9 2 T62 2
auto[1476395008:1610612735] auto[1] 72 1 T4 2 T41 2 T49 2
auto[1610612736:1744830463] auto[0] 114 1 T38 2 T62 2 T88 2
auto[1610612736:1744830463] auto[1] 66 1 T16 2 T62 2 T196 2
auto[1744830464:1879048191] auto[0] 136 1 T4 2 T85 2 T86 2
auto[1744830464:1879048191] auto[1] 64 1 T96 2 T86 2 T44 2
auto[1879048192:2013265919] auto[0] 128 1 T4 2 T20 2 T41 2
auto[1879048192:2013265919] auto[1] 48 1 T61 2 T6 2 T282 2
auto[2013265920:2147483647] auto[0] 126 1 T18 2 T41 2 T38 4
auto[2013265920:2147483647] auto[1] 56 1 T41 2 T38 2 T62 2
auto[2147483648:2281701375] auto[0] 124 1 T15 2 T98 2 T123 2
auto[2147483648:2281701375] auto[1] 62 1 T9 2 T195 2 T49 2
auto[2281701376:2415919103] auto[0] 130 1 T3 2 T82 2 T100 2
auto[2281701376:2415919103] auto[1] 62 1 T50 4 T62 2 T196 2
auto[2415919104:2550136831] auto[0] 150 1 T13 2 T16 2 T82 2
auto[2415919104:2550136831] auto[1] 74 1 T39 2 T63 2 T89 2
auto[2550136832:2684354559] auto[0] 162 1 T16 4 T82 2 T29 2
auto[2550136832:2684354559] auto[1] 68 1 T77 2 T190 2 T390 2
auto[2684354560:2818572287] auto[0] 104 1 T18 2 T98 2 T38 6
auto[2684354560:2818572287] auto[1] 70 1 T100 2 T38 4 T62 2
auto[2818572288:2952790015] auto[0] 148 1 T50 2 T38 2 T62 10
auto[2818572288:2952790015] auto[1] 70 1 T62 4 T55 2 T199 2
auto[2952790016:3087007743] auto[0] 128 1 T4 2 T13 2 T41 4
auto[2952790016:3087007743] auto[1] 50 1 T123 2 T62 2 T114 2
auto[3087007744:3221225471] auto[0] 138 1 T85 2 T41 6 T100 2
auto[3087007744:3221225471] auto[1] 64 1 T38 2 T114 2 T63 2
auto[3221225472:3355443199] auto[0] 154 1 T86 2 T38 6 T62 4
auto[3221225472:3355443199] auto[1] 64 1 T98 2 T188 2 T194 2
auto[3355443200:3489660927] auto[0] 132 1 T20 2 T29 2 T99 2
auto[3355443200:3489660927] auto[1] 76 1 T18 2 T41 2 T124 2
auto[3489660928:3623878655] auto[0] 120 1 T38 4 T62 2 T88 2
auto[3489660928:3623878655] auto[1] 86 1 T16 2 T41 2 T95 2
auto[3623878656:3758096383] auto[0] 136 1 T13 2 T38 2 T62 4
auto[3623878656:3758096383] auto[1] 72 1 T4 2 T18 2 T29 2
auto[3758096384:3892314111] auto[0] 146 1 T16 2 T18 2 T8 2
auto[3758096384:3892314111] auto[1] 70 1 T20 2 T50 2 T39 2
auto[3892314112:4026531839] auto[0] 104 1 T3 2 T35 2 T99 2
auto[3892314112:4026531839] auto[1] 64 1 T14 2 T28 2 T42 2
auto[4026531840:4160749567] auto[0] 132 1 T13 2 T20 2 T41 2
auto[4026531840:4160749567] auto[1] 56 1 T13 2 T88 2 T25 2
auto[4160749568:4294967295] auto[0] 144 1 T4 2 T18 2 T99 2
auto[4160749568:4294967295] auto[1] 48 1 T3 2 T62 2 T39 2

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