Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2727

1

T3

4

T4

11

T13

6

auto[1]

284

1

T13

8

T77

1

T227

10

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T13	1		T18	1		T35	1
auto[134217728:268435455]	101	1			T14	1		T18	1		T41	1
auto[268435456:402653183]	85	1			T16	1		T20	1		T62	4
auto[402653184:536870911]	81	1			T16	2		T41	1		T62	2
auto[536870912:671088639]	87	1			T82	1		T85	1		T99	1
auto[671088640:805306367]	97	1			T4	1		T18	1		T82	2
auto[805306368:939524095]	102	1			T16	1		T99	1		T50	1
auto[939524096:1073741823]	86	1			T16	1		T18	1		T100	1
auto[1073741824:1207959551]	109	1			T4	1		T13	1		T34	1
auto[1207959552:1342177279]	99	1			T15	1		T41	2		T50	2
auto[1342177280:1476395007]	94	1			T3	1		T95	1		T123	2
auto[1476395008:1610612735]	112	1			T99	1		T100	1		T49	1
auto[1610612736:1744830463]	94	1			T13	1		T20	1		T28	1
auto[1744830464:1879048191]	98	1			T18	1		T8	1		T41	1
auto[1879048192:2013265919]	86	1			T4	1		T13	1		T124	1
auto[2013265920:2147483647]	88	1			T15	1		T38	1		T62	1
auto[2147483648:2281701375]	98	1			T4	3		T13	1		T82	1
auto[2281701376:2415919103]	112	1			T13	1		T82	1		T41	1
auto[2415919104:2550136831]	93	1			T4	1		T20	1		T50	1
auto[2550136832:2684354559]	85	1			T13	1		T195	1		T38	4
auto[2684354560:2818572287]	97	1			T4	1		T18	1		T85	1
auto[2818572288:2952790015]	78	1			T3	1		T9	1		T85	1
auto[2952790016:3087007743]	97	1			T4	1		T35	1		T8	1
auto[3087007744:3221225471]	91	1			T13	2		T16	1		T86	1
auto[3221225472:3355443199]	95	1			T3	1		T13	1		T20	1
auto[3355443200:3489660927]	98	1			T195	1		T99	1		T100	1
auto[3489660928:3623878655]	104	1			T20	1		T100	1		T62	2
auto[3623878656:3758096383]	82	1			T18	1		T196	1		T87	1
auto[3758096384:3892314111]	80	1			T4	1		T195	1		T86	1
auto[3892314112:4026531839]	112	1			T13	1		T85	1		T41	2
auto[4026531840:4160749567]	95	1			T3	1		T13	1		T20	1
auto[4160749568:4294967295]	79	1			T4	1		T13	2		T18	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	85	1			T13	1		T18	1		T35	1
auto[0:134217727]	auto[1]	11	1			T381	1		T317	2		T403	1
auto[134217728:268435455]	auto[0]	94	1			T14	1		T18	1		T41	1
auto[134217728:268435455]	auto[1]	7	1			T381	1		T317	1		T397	2
auto[268435456:402653183]	auto[0]	81	1			T16	1		T20	1		T62	4
auto[268435456:402653183]	auto[1]	4	1			T347	1		T370	2		T405	1
auto[402653184:536870911]	auto[0]	77	1			T16	2		T41	1		T62	2
auto[402653184:536870911]	auto[1]	4	1			T375	1		T404	1		T413	1
auto[536870912:671088639]	auto[0]	79	1			T82	1		T85	1		T99	1
auto[536870912:671088639]	auto[1]	8	1			T227	1		T326	1		T347	1
auto[671088640:805306367]	auto[0]	84	1			T4	1		T18	1		T82	2
auto[671088640:805306367]	auto[1]	13	1			T77	1		T341	1		T347	1
auto[805306368:939524095]	auto[0]	86	1			T16	1		T99	1		T50	1
auto[805306368:939524095]	auto[1]	16	1			T234	1		T341	1		T347	1
auto[939524096:1073741823]	auto[0]	79	1			T16	1		T18	1		T100	1
auto[939524096:1073741823]	auto[1]	7	1			T317	1		T272	1		T314	1
auto[1073741824:1207959551]	auto[0]	102	1			T4	1		T34	1		T86	1
auto[1073741824:1207959551]	auto[1]	7	1			T13	1		T227	1		T342	1
auto[1207959552:1342177279]	auto[0]	91	1			T15	1		T41	2		T50	2
auto[1207959552:1342177279]	auto[1]	8	1			T227	1		T397	1		T398	1
auto[1342177280:1476395007]	auto[0]	87	1			T3	1		T95	1		T123	2
auto[1342177280:1476395007]	auto[1]	7	1			T356	1		T403	1		T376	1
auto[1476395008:1610612735]	auto[0]	100	1			T99	1		T100	1		T49	1
auto[1476395008:1610612735]	auto[1]	12	1			T381	1		T341	1		T375	1
auto[1610612736:1744830463]	auto[0]	85	1			T20	1		T28	1		T85	1
auto[1610612736:1744830463]	auto[1]	9	1			T13	1		T227	1		T234	1
auto[1744830464:1879048191]	auto[0]	88	1			T18	1		T8	1		T41	1
auto[1744830464:1879048191]	auto[1]	10	1			T376	1		T247	1		T228	1
auto[1879048192:2013265919]	auto[0]	79	1			T4	1		T124	1		T50	1
auto[1879048192:2013265919]	auto[1]	7	1			T13	1		T381	1		T342	1
auto[2013265920:2147483647]	auto[0]	75	1			T15	1		T38	1		T62	1
auto[2013265920:2147483647]	auto[1]	13	1			T268	1		T317	1		T397	1
auto[2147483648:2281701375]	auto[0]	89	1			T4	3		T82	1		T85	1
auto[2147483648:2281701375]	auto[1]	9	1			T13	1		T268	3		T375	1
auto[2281701376:2415919103]	auto[0]	100	1			T82	1		T41	1		T98	1
auto[2281701376:2415919103]	auto[1]	12	1			T13	1		T227	1		T326	1
auto[2415919104:2550136831]	auto[0]	83	1			T4	1		T20	1		T50	1
auto[2415919104:2550136831]	auto[1]	10	1			T227	1		T341	2		T342	2
auto[2550136832:2684354559]	auto[0]	79	1			T13	1		T195	1		T38	4
auto[2550136832:2684354559]	auto[1]	6	1			T234	1		T272	1		T396	1
auto[2684354560:2818572287]	auto[0]	86	1			T4	1		T18	1		T85	1
auto[2684354560:2818572287]	auto[1]	11	1			T227	2		T326	1		T317	2
auto[2818572288:2952790015]	auto[0]	72	1			T3	1		T9	1		T85	1
auto[2818572288:2952790015]	auto[1]	6	1			T342	1		T397	1		T329	1
auto[2952790016:3087007743]	auto[0]	86	1			T4	1		T35	1		T8	1
auto[2952790016:3087007743]	auto[1]	11	1			T381	2		T347	1		T247	1
auto[3087007744:3221225471]	auto[0]	83	1			T13	2		T16	1		T86	1
auto[3087007744:3221225471]	auto[1]	8	1			T268	1		T317	1		T342	2
auto[3221225472:3355443199]	auto[0]	86	1			T3	1		T20	1		T41	2
auto[3221225472:3355443199]	auto[1]	9	1			T13	1		T268	1		T341	1
auto[3355443200:3489660927]	auto[0]	89	1			T195	1		T99	1		T100	1
auto[3355443200:3489660927]	auto[1]	9	1			T400	3		T376	1		T414	1
auto[3489660928:3623878655]	auto[0]	95	1			T20	1		T100	1		T62	2
auto[3489660928:3623878655]	auto[1]	9	1			T381	1		T268	1		T342	1
auto[3623878656:3758096383]	auto[0]	73	1			T18	1		T196	1		T87	1
auto[3623878656:3758096383]	auto[1]	9	1			T268	1		T375	1		T247	1
auto[3758096384:3892314111]	auto[0]	72	1			T4	1		T195	1		T86	1
auto[3758096384:3892314111]	auto[1]	8	1			T227	1		T341	1		T272	1
auto[3892314112:4026531839]	auto[0]	103	1			T85	1		T41	2		T99	1
auto[3892314112:4026531839]	auto[1]	9	1			T13	1		T227	1		T341	2
auto[4026531840:4160749567]	auto[0]	86	1			T3	1		T13	1		T20	1
auto[4026531840:4160749567]	auto[1]	9	1			T317	1		T375	1		T396	1
auto[4160749568:4294967295]	auto[0]	73	1			T4	1		T13	1		T18	1
auto[4160749568:4294967295]	auto[1]	6	1			T13	1		T381	1		T247	1