Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.82 99.10 97.71 98.67 100.00 99.11 98.41 91.71


Total test records in report: 1072
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T1008 /workspace/coverage/default/10.keymgr_sideload_kmac.386756950 Mar 09 04:53:52 PM PST 24 Mar 09 04:53:56 PM PST 24 254595696 ps
T1009 /workspace/coverage/default/7.keymgr_smoke.3313947761 Mar 09 04:53:46 PM PST 24 Mar 09 04:53:53 PM PST 24 358353624 ps
T1010 /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2739227160 Mar 09 04:54:13 PM PST 24 Mar 09 04:54:16 PM PST 24 116397991 ps
T1011 /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2614557550 Mar 09 04:53:50 PM PST 24 Mar 09 04:53:56 PM PST 24 690180690 ps
T1012 /workspace/coverage/default/14.keymgr_random.2617727350 Mar 09 04:53:58 PM PST 24 Mar 09 04:54:02 PM PST 24 380389357 ps
T1013 /workspace/coverage/default/39.keymgr_cfg_regwen.359975733 Mar 09 04:55:13 PM PST 24 Mar 09 04:57:30 PM PST 24 2545737120 ps
T1014 /workspace/coverage/default/9.keymgr_sw_invalid_input.2238745566 Mar 09 04:53:46 PM PST 24 Mar 09 04:53:55 PM PST 24 2345358908 ps
T1015 /workspace/coverage/default/49.keymgr_sw_invalid_input.820820330 Mar 09 04:55:31 PM PST 24 Mar 09 04:55:34 PM PST 24 161874578 ps
T1016 /workspace/coverage/default/47.keymgr_lc_disable.1941976956 Mar 09 04:55:26 PM PST 24 Mar 09 04:55:32 PM PST 24 187549201 ps
T1017 /workspace/coverage/default/49.keymgr_random.196176214 Mar 09 04:55:30 PM PST 24 Mar 09 04:55:41 PM PST 24 339960753 ps
T1018 /workspace/coverage/default/47.keymgr_sw_invalid_input.2764602846 Mar 09 04:55:36 PM PST 24 Mar 09 04:55:41 PM PST 24 185966060 ps
T1019 /workspace/coverage/default/35.keymgr_stress_all.2896334664 Mar 09 04:54:52 PM PST 24 Mar 09 04:54:55 PM PST 24 404094030 ps
T1020 /workspace/coverage/default/37.keymgr_sw_invalid_input.2956881782 Mar 09 04:54:48 PM PST 24 Mar 09 04:55:19 PM PST 24 1042551674 ps
T339 /workspace/coverage/default/17.keymgr_kmac_rsp_err.1820590981 Mar 09 04:54:28 PM PST 24 Mar 09 04:54:55 PM PST 24 1755058732 ps
T224 /workspace/coverage/default/5.keymgr_stress_all.1882765855 Mar 09 04:53:39 PM PST 24 Mar 09 04:54:25 PM PST 24 4436543520 ps
T1021 /workspace/coverage/default/35.keymgr_sideload_protect.3255584651 Mar 09 04:54:48 PM PST 24 Mar 09 04:54:51 PM PST 24 579678015 ps
T1022 /workspace/coverage/default/1.keymgr_sideload_protect.4133179528 Mar 09 04:53:28 PM PST 24 Mar 09 04:53:32 PM PST 24 146271992 ps
T1023 /workspace/coverage/default/43.keymgr_sideload_protect.3412501387 Mar 09 04:55:01 PM PST 24 Mar 09 04:55:07 PM PST 24 534937147 ps
T1024 /workspace/coverage/default/35.keymgr_smoke.1588078687 Mar 09 04:54:51 PM PST 24 Mar 09 04:54:57 PM PST 24 200741112 ps
T1025 /workspace/coverage/default/26.keymgr_stress_all.1747638157 Mar 09 04:54:20 PM PST 24 Mar 09 04:55:02 PM PST 24 3151690152 ps
T1026 /workspace/coverage/default/16.keymgr_custom_cm.2207101330 Mar 09 04:54:05 PM PST 24 Mar 09 04:54:16 PM PST 24 883359534 ps
T1027 /workspace/coverage/default/31.keymgr_lc_disable.635133509 Mar 09 04:54:47 PM PST 24 Mar 09 04:54:50 PM PST 24 127384071 ps
T1028 /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3024898715 Mar 09 04:54:21 PM PST 24 Mar 09 04:54:25 PM PST 24 76049566 ps
T1029 /workspace/coverage/default/17.keymgr_sw_invalid_input.4229421609 Mar 09 04:53:58 PM PST 24 Mar 09 04:54:10 PM PST 24 1083373444 ps
T1030 /workspace/coverage/default/25.keymgr_custom_cm.3148119328 Mar 09 04:54:32 PM PST 24 Mar 09 04:54:37 PM PST 24 106051614 ps
T412 /workspace/coverage/default/17.keymgr_cfg_regwen.2696429161 Mar 09 04:54:05 PM PST 24 Mar 09 04:54:15 PM PST 24 183606727 ps
T1031 /workspace/coverage/default/36.keymgr_smoke.1851696018 Mar 09 04:54:52 PM PST 24 Mar 09 04:55:01 PM PST 24 71841876 ps
T1032 /workspace/coverage/default/25.keymgr_direct_to_disabled.87210395 Mar 09 04:54:18 PM PST 24 Mar 09 04:54:20 PM PST 24 46797311 ps
T1033 /workspace/coverage/default/15.keymgr_random.3532148471 Mar 09 04:53:55 PM PST 24 Mar 09 04:54:02 PM PST 24 262779981 ps
T1034 /workspace/coverage/default/35.keymgr_hwsw_invalid_input.234356268 Mar 09 04:54:48 PM PST 24 Mar 09 04:54:57 PM PST 24 317625657 ps
T1035 /workspace/coverage/default/21.keymgr_stress_all.2991209882 Mar 09 04:54:26 PM PST 24 Mar 09 04:54:53 PM PST 24 3929909060 ps
T271 /workspace/coverage/default/9.keymgr_cfg_regwen.40760845 Mar 09 04:53:57 PM PST 24 Mar 09 04:55:29 PM PST 24 1689668420 ps
T1036 /workspace/coverage/default/37.keymgr_kmac_rsp_err.2245634818 Mar 09 04:54:59 PM PST 24 Mar 09 04:55:09 PM PST 24 61194926 ps
T1037 /workspace/coverage/default/34.keymgr_sideload_aes.2829765810 Mar 09 04:54:51 PM PST 24 Mar 09 04:54:53 PM PST 24 387809573 ps
T1038 /workspace/coverage/default/42.keymgr_direct_to_disabled.1235567948 Mar 09 04:54:51 PM PST 24 Mar 09 04:54:55 PM PST 24 60489127 ps
T1039 /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3380682601 Mar 09 04:54:13 PM PST 24 Mar 09 04:54:15 PM PST 24 50779693 ps
T1040 /workspace/coverage/default/9.keymgr_custom_cm.2364363198 Mar 09 04:53:39 PM PST 24 Mar 09 04:53:42 PM PST 24 68459545 ps
T1041 /workspace/coverage/default/39.keymgr_alert_test.3408133675 Mar 09 04:54:50 PM PST 24 Mar 09 04:54:51 PM PST 24 18622402 ps
T145 /workspace/coverage/default/20.keymgr_custom_cm.2923083261 Mar 09 04:54:13 PM PST 24 Mar 09 04:54:17 PM PST 24 134958966 ps
T1042 /workspace/coverage/default/0.keymgr_sideload_otbn.2937689697 Mar 09 04:53:16 PM PST 24 Mar 09 04:53:41 PM PST 24 965887277 ps
T1043 /workspace/coverage/default/10.keymgr_kmac_rsp_err.2274665831 Mar 09 04:53:50 PM PST 24 Mar 09 04:53:57 PM PST 24 430462683 ps
T1044 /workspace/coverage/default/41.keymgr_sideload_protect.1224538034 Mar 09 04:54:50 PM PST 24 Mar 09 04:54:52 PM PST 24 78490027 ps
T1045 /workspace/coverage/default/28.keymgr_custom_cm.3384369785 Mar 09 04:54:34 PM PST 24 Mar 09 04:54:38 PM PST 24 702811766 ps
T1046 /workspace/coverage/default/15.keymgr_smoke.917785400 Mar 09 04:53:57 PM PST 24 Mar 09 04:54:05 PM PST 24 212433696 ps
T1047 /workspace/coverage/default/2.keymgr_smoke.552907736 Mar 09 04:53:29 PM PST 24 Mar 09 04:53:32 PM PST 24 57587368 ps
T1048 /workspace/coverage/default/5.keymgr_sideload_kmac.2829947320 Mar 09 04:53:44 PM PST 24 Mar 09 04:53:46 PM PST 24 29816723 ps
T1049 /workspace/coverage/default/40.keymgr_sideload_kmac.705443175 Mar 09 04:55:01 PM PST 24 Mar 09 04:55:07 PM PST 24 148946694 ps
T1050 /workspace/coverage/default/13.keymgr_sideload_otbn.2001094933 Mar 09 04:53:57 PM PST 24 Mar 09 04:54:12 PM PST 24 1040614635 ps
T1051 /workspace/coverage/default/32.keymgr_direct_to_disabled.2381185643 Mar 09 04:54:47 PM PST 24 Mar 09 04:54:50 PM PST 24 74745306 ps
T1052 /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1494820814 Mar 09 04:53:43 PM PST 24 Mar 09 04:53:49 PM PST 24 462898730 ps
T1053 /workspace/coverage/default/40.keymgr_sideload_aes.1047386873 Mar 09 04:54:57 PM PST 24 Mar 09 04:55:43 PM PST 24 2208247706 ps
T1054 /workspace/coverage/default/37.keymgr_sideload_otbn.3531199219 Mar 09 04:54:48 PM PST 24 Mar 09 04:54:52 PM PST 24 120743635 ps
T1055 /workspace/coverage/default/20.keymgr_direct_to_disabled.1436481686 Mar 09 04:53:55 PM PST 24 Mar 09 04:54:09 PM PST 24 2847921177 ps
T1056 /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3166794555 Mar 09 04:54:12 PM PST 24 Mar 09 04:54:20 PM PST 24 406983068 ps
T1057 /workspace/coverage/default/33.keymgr_lc_disable.3210362295 Mar 09 04:54:59 PM PST 24 Mar 09 04:55:03 PM PST 24 137040425 ps
T1058 /workspace/coverage/default/3.keymgr_sw_invalid_input.1130679654 Mar 09 04:53:43 PM PST 24 Mar 09 04:53:47 PM PST 24 178897143 ps
T1059 /workspace/coverage/default/19.keymgr_random.251868611 Mar 09 04:54:07 PM PST 24 Mar 09 04:54:12 PM PST 24 227583998 ps
T226 /workspace/coverage/default/36.keymgr_lc_disable.15355377 Mar 09 04:54:50 PM PST 24 Mar 09 04:54:54 PM PST 24 1537324566 ps
T1060 /workspace/coverage/default/21.keymgr_sideload_otbn.1170815015 Mar 09 04:53:57 PM PST 24 Mar 09 04:54:03 PM PST 24 897861694 ps
T1061 /workspace/coverage/default/37.keymgr_custom_cm.3072836278 Mar 09 04:55:12 PM PST 24 Mar 09 04:55:18 PM PST 24 355025367 ps
T1062 /workspace/coverage/default/23.keymgr_sideload_otbn.2612538715 Mar 09 04:54:09 PM PST 24 Mar 09 04:54:13 PM PST 24 421756990 ps
T1063 /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3534110595 Mar 09 04:55:31 PM PST 24 Mar 09 04:55:34 PM PST 24 57017977 ps
T1064 /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3874336401 Mar 09 04:53:47 PM PST 24 Mar 09 04:54:05 PM PST 24 620843847 ps
T1065 /workspace/coverage/default/3.keymgr_sideload_kmac.1748507863 Mar 09 04:53:18 PM PST 24 Mar 09 04:53:23 PM PST 24 175747104 ps
T1066 /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3458904035 Mar 09 04:54:28 PM PST 24 Mar 09 04:54:31 PM PST 24 32759447 ps
T1067 /workspace/coverage/default/13.keymgr_alert_test.2656014591 Mar 09 04:53:49 PM PST 24 Mar 09 04:53:50 PM PST 24 16920450 ps
T1068 /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1568022292 Mar 09 04:55:18 PM PST 24 Mar 09 04:55:26 PM PST 24 209611475 ps
T1069 /workspace/coverage/default/44.keymgr_sideload_otbn.3387341139 Mar 09 04:55:22 PM PST 24 Mar 09 04:55:28 PM PST 24 664784168 ps
T1070 /workspace/coverage/default/19.keymgr_alert_test.121203859 Mar 09 04:54:09 PM PST 24 Mar 09 04:54:10 PM PST 24 14537214 ps
T1071 /workspace/coverage/default/24.keymgr_smoke.3286149107 Mar 09 04:54:15 PM PST 24 Mar 09 04:54:21 PM PST 24 163871594 ps
T139 /workspace/coverage/default/7.keymgr_custom_cm.2232638256 Mar 09 04:53:49 PM PST 24 Mar 09 04:53:56 PM PST 24 289479377 ps
T1072 /workspace/coverage/default/39.keymgr_sideload_otbn.1276228005 Mar 09 04:54:58 PM PST 24 Mar 09 04:55:05 PM PST 24 1553181155 ps

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.320566768
Short name T18
Test name
Test status
Simulation time 224580318 ps
CPU time 5.1 seconds
Started Mar 09 04:54:01 PM PST 24
Finished Mar 09 04:54:06 PM PST 24
Peak memory 222468 kb
Host smart-81fe98bb-2be4-49e2-9b46-46b83019be46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320566768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.320566768
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3733820273
Short name T62
Test name
Test status
Simulation time 4060408134 ps
CPU time 44.76 seconds
Started Mar 09 04:54:18 PM PST 24
Finished Mar 09 04:55:03 PM PST 24
Peak memory 222580 kb
Host smart-fb68dbde-3c05-4f76-9359-d6cc64783fc5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733820273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3733820273
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2601158418
Short name T34
Test name
Test status
Simulation time 114188643 ps
CPU time 6.02 seconds
Started Mar 09 04:55:17 PM PST 24
Finished Mar 09 04:55:24 PM PST 24
Peak memory 222660 kb
Host smart-c76746d5-1117-4077-9523-7dd6c4c10ebe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601158418 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2601158418
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2258122981
Short name T5
Test name
Test status
Simulation time 2631497439 ps
CPU time 40.48 seconds
Started Mar 09 04:53:30 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 236084 kb
Host smart-19e48493-1652-4300-b4cc-ff3264d9d46c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258122981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2258122981
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1708952997
Short name T38
Test name
Test status
Simulation time 1199599991 ps
CPU time 33.26 seconds
Started Mar 09 04:54:19 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 215820 kb
Host smart-4903f47d-f199-44b1-95b8-294843ea498a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708952997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1708952997
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1343988895
Short name T109
Test name
Test status
Simulation time 188489646 ps
CPU time 5.37 seconds
Started Mar 09 02:03:58 PM PST 24
Finished Mar 09 02:04:04 PM PST 24
Peak memory 222012 kb
Host smart-7f787e5c-7295-4e10-b85d-e80e973968aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343988895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1343988895
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2813266194
Short name T44
Test name
Test status
Simulation time 1704485629 ps
CPU time 57.24 seconds
Started Mar 09 04:55:37 PM PST 24
Finished Mar 09 04:56:34 PM PST 24
Peak memory 222492 kb
Host smart-f758028e-edbd-4559-9241-8fa8bd2b8fcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813266194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2813266194
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3302632127
Short name T9
Test name
Test status
Simulation time 123389906 ps
CPU time 1.55 seconds
Started Mar 09 04:54:43 PM PST 24
Finished Mar 09 04:54:44 PM PST 24
Peak memory 208632 kb
Host smart-f84700d6-d3b8-431b-9cfa-36252df1879f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302632127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3302632127
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3030597425
Short name T13
Test name
Test status
Simulation time 63920597 ps
CPU time 4.3 seconds
Started Mar 09 04:54:26 PM PST 24
Finished Mar 09 04:54:31 PM PST 24
Peak memory 214772 kb
Host smart-50d92fa2-bbbe-47e8-820d-eba9bd9fb6f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3030597425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3030597425
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.944362405
Short name T6
Test name
Test status
Simulation time 8406663130 ps
CPU time 151.73 seconds
Started Mar 09 04:55:08 PM PST 24
Finished Mar 09 04:57:40 PM PST 24
Peak memory 215992 kb
Host smart-b02d93c0-e072-4dc7-b898-326102120f2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944362405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.944362405
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.4147098857
Short name T370
Test name
Test status
Simulation time 7126944412 ps
CPU time 102.5 seconds
Started Mar 09 04:54:01 PM PST 24
Finished Mar 09 04:55:44 PM PST 24
Peak memory 221100 kb
Host smart-49fbc446-a560-4804-8d8a-8ace9192ef07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4147098857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.4147098857
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2777172177
Short name T105
Test name
Test status
Simulation time 140932444 ps
CPU time 4.77 seconds
Started Mar 09 02:04:05 PM PST 24
Finished Mar 09 02:04:10 PM PST 24
Peak memory 213764 kb
Host smart-fb20c8cd-2bfd-47f6-ae48-07bd20dcc73a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777172177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2777172177
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3594649778
Short name T317
Test name
Test status
Simulation time 287242271 ps
CPU time 16.47 seconds
Started Mar 09 04:54:33 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 215116 kb
Host smart-c58afd7a-65a7-4c50-a0ac-9e7d49028f70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594649778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3594649778
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.989646660
Short name T108
Test name
Test status
Simulation time 127661146 ps
CPU time 7.84 seconds
Started Mar 09 04:53:14 PM PST 24
Finished Mar 09 04:53:22 PM PST 24
Peak memory 222612 kb
Host smart-162d7360-9748-4821-8961-2506e17826e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989646660 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.989646660
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2320757768
Short name T986
Test name
Test status
Simulation time 11100869192 ps
CPU time 151.72 seconds
Started Mar 09 04:53:51 PM PST 24
Finished Mar 09 04:56:23 PM PST 24
Peak memory 222524 kb
Host smart-a17a0594-bdbe-442a-a038-633023cb2c8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2320757768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2320757768
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.4005075112
Short name T39
Test name
Test status
Simulation time 17707311600 ps
CPU time 39.67 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:55:29 PM PST 24
Peak memory 221264 kb
Host smart-a1ecc2d5-1c57-4416-8eb6-15b4d2ee8fd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005075112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.4005075112
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2983168860
Short name T341
Test name
Test status
Simulation time 2402548766 ps
CPU time 15.57 seconds
Started Mar 09 04:55:03 PM PST 24
Finished Mar 09 04:55:18 PM PST 24
Peak memory 214372 kb
Host smart-370a51ab-e114-4594-ab5d-252bd78f575d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2983168860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2983168860
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2492505555
Short name T245
Test name
Test status
Simulation time 109723849 ps
CPU time 3.18 seconds
Started Mar 09 04:54:06 PM PST 24
Finished Mar 09 04:54:09 PM PST 24
Peak memory 209344 kb
Host smart-411f91d0-fc66-495b-8170-5b013a20b711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492505555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2492505555
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.157756956
Short name T41
Test name
Test status
Simulation time 3429226138 ps
CPU time 43.58 seconds
Started Mar 09 04:54:00 PM PST 24
Finished Mar 09 04:54:44 PM PST 24
Peak memory 216300 kb
Host smart-b7b48ae0-df87-40c9-a98f-9433fda01116
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157756956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.157756956
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2696429161
Short name T412
Test name
Test status
Simulation time 183606727 ps
CPU time 10.41 seconds
Started Mar 09 04:54:05 PM PST 24
Finished Mar 09 04:54:15 PM PST 24
Peak memory 214312 kb
Host smart-520f818a-6274-4726-8ab7-2d23c1527f67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2696429161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2696429161
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.631251991
Short name T268
Test name
Test status
Simulation time 92565887 ps
CPU time 5.47 seconds
Started Mar 09 04:55:00 PM PST 24
Finished Mar 09 04:55:05 PM PST 24
Peak memory 215632 kb
Host smart-530989df-704c-474d-ac03-38fb8bfe1341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=631251991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.631251991
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1990375550
Short name T70
Test name
Test status
Simulation time 4073338118 ps
CPU time 38.87 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:40 PM PST 24
Peak memory 217144 kb
Host smart-b7c71050-7f20-4a8b-9f26-b861000b38ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990375550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1990375550
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.4039663021
Short name T32
Test name
Test status
Simulation time 943476252 ps
CPU time 11.73 seconds
Started Mar 09 04:55:26 PM PST 24
Finished Mar 09 04:55:37 PM PST 24
Peak memory 220140 kb
Host smart-476ae2a3-0b0b-4733-a5dc-de812aed2862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039663021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.4039663021
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.848932588
Short name T151
Test name
Test status
Simulation time 235149558 ps
CPU time 6.46 seconds
Started Mar 09 02:03:44 PM PST 24
Finished Mar 09 02:03:50 PM PST 24
Peak memory 213572 kb
Host smart-8b1cb079-687a-4015-90c9-2af910f0528b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848932588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
848932588
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.4051463285
Short name T4
Test name
Test status
Simulation time 262598228 ps
CPU time 8.24 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:57 PM PST 24
Peak memory 215128 kb
Host smart-f93baea7-6959-41b4-9e20-41bd57f998b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051463285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.4051463285
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3450964661
Short name T227
Test name
Test status
Simulation time 196603223 ps
CPU time 11.44 seconds
Started Mar 09 04:53:51 PM PST 24
Finished Mar 09 04:54:08 PM PST 24
Peak memory 214324 kb
Host smart-6ba0da73-bcf4-464b-84bc-5225116adecc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3450964661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3450964661
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2627054445
Short name T875
Test name
Test status
Simulation time 1116990835 ps
CPU time 6.17 seconds
Started Mar 09 04:53:41 PM PST 24
Finished Mar 09 04:53:48 PM PST 24
Peak memory 209864 kb
Host smart-ecf7619f-d549-4c03-aba1-d7359fbb60c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627054445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2627054445
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.487064738
Short name T216
Test name
Test status
Simulation time 128648663323 ps
CPU time 701.5 seconds
Started Mar 09 04:54:04 PM PST 24
Finished Mar 09 05:05:46 PM PST 24
Peak memory 222536 kb
Host smart-e31e5166-04df-4118-b7df-e6f228a13b13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487064738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.487064738
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.749828227
Short name T142
Test name
Test status
Simulation time 1396925268 ps
CPU time 14.07 seconds
Started Mar 09 04:54:27 PM PST 24
Finished Mar 09 04:54:41 PM PST 24
Peak memory 222640 kb
Host smart-d52b9dc1-c29b-4f8b-a445-1203b6641446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749828227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.749828227
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.514710233
Short name T324
Test name
Test status
Simulation time 163660753 ps
CPU time 3.56 seconds
Started Mar 09 04:55:25 PM PST 24
Finished Mar 09 04:55:28 PM PST 24
Peak memory 209728 kb
Host smart-e273a9ea-78d2-44d5-b2f3-e8046801d94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514710233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.514710233
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.4152561099
Short name T8
Test name
Test status
Simulation time 125484894 ps
CPU time 5.42 seconds
Started Mar 09 04:55:23 PM PST 24
Finished Mar 09 04:55:29 PM PST 24
Peak memory 214604 kb
Host smart-f7ed7ede-c67d-4d6a-80db-9997d973a0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152561099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4152561099
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.4263808851
Short name T17
Test name
Test status
Simulation time 319023676 ps
CPU time 1.15 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:53:59 PM PST 24
Peak memory 206040 kb
Host smart-990c0624-db50-47ce-acf1-28fcbd7909a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263808851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.4263808851
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2804503953
Short name T150
Test name
Test status
Simulation time 427300816 ps
CPU time 9.33 seconds
Started Mar 09 02:03:53 PM PST 24
Finished Mar 09 02:04:02 PM PST 24
Peak memory 213572 kb
Host smart-0fc78cf0-76a3-4af3-95c1-00caf189355b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804503953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2804503953
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.4174318266
Short name T222
Test name
Test status
Simulation time 6475575730 ps
CPU time 45.34 seconds
Started Mar 09 04:54:13 PM PST 24
Finished Mar 09 04:54:59 PM PST 24
Peak memory 222460 kb
Host smart-684548c6-bda7-41de-81aa-4b8ab6611b03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174318266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.4174318266
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1524740155
Short name T315
Test name
Test status
Simulation time 290161595 ps
CPU time 15.96 seconds
Started Mar 09 04:54:15 PM PST 24
Finished Mar 09 04:54:31 PM PST 24
Peak memory 214868 kb
Host smart-e56aa430-2074-430d-b2ce-ad6455d1028c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1524740155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1524740155
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1677478857
Short name T95
Test name
Test status
Simulation time 501666719 ps
CPU time 5.87 seconds
Started Mar 09 04:54:46 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 218932 kb
Host smart-93803189-639e-4dc4-9d71-95ec388f3224
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677478857 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1677478857
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3137964014
Short name T247
Test name
Test status
Simulation time 4691832214 ps
CPU time 125.19 seconds
Started Mar 09 04:54:06 PM PST 24
Finished Mar 09 04:56:11 PM PST 24
Peak memory 215892 kb
Host smart-13f08e92-36f6-48d9-be46-61d2f45d831b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3137964014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3137964014
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1272103082
Short name T56
Test name
Test status
Simulation time 5743369144 ps
CPU time 44.19 seconds
Started Mar 09 04:54:24 PM PST 24
Finished Mar 09 04:55:09 PM PST 24
Peak memory 215616 kb
Host smart-24de7644-a5a4-4dc1-abc0-b21912796b35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272103082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1272103082
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1175887055
Short name T33
Test name
Test status
Simulation time 56247890 ps
CPU time 3.27 seconds
Started Mar 09 04:54:30 PM PST 24
Finished Mar 09 04:54:34 PM PST 24
Peak memory 208936 kb
Host smart-1e04029b-0ee4-48ca-81e6-a96407a723f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175887055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1175887055
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.4167396520
Short name T196
Test name
Test status
Simulation time 863110781 ps
CPU time 25 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:33 PM PST 24
Peak memory 219748 kb
Host smart-6af2da5e-3617-42dc-a5bd-fb224e7d9cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167396520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.4167396520
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2232638256
Short name T139
Test name
Test status
Simulation time 289479377 ps
CPU time 6.54 seconds
Started Mar 09 04:53:49 PM PST 24
Finished Mar 09 04:53:56 PM PST 24
Peak memory 218120 kb
Host smart-a29b5e2a-1783-420c-bdb2-0c60a13aea85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232638256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2232638256
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2262457147
Short name T864
Test name
Test status
Simulation time 2269089710 ps
CPU time 43.16 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:41 PM PST 24
Peak memory 216284 kb
Host smart-e568e5e2-455b-4393-87c0-49f473d193b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262457147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2262457147
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2941798854
Short name T152
Test name
Test status
Simulation time 1091198646 ps
CPU time 5.61 seconds
Started Mar 09 02:03:53 PM PST 24
Finished Mar 09 02:03:58 PM PST 24
Peak memory 208908 kb
Host smart-52f5a1fd-2719-4d35-a307-9e113af9a637
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941798854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2941798854
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2398348177
Short name T282
Test name
Test status
Simulation time 47830007 ps
CPU time 3.32 seconds
Started Mar 09 04:54:59 PM PST 24
Finished Mar 09 04:55:03 PM PST 24
Peak memory 222336 kb
Host smart-9daae31d-3519-4357-aea4-5e441d48d1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398348177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2398348177
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.757430117
Short name T147
Test name
Test status
Simulation time 1067544087 ps
CPU time 9.32 seconds
Started Mar 09 02:03:41 PM PST 24
Finished Mar 09 02:03:50 PM PST 24
Peak memory 209076 kb
Host smart-98fc8276-0db7-421a-81b0-00f8715c228d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757430117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
757430117
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2341603548
Short name T2
Test name
Test status
Simulation time 235551072 ps
CPU time 5.56 seconds
Started Mar 09 04:55:19 PM PST 24
Finished Mar 09 04:55:25 PM PST 24
Peak memory 219084 kb
Host smart-f3fa0361-7ef6-491b-9547-66bb88a6dceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341603548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2341603548
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.4011882321
Short name T137
Test name
Test status
Simulation time 1243947833 ps
CPU time 38.23 seconds
Started Mar 09 04:55:11 PM PST 24
Finished Mar 09 04:55:49 PM PST 24
Peak memory 221804 kb
Host smart-f22d6714-46c3-44e5-8842-15d4484d7638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011882321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.4011882321
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.627937025
Short name T286
Test name
Test status
Simulation time 985799766 ps
CPU time 26.07 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:33 PM PST 24
Peak memory 209800 kb
Host smart-4565643b-a8a5-46d5-94d2-98cd9d5c4dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627937025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.627937025
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2990465994
Short name T326
Test name
Test status
Simulation time 87155056 ps
CPU time 4.74 seconds
Started Mar 09 04:54:59 PM PST 24
Finished Mar 09 04:55:04 PM PST 24
Peak memory 214332 kb
Host smart-05cdfbc1-2915-4981-8b15-afe6fd756242
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2990465994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2990465994
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1867073856
Short name T365
Test name
Test status
Simulation time 59306063 ps
CPU time 3.28 seconds
Started Mar 09 04:54:59 PM PST 24
Finished Mar 09 04:55:02 PM PST 24
Peak memory 208768 kb
Host smart-eae71f7b-64fa-42d5-90e6-c620f00185f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867073856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1867073856
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3998936671
Short name T312
Test name
Test status
Simulation time 239775935 ps
CPU time 4.41 seconds
Started Mar 09 04:53:48 PM PST 24
Finished Mar 09 04:53:53 PM PST 24
Peak memory 215492 kb
Host smart-368c7aac-f895-4f83-b49c-f244861c3575
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3998936671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3998936671
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3329197766
Short name T138
Test name
Test status
Simulation time 65260889 ps
CPU time 3.64 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 217688 kb
Host smart-e1d9de43-f536-4631-9a33-80b729cc4c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329197766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3329197766
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2325258505
Short name T407
Test name
Test status
Simulation time 56740291 ps
CPU time 3.03 seconds
Started Mar 09 04:53:46 PM PST 24
Finished Mar 09 04:53:50 PM PST 24
Peak memory 214316 kb
Host smart-3e56147e-f886-41ad-9ccf-b63f77dd373c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325258505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2325258505
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4135609958
Short name T862
Test name
Test status
Simulation time 126844621 ps
CPU time 5.34 seconds
Started Mar 09 04:54:10 PM PST 24
Finished Mar 09 04:54:15 PM PST 24
Peak memory 214404 kb
Host smart-1c087987-4188-4017-8ae6-5ca894ecc081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135609958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4135609958
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1643888535
Short name T405
Test name
Test status
Simulation time 1404771709 ps
CPU time 16.57 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:55:03 PM PST 24
Peak memory 214832 kb
Host smart-27b3aaca-496b-47ba-be3b-b3e3dcaf661b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643888535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1643888535
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1621018552
Short name T73
Test name
Test status
Simulation time 1224860326 ps
CPU time 16.02 seconds
Started Mar 09 04:55:13 PM PST 24
Finished Mar 09 04:55:29 PM PST 24
Peak memory 216172 kb
Host smart-4d80f9bc-cd5a-4f6d-8112-182a36225c7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621018552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1621018552
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3666160605
Short name T146
Test name
Test status
Simulation time 1166206439 ps
CPU time 11.13 seconds
Started Mar 09 04:54:25 PM PST 24
Finished Mar 09 04:54:37 PM PST 24
Peak memory 210776 kb
Host smart-e5a909a4-6331-4110-8630-15587a726483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666160605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3666160605
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1435664384
Short name T143
Test name
Test status
Simulation time 912999179 ps
CPU time 11.52 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:55:01 PM PST 24
Peak memory 217252 kb
Host smart-fb8223be-5c24-4c7f-b00c-30e433b4fc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435664384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1435664384
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1016328750
Short name T135
Test name
Test status
Simulation time 120119706 ps
CPU time 5.18 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:54:54 PM PST 24
Peak memory 218284 kb
Host smart-696088f8-b956-4125-9347-7eddf841987a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016328750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1016328750
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2181344628
Short name T141
Test name
Test status
Simulation time 292756171 ps
CPU time 5.06 seconds
Started Mar 09 04:53:11 PM PST 24
Finished Mar 09 04:53:16 PM PST 24
Peak memory 217568 kb
Host smart-6973dace-87c6-4b95-a5e6-4630d57e2a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181344628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2181344628
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2367939037
Short name T140
Test name
Test status
Simulation time 246591448 ps
CPU time 3.61 seconds
Started Mar 09 04:53:21 PM PST 24
Finished Mar 09 04:53:24 PM PST 24
Peak memory 222588 kb
Host smart-bf97bf41-0269-4f1b-a1fe-fb0417982be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367939037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2367939037
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.4164663310
Short name T28
Test name
Test status
Simulation time 164318225 ps
CPU time 2.41 seconds
Started Mar 09 04:54:17 PM PST 24
Finished Mar 09 04:54:20 PM PST 24
Peak memory 217872 kb
Host smart-f8d32edd-c36b-4808-8a95-ade0b7f7c349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164663310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.4164663310
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.837689302
Short name T54
Test name
Test status
Simulation time 54248042 ps
CPU time 2.75 seconds
Started Mar 09 04:54:08 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 210188 kb
Host smart-be45aa28-cf46-4e90-b8ca-75397179c41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837689302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.837689302
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.305551654
Short name T597
Test name
Test status
Simulation time 332640725 ps
CPU time 3.44 seconds
Started Mar 09 04:53:43 PM PST 24
Finished Mar 09 04:53:47 PM PST 24
Peak memory 206840 kb
Host smart-a54a0138-eb31-4e68-aeaa-448e60ffc07c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305551654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.305551654
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.212540908
Short name T238
Test name
Test status
Simulation time 119874539 ps
CPU time 5.85 seconds
Started Mar 09 04:54:27 PM PST 24
Finished Mar 09 04:54:34 PM PST 24
Peak memory 214276 kb
Host smart-46763c3d-a5a2-4c58-a476-d213442efaa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212540908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.212540908
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.3623508215
Short name T264
Test name
Test status
Simulation time 13359804597 ps
CPU time 40.33 seconds
Started Mar 09 04:54:05 PM PST 24
Finished Mar 09 04:54:45 PM PST 24
Peak memory 222500 kb
Host smart-afc09853-845d-4426-8292-1a5961e9fdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623508215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.3623508215
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2991209882
Short name T1035
Test name
Test status
Simulation time 3929909060 ps
CPU time 25.73 seconds
Started Mar 09 04:54:26 PM PST 24
Finished Mar 09 04:54:53 PM PST 24
Peak memory 216644 kb
Host smart-2763dc1d-e8d6-404a-8d74-2f14500e9ba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991209882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2991209882
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.352605275
Short name T328
Test name
Test status
Simulation time 190998629 ps
CPU time 3.42 seconds
Started Mar 09 04:54:36 PM PST 24
Finished Mar 09 04:54:39 PM PST 24
Peak memory 214288 kb
Host smart-02111179-9646-401c-ac37-77015035e3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352605275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.352605275
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.628404898
Short name T188
Test name
Test status
Simulation time 876853306 ps
CPU time 7.65 seconds
Started Mar 09 04:54:45 PM PST 24
Finished Mar 09 04:54:53 PM PST 24
Peak memory 214224 kb
Host smart-d56fb0af-7609-4ae1-8a4d-b25adc9af454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628404898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.628404898
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2961464718
Short name T214
Test name
Test status
Simulation time 1328107364 ps
CPU time 53.35 seconds
Started Mar 09 04:54:54 PM PST 24
Finished Mar 09 04:55:53 PM PST 24
Peak memory 222480 kb
Host smart-0f3f1122-655b-480d-b9f6-e7c5622e5d83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961464718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2961464718
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.533032963
Short name T229
Test name
Test status
Simulation time 1160269544 ps
CPU time 15.82 seconds
Started Mar 09 04:55:21 PM PST 24
Finished Mar 09 04:55:37 PM PST 24
Peak memory 214296 kb
Host smart-6e397398-3271-4805-b274-203d0a0c1482
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=533032963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.533032963
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1815893025
Short name T350
Test name
Test status
Simulation time 81875339 ps
CPU time 4.86 seconds
Started Mar 09 04:55:14 PM PST 24
Finished Mar 09 04:55:20 PM PST 24
Peak memory 215312 kb
Host smart-5a7a25ca-9d49-4172-81f5-b27180824e58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1815893025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1815893025
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.714164835
Short name T155
Test name
Test status
Simulation time 584589060 ps
CPU time 17.25 seconds
Started Mar 09 02:04:00 PM PST 24
Finished Mar 09 02:04:17 PM PST 24
Peak memory 208912 kb
Host smart-6190e5ce-3bde-4a8f-a3bd-5abfd01619ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714164835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.714164835
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.288161535
Short name T159
Test name
Test status
Simulation time 162714226 ps
CPU time 3.6 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:46 PM PST 24
Peak memory 213724 kb
Host smart-edd69fdb-631a-4503-bd5f-d6473b3bad75
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288161535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
288161535
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.214279418
Short name T154
Test name
Test status
Simulation time 394112307 ps
CPU time 3.8 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 210680 kb
Host smart-02a1262f-f2a8-4fcb-9f5a-541f61ae8755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214279418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.214279418
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.560539963
Short name T136
Test name
Test status
Simulation time 204218186 ps
CPU time 6.93 seconds
Started Mar 09 04:54:04 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 216576 kb
Host smart-218195c8-338c-4cac-a092-c09b3b60367d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560539963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.560539963
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2923083261
Short name T145
Test name
Test status
Simulation time 134958966 ps
CPU time 3.66 seconds
Started Mar 09 04:54:13 PM PST 24
Finished Mar 09 04:54:17 PM PST 24
Peak memory 222676 kb
Host smart-6ffc8c61-9b86-48ab-a9dc-360c8f04bf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923083261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2923083261
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.4109490243
Short name T337
Test name
Test status
Simulation time 3476776949 ps
CPU time 9.26 seconds
Started Mar 09 04:53:10 PM PST 24
Finished Mar 09 04:53:19 PM PST 24
Peak memory 208872 kb
Host smart-3ab0b413-afc1-4d16-827d-4e90ebf998e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109490243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.4109490243
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_random.1520870046
Short name T124
Test name
Test status
Simulation time 13210188106 ps
CPU time 54.64 seconds
Started Mar 09 04:53:40 PM PST 24
Finished Mar 09 04:54:35 PM PST 24
Peak memory 209528 kb
Host smart-806cc402-4465-4b28-9c52-a2bb77763238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520870046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1520870046
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.4021304547
Short name T241
Test name
Test status
Simulation time 1809060062 ps
CPU time 7.36 seconds
Started Mar 09 04:53:26 PM PST 24
Finished Mar 09 04:53:33 PM PST 24
Peak memory 215316 kb
Host smart-7cb1a45c-4854-4651-9921-2c04b416340d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4021304547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.4021304547
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3722403569
Short name T347
Test name
Test status
Simulation time 385923710 ps
CPU time 4.24 seconds
Started Mar 09 04:54:01 PM PST 24
Finished Mar 09 04:54:06 PM PST 24
Peak memory 214276 kb
Host smart-6566755e-804e-49fb-9988-5941af02f041
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3722403569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3722403569
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1560565641
Short name T20
Test name
Test status
Simulation time 882606342 ps
CPU time 6.83 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 219332 kb
Host smart-52188711-4dc1-4aaa-ac24-d2a1b517c99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560565641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1560565641
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3959446369
Short name T55
Test name
Test status
Simulation time 202107914 ps
CPU time 3.07 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 219864 kb
Host smart-81cf84ee-9115-43c4-8c9b-32e3b5e15258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959446369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3959446369
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2243910833
Short name T96
Test name
Test status
Simulation time 905838872 ps
CPU time 7 seconds
Started Mar 09 04:54:04 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 222912 kb
Host smart-5ef8a4df-4d92-4ed5-8e55-714065b81bab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243910833 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2243910833
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3864484549
Short name T711
Test name
Test status
Simulation time 341086901 ps
CPU time 4.47 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 206912 kb
Host smart-cc97ed6a-3b81-4981-bbd7-79c1a7f69bb2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864484549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3864484549
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1802026906
Short name T307
Test name
Test status
Simulation time 323847515 ps
CPU time 8.96 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:05 PM PST 24
Peak memory 208040 kb
Host smart-23a4fcc8-9c41-4ab5-a2cc-8c8b121b2355
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802026906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1802026906
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1268191006
Short name T961
Test name
Test status
Simulation time 199070305 ps
CPU time 5.72 seconds
Started Mar 09 04:53:59 PM PST 24
Finished Mar 09 04:54:05 PM PST 24
Peak memory 214288 kb
Host smart-49f5f5db-38f2-4794-b915-7b825f4f7896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268191006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1268191006
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1001142603
Short name T210
Test name
Test status
Simulation time 844203410 ps
CPU time 3.24 seconds
Started Mar 09 04:54:05 PM PST 24
Finished Mar 09 04:54:08 PM PST 24
Peak memory 220272 kb
Host smart-9b78597e-c319-4672-8012-24c99f7b5fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001142603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1001142603
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.3040961482
Short name T201
Test name
Test status
Simulation time 390594208 ps
CPU time 14.99 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:12 PM PST 24
Peak memory 222684 kb
Host smart-2d4e2bee-dad2-4745-8fce-814018c29db0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040961482 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.3040961482
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3869829772
Short name T366
Test name
Test status
Simulation time 1104995425 ps
CPU time 20.49 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:17 PM PST 24
Peak memory 220272 kb
Host smart-febdb950-40ad-432b-b587-7f5db6cfeabb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869829772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3869829772
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1212867800
Short name T204
Test name
Test status
Simulation time 566405232 ps
CPU time 4.73 seconds
Started Mar 09 04:53:54 PM PST 24
Finished Mar 09 04:53:59 PM PST 24
Peak memory 214428 kb
Host smart-211c88fb-2ee8-47ba-bffe-6c02ae278cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212867800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1212867800
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.962740859
Short name T207
Test name
Test status
Simulation time 1026916924 ps
CPU time 13.47 seconds
Started Mar 09 04:54:08 PM PST 24
Finished Mar 09 04:54:22 PM PST 24
Peak memory 222708 kb
Host smart-0bba14e4-4d31-4307-9708-ded834142297
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962740859 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.962740859
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1223185486
Short name T375
Test name
Test status
Simulation time 177231927 ps
CPU time 9.19 seconds
Started Mar 09 04:54:30 PM PST 24
Finished Mar 09 04:54:40 PM PST 24
Peak memory 214336 kb
Host smart-3b246513-c8ad-45a3-b419-75ee9ee524a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1223185486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1223185486
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.26514156
Short name T200
Test name
Test status
Simulation time 1049946266 ps
CPU time 14.66 seconds
Started Mar 09 04:54:34 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 214336 kb
Host smart-1b6f397b-6512-47eb-8c9f-2800fea2df79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26514156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.26514156
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1041010254
Short name T295
Test name
Test status
Simulation time 124111343 ps
CPU time 4.2 seconds
Started Mar 09 04:54:39 PM PST 24
Finished Mar 09 04:54:43 PM PST 24
Peak memory 209696 kb
Host smart-2fdd8f1f-2b01-4f07-8a86-913a15a40983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041010254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1041010254
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1667075844
Short name T230
Test name
Test status
Simulation time 37045805 ps
CPU time 2.55 seconds
Started Mar 09 04:54:51 PM PST 24
Finished Mar 09 04:54:54 PM PST 24
Peak memory 214284 kb
Host smart-ac65ccd7-1b97-49e1-a686-2cd1c8015867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1667075844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1667075844
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.605103654
Short name T300
Test name
Test status
Simulation time 217708368 ps
CPU time 8.03 seconds
Started Mar 09 04:54:32 PM PST 24
Finished Mar 09 04:54:41 PM PST 24
Peak memory 208120 kb
Host smart-13da50a8-85ef-4c6a-8f6a-55cda1b75f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605103654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.605103654
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3448118
Short name T202
Test name
Test status
Simulation time 1804611964 ps
CPU time 43.59 seconds
Started Mar 09 04:54:57 PM PST 24
Finished Mar 09 04:55:46 PM PST 24
Peak memory 221768 kb
Host smart-1b7ad8a2-769e-4b42-9d71-d9f635642fb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3448118
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.56679853
Short name T322
Test name
Test status
Simulation time 296502052 ps
CPU time 11.72 seconds
Started Mar 09 04:54:51 PM PST 24
Finished Mar 09 04:55:03 PM PST 24
Peak memory 214272 kb
Host smart-37402acc-bd54-4506-b82d-cf206f6808dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56679853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.56679853
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_random.3231607268
Short name T291
Test name
Test status
Simulation time 357825305 ps
CPU time 4.73 seconds
Started Mar 09 04:55:19 PM PST 24
Finished Mar 09 04:55:24 PM PST 24
Peak memory 214368 kb
Host smart-a6de0712-1f4e-4f75-8d1e-bea2b741f04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231607268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3231607268
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3789720897
Short name T338
Test name
Test status
Simulation time 127415528 ps
CPU time 5.49 seconds
Started Mar 09 04:55:30 PM PST 24
Finished Mar 09 04:55:37 PM PST 24
Peak memory 222380 kb
Host smart-3917d442-3e75-4e75-a241-139cb4f8c9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789720897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3789720897
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2355210813
Short name T7
Test name
Test status
Simulation time 451718521 ps
CPU time 5.4 seconds
Started Mar 09 04:53:33 PM PST 24
Finished Mar 09 04:53:39 PM PST 24
Peak memory 210040 kb
Host smart-245338d5-9b90-49a8-a293-84cc8fda24a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355210813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2355210813
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.386354497
Short name T494
Test name
Test status
Simulation time 68856449 ps
CPU time 4.84 seconds
Started Mar 09 02:03:45 PM PST 24
Finished Mar 09 02:03:50 PM PST 24
Peak memory 205304 kb
Host smart-bc6ab65c-fa55-4616-8f0b-eea011575c94
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386354497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.386354497
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2936302174
Short name T421
Test name
Test status
Simulation time 907827217 ps
CPU time 13.14 seconds
Started Mar 09 02:03:32 PM PST 24
Finished Mar 09 02:03:45 PM PST 24
Peak memory 205200 kb
Host smart-8e3cd8aa-e3d2-41fe-9702-a3c3eef8253b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936302174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
936302174
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1094783218
Short name T548
Test name
Test status
Simulation time 54257073 ps
CPU time 1.19 seconds
Started Mar 09 02:03:39 PM PST 24
Finished Mar 09 02:03:41 PM PST 24
Peak memory 205240 kb
Host smart-fb5d5aed-cc17-40cb-8aee-dfeae4264b97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094783218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
094783218
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.869932906
Short name T171
Test name
Test status
Simulation time 123590392 ps
CPU time 1.22 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:44 PM PST 24
Peak memory 205480 kb
Host smart-660044d4-4517-4061-9e6a-000e93df6c66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869932906 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.869932906
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2277048039
Short name T466
Test name
Test status
Simulation time 96490239 ps
CPU time 1.44 seconds
Started Mar 09 02:03:32 PM PST 24
Finished Mar 09 02:03:33 PM PST 24
Peak memory 205300 kb
Host smart-28c704f9-7ce5-4850-90b7-852272410cac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277048039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2277048039
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2717339114
Short name T502
Test name
Test status
Simulation time 28027091 ps
CPU time 0.82 seconds
Started Mar 09 02:03:41 PM PST 24
Finished Mar 09 02:03:42 PM PST 24
Peak memory 205196 kb
Host smart-950348d9-be0f-4ddc-98a9-f4d22d6031cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717339114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2717339114
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.194121439
Short name T450
Test name
Test status
Simulation time 81056194 ps
CPU time 1.57 seconds
Started Mar 09 02:03:41 PM PST 24
Finished Mar 09 02:03:43 PM PST 24
Peak memory 205348 kb
Host smart-fc23fc31-fa4b-4ce0-ad1c-5e22adef75a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194121439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.194121439
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.329801706
Short name T164
Test name
Test status
Simulation time 290791756 ps
CPU time 5.87 seconds
Started Mar 09 02:03:38 PM PST 24
Finished Mar 09 02:03:44 PM PST 24
Peak memory 218468 kb
Host smart-693a677f-24da-494f-992c-5d0b2c91fcb1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329801706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.329801706
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1171205454
Short name T444
Test name
Test status
Simulation time 89590274 ps
CPU time 4.03 seconds
Started Mar 09 02:03:36 PM PST 24
Finished Mar 09 02:03:40 PM PST 24
Peak memory 213888 kb
Host smart-9258dc00-815a-46f4-90f1-8c38ff73fc1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171205454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1171205454
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3089871695
Short name T499
Test name
Test status
Simulation time 134928197 ps
CPU time 1.29 seconds
Started Mar 09 02:03:33 PM PST 24
Finished Mar 09 02:03:35 PM PST 24
Peak memory 213572 kb
Host smart-dcfd1456-e7e5-4c85-8dc4-50f8c4e866fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089871695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3089871695
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.279102241
Short name T160
Test name
Test status
Simulation time 150317352 ps
CPU time 5.29 seconds
Started Mar 09 02:03:39 PM PST 24
Finished Mar 09 02:03:45 PM PST 24
Peak memory 208688 kb
Host smart-cae2acee-3c9d-41af-8154-8979723822d3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279102241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
279102241
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.4211518500
Short name T168
Test name
Test status
Simulation time 504647891 ps
CPU time 6.31 seconds
Started Mar 09 02:03:31 PM PST 24
Finished Mar 09 02:03:38 PM PST 24
Peak memory 205136 kb
Host smart-b85f4813-b728-4a34-8bf0-7992bcd597d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211518500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.4
211518500
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3502282936
Short name T493
Test name
Test status
Simulation time 160709265 ps
CPU time 1.25 seconds
Started Mar 09 02:03:40 PM PST 24
Finished Mar 09 02:03:41 PM PST 24
Peak memory 205232 kb
Host smart-a84a8f0c-86b5-4eb7-bd81-a2c232d6d15b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502282936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
502282936
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3242367022
Short name T459
Test name
Test status
Simulation time 27077739 ps
CPU time 1.84 seconds
Started Mar 09 02:03:38 PM PST 24
Finished Mar 09 02:03:40 PM PST 24
Peak memory 213604 kb
Host smart-37881480-7787-40aa-bc61-7b27f419fe4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242367022 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3242367022
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2583997510
Short name T458
Test name
Test status
Simulation time 99494001 ps
CPU time 0.72 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:43 PM PST 24
Peak memory 205088 kb
Host smart-4628f45d-1d8c-432f-86b6-7f4b40117137
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583997510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2583997510
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1176302781
Short name T134
Test name
Test status
Simulation time 197173279 ps
CPU time 1.61 seconds
Started Mar 09 02:03:35 PM PST 24
Finished Mar 09 02:03:37 PM PST 24
Peak memory 205348 kb
Host smart-62b5be83-d45a-4c31-8df0-16ca17b03eb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176302781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1176302781
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4035306551
Short name T165
Test name
Test status
Simulation time 772255457 ps
CPU time 5.71 seconds
Started Mar 09 02:03:31 PM PST 24
Finished Mar 09 02:03:37 PM PST 24
Peak memory 213808 kb
Host smart-a67d4a83-42e5-4f26-96d0-aa88e3869cd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035306551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.4035306551
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1501924983
Short name T456
Test name
Test status
Simulation time 131119957 ps
CPU time 6.33 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:48 PM PST 24
Peak memory 213784 kb
Host smart-c2e83d24-bdd3-4d89-8221-dd22028829c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501924983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1501924983
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2088058150
Short name T550
Test name
Test status
Simulation time 615661377 ps
CPU time 2.31 seconds
Started Mar 09 02:03:38 PM PST 24
Finished Mar 09 02:03:41 PM PST 24
Peak memory 215568 kb
Host smart-f613b219-a9d9-4b16-8a96-a7dd5a917a6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088058150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2088058150
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3647746011
Short name T506
Test name
Test status
Simulation time 42610793 ps
CPU time 1.46 seconds
Started Mar 09 02:03:47 PM PST 24
Finished Mar 09 02:03:49 PM PST 24
Peak memory 213512 kb
Host smart-d68f1b20-ac17-4da2-b807-3a3e4b79552a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647746011 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3647746011
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2614949980
Short name T129
Test name
Test status
Simulation time 31074881 ps
CPU time 0.95 seconds
Started Mar 09 02:03:48 PM PST 24
Finished Mar 09 02:03:49 PM PST 24
Peak memory 205144 kb
Host smart-9062e258-ece6-4d9b-a55c-990af7161757
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614949980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2614949980
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1570941903
Short name T537
Test name
Test status
Simulation time 15491530 ps
CPU time 0.75 seconds
Started Mar 09 02:03:47 PM PST 24
Finished Mar 09 02:03:48 PM PST 24
Peak memory 205080 kb
Host smart-7f5f4230-1247-44f1-b500-b8182d119d2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570941903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1570941903
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1294309576
Short name T539
Test name
Test status
Simulation time 98856292 ps
CPU time 2.68 seconds
Started Mar 09 02:03:48 PM PST 24
Finished Mar 09 02:03:51 PM PST 24
Peak memory 213836 kb
Host smart-39217f32-6503-4807-a71e-860eafa9f796
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294309576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1294309576
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.532459146
Short name T519
Test name
Test status
Simulation time 406539204 ps
CPU time 9.51 seconds
Started Mar 09 02:03:47 PM PST 24
Finished Mar 09 02:03:57 PM PST 24
Peak memory 213840 kb
Host smart-708e1076-44c7-4511-8b5e-48bda2610863
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532459146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.532459146
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1399842698
Short name T117
Test name
Test status
Simulation time 43665491 ps
CPU time 2.58 seconds
Started Mar 09 02:03:49 PM PST 24
Finished Mar 09 02:03:52 PM PST 24
Peak memory 213596 kb
Host smart-34b17842-3c10-4eb1-89e5-c142fbd6b8d5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399842698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1399842698
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2132530463
Short name T148
Test name
Test status
Simulation time 143650145 ps
CPU time 4.95 seconds
Started Mar 09 02:03:50 PM PST 24
Finished Mar 09 02:03:55 PM PST 24
Peak memory 213568 kb
Host smart-9d182156-a401-40d5-9264-4ab1fa0e3ad4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132530463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2132530463
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3820970005
Short name T470
Test name
Test status
Simulation time 205783601 ps
CPU time 2.12 seconds
Started Mar 09 02:03:48 PM PST 24
Finished Mar 09 02:03:50 PM PST 24
Peak memory 213600 kb
Host smart-0722e086-94be-4f53-ba10-a8aeef4679c4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820970005 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3820970005
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.312357877
Short name T475
Test name
Test status
Simulation time 16905085 ps
CPU time 1.03 seconds
Started Mar 09 02:03:47 PM PST 24
Finished Mar 09 02:03:48 PM PST 24
Peak memory 205224 kb
Host smart-d730171b-f306-4b84-9358-e42b9c7368cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312357877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.312357877
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1750759521
Short name T517
Test name
Test status
Simulation time 59826769 ps
CPU time 0.71 seconds
Started Mar 09 02:03:48 PM PST 24
Finished Mar 09 02:03:49 PM PST 24
Peak memory 205188 kb
Host smart-22820e7e-84ec-43dd-a7e4-98f0d45f3e7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750759521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1750759521
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.502963413
Short name T111
Test name
Test status
Simulation time 119663682 ps
CPU time 4.31 seconds
Started Mar 09 02:03:46 PM PST 24
Finished Mar 09 02:03:50 PM PST 24
Peak memory 213896 kb
Host smart-ea593179-8ba2-463d-886f-3b58335afd3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502963413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.502963413
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2365162044
Short name T110
Test name
Test status
Simulation time 429736087 ps
CPU time 10.61 seconds
Started Mar 09 02:03:49 PM PST 24
Finished Mar 09 02:04:00 PM PST 24
Peak memory 219972 kb
Host smart-fea19a9a-ce7d-406f-9202-cbeee65cc85d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365162044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2365162044
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2529703675
Short name T454
Test name
Test status
Simulation time 130279515 ps
CPU time 4.74 seconds
Started Mar 09 02:03:47 PM PST 24
Finished Mar 09 02:03:52 PM PST 24
Peak memory 213672 kb
Host smart-d3e6d0a7-1969-4e32-8f7e-571c4cd1569e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529703675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2529703675
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3541081532
Short name T524
Test name
Test status
Simulation time 78767769 ps
CPU time 1.2 seconds
Started Mar 09 02:03:55 PM PST 24
Finished Mar 09 02:03:56 PM PST 24
Peak memory 213548 kb
Host smart-4f530a71-d357-49d2-ac28-a476d2ae5794
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541081532 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3541081532
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3255989706
Short name T126
Test name
Test status
Simulation time 61941188 ps
CPU time 1.13 seconds
Started Mar 09 02:03:50 PM PST 24
Finished Mar 09 02:03:51 PM PST 24
Peak memory 205184 kb
Host smart-6ceaee97-829e-49cd-8ec6-4af08686f1bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255989706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3255989706
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.4212807729
Short name T534
Test name
Test status
Simulation time 13094558 ps
CPU time 0.9 seconds
Started Mar 09 02:03:50 PM PST 24
Finished Mar 09 02:03:51 PM PST 24
Peak memory 205264 kb
Host smart-2d78c4fd-3215-4ead-b338-456489884682
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212807729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.4212807729
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.575622759
Short name T166
Test name
Test status
Simulation time 188814692 ps
CPU time 2.96 seconds
Started Mar 09 02:03:50 PM PST 24
Finished Mar 09 02:03:53 PM PST 24
Peak memory 221984 kb
Host smart-e9b21b16-8681-45f5-81bd-d242a742e227
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575622759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.575622759
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3266594246
Short name T522
Test name
Test status
Simulation time 177910021 ps
CPU time 4.33 seconds
Started Mar 09 02:03:47 PM PST 24
Finished Mar 09 02:03:51 PM PST 24
Peak memory 213840 kb
Host smart-6ddb9b7a-f0fa-4a86-8236-b7207b923bd3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266594246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3266594246
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2219682832
Short name T163
Test name
Test status
Simulation time 32039327 ps
CPU time 2.51 seconds
Started Mar 09 02:03:50 PM PST 24
Finished Mar 09 02:03:53 PM PST 24
Peak memory 215640 kb
Host smart-ac022554-4bf4-47b8-a554-cf021f0d836d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219682832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2219682832
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2395564740
Short name T530
Test name
Test status
Simulation time 13173296 ps
CPU time 1.06 seconds
Started Mar 09 02:03:56 PM PST 24
Finished Mar 09 02:03:58 PM PST 24
Peak memory 205320 kb
Host smart-2562eac6-008d-4604-9d50-0a109d397c2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395564740 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2395564740
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1718156814
Short name T130
Test name
Test status
Simulation time 25729687 ps
CPU time 1.22 seconds
Started Mar 09 02:03:55 PM PST 24
Finished Mar 09 02:03:57 PM PST 24
Peak memory 205248 kb
Host smart-56b7cb39-c066-4f0b-a9f2-eacfc50bee32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718156814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1718156814
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.529238536
Short name T455
Test name
Test status
Simulation time 10719725 ps
CPU time 0.75 seconds
Started Mar 09 02:03:56 PM PST 24
Finished Mar 09 02:03:57 PM PST 24
Peak memory 205124 kb
Host smart-fb5c0325-e109-46ed-86ab-7bd60150fd3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529238536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.529238536
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2126971256
Short name T469
Test name
Test status
Simulation time 97802172 ps
CPU time 1.66 seconds
Started Mar 09 02:03:52 PM PST 24
Finished Mar 09 02:03:53 PM PST 24
Peak memory 205392 kb
Host smart-fa3c30de-a328-4d4e-9e29-1c562138a755
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126971256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2126971256
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4072898148
Short name T437
Test name
Test status
Simulation time 8392387544 ps
CPU time 49.61 seconds
Started Mar 09 02:03:54 PM PST 24
Finished Mar 09 02:04:44 PM PST 24
Peak memory 230164 kb
Host smart-b5596ff5-3b44-49c1-bd83-f9f0e72f4c2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072898148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.4072898148
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3167639194
Short name T500
Test name
Test status
Simulation time 857078580 ps
CPU time 6.27 seconds
Started Mar 09 02:03:54 PM PST 24
Finished Mar 09 02:04:00 PM PST 24
Peak memory 213788 kb
Host smart-077f45c2-68a0-497c-8033-90df2b151606
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167639194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3167639194
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2053917315
Short name T544
Test name
Test status
Simulation time 58229164 ps
CPU time 1.82 seconds
Started Mar 09 02:03:53 PM PST 24
Finished Mar 09 02:03:55 PM PST 24
Peak memory 214952 kb
Host smart-39a21ddb-fedc-4786-82f9-77419cf2850c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053917315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2053917315
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1824644051
Short name T551
Test name
Test status
Simulation time 19214387 ps
CPU time 1.37 seconds
Started Mar 09 02:03:55 PM PST 24
Finished Mar 09 02:03:56 PM PST 24
Peak memory 213604 kb
Host smart-4d1bb0a2-f1ea-4998-86ba-e5b8e3ae50ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824644051 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1824644051
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.4100735896
Short name T457
Test name
Test status
Simulation time 59504425 ps
CPU time 1.27 seconds
Started Mar 09 02:03:52 PM PST 24
Finished Mar 09 02:03:53 PM PST 24
Peak memory 205116 kb
Host smart-5c3fb1d3-e08e-4a73-a41d-3cdc55c660e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100735896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.4100735896
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.16361057
Short name T553
Test name
Test status
Simulation time 35289391 ps
CPU time 0.79 seconds
Started Mar 09 02:03:52 PM PST 24
Finished Mar 09 02:03:53 PM PST 24
Peak memory 205180 kb
Host smart-c22d37f7-dba2-444d-8371-f520e4177c0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16361057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.16361057
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3357794743
Short name T486
Test name
Test status
Simulation time 211041708 ps
CPU time 6.3 seconds
Started Mar 09 02:03:56 PM PST 24
Finished Mar 09 02:04:03 PM PST 24
Peak memory 213784 kb
Host smart-572ee340-cbbc-4c14-9490-f90684df0c32
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357794743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3357794743
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3145839046
Short name T540
Test name
Test status
Simulation time 346956382 ps
CPU time 7.68 seconds
Started Mar 09 02:03:52 PM PST 24
Finished Mar 09 02:04:00 PM PST 24
Peak memory 219872 kb
Host smart-fede1837-a4a1-45e5-ac89-77abe8ba88f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145839046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3145839046
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2221467800
Short name T525
Test name
Test status
Simulation time 295558225 ps
CPU time 3.14 seconds
Started Mar 09 02:03:56 PM PST 24
Finished Mar 09 02:03:59 PM PST 24
Peak memory 213592 kb
Host smart-f8383ac9-a422-4a1f-b14c-e36fcfdefd4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221467800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2221467800
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.515392107
Short name T445
Test name
Test status
Simulation time 35008371 ps
CPU time 1 seconds
Started Mar 09 02:03:59 PM PST 24
Finished Mar 09 02:04:00 PM PST 24
Peak memory 205184 kb
Host smart-279937eb-381d-4c47-8bc2-a7355fd9cf41
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515392107 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.515392107
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2495130544
Short name T520
Test name
Test status
Simulation time 23933529 ps
CPU time 1.53 seconds
Started Mar 09 02:03:54 PM PST 24
Finished Mar 09 02:03:56 PM PST 24
Peak memory 205280 kb
Host smart-611e6652-ff35-48d9-86b3-d1893a23f331
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495130544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2495130544
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2525253303
Short name T474
Test name
Test status
Simulation time 40637729 ps
CPU time 0.73 seconds
Started Mar 09 02:03:52 PM PST 24
Finished Mar 09 02:03:53 PM PST 24
Peak memory 205104 kb
Host smart-311d653e-74e1-4769-afff-03dfc04fcdcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525253303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2525253303
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2393649212
Short name T462
Test name
Test status
Simulation time 36686972 ps
CPU time 2.03 seconds
Started Mar 09 02:03:50 PM PST 24
Finished Mar 09 02:03:53 PM PST 24
Peak memory 205364 kb
Host smart-6e10778b-6a8c-46f4-85ba-9e46542461c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393649212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2393649212
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1469631141
Short name T429
Test name
Test status
Simulation time 105749167 ps
CPU time 3.21 seconds
Started Mar 09 02:03:55 PM PST 24
Finished Mar 09 02:03:59 PM PST 24
Peak memory 213972 kb
Host smart-bf1434af-842b-4b31-8f88-f16914778b12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469631141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1469631141
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.589974680
Short name T535
Test name
Test status
Simulation time 280874427 ps
CPU time 2.75 seconds
Started Mar 09 02:03:55 PM PST 24
Finished Mar 09 02:03:59 PM PST 24
Peak memory 213488 kb
Host smart-82969434-7d15-4ab9-980d-90ad0fa2c316
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589974680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.589974680
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2887787326
Short name T158
Test name
Test status
Simulation time 207250597 ps
CPU time 7.72 seconds
Started Mar 09 02:03:56 PM PST 24
Finished Mar 09 02:04:04 PM PST 24
Peak memory 209056 kb
Host smart-989c9deb-2d9c-4d3f-9d39-1d8d13fc8fbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887787326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2887787326
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.640816111
Short name T431
Test name
Test status
Simulation time 87154621 ps
CPU time 1.85 seconds
Started Mar 09 02:03:58 PM PST 24
Finished Mar 09 02:04:00 PM PST 24
Peak memory 221644 kb
Host smart-00665b1a-9e91-4149-a38e-fd966945fede
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640816111 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.640816111
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.604722394
Short name T538
Test name
Test status
Simulation time 29237765 ps
CPU time 0.76 seconds
Started Mar 09 02:04:05 PM PST 24
Finished Mar 09 02:04:06 PM PST 24
Peak memory 205152 kb
Host smart-907c7c42-28d4-4b31-9c73-cb6d180583c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604722394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.604722394
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1573783615
Short name T515
Test name
Test status
Simulation time 49834562 ps
CPU time 2.06 seconds
Started Mar 09 02:03:59 PM PST 24
Finished Mar 09 02:04:01 PM PST 24
Peak memory 205376 kb
Host smart-deee598c-2e31-4b61-82ce-4d0261e89c0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573783615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1573783615
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3576984513
Short name T549
Test name
Test status
Simulation time 310668569 ps
CPU time 6.43 seconds
Started Mar 09 02:04:01 PM PST 24
Finished Mar 09 02:04:07 PM PST 24
Peak memory 213836 kb
Host smart-22ef3378-4896-4575-9564-aeb89614500e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576984513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3576984513
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1350315942
Short name T463
Test name
Test status
Simulation time 27778455 ps
CPU time 2.23 seconds
Started Mar 09 02:03:58 PM PST 24
Finished Mar 09 02:04:01 PM PST 24
Peak memory 213552 kb
Host smart-62d2279c-3d8e-4214-93ba-96e7632d487b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350315942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1350315942
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.806522467
Short name T452
Test name
Test status
Simulation time 25612065 ps
CPU time 1.1 seconds
Started Mar 09 02:04:01 PM PST 24
Finished Mar 09 02:04:02 PM PST 24
Peak memory 205312 kb
Host smart-5e09450e-6af6-4161-876c-9a9da75da0c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806522467 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.806522467
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3787209233
Short name T479
Test name
Test status
Simulation time 48330770 ps
CPU time 1.05 seconds
Started Mar 09 02:04:05 PM PST 24
Finished Mar 09 02:04:06 PM PST 24
Peak memory 205140 kb
Host smart-a292a976-c5ff-499e-8ca2-82b8c69f34eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787209233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3787209233
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2815977976
Short name T435
Test name
Test status
Simulation time 14552027 ps
CPU time 0.91 seconds
Started Mar 09 02:04:04 PM PST 24
Finished Mar 09 02:04:06 PM PST 24
Peak memory 205220 kb
Host smart-47e37658-b597-4b13-89dd-16c3987e6efd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815977976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2815977976
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3784203810
Short name T504
Test name
Test status
Simulation time 67921000 ps
CPU time 2.02 seconds
Started Mar 09 02:04:02 PM PST 24
Finished Mar 09 02:04:04 PM PST 24
Peak memory 205336 kb
Host smart-ec231552-d0a3-47c2-90fc-3336ac3850c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784203810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3784203810
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1219196901
Short name T478
Test name
Test status
Simulation time 682764089 ps
CPU time 13.58 seconds
Started Mar 09 02:04:05 PM PST 24
Finished Mar 09 02:04:19 PM PST 24
Peak memory 214192 kb
Host smart-02c3eb59-23a6-4891-871c-501027270061
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219196901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1219196901
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3901396065
Short name T480
Test name
Test status
Simulation time 830223063 ps
CPU time 10.74 seconds
Started Mar 09 02:04:04 PM PST 24
Finished Mar 09 02:04:16 PM PST 24
Peak memory 213732 kb
Host smart-99260f94-5e17-491f-ba79-9b682ea75b09
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901396065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3901396065
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3468120851
Short name T490
Test name
Test status
Simulation time 134196938 ps
CPU time 1.85 seconds
Started Mar 09 02:04:01 PM PST 24
Finished Mar 09 02:04:03 PM PST 24
Peak memory 213584 kb
Host smart-9b7a618f-0626-47f2-b631-fd6243196fa1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468120851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3468120851
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2960065766
Short name T438
Test name
Test status
Simulation time 43510515 ps
CPU time 1.87 seconds
Started Mar 09 02:04:02 PM PST 24
Finished Mar 09 02:04:03 PM PST 24
Peak memory 213668 kb
Host smart-aecd6f21-b604-4ebd-80f0-53190f8a4c73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960065766 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2960065766
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2283357125
Short name T477
Test name
Test status
Simulation time 17475643 ps
CPU time 1.18 seconds
Started Mar 09 02:04:05 PM PST 24
Finished Mar 09 02:04:06 PM PST 24
Peak memory 205212 kb
Host smart-9362a5c1-5f69-426c-9967-7a585f32bf81
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283357125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2283357125
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3598028224
Short name T546
Test name
Test status
Simulation time 34707515 ps
CPU time 0.79 seconds
Started Mar 09 02:04:03 PM PST 24
Finished Mar 09 02:04:03 PM PST 24
Peak memory 205184 kb
Host smart-ef133aed-ba8e-4181-bed1-9ba112ff18ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598028224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3598028224
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1744156051
Short name T127
Test name
Test status
Simulation time 35002141 ps
CPU time 1.8 seconds
Started Mar 09 02:04:01 PM PST 24
Finished Mar 09 02:04:03 PM PST 24
Peak memory 205316 kb
Host smart-663f7bd3-eaff-4096-8f18-ad0c54fb2246
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744156051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1744156051
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3323407723
Short name T505
Test name
Test status
Simulation time 626586256 ps
CPU time 12.15 seconds
Started Mar 09 02:04:01 PM PST 24
Finished Mar 09 02:04:13 PM PST 24
Peak memory 213732 kb
Host smart-5317fde0-aa1a-4113-9591-731462ed968f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323407723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3323407723
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1752024747
Short name T489
Test name
Test status
Simulation time 124469974 ps
CPU time 2.38 seconds
Started Mar 09 02:04:01 PM PST 24
Finished Mar 09 02:04:03 PM PST 24
Peak memory 213656 kb
Host smart-eb27eaea-f899-4b54-be44-efa075a35bb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752024747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1752024747
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3317496436
Short name T161
Test name
Test status
Simulation time 185568205 ps
CPU time 5.25 seconds
Started Mar 09 02:04:03 PM PST 24
Finished Mar 09 02:04:08 PM PST 24
Peak memory 208788 kb
Host smart-a6455f8e-c67f-442e-82b3-b0ca71e87c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317496436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3317496436
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1439261049
Short name T472
Test name
Test status
Simulation time 14641012 ps
CPU time 0.97 seconds
Started Mar 09 02:04:03 PM PST 24
Finished Mar 09 02:04:04 PM PST 24
Peak memory 205316 kb
Host smart-8ee8d452-6114-4adb-b538-d1f8663b4bfd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439261049 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1439261049
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2868818343
Short name T497
Test name
Test status
Simulation time 9458784 ps
CPU time 0.87 seconds
Started Mar 09 02:04:01 PM PST 24
Finished Mar 09 02:04:02 PM PST 24
Peak memory 205088 kb
Host smart-36ac459a-2eaa-4925-afbd-45ed785c9302
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868818343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2868818343
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1002193758
Short name T464
Test name
Test status
Simulation time 15088309 ps
CPU time 0.72 seconds
Started Mar 09 02:04:00 PM PST 24
Finished Mar 09 02:04:01 PM PST 24
Peak memory 205124 kb
Host smart-1fba3c70-c6a2-4ff6-806a-642d4b0e81cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002193758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1002193758
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.482659028
Short name T543
Test name
Test status
Simulation time 60644171 ps
CPU time 1.54 seconds
Started Mar 09 02:04:08 PM PST 24
Finished Mar 09 02:04:10 PM PST 24
Peak memory 205336 kb
Host smart-35f00148-b565-49fd-ab35-a4ef7b1b805a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482659028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.482659028
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2556825240
Short name T167
Test name
Test status
Simulation time 352101119 ps
CPU time 5.4 seconds
Started Mar 09 02:04:02 PM PST 24
Finished Mar 09 02:04:08 PM PST 24
Peak memory 213744 kb
Host smart-1bfbbe74-1d00-4a02-a82b-3ed4bc1a768e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556825240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2556825240
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1906840399
Short name T133
Test name
Test status
Simulation time 275516057 ps
CPU time 2.86 seconds
Started Mar 09 02:04:04 PM PST 24
Finished Mar 09 02:04:08 PM PST 24
Peak memory 213604 kb
Host smart-f233fa5a-11e3-42ee-9937-dc37f6393cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906840399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1906840399
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1955687368
Short name T552
Test name
Test status
Simulation time 104132987 ps
CPU time 4.21 seconds
Started Mar 09 02:04:05 PM PST 24
Finished Mar 09 02:04:09 PM PST 24
Peak memory 208748 kb
Host smart-30dd1bb2-241f-4f1b-94a5-0911f67adf36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955687368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1955687368
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.91961059
Short name T453
Test name
Test status
Simulation time 621710752 ps
CPU time 6.74 seconds
Started Mar 09 02:03:37 PM PST 24
Finished Mar 09 02:03:44 PM PST 24
Peak memory 205380 kb
Host smart-644339c3-462a-4fa1-8720-053b017f460b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91961059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.91961059
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.251700109
Short name T526
Test name
Test status
Simulation time 179144897 ps
CPU time 1.24 seconds
Started Mar 09 02:03:44 PM PST 24
Finished Mar 09 02:03:45 PM PST 24
Peak memory 205344 kb
Host smart-ea768615-f584-47bb-a7da-2f89bdc36d3c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251700109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.251700109
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.676962684
Short name T132
Test name
Test status
Simulation time 16149828 ps
CPU time 0.94 seconds
Started Mar 09 02:03:31 PM PST 24
Finished Mar 09 02:03:32 PM PST 24
Peak memory 205312 kb
Host smart-8c4122ba-e30a-4709-929c-4298e6b59691
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676962684 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.676962684
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1265807084
Short name T482
Test name
Test status
Simulation time 111144194 ps
CPU time 1.48 seconds
Started Mar 09 02:03:35 PM PST 24
Finished Mar 09 02:03:37 PM PST 24
Peak memory 205292 kb
Host smart-404aa2bf-15ee-4011-94a0-e7cb1699c4b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265807084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1265807084
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2355667401
Short name T509
Test name
Test status
Simulation time 9562883 ps
CPU time 0.82 seconds
Started Mar 09 02:03:37 PM PST 24
Finished Mar 09 02:03:38 PM PST 24
Peak memory 205184 kb
Host smart-3ec43226-ae31-452e-add3-e4b74a040067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355667401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2355667401
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3153487071
Short name T447
Test name
Test status
Simulation time 118039824 ps
CPU time 3.94 seconds
Started Mar 09 02:03:33 PM PST 24
Finished Mar 09 02:03:37 PM PST 24
Peak memory 213820 kb
Host smart-0e75056b-ca9e-4bee-accc-46bd49a924e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153487071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3153487071
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.924750921
Short name T118
Test name
Test status
Simulation time 23020325 ps
CPU time 1.35 seconds
Started Mar 09 02:03:38 PM PST 24
Finished Mar 09 02:03:40 PM PST 24
Peak memory 213548 kb
Host smart-8e0f2baf-6ba0-4a6e-a9f9-1d6a72eb90f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924750921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.924750921
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.4278288197
Short name T131
Test name
Test status
Simulation time 108855418 ps
CPU time 3.17 seconds
Started Mar 09 02:03:39 PM PST 24
Finished Mar 09 02:03:43 PM PST 24
Peak memory 209000 kb
Host smart-4b9b82a7-c0cb-4b17-b193-08992b3d84cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278288197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.4278288197
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.4015266066
Short name T471
Test name
Test status
Simulation time 7153384 ps
CPU time 0.79 seconds
Started Mar 09 02:04:04 PM PST 24
Finished Mar 09 02:04:05 PM PST 24
Peak memory 205180 kb
Host smart-6b4fd8c9-e18f-4bd3-8467-bc0ba176ed3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015266066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.4015266066
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1787205823
Short name T430
Test name
Test status
Simulation time 30403364 ps
CPU time 0.84 seconds
Started Mar 09 02:04:06 PM PST 24
Finished Mar 09 02:04:07 PM PST 24
Peak memory 205176 kb
Host smart-fd2fa167-e4c4-4309-9208-64021526b772
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787205823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1787205823
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3258478560
Short name T495
Test name
Test status
Simulation time 21810762 ps
CPU time 0.75 seconds
Started Mar 09 02:04:05 PM PST 24
Finished Mar 09 02:04:07 PM PST 24
Peak memory 205232 kb
Host smart-1219f254-14d4-4e9b-9160-ab0d9fd1f83d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258478560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3258478560
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3090949578
Short name T510
Test name
Test status
Simulation time 21975750 ps
CPU time 0.7 seconds
Started Mar 09 02:04:03 PM PST 24
Finished Mar 09 02:04:03 PM PST 24
Peak memory 205148 kb
Host smart-654fa0bc-65fc-4d82-a65b-d1108338e3f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090949578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3090949578
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1294470332
Short name T441
Test name
Test status
Simulation time 9652873 ps
CPU time 0.85 seconds
Started Mar 09 02:04:05 PM PST 24
Finished Mar 09 02:04:07 PM PST 24
Peak memory 205124 kb
Host smart-85ac8154-34b5-44e3-9669-f81558c9b79c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294470332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1294470332
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.4176637753
Short name T483
Test name
Test status
Simulation time 117601105 ps
CPU time 0.77 seconds
Started Mar 09 02:04:14 PM PST 24
Finished Mar 09 02:04:15 PM PST 24
Peak memory 205192 kb
Host smart-09263ae6-5b7d-4361-955b-fcd40f0af42c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176637753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.4176637753
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.834288314
Short name T507
Test name
Test status
Simulation time 101633913 ps
CPU time 0.84 seconds
Started Mar 09 02:04:04 PM PST 24
Finished Mar 09 02:04:05 PM PST 24
Peak memory 205192 kb
Host smart-4cbe2c59-9394-4d7b-b4ac-f2023f0c70d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834288314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.834288314
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1789075693
Short name T541
Test name
Test status
Simulation time 21076296 ps
CPU time 0.74 seconds
Started Mar 09 02:04:05 PM PST 24
Finished Mar 09 02:04:06 PM PST 24
Peak memory 205232 kb
Host smart-0267ec0a-7fa9-4fb9-8258-4cd2c86ba064
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789075693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1789075693
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3540231825
Short name T516
Test name
Test status
Simulation time 10095401 ps
CPU time 0.72 seconds
Started Mar 09 02:04:03 PM PST 24
Finished Mar 09 02:04:04 PM PST 24
Peak memory 205172 kb
Host smart-718260a8-5c23-45b8-8fa0-7b7e5caae77d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540231825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3540231825
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3151887149
Short name T476
Test name
Test status
Simulation time 18742939 ps
CPU time 0.8 seconds
Started Mar 09 02:04:04 PM PST 24
Finished Mar 09 02:04:05 PM PST 24
Peak memory 205112 kb
Host smart-0aed717f-a36f-430f-b552-d22d329701c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151887149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3151887149
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2314585275
Short name T533
Test name
Test status
Simulation time 135169412 ps
CPU time 4.21 seconds
Started Mar 09 02:03:41 PM PST 24
Finished Mar 09 02:03:45 PM PST 24
Peak memory 205120 kb
Host smart-055e3503-018b-4ac7-b45b-ab1eb59203c1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314585275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
314585275
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1667316448
Short name T424
Test name
Test status
Simulation time 258623187 ps
CPU time 11.76 seconds
Started Mar 09 02:03:41 PM PST 24
Finished Mar 09 02:03:53 PM PST 24
Peak memory 205184 kb
Host smart-c6b1bdf3-d7c6-4728-b337-def5e087177b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667316448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
667316448
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1622729404
Short name T518
Test name
Test status
Simulation time 12651091 ps
CPU time 0.9 seconds
Started Mar 09 02:03:39 PM PST 24
Finished Mar 09 02:03:40 PM PST 24
Peak memory 205084 kb
Host smart-317b30c4-8cf0-41cf-ba70-01e3c9c17594
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622729404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
622729404
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2367681335
Short name T460
Test name
Test status
Simulation time 105592426 ps
CPU time 1.28 seconds
Started Mar 09 02:03:41 PM PST 24
Finished Mar 09 02:03:42 PM PST 24
Peak memory 205404 kb
Host smart-22937775-0cbf-4f4e-95e8-64f13378d311
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367681335 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2367681335
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3125127176
Short name T512
Test name
Test status
Simulation time 24542483 ps
CPU time 1.15 seconds
Started Mar 09 02:03:36 PM PST 24
Finished Mar 09 02:03:38 PM PST 24
Peak memory 205232 kb
Host smart-3359b69c-9415-4f93-a52b-3edd9efbb1b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125127176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3125127176
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3228822975
Short name T491
Test name
Test status
Simulation time 19963411 ps
CPU time 0.99 seconds
Started Mar 09 02:03:32 PM PST 24
Finished Mar 09 02:03:34 PM PST 24
Peak memory 205200 kb
Host smart-426892f6-b706-4dd4-a528-b7d1fce4537c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228822975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3228822975
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.4145645201
Short name T473
Test name
Test status
Simulation time 1218503694 ps
CPU time 21.84 seconds
Started Mar 09 02:03:40 PM PST 24
Finished Mar 09 02:04:02 PM PST 24
Peak memory 213664 kb
Host smart-987bd445-6178-4a07-9c83-22e56fadaab5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145645201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.4145645201
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3555732522
Short name T532
Test name
Test status
Simulation time 206084551 ps
CPU time 2.2 seconds
Started Mar 09 02:03:40 PM PST 24
Finished Mar 09 02:03:42 PM PST 24
Peak memory 216640 kb
Host smart-af5a03a3-8795-435c-bf63-5a790584613d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555732522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3555732522
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.564016339
Short name T529
Test name
Test status
Simulation time 39263953 ps
CPU time 0.72 seconds
Started Mar 09 02:04:02 PM PST 24
Finished Mar 09 02:04:03 PM PST 24
Peak memory 205184 kb
Host smart-aa46918c-6aae-492f-9641-a476e128f837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564016339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.564016339
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.4057255561
Short name T508
Test name
Test status
Simulation time 113243784 ps
CPU time 0.76 seconds
Started Mar 09 02:04:04 PM PST 24
Finished Mar 09 02:04:05 PM PST 24
Peak memory 205108 kb
Host smart-53c99b67-2c0d-43b7-8d48-2b876ab80d43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057255561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.4057255561
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2068421514
Short name T425
Test name
Test status
Simulation time 8753537 ps
CPU time 0.81 seconds
Started Mar 09 02:04:05 PM PST 24
Finished Mar 09 02:04:06 PM PST 24
Peak memory 205156 kb
Host smart-daabd13f-e6e1-425d-90d5-ae17db09c7c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068421514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2068421514
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.775843507
Short name T521
Test name
Test status
Simulation time 10437753 ps
CPU time 0.85 seconds
Started Mar 09 02:04:03 PM PST 24
Finished Mar 09 02:04:04 PM PST 24
Peak memory 205092 kb
Host smart-a1ad9f67-9bfd-4662-9130-2ec9330d718b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775843507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.775843507
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.730419158
Short name T180
Test name
Test status
Simulation time 14845607 ps
CPU time 0.75 seconds
Started Mar 09 02:04:06 PM PST 24
Finished Mar 09 02:04:07 PM PST 24
Peak memory 205204 kb
Host smart-7fb45f15-0e08-49e3-9daa-aa2e4956f04a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730419158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.730419158
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3088148871
Short name T448
Test name
Test status
Simulation time 16826310 ps
CPU time 0.85 seconds
Started Mar 09 02:04:02 PM PST 24
Finished Mar 09 02:04:03 PM PST 24
Peak memory 205160 kb
Host smart-5ccb463b-698b-492a-9951-7fde5ae86854
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088148871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3088148871
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2990512602
Short name T419
Test name
Test status
Simulation time 10437126 ps
CPU time 0.81 seconds
Started Mar 09 02:04:06 PM PST 24
Finished Mar 09 02:04:07 PM PST 24
Peak memory 205208 kb
Host smart-e377a7ad-b284-4c0f-962f-cd2116d6c90d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990512602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2990512602
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.790362800
Short name T536
Test name
Test status
Simulation time 10088340 ps
CPU time 0.75 seconds
Started Mar 09 02:04:05 PM PST 24
Finished Mar 09 02:04:06 PM PST 24
Peak memory 205220 kb
Host smart-3602d757-eeb9-4a62-9296-a830c0f50e8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790362800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.790362800
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2619038894
Short name T496
Test name
Test status
Simulation time 9753837 ps
CPU time 0.83 seconds
Started Mar 09 02:04:05 PM PST 24
Finished Mar 09 02:04:06 PM PST 24
Peak memory 205092 kb
Host smart-ac0e6ded-7f34-45b9-be69-4ae1109b5a25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619038894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2619038894
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3852403261
Short name T527
Test name
Test status
Simulation time 16944394 ps
CPU time 0.72 seconds
Started Mar 09 02:04:03 PM PST 24
Finished Mar 09 02:04:04 PM PST 24
Peak memory 205164 kb
Host smart-3806e002-45f3-4184-92ee-e0dde595378e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852403261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3852403261
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.373214288
Short name T128
Test name
Test status
Simulation time 134958940 ps
CPU time 8.75 seconds
Started Mar 09 02:03:41 PM PST 24
Finished Mar 09 02:03:50 PM PST 24
Peak memory 205284 kb
Host smart-a14b04cb-3cbe-4dc8-903f-d7b6b77e1144
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373214288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.373214288
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2752035140
Short name T498
Test name
Test status
Simulation time 1039994477 ps
CPU time 14.82 seconds
Started Mar 09 02:03:39 PM PST 24
Finished Mar 09 02:03:54 PM PST 24
Peak memory 205276 kb
Host smart-5be9d56a-f328-4008-b320-9f82db9a2061
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752035140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
752035140
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.241368192
Short name T465
Test name
Test status
Simulation time 39425294 ps
CPU time 0.95 seconds
Started Mar 09 02:03:41 PM PST 24
Finished Mar 09 02:03:42 PM PST 24
Peak memory 205176 kb
Host smart-fec8b7e9-7869-4626-a3a6-2e571cd7d9d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241368192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.241368192
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2926513777
Short name T488
Test name
Test status
Simulation time 24128984 ps
CPU time 1.41 seconds
Started Mar 09 02:03:41 PM PST 24
Finished Mar 09 02:03:42 PM PST 24
Peak memory 213524 kb
Host smart-b0c87a43-453e-48b1-bd04-16b268f257d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926513777 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2926513777
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2082670247
Short name T528
Test name
Test status
Simulation time 57818221 ps
CPU time 1.27 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:44 PM PST 24
Peak memory 205128 kb
Host smart-4bbe7ffa-4ee3-45e4-b64c-ce9926669d21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082670247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2082670247
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2477478583
Short name T181
Test name
Test status
Simulation time 11883695 ps
CPU time 0.81 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:43 PM PST 24
Peak memory 205172 kb
Host smart-08f6d1d0-1f68-437c-97b1-1a2d34e17ad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477478583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2477478583
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.2953111433
Short name T542
Test name
Test status
Simulation time 36871271 ps
CPU time 2.52 seconds
Started Mar 09 02:03:41 PM PST 24
Finished Mar 09 02:03:44 PM PST 24
Peak memory 205284 kb
Host smart-d2dc2918-29c3-44a1-bb3d-93b90454b56f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953111433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.2953111433
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.604224250
Short name T106
Test name
Test status
Simulation time 101347175 ps
CPU time 2.29 seconds
Started Mar 09 02:03:39 PM PST 24
Finished Mar 09 02:03:42 PM PST 24
Peak memory 213828 kb
Host smart-69928390-d20c-40f0-9ffd-4b978057e696
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604224250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.604224250
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3774295727
Short name T503
Test name
Test status
Simulation time 390568684 ps
CPU time 5.67 seconds
Started Mar 09 02:03:40 PM PST 24
Finished Mar 09 02:03:46 PM PST 24
Peak memory 213764 kb
Host smart-d3b17c9f-5822-4a81-aec2-b8e3d5f3fbce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774295727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3774295727
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.15370105
Short name T427
Test name
Test status
Simulation time 72301717 ps
CPU time 2.64 seconds
Started Mar 09 02:03:38 PM PST 24
Finished Mar 09 02:03:40 PM PST 24
Peak memory 213620 kb
Host smart-1032aec4-145d-4cb1-abfb-1ad895b02db5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15370105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.15370105
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.666303928
Short name T511
Test name
Test status
Simulation time 18369824 ps
CPU time 0.85 seconds
Started Mar 09 02:04:03 PM PST 24
Finished Mar 09 02:04:03 PM PST 24
Peak memory 205148 kb
Host smart-9d89a381-eeba-4785-bc67-74fee11b8602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666303928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.666303928
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1650702352
Short name T451
Test name
Test status
Simulation time 35262943 ps
CPU time 0.88 seconds
Started Mar 09 02:04:10 PM PST 24
Finished Mar 09 02:04:11 PM PST 24
Peak memory 205156 kb
Host smart-3a22b174-1277-428d-a931-e04f5de31c51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650702352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1650702352
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.326668734
Short name T523
Test name
Test status
Simulation time 18705948 ps
CPU time 0.72 seconds
Started Mar 09 02:04:06 PM PST 24
Finished Mar 09 02:04:07 PM PST 24
Peak memory 205176 kb
Host smart-518e9c84-4a54-4136-99a6-5ee4493d11ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326668734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.326668734
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1495724153
Short name T468
Test name
Test status
Simulation time 22747411 ps
CPU time 0.75 seconds
Started Mar 09 02:04:07 PM PST 24
Finished Mar 09 02:04:08 PM PST 24
Peak memory 205216 kb
Host smart-c21c75e9-05d3-48ce-b422-5fa0ab3c92cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495724153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1495724153
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4279946677
Short name T433
Test name
Test status
Simulation time 25357878 ps
CPU time 0.78 seconds
Started Mar 09 02:04:10 PM PST 24
Finished Mar 09 02:04:11 PM PST 24
Peak memory 205172 kb
Host smart-1d151fae-ca5c-409e-9efd-a6dc9ecd8e15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279946677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.4279946677
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1610938148
Short name T434
Test name
Test status
Simulation time 49014722 ps
CPU time 0.74 seconds
Started Mar 09 02:04:11 PM PST 24
Finished Mar 09 02:04:13 PM PST 24
Peak memory 205168 kb
Host smart-68639f9b-55dc-4847-bac4-d7c77843fe3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610938148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1610938148
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3290358935
Short name T440
Test name
Test status
Simulation time 86410022 ps
CPU time 0.78 seconds
Started Mar 09 02:04:06 PM PST 24
Finished Mar 09 02:04:07 PM PST 24
Peak memory 205188 kb
Host smart-9ec23d18-71e6-479b-a0af-0699259d38c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290358935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3290358935
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.882336823
Short name T513
Test name
Test status
Simulation time 12846319 ps
CPU time 0.82 seconds
Started Mar 09 02:04:08 PM PST 24
Finished Mar 09 02:04:09 PM PST 24
Peak memory 205232 kb
Host smart-a206d4ec-478d-4a28-a7d8-46bd7a9c17d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882336823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.882336823
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2962416924
Short name T179
Test name
Test status
Simulation time 12801656 ps
CPU time 0.87 seconds
Started Mar 09 02:04:09 PM PST 24
Finished Mar 09 02:04:10 PM PST 24
Peak memory 205108 kb
Host smart-b2da532e-a4d4-41b9-8ef9-3fd3b02ad93f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962416924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2962416924
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.276150151
Short name T420
Test name
Test status
Simulation time 24366550 ps
CPU time 0.92 seconds
Started Mar 09 02:04:08 PM PST 24
Finished Mar 09 02:04:09 PM PST 24
Peak memory 205188 kb
Host smart-b4bb1708-b6e3-4f7d-8feb-81fbbdd02f74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276150151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.276150151
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2906068729
Short name T467
Test name
Test status
Simulation time 428678431 ps
CPU time 1.89 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:44 PM PST 24
Peak memory 213540 kb
Host smart-1e60c691-2162-450f-af59-2926c00e42b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906068729 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2906068729
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3202554344
Short name T446
Test name
Test status
Simulation time 24009946 ps
CPU time 1.39 seconds
Started Mar 09 02:03:44 PM PST 24
Finished Mar 09 02:03:46 PM PST 24
Peak memory 205184 kb
Host smart-feb41d17-e8aa-4862-b84b-ee760696fd5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202554344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3202554344
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2224336606
Short name T492
Test name
Test status
Simulation time 29800128 ps
CPU time 0.84 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:43 PM PST 24
Peak memory 205172 kb
Host smart-ccf6d035-668c-4880-a9b9-512258ea7312
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224336606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2224336606
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1436443491
Short name T125
Test name
Test status
Simulation time 45921196 ps
CPU time 1.55 seconds
Started Mar 09 02:03:41 PM PST 24
Finished Mar 09 02:03:43 PM PST 24
Peak memory 205424 kb
Host smart-773fee94-d6e4-4850-9410-adaa41b74df2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436443491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1436443491
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.684710860
Short name T107
Test name
Test status
Simulation time 1859369612 ps
CPU time 5.36 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:48 PM PST 24
Peak memory 213764 kb
Host smart-dd53a192-213a-440e-9dde-dd3a47c64c46
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684710860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.684710860
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.35738667
Short name T112
Test name
Test status
Simulation time 350652920 ps
CPU time 8.1 seconds
Started Mar 09 02:03:37 PM PST 24
Finished Mar 09 02:03:45 PM PST 24
Peak memory 213816 kb
Host smart-cb7184ef-11b3-4233-8ade-67303c12e22a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35738667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.ke
ymgr_shadow_reg_errors_with_csr_rw.35738667
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.4063816231
Short name T116
Test name
Test status
Simulation time 434893183 ps
CPU time 2.59 seconds
Started Mar 09 02:03:39 PM PST 24
Finished Mar 09 02:03:41 PM PST 24
Peak memory 213488 kb
Host smart-6f0b51d3-65ed-405e-a44f-b40ca7051c65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063816231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.4063816231
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3005342522
Short name T162
Test name
Test status
Simulation time 282235671 ps
CPU time 5.55 seconds
Started Mar 09 02:03:41 PM PST 24
Finished Mar 09 02:03:46 PM PST 24
Peak memory 208888 kb
Host smart-a52d700a-68c8-43fb-84e8-402d8c4c5d03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005342522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3005342522
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2952572570
Short name T442
Test name
Test status
Simulation time 36232507 ps
CPU time 1.52 seconds
Started Mar 09 02:03:41 PM PST 24
Finished Mar 09 02:03:43 PM PST 24
Peak memory 213684 kb
Host smart-14019a3c-d5bc-4f1f-9014-1d8ccf15b2ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952572570 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2952572570
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1313284077
Short name T545
Test name
Test status
Simulation time 161336745 ps
CPU time 1.3 seconds
Started Mar 09 02:03:44 PM PST 24
Finished Mar 09 02:03:45 PM PST 24
Peak memory 205260 kb
Host smart-b0339ddc-4df1-4daf-a5f9-aa55180ce136
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313284077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1313284077
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3111489527
Short name T439
Test name
Test status
Simulation time 39054274 ps
CPU time 0.71 seconds
Started Mar 09 02:03:46 PM PST 24
Finished Mar 09 02:03:47 PM PST 24
Peak memory 205120 kb
Host smart-0ff350b7-6cad-4de4-b968-039d8f7c7205
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111489527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3111489527
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.707139799
Short name T423
Test name
Test status
Simulation time 1216696720 ps
CPU time 6.55 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:49 PM PST 24
Peak memory 213740 kb
Host smart-5a4d864a-bc7f-4525-a47b-f5044af500e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707139799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.707139799
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3722406140
Short name T461
Test name
Test status
Simulation time 71077879 ps
CPU time 2.3 seconds
Started Mar 09 02:03:43 PM PST 24
Finished Mar 09 02:03:45 PM PST 24
Peak memory 213568 kb
Host smart-f04a78da-d85d-461e-a46b-a2b98349dc1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722406140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3722406140
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3031107121
Short name T119
Test name
Test status
Simulation time 92415061 ps
CPU time 1.95 seconds
Started Mar 09 02:03:44 PM PST 24
Finished Mar 09 02:03:46 PM PST 24
Peak memory 213620 kb
Host smart-289574ba-0d7c-4e77-9d1c-193fa3d42e78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031107121 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3031107121
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1377230146
Short name T432
Test name
Test status
Simulation time 11310326 ps
CPU time 0.8 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:43 PM PST 24
Peak memory 205188 kb
Host smart-fde21fda-abd9-48ac-9150-574d4ee9b4c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377230146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1377230146
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.748961280
Short name T514
Test name
Test status
Simulation time 89722314 ps
CPU time 1.59 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:44 PM PST 24
Peak memory 205364 kb
Host smart-48b47b25-d89f-402a-906b-f1711dc1f968
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748961280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.748961280
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1417245108
Short name T170
Test name
Test status
Simulation time 249428033 ps
CPU time 2.43 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:44 PM PST 24
Peak memory 221984 kb
Host smart-96ae7430-1835-4d24-84f2-7ce980cf437b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417245108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1417245108
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.938412032
Short name T484
Test name
Test status
Simulation time 667994911 ps
CPU time 16.27 seconds
Started Mar 09 02:03:44 PM PST 24
Finished Mar 09 02:04:01 PM PST 24
Peak memory 213904 kb
Host smart-b5ec4e58-a6f9-45e2-8de7-82f01bcf0827
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938412032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.938412032
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1181316148
Short name T449
Test name
Test status
Simulation time 25914496 ps
CPU time 1.49 seconds
Started Mar 09 02:03:45 PM PST 24
Finished Mar 09 02:03:46 PM PST 24
Peak memory 213556 kb
Host smart-d2803801-facc-4a2a-b228-73504693c63c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181316148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1181316148
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2277902626
Short name T422
Test name
Test status
Simulation time 96955793 ps
CPU time 1.87 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:43 PM PST 24
Peak memory 213588 kb
Host smart-4ac57e0a-14e7-49c7-9e6e-017bc51039b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277902626 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2277902626
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.4122665517
Short name T547
Test name
Test status
Simulation time 12753404 ps
CPU time 1.28 seconds
Started Mar 09 02:03:49 PM PST 24
Finished Mar 09 02:03:51 PM PST 24
Peak memory 205340 kb
Host smart-6d34b4bd-76a4-4f8c-a99d-96acdc057e05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122665517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.4122665517
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.342763980
Short name T485
Test name
Test status
Simulation time 23834972 ps
CPU time 1.03 seconds
Started Mar 09 02:03:46 PM PST 24
Finished Mar 09 02:03:48 PM PST 24
Peak memory 205300 kb
Host smart-27a5a020-18c2-4323-8ed5-953dbdeed3ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342763980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.342763980
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.4083717328
Short name T169
Test name
Test status
Simulation time 319499298 ps
CPU time 3.21 seconds
Started Mar 09 02:03:48 PM PST 24
Finished Mar 09 02:03:52 PM PST 24
Peak memory 213828 kb
Host smart-2989b92c-f130-4433-92e2-b3d07b90f873
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083717328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.4083717328
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4078876582
Short name T487
Test name
Test status
Simulation time 1917951900 ps
CPU time 7.13 seconds
Started Mar 09 02:03:45 PM PST 24
Finished Mar 09 02:03:52 PM PST 24
Peak memory 219916 kb
Host smart-b73b6a3e-e063-4250-ae59-ff0469b8d1c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078876582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.4078876582
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1688503474
Short name T426
Test name
Test status
Simulation time 167869929 ps
CPU time 3.13 seconds
Started Mar 09 02:03:49 PM PST 24
Finished Mar 09 02:03:52 PM PST 24
Peak memory 213660 kb
Host smart-68028e8e-5244-48ee-a1aa-7a34dbd542d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688503474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1688503474
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.4080263569
Short name T380
Test name
Test status
Simulation time 130796120 ps
CPU time 6.06 seconds
Started Mar 09 02:03:49 PM PST 24
Finished Mar 09 02:03:55 PM PST 24
Peak memory 213660 kb
Host smart-5a46fa09-85a9-409d-9adc-9c13dae69437
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080263569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.4080263569
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1066393592
Short name T436
Test name
Test status
Simulation time 53972476 ps
CPU time 1.18 seconds
Started Mar 09 02:03:48 PM PST 24
Finished Mar 09 02:03:49 PM PST 24
Peak memory 213636 kb
Host smart-2cf84eba-c2b3-42af-8572-8cc8e0722719
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066393592 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1066393592
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3802589856
Short name T531
Test name
Test status
Simulation time 18067732 ps
CPU time 0.93 seconds
Started Mar 09 02:03:52 PM PST 24
Finished Mar 09 02:03:53 PM PST 24
Peak memory 205120 kb
Host smart-74db42aa-0c60-4f3a-8c77-68f57b42cec1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802589856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3802589856
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1631320700
Short name T428
Test name
Test status
Simulation time 15773187 ps
CPU time 0.71 seconds
Started Mar 09 02:03:49 PM PST 24
Finished Mar 09 02:03:50 PM PST 24
Peak memory 205056 kb
Host smart-ada130e5-71c4-4db0-bde3-9da6c9d882a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631320700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1631320700
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3036678740
Short name T481
Test name
Test status
Simulation time 146208229 ps
CPU time 2.38 seconds
Started Mar 09 02:03:49 PM PST 24
Finished Mar 09 02:03:52 PM PST 24
Peak memory 213524 kb
Host smart-d221ff96-b725-444e-a96c-460122f99fa9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036678740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3036678740
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4044330713
Short name T501
Test name
Test status
Simulation time 1339026950 ps
CPU time 6.8 seconds
Started Mar 09 02:03:42 PM PST 24
Finished Mar 09 02:03:49 PM PST 24
Peak memory 213788 kb
Host smart-cbdc8fea-3fed-43b5-abc8-886259068d96
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044330713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4044330713
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3182582682
Short name T443
Test name
Test status
Simulation time 111070545 ps
CPU time 2.09 seconds
Started Mar 09 02:03:43 PM PST 24
Finished Mar 09 02:03:45 PM PST 24
Peak memory 213516 kb
Host smart-7657944a-f514-4886-a0f3-a1e14137240e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182582682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3182582682
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.4096619620
Short name T825
Test name
Test status
Simulation time 44108985 ps
CPU time 0.73 seconds
Started Mar 09 04:53:19 PM PST 24
Finished Mar 09 04:53:20 PM PST 24
Peak memory 205828 kb
Host smart-9a32fd7a-f2a4-4ffa-9f12-ecc5d35c1180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096619620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.4096619620
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.971783671
Short name T836
Test name
Test status
Simulation time 58915177 ps
CPU time 2.95 seconds
Started Mar 09 04:53:34 PM PST 24
Finished Mar 09 04:53:37 PM PST 24
Peak memory 214428 kb
Host smart-aaf5ff57-652b-42a9-ae1a-87969115e25c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=971783671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.971783671
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3697968884
Short name T681
Test name
Test status
Simulation time 461928889 ps
CPU time 5.3 seconds
Started Mar 09 04:53:39 PM PST 24
Finished Mar 09 04:53:44 PM PST 24
Peak memory 209640 kb
Host smart-76810e0f-d2a5-4a1e-97c3-f8292e017eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697968884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3697968884
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3320628372
Short name T184
Test name
Test status
Simulation time 580016437 ps
CPU time 6.06 seconds
Started Mar 09 04:53:27 PM PST 24
Finished Mar 09 04:53:33 PM PST 24
Peak memory 222440 kb
Host smart-dee86e41-dfc2-4964-a05d-2df216bf4d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320628372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3320628372
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.262128190
Short name T741
Test name
Test status
Simulation time 111026223 ps
CPU time 5.79 seconds
Started Mar 09 04:53:35 PM PST 24
Finished Mar 09 04:53:41 PM PST 24
Peak memory 218756 kb
Host smart-bcfa891b-fd33-4c21-9aaa-16a70c8e4f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262128190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.262128190
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1690892306
Short name T37
Test name
Test status
Simulation time 1260861474 ps
CPU time 36.86 seconds
Started Mar 09 04:53:34 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 235124 kb
Host smart-41f2d4ef-ac53-4433-8221-59f469efaf6f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690892306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1690892306
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3930071564
Short name T806
Test name
Test status
Simulation time 243633701 ps
CPU time 6.74 seconds
Started Mar 09 04:53:06 PM PST 24
Finished Mar 09 04:53:13 PM PST 24
Peak memory 208496 kb
Host smart-810237ae-e8d1-4336-b8dc-4308c71a1630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930071564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3930071564
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2665981491
Short name T687
Test name
Test status
Simulation time 43090089 ps
CPU time 2.45 seconds
Started Mar 09 04:53:21 PM PST 24
Finished Mar 09 04:53:23 PM PST 24
Peak memory 206932 kb
Host smart-56c2c6d8-5134-435d-b561-1bd5675b85f3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665981491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2665981491
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.523670524
Short name T955
Test name
Test status
Simulation time 3218176085 ps
CPU time 61.12 seconds
Started Mar 09 04:53:19 PM PST 24
Finished Mar 09 04:54:20 PM PST 24
Peak memory 208508 kb
Host smart-71e6e3c2-7381-4732-bb94-0905f66ce236
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523670524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.523670524
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2937689697
Short name T1042
Test name
Test status
Simulation time 965887277 ps
CPU time 25.22 seconds
Started Mar 09 04:53:16 PM PST 24
Finished Mar 09 04:53:41 PM PST 24
Peak memory 208028 kb
Host smart-4f117e4e-9db0-4257-a456-095eb4e5dd30
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937689697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2937689697
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1711407993
Short name T249
Test name
Test status
Simulation time 118870260 ps
CPU time 1.62 seconds
Started Mar 09 04:53:29 PM PST 24
Finished Mar 09 04:53:36 PM PST 24
Peak memory 207576 kb
Host smart-5e134e63-0238-45bd-8ad0-c70d2ec2f238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711407993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1711407993
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2754794694
Short name T730
Test name
Test status
Simulation time 647815829 ps
CPU time 7.72 seconds
Started Mar 09 04:53:01 PM PST 24
Finished Mar 09 04:53:10 PM PST 24
Peak memory 208016 kb
Host smart-6e243fe8-23f3-4d62-ab66-757451b96dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754794694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2754794694
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3395233189
Short name T765
Test name
Test status
Simulation time 349557703 ps
CPU time 3.31 seconds
Started Mar 09 04:53:35 PM PST 24
Finished Mar 09 04:53:38 PM PST 24
Peak memory 206064 kb
Host smart-e0074cdc-9230-4d8b-9455-b2fbf32aaa9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395233189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3395233189
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3364428231
Short name T345
Test name
Test status
Simulation time 269973660 ps
CPU time 4.29 seconds
Started Mar 09 04:53:17 PM PST 24
Finished Mar 09 04:53:21 PM PST 24
Peak memory 218428 kb
Host smart-2bfe8c5a-8cc3-48ad-99c7-0ceac3e30714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364428231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3364428231
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2467018612
Short name T57
Test name
Test status
Simulation time 196768028 ps
CPU time 3.68 seconds
Started Mar 09 04:53:29 PM PST 24
Finished Mar 09 04:53:33 PM PST 24
Peak memory 210412 kb
Host smart-296d9aba-3752-45ae-8584-ee5942a4be0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467018612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2467018612
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1715884515
Short name T572
Test name
Test status
Simulation time 19917197 ps
CPU time 1.01 seconds
Started Mar 09 04:53:17 PM PST 24
Finished Mar 09 04:53:18 PM PST 24
Peak memory 206064 kb
Host smart-c1a5ee4d-c7c4-44b9-ad3a-0cfbe563b236
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715884515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1715884515
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1009139913
Short name T306
Test name
Test status
Simulation time 179822219 ps
CPU time 4.34 seconds
Started Mar 09 04:53:37 PM PST 24
Finished Mar 09 04:53:41 PM PST 24
Peak memory 210148 kb
Host smart-32c9c6d9-072e-4d2e-b207-5b8f9eae7a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009139913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1009139913
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1308771004
Short name T907
Test name
Test status
Simulation time 267011948 ps
CPU time 8.99 seconds
Started Mar 09 04:53:26 PM PST 24
Finished Mar 09 04:53:35 PM PST 24
Peak memory 220176 kb
Host smart-6df4125d-157b-4047-b132-166177ccb0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308771004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1308771004
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2995045873
Short name T320
Test name
Test status
Simulation time 283009594 ps
CPU time 9.6 seconds
Started Mar 09 04:53:32 PM PST 24
Finished Mar 09 04:53:41 PM PST 24
Peak memory 210324 kb
Host smart-e92fde3d-8ebd-47ba-a6fb-19e03978af4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995045873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2995045873
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1822456813
Short name T922
Test name
Test status
Simulation time 69496591 ps
CPU time 3.37 seconds
Started Mar 09 04:53:10 PM PST 24
Finished Mar 09 04:53:14 PM PST 24
Peak memory 209984 kb
Host smart-ea002655-7733-42f5-97d6-f7ba46ef8226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822456813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1822456813
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2339643055
Short name T956
Test name
Test status
Simulation time 101967305 ps
CPU time 4.31 seconds
Started Mar 09 04:53:19 PM PST 24
Finished Mar 09 04:53:23 PM PST 24
Peak memory 207700 kb
Host smart-020b4bf6-c76f-41a8-be96-9f78ed512b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339643055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2339643055
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3502849090
Short name T11
Test name
Test status
Simulation time 3562151820 ps
CPU time 20.22 seconds
Started Mar 09 04:53:19 PM PST 24
Finished Mar 09 04:53:40 PM PST 24
Peak memory 236036 kb
Host smart-38d21b4f-fd18-4d36-9013-2fb3249d87eb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502849090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3502849090
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3365030110
Short name T274
Test name
Test status
Simulation time 76506437 ps
CPU time 2.48 seconds
Started Mar 09 04:53:18 PM PST 24
Finished Mar 09 04:53:21 PM PST 24
Peak memory 206920 kb
Host smart-b3663b0c-11cc-4c03-a801-82c418d034ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365030110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3365030110
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.999513867
Short name T574
Test name
Test status
Simulation time 60381852 ps
CPU time 3.04 seconds
Started Mar 09 04:53:33 PM PST 24
Finished Mar 09 04:53:36 PM PST 24
Peak memory 207996 kb
Host smart-951941e6-d3f1-45ce-8dca-9dd7b268acb1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999513867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.999513867
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3212323094
Short name T847
Test name
Test status
Simulation time 34927654 ps
CPU time 2.4 seconds
Started Mar 09 04:53:11 PM PST 24
Finished Mar 09 04:53:14 PM PST 24
Peak memory 207280 kb
Host smart-06b713a4-84f4-4b6f-8935-7d1995a7eec8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212323094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3212323094
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1505232658
Short name T926
Test name
Test status
Simulation time 56485522 ps
CPU time 3.05 seconds
Started Mar 09 04:53:14 PM PST 24
Finished Mar 09 04:53:17 PM PST 24
Peak memory 207952 kb
Host smart-3a289ffa-0bb9-498b-ba40-220540f244dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505232658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1505232658
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.4133179528
Short name T1022
Test name
Test status
Simulation time 146271992 ps
CPU time 4.78 seconds
Started Mar 09 04:53:28 PM PST 24
Finished Mar 09 04:53:32 PM PST 24
Peak memory 214344 kb
Host smart-a023ef46-aac1-4b9b-90bb-85713a505ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133179528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.4133179528
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1058289638
Short name T573
Test name
Test status
Simulation time 196865033 ps
CPU time 2.57 seconds
Started Mar 09 04:53:43 PM PST 24
Finished Mar 09 04:53:46 PM PST 24
Peak memory 207016 kb
Host smart-6d5a9afd-f3d6-4b24-83e9-8cbd44538d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058289638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1058289638
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3037369964
Short name T888
Test name
Test status
Simulation time 14549630795 ps
CPU time 107.1 seconds
Started Mar 09 04:53:42 PM PST 24
Finished Mar 09 04:55:29 PM PST 24
Peak memory 222564 kb
Host smart-ea56987d-2852-4b03-bb10-ac3e88d561dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037369964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3037369964
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.342124292
Short name T206
Test name
Test status
Simulation time 424881763 ps
CPU time 6.56 seconds
Started Mar 09 04:53:29 PM PST 24
Finished Mar 09 04:53:35 PM PST 24
Peak memory 222640 kb
Host smart-c66659e7-786c-49f4-b22f-ac7552a3d333
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342124292 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.342124292
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2616166165
Short name T872
Test name
Test status
Simulation time 545827809 ps
CPU time 6.23 seconds
Started Mar 09 04:53:41 PM PST 24
Finished Mar 09 04:53:48 PM PST 24
Peak memory 210248 kb
Host smart-2bd854cb-549c-445d-a0bd-268ed0cbdb66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616166165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2616166165
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.138489274
Short name T953
Test name
Test status
Simulation time 91426436 ps
CPU time 3.63 seconds
Started Mar 09 04:53:41 PM PST 24
Finished Mar 09 04:53:45 PM PST 24
Peak memory 210464 kb
Host smart-aa450b34-6b8c-4cb2-984f-97b68491efd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138489274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.138489274
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.84054905
Short name T800
Test name
Test status
Simulation time 14133119 ps
CPU time 0.72 seconds
Started Mar 09 04:53:59 PM PST 24
Finished Mar 09 04:54:00 PM PST 24
Peak memory 205896 kb
Host smart-adfeab5a-5c70-4f2d-8ea2-20e7a211f246
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84054905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.84054905
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2289227834
Short name T217
Test name
Test status
Simulation time 445552979 ps
CPU time 8.68 seconds
Started Mar 09 04:54:00 PM PST 24
Finished Mar 09 04:54:09 PM PST 24
Peak memory 221800 kb
Host smart-55a37d08-b77c-4195-afd9-6ad24142e070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289227834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2289227834
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1880139108
Short name T408
Test name
Test status
Simulation time 2058316135 ps
CPU time 5.04 seconds
Started Mar 09 04:53:53 PM PST 24
Finished Mar 09 04:53:58 PM PST 24
Peak memory 218280 kb
Host smart-21c1a0ae-eaed-4b0b-813e-54e2a1de3ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880139108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1880139108
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3874336401
Short name T1064
Test name
Test status
Simulation time 620843847 ps
CPU time 11.56 seconds
Started Mar 09 04:53:47 PM PST 24
Finished Mar 09 04:54:05 PM PST 24
Peak memory 208744 kb
Host smart-647583b8-7b15-4439-af2f-c1c73e21f04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874336401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3874336401
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2274665831
Short name T1043
Test name
Test status
Simulation time 430462683 ps
CPU time 6.53 seconds
Started Mar 09 04:53:50 PM PST 24
Finished Mar 09 04:53:57 PM PST 24
Peak memory 214256 kb
Host smart-0037571d-b804-4231-aa37-e1e0c39f6430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274665831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2274665831
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2093340609
Short name T712
Test name
Test status
Simulation time 528015586 ps
CPU time 3.24 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:01 PM PST 24
Peak memory 209368 kb
Host smart-2bf41c0e-e158-45c9-9e56-b1d722aa4dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093340609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2093340609
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.4262425802
Short name T771
Test name
Test status
Simulation time 4264484279 ps
CPU time 30.85 seconds
Started Mar 09 04:53:54 PM PST 24
Finished Mar 09 04:54:31 PM PST 24
Peak memory 208528 kb
Host smart-3c5e16d1-f546-4f35-8241-394f0c6c774e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262425802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.4262425802
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.953451046
Short name T560
Test name
Test status
Simulation time 364403435 ps
CPU time 3.57 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:01 PM PST 24
Peak memory 206736 kb
Host smart-4346d6f8-354a-4a9f-922b-351e3dc813bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953451046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.953451046
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3887356336
Short name T334
Test name
Test status
Simulation time 4051873737 ps
CPU time 28.57 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:26 PM PST 24
Peak memory 208144 kb
Host smart-89192824-8c45-4208-9d2d-f4bb3a77e5f5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887356336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3887356336
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.386756950
Short name T1008
Test name
Test status
Simulation time 254595696 ps
CPU time 4.12 seconds
Started Mar 09 04:53:52 PM PST 24
Finished Mar 09 04:53:56 PM PST 24
Peak memory 208688 kb
Host smart-284019a1-c3c8-43d4-a34a-fe3c5db34555
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386756950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.386756950
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3098119426
Short name T821
Test name
Test status
Simulation time 146698797 ps
CPU time 6.56 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 208604 kb
Host smart-f83d9d44-ce4d-471c-ba85-ffb5447dcb98
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098119426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3098119426
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1517871374
Short name T908
Test name
Test status
Simulation time 199906923 ps
CPU time 2.57 seconds
Started Mar 09 04:53:43 PM PST 24
Finished Mar 09 04:53:45 PM PST 24
Peak memory 209740 kb
Host smart-053f027c-b281-4304-89bd-a93fc34eb13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517871374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1517871374
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3430745825
Short name T571
Test name
Test status
Simulation time 369389289 ps
CPU time 4.28 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 206668 kb
Host smart-5a95ea83-7088-4980-ae16-e3aec3e9645f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430745825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3430745825
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1545655082
Short name T294
Test name
Test status
Simulation time 3356550971 ps
CPU time 26.69 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:22 PM PST 24
Peak memory 216180 kb
Host smart-ff8d779e-c168-4099-b95c-078caa4b879a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545655082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1545655082
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2732099113
Short name T906
Test name
Test status
Simulation time 212097784 ps
CPU time 9.33 seconds
Started Mar 09 04:53:53 PM PST 24
Finished Mar 09 04:54:03 PM PST 24
Peak memory 220696 kb
Host smart-bbc515fb-e900-4073-9982-b9f301247071
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732099113 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2732099113
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2640310632
Short name T257
Test name
Test status
Simulation time 208220569 ps
CPU time 5.9 seconds
Started Mar 09 04:53:36 PM PST 24
Finished Mar 09 04:53:42 PM PST 24
Peak memory 208912 kb
Host smart-0532d014-0380-455e-a41f-d360789d6633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640310632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2640310632
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.773787194
Short name T376
Test name
Test status
Simulation time 274370717 ps
CPU time 7.93 seconds
Started Mar 09 04:54:06 PM PST 24
Finished Mar 09 04:54:15 PM PST 24
Peak memory 215196 kb
Host smart-1ecc939f-58ab-44f4-95b0-be2fef4aa17b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=773787194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.773787194
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3689596315
Short name T26
Test name
Test status
Simulation time 158052970 ps
CPU time 3.76 seconds
Started Mar 09 04:53:54 PM PST 24
Finished Mar 09 04:53:58 PM PST 24
Peak memory 210428 kb
Host smart-4617390b-8b78-45b2-8017-69aae538b32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689596315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3689596315
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1619495771
Short name T796
Test name
Test status
Simulation time 5207824692 ps
CPU time 13.93 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 219944 kb
Host smart-f7969d67-1db8-449f-8cb1-1cee84ba0f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619495771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1619495771
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3059473693
Short name T358
Test name
Test status
Simulation time 135415506 ps
CPU time 3.58 seconds
Started Mar 09 04:54:05 PM PST 24
Finished Mar 09 04:54:08 PM PST 24
Peak memory 210904 kb
Host smart-301df218-aacc-4ebd-856c-858ec4de8043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059473693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3059473693
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3902562249
Short name T843
Test name
Test status
Simulation time 742078488 ps
CPU time 1.81 seconds
Started Mar 09 04:53:54 PM PST 24
Finished Mar 09 04:53:57 PM PST 24
Peak memory 206552 kb
Host smart-43235fce-b11e-49d4-9ef0-63a415cb8184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902562249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3902562249
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.4165282893
Short name T901
Test name
Test status
Simulation time 987429423 ps
CPU time 19.62 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:17 PM PST 24
Peak memory 208536 kb
Host smart-e5765a37-5e22-417f-9769-998ff148e393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165282893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.4165282893
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.282273218
Short name T318
Test name
Test status
Simulation time 2891615646 ps
CPU time 27.87 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:25 PM PST 24
Peak memory 207912 kb
Host smart-934184ea-7666-45b5-910e-e02fc97a2685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282273218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.282273218
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1193114435
Short name T915
Test name
Test status
Simulation time 95237815 ps
CPU time 3.84 seconds
Started Mar 09 04:54:08 PM PST 24
Finished Mar 09 04:54:12 PM PST 24
Peak memory 208876 kb
Host smart-2d3500e0-90e1-4dfd-9c7d-90f87777f837
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193114435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1193114435
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1555715787
Short name T697
Test name
Test status
Simulation time 523941935 ps
CPU time 6.4 seconds
Started Mar 09 04:53:45 PM PST 24
Finished Mar 09 04:53:51 PM PST 24
Peak memory 208656 kb
Host smart-caa1722d-3985-46a3-be4b-327e6bdf7b78
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555715787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1555715787
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3330621538
Short name T746
Test name
Test status
Simulation time 381731251 ps
CPU time 9.42 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:05 PM PST 24
Peak memory 214320 kb
Host smart-7217f81f-bb00-4603-96d9-2e4e2ade6106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330621538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3330621538
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1180366114
Short name T852
Test name
Test status
Simulation time 170453069 ps
CPU time 6.27 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 208312 kb
Host smart-aaaf77f8-43cc-4c1c-b967-db2d4e9c1876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180366114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1180366114
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3497816419
Short name T636
Test name
Test status
Simulation time 102390403 ps
CPU time 4.76 seconds
Started Mar 09 04:53:53 PM PST 24
Finished Mar 09 04:53:58 PM PST 24
Peak memory 208212 kb
Host smart-5f8a6bd0-3532-41af-9db3-492ed503eae6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497816419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3497816419
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3166794555
Short name T1056
Test name
Test status
Simulation time 406983068 ps
CPU time 7.7 seconds
Started Mar 09 04:54:12 PM PST 24
Finished Mar 09 04:54:20 PM PST 24
Peak memory 219836 kb
Host smart-38dcdc7a-5c68-42bd-ae0a-2fc0bbb2611b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166794555 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3166794555
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1616392792
Short name T639
Test name
Test status
Simulation time 194046534 ps
CPU time 3.17 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:00 PM PST 24
Peak memory 207028 kb
Host smart-b87a13aa-9e20-484f-907f-a3246ed69157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616392792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1616392792
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2896603409
Short name T764
Test name
Test status
Simulation time 168361632 ps
CPU time 2.68 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:53:58 PM PST 24
Peak memory 210396 kb
Host smart-1c870ea7-bb8c-44a4-9f90-db765deec735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896603409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2896603409
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.954886715
Short name T555
Test name
Test status
Simulation time 15987304 ps
CPU time 0.97 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:53:58 PM PST 24
Peak memory 206020 kb
Host smart-bfdbf347-590e-4d9f-8d3c-98622149f168
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954886715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.954886715
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.599244732
Short name T396
Test name
Test status
Simulation time 51653473 ps
CPU time 3.93 seconds
Started Mar 09 04:53:54 PM PST 24
Finished Mar 09 04:53:59 PM PST 24
Peak memory 214192 kb
Host smart-c56a11e2-a9c8-4f77-bf33-927339b354ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=599244732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.599244732
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.539609892
Short name T747
Test name
Test status
Simulation time 77088876 ps
CPU time 1.48 seconds
Started Mar 09 04:53:54 PM PST 24
Finished Mar 09 04:53:56 PM PST 24
Peak memory 207608 kb
Host smart-2c068ed2-a472-417a-ba5e-c70cdfff803b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539609892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.539609892
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1027415692
Short name T270
Test name
Test status
Simulation time 60574344 ps
CPU time 3.37 seconds
Started Mar 09 04:53:53 PM PST 24
Finished Mar 09 04:53:56 PM PST 24
Peak memory 214308 kb
Host smart-131d59eb-7cb9-427e-930d-747d60b9e291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027415692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1027415692
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1956876318
Short name T175
Test name
Test status
Simulation time 51930566 ps
CPU time 2.74 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:00 PM PST 24
Peak memory 209316 kb
Host smart-171f5467-4f50-408f-8c77-143ad506704e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956876318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1956876318
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.3120676696
Short name T679
Test name
Test status
Simulation time 1600958036 ps
CPU time 12.49 seconds
Started Mar 09 04:54:04 PM PST 24
Finished Mar 09 04:54:17 PM PST 24
Peak memory 218352 kb
Host smart-965e49d0-e94a-40f6-8aa3-a253e8edf3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120676696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3120676696
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2789819395
Short name T810
Test name
Test status
Simulation time 124533997 ps
CPU time 2.6 seconds
Started Mar 09 04:53:54 PM PST 24
Finished Mar 09 04:53:57 PM PST 24
Peak memory 208504 kb
Host smart-2d915e1d-2c74-4371-b79b-b05db70d0ea7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789819395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2789819395
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2562405221
Short name T1002
Test name
Test status
Simulation time 610617404 ps
CPU time 4.57 seconds
Started Mar 09 04:54:00 PM PST 24
Finished Mar 09 04:54:05 PM PST 24
Peak memory 206916 kb
Host smart-872581cd-f60d-4d0c-8919-44267685b9ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562405221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2562405221
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1660036777
Short name T233
Test name
Test status
Simulation time 123689960 ps
CPU time 2.41 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:00 PM PST 24
Peak memory 206960 kb
Host smart-762b383a-fb0b-4ceb-83c5-0450ce3327c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660036777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1660036777
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1361617527
Short name T76
Test name
Test status
Simulation time 54905244 ps
CPU time 2.98 seconds
Started Mar 09 04:54:01 PM PST 24
Finished Mar 09 04:54:04 PM PST 24
Peak memory 206864 kb
Host smart-842a2372-9f6f-45b3-b044-201fdbee0e0a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361617527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1361617527
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.4134046523
Short name T232
Test name
Test status
Simulation time 143414259 ps
CPU time 2.29 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:00 PM PST 24
Peak memory 215792 kb
Host smart-c823ae87-3f1e-4362-907b-8336cba556c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134046523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.4134046523
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3029369620
Short name T757
Test name
Test status
Simulation time 85929270 ps
CPU time 2.58 seconds
Started Mar 09 04:53:51 PM PST 24
Finished Mar 09 04:53:54 PM PST 24
Peak memory 208320 kb
Host smart-b373598e-8cfa-4608-8742-da8069a4ac87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029369620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3029369620
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2252378586
Short name T833
Test name
Test status
Simulation time 91752990 ps
CPU time 7.79 seconds
Started Mar 09 04:53:38 PM PST 24
Finished Mar 09 04:53:46 PM PST 24
Peak memory 222664 kb
Host smart-d16688db-f82e-416a-a231-3268721c32de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252378586 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2252378586
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.843816210
Short name T615
Test name
Test status
Simulation time 1449914170 ps
CPU time 8.96 seconds
Started Mar 09 04:54:18 PM PST 24
Finished Mar 09 04:54:27 PM PST 24
Peak memory 214284 kb
Host smart-2d5d01cb-74aa-43b4-a5ba-a46f9ecbe1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843816210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.843816210
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.748138608
Short name T879
Test name
Test status
Simulation time 150472642 ps
CPU time 1.98 seconds
Started Mar 09 04:53:54 PM PST 24
Finished Mar 09 04:54:01 PM PST 24
Peak memory 210828 kb
Host smart-b2be245a-96a8-4811-98d8-75c02bfa1be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748138608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.748138608
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2656014591
Short name T1067
Test name
Test status
Simulation time 16920450 ps
CPU time 0.76 seconds
Started Mar 09 04:53:49 PM PST 24
Finished Mar 09 04:53:50 PM PST 24
Peak memory 205756 kb
Host smart-52049e5a-131e-4162-8f15-b5ea00a85811
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656014591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2656014591
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3458217666
Short name T947
Test name
Test status
Simulation time 226024666 ps
CPU time 3.29 seconds
Started Mar 09 04:54:05 PM PST 24
Finished Mar 09 04:54:08 PM PST 24
Peak memory 215160 kb
Host smart-25a144ea-f445-4f61-ab1d-1aa7644804a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3458217666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3458217666
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1060560938
Short name T30
Test name
Test status
Simulation time 1434086165 ps
CPU time 11.06 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:09 PM PST 24
Peak memory 214288 kb
Host smart-3afb1aa8-6a9e-40e1-8c12-a26f3ae521b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060560938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1060560938
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.70568074
Short name T913
Test name
Test status
Simulation time 2262583848 ps
CPU time 5.64 seconds
Started Mar 09 04:54:03 PM PST 24
Finished Mar 09 04:54:09 PM PST 24
Peak memory 208952 kb
Host smart-53b411af-a542-4903-8506-9abc4e826da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70568074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.70568074
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3546227921
Short name T299
Test name
Test status
Simulation time 562496038 ps
CPU time 6.9 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:05 PM PST 24
Peak memory 219140 kb
Host smart-81f98abe-46c7-4dd9-989a-0d98c0201d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546227921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3546227921
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1855706114
Short name T748
Test name
Test status
Simulation time 66287360 ps
CPU time 1.7 seconds
Started Mar 09 04:54:04 PM PST 24
Finished Mar 09 04:54:06 PM PST 24
Peak memory 206096 kb
Host smart-e400bc03-60ef-4ec1-8a22-a9a95626e632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855706114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1855706114
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.4117069905
Short name T880
Test name
Test status
Simulation time 610918347 ps
CPU time 6.76 seconds
Started Mar 09 04:53:58 PM PST 24
Finished Mar 09 04:54:05 PM PST 24
Peak memory 218484 kb
Host smart-078b2558-f7d8-46f2-bcac-700f7df86197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117069905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.4117069905
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3585845209
Short name T197
Test name
Test status
Simulation time 195645623 ps
CPU time 3.03 seconds
Started Mar 09 04:54:08 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 206952 kb
Host smart-7520fc78-361b-4f0f-abc3-dadceb9daa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585845209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3585845209
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2328806991
Short name T754
Test name
Test status
Simulation time 225092114 ps
CPU time 2.95 seconds
Started Mar 09 04:54:06 PM PST 24
Finished Mar 09 04:54:09 PM PST 24
Peak memory 207248 kb
Host smart-afbec04d-deb9-4df5-8dcf-f5f6ac15a8cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328806991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2328806991
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2937283369
Short name T75
Test name
Test status
Simulation time 136348101 ps
CPU time 3.4 seconds
Started Mar 09 04:53:53 PM PST 24
Finished Mar 09 04:53:57 PM PST 24
Peak memory 208848 kb
Host smart-3022d605-d649-4c4c-b9a1-d760306d1f56
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937283369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2937283369
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2001094933
Short name T1050
Test name
Test status
Simulation time 1040614635 ps
CPU time 14.55 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:12 PM PST 24
Peak memory 207892 kb
Host smart-66559e25-6f91-494d-a708-b7815a5456b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001094933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2001094933
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1030053213
Short name T621
Test name
Test status
Simulation time 186389711 ps
CPU time 1.79 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:53:57 PM PST 24
Peak memory 208940 kb
Host smart-79580897-b84d-4583-9cf3-5697c2f04f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030053213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1030053213
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1097391021
Short name T182
Test name
Test status
Simulation time 891992218 ps
CPU time 10.19 seconds
Started Mar 09 04:54:01 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 208496 kb
Host smart-021a35b3-17f2-4beb-a506-267635bcb186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097391021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1097391021
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1587009336
Short name T890
Test name
Test status
Simulation time 375335065 ps
CPU time 12.22 seconds
Started Mar 09 04:53:59 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 219052 kb
Host smart-f83ed7c0-2e21-4d45-9e81-2c4fdb70a303
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587009336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1587009336
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3009062057
Short name T236
Test name
Test status
Simulation time 9395570358 ps
CPU time 89.93 seconds
Started Mar 09 04:54:08 PM PST 24
Finished Mar 09 04:55:38 PM PST 24
Peak memory 219788 kb
Host smart-1e6d33da-ad5d-45fd-9b75-9283f9d03dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009062057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3009062057
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3791847410
Short name T842
Test name
Test status
Simulation time 11644929 ps
CPU time 0.87 seconds
Started Mar 09 04:54:08 PM PST 24
Finished Mar 09 04:54:09 PM PST 24
Peak memory 205896 kb
Host smart-1e26020b-935c-479b-a70b-a6df868df4af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791847410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3791847410
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2818889443
Short name T758
Test name
Test status
Simulation time 16770536 ps
CPU time 1.34 seconds
Started Mar 09 04:54:05 PM PST 24
Finished Mar 09 04:54:06 PM PST 24
Peak memory 208140 kb
Host smart-d7f9d74f-154d-4d26-a0ef-2cff3be2afdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818889443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2818889443
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.451022906
Short name T90
Test name
Test status
Simulation time 155836942 ps
CPU time 3.7 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:00 PM PST 24
Peak memory 218464 kb
Host smart-6a6d3074-885e-4580-a434-22bf2ef68fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451022906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.451022906
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.469871543
Short name T651
Test name
Test status
Simulation time 203196888 ps
CPU time 2.81 seconds
Started Mar 09 04:54:06 PM PST 24
Finished Mar 09 04:54:10 PM PST 24
Peak memory 207100 kb
Host smart-1f0bbb32-ea66-42ff-b52b-622446df6733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469871543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.469871543
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2617727350
Short name T1012
Test name
Test status
Simulation time 380389357 ps
CPU time 3.54 seconds
Started Mar 09 04:53:58 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 218300 kb
Host smart-3af4c997-1b4c-45fc-b9bc-79bd69509e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617727350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2617727350
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3942127149
Short name T916
Test name
Test status
Simulation time 49962605 ps
CPU time 2.69 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:53:58 PM PST 24
Peak memory 206876 kb
Host smart-3fee852a-d802-43d7-befe-78541f75d91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942127149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3942127149
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1313604026
Short name T389
Test name
Test status
Simulation time 64719986 ps
CPU time 3.14 seconds
Started Mar 09 04:54:02 PM PST 24
Finished Mar 09 04:54:05 PM PST 24
Peak memory 208044 kb
Host smart-cfb3e668-3c2b-4fec-a407-afb1f41f62a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313604026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1313604026
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1443090596
Short name T834
Test name
Test status
Simulation time 531537664 ps
CPU time 4.21 seconds
Started Mar 09 04:53:59 PM PST 24
Finished Mar 09 04:54:03 PM PST 24
Peak memory 209380 kb
Host smart-993b459d-7085-4f20-b017-062c80dda4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443090596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1443090596
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2492007086
Short name T999
Test name
Test status
Simulation time 158873128 ps
CPU time 4.63 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:01 PM PST 24
Peak memory 206808 kb
Host smart-007610bc-3c6f-41c5-89f0-4860e7d2a2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492007086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2492007086
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.4180626825
Short name T221
Test name
Test status
Simulation time 6413054752 ps
CPU time 71.46 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:55:09 PM PST 24
Peak memory 217024 kb
Host smart-f9db917a-2d85-4ddd-8577-f8c051eb3d02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180626825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.4180626825
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.1025848212
Short name T656
Test name
Test status
Simulation time 652761685 ps
CPU time 10.17 seconds
Started Mar 09 04:54:01 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 222648 kb
Host smart-94653901-9f57-4bf9-ba41-6c30a80040d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025848212 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.1025848212
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3256780393
Short name T611
Test name
Test status
Simulation time 362086081 ps
CPU time 5.86 seconds
Started Mar 09 04:53:58 PM PST 24
Finished Mar 09 04:54:04 PM PST 24
Peak memory 208840 kb
Host smart-5e6c77d3-45f1-4c60-bb76-347315d46b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256780393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3256780393
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1961244037
Short name T696
Test name
Test status
Simulation time 202225244 ps
CPU time 2.52 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:00 PM PST 24
Peak memory 210076 kb
Host smart-ba410b9c-301b-4f0c-a05a-e1fb20f17c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961244037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1961244037
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3400203128
Short name T798
Test name
Test status
Simulation time 66824205 ps
CPU time 1 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:08 PM PST 24
Peak memory 206084 kb
Host smart-f7f5ba29-9675-413d-ae46-3bba8afc04b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400203128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3400203128
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.246296792
Short name T272
Test name
Test status
Simulation time 163435051 ps
CPU time 2.71 seconds
Started Mar 09 04:54:05 PM PST 24
Finished Mar 09 04:54:08 PM PST 24
Peak memory 214384 kb
Host smart-0997564a-3653-4151-9305-0acf8a1f2080
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=246296792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.246296792
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.695238691
Short name T27
Test name
Test status
Simulation time 354449161 ps
CPU time 4.82 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 209152 kb
Host smart-9b5ded45-f2e2-4843-a20a-cd4b9af926e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695238691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.695238691
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.438701989
Short name T74
Test name
Test status
Simulation time 1598700482 ps
CPU time 16.28 seconds
Started Mar 09 04:53:58 PM PST 24
Finished Mar 09 04:54:15 PM PST 24
Peak memory 218320 kb
Host smart-54f16374-866c-4ed8-951d-f1d9bd5bc4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438701989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.438701989
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_random.3532148471
Short name T1033
Test name
Test status
Simulation time 262779981 ps
CPU time 6.83 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 218672 kb
Host smart-bf8e1d8e-bc8c-41e8-b21e-14d6ab2dbe73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532148471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3532148471
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3432870762
Short name T231
Test name
Test status
Simulation time 142132346 ps
CPU time 4.5 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:00 PM PST 24
Peak memory 206728 kb
Host smart-f302d9cc-fbce-46e6-b1f9-ca90114686bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432870762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3432870762
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.614759794
Short name T622
Test name
Test status
Simulation time 576617238 ps
CPU time 5.01 seconds
Started Mar 09 04:53:52 PM PST 24
Finished Mar 09 04:53:57 PM PST 24
Peak memory 206936 kb
Host smart-767ab9ec-2030-47e2-8182-f1d4e33f790f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614759794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.614759794
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3649184676
Short name T969
Test name
Test status
Simulation time 61307714 ps
CPU time 2.97 seconds
Started Mar 09 04:53:58 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 208176 kb
Host smart-49091cb1-ed80-4d75-a9b5-70b6c5deb53b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649184676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3649184676
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1095823719
Short name T177
Test name
Test status
Simulation time 399563998 ps
CPU time 3.81 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:01 PM PST 24
Peak memory 208460 kb
Host smart-b4a42f97-ad30-4a54-8953-6317f889639c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095823719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1095823719
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2672617240
Short name T817
Test name
Test status
Simulation time 293991384 ps
CPU time 2.39 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:00 PM PST 24
Peak memory 210200 kb
Host smart-4d7ff4df-a67b-40ff-9df0-0c9c993d2863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672617240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2672617240
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.917785400
Short name T1046
Test name
Test status
Simulation time 212433696 ps
CPU time 7.37 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:05 PM PST 24
Peak memory 207736 kb
Host smart-ec6ae858-26c7-4e82-a1ec-3f5b976bc636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917785400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.917785400
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.695736009
Short name T889
Test name
Test status
Simulation time 1590793539 ps
CPU time 30.77 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:28 PM PST 24
Peak memory 222488 kb
Host smart-e15b877d-1a3d-4bbc-8d38-f2c17bdc2ea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695736009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.695736009
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.616777169
Short name T613
Test name
Test status
Simulation time 612413098 ps
CPU time 5.03 seconds
Started Mar 09 04:54:03 PM PST 24
Finished Mar 09 04:54:08 PM PST 24
Peak memory 208756 kb
Host smart-aad7211a-f214-4b04-995e-9617b4d78791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616777169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.616777169
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3859329595
Short name T777
Test name
Test status
Simulation time 628695159 ps
CPU time 2.59 seconds
Started Mar 09 04:54:04 PM PST 24
Finished Mar 09 04:54:07 PM PST 24
Peak memory 209908 kb
Host smart-9ae5c7f1-b964-4366-a671-67dabb04fefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859329595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3859329595
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2434677706
Short name T121
Test name
Test status
Simulation time 18613373 ps
CPU time 0.78 seconds
Started Mar 09 04:54:03 PM PST 24
Finished Mar 09 04:54:04 PM PST 24
Peak memory 205824 kb
Host smart-8c59b3cf-ebe8-4dbb-9e20-6d4fa39c0fe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434677706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2434677706
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2207101330
Short name T1026
Test name
Test status
Simulation time 883359534 ps
CPU time 10.48 seconds
Started Mar 09 04:54:05 PM PST 24
Finished Mar 09 04:54:16 PM PST 24
Peak memory 214656 kb
Host smart-abf492a2-6096-44b3-8057-46279a747ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207101330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2207101330
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.97824069
Short name T803
Test name
Test status
Simulation time 3231425095 ps
CPU time 11.49 seconds
Started Mar 09 04:54:01 PM PST 24
Finished Mar 09 04:54:13 PM PST 24
Peak memory 219856 kb
Host smart-d645cd44-b8cd-477e-b76c-9feba965157a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97824069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.97824069
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1811284017
Short name T928
Test name
Test status
Simulation time 159556588 ps
CPU time 4.09 seconds
Started Mar 09 04:54:21 PM PST 24
Finished Mar 09 04:54:25 PM PST 24
Peak memory 214336 kb
Host smart-9350d6b8-2ddf-4049-83ef-fcbab8ef60c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811284017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1811284017
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3181740127
Short name T988
Test name
Test status
Simulation time 111766612 ps
CPU time 3.46 seconds
Started Mar 09 04:54:03 PM PST 24
Finished Mar 09 04:54:07 PM PST 24
Peak memory 208892 kb
Host smart-f69461ba-c0f0-4bbd-be96-4481355f86c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181740127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3181740127
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.394737277
Short name T371
Test name
Test status
Simulation time 451912995 ps
CPU time 6.47 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 218144 kb
Host smart-5d86fd70-f78c-4cdf-95a8-1dfdb3f9b16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394737277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.394737277
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2896767614
Short name T659
Test name
Test status
Simulation time 27297941 ps
CPU time 2.03 seconds
Started Mar 09 04:54:16 PM PST 24
Finished Mar 09 04:54:19 PM PST 24
Peak memory 208468 kb
Host smart-d0405ead-2850-40f9-8fc5-e9990f0d1b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896767614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2896767614
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.956337505
Short name T788
Test name
Test status
Simulation time 155943802 ps
CPU time 3.49 seconds
Started Mar 09 04:54:05 PM PST 24
Finished Mar 09 04:54:14 PM PST 24
Peak memory 208460 kb
Host smart-1b81e84b-15ec-4a17-8e75-cba98d6ec8cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956337505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.956337505
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1138096504
Short name T627
Test name
Test status
Simulation time 351171283 ps
CPU time 8.69 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:05 PM PST 24
Peak memory 208336 kb
Host smart-4d0c47ae-551f-4827-91db-cd94344f21f4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138096504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1138096504
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.450767169
Short name T277
Test name
Test status
Simulation time 201893916 ps
CPU time 3.35 seconds
Started Mar 09 04:53:59 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 208628 kb
Host smart-e6a75847-1222-413f-8751-2e744c622be8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450767169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.450767169
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2448798768
Short name T252
Test name
Test status
Simulation time 854199591 ps
CPU time 5.28 seconds
Started Mar 09 04:53:59 PM PST 24
Finished Mar 09 04:54:05 PM PST 24
Peak memory 208316 kb
Host smart-3085baa0-7baf-43bb-8183-6a7382e27e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448798768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2448798768
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2340685253
Short name T980
Test name
Test status
Simulation time 165421659 ps
CPU time 5.21 seconds
Started Mar 09 04:54:01 PM PST 24
Finished Mar 09 04:54:06 PM PST 24
Peak memory 208184 kb
Host smart-44868a48-ffd1-43ca-8119-14f62ef1d048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340685253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2340685253
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3549801978
Short name T648
Test name
Test status
Simulation time 113569033 ps
CPU time 5.28 seconds
Started Mar 09 04:53:53 PM PST 24
Finished Mar 09 04:54:00 PM PST 24
Peak memory 208652 kb
Host smart-3f4a5d9c-6c95-41d2-981a-4fddb300b609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549801978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3549801978
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2800300456
Short name T797
Test name
Test status
Simulation time 57179638 ps
CPU time 2.6 seconds
Started Mar 09 04:54:32 PM PST 24
Finished Mar 09 04:54:37 PM PST 24
Peak memory 210156 kb
Host smart-d004ebe8-ae63-4ed0-a933-48cfc5334e09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800300456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2800300456
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2440276648
Short name T839
Test name
Test status
Simulation time 13171385 ps
CPU time 0.82 seconds
Started Mar 09 04:54:09 PM PST 24
Finished Mar 09 04:54:10 PM PST 24
Peak memory 205700 kb
Host smart-5af7adbf-a4f2-48fe-b5d3-f1172f3ad4c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440276648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2440276648
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.807022828
Short name T377
Test name
Test status
Simulation time 2298372157 ps
CPU time 15.52 seconds
Started Mar 09 04:54:03 PM PST 24
Finished Mar 09 04:54:19 PM PST 24
Peak memory 215032 kb
Host smart-71bbc4e2-9a49-415d-b246-8aa18f974610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807022828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.807022828
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.850891634
Short name T664
Test name
Test status
Simulation time 283887784 ps
CPU time 2.85 seconds
Started Mar 09 04:54:27 PM PST 24
Finished Mar 09 04:54:31 PM PST 24
Peak memory 207436 kb
Host smart-2ecfe1b5-c663-4adc-abb8-0db438083656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850891634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.850891634
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3446071058
Short name T362
Test name
Test status
Simulation time 1473605567 ps
CPU time 9.1 seconds
Started Mar 09 04:53:54 PM PST 24
Finished Mar 09 04:54:04 PM PST 24
Peak memory 214188 kb
Host smart-f8726347-4d2b-4a89-ab1b-1937987696c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446071058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3446071058
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1820590981
Short name T339
Test name
Test status
Simulation time 1755058732 ps
CPU time 25.75 seconds
Started Mar 09 04:54:28 PM PST 24
Finished Mar 09 04:54:55 PM PST 24
Peak memory 222460 kb
Host smart-1c01eefd-ae04-4df0-97c4-ff16fc90c19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820590981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1820590981
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.149755029
Short name T410
Test name
Test status
Simulation time 3009760999 ps
CPU time 42.05 seconds
Started Mar 09 04:54:30 PM PST 24
Finished Mar 09 04:55:13 PM PST 24
Peak memory 222372 kb
Host smart-1f08f8a2-7e04-4c37-b693-30713274cb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149755029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.149755029
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.731512857
Short name T677
Test name
Test status
Simulation time 5571845393 ps
CPU time 18.96 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:15 PM PST 24
Peak memory 208240 kb
Host smart-1c8963c6-6879-4a24-902f-1338a3c1bfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731512857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.731512857
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2460615236
Short name T607
Test name
Test status
Simulation time 1055443447 ps
CPU time 8.33 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:15 PM PST 24
Peak memory 206800 kb
Host smart-502fba9f-6570-466f-b6bc-d776c113c903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460615236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2460615236
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1142163012
Short name T985
Test name
Test status
Simulation time 369271902 ps
CPU time 3.6 seconds
Started Mar 09 04:54:18 PM PST 24
Finished Mar 09 04:54:22 PM PST 24
Peak memory 208588 kb
Host smart-2658eacd-1cf3-44b9-bdae-d192e7152a29
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142163012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1142163012
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.546305093
Short name T894
Test name
Test status
Simulation time 578718838 ps
CPU time 4.65 seconds
Started Mar 09 04:54:02 PM PST 24
Finished Mar 09 04:54:07 PM PST 24
Peak memory 206884 kb
Host smart-433b01fd-8dd7-4393-a7bc-91bf2a3cfa99
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546305093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.546305093
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1108617961
Short name T570
Test name
Test status
Simulation time 71984195 ps
CPU time 2.84 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:53:59 PM PST 24
Peak memory 208732 kb
Host smart-9d79a5c5-27ac-4634-b60b-f42b40bfa4b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108617961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1108617961
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3122295187
Short name T628
Test name
Test status
Simulation time 538658756 ps
CPU time 12.14 seconds
Started Mar 09 04:54:29 PM PST 24
Finished Mar 09 04:54:42 PM PST 24
Peak memory 208760 kb
Host smart-bbd18fc0-c0a7-466a-9afe-d7f13ddb7d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122295187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3122295187
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2014304137
Short name T601
Test name
Test status
Simulation time 384815261 ps
CPU time 2.86 seconds
Started Mar 09 04:54:06 PM PST 24
Finished Mar 09 04:54:09 PM PST 24
Peak memory 208256 kb
Host smart-a32af125-d50b-464e-92ce-ea9cc91ae952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014304137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2014304137
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.986453466
Short name T630
Test name
Test status
Simulation time 2474345219 ps
CPU time 17.38 seconds
Started Mar 09 04:54:33 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 220676 kb
Host smart-ecf338e2-afc6-4acf-8476-7085f9b0d745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986453466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.986453466
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3076537664
Short name T248
Test name
Test status
Simulation time 512213186 ps
CPU time 5.52 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:14 PM PST 24
Peak memory 222660 kb
Host smart-3af6494f-5177-498e-a391-fdd5c5d08eac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076537664 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3076537664
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.4229421609
Short name T1029
Test name
Test status
Simulation time 1083373444 ps
CPU time 11.32 seconds
Started Mar 09 04:53:58 PM PST 24
Finished Mar 09 04:54:10 PM PST 24
Peak memory 208196 kb
Host smart-2edf24f2-2760-4e0b-a0cf-781bd39b872d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229421609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.4229421609
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3658494956
Short name T742
Test name
Test status
Simulation time 395722729 ps
CPU time 4.17 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:53:59 PM PST 24
Peak memory 210584 kb
Host smart-b4eac113-6ec0-4eb0-bd56-81b90c120935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658494956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3658494956
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2107766645
Short name T853
Test name
Test status
Simulation time 45661429 ps
CPU time 0.9 seconds
Started Mar 09 04:54:05 PM PST 24
Finished Mar 09 04:54:06 PM PST 24
Peak memory 205876 kb
Host smart-684a028d-8bb4-40f1-be3c-9d746aaac384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107766645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2107766645
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3039049696
Short name T77
Test name
Test status
Simulation time 65383617 ps
CPU time 2.69 seconds
Started Mar 09 04:54:31 PM PST 24
Finished Mar 09 04:54:35 PM PST 24
Peak memory 214248 kb
Host smart-96fc9d45-3fed-4d5f-bdfe-b73aa284f5a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3039049696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3039049696
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.4293255715
Short name T936
Test name
Test status
Simulation time 268265765 ps
CPU time 3.51 seconds
Started Mar 09 04:54:33 PM PST 24
Finished Mar 09 04:54:38 PM PST 24
Peak memory 214584 kb
Host smart-05dc6805-b7b5-4ae3-bd3d-72039dc622cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293255715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.4293255715
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2461657214
Short name T835
Test name
Test status
Simulation time 97339988 ps
CPU time 3.1 seconds
Started Mar 09 04:54:20 PM PST 24
Finished Mar 09 04:54:24 PM PST 24
Peak memory 210184 kb
Host smart-cb7be4d7-e996-4b4f-be68-defa7454b6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461657214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2461657214
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.117519662
Short name T737
Test name
Test status
Simulation time 4972003765 ps
CPU time 14.22 seconds
Started Mar 09 04:54:02 PM PST 24
Finished Mar 09 04:54:17 PM PST 24
Peak memory 214344 kb
Host smart-2175244f-01ac-4334-8209-efc5f04e2fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117519662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.117519662
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_random.1297492713
Short name T645
Test name
Test status
Simulation time 69527033 ps
CPU time 2.78 seconds
Started Mar 09 04:54:01 PM PST 24
Finished Mar 09 04:54:04 PM PST 24
Peak memory 207492 kb
Host smart-e5bcf9ac-10e3-4a69-8325-491e50ffcf28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297492713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1297492713
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1155610476
Short name T285
Test name
Test status
Simulation time 123625051 ps
CPU time 3.2 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:01 PM PST 24
Peak memory 208448 kb
Host smart-9af1d37f-284b-4469-976b-eb576dcb8e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155610476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1155610476
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3975546349
Short name T898
Test name
Test status
Simulation time 28330983 ps
CPU time 2.38 seconds
Started Mar 09 04:54:01 PM PST 24
Finished Mar 09 04:54:03 PM PST 24
Peak memory 208764 kb
Host smart-17ddef66-8bdd-42e7-b1c3-a9742966f420
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975546349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3975546349
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.329046904
Short name T756
Test name
Test status
Simulation time 1486009484 ps
CPU time 30.03 seconds
Started Mar 09 04:54:29 PM PST 24
Finished Mar 09 04:55:00 PM PST 24
Peak memory 208476 kb
Host smart-9c8a4e1a-2d06-4d15-a286-7a3879009278
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329046904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.329046904
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.875103554
Short name T316
Test name
Test status
Simulation time 122521446 ps
CPU time 2.47 seconds
Started Mar 09 04:54:06 PM PST 24
Finished Mar 09 04:54:09 PM PST 24
Peak memory 206676 kb
Host smart-f31e57a6-8820-4d9a-ac1e-082d097389ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875103554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.875103554
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3527065136
Short name T990
Test name
Test status
Simulation time 160059990 ps
CPU time 3.86 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:12 PM PST 24
Peak memory 209496 kb
Host smart-790c3778-6680-4c45-81c4-f1a9f68660c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527065136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3527065136
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1720343930
Short name T1001
Test name
Test status
Simulation time 33114794 ps
CPU time 2.42 seconds
Started Mar 09 04:54:03 PM PST 24
Finished Mar 09 04:54:06 PM PST 24
Peak memory 206828 kb
Host smart-32d7525e-512f-4380-bb3b-179e33abbf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720343930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1720343930
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2591564560
Short name T409
Test name
Test status
Simulation time 91625378 ps
CPU time 2.79 seconds
Started Mar 09 04:53:58 PM PST 24
Finished Mar 09 04:54:01 PM PST 24
Peak memory 221860 kb
Host smart-a3f1b463-278c-455c-a34c-77dcc4725b9d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591564560 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2591564560
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2516343861
Short name T156
Test name
Test status
Simulation time 214548043 ps
CPU time 2.35 seconds
Started Mar 09 04:54:28 PM PST 24
Finished Mar 09 04:54:31 PM PST 24
Peak memory 210428 kb
Host smart-5d3c5c1e-e73c-4418-a14d-b4a3ac93be1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516343861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2516343861
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.121203859
Short name T1070
Test name
Test status
Simulation time 14537214 ps
CPU time 0.81 seconds
Started Mar 09 04:54:09 PM PST 24
Finished Mar 09 04:54:10 PM PST 24
Peak memory 205900 kb
Host smart-50ce74b1-2d6d-41d0-96c1-7b34601aadf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121203859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.121203859
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3077941269
Short name T416
Test name
Test status
Simulation time 149730466 ps
CPU time 3.04 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:53:59 PM PST 24
Peak memory 214316 kb
Host smart-ca011ac7-5be6-4e1c-8cc1-8b9756c6b429
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3077941269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3077941269
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1569611612
Short name T878
Test name
Test status
Simulation time 1102785437 ps
CPU time 11.39 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:19 PM PST 24
Peak memory 222456 kb
Host smart-3906e326-37f6-4f7a-963a-cc91f3f46b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569611612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1569611612
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1216997379
Short name T699
Test name
Test status
Simulation time 212259783 ps
CPU time 2.98 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:01 PM PST 24
Peak memory 207620 kb
Host smart-e3240ba4-4438-43c0-8a54-de143fe2cfa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216997379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1216997379
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.892246644
Short name T364
Test name
Test status
Simulation time 356482992 ps
CPU time 7.65 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:16 PM PST 24
Peak memory 208324 kb
Host smart-8dcff93c-1fbf-4814-8d0d-4f6a12ed1f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892246644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.892246644
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.4115062695
Short name T240
Test name
Test status
Simulation time 221048783 ps
CPU time 4.11 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:00 PM PST 24
Peak memory 214284 kb
Host smart-cbdc3bcb-fe88-47ee-a400-b1ac66f591ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115062695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.4115062695
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2924045510
Short name T209
Test name
Test status
Simulation time 154001685 ps
CPU time 4.8 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 209688 kb
Host smart-ec7357bc-a2b1-456f-8b93-c29fda05dd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924045510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2924045510
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.251868611
Short name T1059
Test name
Test status
Simulation time 227583998 ps
CPU time 4.17 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:12 PM PST 24
Peak memory 222408 kb
Host smart-a69f12ad-1ffc-42a0-97c7-915ff2bae602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251868611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.251868611
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2766504184
Short name T353
Test name
Test status
Simulation time 358092264 ps
CPU time 3.36 seconds
Started Mar 09 04:54:29 PM PST 24
Finished Mar 09 04:54:33 PM PST 24
Peak memory 207132 kb
Host smart-8b0774a0-f6ba-4777-9eea-6af66fcbb9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766504184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2766504184
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2368630923
Short name T791
Test name
Test status
Simulation time 521815471 ps
CPU time 6.64 seconds
Started Mar 09 04:54:06 PM PST 24
Finished Mar 09 04:54:12 PM PST 24
Peak memory 208468 kb
Host smart-5d175d3f-e441-48d2-b2cc-139631c86e1a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368630923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2368630923
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2711881206
Short name T382
Test name
Test status
Simulation time 533609592 ps
CPU time 4.52 seconds
Started Mar 09 04:54:06 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 207988 kb
Host smart-a41c4fb9-1c01-4166-a6a0-986ca4bbe809
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711881206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2711881206
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2653758859
Short name T952
Test name
Test status
Simulation time 294947917 ps
CPU time 3.7 seconds
Started Mar 09 04:54:20 PM PST 24
Finished Mar 09 04:54:24 PM PST 24
Peak memory 208440 kb
Host smart-11b43dac-ee05-4a4d-9cbc-759762befcde
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653758859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2653758859
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.477146607
Short name T981
Test name
Test status
Simulation time 279504411 ps
CPU time 3.22 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:10 PM PST 24
Peak memory 222492 kb
Host smart-efe69d24-e21b-476e-ae9f-34c3a0ebe9d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477146607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.477146607
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3522460558
Short name T674
Test name
Test status
Simulation time 1524509106 ps
CPU time 4.18 seconds
Started Mar 09 04:53:53 PM PST 24
Finished Mar 09 04:53:58 PM PST 24
Peak memory 207008 kb
Host smart-5a24a9c1-a079-47a9-997e-dd9f9c582a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522460558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3522460558
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3225792442
Short name T612
Test name
Test status
Simulation time 1065199401 ps
CPU time 4.95 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 208448 kb
Host smart-71e766d1-4e32-481d-bcac-b0f594bf3e7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225792442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3225792442
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3986780845
Short name T975
Test name
Test status
Simulation time 218271309 ps
CPU time 3.72 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:12 PM PST 24
Peak memory 218400 kb
Host smart-6a666723-d790-4f0c-8ee8-afd00dea3710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986780845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3986780845
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2539262548
Short name T593
Test name
Test status
Simulation time 30408079 ps
CPU time 1.91 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:53:58 PM PST 24
Peak memory 210112 kb
Host smart-d08b6872-d209-49bd-af1b-361273018a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539262548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2539262548
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3557064692
Short name T721
Test name
Test status
Simulation time 11711690 ps
CPU time 0.76 seconds
Started Mar 09 04:53:41 PM PST 24
Finished Mar 09 04:53:42 PM PST 24
Peak memory 205844 kb
Host smart-f35ff0a3-c2d9-4a75-a479-874baad225a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557064692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3557064692
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1170933847
Short name T397
Test name
Test status
Simulation time 344053888 ps
CPU time 9.87 seconds
Started Mar 09 04:53:25 PM PST 24
Finished Mar 09 04:53:35 PM PST 24
Peak memory 214256 kb
Host smart-ab1b6c80-827e-4e26-89b5-1fcbdfe94fba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1170933847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1170933847
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2334033193
Short name T779
Test name
Test status
Simulation time 189646869 ps
CPU time 5.13 seconds
Started Mar 09 04:53:45 PM PST 24
Finished Mar 09 04:53:50 PM PST 24
Peak memory 210256 kb
Host smart-5b216ef5-60af-4b28-be07-02830d1b90c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334033193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2334033193
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2698401661
Short name T669
Test name
Test status
Simulation time 229136924 ps
CPU time 2.58 seconds
Started Mar 09 04:53:17 PM PST 24
Finished Mar 09 04:53:19 PM PST 24
Peak memory 218324 kb
Host smart-d33bd851-6554-4d9c-8e22-8513fc56e6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698401661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2698401661
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2838274966
Short name T29
Test name
Test status
Simulation time 121542692 ps
CPU time 5.32 seconds
Started Mar 09 04:53:41 PM PST 24
Finished Mar 09 04:53:47 PM PST 24
Peak memory 211264 kb
Host smart-f097ff80-4d1b-4458-aab9-821643ff9dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838274966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2838274966
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.4068349858
Short name T594
Test name
Test status
Simulation time 149633145 ps
CPU time 3.98 seconds
Started Mar 09 04:53:38 PM PST 24
Finished Mar 09 04:53:42 PM PST 24
Peak memory 209520 kb
Host smart-6b652e33-e297-421b-b980-7af340b9cffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068349858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.4068349858
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.811079123
Short name T388
Test name
Test status
Simulation time 3554383683 ps
CPU time 14.36 seconds
Started Mar 09 04:53:33 PM PST 24
Finished Mar 09 04:53:48 PM PST 24
Peak memory 214392 kb
Host smart-172d0466-1100-4d6c-8eb8-c5a6665cafd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811079123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.811079123
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2886498108
Short name T191
Test name
Test status
Simulation time 78733736 ps
CPU time 3.65 seconds
Started Mar 09 04:53:20 PM PST 24
Finished Mar 09 04:53:29 PM PST 24
Peak memory 208556 kb
Host smart-ba99ffd6-661b-4803-acdf-65693f1da88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886498108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2886498108
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.4069936533
Short name T564
Test name
Test status
Simulation time 56446634 ps
CPU time 3.05 seconds
Started Mar 09 04:53:26 PM PST 24
Finished Mar 09 04:53:29 PM PST 24
Peak memory 208612 kb
Host smart-6d744858-edd5-4eee-915e-80bcba803ac6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069936533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.4069936533
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3719848672
Short name T620
Test name
Test status
Simulation time 32889296 ps
CPU time 2.48 seconds
Started Mar 09 04:53:30 PM PST 24
Finished Mar 09 04:53:32 PM PST 24
Peak memory 208556 kb
Host smart-f7d0ac5f-fa8c-422d-899e-603a3fc973e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719848672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3719848672
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2945901417
Short name T1004
Test name
Test status
Simulation time 58540084 ps
CPU time 3.04 seconds
Started Mar 09 04:53:40 PM PST 24
Finished Mar 09 04:53:43 PM PST 24
Peak memory 206968 kb
Host smart-a53aef35-4ba0-43ac-8082-9c65267f0169
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945901417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2945901417
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1836928605
Short name T330
Test name
Test status
Simulation time 195571018 ps
CPU time 2.55 seconds
Started Mar 09 04:53:23 PM PST 24
Finished Mar 09 04:53:25 PM PST 24
Peak memory 209500 kb
Host smart-6adc14db-c1a1-4db4-8753-cc281e4b2fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836928605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1836928605
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.552907736
Short name T1047
Test name
Test status
Simulation time 57587368 ps
CPU time 2.91 seconds
Started Mar 09 04:53:29 PM PST 24
Finished Mar 09 04:53:32 PM PST 24
Peak memory 208232 kb
Host smart-27904ede-0048-4ec9-80d4-226998edb462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552907736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.552907736
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2886905468
Short name T786
Test name
Test status
Simulation time 1711721941 ps
CPU time 15.8 seconds
Started Mar 09 04:53:27 PM PST 24
Finished Mar 09 04:53:43 PM PST 24
Peak memory 222392 kb
Host smart-81acfc91-5076-441f-b36f-7a85384f42fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886905468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2886905468
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1494820814
Short name T1052
Test name
Test status
Simulation time 462898730 ps
CPU time 5.05 seconds
Started Mar 09 04:53:43 PM PST 24
Finished Mar 09 04:53:49 PM PST 24
Peak memory 222616 kb
Host smart-3a0336f5-5841-45f9-a11b-26f9690a8fee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494820814 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1494820814
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3015579247
Short name T994
Test name
Test status
Simulation time 49655873 ps
CPU time 3.37 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:53:59 PM PST 24
Peak memory 207776 kb
Host smart-486c8a2b-ea1e-45eb-9341-ef1d756a4579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015579247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3015579247
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.4129749328
Short name T567
Test name
Test status
Simulation time 87041015 ps
CPU time 3.16 seconds
Started Mar 09 04:53:43 PM PST 24
Finished Mar 09 04:53:46 PM PST 24
Peak memory 210912 kb
Host smart-b2d25d69-c694-4eeb-8843-884b78db0827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129749328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.4129749328
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3597395453
Short name T101
Test name
Test status
Simulation time 22503656 ps
CPU time 0.93 seconds
Started Mar 09 04:54:04 PM PST 24
Finished Mar 09 04:54:06 PM PST 24
Peak memory 205788 kb
Host smart-f4ccd1e8-4b39-49c8-ae1a-8c516ed31c8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597395453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3597395453
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3640959750
Short name T228
Test name
Test status
Simulation time 524166320 ps
CPU time 4.3 seconds
Started Mar 09 04:54:28 PM PST 24
Finished Mar 09 04:54:33 PM PST 24
Peak memory 214300 kb
Host smart-c273dc42-6992-4c50-8496-7e72a83e452f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3640959750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3640959750
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1436481686
Short name T1055
Test name
Test status
Simulation time 2847921177 ps
CPU time 13.22 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:09 PM PST 24
Peak memory 218476 kb
Host smart-23bd8afc-8cb1-41a9-825b-b75a815b362e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436481686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1436481686
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1388785994
Short name T378
Test name
Test status
Simulation time 37097901203 ps
CPU time 38.19 seconds
Started Mar 09 04:54:12 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 209412 kb
Host smart-3c020df1-c6cb-440f-8bbe-00897e287fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388785994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1388785994
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1631841699
Short name T661
Test name
Test status
Simulation time 161639424 ps
CPU time 3.18 seconds
Started Mar 09 04:54:01 PM PST 24
Finished Mar 09 04:54:04 PM PST 24
Peak memory 209684 kb
Host smart-463e7246-d40f-4552-9861-9ac5b5cb10d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631841699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1631841699
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.139671634
Short name T178
Test name
Test status
Simulation time 132287648 ps
CPU time 5.01 seconds
Started Mar 09 04:54:06 PM PST 24
Finished Mar 09 04:54:12 PM PST 24
Peak memory 207528 kb
Host smart-e5c85993-323a-4c87-b98b-ebd3de3fa3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139671634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.139671634
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1587391919
Short name T781
Test name
Test status
Simulation time 3150481875 ps
CPU time 22.74 seconds
Started Mar 09 04:54:23 PM PST 24
Finished Mar 09 04:54:46 PM PST 24
Peak memory 207976 kb
Host smart-d5723cf6-ddba-4a43-8e2c-255b91ec1b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587391919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1587391919
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1673133265
Short name T394
Test name
Test status
Simulation time 263513349 ps
CPU time 3.51 seconds
Started Mar 09 04:54:02 PM PST 24
Finished Mar 09 04:54:06 PM PST 24
Peak memory 209076 kb
Host smart-05b95540-c21b-4f18-a4c3-07b4d6cbcf62
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673133265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1673133265
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3331290955
Short name T811
Test name
Test status
Simulation time 309678866 ps
CPU time 3.9 seconds
Started Mar 09 04:54:08 PM PST 24
Finished Mar 09 04:54:12 PM PST 24
Peak memory 209060 kb
Host smart-f40b8896-30ef-461f-bd39-8f80c80cd64a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331290955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3331290955
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3540126923
Short name T718
Test name
Test status
Simulation time 1607358373 ps
CPU time 12.67 seconds
Started Mar 09 04:54:08 PM PST 24
Finished Mar 09 04:54:21 PM PST 24
Peak memory 208092 kb
Host smart-944b353d-6d7c-41d8-9714-54023645ef0e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540126923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3540126923
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3234310003
Short name T401
Test name
Test status
Simulation time 723712530 ps
CPU time 2.19 seconds
Started Mar 09 04:54:10 PM PST 24
Finished Mar 09 04:54:13 PM PST 24
Peak memory 210124 kb
Host smart-aa2927df-57cf-4090-90a3-aa5cfcc4d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234310003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3234310003
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2356227503
Short name T750
Test name
Test status
Simulation time 33631728 ps
CPU time 1.95 seconds
Started Mar 09 04:54:27 PM PST 24
Finished Mar 09 04:54:30 PM PST 24
Peak memory 207956 kb
Host smart-d72807fc-8bbc-4b8f-a510-3acc6f6d2977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356227503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2356227503
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1000761178
Short name T368
Test name
Test status
Simulation time 841478387 ps
CPU time 33.44 seconds
Started Mar 09 04:54:04 PM PST 24
Finished Mar 09 04:54:38 PM PST 24
Peak memory 220312 kb
Host smart-747b40b3-05a8-4dd9-90c9-fcab7fa1a5f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000761178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1000761178
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.2311373463
Short name T213
Test name
Test status
Simulation time 218816961 ps
CPU time 4.83 seconds
Started Mar 09 04:54:16 PM PST 24
Finished Mar 09 04:54:21 PM PST 24
Peak memory 219236 kb
Host smart-9c0552f7-0ca2-4f89-92f8-58d6bf160e83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311373463 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.2311373463
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2209583048
Short name T789
Test name
Test status
Simulation time 404956286 ps
CPU time 6.92 seconds
Started Mar 09 04:54:27 PM PST 24
Finished Mar 09 04:54:35 PM PST 24
Peak memory 218048 kb
Host smart-04a16377-d27f-499d-862d-d7dcf8eefda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209583048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2209583048
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2739227160
Short name T1010
Test name
Test status
Simulation time 116397991 ps
CPU time 2.33 seconds
Started Mar 09 04:54:13 PM PST 24
Finished Mar 09 04:54:16 PM PST 24
Peak memory 209896 kb
Host smart-7676335c-03d4-4b1f-9186-0c4b5e426ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739227160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2739227160
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3271933447
Short name T874
Test name
Test status
Simulation time 21626118 ps
CPU time 0.81 seconds
Started Mar 09 04:54:28 PM PST 24
Finished Mar 09 04:54:30 PM PST 24
Peak memory 205892 kb
Host smart-26cef1d7-10b6-4222-8717-9d062a1308e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271933447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3271933447
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1611217104
Short name T414
Test name
Test status
Simulation time 33855985 ps
CPU time 2.58 seconds
Started Mar 09 04:53:59 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 214304 kb
Host smart-f8ca7e0b-0e82-4810-bfd7-33ca34a4fa50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1611217104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1611217104
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2480196134
Short name T925
Test name
Test status
Simulation time 798479238 ps
CPU time 4.91 seconds
Started Mar 09 04:54:06 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 209856 kb
Host smart-dc49b893-cc6c-4d09-8723-dad41b6ac410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480196134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2480196134
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1202084684
Short name T948
Test name
Test status
Simulation time 1270566598 ps
CPU time 15.36 seconds
Started Mar 09 04:54:04 PM PST 24
Finished Mar 09 04:54:19 PM PST 24
Peak memory 208408 kb
Host smart-edfec2e2-0baf-4392-a49b-31e9df3ae976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202084684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1202084684
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.4137794856
Short name T255
Test name
Test status
Simulation time 109400229 ps
CPU time 4.84 seconds
Started Mar 09 04:54:21 PM PST 24
Finished Mar 09 04:54:26 PM PST 24
Peak memory 214280 kb
Host smart-e285ebe8-ea96-4540-938d-a19829f3cfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137794856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.4137794856
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2025053392
Short name T58
Test name
Test status
Simulation time 184376093 ps
CPU time 5.96 seconds
Started Mar 09 04:54:09 PM PST 24
Finished Mar 09 04:54:25 PM PST 24
Peak memory 210392 kb
Host smart-b1e4d444-31ed-4559-a89e-759bfaba4969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025053392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2025053392
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3970322404
Short name T731
Test name
Test status
Simulation time 318263650 ps
CPU time 8.89 seconds
Started Mar 09 04:54:27 PM PST 24
Finished Mar 09 04:54:37 PM PST 24
Peak memory 214376 kb
Host smart-b21f0770-ce47-49c8-8ae8-4d26580b4067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970322404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3970322404
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3590660267
Short name T675
Test name
Test status
Simulation time 344199118 ps
CPU time 2.58 seconds
Started Mar 09 04:54:04 PM PST 24
Finished Mar 09 04:54:07 PM PST 24
Peak memory 207396 kb
Host smart-5fa1d77a-0c7c-4c49-ae33-983795483380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590660267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3590660267
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3690539124
Short name T36
Test name
Test status
Simulation time 251348329 ps
CPU time 7.13 seconds
Started Mar 09 04:54:00 PM PST 24
Finished Mar 09 04:54:07 PM PST 24
Peak memory 208516 kb
Host smart-0c069996-752a-4977-8e21-c40782fbfe3f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690539124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3690539124
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.563236255
Short name T861
Test name
Test status
Simulation time 60798675 ps
CPU time 3.01 seconds
Started Mar 09 04:54:04 PM PST 24
Finished Mar 09 04:54:07 PM PST 24
Peak memory 208260 kb
Host smart-6592b940-aa02-403a-aa19-e6476cbe8b3f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563236255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.563236255
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1170815015
Short name T1060
Test name
Test status
Simulation time 897861694 ps
CPU time 4.88 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:54:03 PM PST 24
Peak memory 208540 kb
Host smart-6d7ea9d6-9a51-4126-b02b-317d9065f605
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170815015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1170815015
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3069650125
Short name T35
Test name
Test status
Simulation time 172073636 ps
CPU time 3.17 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 208064 kb
Host smart-0586c228-bf6b-4d6f-9564-5d4e39c66339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069650125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3069650125
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3105309258
Short name T387
Test name
Test status
Simulation time 4963236288 ps
CPU time 44.38 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:40 PM PST 24
Peak memory 208996 kb
Host smart-53f1ee41-5dd2-4b5e-a598-58632b426c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105309258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3105309258
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2325245246
Short name T893
Test name
Test status
Simulation time 85258840 ps
CPU time 5.51 seconds
Started Mar 09 04:54:16 PM PST 24
Finished Mar 09 04:54:22 PM PST 24
Peak memory 222632 kb
Host smart-85dbebb0-266f-4a5d-bf93-6a2f039eb3a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325245246 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2325245246
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2982777820
Short name T237
Test name
Test status
Simulation time 459017881 ps
CPU time 10.15 seconds
Started Mar 09 04:54:09 PM PST 24
Finished Mar 09 04:54:20 PM PST 24
Peak memory 214276 kb
Host smart-f9e7a0cf-605e-4af4-a8ba-402a3f0bc06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982777820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2982777820
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3380682601
Short name T1039
Test name
Test status
Simulation time 50779693 ps
CPU time 1.67 seconds
Started Mar 09 04:54:13 PM PST 24
Finished Mar 09 04:54:15 PM PST 24
Peak memory 209960 kb
Host smart-00282e92-cb7b-4b15-b593-4d68b65407be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380682601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3380682601
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1149096167
Short name T763
Test name
Test status
Simulation time 23862356 ps
CPU time 0.79 seconds
Started Mar 09 04:54:15 PM PST 24
Finished Mar 09 04:54:17 PM PST 24
Peak memory 205880 kb
Host smart-7298cdd4-a9f8-46ba-a2a8-01b2cb7556aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149096167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1149096167
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3590646685
Short name T998
Test name
Test status
Simulation time 140915518 ps
CPU time 3.74 seconds
Started Mar 09 04:54:00 PM PST 24
Finished Mar 09 04:54:04 PM PST 24
Peak memory 222520 kb
Host smart-6e99ff3c-92f0-4384-9cd8-09e62b47629e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590646685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3590646685
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2248524593
Short name T88
Test name
Test status
Simulation time 99165676 ps
CPU time 4.42 seconds
Started Mar 09 04:54:09 PM PST 24
Finished Mar 09 04:54:13 PM PST 24
Peak memory 220712 kb
Host smart-fccca876-6c1b-433b-aa70-1380efdd55eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248524593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2248524593
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1992700472
Short name T340
Test name
Test status
Simulation time 164122299 ps
CPU time 3.63 seconds
Started Mar 09 04:54:11 PM PST 24
Finished Mar 09 04:54:14 PM PST 24
Peak memory 211392 kb
Host smart-c201e5ca-d4e4-4f90-9e65-7e66267f86de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992700472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1992700472
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3105395706
Short name T45
Test name
Test status
Simulation time 104669159 ps
CPU time 3.26 seconds
Started Mar 09 04:54:08 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 214508 kb
Host smart-a64576b5-5c36-455d-8946-cf18b6747b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105395706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3105395706
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3841486280
Short name T909
Test name
Test status
Simulation time 41845806 ps
CPU time 3 seconds
Started Mar 09 04:54:30 PM PST 24
Finished Mar 09 04:54:33 PM PST 24
Peak memory 218256 kb
Host smart-436458d1-fad2-468f-9dfb-8f8e3cda1f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841486280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3841486280
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2866444863
Short name T896
Test name
Test status
Simulation time 233757046 ps
CPU time 4.24 seconds
Started Mar 09 04:54:16 PM PST 24
Finished Mar 09 04:54:20 PM PST 24
Peak memory 206684 kb
Host smart-654f7e4d-b2e2-4657-94d1-048e4d95f1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866444863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2866444863
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.252138782
Short name T357
Test name
Test status
Simulation time 229610409 ps
CPU time 8.3 seconds
Started Mar 09 04:54:34 PM PST 24
Finished Mar 09 04:54:43 PM PST 24
Peak memory 207968 kb
Host smart-b0107378-7554-4161-8d38-fa297ef017d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252138782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.252138782
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3576869474
Short name T963
Test name
Test status
Simulation time 3501057272 ps
CPU time 41.49 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:49 PM PST 24
Peak memory 208752 kb
Host smart-8f1f9503-147e-468f-9f44-fea900e67a3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576869474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3576869474
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.2074406141
Short name T979
Test name
Test status
Simulation time 190649223 ps
CPU time 2.63 seconds
Started Mar 09 04:54:21 PM PST 24
Finished Mar 09 04:54:23 PM PST 24
Peak memory 206952 kb
Host smart-cbaa0e5d-a423-4965-ab0f-601116c8a5e9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074406141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.2074406141
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1352895349
Short name T689
Test name
Test status
Simulation time 453683352 ps
CPU time 3.89 seconds
Started Mar 09 04:54:30 PM PST 24
Finished Mar 09 04:54:35 PM PST 24
Peak memory 215912 kb
Host smart-e51cd27f-3b11-43ff-b101-766e642ac320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352895349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1352895349
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1554785728
Short name T183
Test name
Test status
Simulation time 431284808 ps
CPU time 7.87 seconds
Started Mar 09 04:54:22 PM PST 24
Finished Mar 09 04:54:30 PM PST 24
Peak memory 206728 kb
Host smart-c80e38fd-a981-43d9-8fd7-1f8fa623df0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554785728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1554785728
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3657679512
Short name T705
Test name
Test status
Simulation time 302843048 ps
CPU time 13.41 seconds
Started Mar 09 04:54:18 PM PST 24
Finished Mar 09 04:54:31 PM PST 24
Peak memory 222588 kb
Host smart-f376aab5-2b2e-451c-87fb-1bd5998ff7c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657679512 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3657679512
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2945234338
Short name T892
Test name
Test status
Simulation time 38264135 ps
CPU time 2.84 seconds
Started Mar 09 04:54:10 PM PST 24
Finished Mar 09 04:54:13 PM PST 24
Peak memory 208332 kb
Host smart-60ffa87f-ab29-4857-a445-2a4059e112a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945234338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2945234338
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2700008818
Short name T854
Test name
Test status
Simulation time 54941574 ps
CPU time 1.62 seconds
Started Mar 09 04:54:09 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 209676 kb
Host smart-18cc578b-7915-41c9-893a-78baedd2ade1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700008818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2700008818
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.186604051
Short name T870
Test name
Test status
Simulation time 28180426 ps
CPU time 0.79 seconds
Started Mar 09 04:54:15 PM PST 24
Finished Mar 09 04:54:16 PM PST 24
Peak memory 205908 kb
Host smart-9d0ca116-385f-46ac-abb6-defd66ef95d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186604051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.186604051
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2303132137
Short name T60
Test name
Test status
Simulation time 249929854 ps
CPU time 8.16 seconds
Started Mar 09 04:54:29 PM PST 24
Finished Mar 09 04:54:38 PM PST 24
Peak memory 208924 kb
Host smart-17d6f400-d492-4bfd-a286-4c9d6d50f4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303132137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2303132137
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.469089839
Short name T91
Test name
Test status
Simulation time 282881746 ps
CPU time 5.63 seconds
Started Mar 09 04:54:12 PM PST 24
Finished Mar 09 04:54:18 PM PST 24
Peak memory 222376 kb
Host smart-e0304fe6-ea64-41a4-991a-1bccf418c0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469089839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.469089839
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.707998241
Short name T768
Test name
Test status
Simulation time 95125957 ps
CPU time 3.83 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 207324 kb
Host smart-198007e6-2a02-48e3-ab61-b91b6b346915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707998241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.707998241
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2208340587
Short name T585
Test name
Test status
Simulation time 1519508947 ps
CPU time 44.32 seconds
Started Mar 09 04:54:09 PM PST 24
Finished Mar 09 04:54:54 PM PST 24
Peak memory 209364 kb
Host smart-e87ecf67-8037-4961-b82a-717f0a51fbc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208340587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2208340587
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1952906295
Short name T587
Test name
Test status
Simulation time 58355616 ps
CPU time 2.28 seconds
Started Mar 09 04:54:08 PM PST 24
Finished Mar 09 04:54:10 PM PST 24
Peak memory 206744 kb
Host smart-640154c3-d550-4eaa-85dd-dbcdee3fca32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952906295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1952906295
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1704842128
Short name T813
Test name
Test status
Simulation time 63686636 ps
CPU time 2.75 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 206876 kb
Host smart-8f6fac90-dfbd-415c-851b-4c7d97c7d422
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704842128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1704842128
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2638323326
Short name T815
Test name
Test status
Simulation time 621645665 ps
CPU time 11.85 seconds
Started Mar 09 04:54:30 PM PST 24
Finished Mar 09 04:54:43 PM PST 24
Peak memory 207868 kb
Host smart-53d2be3a-ea41-47f8-8a91-385dac16fb79
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638323326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2638323326
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2612538715
Short name T1062
Test name
Test status
Simulation time 421756990 ps
CPU time 4.13 seconds
Started Mar 09 04:54:09 PM PST 24
Finished Mar 09 04:54:13 PM PST 24
Peak memory 206936 kb
Host smart-aadb6d75-50cb-451e-99d3-dccf3e659b4b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612538715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2612538715
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.4018569653
Short name T296
Test name
Test status
Simulation time 79269022 ps
CPU time 3.3 seconds
Started Mar 09 04:54:25 PM PST 24
Finished Mar 09 04:54:30 PM PST 24
Peak memory 209200 kb
Host smart-ae96c065-7d3d-487f-a1dc-07c673394c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018569653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.4018569653
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.318441106
Short name T102
Test name
Test status
Simulation time 406092537 ps
CPU time 2.99 seconds
Started Mar 09 04:54:19 PM PST 24
Finished Mar 09 04:54:22 PM PST 24
Peak memory 206728 kb
Host smart-6838dba5-4609-4507-acc5-84595824c091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318441106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.318441106
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3741206320
Short name T211
Test name
Test status
Simulation time 451831768 ps
CPU time 10.47 seconds
Started Mar 09 04:54:10 PM PST 24
Finished Mar 09 04:54:21 PM PST 24
Peak memory 220440 kb
Host smart-83655d52-f2d6-4579-9d2b-498168968d21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3741206320 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3741206320
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3119798729
Short name T417
Test name
Test status
Simulation time 1901285575 ps
CPU time 56.32 seconds
Started Mar 09 04:54:24 PM PST 24
Finished Mar 09 04:55:21 PM PST 24
Peak memory 214336 kb
Host smart-a3cf1954-3403-4036-b4db-1c5599345a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119798729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3119798729
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.21285035
Short name T52
Test name
Test status
Simulation time 846957800 ps
CPU time 8.07 seconds
Started Mar 09 04:54:16 PM PST 24
Finished Mar 09 04:54:25 PM PST 24
Peak memory 210840 kb
Host smart-e7a39aed-3c18-4fa7-af10-3d46d203f5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21285035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.21285035
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.408025161
Short name T559
Test name
Test status
Simulation time 11049966 ps
CPU time 0.73 seconds
Started Mar 09 04:54:41 PM PST 24
Finished Mar 09 04:54:42 PM PST 24
Peak memory 205868 kb
Host smart-c821bdc0-3002-41ae-94c5-340c9bbf85b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408025161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.408025161
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2581956966
Short name T25
Test name
Test status
Simulation time 159475789 ps
CPU time 6.41 seconds
Started Mar 09 04:54:24 PM PST 24
Finished Mar 09 04:54:32 PM PST 24
Peak memory 214692 kb
Host smart-b3fe6116-9a28-462c-9944-5c270466768b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581956966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2581956966
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.160120825
Short name T72
Test name
Test status
Simulation time 230247857 ps
CPU time 4.27 seconds
Started Mar 09 04:54:43 PM PST 24
Finished Mar 09 04:54:48 PM PST 24
Peak memory 207932 kb
Host smart-fca17d5d-bca4-4090-a5aa-44c5d434718c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160120825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.160120825
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.615983709
Short name T812
Test name
Test status
Simulation time 1764893630 ps
CPU time 12.19 seconds
Started Mar 09 04:54:17 PM PST 24
Finished Mar 09 04:54:30 PM PST 24
Peak memory 214440 kb
Host smart-63e69781-1cdd-4ae6-98dc-fc1b3f6328a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615983709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.615983709
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2439538736
Short name T942
Test name
Test status
Simulation time 255404907 ps
CPU time 7.48 seconds
Started Mar 09 04:54:15 PM PST 24
Finished Mar 09 04:54:23 PM PST 24
Peak memory 222464 kb
Host smart-6326bfe2-9263-4cbb-ad5f-059484322e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439538736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2439538736
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_random.2722995865
Short name T976
Test name
Test status
Simulation time 589336681 ps
CPU time 5.24 seconds
Started Mar 09 04:54:14 PM PST 24
Finished Mar 09 04:54:20 PM PST 24
Peak memory 207276 kb
Host smart-868c5297-3eb4-42f9-b965-e18dc9d6050a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722995865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2722995865
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3419848026
Short name T361
Test name
Test status
Simulation time 1047542471 ps
CPU time 8.01 seconds
Started Mar 09 04:54:28 PM PST 24
Finished Mar 09 04:54:37 PM PST 24
Peak memory 208520 kb
Host smart-fcb46c8c-b6d3-49e7-ab44-d5681d00f32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419848026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3419848026
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.1376240751
Short name T336
Test name
Test status
Simulation time 8421197955 ps
CPU time 59.27 seconds
Started Mar 09 04:54:18 PM PST 24
Finished Mar 09 04:55:18 PM PST 24
Peak memory 208228 kb
Host smart-5ccd5d03-b029-4939-9934-42910dc96046
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376240751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.1376240751
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.667126913
Short name T83
Test name
Test status
Simulation time 10207820384 ps
CPU time 70.21 seconds
Started Mar 09 04:54:34 PM PST 24
Finished Mar 09 04:55:45 PM PST 24
Peak memory 208672 kb
Host smart-d90f9402-7f98-4095-ace6-ac33ffdd36bb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667126913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.667126913
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2460890784
Short name T769
Test name
Test status
Simulation time 453218157 ps
CPU time 5.5 seconds
Started Mar 09 04:54:46 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 208468 kb
Host smart-09525f4c-f1cc-4341-b0d0-5c125d769e82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460890784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2460890784
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3580829482
Short name T292
Test name
Test status
Simulation time 387458046 ps
CPU time 7.65 seconds
Started Mar 09 04:54:26 PM PST 24
Finished Mar 09 04:54:35 PM PST 24
Peak memory 215632 kb
Host smart-9c3a2d07-d513-4f16-8064-57ae356e3a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580829482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3580829482
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3286149107
Short name T1071
Test name
Test status
Simulation time 163871594 ps
CPU time 6.07 seconds
Started Mar 09 04:54:15 PM PST 24
Finished Mar 09 04:54:21 PM PST 24
Peak memory 208240 kb
Host smart-0da4cf58-44fa-42f7-b041-e41493b1e672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286149107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3286149107
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.3111974126
Short name T203
Test name
Test status
Simulation time 656796240 ps
CPU time 4.97 seconds
Started Mar 09 04:54:34 PM PST 24
Finished Mar 09 04:54:40 PM PST 24
Peak memory 222692 kb
Host smart-46690f1f-0541-41d3-af2b-6555e367b981
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111974126 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.3111974126
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1431283171
Short name T309
Test name
Test status
Simulation time 844014276 ps
CPU time 6.47 seconds
Started Mar 09 04:54:14 PM PST 24
Finished Mar 09 04:54:22 PM PST 24
Peak memory 207632 kb
Host smart-75f9ff9f-4b29-4573-93fe-327ccad500e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431283171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1431283171
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3024898715
Short name T1028
Test name
Test status
Simulation time 76049566 ps
CPU time 3.24 seconds
Started Mar 09 04:54:21 PM PST 24
Finished Mar 09 04:54:25 PM PST 24
Peak memory 210360 kb
Host smart-c50eeb7c-83cb-444c-a345-3d0c0786b35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024898715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3024898715
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3465796419
Short name T618
Test name
Test status
Simulation time 15588766 ps
CPU time 0.99 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:48 PM PST 24
Peak memory 206024 kb
Host smart-1b09c64f-b99a-4564-9fad-0bd3675ec589
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465796419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3465796419
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3148119328
Short name T1030
Test name
Test status
Simulation time 106051614 ps
CPU time 3.16 seconds
Started Mar 09 04:54:32 PM PST 24
Finished Mar 09 04:54:37 PM PST 24
Peak memory 207468 kb
Host smart-e1d186f7-405a-4d73-baff-f000cb5f7e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148119328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3148119328
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.87210395
Short name T1032
Test name
Test status
Simulation time 46797311 ps
CPU time 2.25 seconds
Started Mar 09 04:54:18 PM PST 24
Finished Mar 09 04:54:20 PM PST 24
Peak memory 207728 kb
Host smart-d9625b8a-f3a4-4022-bf13-5c639faa7153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87210395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.87210395
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3852157904
Short name T626
Test name
Test status
Simulation time 69264025 ps
CPU time 3.75 seconds
Started Mar 09 04:54:15 PM PST 24
Finished Mar 09 04:54:19 PM PST 24
Peak memory 208560 kb
Host smart-6573dbca-560a-4c43-be11-7956ca3dd844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852157904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3852157904
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_sideload.192831878
Short name T867
Test name
Test status
Simulation time 661970300 ps
CPU time 7.88 seconds
Started Mar 09 04:54:16 PM PST 24
Finished Mar 09 04:54:24 PM PST 24
Peak memory 208284 kb
Host smart-81441d65-2b88-4a7e-b1a6-3e4ca477878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192831878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.192831878
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.552290622
Short name T634
Test name
Test status
Simulation time 3094540726 ps
CPU time 30.4 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:55:17 PM PST 24
Peak memory 208552 kb
Host smart-16e8d97c-2d4a-4642-ae6b-999f71dcd667
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552290622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.552290622
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2033420612
Short name T700
Test name
Test status
Simulation time 127162544 ps
CPU time 2.43 seconds
Started Mar 09 04:54:32 PM PST 24
Finished Mar 09 04:54:36 PM PST 24
Peak memory 206732 kb
Host smart-727b2fd0-9192-4b06-a961-5405db18b1ea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033420612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2033420612
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2286819630
Short name T616
Test name
Test status
Simulation time 41494179 ps
CPU time 1.83 seconds
Started Mar 09 04:54:41 PM PST 24
Finished Mar 09 04:54:43 PM PST 24
Peak memory 206784 kb
Host smart-8ee0750e-c449-40a1-a884-0415b5f1b8f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286819630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2286819630
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.377106343
Short name T195
Test name
Test status
Simulation time 384615253 ps
CPU time 4.62 seconds
Started Mar 09 04:54:46 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 207976 kb
Host smart-e6dd674f-ea57-4c96-98ea-9273a89abf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377106343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.377106343
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1515565907
Short name T782
Test name
Test status
Simulation time 4260484575 ps
CPU time 41.44 seconds
Started Mar 09 04:54:35 PM PST 24
Finished Mar 09 04:55:17 PM PST 24
Peak memory 207964 kb
Host smart-6867daad-451b-44d2-8ac3-85cb33090fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515565907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1515565907
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2007690645
Short name T220
Test name
Test status
Simulation time 209954889 ps
CPU time 6.93 seconds
Started Mar 09 04:54:31 PM PST 24
Finished Mar 09 04:54:40 PM PST 24
Peak memory 222552 kb
Host smart-7f54b80a-6f11-4f4d-816c-c2911de17ab4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007690645 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2007690645
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1256814230
Short name T876
Test name
Test status
Simulation time 233031342 ps
CPU time 6.05 seconds
Started Mar 09 04:54:15 PM PST 24
Finished Mar 09 04:54:21 PM PST 24
Peak memory 218364 kb
Host smart-bc880b1a-0ed9-4f5d-abc8-802511d42905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256814230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1256814230
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2037187594
Short name T153
Test name
Test status
Simulation time 42257341 ps
CPU time 1.69 seconds
Started Mar 09 04:54:30 PM PST 24
Finished Mar 09 04:54:33 PM PST 24
Peak memory 209696 kb
Host smart-d2dabb73-664e-491f-aee4-faf80725c110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037187594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2037187594
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.473582313
Short name T418
Test name
Test status
Simulation time 48461927 ps
CPU time 0.75 seconds
Started Mar 09 04:54:41 PM PST 24
Finished Mar 09 04:54:42 PM PST 24
Peak memory 205844 kb
Host smart-79463e21-9a66-4aa1-a78b-c79c4f5c87d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473582313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.473582313
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.4072767572
Short name T342
Test name
Test status
Simulation time 177926734 ps
CPU time 9.41 seconds
Started Mar 09 04:54:32 PM PST 24
Finished Mar 09 04:54:43 PM PST 24
Peak memory 215832 kb
Host smart-e03e3d2a-7155-495f-97ba-c6bf0b1178ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4072767572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.4072767572
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1330977220
Short name T66
Test name
Test status
Simulation time 573929562 ps
CPU time 12.3 seconds
Started Mar 09 04:54:36 PM PST 24
Finished Mar 09 04:54:48 PM PST 24
Peak memory 219632 kb
Host smart-632223b6-6454-433d-a417-813a0365b651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330977220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1330977220
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3053756094
Short name T327
Test name
Test status
Simulation time 458156242 ps
CPU time 3.9 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 214364 kb
Host smart-a33b29cd-ae9c-4427-a0eb-a16a555caeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053756094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3053756094
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2637543987
Short name T959
Test name
Test status
Simulation time 994221424 ps
CPU time 8.31 seconds
Started Mar 09 04:54:24 PM PST 24
Finished Mar 09 04:54:33 PM PST 24
Peak memory 222464 kb
Host smart-002a6f99-4faa-463a-8b26-0d9fb9eac24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637543987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2637543987
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_random.920397578
Short name T325
Test name
Test status
Simulation time 2766287922 ps
CPU time 38.45 seconds
Started Mar 09 04:54:17 PM PST 24
Finished Mar 09 04:54:55 PM PST 24
Peak memory 218876 kb
Host smart-1f3db5fa-ce13-495a-ad85-1499efa73dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920397578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.920397578
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.39706983
Short name T710
Test name
Test status
Simulation time 3962715946 ps
CPU time 34.78 seconds
Started Mar 09 04:54:18 PM PST 24
Finished Mar 09 04:54:53 PM PST 24
Peak memory 208412 kb
Host smart-7b74dfbb-020d-4720-825a-d5736c29f2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39706983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.39706983
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2811643653
Short name T589
Test name
Test status
Simulation time 286273483 ps
CPU time 4.87 seconds
Started Mar 09 04:54:18 PM PST 24
Finished Mar 09 04:54:24 PM PST 24
Peak memory 206924 kb
Host smart-974341fa-8838-436c-8bad-5e15c328b63e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811643653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2811643653
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3882447086
Short name T1007
Test name
Test status
Simulation time 22198581 ps
CPU time 2.01 seconds
Started Mar 09 04:54:19 PM PST 24
Finished Mar 09 04:54:21 PM PST 24
Peak memory 206808 kb
Host smart-80cd4427-fc61-4d33-a007-65c932b9bbb7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882447086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3882447086
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2360607530
Short name T579
Test name
Test status
Simulation time 133794392 ps
CPU time 5.06 seconds
Started Mar 09 04:54:35 PM PST 24
Finished Mar 09 04:54:41 PM PST 24
Peak memory 208804 kb
Host smart-2bbfa258-70ab-431f-8c97-2405b942fad7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360607530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2360607530
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1730894759
Short name T15
Test name
Test status
Simulation time 136834045 ps
CPU time 3.52 seconds
Started Mar 09 04:54:18 PM PST 24
Finished Mar 09 04:54:22 PM PST 24
Peak memory 209660 kb
Host smart-068b16ed-d0eb-43f8-b012-be3c4c09cc9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730894759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1730894759
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2471907177
Short name T104
Test name
Test status
Simulation time 2427901423 ps
CPU time 6.2 seconds
Started Mar 09 04:54:18 PM PST 24
Finished Mar 09 04:54:25 PM PST 24
Peak memory 206832 kb
Host smart-f29223d0-47c3-4a57-900d-63d80c635d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471907177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2471907177
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1747638157
Short name T1025
Test name
Test status
Simulation time 3151690152 ps
CPU time 41.03 seconds
Started Mar 09 04:54:20 PM PST 24
Finished Mar 09 04:55:02 PM PST 24
Peak memory 215912 kb
Host smart-131521b1-120d-4b9c-a6f3-f6b80d448015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747638157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1747638157
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3278443331
Short name T205
Test name
Test status
Simulation time 291508031 ps
CPU time 3.91 seconds
Started Mar 09 04:54:42 PM PST 24
Finished Mar 09 04:54:46 PM PST 24
Peak memory 222616 kb
Host smart-033e391c-dcff-43f5-a417-bc4e35b9bc6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278443331 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3278443331
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3089995042
Short name T302
Test name
Test status
Simulation time 207670545 ps
CPU time 4.76 seconds
Started Mar 09 04:54:17 PM PST 24
Finished Mar 09 04:54:22 PM PST 24
Peak memory 210184 kb
Host smart-d2404754-cff7-4aa6-a31c-a1cc26113725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089995042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3089995042
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3721696520
Short name T877
Test name
Test status
Simulation time 79055639 ps
CPU time 1.42 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 209808 kb
Host smart-acf3fd78-6be7-4833-9892-72897a21a97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721696520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3721696520
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1066822967
Short name T703
Test name
Test status
Simulation time 19204126 ps
CPU time 0.94 seconds
Started Mar 09 04:54:28 PM PST 24
Finished Mar 09 04:54:29 PM PST 24
Peak memory 206076 kb
Host smart-05011b43-fa9b-46de-8dfe-95bf7d37a076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066822967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1066822967
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3009897882
Short name T399
Test name
Test status
Simulation time 1478050526 ps
CPU time 63.36 seconds
Started Mar 09 04:54:46 PM PST 24
Finished Mar 09 04:55:50 PM PST 24
Peak memory 214492 kb
Host smart-3c51ff95-e286-4f16-912f-a7666b2bc62c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3009897882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3009897882
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.3978244168
Short name T604
Test name
Test status
Simulation time 169789634 ps
CPU time 4.46 seconds
Started Mar 09 04:54:37 PM PST 24
Finished Mar 09 04:54:42 PM PST 24
Peak memory 222748 kb
Host smart-3af722e9-b407-45d8-bff4-4c98e77df700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978244168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.3978244168
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3894189752
Short name T251
Test name
Test status
Simulation time 42715448 ps
CPU time 3.18 seconds
Started Mar 09 04:54:16 PM PST 24
Finished Mar 09 04:54:20 PM PST 24
Peak memory 209800 kb
Host smart-60161fd3-5e82-498b-a54a-a5911c9a03c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894189752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3894189752
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1873736262
Short name T649
Test name
Test status
Simulation time 69775983 ps
CPU time 2.59 seconds
Started Mar 09 04:54:44 PM PST 24
Finished Mar 09 04:54:47 PM PST 24
Peak memory 209060 kb
Host smart-6f428ce0-60b4-46cb-b8b7-17c41d2c0ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873736262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1873736262
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.107052496
Short name T714
Test name
Test status
Simulation time 403664332 ps
CPU time 5.2 seconds
Started Mar 09 04:54:25 PM PST 24
Finished Mar 09 04:54:30 PM PST 24
Peak memory 215760 kb
Host smart-1ccbb2d9-368f-44fa-9cd5-05f31cf167d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107052496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.107052496
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.963890613
Short name T931
Test name
Test status
Simulation time 769856545 ps
CPU time 6.58 seconds
Started Mar 09 04:54:21 PM PST 24
Finished Mar 09 04:54:28 PM PST 24
Peak memory 209932 kb
Host smart-5bb3a4dc-0878-4e3f-ad49-624343f1a61c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963890613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.963890613
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2076824695
Short name T729
Test name
Test status
Simulation time 213583270 ps
CPU time 3.38 seconds
Started Mar 09 04:54:37 PM PST 24
Finished Mar 09 04:54:40 PM PST 24
Peak memory 207356 kb
Host smart-4ac3877a-969e-45e3-8d1f-41749bb7f776
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076824695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2076824695
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3086906924
Short name T900
Test name
Test status
Simulation time 429311151 ps
CPU time 4.12 seconds
Started Mar 09 04:54:18 PM PST 24
Finished Mar 09 04:54:22 PM PST 24
Peak memory 208768 kb
Host smart-3238ded1-93bb-4509-9f33-4f1dc6f6fe4a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086906924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3086906924
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2450337529
Short name T995
Test name
Test status
Simulation time 42925202 ps
CPU time 2.55 seconds
Started Mar 09 04:54:43 PM PST 24
Finished Mar 09 04:54:46 PM PST 24
Peak memory 206984 kb
Host smart-ff134cc8-2e9f-4dc3-8b59-048316bff9bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450337529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2450337529
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.685393723
Short name T819
Test name
Test status
Simulation time 548239236 ps
CPU time 6.62 seconds
Started Mar 09 04:54:41 PM PST 24
Finished Mar 09 04:54:48 PM PST 24
Peak memory 208692 kb
Host smart-50c4e946-0ce5-44d8-9e25-4dce4a84f0f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685393723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.685393723
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3420789734
Short name T653
Test name
Test status
Simulation time 123371164 ps
CPU time 1.91 seconds
Started Mar 09 04:54:41 PM PST 24
Finished Mar 09 04:54:43 PM PST 24
Peak memory 215980 kb
Host smart-b265d7bb-bfef-48e8-8736-528a7a9a669a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420789734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3420789734
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2984598339
Short name T905
Test name
Test status
Simulation time 104346300 ps
CPU time 3.28 seconds
Started Mar 09 04:54:30 PM PST 24
Finished Mar 09 04:54:38 PM PST 24
Peak memory 208716 kb
Host smart-36209d56-01ab-4d09-9607-92dbdfd4eb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984598339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2984598339
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.135775633
Short name T826
Test name
Test status
Simulation time 107142036 ps
CPU time 3.42 seconds
Started Mar 09 04:54:22 PM PST 24
Finished Mar 09 04:54:26 PM PST 24
Peak memory 208548 kb
Host smart-cf95143b-f592-4f62-98c9-ea29488d525f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135775633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.135775633
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.4181980643
Short name T690
Test name
Test status
Simulation time 170426561 ps
CPU time 3.19 seconds
Started Mar 09 04:54:17 PM PST 24
Finished Mar 09 04:54:21 PM PST 24
Peak memory 206852 kb
Host smart-dbb0fbf7-3d47-4170-aa60-7ba86a2776d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181980643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.4181980643
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.4238615035
Short name T1000
Test name
Test status
Simulation time 704631024 ps
CPU time 15.81 seconds
Started Mar 09 04:54:27 PM PST 24
Finished Mar 09 04:54:44 PM PST 24
Peak memory 210988 kb
Host smart-a1854e93-01bb-4602-b8e3-48b9cc944518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238615035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.4238615035
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3117194259
Short name T632
Test name
Test status
Simulation time 106066584 ps
CPU time 0.77 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:49 PM PST 24
Peak memory 205828 kb
Host smart-f1383e1f-bb55-4c75-ba23-aa1fdd91dcd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117194259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3117194259
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3384369785
Short name T1045
Test name
Test status
Simulation time 702811766 ps
CPU time 2.45 seconds
Started Mar 09 04:54:34 PM PST 24
Finished Mar 09 04:54:38 PM PST 24
Peak memory 209632 kb
Host smart-e9fd476c-02e0-40ea-8ac7-b22f2918b5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384369785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3384369785
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3866345864
Short name T733
Test name
Test status
Simulation time 294802614 ps
CPU time 4.65 seconds
Started Mar 09 04:54:30 PM PST 24
Finished Mar 09 04:54:36 PM PST 24
Peak memory 214308 kb
Host smart-bc9bf941-aabf-4af6-ac96-69bf0154ecd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866345864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3866345864
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3458904035
Short name T1066
Test name
Test status
Simulation time 32759447 ps
CPU time 2.43 seconds
Started Mar 09 04:54:28 PM PST 24
Finished Mar 09 04:54:31 PM PST 24
Peak memory 209004 kb
Host smart-8376835d-db8f-426f-8dd7-f430344caf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458904035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3458904035
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3666144757
Short name T868
Test name
Test status
Simulation time 179896038 ps
CPU time 7.67 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:55 PM PST 24
Peak memory 209272 kb
Host smart-f5a8afde-2244-476d-9db5-66c9cdae3340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666144757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3666144757
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3764005219
Short name T297
Test name
Test status
Simulation time 39841958 ps
CPU time 2.92 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 214200 kb
Host smart-1ca06290-ba2f-43bc-8629-eba84acca23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764005219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3764005219
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.597708751
Short name T903
Test name
Test status
Simulation time 100456000 ps
CPU time 2.09 seconds
Started Mar 09 04:54:57 PM PST 24
Finished Mar 09 04:54:59 PM PST 24
Peak memory 208436 kb
Host smart-13ed4eeb-2c9d-4370-bfdc-045b63efe864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597708751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.597708751
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1638840197
Short name T650
Test name
Test status
Simulation time 126136434 ps
CPU time 3.28 seconds
Started Mar 09 04:54:51 PM PST 24
Finished Mar 09 04:54:55 PM PST 24
Peak memory 208676 kb
Host smart-31099913-9dea-4e4b-95bc-53ee5a90505f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638840197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1638840197
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3106227445
Short name T1
Test name
Test status
Simulation time 100671307 ps
CPU time 3.92 seconds
Started Mar 09 04:54:46 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 206856 kb
Host smart-cdd63793-907f-423e-be77-4a32892a1095
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106227445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3106227445
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3746885912
Short name T816
Test name
Test status
Simulation time 69593301 ps
CPU time 2.98 seconds
Started Mar 09 04:54:36 PM PST 24
Finished Mar 09 04:54:39 PM PST 24
Peak memory 208096 kb
Host smart-86a4402f-2a2d-4307-bead-e2a51ea8435b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746885912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3746885912
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1083948158
Short name T14
Test name
Test status
Simulation time 67272568 ps
CPU time 3.01 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 208944 kb
Host smart-92e90cbf-9fe6-428b-a23b-a8d32ea932da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083948158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1083948158
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.4150907380
Short name T122
Test name
Test status
Simulation time 4170545148 ps
CPU time 38.42 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:55:26 PM PST 24
Peak memory 208488 kb
Host smart-dafc0992-0a87-45c0-88ee-08e16ce326cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150907380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.4150907380
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3281215925
Short name T680
Test name
Test status
Simulation time 92973493 ps
CPU time 3.05 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:53 PM PST 24
Peak memory 222656 kb
Host smart-de2de8f1-66f7-414e-965f-885188bea3f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281215925 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3281215925
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.790368432
Short name T910
Test name
Test status
Simulation time 113855664 ps
CPU time 4.58 seconds
Started Mar 09 04:54:45 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 214336 kb
Host smart-f2972839-9b27-48b7-ac21-24c3233276fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790368432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.790368432
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2899523240
Short name T623
Test name
Test status
Simulation time 27928350 ps
CPU time 0.82 seconds
Started Mar 09 04:54:44 PM PST 24
Finished Mar 09 04:54:44 PM PST 24
Peak memory 205904 kb
Host smart-7e30cdf0-9fb4-4a72-96c9-e6af75f4e69b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899523240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2899523240
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1313765451
Short name T406
Test name
Test status
Simulation time 534418037 ps
CPU time 15.28 seconds
Started Mar 09 04:54:30 PM PST 24
Finished Mar 09 04:54:46 PM PST 24
Peak memory 214612 kb
Host smart-cb7c4a73-ab47-4a85-bdfd-e48559df583e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1313765451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1313765451
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.4199632684
Short name T760
Test name
Test status
Simulation time 781932624 ps
CPU time 3.47 seconds
Started Mar 09 04:54:33 PM PST 24
Finished Mar 09 04:54:38 PM PST 24
Peak memory 209748 kb
Host smart-5efb1ee1-3495-45ae-b447-8cb7901a5037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199632684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.4199632684
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1130979514
Short name T943
Test name
Test status
Simulation time 314558330 ps
CPU time 3.22 seconds
Started Mar 09 04:54:32 PM PST 24
Finished Mar 09 04:54:36 PM PST 24
Peak memory 209080 kb
Host smart-41696c72-045e-4db0-8877-5fef5a187739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130979514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1130979514
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2568091215
Short name T189
Test name
Test status
Simulation time 110798784 ps
CPU time 4.59 seconds
Started Mar 09 04:54:32 PM PST 24
Finished Mar 09 04:54:39 PM PST 24
Peak memory 209928 kb
Host smart-c267e1b3-c7f6-4522-a710-0fafdd71e954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568091215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2568091215
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.332783382
Short name T997
Test name
Test status
Simulation time 484448799 ps
CPU time 4.41 seconds
Started Mar 09 04:54:30 PM PST 24
Finished Mar 09 04:54:35 PM PST 24
Peak memory 208708 kb
Host smart-b569fe66-59b5-4654-b9f9-0dbbf2fde308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332783382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.332783382
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.216043286
Short name T319
Test name
Test status
Simulation time 391689340 ps
CPU time 5.22 seconds
Started Mar 09 04:54:31 PM PST 24
Finished Mar 09 04:54:40 PM PST 24
Peak memory 207496 kb
Host smart-ec6737ce-e20d-4c84-903e-c841ef0cdc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216043286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.216043286
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.4100918769
Short name T934
Test name
Test status
Simulation time 202280141 ps
CPU time 3.04 seconds
Started Mar 09 04:54:31 PM PST 24
Finished Mar 09 04:54:35 PM PST 24
Peak memory 208628 kb
Host smart-e0941535-8a87-4f3d-a2d5-4101ab15185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100918769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.4100918769
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.419332802
Short name T691
Test name
Test status
Simulation time 964486125 ps
CPU time 32.49 seconds
Started Mar 09 04:54:52 PM PST 24
Finished Mar 09 04:55:24 PM PST 24
Peak memory 207936 kb
Host smart-282e2812-6bb7-4238-b923-1ed6d80447cd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419332802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.419332802
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.4020015664
Short name T603
Test name
Test status
Simulation time 51087141 ps
CPU time 2.34 seconds
Started Mar 09 04:54:32 PM PST 24
Finished Mar 09 04:54:37 PM PST 24
Peak memory 206888 kb
Host smart-9d96e9d2-5a31-440c-8d67-5a3121af7698
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020015664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.4020015664
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2472950733
Short name T805
Test name
Test status
Simulation time 56884310 ps
CPU time 2.94 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 206956 kb
Host smart-711206c0-c89c-4126-a707-43ce535d6c79
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472950733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2472950733
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2873463797
Short name T701
Test name
Test status
Simulation time 188925595 ps
CPU time 6.62 seconds
Started Mar 09 04:54:32 PM PST 24
Finished Mar 09 04:54:40 PM PST 24
Peak memory 208208 kb
Host smart-3f59db7a-d2c5-42a4-8eda-77da5de231c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873463797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2873463797
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2046357911
Short name T556
Test name
Test status
Simulation time 36055884 ps
CPU time 2.51 seconds
Started Mar 09 04:54:27 PM PST 24
Finished Mar 09 04:54:30 PM PST 24
Peak memory 206672 kb
Host smart-39ebde32-9df4-4ef9-9660-96d78e89584f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046357911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2046357911
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.199150180
Short name T50
Test name
Test status
Simulation time 1370339727 ps
CPU time 42.09 seconds
Started Mar 09 04:54:42 PM PST 24
Finished Mar 09 04:55:24 PM PST 24
Peak memory 216900 kb
Host smart-26106876-05a6-4359-8480-704a382034e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199150180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.199150180
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3919423852
Short name T845
Test name
Test status
Simulation time 638765141 ps
CPU time 7.07 seconds
Started Mar 09 04:54:37 PM PST 24
Finished Mar 09 04:54:45 PM PST 24
Peak memory 222640 kb
Host smart-0eac3bda-cba9-46ea-bac5-2f0d18298be5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919423852 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3919423852
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.4030453636
Short name T82
Test name
Test status
Simulation time 2296920579 ps
CPU time 71.9 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:56:02 PM PST 24
Peak memory 220540 kb
Host smart-90ea850f-6ba1-4123-9322-e5bfaa8fede2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030453636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.4030453636
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3770261514
Short name T832
Test name
Test status
Simulation time 692256663 ps
CPU time 19.22 seconds
Started Mar 09 04:54:33 PM PST 24
Finished Mar 09 04:54:54 PM PST 24
Peak memory 211060 kb
Host smart-04a1cd9b-f62e-4518-b45b-4e19479cc8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770261514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3770261514
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1891249702
Short name T79
Test name
Test status
Simulation time 74150386 ps
CPU time 0.93 seconds
Started Mar 09 04:53:40 PM PST 24
Finished Mar 09 04:53:41 PM PST 24
Peak memory 206044 kb
Host smart-9f3f8d5f-0e3f-4e9a-86c3-146d78a344d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891249702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1891249702
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2802937164
Short name T356
Test name
Test status
Simulation time 30437901 ps
CPU time 2.55 seconds
Started Mar 09 04:53:47 PM PST 24
Finished Mar 09 04:53:50 PM PST 24
Peak memory 214336 kb
Host smart-7de0f4a4-000d-4111-b23b-b33058ca1130
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2802937164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2802937164
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1401239796
Short name T23
Test name
Test status
Simulation time 196378496 ps
CPU time 2.14 seconds
Started Mar 09 04:53:31 PM PST 24
Finished Mar 09 04:53:33 PM PST 24
Peak memory 218484 kb
Host smart-0180de59-3a5b-42e6-b738-60c521cdc527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401239796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1401239796
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1921902392
Short name T728
Test name
Test status
Simulation time 27065772 ps
CPU time 1.89 seconds
Started Mar 09 04:53:22 PM PST 24
Finished Mar 09 04:53:24 PM PST 24
Peak memory 208224 kb
Host smart-73cf54ad-3e8d-4874-8021-18d41fe26098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921902392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1921902392
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2487998938
Short name T860
Test name
Test status
Simulation time 318861719 ps
CPU time 4.28 seconds
Started Mar 09 04:53:41 PM PST 24
Finished Mar 09 04:53:46 PM PST 24
Peak memory 214328 kb
Host smart-8e4e74fb-8fca-4acb-81eb-558fbd057eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487998938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2487998938
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2729310255
Short name T281
Test name
Test status
Simulation time 164887717 ps
CPU time 2.97 seconds
Started Mar 09 04:53:20 PM PST 24
Finished Mar 09 04:53:23 PM PST 24
Peak memory 214272 kb
Host smart-a124b34f-48ec-4714-a823-532c7c807cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729310255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2729310255
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1196023985
Short name T215
Test name
Test status
Simulation time 219978032 ps
CPU time 3.73 seconds
Started Mar 09 04:53:22 PM PST 24
Finished Mar 09 04:53:26 PM PST 24
Peak memory 208952 kb
Host smart-00c83d84-64e1-4c46-8ee6-cd2745f9c723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196023985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1196023985
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2655432184
Short name T583
Test name
Test status
Simulation time 114575822 ps
CPU time 4.44 seconds
Started Mar 09 04:53:44 PM PST 24
Finished Mar 09 04:53:49 PM PST 24
Peak memory 206904 kb
Host smart-c4198d9e-e98a-4367-9a2c-a1993df42cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655432184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2655432184
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1868367702
Short name T97
Test name
Test status
Simulation time 1123472224 ps
CPU time 17.52 seconds
Started Mar 09 04:53:42 PM PST 24
Finished Mar 09 04:54:00 PM PST 24
Peak memory 232708 kb
Host smart-44253d19-6c78-4d93-abfc-95c641862bbe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868367702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1868367702
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1700861032
Short name T972
Test name
Test status
Simulation time 44463707 ps
CPU time 2.78 seconds
Started Mar 09 04:53:42 PM PST 24
Finished Mar 09 04:53:45 PM PST 24
Peak memory 208752 kb
Host smart-358525b7-95e4-4bc7-89b9-ff899f4b9d4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700861032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1700861032
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.4237406614
Short name T802
Test name
Test status
Simulation time 39500200 ps
CPU time 2.34 seconds
Started Mar 09 04:53:47 PM PST 24
Finished Mar 09 04:53:50 PM PST 24
Peak memory 206956 kb
Host smart-b9e99f1b-53fd-4e16-bf1b-0b19068e1055
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237406614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.4237406614
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1748507863
Short name T1065
Test name
Test status
Simulation time 175747104 ps
CPU time 4.83 seconds
Started Mar 09 04:53:18 PM PST 24
Finished Mar 09 04:53:23 PM PST 24
Peak memory 208008 kb
Host smart-0773fa6b-065d-47ef-8b0d-ff5d13c66971
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748507863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1748507863
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2161431921
Short name T829
Test name
Test status
Simulation time 604031834 ps
CPU time 16.23 seconds
Started Mar 09 04:53:43 PM PST 24
Finished Mar 09 04:54:00 PM PST 24
Peak memory 208036 kb
Host smart-a0adcd7e-412e-48f2-9e31-be395cf7082a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161431921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2161431921
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.4039797798
Short name T762
Test name
Test status
Simulation time 499525650 ps
CPU time 14.18 seconds
Started Mar 09 04:53:39 PM PST 24
Finished Mar 09 04:53:53 PM PST 24
Peak memory 209316 kb
Host smart-ea1bd213-7ea2-406a-9752-9c8a4a70e4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039797798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4039797798
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1533274600
Short name T891
Test name
Test status
Simulation time 3262560720 ps
CPU time 10.69 seconds
Started Mar 09 04:53:45 PM PST 24
Finished Mar 09 04:53:56 PM PST 24
Peak memory 208064 kb
Host smart-e48b87ab-6bfe-4c1f-bb33-64d3b935340a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533274600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1533274600
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.582380289
Short name T912
Test name
Test status
Simulation time 603002649 ps
CPU time 24.3 seconds
Started Mar 09 04:53:29 PM PST 24
Finished Mar 09 04:53:53 PM PST 24
Peak memory 222476 kb
Host smart-5fd573aa-e947-41b4-9d85-a58852cb7ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582380289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.582380289
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.798006362
Short name T619
Test name
Test status
Simulation time 808013544 ps
CPU time 4.87 seconds
Started Mar 09 04:53:33 PM PST 24
Finished Mar 09 04:53:38 PM PST 24
Peak memory 222668 kb
Host smart-01d10eb0-1ee4-473a-affa-af01bf5a60b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798006362 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.798006362
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1130679654
Short name T1058
Test name
Test status
Simulation time 178897143 ps
CPU time 3.17 seconds
Started Mar 09 04:53:43 PM PST 24
Finished Mar 09 04:53:47 PM PST 24
Peak memory 207196 kb
Host smart-70248827-fc4e-45ee-ab7c-9097633d09ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130679654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1130679654
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.6903241
Short name T578
Test name
Test status
Simulation time 157866393 ps
CPU time 2.51 seconds
Started Mar 09 04:53:38 PM PST 24
Finished Mar 09 04:53:41 PM PST 24
Peak memory 210400 kb
Host smart-0199a220-a222-476d-b358-8ab1ac957a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6903241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.6903241
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.57443783
Short name T871
Test name
Test status
Simulation time 36237535 ps
CPU time 0.72 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:48 PM PST 24
Peak memory 205896 kb
Host smart-25209888-77eb-4549-b07f-e42cf77a9e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57443783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.57443783
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1514066276
Short name T10
Test name
Test status
Simulation time 10944909574 ps
CPU time 32 seconds
Started Mar 09 04:54:35 PM PST 24
Finished Mar 09 04:55:07 PM PST 24
Peak memory 214572 kb
Host smart-2402fc4f-7179-4b90-a5e4-6e8fb5a7c222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514066276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1514066276
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2690874047
Short name T717
Test name
Test status
Simulation time 5735378541 ps
CPU time 16.74 seconds
Started Mar 09 04:54:32 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 208988 kb
Host smart-5f9f08a8-9c08-42be-b423-ce7bb2141090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690874047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2690874047
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.428059073
Short name T373
Test name
Test status
Simulation time 22315056678 ps
CPU time 64.89 seconds
Started Mar 09 04:54:33 PM PST 24
Finished Mar 09 04:55:39 PM PST 24
Peak memory 227176 kb
Host smart-b8c97727-6d2e-48fd-aa0b-20f2a33e92b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428059073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.428059073
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.2174427516
Short name T743
Test name
Test status
Simulation time 164427602 ps
CPU time 1.99 seconds
Started Mar 09 04:54:39 PM PST 24
Finished Mar 09 04:54:41 PM PST 24
Peak memory 215636 kb
Host smart-d8f4e45d-c009-4b3b-8b15-75a0e6c96344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174427516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.2174427516
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.4121826069
Short name T344
Test name
Test status
Simulation time 288300840 ps
CPU time 3.92 seconds
Started Mar 09 04:54:44 PM PST 24
Finished Mar 09 04:54:48 PM PST 24
Peak memory 210048 kb
Host smart-6e32a60f-ceab-4f70-bb3f-c600169e78da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121826069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.4121826069
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.972237192
Short name T625
Test name
Test status
Simulation time 69609030 ps
CPU time 3.49 seconds
Started Mar 09 04:54:33 PM PST 24
Finished Mar 09 04:54:38 PM PST 24
Peak memory 208288 kb
Host smart-84f730a5-e4ae-46a7-9271-641bf308e959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972237192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.972237192
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.251508012
Short name T84
Test name
Test status
Simulation time 193099535 ps
CPU time 2.94 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 208460 kb
Host smart-1a6bd0ff-5222-4b1e-a952-100cef7bfeb7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251508012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.251508012
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2998378123
Short name T185
Test name
Test status
Simulation time 211919647 ps
CPU time 6.61 seconds
Started Mar 09 04:54:31 PM PST 24
Finished Mar 09 04:54:40 PM PST 24
Peak memory 208144 kb
Host smart-66854940-e5c6-4bbe-853a-acddfb733f99
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998378123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2998378123
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3740804711
Short name T899
Test name
Test status
Simulation time 74198552 ps
CPU time 3.68 seconds
Started Mar 09 04:54:36 PM PST 24
Finished Mar 09 04:54:39 PM PST 24
Peak memory 208812 kb
Host smart-60b0950d-1440-47c8-92d9-679d41b63717
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740804711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3740804711
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.598028465
Short name T692
Test name
Test status
Simulation time 2018427534 ps
CPU time 19.63 seconds
Started Mar 09 04:54:32 PM PST 24
Finished Mar 09 04:54:54 PM PST 24
Peak memory 208356 kb
Host smart-0b5e5304-23e7-46a5-a26b-7c02b286c60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598028465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.598028465
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.4184372519
Short name T787
Test name
Test status
Simulation time 687216380 ps
CPU time 7.95 seconds
Started Mar 09 04:54:45 PM PST 24
Finished Mar 09 04:54:53 PM PST 24
Peak memory 206352 kb
Host smart-41b62dd4-3517-4256-823b-bcab1285cc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184372519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.4184372519
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1116596080
Short name T929
Test name
Test status
Simulation time 129345322 ps
CPU time 4.9 seconds
Started Mar 09 04:54:41 PM PST 24
Finished Mar 09 04:54:46 PM PST 24
Peak memory 210296 kb
Host smart-b5d4fdc7-f50e-4b3c-8be3-0dd711a68aa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116596080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1116596080
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2974205069
Short name T740
Test name
Test status
Simulation time 120043483 ps
CPU time 7.17 seconds
Started Mar 09 04:54:55 PM PST 24
Finished Mar 09 04:55:02 PM PST 24
Peak memory 222628 kb
Host smart-2aa700ea-7acc-412d-ba37-3e49af8cf055
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974205069 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2974205069
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.987352311
Short name T276
Test name
Test status
Simulation time 140749453 ps
CPU time 2.97 seconds
Started Mar 09 04:55:04 PM PST 24
Finished Mar 09 04:55:07 PM PST 24
Peak memory 208244 kb
Host smart-e6624d00-0fd3-47e9-bd9c-5b4dd827d6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987352311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.987352311
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2532138065
Short name T855
Test name
Test status
Simulation time 556795329 ps
CPU time 2.39 seconds
Started Mar 09 04:54:56 PM PST 24
Finished Mar 09 04:54:58 PM PST 24
Peak memory 209896 kb
Host smart-7d86288b-8f79-4038-ad39-8ac4f747efda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532138065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2532138065
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.490890348
Short name T94
Test name
Test status
Simulation time 15300738 ps
CPU time 0.79 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 205904 kb
Host smart-9cb2d025-3a2e-41b9-a86b-9a064207a578
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490890348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.490890348
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1802737105
Short name T352
Test name
Test status
Simulation time 52546734 ps
CPU time 3.83 seconds
Started Mar 09 04:54:40 PM PST 24
Finished Mar 09 04:54:44 PM PST 24
Peak memory 215224 kb
Host smart-fa025034-8ce6-4196-a28a-d46e6913b7da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1802737105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1802737105
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.674290773
Short name T51
Test name
Test status
Simulation time 62492047 ps
CPU time 2.49 seconds
Started Mar 09 04:54:32 PM PST 24
Finished Mar 09 04:54:36 PM PST 24
Peak memory 208524 kb
Host smart-78489103-0e79-4e66-93a3-55b30f47e9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674290773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.674290773
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.652854455
Short name T92
Test name
Test status
Simulation time 331246686 ps
CPU time 3.93 seconds
Started Mar 09 04:54:56 PM PST 24
Finished Mar 09 04:55:00 PM PST 24
Peak memory 209608 kb
Host smart-d1b059b6-f62a-4fcb-81f1-e2f63d77217d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652854455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.652854455
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.635133509
Short name T1027
Test name
Test status
Simulation time 127384071 ps
CPU time 3.14 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 209928 kb
Host smart-523ce37e-b92e-4b71-b8a5-c3a39be693f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635133509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.635133509
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.4151766926
Short name T978
Test name
Test status
Simulation time 166612128 ps
CPU time 4.44 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 214400 kb
Host smart-61b800b2-7ddc-46a6-bd87-05ab9984a134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151766926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.4151766926
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2333208995
Short name T866
Test name
Test status
Simulation time 54787376 ps
CPU time 2.6 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 206904 kb
Host smart-96ada4e6-e284-48de-b89c-11b44204eeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333208995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2333208995
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1086762493
Short name T930
Test name
Test status
Simulation time 1465145669 ps
CPU time 19.73 seconds
Started Mar 09 04:54:51 PM PST 24
Finished Mar 09 04:55:11 PM PST 24
Peak memory 207980 kb
Host smart-387c3246-cc46-43dc-84c3-da50e63d6046
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086762493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1086762493
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1924511803
Short name T289
Test name
Test status
Simulation time 53055135 ps
CPU time 2.04 seconds
Started Mar 09 04:54:41 PM PST 24
Finished Mar 09 04:54:43 PM PST 24
Peak memory 208372 kb
Host smart-2d8b85bf-8da3-43c3-9dbf-83d1d228b7ea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924511803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1924511803
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2348518847
Short name T897
Test name
Test status
Simulation time 161961926 ps
CPU time 3.12 seconds
Started Mar 09 04:54:33 PM PST 24
Finished Mar 09 04:54:38 PM PST 24
Peak memory 209020 kb
Host smart-51cac352-1776-42af-8314-3939ecc407f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348518847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2348518847
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1993806896
Short name T402
Test name
Test status
Simulation time 693740385 ps
CPU time 5.25 seconds
Started Mar 09 04:54:56 PM PST 24
Finished Mar 09 04:55:01 PM PST 24
Peak memory 209856 kb
Host smart-b778a269-a158-458e-9f95-2945b16c213c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993806896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1993806896
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2897206984
Short name T614
Test name
Test status
Simulation time 112094815 ps
CPU time 4.35 seconds
Started Mar 09 04:54:54 PM PST 24
Finished Mar 09 04:54:59 PM PST 24
Peak memory 206636 kb
Host smart-6688be6e-9402-40d9-97e7-1115897bfca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897206984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2897206984
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.793011705
Short name T208
Test name
Test status
Simulation time 273316855 ps
CPU time 5.23 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:55 PM PST 24
Peak memory 222624 kb
Host smart-3ab72090-45f2-48a1-b5cd-5fbf0fa7586c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793011705 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.793011705
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.721788796
Short name T599
Test name
Test status
Simulation time 96481899 ps
CPU time 4.1 seconds
Started Mar 09 04:54:43 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 209364 kb
Host smart-bb208471-b9dc-455d-a8af-0df66609668d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721788796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.721788796
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2700946966
Short name T977
Test name
Test status
Simulation time 74405721 ps
CPU time 2.75 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 209812 kb
Host smart-f5b4b9af-df63-4768-9f43-99cef1769814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700946966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2700946966
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2202401000
Short name T695
Test name
Test status
Simulation time 21141358 ps
CPU time 0.81 seconds
Started Mar 09 04:54:44 PM PST 24
Finished Mar 09 04:54:45 PM PST 24
Peak memory 205904 kb
Host smart-7676243e-7c5b-45cf-af7e-818e4b639d62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202401000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2202401000
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1890614920
Short name T329
Test name
Test status
Simulation time 703301230 ps
CPU time 6.23 seconds
Started Mar 09 04:54:32 PM PST 24
Finished Mar 09 04:54:40 PM PST 24
Peak memory 214316 kb
Host smart-d2e2ac0b-5938-4b26-b94d-a2ecd3d486fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1890614920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1890614920
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2810772311
Short name T61
Test name
Test status
Simulation time 169336385 ps
CPU time 6.24 seconds
Started Mar 09 04:54:45 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 222824 kb
Host smart-c5378e22-ba60-4434-b7e5-36ad625039cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810772311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2810772311
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2381185643
Short name T1051
Test name
Test status
Simulation time 74745306 ps
CPU time 2.98 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 210044 kb
Host smart-fc71b068-7d58-46bc-b028-74387996c967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381185643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2381185643
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1917146547
Short name T298
Test name
Test status
Simulation time 391439611 ps
CPU time 8.3 seconds
Started Mar 09 04:54:53 PM PST 24
Finished Mar 09 04:55:02 PM PST 24
Peak memory 207964 kb
Host smart-4ffc14b6-d0a0-4f18-8918-cb72a3fa60df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917146547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1917146547
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.409637271
Short name T658
Test name
Test status
Simulation time 70679505 ps
CPU time 2.9 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 206668 kb
Host smart-7b30a176-43b4-4bbf-8157-beb49bdc35d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409637271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.409637271
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3743416411
Short name T3
Test name
Test status
Simulation time 789958165 ps
CPU time 9.51 seconds
Started Mar 09 04:54:46 PM PST 24
Finished Mar 09 04:54:56 PM PST 24
Peak memory 209796 kb
Host smart-173bc494-ae7d-40d9-8a92-6a8e9c4db735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743416411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3743416411
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1542049089
Short name T331
Test name
Test status
Simulation time 775986510 ps
CPU time 22.08 seconds
Started Mar 09 04:54:45 PM PST 24
Finished Mar 09 04:55:07 PM PST 24
Peak memory 208408 kb
Host smart-18b5a9f3-d1b3-49a0-9455-c05e6eea9ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542049089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1542049089
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1437646754
Short name T960
Test name
Test status
Simulation time 128364627 ps
CPU time 4.13 seconds
Started Mar 09 04:54:35 PM PST 24
Finished Mar 09 04:54:39 PM PST 24
Peak memory 208764 kb
Host smart-bd63aaed-b8ac-4f70-a157-18b00f72a838
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437646754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1437646754
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3904853325
Short name T676
Test name
Test status
Simulation time 56765040 ps
CPU time 2.92 seconds
Started Mar 09 04:54:57 PM PST 24
Finished Mar 09 04:55:00 PM PST 24
Peak memory 208532 kb
Host smart-e10b924e-1167-475a-9099-b53993e89bd0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904853325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3904853325
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3534795011
Short name T774
Test name
Test status
Simulation time 2187956419 ps
CPU time 40.06 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:55:28 PM PST 24
Peak memory 208404 kb
Host smart-c3432f1f-25ca-4c1e-bb0c-fd5a47339016
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534795011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3534795011
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1159438375
Short name T694
Test name
Test status
Simulation time 110179779 ps
CPU time 3.32 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 209848 kb
Host smart-a7738875-f9d4-4162-b7a0-79616897e8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159438375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1159438375
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1421131858
Short name T383
Test name
Test status
Simulation time 64359820 ps
CPU time 3.06 seconds
Started Mar 09 04:54:46 PM PST 24
Finished Mar 09 04:54:49 PM PST 24
Peak memory 208256 kb
Host smart-86d34ea7-8cdd-44c4-944b-d298752e5020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421131858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1421131858
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.12962852
Short name T223
Test name
Test status
Simulation time 358756605 ps
CPU time 12.23 seconds
Started Mar 09 04:55:04 PM PST 24
Finished Mar 09 04:55:16 PM PST 24
Peak memory 220172 kb
Host smart-9ff29c98-2976-4cd5-b634-618aa0ebeb1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12962852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.12962852
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3497646371
Short name T846
Test name
Test status
Simulation time 261693980 ps
CPU time 3.37 seconds
Started Mar 09 04:55:04 PM PST 24
Finished Mar 09 04:55:07 PM PST 24
Peak memory 222636 kb
Host smart-2cbb1b97-c5ce-410e-bf25-692b61d114ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497646371 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3497646371
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.135304872
Short name T363
Test name
Test status
Simulation time 134936553 ps
CPU time 2.72 seconds
Started Mar 09 04:54:32 PM PST 24
Finished Mar 09 04:54:36 PM PST 24
Peak memory 218152 kb
Host smart-024dd055-aa60-4991-8bf6-ba1f81bca312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135304872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.135304872
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.431406711
Short name T78
Test name
Test status
Simulation time 81798951 ps
CPU time 1.64 seconds
Started Mar 09 04:54:55 PM PST 24
Finished Mar 09 04:54:57 PM PST 24
Peak memory 209960 kb
Host smart-e731b27a-d14b-4ba2-b1e0-cba4f259e2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431406711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.431406711
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2411354528
Short name T967
Test name
Test status
Simulation time 14405321 ps
CPU time 0.84 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:49 PM PST 24
Peak memory 205864 kb
Host smart-e8d49b8d-f74b-48c3-857b-df7069ab8c0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411354528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2411354528
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1858856123
Short name T263
Test name
Test status
Simulation time 64582880 ps
CPU time 2.37 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:03 PM PST 24
Peak memory 214424 kb
Host smart-590ce227-7f13-44ab-b0a1-5a04bdb09409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858856123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1858856123
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.537540819
Short name T778
Test name
Test status
Simulation time 424970444 ps
CPU time 4.9 seconds
Started Mar 09 04:54:46 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 218304 kb
Host smart-8b8d484b-c36b-4771-9b2d-f8700a59fea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537540819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.537540819
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3210362295
Short name T1057
Test name
Test status
Simulation time 137040425 ps
CPU time 4.03 seconds
Started Mar 09 04:54:59 PM PST 24
Finished Mar 09 04:55:03 PM PST 24
Peak memory 210068 kb
Host smart-a68a873d-5f1c-4a60-afab-1227caedf169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210362295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3210362295
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2561121267
Short name T1006
Test name
Test status
Simulation time 867895354 ps
CPU time 3.56 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:54:53 PM PST 24
Peak memory 208268 kb
Host smart-086bb8cb-2e26-4a7b-b6bb-8bb7ae868ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561121267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2561121267
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2479259206
Short name T992
Test name
Test status
Simulation time 570475616 ps
CPU time 6.9 seconds
Started Mar 09 04:54:36 PM PST 24
Finished Mar 09 04:54:43 PM PST 24
Peak memory 208420 kb
Host smart-ef8ed2ed-c4e2-42e0-87d9-75cb414c35b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479259206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2479259206
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3690339577
Short name T562
Test name
Test status
Simulation time 8705552146 ps
CPU time 92.56 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:56:33 PM PST 24
Peak memory 209236 kb
Host smart-abdf7396-1270-4c9f-906e-6c712adb7ced
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690339577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3690339577
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2947334799
Short name T187
Test name
Test status
Simulation time 186450227 ps
CPU time 6.4 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:56 PM PST 24
Peak memory 208104 kb
Host smart-c258b0e6-7e7e-4ea5-96bd-95bc4fa29c71
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947334799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2947334799
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.176035720
Short name T804
Test name
Test status
Simulation time 165020381 ps
CPU time 5.02 seconds
Started Mar 09 04:54:59 PM PST 24
Finished Mar 09 04:55:04 PM PST 24
Peak memory 206876 kb
Host smart-86702d1d-c609-47c6-9e06-d4e6b6f835bf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176035720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.176035720
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.649228945
Short name T332
Test name
Test status
Simulation time 69763413 ps
CPU time 2.87 seconds
Started Mar 09 04:54:56 PM PST 24
Finished Mar 09 04:54:59 PM PST 24
Peak memory 215532 kb
Host smart-d47a4e40-f660-495a-930b-85273aabbe75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649228945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.649228945
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1731990161
Short name T686
Test name
Test status
Simulation time 100005484 ps
CPU time 1.75 seconds
Started Mar 09 04:54:57 PM PST 24
Finished Mar 09 04:54:59 PM PST 24
Peak memory 206744 kb
Host smart-afa181c9-cbda-4adb-aa64-8897dba3cff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731990161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1731990161
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2836233505
Short name T260
Test name
Test status
Simulation time 220830621 ps
CPU time 7.77 seconds
Started Mar 09 04:54:53 PM PST 24
Finished Mar 09 04:55:06 PM PST 24
Peak memory 206948 kb
Host smart-34e9b6ae-07a2-4e4b-a3a5-8c2c8d924ca8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836233505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2836233505
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.605970788
Short name T190
Test name
Test status
Simulation time 53042314 ps
CPU time 3.27 seconds
Started Mar 09 04:54:56 PM PST 24
Finished Mar 09 04:54:59 PM PST 24
Peak memory 208628 kb
Host smart-c627a5de-82ee-4df6-9ddb-a199ff749d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605970788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.605970788
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1610865142
Short name T670
Test name
Test status
Simulation time 127084657 ps
CPU time 2.99 seconds
Started Mar 09 04:54:46 PM PST 24
Finished Mar 09 04:54:49 PM PST 24
Peak memory 210328 kb
Host smart-df0567ae-d35b-43b9-8017-e64a3bbd3fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610865142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1610865142
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1735342392
Short name T863
Test name
Test status
Simulation time 8240501 ps
CPU time 0.79 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:49 PM PST 24
Peak memory 205756 kb
Host smart-6c91b17c-2e99-4b1e-8a21-cce367dc52f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735342392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1735342392
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2460231070
Short name T400
Test name
Test status
Simulation time 84024982 ps
CPU time 3.08 seconds
Started Mar 09 04:54:58 PM PST 24
Finished Mar 09 04:55:01 PM PST 24
Peak memory 214284 kb
Host smart-af292871-f21d-4dcd-ac26-af893bad2fa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2460231070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2460231070
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.4123650829
Short name T799
Test name
Test status
Simulation time 2134010418 ps
CPU time 15.18 seconds
Started Mar 09 04:54:51 PM PST 24
Finished Mar 09 04:55:07 PM PST 24
Peak memory 221236 kb
Host smart-8a3f1a3e-5359-438c-bb39-254b9df66684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123650829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.4123650829
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.6294385
Short name T43
Test name
Test status
Simulation time 127790613 ps
CPU time 5.07 seconds
Started Mar 09 04:54:46 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 209260 kb
Host smart-92ab7145-ec80-4d3c-bc2d-d3ac8de1542f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6294385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.6294385
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3821555039
Short name T98
Test name
Test status
Simulation time 145486148 ps
CPU time 4.32 seconds
Started Mar 09 04:54:52 PM PST 24
Finished Mar 09 04:54:57 PM PST 24
Peak memory 208476 kb
Host smart-e69b37f1-b5da-4c07-bfe7-d8b373a57a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821555039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3821555039
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3225058110
Short name T859
Test name
Test status
Simulation time 765563177 ps
CPU time 5.95 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:07 PM PST 24
Peak memory 214272 kb
Host smart-6ce18ada-10f2-44af-9fd2-978123b2dca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225058110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3225058110
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1720151652
Short name T938
Test name
Test status
Simulation time 273634020 ps
CPU time 3.55 seconds
Started Mar 09 04:55:00 PM PST 24
Finished Mar 09 04:55:03 PM PST 24
Peak memory 208896 kb
Host smart-791503cd-a050-4825-982a-8420b327379d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720151652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1720151652
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2658899496
Short name T606
Test name
Test status
Simulation time 1013466443 ps
CPU time 7.13 seconds
Started Mar 09 04:54:53 PM PST 24
Finished Mar 09 04:55:00 PM PST 24
Peak memory 207172 kb
Host smart-d20223b6-371f-4012-8ccd-f15d3a3e1b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658899496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2658899496
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.177284176
Short name T663
Test name
Test status
Simulation time 44784274 ps
CPU time 2.59 seconds
Started Mar 09 04:54:59 PM PST 24
Finished Mar 09 04:55:01 PM PST 24
Peak memory 206896 kb
Host smart-3a25f3bf-fbbd-40a9-8e0d-d2fc4e519423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177284176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.177284176
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2829765810
Short name T1037
Test name
Test status
Simulation time 387809573 ps
CPU time 2.6 seconds
Started Mar 09 04:54:51 PM PST 24
Finished Mar 09 04:54:53 PM PST 24
Peak memory 208836 kb
Host smart-70432360-756a-4ad6-a0c3-db1ac8b0f168
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829765810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2829765810
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1196553161
Short name T684
Test name
Test status
Simulation time 138470908 ps
CPU time 2.74 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 207320 kb
Host smart-79c8c8f1-aa68-4d06-9010-9a6ef25cd18f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196553161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1196553161
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2275227688
Short name T186
Test name
Test status
Simulation time 115712566 ps
CPU time 3.09 seconds
Started Mar 09 04:54:46 PM PST 24
Finished Mar 09 04:54:49 PM PST 24
Peak memory 214120 kb
Host smart-0092ee79-4c58-41be-ada4-9ced34d0a096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275227688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2275227688
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1741501917
Short name T738
Test name
Test status
Simulation time 299008963 ps
CPU time 4.41 seconds
Started Mar 09 04:54:46 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 206716 kb
Host smart-d1ad833a-28cc-41ec-bcd1-0ed3b034b22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741501917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1741501917
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3287757627
Short name T882
Test name
Test status
Simulation time 123081713 ps
CPU time 2.83 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 214400 kb
Host smart-a94333c7-60b0-4a2a-99bd-c26f06296e98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287757627 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3287757627
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.892559556
Short name T303
Test name
Test status
Simulation time 1147616282 ps
CPU time 14.83 seconds
Started Mar 09 04:54:51 PM PST 24
Finished Mar 09 04:55:05 PM PST 24
Peak memory 214400 kb
Host smart-74f2a18d-a7c3-4515-8800-c7ca8d3b6f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892559556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.892559556
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.167918272
Short name T848
Test name
Test status
Simulation time 285063862 ps
CPU time 2.34 seconds
Started Mar 09 04:54:52 PM PST 24
Finished Mar 09 04:54:55 PM PST 24
Peak memory 209892 kb
Host smart-77af2fd2-9c56-41d2-88ac-594e90fd2dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167918272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.167918272
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1194322096
Short name T575
Test name
Test status
Simulation time 60290605 ps
CPU time 0.89 seconds
Started Mar 09 04:54:51 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 205716 kb
Host smart-da7475da-3f17-4858-a94d-45551a9c5fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194322096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1194322096
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.746174116
Short name T19
Test name
Test status
Simulation time 75563242 ps
CPU time 3.44 seconds
Started Mar 09 04:54:58 PM PST 24
Finished Mar 09 04:55:01 PM PST 24
Peak memory 216388 kb
Host smart-2006c1a4-42ef-4673-b88a-8393e9354992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746174116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.746174116
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.704429585
Short name T580
Test name
Test status
Simulation time 86783144 ps
CPU time 1.67 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 208800 kb
Host smart-d40ba5a5-263d-4859-92ea-9b2c2127c1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704429585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.704429585
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.234356268
Short name T1034
Test name
Test status
Simulation time 317625657 ps
CPU time 8.97 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:57 PM PST 24
Peak memory 214260 kb
Host smart-d8ad50f8-e067-4aaa-9367-b7800839399a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234356268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.234356268
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1718644042
Short name T64
Test name
Test status
Simulation time 990020734 ps
CPU time 8.95 seconds
Started Mar 09 04:54:39 PM PST 24
Finished Mar 09 04:54:48 PM PST 24
Peak memory 209340 kb
Host smart-b25fb36d-4d06-4893-880f-f02741a10b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718644042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1718644042
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.101302443
Short name T369
Test name
Test status
Simulation time 11901496845 ps
CPU time 71.45 seconds
Started Mar 09 04:54:41 PM PST 24
Finished Mar 09 04:55:53 PM PST 24
Peak memory 208996 kb
Host smart-3ba74b20-f4f4-4177-b6c9-c180648e28c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101302443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.101302443
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3232820441
Short name T293
Test name
Test status
Simulation time 577005470 ps
CPU time 16.4 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:55:07 PM PST 24
Peak memory 208528 kb
Host smart-3594fdfa-1217-464c-abd3-488af918a91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232820441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3232820441
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3470158890
Short name T851
Test name
Test status
Simulation time 197648525 ps
CPU time 2.75 seconds
Started Mar 09 04:54:55 PM PST 24
Finished Mar 09 04:54:58 PM PST 24
Peak memory 206996 kb
Host smart-52dd5b7c-8491-4be3-8927-80dc775ef850
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470158890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3470158890
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1742566142
Short name T246
Test name
Test status
Simulation time 452370796 ps
CPU time 8.79 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:54:58 PM PST 24
Peak memory 208840 kb
Host smart-ac238563-59b7-4576-b72a-0e298e4b26c9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742566142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1742566142
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2105223671
Short name T751
Test name
Test status
Simulation time 104219896 ps
CPU time 2.94 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:53 PM PST 24
Peak memory 206760 kb
Host smart-e32dbc57-0f81-41d7-800b-5929aa04440c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105223671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2105223671
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3255584651
Short name T1021
Test name
Test status
Simulation time 579678015 ps
CPU time 3.29 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 209908 kb
Host smart-7dbbe3bf-62e3-485e-8c32-d5a592b01a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255584651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3255584651
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1588078687
Short name T1024
Test name
Test status
Simulation time 200741112 ps
CPU time 5.02 seconds
Started Mar 09 04:54:51 PM PST 24
Finished Mar 09 04:54:57 PM PST 24
Peak memory 208524 kb
Host smart-6082c0e9-0a1c-4927-9edc-7a2ed54fa381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588078687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1588078687
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2896334664
Short name T1019
Test name
Test status
Simulation time 404094030 ps
CPU time 3.39 seconds
Started Mar 09 04:54:52 PM PST 24
Finished Mar 09 04:54:55 PM PST 24
Peak memory 208588 kb
Host smart-f4e4e5c9-8c67-4f71-a9c6-cd45a3f98930
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896334664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2896334664
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3252471429
Short name T113
Test name
Test status
Simulation time 415378719 ps
CPU time 4.15 seconds
Started Mar 09 04:54:57 PM PST 24
Finished Mar 09 04:55:01 PM PST 24
Peak memory 216152 kb
Host smart-e285d91b-c33d-406a-af85-4b1f0591af95
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252471429 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3252471429
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3396427458
Short name T99
Test name
Test status
Simulation time 2373025078 ps
CPU time 57.28 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:55:45 PM PST 24
Peak memory 218492 kb
Host smart-745f489a-1899-41be-b491-0c241ac2bd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396427458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3396427458
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.4262863459
Short name T568
Test name
Test status
Simulation time 218753242 ps
CPU time 4.28 seconds
Started Mar 09 04:54:51 PM PST 24
Finished Mar 09 04:54:56 PM PST 24
Peak memory 211044 kb
Host smart-9fd2a8b9-097c-493a-9298-00ef6e715acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262863459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.4262863459
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3016500028
Short name T655
Test name
Test status
Simulation time 150434489 ps
CPU time 0.86 seconds
Started Mar 09 04:54:57 PM PST 24
Finished Mar 09 04:54:58 PM PST 24
Peak memory 205912 kb
Host smart-a1865d43-c39e-4192-a10e-b62ad4188eff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016500028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3016500028
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1304379378
Short name T411
Test name
Test status
Simulation time 91486269 ps
CPU time 3.27 seconds
Started Mar 09 04:54:55 PM PST 24
Finished Mar 09 04:54:58 PM PST 24
Peak memory 215384 kb
Host smart-2ff99e6f-b27b-4464-9b87-dcd98e279b22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1304379378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1304379378
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.143090678
Short name T850
Test name
Test status
Simulation time 431731180 ps
CPU time 4.47 seconds
Started Mar 09 04:54:52 PM PST 24
Finished Mar 09 04:54:57 PM PST 24
Peak memory 208132 kb
Host smart-d1d0737b-ad63-4bd5-9389-b90782a9fd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143090678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.143090678
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2919140522
Short name T598
Test name
Test status
Simulation time 102947872 ps
CPU time 3.11 seconds
Started Mar 09 04:54:59 PM PST 24
Finished Mar 09 04:55:02 PM PST 24
Peak memory 207604 kb
Host smart-f6b7468a-a60d-48bd-a9b1-72f9164afe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919140522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2919140522
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.4255815941
Short name T732
Test name
Test status
Simulation time 1082219606 ps
CPU time 35.68 seconds
Started Mar 09 04:54:45 PM PST 24
Finished Mar 09 04:55:21 PM PST 24
Peak memory 209348 kb
Host smart-e1a2cde6-e3e7-44bf-9da7-9a4e9b1fc890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255815941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.4255815941
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1265502333
Short name T792
Test name
Test status
Simulation time 101479397 ps
CPU time 3.73 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:54 PM PST 24
Peak memory 211228 kb
Host smart-cb7bb03a-ada6-4639-be78-d8b7aff5607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265502333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1265502333
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.15355377
Short name T226
Test name
Test status
Simulation time 1537324566 ps
CPU time 4.36 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:54 PM PST 24
Peak memory 209560 kb
Host smart-ce60c402-af62-4e30-8deb-a05ccc9af962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15355377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.15355377
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.475305427
Short name T349
Test name
Test status
Simulation time 25717414904 ps
CPU time 137.55 seconds
Started Mar 09 04:54:46 PM PST 24
Finished Mar 09 04:57:03 PM PST 24
Peak memory 214392 kb
Host smart-256aea83-302e-4557-8019-f1dd45f212ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475305427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.475305427
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3821493767
Short name T775
Test name
Test status
Simulation time 1112374214 ps
CPU time 21.97 seconds
Started Mar 09 04:55:05 PM PST 24
Finished Mar 09 04:55:27 PM PST 24
Peak memory 208524 kb
Host smart-a0f5c8cb-e9e0-4b95-934b-b43f4d0d325c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821493767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3821493767
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.1501569196
Short name T685
Test name
Test status
Simulation time 98361172 ps
CPU time 4.48 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 208580 kb
Host smart-6f3e23e1-a7b9-4504-93ee-df1d9ea8afa7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501569196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1501569196
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3749124113
Short name T723
Test name
Test status
Simulation time 359440092 ps
CPU time 5.67 seconds
Started Mar 09 04:54:58 PM PST 24
Finished Mar 09 04:55:03 PM PST 24
Peak memory 206760 kb
Host smart-4074fda6-3c28-4378-9d49-069b5157f101
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749124113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3749124113
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3440335183
Short name T311
Test name
Test status
Simulation time 71594332 ps
CPU time 3.39 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:53 PM PST 24
Peak memory 206804 kb
Host smart-e46a0655-3ef1-4198-9ebd-618e259ed6b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440335183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3440335183
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.4217917635
Short name T794
Test name
Test status
Simulation time 192501792 ps
CPU time 4.17 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:54:53 PM PST 24
Peak memory 209808 kb
Host smart-7ac29ded-5cee-4f07-8a0c-c0fdd5621caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217917635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.4217917635
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1851696018
Short name T1031
Test name
Test status
Simulation time 71841876 ps
CPU time 3.02 seconds
Started Mar 09 04:54:52 PM PST 24
Finished Mar 09 04:55:01 PM PST 24
Peak memory 208420 kb
Host smart-a43aab8e-787d-4674-8478-0145985d3e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851696018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1851696018
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.238224284
Short name T244
Test name
Test status
Simulation time 34148720211 ps
CPU time 214.51 seconds
Started Mar 09 04:54:46 PM PST 24
Finished Mar 09 04:58:21 PM PST 24
Peak memory 222508 kb
Host smart-c3a0ef1e-4299-48c7-b276-26c3bb69767c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238224284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.238224284
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.952860224
Short name T682
Test name
Test status
Simulation time 293834904 ps
CPU time 6.47 seconds
Started Mar 09 04:54:58 PM PST 24
Finished Mar 09 04:55:05 PM PST 24
Peak memory 208452 kb
Host smart-7c70ffda-c657-4fa9-8aa1-a35bbf5f8895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952860224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.952860224
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1599996351
Short name T115
Test name
Test status
Simulation time 193991849 ps
CPU time 1.82 seconds
Started Mar 09 04:55:00 PM PST 24
Finished Mar 09 04:55:02 PM PST 24
Peak memory 210236 kb
Host smart-bfe9c30c-a52a-4e3b-8c23-55ebe9669229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599996351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1599996351
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.358065952
Short name T561
Test name
Test status
Simulation time 15956705 ps
CPU time 0.72 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 205900 kb
Host smart-3dc8615c-acb1-44cc-b46f-d912e11e1817
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358065952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.358065952
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2604107389
Short name T415
Test name
Test status
Simulation time 2665791341 ps
CPU time 74.09 seconds
Started Mar 09 04:54:45 PM PST 24
Finished Mar 09 04:56:00 PM PST 24
Peak memory 217284 kb
Host smart-f43b8beb-4549-4cd6-a1ba-d1b2b0e86f8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2604107389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2604107389
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3072836278
Short name T1061
Test name
Test status
Simulation time 355025367 ps
CPU time 4.92 seconds
Started Mar 09 04:55:12 PM PST 24
Finished Mar 09 04:55:18 PM PST 24
Peak memory 216248 kb
Host smart-31e649be-ce19-4829-a8a2-df3786dba22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072836278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3072836278
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.3449798459
Short name T67
Test name
Test status
Simulation time 661845362 ps
CPU time 3.56 seconds
Started Mar 09 04:54:54 PM PST 24
Finished Mar 09 04:54:58 PM PST 24
Peak memory 218268 kb
Host smart-e379cabe-e6a0-4620-8f3a-c7a82d9c1544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449798459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.3449798459
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2731252634
Short name T304
Test name
Test status
Simulation time 1906557409 ps
CPU time 58.65 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:55:48 PM PST 24
Peak memory 209880 kb
Host smart-49138952-b1ce-4071-b562-a50c7a004837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731252634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2731252634
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2245634818
Short name T1036
Test name
Test status
Simulation time 61194926 ps
CPU time 4.26 seconds
Started Mar 09 04:54:59 PM PST 24
Finished Mar 09 04:55:09 PM PST 24
Peak memory 211616 kb
Host smart-df9e1ff3-8c64-467f-9c6a-fee96995f531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245634818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2245634818
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2708218889
Short name T269
Test name
Test status
Simulation time 154908735 ps
CPU time 2.19 seconds
Started Mar 09 04:54:52 PM PST 24
Finished Mar 09 04:54:55 PM PST 24
Peak memory 214332 kb
Host smart-7dafc246-d82e-475c-a10f-80bd5d8f2ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708218889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2708218889
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2122181075
Short name T982
Test name
Test status
Simulation time 82689215 ps
CPU time 3.82 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 218264 kb
Host smart-18da85c6-82f2-4fa1-98d5-0c72ec0034a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122181075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2122181075
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1580812545
Short name T584
Test name
Test status
Simulation time 83799940 ps
CPU time 2.99 seconds
Started Mar 09 04:54:57 PM PST 24
Finished Mar 09 04:55:01 PM PST 24
Peak memory 206668 kb
Host smart-32a64259-5f13-4bc5-9a08-a9b4bb826896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580812545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1580812545
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2845462865
Short name T301
Test name
Test status
Simulation time 230970317 ps
CPU time 3.4 seconds
Started Mar 09 04:54:45 PM PST 24
Finished Mar 09 04:54:49 PM PST 24
Peak memory 207568 kb
Host smart-157a78e8-6bfe-4c6c-986c-ae0b1891cc70
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845462865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2845462865
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1761927989
Short name T780
Test name
Test status
Simulation time 826198775 ps
CPU time 11.6 seconds
Started Mar 09 04:55:03 PM PST 24
Finished Mar 09 04:55:14 PM PST 24
Peak memory 208248 kb
Host smart-27ee69fa-6010-4f2f-a088-a684148c4155
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761927989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1761927989
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3531199219
Short name T1054
Test name
Test status
Simulation time 120743635 ps
CPU time 3.91 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 206968 kb
Host smart-ae4e1cf8-cd49-4137-8f78-47a4c2a9cd0e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531199219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3531199219
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2772823527
Short name T991
Test name
Test status
Simulation time 32561891 ps
CPU time 2.26 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 214420 kb
Host smart-e014b4d8-0ac5-4b73-b56e-e145e5ef1da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772823527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2772823527
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3389451249
Short name T822
Test name
Test status
Simulation time 634111844 ps
CPU time 7.92 seconds
Started Mar 09 04:54:56 PM PST 24
Finished Mar 09 04:55:04 PM PST 24
Peak memory 206756 kb
Host smart-8bc09b2e-15d2-4582-bd35-e6a3d1343866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389451249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3389451249
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2956881782
Short name T1020
Test name
Test status
Simulation time 1042551674 ps
CPU time 30.76 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:55:19 PM PST 24
Peak memory 209324 kb
Host smart-b0504b3e-88fe-40fe-82f3-68290aa2f874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956881782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2956881782
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2633542249
Short name T693
Test name
Test status
Simulation time 10701010 ps
CPU time 0.88 seconds
Started Mar 09 04:55:00 PM PST 24
Finished Mar 09 04:55:01 PM PST 24
Peak memory 205852 kb
Host smart-da812d47-20c0-4c81-8c13-9b04639d2bea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633542249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2633542249
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2641464448
Short name T403
Test name
Test status
Simulation time 41995446 ps
CPU time 2.85 seconds
Started Mar 09 04:54:55 PM PST 24
Finished Mar 09 04:54:58 PM PST 24
Peak memory 214332 kb
Host smart-6d714fce-afc9-4439-ad5c-eff30f2410a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2641464448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2641464448
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1894997976
Short name T795
Test name
Test status
Simulation time 234815020 ps
CPU time 3.03 seconds
Started Mar 09 04:54:51 PM PST 24
Finished Mar 09 04:54:54 PM PST 24
Peak memory 214256 kb
Host smart-5ccf44ea-7f2e-41a6-bdd4-022280e87fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894997976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1894997976
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.4249160214
Short name T662
Test name
Test status
Simulation time 54221877 ps
CPU time 2.32 seconds
Started Mar 09 04:54:55 PM PST 24
Finished Mar 09 04:54:58 PM PST 24
Peak memory 207704 kb
Host smart-4bd7c4b0-fabd-4335-a8c8-562411539733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249160214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.4249160214
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3689063407
Short name T89
Test name
Test status
Simulation time 662953857 ps
CPU time 5.75 seconds
Started Mar 09 04:55:02 PM PST 24
Finished Mar 09 04:55:08 PM PST 24
Peak memory 214312 kb
Host smart-1116cd92-4a0d-4457-9794-4fae4e29369c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689063407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3689063407
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2954572061
Short name T844
Test name
Test status
Simulation time 588739934 ps
CPU time 7.04 seconds
Started Mar 09 04:54:59 PM PST 24
Finished Mar 09 04:55:06 PM PST 24
Peak memory 222432 kb
Host smart-948ad7b6-d8be-49a0-9104-fd18ca0b0e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954572061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2954572061
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.1575348019
Short name T46
Test name
Test status
Simulation time 78054535 ps
CPU time 3.51 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 214256 kb
Host smart-1df4c239-90b8-4eee-a6ec-fe105b4b7c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575348019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1575348019
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.123163819
Short name T600
Test name
Test status
Simulation time 565312840 ps
CPU time 6.58 seconds
Started Mar 09 04:55:00 PM PST 24
Finished Mar 09 04:55:06 PM PST 24
Peak memory 207300 kb
Host smart-84cd41ea-7f91-4da8-84ac-8161ea019b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123163819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.123163819
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3528416114
Short name T348
Test name
Test status
Simulation time 87325740 ps
CPU time 3.33 seconds
Started Mar 09 04:55:00 PM PST 24
Finished Mar 09 04:55:04 PM PST 24
Peak memory 208604 kb
Host smart-3d29ca0f-61d0-49d6-9328-fdbcb68a5cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528416114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3528416114
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2711346691
Short name T824
Test name
Test status
Simulation time 278637762 ps
CPU time 4.98 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:53 PM PST 24
Peak memory 206596 kb
Host smart-2ce87cf0-342f-4611-9dba-60b14f392ad0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711346691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2711346691
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3649004911
Short name T745
Test name
Test status
Simulation time 213858966 ps
CPU time 3.24 seconds
Started Mar 09 04:54:47 PM PST 24
Finished Mar 09 04:54:50 PM PST 24
Peak memory 208688 kb
Host smart-cd193c9b-33e2-408b-a299-7d5ce7ba9e3f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649004911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3649004911
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1481326416
Short name T671
Test name
Test status
Simulation time 153279034 ps
CPU time 2.98 seconds
Started Mar 09 04:55:03 PM PST 24
Finished Mar 09 04:55:06 PM PST 24
Peak memory 206928 kb
Host smart-9ef9f0cb-cdec-46dc-bc8a-c5b4295a6dc4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481326416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1481326416
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.578840257
Short name T290
Test name
Test status
Simulation time 293666143 ps
CPU time 3.15 seconds
Started Mar 09 04:55:03 PM PST 24
Finished Mar 09 04:55:06 PM PST 24
Peak memory 209728 kb
Host smart-3606ef5e-1c1a-44fd-8a12-96b187f9f10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578840257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.578840257
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3377609945
Short name T790
Test name
Test status
Simulation time 70133220 ps
CPU time 2.39 seconds
Started Mar 09 04:54:57 PM PST 24
Finished Mar 09 04:54:59 PM PST 24
Peak memory 206872 kb
Host smart-82e81be6-2a0e-4f30-86d6-e11553646a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377609945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3377609945
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2396653721
Short name T225
Test name
Test status
Simulation time 8849904629 ps
CPU time 64 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:55:54 PM PST 24
Peak memory 215364 kb
Host smart-33be1364-8f33-47c4-ac93-59958be5323b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396653721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2396653721
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.2536426227
Short name T212
Test name
Test status
Simulation time 994164397 ps
CPU time 7.56 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:54:56 PM PST 24
Peak memory 222644 kb
Host smart-1f0578e3-b7e5-4fdd-8c1b-33fb442418e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536426227 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.2536426227
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2418990782
Short name T288
Test name
Test status
Simulation time 64323884 ps
CPU time 3.97 seconds
Started Mar 09 04:54:53 PM PST 24
Finished Mar 09 04:54:57 PM PST 24
Peak memory 209624 kb
Host smart-60031582-043a-4195-bb40-774f19b0b676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418990782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2418990782
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.904127259
Short name T673
Test name
Test status
Simulation time 273731504 ps
CPU time 9.54 seconds
Started Mar 09 04:55:02 PM PST 24
Finished Mar 09 04:55:12 PM PST 24
Peak memory 210376 kb
Host smart-041b0930-3503-4b5f-b860-5d7d1723e1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904127259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.904127259
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3408133675
Short name T1041
Test name
Test status
Simulation time 18622402 ps
CPU time 0.76 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 205904 kb
Host smart-c4bdb758-9faa-4460-a058-edacfac94135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408133675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3408133675
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.359975733
Short name T1013
Test name
Test status
Simulation time 2545737120 ps
CPU time 136.87 seconds
Started Mar 09 04:55:13 PM PST 24
Finished Mar 09 04:57:30 PM PST 24
Peak memory 215492 kb
Host smart-a019041e-a331-41dd-b1a2-dde0bbea103d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359975733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.359975733
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1187720001
Short name T24
Test name
Test status
Simulation time 378588997 ps
CPU time 3.81 seconds
Started Mar 09 04:55:04 PM PST 24
Finished Mar 09 04:55:08 PM PST 24
Peak memory 208856 kb
Host smart-b5894837-703e-4a6e-a441-63e53bc447c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187720001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1187720001
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.4224164795
Short name T563
Test name
Test status
Simulation time 38407006 ps
CPU time 1.6 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 218336 kb
Host smart-f2dd2c32-0166-43ea-96fe-546c029c2913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224164795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.4224164795
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.519783131
Short name T887
Test name
Test status
Simulation time 102428283 ps
CPU time 2.81 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 208380 kb
Host smart-d5ce2d5f-62b7-48fa-8350-f14561ddf441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519783131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.519783131
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3447814910
Short name T1003
Test name
Test status
Simulation time 981276577 ps
CPU time 4.4 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:05 PM PST 24
Peak memory 218832 kb
Host smart-b5300760-4af1-4f81-9912-863f5f469585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447814910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3447814910
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3378556853
Short name T100
Test name
Test status
Simulation time 5951838158 ps
CPU time 39.66 seconds
Started Mar 09 04:55:16 PM PST 24
Finished Mar 09 04:55:56 PM PST 24
Peak memory 208540 kb
Host smart-1913a7fc-dc2b-45ad-a926-54027395ba62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378556853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3378556853
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3098568872
Short name T678
Test name
Test status
Simulation time 222444526 ps
CPU time 6.32 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:07 PM PST 24
Peak memory 208156 kb
Host smart-e4de40bc-ca73-43dc-83e7-237adeff3fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098568872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3098568872
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3814938756
Short name T391
Test name
Test status
Simulation time 239709943 ps
CPU time 3.22 seconds
Started Mar 09 04:54:56 PM PST 24
Finished Mar 09 04:54:59 PM PST 24
Peak memory 208556 kb
Host smart-7d0fc449-db69-4241-bc17-e785e4bcc328
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814938756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3814938756
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.831970783
Short name T667
Test name
Test status
Simulation time 212616292 ps
CPU time 2.67 seconds
Started Mar 09 04:54:53 PM PST 24
Finished Mar 09 04:54:56 PM PST 24
Peak memory 206656 kb
Host smart-4b078e5e-d0b4-4767-a57d-f123c3fd3b3a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831970783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.831970783
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1276228005
Short name T1072
Test name
Test status
Simulation time 1553181155 ps
CPU time 6.9 seconds
Started Mar 09 04:54:58 PM PST 24
Finished Mar 09 04:55:05 PM PST 24
Peak memory 208708 kb
Host smart-44fc5456-ed82-420e-93f3-131b18286522
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276228005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1276228005
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2350540588
Short name T192
Test name
Test status
Simulation time 21894861 ps
CPU time 1.77 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 207740 kb
Host smart-4d8a5f36-372a-4a30-a669-9b69ce5e28aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350540588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2350540588
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1229194924
Short name T608
Test name
Test status
Simulation time 756088784 ps
CPU time 7.3 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:57 PM PST 24
Peak memory 208828 kb
Host smart-e2654c24-2007-4a39-8076-cd6b2d7dbea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229194924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1229194924
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.160575774
Short name T818
Test name
Test status
Simulation time 155351938 ps
CPU time 5.95 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:07 PM PST 24
Peak memory 218828 kb
Host smart-29e0e03b-9501-4580-bae4-3b1fc8c4fac0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160575774 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.160575774
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1866817310
Short name T386
Test name
Test status
Simulation time 209894748 ps
CPU time 3.72 seconds
Started Mar 09 04:54:52 PM PST 24
Finished Mar 09 04:54:55 PM PST 24
Peak memory 207984 kb
Host smart-c1554bb6-510f-48f3-931c-c921ea950c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866817310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1866817310
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1640283188
Short name T643
Test name
Test status
Simulation time 56180796 ps
CPU time 1.34 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:51 PM PST 24
Peak memory 209628 kb
Host smart-ec6208ca-6853-4143-aa84-dec98e8be91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640283188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1640283188
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2746211169
Short name T557
Test name
Test status
Simulation time 100692055 ps
CPU time 0.82 seconds
Started Mar 09 04:53:27 PM PST 24
Finished Mar 09 04:53:28 PM PST 24
Peak memory 205844 kb
Host smart-eb2a3073-4a6c-4805-aba3-ed18beffe439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746211169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2746211169
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.908224383
Short name T735
Test name
Test status
Simulation time 1564650793 ps
CPU time 25.04 seconds
Started Mar 09 04:53:38 PM PST 24
Finished Mar 09 04:54:03 PM PST 24
Peak memory 221528 kb
Host smart-9aa5e648-48ad-414c-8412-6906b830309f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908224383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.908224383
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.4014828723
Short name T71
Test name
Test status
Simulation time 44725896 ps
CPU time 3.01 seconds
Started Mar 09 04:53:35 PM PST 24
Finished Mar 09 04:53:38 PM PST 24
Peak memory 209396 kb
Host smart-0e58cd98-8ed5-4d9c-8115-2d0bae0bedf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014828723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.4014828723
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2858914983
Short name T644
Test name
Test status
Simulation time 63553431 ps
CPU time 3.79 seconds
Started Mar 09 04:53:49 PM PST 24
Finished Mar 09 04:53:53 PM PST 24
Peak memory 220872 kb
Host smart-3ab7c55f-8025-4cbb-aa8c-503f0861ff65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858914983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2858914983
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2843696554
Short name T359
Test name
Test status
Simulation time 1656544461 ps
CPU time 9.93 seconds
Started Mar 09 04:53:48 PM PST 24
Finished Mar 09 04:53:58 PM PST 24
Peak memory 214284 kb
Host smart-241f0061-fa55-419d-a61a-bbcb85e8d1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843696554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2843696554
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.1680197805
Short name T666
Test name
Test status
Simulation time 46263630 ps
CPU time 2.72 seconds
Started Mar 09 04:53:53 PM PST 24
Finished Mar 09 04:53:57 PM PST 24
Peak memory 216556 kb
Host smart-7ba53d28-1714-4902-bdfc-0ee9164b8b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680197805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.1680197805
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.174807552
Short name T869
Test name
Test status
Simulation time 4711912310 ps
CPU time 26.29 seconds
Started Mar 09 04:53:40 PM PST 24
Finished Mar 09 04:54:07 PM PST 24
Peak memory 208892 kb
Host smart-1a0ad5ee-0c68-4fd4-830b-1e0ddd579b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174807552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.174807552
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2781827285
Short name T12
Test name
Test status
Simulation time 478280378 ps
CPU time 15.44 seconds
Started Mar 09 04:53:46 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 238380 kb
Host smart-3d2f751c-1b6d-43df-8a5a-4120e114b709
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781827285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2781827285
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3818309520
Short name T254
Test name
Test status
Simulation time 539022323 ps
CPU time 5.26 seconds
Started Mar 09 04:53:36 PM PST 24
Finished Mar 09 04:53:41 PM PST 24
Peak memory 206724 kb
Host smart-66eb955b-c73b-454c-a449-c82fafd5fdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818309520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3818309520
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3417296527
Short name T702
Test name
Test status
Simulation time 1344394174 ps
CPU time 32.75 seconds
Started Mar 09 04:53:29 PM PST 24
Finished Mar 09 04:54:02 PM PST 24
Peak memory 207860 kb
Host smart-11d190e2-6039-4b6b-b291-50d8943b405f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417296527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3417296527
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1795301291
Short name T1005
Test name
Test status
Simulation time 1624582736 ps
CPU time 3.79 seconds
Started Mar 09 04:53:22 PM PST 24
Finished Mar 09 04:53:26 PM PST 24
Peak memory 208844 kb
Host smart-f57f920d-74d9-4c6c-9900-4ecc27174f27
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795301291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1795301291
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1378408277
Short name T273
Test name
Test status
Simulation time 35549819 ps
CPU time 2.41 seconds
Started Mar 09 04:53:49 PM PST 24
Finished Mar 09 04:53:52 PM PST 24
Peak memory 206860 kb
Host smart-83b0f161-1115-44b0-ad5c-5c7e4d13bf9c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378408277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1378408277
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1944502912
Short name T390
Test name
Test status
Simulation time 883913888 ps
CPU time 3.45 seconds
Started Mar 09 04:53:43 PM PST 24
Finished Mar 09 04:53:47 PM PST 24
Peak memory 209956 kb
Host smart-6e32fc97-c4c4-44ea-9cba-9ea82927ee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944502912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1944502912
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2700348546
Short name T569
Test name
Test status
Simulation time 87463390 ps
CPU time 3.33 seconds
Started Mar 09 04:53:46 PM PST 24
Finished Mar 09 04:53:50 PM PST 24
Peak memory 208448 kb
Host smart-ab840be3-edd0-45e4-b8de-02e552e8f614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700348546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2700348546
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.926336738
Short name T218
Test name
Test status
Simulation time 5566388993 ps
CPU time 54.26 seconds
Started Mar 09 04:53:30 PM PST 24
Finished Mar 09 04:54:24 PM PST 24
Peak memory 215732 kb
Host smart-4505ad5f-4b9a-4772-9b34-5a7dce7b17e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926336738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.926336738
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2512040395
Short name T284
Test name
Test status
Simulation time 589001984 ps
CPU time 8.86 seconds
Started Mar 09 04:53:32 PM PST 24
Finished Mar 09 04:53:41 PM PST 24
Peak memory 222736 kb
Host smart-738216d5-ae0a-427a-a100-8410edcdf6f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512040395 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2512040395
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1813068439
Short name T713
Test name
Test status
Simulation time 157697514 ps
CPU time 4.24 seconds
Started Mar 09 04:53:37 PM PST 24
Finished Mar 09 04:53:42 PM PST 24
Peak memory 210104 kb
Host smart-5991c90b-9242-45de-9d1a-7e5614500d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813068439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1813068439
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1044218118
Short name T53
Test name
Test status
Simulation time 163880709 ps
CPU time 3.54 seconds
Started Mar 09 04:53:45 PM PST 24
Finished Mar 09 04:53:49 PM PST 24
Peak memory 210540 kb
Host smart-7f2a10df-9e29-4220-8a4d-d6c3e00273a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044218118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1044218118
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3664335418
Short name T554
Test name
Test status
Simulation time 19585868 ps
CPU time 0.73 seconds
Started Mar 09 04:54:56 PM PST 24
Finished Mar 09 04:54:57 PM PST 24
Peak memory 205908 kb
Host smart-798c2f71-50fa-4e19-9daa-87930c7d88a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664335418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3664335418
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3877468631
Short name T924
Test name
Test status
Simulation time 70187193 ps
CPU time 3.18 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 215340 kb
Host smart-351fbc3e-5e59-437c-a821-828244bb5b53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3877468631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3877468631
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2975754166
Short name T144
Test name
Test status
Simulation time 171999644 ps
CPU time 2.82 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:04 PM PST 24
Peak memory 217324 kb
Host smart-2afdb311-1530-46ce-9bdd-68fd837e5772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975754166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2975754166
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3361125508
Short name T814
Test name
Test status
Simulation time 115742113 ps
CPU time 2.81 seconds
Started Mar 09 04:55:00 PM PST 24
Finished Mar 09 04:55:03 PM PST 24
Peak memory 209384 kb
Host smart-e0fc690c-42e3-455e-a61e-7a380db901d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361125508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3361125508
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2399499495
Short name T287
Test name
Test status
Simulation time 384575945 ps
CPU time 4.59 seconds
Started Mar 09 04:55:29 PM PST 24
Finished Mar 09 04:55:35 PM PST 24
Peak memory 209412 kb
Host smart-eeb35327-6f32-41dd-828a-92b559edba48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399499495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2399499495
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.4135336756
Short name T360
Test name
Test status
Simulation time 104353940 ps
CPU time 5.17 seconds
Started Mar 09 04:55:12 PM PST 24
Finished Mar 09 04:55:17 PM PST 24
Peak memory 210320 kb
Host smart-8686f1a0-6bb1-4442-97f4-e2f29994ba03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135336756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.4135336756
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.339061408
Short name T646
Test name
Test status
Simulation time 291876492 ps
CPU time 3.98 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:05 PM PST 24
Peak memory 209052 kb
Host smart-0cdb7af4-96ce-4dba-a28c-413a5fdfa1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339061408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.339061408
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2616683054
Short name T865
Test name
Test status
Simulation time 399536119 ps
CPU time 11.55 seconds
Started Mar 09 04:55:07 PM PST 24
Finished Mar 09 04:55:19 PM PST 24
Peak memory 209016 kb
Host smart-b1cfbd20-8004-4291-95f2-4ac6758d0faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616683054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2616683054
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2623167831
Short name T565
Test name
Test status
Simulation time 78780970 ps
CPU time 1.76 seconds
Started Mar 09 04:55:03 PM PST 24
Finished Mar 09 04:55:10 PM PST 24
Peak memory 206872 kb
Host smart-76a2cd80-f07c-4f36-8175-0d21f600b024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623167831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2623167831
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1047386873
Short name T1053
Test name
Test status
Simulation time 2208247706 ps
CPU time 45.94 seconds
Started Mar 09 04:54:57 PM PST 24
Finished Mar 09 04:55:43 PM PST 24
Peak memory 209140 kb
Host smart-f520f6f0-17ba-4539-ac10-e68e9c15aebb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047386873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1047386873
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.705443175
Short name T1049
Test name
Test status
Simulation time 148946694 ps
CPU time 5.67 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:07 PM PST 24
Peak memory 206948 kb
Host smart-4912f3ba-c392-4ce0-bad0-a29d311f5102
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705443175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.705443175
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3702824453
Short name T120
Test name
Test status
Simulation time 761408087 ps
CPU time 4.98 seconds
Started Mar 09 04:54:56 PM PST 24
Finished Mar 09 04:55:01 PM PST 24
Peak memory 206748 kb
Host smart-c394850c-6c85-4f73-8855-1f4c1ecf5a5a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702824453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3702824453
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.359232155
Short name T258
Test name
Test status
Simulation time 111705330 ps
CPU time 3.46 seconds
Started Mar 09 04:55:03 PM PST 24
Finished Mar 09 04:55:07 PM PST 24
Peak memory 215916 kb
Host smart-10355619-f8a7-46b6-91e5-cdec3cb17ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359232155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.359232155
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3245549521
Short name T974
Test name
Test status
Simulation time 163548186 ps
CPU time 4.54 seconds
Started Mar 09 04:55:00 PM PST 24
Finished Mar 09 04:55:04 PM PST 24
Peak memory 207864 kb
Host smart-be3b068d-9423-463a-b764-a2ff6ea10a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245549521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3245549521
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2712147698
Short name T828
Test name
Test status
Simulation time 395381018 ps
CPU time 4.69 seconds
Started Mar 09 04:54:59 PM PST 24
Finished Mar 09 04:55:04 PM PST 24
Peak memory 222724 kb
Host smart-302d3736-fd6a-4929-ae9f-91933a9c3523
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712147698 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2712147698
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3364535099
Short name T392
Test name
Test status
Simulation time 411392746 ps
CPU time 11.17 seconds
Started Mar 09 04:55:03 PM PST 24
Finished Mar 09 04:55:15 PM PST 24
Peak memory 218392 kb
Host smart-d2f3f35c-044a-4471-aa17-4f682f2a2c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364535099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3364535099
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2876508193
Short name T577
Test name
Test status
Simulation time 57572240 ps
CPU time 3.26 seconds
Started Mar 09 04:55:09 PM PST 24
Finished Mar 09 04:55:12 PM PST 24
Peak memory 209916 kb
Host smart-0932d5f5-32a5-4038-a09d-dbdf9731a67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876508193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2876508193
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3122743782
Short name T996
Test name
Test status
Simulation time 28103337 ps
CPU time 0.75 seconds
Started Mar 09 04:54:56 PM PST 24
Finished Mar 09 04:54:57 PM PST 24
Peak memory 205904 kb
Host smart-e2251c90-d23b-4fe9-a6df-cf64b30323aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122743782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3122743782
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1551857805
Short name T31
Test name
Test status
Simulation time 4844849971 ps
CPU time 31.73 seconds
Started Mar 09 04:54:52 PM PST 24
Finished Mar 09 04:55:24 PM PST 24
Peak memory 221204 kb
Host smart-f8650f13-7a34-43c3-8579-53016c5b4c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551857805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1551857805
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2909118675
Short name T59
Test name
Test status
Simulation time 53006795 ps
CPU time 2.73 seconds
Started Mar 09 04:55:02 PM PST 24
Finished Mar 09 04:55:05 PM PST 24
Peak memory 207220 kb
Host smart-73f619e4-cc25-4eb1-b565-f87009e508a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909118675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2909118675
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1699588957
Short name T933
Test name
Test status
Simulation time 701532994 ps
CPU time 3.99 seconds
Started Mar 09 04:55:26 PM PST 24
Finished Mar 09 04:55:31 PM PST 24
Peak memory 208980 kb
Host smart-67e1bcf3-f19f-4271-a1df-801d24cb69cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699588957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1699588957
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3787269378
Short name T279
Test name
Test status
Simulation time 595622450 ps
CPU time 7.21 seconds
Started Mar 09 04:55:07 PM PST 24
Finished Mar 09 04:55:14 PM PST 24
Peak memory 211544 kb
Host smart-d55ecbca-4284-49d0-8c10-cf373b122d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787269378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3787269378
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.900472043
Short name T63
Test name
Test status
Simulation time 1120496069 ps
CPU time 4.06 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:06 PM PST 24
Peak memory 209860 kb
Host smart-ab5aabd2-8289-4d70-95c2-9a0cdb2a4d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900472043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.900472043
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2747191258
Short name T355
Test name
Test status
Simulation time 64924730 ps
CPU time 4.02 seconds
Started Mar 09 04:54:48 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 222496 kb
Host smart-2300bc81-5ab9-449e-aea6-3aee924ed5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747191258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2747191258
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.635960417
Short name T895
Test name
Test status
Simulation time 362026844 ps
CPU time 3.69 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:54:53 PM PST 24
Peak memory 206884 kb
Host smart-47adf292-3cb8-4c63-9146-54dd23877a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635960417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.635960417
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1828806547
Short name T704
Test name
Test status
Simulation time 1626808531 ps
CPU time 42.39 seconds
Started Mar 09 04:55:22 PM PST 24
Finished Mar 09 04:56:10 PM PST 24
Peak memory 208912 kb
Host smart-0a4b2bdf-c2a0-4d73-828e-cc0f0f9710c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828806547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1828806547
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.4162860751
Short name T333
Test name
Test status
Simulation time 104016925 ps
CPU time 2.82 seconds
Started Mar 09 04:55:02 PM PST 24
Finished Mar 09 04:55:05 PM PST 24
Peak memory 206844 kb
Host smart-2bfa91ff-27fc-41ee-b562-ec5cbadccb6c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162860751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.4162860751
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2754846804
Short name T647
Test name
Test status
Simulation time 1121033663 ps
CPU time 8.08 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:09 PM PST 24
Peak memory 207760 kb
Host smart-fc44881b-d4d6-47bb-8e7b-143501daf13a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754846804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2754846804
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1224538034
Short name T1044
Test name
Test status
Simulation time 78490027 ps
CPU time 1.89 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:52 PM PST 24
Peak memory 215576 kb
Host smart-247e1e62-3686-4ccb-8098-7de511d309cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224538034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1224538034
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1147835109
Short name T911
Test name
Test status
Simulation time 349017346 ps
CPU time 3.75 seconds
Started Mar 09 04:54:49 PM PST 24
Finished Mar 09 04:54:53 PM PST 24
Peak memory 208196 kb
Host smart-4b9041bc-305a-479d-b17e-f1cf8f4b384d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147835109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1147835109
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1479514979
Short name T716
Test name
Test status
Simulation time 468476677 ps
CPU time 5.57 seconds
Started Mar 09 04:55:19 PM PST 24
Finished Mar 09 04:55:25 PM PST 24
Peak memory 218164 kb
Host smart-0abd7c52-9e39-48a9-b4cf-9107f7284a1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479514979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1479514979
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2346730228
Short name T665
Test name
Test status
Simulation time 234083380 ps
CPU time 6.11 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:07 PM PST 24
Peak memory 222572 kb
Host smart-53bd7502-268a-4cc4-ba50-348de7f12d48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346730228 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2346730228
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3399562934
Short name T346
Test name
Test status
Simulation time 538036515 ps
CPU time 8.14 seconds
Started Mar 09 04:54:57 PM PST 24
Finished Mar 09 04:55:05 PM PST 24
Peak memory 209096 kb
Host smart-a8458556-0978-4aec-be26-27bc9a12d65a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399562934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3399562934
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.250407551
Short name T962
Test name
Test status
Simulation time 386862497 ps
CPU time 3.73 seconds
Started Mar 09 04:54:51 PM PST 24
Finished Mar 09 04:54:54 PM PST 24
Peak memory 210676 kb
Host smart-12a5f36a-dcaa-4850-bca7-d4ba10b20be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250407551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.250407551
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1820207828
Short name T722
Test name
Test status
Simulation time 18126244 ps
CPU time 0.84 seconds
Started Mar 09 04:55:20 PM PST 24
Finished Mar 09 04:55:21 PM PST 24
Peak memory 205824 kb
Host smart-d8992f70-030c-4d1b-b9cb-45228ba9daec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820207828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1820207828
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1235567948
Short name T1038
Test name
Test status
Simulation time 60489127 ps
CPU time 3.21 seconds
Started Mar 09 04:54:51 PM PST 24
Finished Mar 09 04:54:55 PM PST 24
Peak memory 207904 kb
Host smart-8a106265-479f-4199-abf1-2d7be9a5eca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235567948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1235567948
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1267896701
Short name T393
Test name
Test status
Simulation time 175724415 ps
CPU time 3.85 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:05 PM PST 24
Peak memory 208692 kb
Host smart-5efe4fe0-48e0-4bc4-b50d-df05b25ac472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267896701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1267896701
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1739536601
Short name T321
Test name
Test status
Simulation time 304518082 ps
CPU time 4.02 seconds
Started Mar 09 04:55:04 PM PST 24
Finished Mar 09 04:55:08 PM PST 24
Peak memory 214332 kb
Host smart-592e4755-90bc-4e3c-a37b-769bed92faec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739536601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1739536601
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3951865472
Short name T49
Test name
Test status
Simulation time 120442491 ps
CPU time 3.58 seconds
Started Mar 09 04:55:25 PM PST 24
Finished Mar 09 04:55:28 PM PST 24
Peak memory 208744 kb
Host smart-e139cda1-1670-41c8-a3aa-d123d5c3b69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951865472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3951865472
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1483799685
Short name T949
Test name
Test status
Simulation time 129044226 ps
CPU time 2.45 seconds
Started Mar 09 04:54:57 PM PST 24
Finished Mar 09 04:55:00 PM PST 24
Peak memory 208148 kb
Host smart-cc8dfd6e-07cb-4ed2-8057-0af36f1a898b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483799685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1483799685
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.848546100
Short name T631
Test name
Test status
Simulation time 52824328 ps
CPU time 2.73 seconds
Started Mar 09 04:54:50 PM PST 24
Finished Mar 09 04:54:53 PM PST 24
Peak memory 206768 kb
Host smart-4fbc1e89-0a6c-4dbd-9478-fcf3ecdc7d9e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848546100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.848546100
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2201334604
Short name T827
Test name
Test status
Simulation time 247044134 ps
CPU time 3.76 seconds
Started Mar 09 04:55:15 PM PST 24
Finished Mar 09 04:55:19 PM PST 24
Peak memory 206928 kb
Host smart-12fea995-c9a5-4a5f-816e-8ca9bfd71e39
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201334604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2201334604
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.2581214383
Short name T582
Test name
Test status
Simulation time 360343303 ps
CPU time 2.27 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:04 PM PST 24
Peak memory 208868 kb
Host smart-4ad6c0b0-8d49-4088-ac27-2183bd573c12
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581214383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.2581214383
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.313773293
Short name T830
Test name
Test status
Simulation time 71633862 ps
CPU time 2.68 seconds
Started Mar 09 04:55:04 PM PST 24
Finished Mar 09 04:55:06 PM PST 24
Peak memory 209992 kb
Host smart-796b7fc3-53ba-4e4d-b8e3-63ecac0d1bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313773293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.313773293
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2628929455
Short name T793
Test name
Test status
Simulation time 351171128 ps
CPU time 5.42 seconds
Started Mar 09 04:55:00 PM PST 24
Finished Mar 09 04:55:05 PM PST 24
Peak memory 206748 kb
Host smart-d4f2a72b-aee5-4384-842e-4d090943f626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628929455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2628929455
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3989693803
Short name T767
Test name
Test status
Simulation time 2588320833 ps
CPU time 58.4 seconds
Started Mar 09 04:55:24 PM PST 24
Finished Mar 09 04:56:23 PM PST 24
Peak memory 221620 kb
Host smart-f204518b-a434-481f-b4e3-8e60407bec4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989693803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3989693803
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2774934054
Short name T199
Test name
Test status
Simulation time 88387325 ps
CPU time 3.75 seconds
Started Mar 09 04:55:00 PM PST 24
Finished Mar 09 04:55:04 PM PST 24
Peak memory 222648 kb
Host smart-ca9d5164-aca3-42f5-84fe-a4fa1740b943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774934054 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2774934054
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1701038354
Short name T261
Test name
Test status
Simulation time 244065305 ps
CPU time 6.03 seconds
Started Mar 09 04:55:12 PM PST 24
Finished Mar 09 04:55:18 PM PST 24
Peak memory 210072 kb
Host smart-38bc0660-9dd9-4cc3-88ea-f687aef7a97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701038354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1701038354
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3736972306
Short name T698
Test name
Test status
Simulation time 46426774 ps
CPU time 2.59 seconds
Started Mar 09 04:55:24 PM PST 24
Finished Mar 09 04:55:27 PM PST 24
Peak memory 209928 kb
Host smart-f391c531-ef99-4e73-ad62-7fa9f056de0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736972306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3736972306
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.850300553
Short name T93
Test name
Test status
Simulation time 13145025 ps
CPU time 0.89 seconds
Started Mar 09 04:55:19 PM PST 24
Finished Mar 09 04:55:20 PM PST 24
Peak memory 205844 kb
Host smart-9aa8246f-9e28-43e4-9d13-d3a62ad84eed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850300553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.850300553
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1056647953
Short name T941
Test name
Test status
Simulation time 140211592 ps
CPU time 5.51 seconds
Started Mar 09 04:55:32 PM PST 24
Finished Mar 09 04:55:38 PM PST 24
Peak memory 221456 kb
Host smart-91ebd72b-71ab-4431-84d3-feb36655aaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056647953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1056647953
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1264830463
Short name T372
Test name
Test status
Simulation time 2382382008 ps
CPU time 29.97 seconds
Started Mar 09 04:55:08 PM PST 24
Finished Mar 09 04:55:38 PM PST 24
Peak memory 208952 kb
Host smart-2fab2c8a-d3a7-4f9e-a700-6a8cef2a16d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264830463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1264830463
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.4158865456
Short name T773
Test name
Test status
Simulation time 226680249 ps
CPU time 4.09 seconds
Started Mar 09 04:55:18 PM PST 24
Finished Mar 09 04:55:23 PM PST 24
Peak memory 208648 kb
Host smart-324c5398-e96a-48d9-952b-9a41771426a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158865456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4158865456
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3005027740
Short name T266
Test name
Test status
Simulation time 244743414 ps
CPU time 9.83 seconds
Started Mar 09 04:55:02 PM PST 24
Finished Mar 09 04:55:12 PM PST 24
Peak memory 222400 kb
Host smart-ca879f9c-e104-4bb2-a294-fb1f4269162e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005027740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3005027740
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1121404938
Short name T820
Test name
Test status
Simulation time 101516706 ps
CPU time 5.07 seconds
Started Mar 09 04:54:55 PM PST 24
Finished Mar 09 04:55:00 PM PST 24
Peak memory 210320 kb
Host smart-7a23f314-f640-4f01-b4ab-b88e57a0d29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121404938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1121404938
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1353385396
Short name T884
Test name
Test status
Simulation time 12671044260 ps
CPU time 47.29 seconds
Started Mar 09 04:54:59 PM PST 24
Finished Mar 09 04:55:47 PM PST 24
Peak memory 209396 kb
Host smart-c19f3667-1290-40fc-a586-49a127d36cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353385396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1353385396
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2742528884
Short name T259
Test name
Test status
Simulation time 744964961 ps
CPU time 5.62 seconds
Started Mar 09 04:55:20 PM PST 24
Finished Mar 09 04:55:26 PM PST 24
Peak memory 207988 kb
Host smart-bfe3228b-42ea-4019-ae9f-cfcc0fb66dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742528884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2742528884
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1694568775
Short name T709
Test name
Test status
Simulation time 210130893 ps
CPU time 3.02 seconds
Started Mar 09 04:55:04 PM PST 24
Finished Mar 09 04:55:07 PM PST 24
Peak memory 206868 kb
Host smart-a317963c-def0-4c14-9e7d-43efc9faf275
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694568775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1694568775
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2721171210
Short name T837
Test name
Test status
Simulation time 102213470 ps
CPU time 3.22 seconds
Started Mar 09 04:55:00 PM PST 24
Finished Mar 09 04:55:03 PM PST 24
Peak memory 208504 kb
Host smart-41fa8c2d-a143-48f0-adff-ca0af9fdbe93
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721171210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2721171210
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.521084275
Short name T761
Test name
Test status
Simulation time 45830544 ps
CPU time 2.27 seconds
Started Mar 09 04:55:20 PM PST 24
Finished Mar 09 04:55:23 PM PST 24
Peak memory 208888 kb
Host smart-8f6abe7e-7578-40bb-91f5-baae8cb36864
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521084275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.521084275
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3412501387
Short name T1023
Test name
Test status
Simulation time 534937147 ps
CPU time 5.99 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:07 PM PST 24
Peak memory 208612 kb
Host smart-d140fa5e-09f7-4929-ba72-81d4f673162d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412501387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3412501387
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2305540860
Short name T752
Test name
Test status
Simulation time 239159966 ps
CPU time 2.89 seconds
Started Mar 09 04:55:20 PM PST 24
Finished Mar 09 04:55:23 PM PST 24
Peak memory 206824 kb
Host smart-fe66c984-4fad-412f-8c6b-4a4894c7fa19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305540860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2305540860
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2254232179
Short name T668
Test name
Test status
Simulation time 114206673 ps
CPU time 3.99 seconds
Started Mar 09 04:55:05 PM PST 24
Finished Mar 09 04:55:09 PM PST 24
Peak memory 208460 kb
Host smart-0bb3e415-c3e4-4554-913e-4625544fe16f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254232179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2254232179
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3772159361
Short name T385
Test name
Test status
Simulation time 843595917 ps
CPU time 11.9 seconds
Started Mar 09 04:55:14 PM PST 24
Finished Mar 09 04:55:27 PM PST 24
Peak memory 220104 kb
Host smart-b5e5a03b-cbcc-417a-9bf5-ce7e60faeab8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772159361 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3772159361
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.939591896
Short name T808
Test name
Test status
Simulation time 48694233 ps
CPU time 3.2 seconds
Started Mar 09 04:54:58 PM PST 24
Finished Mar 09 04:55:01 PM PST 24
Peak memory 207904 kb
Host smart-cc3ada01-70a8-4e6c-bd32-130c2d3a6428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939591896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.939591896
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1049516882
Short name T715
Test name
Test status
Simulation time 163553133 ps
CPU time 2.34 seconds
Started Mar 09 04:55:02 PM PST 24
Finished Mar 09 04:55:05 PM PST 24
Peak memory 210516 kb
Host smart-9e34f47c-e1bb-4df7-b5a4-1c22a5091d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049516882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1049516882
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3781735177
Short name T708
Test name
Test status
Simulation time 15668682 ps
CPU time 0.79 seconds
Started Mar 09 04:55:11 PM PST 24
Finished Mar 09 04:55:12 PM PST 24
Peak memory 205908 kb
Host smart-0e2d915f-f180-4900-b7ab-da0505dc9a45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781735177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3781735177
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3445941440
Short name T314
Test name
Test status
Simulation time 2151340826 ps
CPU time 115.55 seconds
Started Mar 09 04:55:21 PM PST 24
Finished Mar 09 04:57:17 PM PST 24
Peak memory 216832 kb
Host smart-9b726128-f9cd-4987-b803-380164259287
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3445941440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3445941440
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2376966658
Short name T22
Test name
Test status
Simulation time 207578889 ps
CPU time 8.17 seconds
Started Mar 09 04:55:13 PM PST 24
Finished Mar 09 04:55:22 PM PST 24
Peak memory 222364 kb
Host smart-12195481-3b3f-4da0-adbd-49225b9435fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376966658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2376966658
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.768319086
Short name T262
Test name
Test status
Simulation time 806300064 ps
CPU time 4.99 seconds
Started Mar 09 04:55:11 PM PST 24
Finished Mar 09 04:55:16 PM PST 24
Peak memory 218512 kb
Host smart-4bbe6bdd-c72c-4938-8851-c823af119fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768319086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.768319086
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.268729995
Short name T343
Test name
Test status
Simulation time 712835902 ps
CPU time 19.89 seconds
Started Mar 09 04:55:11 PM PST 24
Finished Mar 09 04:55:31 PM PST 24
Peak memory 209472 kb
Host smart-b688c4a9-3643-4928-aaf8-66532396c9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268729995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.268729995
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.2022135786
Short name T323
Test name
Test status
Simulation time 362482173 ps
CPU time 10.83 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:12 PM PST 24
Peak memory 214320 kb
Host smart-9731bc5c-7920-4e91-b1b2-a4ff71cc1857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022135786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.2022135786
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2261254871
Short name T351
Test name
Test status
Simulation time 209027615 ps
CPU time 3.67 seconds
Started Mar 09 04:55:11 PM PST 24
Finished Mar 09 04:55:15 PM PST 24
Peak memory 207672 kb
Host smart-b029d870-088a-4018-bb76-9c73bb766db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261254871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2261254871
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3960698527
Short name T719
Test name
Test status
Simulation time 1466164869 ps
CPU time 47.43 seconds
Started Mar 09 04:55:00 PM PST 24
Finished Mar 09 04:55:47 PM PST 24
Peak memory 218164 kb
Host smart-154522b7-47d0-4d6f-99bb-b383f0e98d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960698527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3960698527
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1628869300
Short name T753
Test name
Test status
Simulation time 82646055 ps
CPU time 3.9 seconds
Started Mar 09 04:55:12 PM PST 24
Finished Mar 09 04:55:15 PM PST 24
Peak memory 208864 kb
Host smart-298cbe2d-2ac6-43f4-b954-2c9f08879830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628869300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1628869300
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.4294877337
Short name T592
Test name
Test status
Simulation time 937941108 ps
CPU time 25.06 seconds
Started Mar 09 04:55:09 PM PST 24
Finished Mar 09 04:55:35 PM PST 24
Peak memory 208876 kb
Host smart-8d1d5487-e1b3-4e9f-94a8-94d55e017154
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294877337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.4294877337
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2371383496
Short name T638
Test name
Test status
Simulation time 1193692368 ps
CPU time 32.22 seconds
Started Mar 09 04:55:16 PM PST 24
Finished Mar 09 04:55:54 PM PST 24
Peak memory 208720 kb
Host smart-2d8b8013-43c0-45c3-b57a-1b3804caecde
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371383496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2371383496
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3387341139
Short name T1069
Test name
Test status
Simulation time 664784168 ps
CPU time 5.58 seconds
Started Mar 09 04:55:22 PM PST 24
Finished Mar 09 04:55:28 PM PST 24
Peak memory 208656 kb
Host smart-b15e7ac9-baa8-4c3c-bb32-8617c897c9fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387341139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3387341139
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3008695276
Short name T683
Test name
Test status
Simulation time 82015374 ps
CPU time 3.56 seconds
Started Mar 09 04:55:06 PM PST 24
Finished Mar 09 04:55:10 PM PST 24
Peak memory 210004 kb
Host smart-9bd09129-1ef0-4725-9ace-6cdcee2454db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008695276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3008695276
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.30685718
Short name T617
Test name
Test status
Simulation time 202114432 ps
CPU time 2.77 seconds
Started Mar 09 04:54:59 PM PST 24
Finished Mar 09 04:55:02 PM PST 24
Peak memory 206824 kb
Host smart-f503e456-62d2-414a-96cc-14fccf1c4bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30685718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.30685718
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3147123917
Short name T283
Test name
Test status
Simulation time 634249339 ps
CPU time 28.4 seconds
Started Mar 09 04:55:10 PM PST 24
Finished Mar 09 04:55:38 PM PST 24
Peak memory 221088 kb
Host smart-e42894cc-a7ed-425c-add3-f8a5e03e3a89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147123917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3147123917
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1568022292
Short name T1068
Test name
Test status
Simulation time 209611475 ps
CPU time 8.08 seconds
Started Mar 09 04:55:18 PM PST 24
Finished Mar 09 04:55:26 PM PST 24
Peak memory 222532 kb
Host smart-2bb775ce-1137-488e-9f44-0cb128e5ccc2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568022292 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1568022292
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2000493864
Short name T194
Test name
Test status
Simulation time 1565165038 ps
CPU time 10.72 seconds
Started Mar 09 04:55:14 PM PST 24
Finished Mar 09 04:55:25 PM PST 24
Peak memory 219592 kb
Host smart-c252ea81-2162-4c98-a4b4-47e2121292fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000493864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2000493864
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.4032540256
Short name T157
Test name
Test status
Simulation time 90263439 ps
CPU time 2.36 seconds
Started Mar 09 04:55:01 PM PST 24
Finished Mar 09 04:55:03 PM PST 24
Peak memory 209596 kb
Host smart-da8bfa95-1548-469b-a9ba-5e1d0af548ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032540256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.4032540256
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1758333883
Short name T838
Test name
Test status
Simulation time 43658307 ps
CPU time 0.75 seconds
Started Mar 09 04:55:28 PM PST 24
Finished Mar 09 04:55:30 PM PST 24
Peak memory 205840 kb
Host smart-c7594ea8-d7eb-425e-9e97-9ca7feba0a10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758333883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1758333883
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.4126380136
Short name T971
Test name
Test status
Simulation time 49084152 ps
CPU time 3.58 seconds
Started Mar 09 04:55:13 PM PST 24
Finished Mar 09 04:55:17 PM PST 24
Peak memory 215208 kb
Host smart-122d05a6-60f1-459c-ac4e-c09a564b0d78
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4126380136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.4126380136
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.812972898
Short name T21
Test name
Test status
Simulation time 440857873 ps
CPU time 5.13 seconds
Started Mar 09 04:55:23 PM PST 24
Finished Mar 09 04:55:28 PM PST 24
Peak memory 214644 kb
Host smart-59fa68a7-7fa7-4fd5-838e-e6b0a0493f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812972898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.812972898
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3275993337
Short name T69
Test name
Test status
Simulation time 470853661 ps
CPU time 12.46 seconds
Started Mar 09 04:55:07 PM PST 24
Finished Mar 09 04:55:20 PM PST 24
Peak memory 209852 kb
Host smart-62747a00-6976-4b90-bcbc-323ab6fee745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275993337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3275993337
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2744928468
Short name T86
Test name
Test status
Simulation time 283429160 ps
CPU time 9.23 seconds
Started Mar 09 04:55:15 PM PST 24
Finished Mar 09 04:55:24 PM PST 24
Peak memory 214344 kb
Host smart-a30b9a9c-0578-42f3-b1f0-ee66d8fa59fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744928468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2744928468
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.869224784
Short name T766
Test name
Test status
Simulation time 128590721 ps
CPU time 6.27 seconds
Started Mar 09 04:55:10 PM PST 24
Finished Mar 09 04:55:21 PM PST 24
Peak memory 210160 kb
Host smart-6ac48e96-4c90-4ed1-9c6b-d80ca16108c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869224784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.869224784
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1080153869
Short name T47
Test name
Test status
Simulation time 2287071211 ps
CPU time 3.75 seconds
Started Mar 09 04:55:06 PM PST 24
Finished Mar 09 04:55:09 PM PST 24
Peak memory 219784 kb
Host smart-e7a26099-700e-4d7b-87bc-11370316f215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080153869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1080153869
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.118386145
Short name T672
Test name
Test status
Simulation time 101835942 ps
CPU time 3.58 seconds
Started Mar 09 04:55:12 PM PST 24
Finished Mar 09 04:55:16 PM PST 24
Peak memory 218284 kb
Host smart-48362008-bd1c-4928-9703-ec218c4314c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118386145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.118386145
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.120178801
Short name T858
Test name
Test status
Simulation time 730439284 ps
CPU time 8.93 seconds
Started Mar 09 04:55:08 PM PST 24
Finished Mar 09 04:55:17 PM PST 24
Peak memory 208632 kb
Host smart-9198a4a6-8ecd-41a0-8b11-7aad0a6e78f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120178801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.120178801
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1195918100
Short name T581
Test name
Test status
Simulation time 924279837 ps
CPU time 5.87 seconds
Started Mar 09 04:55:33 PM PST 24
Finished Mar 09 04:55:40 PM PST 24
Peak memory 208064 kb
Host smart-bb0d383f-3aea-4d02-a38a-1eae446b3bc3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195918100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1195918100
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.111511669
Short name T927
Test name
Test status
Simulation time 47942056 ps
CPU time 2.8 seconds
Started Mar 09 04:55:18 PM PST 24
Finished Mar 09 04:55:21 PM PST 24
Peak memory 207004 kb
Host smart-344e6238-eb75-4423-8d30-a5f303a4de78
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111511669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.111511669
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.4128122127
Short name T657
Test name
Test status
Simulation time 163929148 ps
CPU time 2.76 seconds
Started Mar 09 04:55:03 PM PST 24
Finished Mar 09 04:55:05 PM PST 24
Peak memory 208540 kb
Host smart-fc87f639-71c7-4e44-96cb-d4d1b1ad71ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128122127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.4128122127
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3743894750
Short name T720
Test name
Test status
Simulation time 159280430 ps
CPU time 3.07 seconds
Started Mar 09 04:55:33 PM PST 24
Finished Mar 09 04:55:37 PM PST 24
Peak memory 218508 kb
Host smart-d4f8c0f9-0d43-4a0e-afec-a93a079ffea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743894750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3743894750
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3569638111
Short name T591
Test name
Test status
Simulation time 4591075515 ps
CPU time 28.76 seconds
Started Mar 09 04:55:04 PM PST 24
Finished Mar 09 04:55:32 PM PST 24
Peak memory 208180 kb
Host smart-9c2ea6ce-8edf-4fc4-b013-3f8c48c9f742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569638111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3569638111
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1283430750
Short name T275
Test name
Test status
Simulation time 11667470590 ps
CPU time 120.6 seconds
Started Mar 09 04:55:04 PM PST 24
Finished Mar 09 04:57:05 PM PST 24
Peak memory 216696 kb
Host smart-1762a956-7ccc-461a-8f4d-953409b35e91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283430750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1283430750
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3217677399
Short name T921
Test name
Test status
Simulation time 875941215 ps
CPU time 6.78 seconds
Started Mar 09 04:55:18 PM PST 24
Finished Mar 09 04:55:25 PM PST 24
Peak memory 207352 kb
Host smart-1f3885f9-6aea-40c2-bcc3-303ca18232ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217677399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3217677399
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.501265816
Short name T770
Test name
Test status
Simulation time 43620054 ps
CPU time 1.44 seconds
Started Mar 09 04:55:27 PM PST 24
Finished Mar 09 04:55:29 PM PST 24
Peak memory 209740 kb
Host smart-1195b98c-132e-4def-af33-aba1491dcb57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501265816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.501265816
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.4074668198
Short name T688
Test name
Test status
Simulation time 10686858 ps
CPU time 0.74 seconds
Started Mar 09 04:55:09 PM PST 24
Finished Mar 09 04:55:10 PM PST 24
Peak memory 205904 kb
Host smart-e02ce61a-6f60-4705-95e7-e87fda5fd4f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074668198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4074668198
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3358203905
Short name T954
Test name
Test status
Simulation time 98697059 ps
CPU time 3.88 seconds
Started Mar 09 04:55:31 PM PST 24
Finished Mar 09 04:55:36 PM PST 24
Peak memory 210188 kb
Host smart-6ddb8083-efe6-4664-b06b-07b7db160dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358203905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3358203905
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.476216018
Short name T610
Test name
Test status
Simulation time 550178523 ps
CPU time 11.26 seconds
Started Mar 09 04:55:20 PM PST 24
Finished Mar 09 04:55:32 PM PST 24
Peak memory 207992 kb
Host smart-bf6a4328-650c-40fc-92c2-7846c70039dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476216018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.476216018
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2472849429
Short name T243
Test name
Test status
Simulation time 962703809 ps
CPU time 30.56 seconds
Started Mar 09 04:55:32 PM PST 24
Finished Mar 09 04:56:03 PM PST 24
Peak memory 214316 kb
Host smart-1f20ff6b-ccd9-41f2-9cfb-72e32b135b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472849429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2472849429
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2359693820
Short name T265
Test name
Test status
Simulation time 399784827 ps
CPU time 4.71 seconds
Started Mar 09 04:55:24 PM PST 24
Finished Mar 09 04:55:29 PM PST 24
Peak memory 214140 kb
Host smart-f742d6eb-a223-4935-9cb9-028fdf51f179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359693820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2359693820
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.604393298
Short name T856
Test name
Test status
Simulation time 97626051 ps
CPU time 2.8 seconds
Started Mar 09 04:55:11 PM PST 24
Finished Mar 09 04:55:14 PM PST 24
Peak memory 222588 kb
Host smart-10116e50-5d64-4002-8bdc-a6cea27b970e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604393298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.604393298
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2558087655
Short name T755
Test name
Test status
Simulation time 1761206988 ps
CPU time 23.45 seconds
Started Mar 09 04:55:26 PM PST 24
Finished Mar 09 04:55:49 PM PST 24
Peak memory 208516 kb
Host smart-c91e1640-70ae-4f8e-a8be-a8e3e3d1c3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558087655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2558087655
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2414626809
Short name T176
Test name
Test status
Simulation time 159584269 ps
CPU time 4.91 seconds
Started Mar 09 04:55:10 PM PST 24
Finished Mar 09 04:55:15 PM PST 24
Peak memory 206768 kb
Host smart-3c3b2d6e-902f-477b-b824-c007738836b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414626809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2414626809
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1590247170
Short name T883
Test name
Test status
Simulation time 85777712 ps
CPU time 3.84 seconds
Started Mar 09 04:55:24 PM PST 24
Finished Mar 09 04:55:28 PM PST 24
Peak memory 208684 kb
Host smart-69af87e9-6a4b-41bf-ae0b-e2f4538ea568
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590247170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1590247170
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.100141979
Short name T633
Test name
Test status
Simulation time 864585984 ps
CPU time 3.44 seconds
Started Mar 09 04:55:29 PM PST 24
Finished Mar 09 04:55:34 PM PST 24
Peak memory 208520 kb
Host smart-2183f02c-cf6d-49c0-a1fe-00b6601200fc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100141979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.100141979
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3638970855
Short name T857
Test name
Test status
Simulation time 73151373 ps
CPU time 3.26 seconds
Started Mar 09 04:55:32 PM PST 24
Finished Mar 09 04:55:36 PM PST 24
Peak memory 206928 kb
Host smart-12f1d90f-bfc0-49ed-a51a-19b5f3b6c44c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638970855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3638970855
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.133997668
Short name T904
Test name
Test status
Simulation time 46639430 ps
CPU time 2.21 seconds
Started Mar 09 04:55:27 PM PST 24
Finished Mar 09 04:55:30 PM PST 24
Peak memory 209928 kb
Host smart-314534b0-d735-4c23-81d6-9996c037e206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133997668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.133997668
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2642127340
Short name T886
Test name
Test status
Simulation time 135332692 ps
CPU time 4.33 seconds
Started Mar 09 04:55:11 PM PST 24
Finished Mar 09 04:55:15 PM PST 24
Peak memory 208408 kb
Host smart-ae1693b3-f1de-4e8c-a283-e3e055b5dbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642127340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2642127340
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3007374292
Short name T784
Test name
Test status
Simulation time 4089642334 ps
CPU time 18.63 seconds
Started Mar 09 04:55:29 PM PST 24
Finished Mar 09 04:55:49 PM PST 24
Peak memory 216732 kb
Host smart-d1229f00-29bb-42a2-88f3-5d9130e1e27a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007374292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3007374292
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3723158166
Short name T642
Test name
Test status
Simulation time 787098336 ps
CPU time 5.45 seconds
Started Mar 09 04:55:24 PM PST 24
Finished Mar 09 04:55:30 PM PST 24
Peak memory 222084 kb
Host smart-fc4dace1-d9a1-4e40-82af-98de28926c0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723158166 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3723158166
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.871659286
Short name T654
Test name
Test status
Simulation time 97474542 ps
CPU time 4.7 seconds
Started Mar 09 04:55:33 PM PST 24
Finished Mar 09 04:55:39 PM PST 24
Peak memory 209244 kb
Host smart-d7367aae-f775-4519-8c2c-cee7a66fefa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871659286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.871659286
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2213356243
Short name T724
Test name
Test status
Simulation time 42543410 ps
CPU time 1.67 seconds
Started Mar 09 04:55:39 PM PST 24
Finished Mar 09 04:55:41 PM PST 24
Peak memory 210260 kb
Host smart-3a1d8807-03d0-4df1-b1b4-1809abaddd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213356243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2213356243
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1607745490
Short name T944
Test name
Test status
Simulation time 46836465 ps
CPU time 0.76 seconds
Started Mar 09 04:55:36 PM PST 24
Finished Mar 09 04:55:37 PM PST 24
Peak memory 205840 kb
Host smart-34326693-dd9d-4638-83c6-c19bcafa493c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607745490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1607745490
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2536109278
Short name T381
Test name
Test status
Simulation time 100821829 ps
CPU time 3.75 seconds
Started Mar 09 04:55:16 PM PST 24
Finished Mar 09 04:55:20 PM PST 24
Peak memory 214308 kb
Host smart-10a1107a-1d52-4a45-a5ba-30eb76b54020
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2536109278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2536109278
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.238917697
Short name T841
Test name
Test status
Simulation time 576473605 ps
CPU time 2.91 seconds
Started Mar 09 04:55:16 PM PST 24
Finished Mar 09 04:55:19 PM PST 24
Peak memory 218280 kb
Host smart-442622ed-7cee-48af-93f8-5b296121ab24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238917697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.238917697
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1790791498
Short name T725
Test name
Test status
Simulation time 181626957 ps
CPU time 6.21 seconds
Started Mar 09 04:55:34 PM PST 24
Finished Mar 09 04:55:41 PM PST 24
Peak memory 214268 kb
Host smart-7c223e1f-711b-41c4-94a2-daeb7f165a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790791498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1790791498
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.950370598
Short name T267
Test name
Test status
Simulation time 224392563 ps
CPU time 6.66 seconds
Started Mar 09 04:55:36 PM PST 24
Finished Mar 09 04:55:43 PM PST 24
Peak memory 222384 kb
Host smart-34e8422f-2b1d-4ba1-a283-878bdc6c3e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950370598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.950370598
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1941976956
Short name T1016
Test name
Test status
Simulation time 187549201 ps
CPU time 6.19 seconds
Started Mar 09 04:55:26 PM PST 24
Finished Mar 09 04:55:32 PM PST 24
Peak memory 210064 kb
Host smart-31c3a461-46dc-449e-a22b-a248d97c8f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941976956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1941976956
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2708297353
Short name T235
Test name
Test status
Simulation time 111343730 ps
CPU time 4.06 seconds
Started Mar 09 04:55:28 PM PST 24
Finished Mar 09 04:55:32 PM PST 24
Peak memory 219068 kb
Host smart-f3fe7bd1-703b-49cf-9566-d02ebba97b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708297353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2708297353
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1517047608
Short name T734
Test name
Test status
Simulation time 52860154 ps
CPU time 2.88 seconds
Started Mar 09 04:55:21 PM PST 24
Finished Mar 09 04:55:24 PM PST 24
Peak memory 208588 kb
Host smart-24f20c75-ca69-49af-b25c-b0c1e95f1006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517047608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1517047608
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1249876197
Short name T923
Test name
Test status
Simulation time 219039477 ps
CPU time 7.76 seconds
Started Mar 09 04:55:18 PM PST 24
Finished Mar 09 04:55:26 PM PST 24
Peak memory 207968 kb
Host smart-94419a85-5a62-475a-aded-ad76b295f93c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249876197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1249876197
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1280360547
Short name T807
Test name
Test status
Simulation time 130752303 ps
CPU time 2.58 seconds
Started Mar 09 04:55:15 PM PST 24
Finished Mar 09 04:55:18 PM PST 24
Peak memory 206876 kb
Host smart-9cfc030d-fc61-4e02-9244-9d07de838014
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280360547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1280360547
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2904315788
Short name T198
Test name
Test status
Simulation time 216781949 ps
CPU time 2.84 seconds
Started Mar 09 04:55:25 PM PST 24
Finished Mar 09 04:55:28 PM PST 24
Peak memory 208864 kb
Host smart-c155d981-1357-42c3-b0f4-9828b908306f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904315788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2904315788
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2241036375
Short name T253
Test name
Test status
Simulation time 165986835 ps
CPU time 3.22 seconds
Started Mar 09 04:55:19 PM PST 24
Finished Mar 09 04:55:23 PM PST 24
Peak memory 208924 kb
Host smart-99dafd97-dac5-4ee7-9586-2a042500d186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241036375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2241036375
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2287904639
Short name T932
Test name
Test status
Simulation time 70539785 ps
CPU time 2.37 seconds
Started Mar 09 04:55:28 PM PST 24
Finished Mar 09 04:55:31 PM PST 24
Peak memory 208652 kb
Host smart-4e5a4f65-1ea1-48f3-9deb-49cffb7e659a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287904639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2287904639
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.334896773
Short name T310
Test name
Test status
Simulation time 241510420 ps
CPU time 6.87 seconds
Started Mar 09 04:55:31 PM PST 24
Finished Mar 09 04:55:39 PM PST 24
Peak memory 220516 kb
Host smart-b5be60f6-0fed-4875-beee-c2664c7cd2cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334896773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.334896773
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1562539447
Short name T785
Test name
Test status
Simulation time 540403432 ps
CPU time 4.83 seconds
Started Mar 09 04:55:15 PM PST 24
Finished Mar 09 04:55:20 PM PST 24
Peak memory 222632 kb
Host smart-eb938868-5047-4b4b-92c1-183aa501450e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562539447 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1562539447
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2764602846
Short name T1018
Test name
Test status
Simulation time 185966060 ps
CPU time 4.61 seconds
Started Mar 09 04:55:36 PM PST 24
Finished Mar 09 04:55:41 PM PST 24
Peak memory 208764 kb
Host smart-7dd45ab1-763c-4ffb-9e55-33d163b80de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764602846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2764602846
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3113923941
Short name T635
Test name
Test status
Simulation time 333180017 ps
CPU time 4.63 seconds
Started Mar 09 04:55:31 PM PST 24
Finished Mar 09 04:55:36 PM PST 24
Peak memory 210392 kb
Host smart-e6bf3187-e874-492d-a60b-da48e5052e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113923941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3113923941
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2041464585
Short name T602
Test name
Test status
Simulation time 35169145 ps
CPU time 0.71 seconds
Started Mar 09 04:55:37 PM PST 24
Finished Mar 09 04:55:38 PM PST 24
Peak memory 205880 kb
Host smart-9a7a4a50-fe41-4d0e-b268-65c2b9264e60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041464585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2041464585
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.370173157
Short name T398
Test name
Test status
Simulation time 340458822 ps
CPU time 5.67 seconds
Started Mar 09 04:55:23 PM PST 24
Finished Mar 09 04:55:30 PM PST 24
Peak memory 214596 kb
Host smart-c62f1def-0cff-4180-8bac-884948bd5665
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=370173157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.370173157
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1272792460
Short name T250
Test name
Test status
Simulation time 219271425 ps
CPU time 4.9 seconds
Started Mar 09 04:55:13 PM PST 24
Finished Mar 09 04:55:18 PM PST 24
Peak memory 214332 kb
Host smart-11af448b-0d84-42d1-9574-c23e4a6c9b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272792460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1272792460
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1661728904
Short name T965
Test name
Test status
Simulation time 561806788 ps
CPU time 5.91 seconds
Started Mar 09 04:55:15 PM PST 24
Finished Mar 09 04:55:21 PM PST 24
Peak memory 208156 kb
Host smart-10d640ff-281d-4cc6-a61b-37c9f4a96f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661728904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1661728904
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1362312618
Short name T219
Test name
Test status
Simulation time 81641747 ps
CPU time 3.89 seconds
Started Mar 09 04:55:18 PM PST 24
Finished Mar 09 04:55:22 PM PST 24
Peak memory 208616 kb
Host smart-26f21d7f-f69c-4bb8-895a-97a94215a235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362312618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1362312618
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3177239273
Short name T918
Test name
Test status
Simulation time 603039094 ps
CPU time 4.34 seconds
Started Mar 09 04:55:13 PM PST 24
Finished Mar 09 04:55:17 PM PST 24
Peak memory 208244 kb
Host smart-3d2bcc43-3ad3-42c0-b757-4ed2616ac6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177239273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3177239273
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1044561484
Short name T823
Test name
Test status
Simulation time 399440578 ps
CPU time 3.8 seconds
Started Mar 09 04:55:23 PM PST 24
Finished Mar 09 04:55:27 PM PST 24
Peak memory 207132 kb
Host smart-71696934-7515-4170-99c1-1634111dac34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044561484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1044561484
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.581490444
Short name T937
Test name
Test status
Simulation time 877922380 ps
CPU time 7.5 seconds
Started Mar 09 04:55:16 PM PST 24
Finished Mar 09 04:55:24 PM PST 24
Peak memory 208648 kb
Host smart-68ee2bc9-74f5-4cf1-ae01-41e9ee658fc3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581490444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.581490444
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.755580245
Short name T354
Test name
Test status
Simulation time 8902080804 ps
CPU time 38.76 seconds
Started Mar 09 04:55:36 PM PST 24
Finished Mar 09 04:56:15 PM PST 24
Peak memory 208536 kb
Host smart-c63045ab-9a90-48a8-9c3f-ccf12b9e4f28
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755580245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.755580245
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.940606429
Short name T624
Test name
Test status
Simulation time 286484194 ps
CPU time 3.41 seconds
Started Mar 09 04:55:29 PM PST 24
Finished Mar 09 04:55:33 PM PST 24
Peak memory 208640 kb
Host smart-969ddd2b-ae68-4ec0-a540-8e509640d80c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940606429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.940606429
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3573206908
Short name T983
Test name
Test status
Simulation time 450277132 ps
CPU time 2.9 seconds
Started Mar 09 04:55:24 PM PST 24
Finished Mar 09 04:55:27 PM PST 24
Peak memory 209088 kb
Host smart-ce728635-ab62-4aa2-bd85-6fe805161ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573206908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3573206908
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.161400653
Short name T586
Test name
Test status
Simulation time 107444887 ps
CPU time 3.39 seconds
Started Mar 09 04:55:39 PM PST 24
Finished Mar 09 04:55:42 PM PST 24
Peak memory 206752 kb
Host smart-6ce1b63b-4952-448a-ac6e-04a654a6b4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161400653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.161400653
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.461987616
Short name T40
Test name
Test status
Simulation time 2188171716 ps
CPU time 42.31 seconds
Started Mar 09 04:55:26 PM PST 24
Finished Mar 09 04:56:08 PM PST 24
Peak memory 216788 kb
Host smart-22ad9657-46ec-4f94-b9b8-f73167505c82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461987616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.461987616
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.284381048
Short name T726
Test name
Test status
Simulation time 70122074 ps
CPU time 3.73 seconds
Started Mar 09 04:55:26 PM PST 24
Finished Mar 09 04:55:30 PM PST 24
Peak memory 222664 kb
Host smart-9aea51cb-fbd7-443e-b3fb-1a8dd34e860a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284381048 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.284381048
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3360142926
Short name T940
Test name
Test status
Simulation time 564230259 ps
CPU time 4.98 seconds
Started Mar 09 04:55:26 PM PST 24
Finished Mar 09 04:55:31 PM PST 24
Peak memory 207180 kb
Host smart-d0d11efd-4e3e-4ddc-af2c-f13c22dff951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360142926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3360142926
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3985649760
Short name T149
Test name
Test status
Simulation time 104890009 ps
CPU time 1.91 seconds
Started Mar 09 04:55:33 PM PST 24
Finished Mar 09 04:55:36 PM PST 24
Peak memory 210180 kb
Host smart-71457322-c042-46bd-a90a-985730ca16c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985649760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3985649760
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3526580957
Short name T966
Test name
Test status
Simulation time 7840420 ps
CPU time 0.81 seconds
Started Mar 09 04:55:47 PM PST 24
Finished Mar 09 04:55:48 PM PST 24
Peak memory 205856 kb
Host smart-2667fc95-1a92-489b-9e58-9e04d587186b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526580957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3526580957
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2920904766
Short name T404
Test name
Test status
Simulation time 137569587 ps
CPU time 2.86 seconds
Started Mar 09 04:55:28 PM PST 24
Finished Mar 09 04:55:31 PM PST 24
Peak memory 214372 kb
Host smart-04632396-3986-4de9-bba6-b3a8a85a17ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2920904766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2920904766
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2543649563
Short name T42
Test name
Test status
Simulation time 118661164 ps
CPU time 2.64 seconds
Started Mar 09 04:55:32 PM PST 24
Finished Mar 09 04:55:35 PM PST 24
Peak memory 218120 kb
Host smart-1208548d-ccc3-434e-a5ea-d1e0beb39e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543649563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2543649563
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2268858257
Short name T242
Test name
Test status
Simulation time 1496767927 ps
CPU time 4.67 seconds
Started Mar 09 04:55:27 PM PST 24
Finished Mar 09 04:55:33 PM PST 24
Peak memory 208568 kb
Host smart-86118793-6ba1-4c8f-bb17-8345c3faf21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268858257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2268858257
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2694684882
Short name T917
Test name
Test status
Simulation time 545539570 ps
CPU time 5.73 seconds
Started Mar 09 04:55:29 PM PST 24
Finished Mar 09 04:55:37 PM PST 24
Peak memory 209892 kb
Host smart-428f7dbd-550f-472b-8bf6-aca9686bd949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694684882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2694684882
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.196176214
Short name T1017
Test name
Test status
Simulation time 339960753 ps
CPU time 9.65 seconds
Started Mar 09 04:55:30 PM PST 24
Finished Mar 09 04:55:41 PM PST 24
Peak memory 207012 kb
Host smart-b21f4d91-99f3-4e49-b031-08d14ef3cfda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196176214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.196176214
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1509003447
Short name T968
Test name
Test status
Simulation time 3823869342 ps
CPU time 12.68 seconds
Started Mar 09 04:55:31 PM PST 24
Finished Mar 09 04:55:44 PM PST 24
Peak memory 206820 kb
Host smart-89552590-2e3a-4d1b-99bb-d912e75e02a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509003447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1509003447
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1920431210
Short name T987
Test name
Test status
Simulation time 509269660 ps
CPU time 10.2 seconds
Started Mar 09 04:55:30 PM PST 24
Finished Mar 09 04:55:41 PM PST 24
Peak memory 208148 kb
Host smart-a32daf18-ddd7-464f-adb7-55c8f2bb7c65
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920431210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1920431210
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2754716886
Short name T776
Test name
Test status
Simulation time 23483368 ps
CPU time 2.12 seconds
Started Mar 09 04:55:42 PM PST 24
Finished Mar 09 04:55:44 PM PST 24
Peak memory 207564 kb
Host smart-942bbcd4-515c-4bc9-a2fe-cf947cfe2b07
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754716886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2754716886
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.202962420
Short name T984
Test name
Test status
Simulation time 296950762 ps
CPU time 8.23 seconds
Started Mar 09 04:55:42 PM PST 24
Finished Mar 09 04:55:51 PM PST 24
Peak memory 208688 kb
Host smart-daa9ded5-7c15-4841-8edc-a3d132f6f6ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202962420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.202962420
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.430838994
Short name T939
Test name
Test status
Simulation time 622013835 ps
CPU time 4.65 seconds
Started Mar 09 04:55:25 PM PST 24
Finished Mar 09 04:55:29 PM PST 24
Peak memory 218324 kb
Host smart-168ec0fd-51aa-4758-8385-02c500854900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430838994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.430838994
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1026528456
Short name T595
Test name
Test status
Simulation time 989421506 ps
CPU time 9.09 seconds
Started Mar 09 04:55:34 PM PST 24
Finished Mar 09 04:55:43 PM PST 24
Peak memory 208520 kb
Host smart-c8810d34-8d8f-4f04-8546-d3f96a8b180b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026528456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1026528456
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.2309964001
Short name T114
Test name
Test status
Simulation time 81449518 ps
CPU time 3.53 seconds
Started Mar 09 04:55:28 PM PST 24
Finished Mar 09 04:55:32 PM PST 24
Peak memory 214500 kb
Host smart-02b243ea-1546-43c5-a774-63d5557c587f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309964001 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.2309964001
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.820820330
Short name T1015
Test name
Test status
Simulation time 161874578 ps
CPU time 2.76 seconds
Started Mar 09 04:55:31 PM PST 24
Finished Mar 09 04:55:34 PM PST 24
Peak memory 207980 kb
Host smart-875d63db-2822-4b5c-8905-103b7751ca1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820820330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.820820330
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3534110595
Short name T1063
Test name
Test status
Simulation time 57017977 ps
CPU time 2.22 seconds
Started Mar 09 04:55:31 PM PST 24
Finished Mar 09 04:55:34 PM PST 24
Peak memory 210208 kb
Host smart-02325c21-c48e-4995-ac4b-88b6f2a3e84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534110595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3534110595
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3949559083
Short name T801
Test name
Test status
Simulation time 12555046 ps
CPU time 0.69 seconds
Started Mar 09 04:53:31 PM PST 24
Finished Mar 09 04:53:32 PM PST 24
Peak memory 205816 kb
Host smart-c292a2a1-d285-43c5-8359-cbf3416e5575
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949559083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3949559083
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.144654400
Short name T234
Test name
Test status
Simulation time 50734486 ps
CPU time 3.5 seconds
Started Mar 09 04:53:43 PM PST 24
Finished Mar 09 04:53:47 PM PST 24
Peak memory 214516 kb
Host smart-9b83f602-08ae-44fe-ac6b-4c678a7da3da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=144654400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.144654400
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1365719683
Short name T707
Test name
Test status
Simulation time 426876704 ps
CPU time 5.85 seconds
Started Mar 09 04:53:42 PM PST 24
Finished Mar 09 04:53:48 PM PST 24
Peak memory 210072 kb
Host smart-766611b1-466a-4150-a3e8-a7cc532b720b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365719683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1365719683
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.533929727
Short name T278
Test name
Test status
Simulation time 195318230 ps
CPU time 1.93 seconds
Started Mar 09 04:53:46 PM PST 24
Finished Mar 09 04:53:49 PM PST 24
Peak memory 207836 kb
Host smart-e385a8ca-b022-4ec6-b288-8dc403f97288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533929727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.533929727
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2708219333
Short name T379
Test name
Test status
Simulation time 633931041 ps
CPU time 3.97 seconds
Started Mar 09 04:53:46 PM PST 24
Finished Mar 09 04:53:50 PM PST 24
Peak memory 214280 kb
Host smart-b6479ebe-ec4d-4ca0-b5b2-3d1bff60ac8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708219333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2708219333
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.415016003
Short name T280
Test name
Test status
Simulation time 175413030 ps
CPU time 3.43 seconds
Started Mar 09 04:53:36 PM PST 24
Finished Mar 09 04:53:39 PM PST 24
Peak memory 210816 kb
Host smart-0beba79b-62fb-4686-a25a-0ac6966ba96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415016003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.415016003
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.4173004006
Short name T935
Test name
Test status
Simulation time 109488388 ps
CPU time 3.45 seconds
Started Mar 09 04:53:40 PM PST 24
Finished Mar 09 04:53:44 PM PST 24
Peak memory 217764 kb
Host smart-4b994569-5336-42f6-9e25-28a6fca710f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173004006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.4173004006
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.4254057066
Short name T920
Test name
Test status
Simulation time 160612237 ps
CPU time 4.82 seconds
Started Mar 09 04:53:49 PM PST 24
Finished Mar 09 04:53:54 PM PST 24
Peak memory 209348 kb
Host smart-08a22c32-5bc9-42ed-9d9f-236745e96e77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254057066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.4254057066
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4148819756
Short name T103
Test name
Test status
Simulation time 432539722 ps
CPU time 6.53 seconds
Started Mar 09 04:53:49 PM PST 24
Finished Mar 09 04:53:56 PM PST 24
Peak memory 207884 kb
Host smart-13d23a94-e675-4244-8db4-346304395c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148819756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4148819756
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.459980918
Short name T951
Test name
Test status
Simulation time 438967097 ps
CPU time 5.84 seconds
Started Mar 09 04:53:50 PM PST 24
Finished Mar 09 04:53:57 PM PST 24
Peak memory 208320 kb
Host smart-287a2abc-7f72-4250-b65b-eee13f9dbb83
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459980918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.459980918
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2829947320
Short name T1048
Test name
Test status
Simulation time 29816723 ps
CPU time 2.34 seconds
Started Mar 09 04:53:44 PM PST 24
Finished Mar 09 04:53:46 PM PST 24
Peak memory 206908 kb
Host smart-7a2048ad-f5b4-47bc-bf83-b333e0a468db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829947320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2829947320
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1734475344
Short name T590
Test name
Test status
Simulation time 715187187 ps
CPU time 7.4 seconds
Started Mar 09 04:53:51 PM PST 24
Finished Mar 09 04:53:59 PM PST 24
Peak memory 208480 kb
Host smart-dc3418c2-1854-4e6e-a7a1-1f4f6eaf23da
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734475344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1734475344
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1881933161
Short name T759
Test name
Test status
Simulation time 41607457 ps
CPU time 2.49 seconds
Started Mar 09 04:53:41 PM PST 24
Finished Mar 09 04:53:44 PM PST 24
Peak memory 208308 kb
Host smart-1973929e-1d17-43ab-84e5-d9d4bbfa00e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881933161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1881933161
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.820501519
Short name T588
Test name
Test status
Simulation time 119608645 ps
CPU time 2.58 seconds
Started Mar 09 04:53:37 PM PST 24
Finished Mar 09 04:53:40 PM PST 24
Peak memory 206748 kb
Host smart-dd147f9c-b0fe-45a6-b11c-db7b95436e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820501519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.820501519
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1882765855
Short name T224
Test name
Test status
Simulation time 4436543520 ps
CPU time 45.54 seconds
Started Mar 09 04:53:39 PM PST 24
Finished Mar 09 04:54:25 PM PST 24
Peak memory 215936 kb
Host smart-b229f619-fbc0-4d53-8eff-de29682b7b71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882765855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1882765855
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.4171093898
Short name T744
Test name
Test status
Simulation time 244012827 ps
CPU time 3.61 seconds
Started Mar 09 04:54:18 PM PST 24
Finished Mar 09 04:54:22 PM PST 24
Peak memory 218264 kb
Host smart-7864f97a-cb35-4cee-b862-cd6e8863bc67
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171093898 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.4171093898
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3952976278
Short name T305
Test name
Test status
Simulation time 220511680 ps
CPU time 8.26 seconds
Started Mar 09 04:53:38 PM PST 24
Finished Mar 09 04:53:46 PM PST 24
Peak memory 214252 kb
Host smart-9b7cdaf9-ca3e-47ed-899a-38798d7daea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952976278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3952976278
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3065944005
Short name T395
Test name
Test status
Simulation time 477858847 ps
CPU time 8.88 seconds
Started Mar 09 04:53:41 PM PST 24
Finished Mar 09 04:53:50 PM PST 24
Peak memory 210964 kb
Host smart-b7d469a7-da26-4ce8-a5a9-81fd7489811b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065944005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3065944005
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3317811601
Short name T919
Test name
Test status
Simulation time 15720312 ps
CPU time 0.72 seconds
Started Mar 09 04:53:52 PM PST 24
Finished Mar 09 04:53:54 PM PST 24
Peak memory 205772 kb
Host smart-b819b048-7432-40d4-b471-6fe017ea98b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317811601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3317811601
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3070643646
Short name T413
Test name
Test status
Simulation time 981058561 ps
CPU time 50.79 seconds
Started Mar 09 04:53:31 PM PST 24
Finished Mar 09 04:54:22 PM PST 24
Peak memory 222496 kb
Host smart-42c9ffc1-c930-4c75-bae2-8d7e2361bf6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070643646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3070643646
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1384177154
Short name T914
Test name
Test status
Simulation time 7891961137 ps
CPU time 29.74 seconds
Started Mar 09 04:53:42 PM PST 24
Finished Mar 09 04:54:12 PM PST 24
Peak memory 214396 kb
Host smart-2cb77bcb-4247-45da-b751-bedd12779c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384177154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1384177154
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1469694371
Short name T384
Test name
Test status
Simulation time 21059248 ps
CPU time 1.56 seconds
Started Mar 09 04:53:35 PM PST 24
Finished Mar 09 04:53:42 PM PST 24
Peak memory 207564 kb
Host smart-4442d348-428c-416d-b9f8-a9b001eefbb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469694371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1469694371
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3770173138
Short name T706
Test name
Test status
Simulation time 118536511 ps
CPU time 4.82 seconds
Started Mar 09 04:53:38 PM PST 24
Finished Mar 09 04:53:42 PM PST 24
Peak memory 222436 kb
Host smart-ab79b2d8-585c-48a4-b40e-14338c84d0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770173138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3770173138
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.911051478
Short name T374
Test name
Test status
Simulation time 343278569 ps
CPU time 7.05 seconds
Started Mar 09 04:53:43 PM PST 24
Finished Mar 09 04:53:50 PM PST 24
Peak memory 211296 kb
Host smart-0eccd031-5073-4e5d-ae45-aae229c4de4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911051478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.911051478
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3331968336
Short name T736
Test name
Test status
Simulation time 323622843 ps
CPU time 4.28 seconds
Started Mar 09 04:53:52 PM PST 24
Finished Mar 09 04:53:56 PM PST 24
Peak memory 220440 kb
Host smart-4de2d9bc-c37e-449c-b642-1367a19ac12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331968336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3331968336
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_sideload.4172781925
Short name T256
Test name
Test status
Simulation time 362917074 ps
CPU time 7.19 seconds
Started Mar 09 04:53:30 PM PST 24
Finished Mar 09 04:53:37 PM PST 24
Peak memory 208508 kb
Host smart-690b2813-e334-4f15-af9c-6167793dc5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172781925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.4172781925
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1712173709
Short name T727
Test name
Test status
Simulation time 36887378 ps
CPU time 2.45 seconds
Started Mar 09 04:53:29 PM PST 24
Finished Mar 09 04:53:32 PM PST 24
Peak memory 208300 kb
Host smart-c566f3f7-bed2-4c40-97c8-e77d544e5a2d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712173709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1712173709
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1625039905
Short name T596
Test name
Test status
Simulation time 291554737 ps
CPU time 3.54 seconds
Started Mar 09 04:53:35 PM PST 24
Finished Mar 09 04:53:43 PM PST 24
Peak memory 208716 kb
Host smart-83f71e05-68e9-4cec-9968-ecbb8f139b00
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625039905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1625039905
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1443200729
Short name T308
Test name
Test status
Simulation time 96713643 ps
CPU time 4.2 seconds
Started Mar 09 04:53:39 PM PST 24
Finished Mar 09 04:53:44 PM PST 24
Peak memory 209052 kb
Host smart-1dc95307-0bdb-4549-a264-30c40f211e62
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443200729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1443200729
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3080418147
Short name T558
Test name
Test status
Simulation time 69485753 ps
CPU time 1.63 seconds
Started Mar 09 04:53:38 PM PST 24
Finished Mar 09 04:53:39 PM PST 24
Peak memory 207160 kb
Host smart-8b65d5db-ab5d-4016-8ad9-bd7738ac2ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080418147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3080418147
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1602235570
Short name T950
Test name
Test status
Simulation time 37460147 ps
CPU time 2.46 seconds
Started Mar 09 04:53:35 PM PST 24
Finished Mar 09 04:53:38 PM PST 24
Peak memory 208524 kb
Host smart-4e6015ee-a7de-4281-aa79-f4be7477af6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602235570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1602235570
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2585505309
Short name T576
Test name
Test status
Simulation time 590146704 ps
CPU time 6.8 seconds
Started Mar 09 04:53:27 PM PST 24
Finished Mar 09 04:53:34 PM PST 24
Peak memory 206696 kb
Host smart-b8aad303-3b9b-479d-9df1-78773502a2af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585505309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2585505309
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1818353425
Short name T957
Test name
Test status
Simulation time 224204977 ps
CPU time 4.21 seconds
Started Mar 09 04:53:52 PM PST 24
Finished Mar 09 04:53:57 PM PST 24
Peak memory 214412 kb
Host smart-481629f2-7210-4ae0-b169-0ba973f3ce6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818353425 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1818353425
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.305252401
Short name T123
Test name
Test status
Simulation time 177341899 ps
CPU time 6.46 seconds
Started Mar 09 04:53:36 PM PST 24
Finished Mar 09 04:53:42 PM PST 24
Peak memory 210228 kb
Host smart-5cb2fd74-b7ae-424f-a82b-09437f2caaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305252401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.305252401
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.791658714
Short name T660
Test name
Test status
Simulation time 126766613 ps
CPU time 1.91 seconds
Started Mar 09 04:53:54 PM PST 24
Finished Mar 09 04:53:56 PM PST 24
Peak memory 209668 kb
Host smart-a23ef6fd-1225-43e2-891d-189daa5b205d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791658714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.791658714
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3584166965
Short name T945
Test name
Test status
Simulation time 63852846 ps
CPU time 0.75 seconds
Started Mar 09 04:53:49 PM PST 24
Finished Mar 09 04:53:50 PM PST 24
Peak memory 205884 kb
Host smart-a199517f-f6bf-4688-871d-165c69c9a344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584166965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3584166965
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2794515948
Short name T640
Test name
Test status
Simulation time 70591818 ps
CPU time 2.75 seconds
Started Mar 09 04:53:51 PM PST 24
Finished Mar 09 04:53:59 PM PST 24
Peak memory 209844 kb
Host smart-b8893c4b-4f40-49ed-8c0f-a2f1509bb287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794515948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2794515948
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.665822697
Short name T87
Test name
Test status
Simulation time 8811580575 ps
CPU time 80.97 seconds
Started Mar 09 04:53:48 PM PST 24
Finished Mar 09 04:55:09 PM PST 24
Peak memory 222508 kb
Host smart-b7f49ba1-aa20-44b1-861f-348c88c810c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665822697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.665822697
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.708273254
Short name T80
Test name
Test status
Simulation time 11345224483 ps
CPU time 131.6 seconds
Started Mar 09 04:53:47 PM PST 24
Finished Mar 09 04:56:00 PM PST 24
Peak memory 228592 kb
Host smart-9a58ac32-d422-4067-9bbb-ae64cfe170ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708273254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.708273254
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_random.1296050494
Short name T335
Test name
Test status
Simulation time 350449687 ps
CPU time 4.07 seconds
Started Mar 09 04:53:34 PM PST 24
Finished Mar 09 04:53:38 PM PST 24
Peak memory 209352 kb
Host smart-fb40889c-abf9-41dc-b640-1cc3cb10a201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296050494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1296050494
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3811938307
Short name T885
Test name
Test status
Simulation time 416071715 ps
CPU time 3.79 seconds
Started Mar 09 04:53:34 PM PST 24
Finished Mar 09 04:53:38 PM PST 24
Peak memory 206872 kb
Host smart-30dc9e83-26b7-44fc-b336-a0b62d807b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811938307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3811938307
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2165431928
Short name T849
Test name
Test status
Simulation time 553433765 ps
CPU time 14.22 seconds
Started Mar 09 04:53:43 PM PST 24
Finished Mar 09 04:53:58 PM PST 24
Peak memory 208004 kb
Host smart-51b3f400-c993-4861-94c7-98570721dbd9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165431928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2165431928
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2834063724
Short name T174
Test name
Test status
Simulation time 1185477915 ps
CPU time 3.9 seconds
Started Mar 09 04:53:38 PM PST 24
Finished Mar 09 04:53:42 PM PST 24
Peak memory 208824 kb
Host smart-1484d14f-7d14-44be-bdbd-d32d69561edd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834063724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2834063724
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3438841918
Short name T989
Test name
Test status
Simulation time 677331328 ps
CPU time 9.03 seconds
Started Mar 09 04:53:46 PM PST 24
Finished Mar 09 04:53:55 PM PST 24
Peak memory 208424 kb
Host smart-385d917c-447f-4db0-b643-2a9778db77a2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438841918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3438841918
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.792106304
Short name T609
Test name
Test status
Simulation time 338007160 ps
CPU time 4.04 seconds
Started Mar 09 04:53:42 PM PST 24
Finished Mar 09 04:53:46 PM PST 24
Peak memory 209424 kb
Host smart-8638c284-b219-48b2-9c6d-57001af7ce49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792106304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.792106304
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3313947761
Short name T1009
Test name
Test status
Simulation time 358353624 ps
CPU time 7.2 seconds
Started Mar 09 04:53:46 PM PST 24
Finished Mar 09 04:53:53 PM PST 24
Peak memory 208456 kb
Host smart-5f80cccb-e650-4a6d-9cc5-a390c850bc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313947761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3313947761
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.144505163
Short name T367
Test name
Test status
Simulation time 2539133197 ps
CPU time 68.28 seconds
Started Mar 09 04:53:48 PM PST 24
Finished Mar 09 04:54:56 PM PST 24
Peak memory 222540 kb
Host smart-b04c1e86-04c9-454d-a09b-579942074501
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144505163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.144505163
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3133997847
Short name T946
Test name
Test status
Simulation time 129250434 ps
CPU time 2.56 seconds
Started Mar 09 04:53:50 PM PST 24
Finished Mar 09 04:53:53 PM PST 24
Peak memory 222596 kb
Host smart-2a04fc16-33ae-44f4-8269-8574589fb08e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133997847 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3133997847
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.4009873268
Short name T809
Test name
Test status
Simulation time 96524121 ps
CPU time 2.22 seconds
Started Mar 09 04:53:44 PM PST 24
Finished Mar 09 04:53:46 PM PST 24
Peak memory 207216 kb
Host smart-d0abd416-5e31-48f2-8c01-2e42a9908c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009873268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.4009873268
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1429974076
Short name T652
Test name
Test status
Simulation time 108570915 ps
CPU time 1.32 seconds
Started Mar 09 04:53:37 PM PST 24
Finished Mar 09 04:53:39 PM PST 24
Peak memory 210576 kb
Host smart-b6673467-7b01-4c00-98fb-e38d464c0697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429974076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1429974076
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.529396187
Short name T637
Test name
Test status
Simulation time 54017533 ps
CPU time 0.76 seconds
Started Mar 09 04:53:39 PM PST 24
Finished Mar 09 04:53:40 PM PST 24
Peak memory 205904 kb
Host smart-d724f236-2fce-4aa9-b9b2-78e50eb0239b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529396187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.529396187
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.518672991
Short name T873
Test name
Test status
Simulation time 46465193 ps
CPU time 1.46 seconds
Started Mar 09 04:54:03 PM PST 24
Finished Mar 09 04:54:05 PM PST 24
Peak memory 214316 kb
Host smart-944e7b21-12f9-4dcb-a4e5-b1e5db784206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518672991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.518672991
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2965043282
Short name T68
Test name
Test status
Simulation time 330824681 ps
CPU time 7.93 seconds
Started Mar 09 04:53:39 PM PST 24
Finished Mar 09 04:53:47 PM PST 24
Peak memory 208476 kb
Host smart-4b5ac882-1de7-4fb0-8787-8d48ab84dbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965043282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2965043282
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.745535998
Short name T16
Test name
Test status
Simulation time 302086625 ps
CPU time 4.6 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:05 PM PST 24
Peak memory 219048 kb
Host smart-5311cf2b-ce97-4e1b-9808-6fc3b8ebaba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745535998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.745535998
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2008585890
Short name T193
Test name
Test status
Simulation time 113194078 ps
CPU time 4.94 seconds
Started Mar 09 04:54:07 PM PST 24
Finished Mar 09 04:54:13 PM PST 24
Peak memory 214348 kb
Host smart-72435f34-688e-45e7-afce-2b997412993a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008585890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2008585890
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1166549641
Short name T48
Test name
Test status
Simulation time 158778457 ps
CPU time 2.4 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:53:58 PM PST 24
Peak memory 210472 kb
Host smart-03112dae-5e04-47f5-a645-528e21e641e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166549641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1166549641
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.882995180
Short name T172
Test name
Test status
Simulation time 421883828 ps
CPU time 5.19 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:00 PM PST 24
Peak memory 214284 kb
Host smart-098cb773-0995-4888-b113-402d97acb9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882995180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.882995180
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2628674823
Short name T831
Test name
Test status
Simulation time 373380386 ps
CPU time 3.45 seconds
Started Mar 09 04:53:54 PM PST 24
Finished Mar 09 04:53:58 PM PST 24
Peak memory 207236 kb
Host smart-54e1474d-d016-4521-9353-33d135a4de83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628674823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2628674823
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2661890231
Short name T772
Test name
Test status
Simulation time 45212698 ps
CPU time 1.89 seconds
Started Mar 09 04:53:54 PM PST 24
Finished Mar 09 04:53:57 PM PST 24
Peak memory 206916 kb
Host smart-2d8503aa-371e-486e-8e6d-65c0696c34bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661890231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2661890231
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3364344206
Short name T605
Test name
Test status
Simulation time 83045425 ps
CPU time 3.21 seconds
Started Mar 09 04:53:34 PM PST 24
Finished Mar 09 04:53:37 PM PST 24
Peak memory 206776 kb
Host smart-d2905ad9-f4da-49f7-8737-01fc8c7e4036
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364344206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3364344206
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1038171732
Short name T881
Test name
Test status
Simulation time 170665050 ps
CPU time 3.7 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:01 PM PST 24
Peak memory 206848 kb
Host smart-1509412b-0c42-4578-baca-c2043edb95cd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038171732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1038171732
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.88064399
Short name T749
Test name
Test status
Simulation time 1619088805 ps
CPU time 25.17 seconds
Started Mar 09 04:53:46 PM PST 24
Finished Mar 09 04:54:12 PM PST 24
Peak memory 208740 kb
Host smart-f88cf1ca-0304-4db8-93d6-42cc2ad7de41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88064399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.88064399
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1343678297
Short name T629
Test name
Test status
Simulation time 71747814 ps
CPU time 2.24 seconds
Started Mar 09 04:53:35 PM PST 24
Finished Mar 09 04:53:37 PM PST 24
Peak memory 206752 kb
Host smart-14cc61db-0ee0-4b12-8eea-61760aec8717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343678297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1343678297
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.76729508
Short name T964
Test name
Test status
Simulation time 3788408492 ps
CPU time 34.87 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:32 PM PST 24
Peak memory 222472 kb
Host smart-550eaf24-199f-4f63-aba4-196261e5661e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76729508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.76729508
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2614557550
Short name T1011
Test name
Test status
Simulation time 690180690 ps
CPU time 5.06 seconds
Started Mar 09 04:53:50 PM PST 24
Finished Mar 09 04:53:56 PM PST 24
Peak memory 222588 kb
Host smart-c83b7ece-5e44-4c5f-83e2-f2556e71b312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614557550 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2614557550
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3961437831
Short name T993
Test name
Test status
Simulation time 211588236 ps
CPU time 5.05 seconds
Started Mar 09 04:53:39 PM PST 24
Finished Mar 09 04:53:44 PM PST 24
Peak memory 209800 kb
Host smart-66682e88-b40c-4b60-897a-3452502b0f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961437831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3961437831
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3201637499
Short name T173
Test name
Test status
Simulation time 114078632 ps
CPU time 1.81 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:53:58 PM PST 24
Peak memory 209820 kb
Host smart-4bf4f3f8-03d1-45bc-869d-542198e3a3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201637499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3201637499
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.83850743
Short name T958
Test name
Test status
Simulation time 16663531 ps
CPU time 0.8 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:53:58 PM PST 24
Peak memory 205908 kb
Host smart-23354ca9-7f82-4110-ae15-839ff78674c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83850743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.83850743
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.40760845
Short name T271
Test name
Test status
Simulation time 1689668420 ps
CPU time 91.47 seconds
Started Mar 09 04:53:57 PM PST 24
Finished Mar 09 04:55:29 PM PST 24
Peak memory 215788 kb
Host smart-ee4ff6f6-c217-4c22-a452-63cb11c55a4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=40760845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.40760845
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2364363198
Short name T1040
Test name
Test status
Simulation time 68459545 ps
CPU time 3.39 seconds
Started Mar 09 04:53:39 PM PST 24
Finished Mar 09 04:53:42 PM PST 24
Peak memory 214360 kb
Host smart-c2c6631e-8ba1-4a84-af64-5ed54afaf5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364363198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2364363198
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.4134039781
Short name T65
Test name
Test status
Simulation time 42416126 ps
CPU time 1.9 seconds
Started Mar 09 04:53:54 PM PST 24
Finished Mar 09 04:53:57 PM PST 24
Peak memory 207084 kb
Host smart-e63b554b-640f-43b7-b48d-1755fe719962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134039781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4134039781
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.955478059
Short name T902
Test name
Test status
Simulation time 105135863 ps
CPU time 3.41 seconds
Started Mar 09 04:53:38 PM PST 24
Finished Mar 09 04:53:41 PM PST 24
Peak memory 208832 kb
Host smart-1f976fa6-5f48-4ffe-ae05-713f3d742a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955478059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.955478059
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1574524952
Short name T239
Test name
Test status
Simulation time 553354588 ps
CPU time 6.48 seconds
Started Mar 09 04:53:45 PM PST 24
Finished Mar 09 04:53:51 PM PST 24
Peak memory 214312 kb
Host smart-80bef1b3-cbc5-478c-8e34-41334b2fa5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574524952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1574524952
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2473360695
Short name T970
Test name
Test status
Simulation time 321487214 ps
CPU time 4.17 seconds
Started Mar 09 04:53:54 PM PST 24
Finished Mar 09 04:53:59 PM PST 24
Peak memory 214420 kb
Host smart-03c05139-d989-4deb-8599-03eff3d46bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473360695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2473360695
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.314132367
Short name T85
Test name
Test status
Simulation time 309809165 ps
CPU time 8.06 seconds
Started Mar 09 04:53:56 PM PST 24
Finished Mar 09 04:54:05 PM PST 24
Peak memory 218276 kb
Host smart-0586bb3f-fcee-47cd-b9c6-58fcf5eec646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314132367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.314132367
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.4119534161
Short name T313
Test name
Test status
Simulation time 193759644 ps
CPU time 2.89 seconds
Started Mar 09 04:54:35 PM PST 24
Finished Mar 09 04:54:38 PM PST 24
Peak memory 206800 kb
Host smart-f49b4154-dfb5-48f1-bb6f-d1d70989c315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119534161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.4119534161
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3579449381
Short name T641
Test name
Test status
Simulation time 101970543 ps
CPU time 2.83 seconds
Started Mar 09 04:53:36 PM PST 24
Finished Mar 09 04:53:39 PM PST 24
Peak memory 207260 kb
Host smart-cb3dba86-ac2f-4119-91e7-1b64884fac59
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579449381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3579449381
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2876678854
Short name T739
Test name
Test status
Simulation time 11719399056 ps
CPU time 43.16 seconds
Started Mar 09 04:53:42 PM PST 24
Finished Mar 09 04:54:25 PM PST 24
Peak memory 208568 kb
Host smart-50538c0e-1389-4621-9f87-dbf55b85f586
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876678854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2876678854
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.223904778
Short name T840
Test name
Test status
Simulation time 355173438 ps
CPU time 7.35 seconds
Started Mar 09 04:53:55 PM PST 24
Finished Mar 09 04:54:03 PM PST 24
Peak memory 208096 kb
Host smart-2beab797-315d-4b71-8296-b5408a603866
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223904778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.223904778
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1231629788
Short name T566
Test name
Test status
Simulation time 218384813 ps
CPU time 5.04 seconds
Started Mar 09 04:54:34 PM PST 24
Finished Mar 09 04:54:40 PM PST 24
Peak memory 209148 kb
Host smart-946d89de-3875-4629-9226-82780a495820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231629788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1231629788
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1277143407
Short name T81
Test name
Test status
Simulation time 83337381 ps
CPU time 1.95 seconds
Started Mar 09 04:53:48 PM PST 24
Finished Mar 09 04:53:50 PM PST 24
Peak memory 207212 kb
Host smart-1b39e57f-1dab-4691-90b7-98eb3bbf2e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277143407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1277143407
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3322287067
Short name T973
Test name
Test status
Simulation time 159512663 ps
CPU time 10.04 seconds
Started Mar 09 04:54:00 PM PST 24
Finished Mar 09 04:54:11 PM PST 24
Peak memory 222556 kb
Host smart-24ae3146-4b4d-4833-ae73-50c26fc30e2b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322287067 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3322287067
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2238745566
Short name T1014
Test name
Test status
Simulation time 2345358908 ps
CPU time 8.61 seconds
Started Mar 09 04:53:46 PM PST 24
Finished Mar 09 04:53:55 PM PST 24
Peak memory 207144 kb
Host smart-1a4120b7-755e-4dba-a084-55c1e9864773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238745566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2238745566
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1813905744
Short name T783
Test name
Test status
Simulation time 418035233 ps
CPU time 3.64 seconds
Started Mar 09 04:53:52 PM PST 24
Finished Mar 09 04:53:56 PM PST 24
Peak memory 210508 kb
Host smart-165df123-b70e-42db-96e9-aba8f4f8b9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813905744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1813905744
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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