Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
71.43	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	17	32	65.31

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	16	19	54.29	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	73	1			T4	1		T28	1		T110	1
auto[OpGenId]	7	1			T48	1		T103	1		T200	1
auto[OpGenSwOut]	19	1			T100	1		T101	1		T201	1
auto[OpGenHwOut]	31	1			T101	1		T102	1		T6	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1813	1			T13	3		T48	1		T100	8
auto[StInit]	144	1			T48	1		T100	2		T35	1
auto[StCreatorRootKey]	58	1			T50	1		T19	1		T20	1
auto[StOwnerIntKey]	41	1			T2	1		T15	1		T48	1
auto[StOwnerKey]	27	1			T28	1		T103	1		T32	1
auto[StDisabled]	317	1			T4	1		T13	7		T15	5
auto[StInvalid]	45	1			T24	1		T36	1		T87	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3393

1

T1

1

T2

2

T3

1

auto[1]

130

1

T4

1

T48

1

T28

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1797	1			T13	3		T48	1		T100	8
auto[StReset]	auto[1]	16	1			T110	1		T103	1		T202	2
auto[StInit]	auto[0]	76	1			T100	1		T35	1		T106	2
auto[StInit]	auto[1]	68	1			T48	1		T100	1		T101	2
auto[StCreatorRootKey]	auto[0]	38	1			T50	1		T19	1		T20	1
auto[StCreatorRootKey]	auto[1]	20	1			T41	1		T52	1		T57	1
auto[StOwnerIntKey]	auto[0]	32	1			T2	1		T15	1		T48	1
auto[StOwnerIntKey]	auto[1]	9	1			T201	1		T29	1		T136	1
auto[StOwnerKey]	auto[0]	17	1			T103	1		T32	1		T37	1
auto[StOwnerKey]	auto[1]	10	1			T28	1		T33	1		T140	1
auto[StDisabled]	auto[0]	310	1			T13	7		T15	5		T48	2
auto[StDisabled]	auto[1]	7	1			T4	1		T203	1		T204	1
auto[StInvalid]	auto[0]	45	1			T24	1		T36	1		T87	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	16	19	54.29	16

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpGenId]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	16	1			T110	1		T103	1		T202	2
auto[StInit]	auto[OpAdvance]	31	1			T103	1		T122	1		T42	1
auto[StInit]	auto[OpGenId]	5	1			T48	1		T103	1		T205	1
auto[StInit]	auto[OpGenSwOut]	12	1			T100	1		T101	1		T201	1
auto[StInit]	auto[OpGenHwOut]	20	1			T101	1		T102	1		T6	1
auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T41	1		T52	1		T57	1
auto[StCreatorRootKey]	auto[OpGenId]	1	1			T200	1		-	-		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T206	1		T207	1		T208	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	6	1			T46	1		T209	1		T210	1
auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T201	1		T136	1		T211	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T29	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	2	1			T212	1		T10	1		-	-
auto[StOwnerKey]	auto[OpAdvance]	7	1			T28	1		T33	1		T140	1
auto[StOwnerKey]	auto[OpGenId]	1	1			T213	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T58	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T57	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	4	1			T4	1		T203	1		T214	1
auto[StDisabled]	auto[OpGenSwOut]	1	1			T204	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	2	1			T212	1		T215	1		-	-