Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.05	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	76	254	76.97

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	57	223	79.64	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4337

1

T1

2

T3

4

T4

4

auto[1]

547

1

T14

2

T15

4

T18

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4337

1

T1

2

T3

4

T4

4

auto[1]

547

1

T14

2

T15

4

T18

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4378

1

T1

2

T3

4

T4

4

auto[1]

506

1

T13

3

T78

6

T81

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4378

1

T1

2

T3

4

T4

4

auto[1]

506

1

T13

3

T78

6

T81

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	385	1			T4	1		T13	2		T79	3
auto[OpGenId]	989	1			T3	1		T13	14		T15	9
auto[OpGenSwOut]	985	1			T1	1		T3	3		T4	2
auto[OpGenHwOut]	2467	1			T4	1		T13	6		T14	9
auto[OpDisable]	58	1			T1	1		T18	1		T62	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	385	1			T4	1		T13	2		T79	3
auto[OpGenId]	989	1			T3	1		T13	14		T15	9
auto[OpGenSwOut]	985	1			T1	1		T3	3		T4	2
auto[OpGenHwOut]	2467	1			T4	1		T13	6		T14	9
auto[OpDisable]	58	1			T1	1		T18	1		T62	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4387

1

T1

2

T3

4

T4

4

auto[1]

497

1

T13

1

T15

3

T16

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4387

1

T1

2

T3

4

T4

4

auto[1]

497

1

T13

1

T15

3

T16

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4598

1

T1

2

T3

4

T4

4

auto[1]

286

1

T79

6

T81

5

T115

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1691	1			T1	1		T3	2		T4	1
auto[1]	602	1			T13	3		T14	3		T15	2
auto[2]	656	1			T1	1		T3	1		T4	1
auto[3]	641	1			T13	4		T14	1		T15	4
auto[4]	333	1			T3	1		T4	1		T13	4
auto[5]	323	1			T4	1		T13	2		T16	2
auto[6]	330	1			T13	1		T14	1		T15	1
auto[7]	308	1			T14	1		T15	2		T16	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1294	1			T3	1		T4	2		T13	7
clear_one[1]	602	1			T13	3		T14	3		T15	2
clear_one[2]	656	1			T1	1		T3	1		T4	1
clear_one[3]	641	1			T13	4		T14	1		T15	4
clear_none	1691	1			T1	1		T3	2		T4	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	917	1			T3	2		T13	10		T14	1
auto[StInit]	688	1			T4	1		T13	2		T14	1
auto[StCreatorRootKey]	521	1			T3	1		T4	1		T13	3
auto[StOwnerIntKey]	464	1			T3	1		T13	4		T14	1
auto[StOwnerKey]	445	1			T4	1		T13	3		T14	1
auto[StDisabled]	1688	1			T1	2		T4	1		T13	5
auto[StInvalid]	161	1			T24	4		T36	1		T87	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	917	1			T3	2		T13	10		T14	1
auto[StInit]	688	1			T4	1		T13	2		T14	1
auto[StCreatorRootKey]	521	1			T3	1		T4	1		T13	3
auto[StOwnerIntKey]	464	1			T3	1		T13	4		T14	1
auto[StOwnerKey]	445	1			T4	1		T13	3		T14	1
auto[StDisabled]	1688	1			T1	2		T4	1		T13	5
auto[StInvalid]	161	1			T24	4		T36	1		T87	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	57	223	79.64	57

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[2]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[3]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[3]]	[auto[StInvalid]]	[auto[OpGenId]]	0	1	1
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	4
[auto[4] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	4
[auto[4] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	16
[auto[4] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	4

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T216	1		T217	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	137	1			T13	2		T15	1		T81	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	145	1			T3	1		T13	1		T48	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	267	1			T13	2		T14	1		T79	1
auto[0]	auto[StInit]	auto[OpAdvance]	52	1			T183	1		T188	1		T103	1
auto[0]	auto[StInit]	auto[OpGenId]	78	1			T13	1		T61	1		T31	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	91	1			T4	1		T13	1		T15	2
auto[0]	auto[StInit]	auto[OpGenHwOut]	170	1			T15	1		T16	1		T17	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	16	1			T13	1		T88	1		T218	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	47	1			T48	1		T20	1		T199	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	42	1			T48	1		T88	1		T219	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	76	1			T18	1		T78	1		T123	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	16	1			T27	1		T103	1		T45	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	31	1			T125	4		T54	1		T199	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T3	1		T41	1		T220	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	55	1			T13	1		T15	1		T78	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T219	1		T221	1		T222	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	21	1			T73	1		T223	1		T224	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T13	1		T190	1		T225	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T107	1		T180	1		T226	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	20	1			T79	2		T199	1		T227	1
auto[0]	auto[StDisabled]	auto[OpGenId]	47	1			T15	3		T48	1		T85	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	49	1			T15	1		T79	3		T228	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	190	1			T17	2		T78	2		T188	1
auto[0]	auto[StDisabled]	auto[OpDisable]	18	1			T1	1		T229	1		T230	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	7	1			T186	1		T231	1		T232	1
auto[0]	auto[StInvalid]	auto[OpGenId]	11	1			T87	1		T95	1		T233	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T233	1		T234	1		T235	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T179	1		T194	1		T236	1
auto[1]	auto[StReset]	auto[OpGenId]	14	1			T13	1		T115	1		T184	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	21	1			T36	1		T176	1		T37	2
auto[1]	auto[StReset]	auto[OpGenHwOut]	34	1			T24	1		T195	3		T237	1
auto[1]	auto[StInit]	auto[OpAdvance]	11	1			T81	1		T115	1		T26	1
auto[1]	auto[StInit]	auto[OpGenId]	14	1			T81	1		T115	1		T89	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	8	1			T211	1		T58	1		T238	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	22	1			T14	1		T26	1		T239	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T240	1		T241	1		T242	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T28	1		T227	1		T243	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T81	1		T115	1		T189	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T13	1		T192	1		T244	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T79	1		T245	1		T57	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T41	1		T246	1		T247	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T248	1		T68	1		T249	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T250	1		T251	1		T252	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T253	1		T82	1		T254	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	12	1			T255	1		T256	1		T257	2
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T178	1		T125	2		T258	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T13	1		T14	1		T78	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	16	1			T6	1		T125	1		T253	1
auto[1]	auto[StDisabled]	auto[OpGenId]	49	1			T15	2		T79	1		T62	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T61	1		T125	1		T259	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	144	1			T14	1		T16	2		T78	1
auto[1]	auto[StDisabled]	auto[OpDisable]	13	1			T55	1		T45	1		T211	1
auto[1]	auto[StInvalid]	auto[OpGenId]	9	1			T87	1		T197	1		T231	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T95	1		T179	1		T84	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T235	1		T260	1		T261	1
auto[2]	auto[StReset]	auto[OpGenId]	23	1			T13	1		T48	1		T42	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	16	1			T62	1		T211	1		T46	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	32	1			T48	1		T237	1		T41	1
auto[2]	auto[StInit]	auto[OpAdvance]	6	1			T6	1		T93	1		T262	1
auto[2]	auto[StInit]	auto[OpGenId]	14	1			T103	1		T86	2		T263	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	16	1			T25	1		T264	1		T90	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	19	1			T15	1		T25	3		T195	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T4	1		T212	1		T68	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T13	1		T62	2		T265	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T3	1		T79	2		T31	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	47	1			T16	1		T120	1		T266	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T188	1		T267	1		T203	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T13	1		T246	1		T211	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T15	1		T49	1		T268	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T192	1		T196	1		T201	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T115	1		T62	1		T220	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	15	1			T55	1		T211	1		T57	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T32	1		T6	1		T62	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	29	1			T109	1		T193	1		T250	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	35	1			T115	2		T48	1		T187	1
auto[2]	auto[StDisabled]	auto[OpGenId]	35	1			T85	1		T219	1		T199	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	49	1			T1	1		T48	2		T6	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T14	1		T17	1		T191	1
auto[2]	auto[StDisabled]	auto[OpDisable]	4	1			T62	1		T54	1		T269	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T270	1		T271	1		T272	1
auto[2]	auto[StInvalid]	auto[OpGenId]	7	1			T179	1		T184	1		T60	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T24	1		T36	1		T95	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T184	1		T236	1		T273	1
auto[3]	auto[StReset]	auto[OpGenId]	20	1			T13	2		T28	1		T274	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	20	1			T79	1		T233	1		T45	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	42	1			T193	1		T250	2		T237	1
auto[3]	auto[StInit]	auto[OpAdvance]	6	1			T25	1		T275	1		T276	1
auto[3]	auto[StInit]	auto[OpGenId]	12	1			T263	1		T275	1		T277	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	20	1			T25	1		T26	1		T62	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	24	1			T266	1		T6	1		T278	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T88	1		T248	1		T279	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T61	1		T280	1		T281	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T15	1		T282	1		T245	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T107	1		T108	1		T283	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T253	1		T284	1		T285	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T81	2		T286	1		T278	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T48	1		T6	1		T212	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	53	1			T15	1		T17	1		T81	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T187	1		T72	1		T287	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	13	1			T15	1		T6	1		T288	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T15	1		T289	1		T290	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	28	1			T17	1		T123	1		T108	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	23	1			T45	2		T291	1		T292	1
auto[3]	auto[StDisabled]	auto[OpGenId]	45	1			T13	2		T48	1		T293	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T80	2		T198	1		T225	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	144	1			T14	1		T188	1		T123	1
auto[3]	auto[StDisabled]	auto[OpDisable]	8	1			T45	1		T211	1		T294	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	8	1			T24	1		T179	1		T194	2
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T233	1		T295	1		-	-
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T87	1		T232	1		T273	1
auto[4]	auto[StReset]	auto[OpGenId]	6	1			T3	1		T45	1		T34	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	6	1			T13	1		T211	1		T46	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	21	1			T252	1		T82	1		T296	1
auto[4]	auto[StInit]	auto[OpAdvance]	6	1			T293	1		T297	1		T298	1
auto[4]	auto[StInit]	auto[OpGenId]	5	1			T280	1		T90	1		T299	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	3	1			T65	1		T199	1		T57	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	24	1			T65	1		T300	1		T301	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T246	1		T57	1		T302	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T82	1		T74	1		T303	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T80	1		T6	1		T304	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T14	1		T305	1		T193	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T211	1		T306	1		T307	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T13	1		T274	1		T302	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T48	1		T88	1		T211	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T266	1		T288	1		T293	3
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T81	1		T308	1		T309	2
auto[4]	auto[StOwnerKey]	auto[OpGenId]	5	1			T211	1		T207	1		T310	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T13	1		T27	1		T93	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T4	1		T305	1		T266	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	8	1			T85	1		T227	1		T311	1
auto[4]	auto[StDisabled]	auto[OpGenId]	28	1			T13	1		T115	2		T199	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T81	1		T188	1		T6	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	68	1			T17	1		T195	1		T266	1
auto[4]	auto[StDisabled]	auto[OpDisable]	3	1			T312	1		T313	1		T279	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T314	1		T315	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	3	1			T186	1		T60	1		T316	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T87	1		T261	1		T317	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T24	1		T60	1		T84	1
auto[5]	auto[StReset]	auto[OpGenId]	8	1			T81	1		T275	1		T318	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	7	1			T82	1		T319	1		T320	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	18	1			T80	1		T244	1		T321	1
auto[5]	auto[StInit]	auto[OpAdvance]	1	1			T322	1		-	-		-	-
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T277	2		T323	1		T207	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	8	1			T48	1		T86	1		T324	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	13	1			T237	1		T243	1		T325	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T326	1		T327	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T328	1		T46	1		T318	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T329	1		T318	1		T207	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T330	1		T321	1		T239	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T259	1		T331	1		T332	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T91	1		T268	1		T333	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T115	1		T180	1		T280	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T13	1		T334	1		T335	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T68	2		-	-		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	7	1			T259	1		T56	1		T336	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T228	1		T337	1		T338	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	29	1			T195	1		T196	1		T339	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	12	1			T27	1		T88	1		T340	1
auto[5]	auto[StDisabled]	auto[OpGenId]	27	1			T13	1		T85	1		T225	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T4	1		T79	1		T80	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	74	1			T16	2		T79	1		T107	1
auto[5]	auto[StDisabled]	auto[OpDisable]	6	1			T18	1		T341	1		T46	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T233	1		T342	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	2	1			T343	1		T270	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T316	1		T344	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T179	1		T194	1		T234	1
auto[6]	auto[StReset]	auto[OpGenId]	13	1			T24	1		T29	1		T245	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	5	1			T330	1		T345	1		T57	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	20	1			T300	1		T321	1		T301	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T24	1		T25	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	7	1			T36	1		T45	1		T346	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	5	1			T45	1		T304	1		T38	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	13	1			T193	1		T347	1		T348	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T302	1		T349	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T199	2		T350	1		T351	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T352	1		T353	1		T354	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	13	1			T17	1		T355	1		T296	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T356	1		T357	1		T358	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T61	1		T64	1		T359	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T93	1		T324	1		T341	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T14	1		T109	1		T37	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T254	1		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T332	1		T360	1		T361	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T46	1		T60	1		T362	2
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T198	1		T283	1		T237	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	10	1			T13	1		T362	2		T216	1
auto[6]	auto[StDisabled]	auto[OpGenId]	31	1			T15	1		T125	1		T199	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	22	1			T199	1		T41	1		T211	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	86	1			T78	1		T108	1		T305	1
auto[6]	auto[StDisabled]	auto[OpDisable]	1	1			T292	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T342	1		T363	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T24	1		T95	2		T84	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T197	1		T184	1		T84	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T364	1		T365	1		T319	1
auto[7]	auto[StReset]	auto[OpGenId]	9	1			T275	1		T45	2		T57	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	9	1			T48	1		T24	1		T265	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	22	1			T115	1		T195	1		T76	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T89	1		T366	1		T367	1
auto[7]	auto[StInit]	auto[OpGenId]	5	1			T90	1		T268	1		T238	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	5	1			T26	2		T270	1		T94	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	19	1			T48	1		T32	1		T263	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T211	1		T368	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T45	1		T369	1		T370	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T199	1		T212	1		T292	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	26	1			T191	1		T85	1		T109	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T178	1		T371	1		T241	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T219	1		T199	1		T372	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T228	1		T82	1		T373	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	13	1			T16	1		T283	1		T237	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T6	1		T374	1		T375	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	10	1			T253	1		T246	1		T211	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T376	1		T377	1		T279	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T16	1		T192	1		T6	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	9	1			T227	1		T378	1		T379	1
auto[7]	auto[StDisabled]	auto[OpGenId]	23	1			T15	1		T6	2		T278	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	13	1			T198	1		T199	1		T211	2
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	70	1			T14	1		T15	1		T123	1
auto[7]	auto[StDisabled]	auto[OpDisable]	5	1			T45	1		T380	1		T381	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	1	1			T236	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	4	1			T235	1		T295	1		T271	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T236	1		T319	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T231	1		T343	1		T382	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1294

1

T3

1

T4

2

T13

7

clear_one[1]

auto[0]

auto[0]

auto[0]

338

1

T13

2

T14

3

T79

1

clear_one[1]

auto[0]

auto[0]

auto[1]

124

1

T13

1

T15

2

T16

2

clear_one[1]

auto[0]

auto[1]

auto[0]

111

1

T78

2

T176

1

T195

1

clear_one[1]

auto[0]

auto[1]

auto[1]

29

1

T255

1

T383

1

T257

4

clear_one[2]

auto[0]

auto[0]

auto[0]

387

1

T1

1

T3

1

T4

1

clear_one[2]

auto[0]

auto[0]

auto[1]

97

1

T16

1

T17

1

T123

1

clear_one[2]

auto[1]

auto[0]

auto[0]

132

1

T14

1

T188

1

T48

2

clear_one[2]

auto[1]

auto[0]

auto[1]

40

1

T62

2

T384

1

T282

1

clear_one[3]

auto[0]

auto[0]

auto[0]

368

1

T13

3

T15

3

T17

2

clear_one[3]

auto[0]

auto[1]

auto[0]

114

1

T13

1

T81

2

T61

1

clear_one[3]

auto[1]

auto[0]

auto[0]

119

1

T14

1

T15

1

T48

1

clear_one[3]

auto[1]

auto[1]

auto[0]

40

1

T188

1

T176

1

T280

1

clear_none

auto[0]

auto[0]

auto[0]

1181

1

T1

1

T3

2

T4

1

clear_none

auto[0]

auto[0]

auto[1]

128

1

T15

1

T17

2

T79

1

clear_none

auto[0]

auto[1]

auto[0]

145

1

T13

2

T78

4

T109

1

clear_none

auto[0]

auto[1]

auto[1]

21

1

T198

1

T223

1

T385

1

clear_none

auto[1]

auto[0]

auto[0]

134

1

T15

3

T18

1

T191

1

clear_none

auto[1]

auto[0]

auto[1]

36

1

T79

1

T190

1

T264

2

clear_none

auto[1]

auto[1]

auto[0]

24

1

T188

1

T62

1

T45

1

clear_none

auto[1]

auto[1]

auto[1]

22

1

T199

1

T73

1

T386

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1233	1			T3	1		T4	2		T13	7
clear_all	auto[1]	61	1			T79	1		T81	1		T115	1
clear_one[1]	auto[0]	560	1			T13	3		T14	3		T15	2
clear_one[1]	auto[1]	42	1			T79	1		T81	2		T115	2
clear_one[2]	auto[0]	618	1			T1	1		T3	1		T4	1
clear_one[2]	auto[1]	38	1			T79	1		T115	1		T267	2
clear_one[3]	auto[0]	592	1			T13	4		T14	1		T15	4
clear_one[3]	auto[1]	49	1			T81	2		T293	1		T72	4
clear_none	auto[0]	1595	1			T1	1		T3	2		T4	1
clear_none	auto[1]	96	1			T79	3		T125	3		T267	1