Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10722

1

T1

1

T2

4

T3

12

auto[Attestation]

7603

1

T1

2

T2

3

T3

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2628	1			T1	1		T3	2		T4	3
auto[Aes]	3384	1			T2	2		T3	2		T4	1
auto[Kmac]	3285	1			T2	2		T3	4		T4	2
auto[Otbn]	3359	1			T3	3		T4	3		T13	19

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7204	1			T1	2		T2	3		T3	3
auto[OpGenId]	5669	1			T1	2		T2	3		T3	4
auto[OpGenSwOut]	5804	1			T1	1		T2	1		T3	6
auto[OpGenHwOut]	6852	1			T2	3		T3	5		T4	4
auto[OpDisable]	117	1			T1	1		T13	1		T15	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9436

1

T1

2

T2

7

T3

9

auto[OpDoneFail]

16210

1

T1

4

T2

3

T3

9

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6242	1			T1	1		T2	1		T3	10
auto[StInit]	3965	1			T1	3		T2	4		T3	1
auto[StCreatorRootKey]	2849	1			T2	3		T3	3		T4	1
auto[StOwnerIntKey]	2434	1			T2	2		T3	4		T4	4
auto[StOwnerKey]	2132	1			T4	4		T13	25		T14	2
auto[StDisabled]	6976	1			T1	2		T4	3		T13	58
auto[StInvalid]	1048	1			T24	26		T36	16		T87	29

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	340	1			T13	3		T79	1		T100	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	119	1			T4	1		T48	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	57	1			T79	1		T176	1		T177	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	69	1			T3	1		T4	1		T48	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	62	1			T13	2		T79	1		T178	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	185	1			T1	1		T13	2		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	33	1			T24	1		T95	3		T179	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	348	1			T3	1		T13	2		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	97	1			T48	1		T21	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	69	1			T3	1		T13	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	60	1			T13	1		T180	1		T181	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	59	1			T182	1		T178	2		T125	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	198	1			T13	1		T79	2		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	38	1			T24	1		T87	2		T95	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	301	1			T3	3		T13	2		T35	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	108	1			T15	2		T103	2		T25	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	79	1			T13	1		T115	1		T176	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	65	1			T13	2		T115	1		T183	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	43	1			T4	1		T27	1		T120	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	177	1			T13	2		T15	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	25	1			T24	1		T95	2		T184	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	281	1			T13	1		T81	2		T115	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	114	1			T13	1		T15	2		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T13	1		T15	2		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	87	1			T15	1		T28	2		T120	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	43	1			T48	1		T180	1		T185	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	181	1			T4	1		T13	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	30	1			T24	1		T36	1		T87	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	73	1			T13	1		T15	1		T103	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	104	1			T13	1		T15	2		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	69	1			T13	1		T62	2		T49	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	73	1			T15	1		T48	1		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	45	1			T13	1		T15	2		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	181	1			T13	2		T15	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	31	1			T36	2		T186	1		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	77	1			T13	1		T48	1		T102	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	125	1			T13	1		T15	2		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	69	1			T115	1		T183	1		T187	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	50	1			T2	1		T180	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	63	1			T61	1		T103	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	192	1			T13	1		T188	1		T85	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	37	1			T24	2		T36	2		T87	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	76	1			T13	2		T15	1		T48	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	129	1			T15	1		T48	1		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	86	1			T79	2		T80	1		T115	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	50	1			T182	1		T6	1		T93	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	43	1			T13	2		T103	1		T178	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	202	1			T15	1		T18	1		T188	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	36	1			T24	2		T87	1		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	75	1			T24	2		T103	2		T6	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	117	1			T35	1		T61	1		T103	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	79	1			T15	1		T79	2		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	74	1			T36	1		T49	2		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	53	1			T4	1		T32	1		T190	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	205	1			T13	3		T15	2		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	34	1			T87	2		T186	1		T95	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	240	1			T3	1		T13	4		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	100	1			T35	1		T103	1		T21	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	70	1			T13	1		T27	1		T188	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	49	1			T13	1		T81	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	39	1			T13	2		T180	1		T176	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	147	1			T13	2		T15	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	29	1			T87	1		T186	1		T95	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	479	1			T14	4		T79	2		T191	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	125	1			T15	1		T192	1		T178	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	104	1			T2	1		T14	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	87	1			T4	1		T13	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	66	1			T14	1		T193	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	237	1			T13	2		T14	1		T15	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	28	1			T24	1		T87	1		T194	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	429	1			T13	1		T79	1		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	127	1			T15	1		T100	1		T26	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T13	2		T78	1		T61	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	90	1			T2	1		T13	1		T183	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	88	1			T103	1		T195	1		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	286	1			T78	2		T27	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	34	1			T87	1		T186	1		T197	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	462	1			T3	1		T13	2		T81	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	124	1			T13	1		T15	1		T115	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	108	1			T13	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	89	1			T3	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	64	1			T13	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	245	1			T13	1		T15	3		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	41	1			T24	2		T87	2		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	58	1			T13	2		T15	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	117	1			T15	2		T48	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T13	2		T53	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	46	1			T13	2		T186	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	40	1			T80	1		T180	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	150	1			T4	1		T188	4		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	29	1			T24	1		T179	1		T184	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	54	1			T13	3		T15	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	125	1			T13	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	109	1			T18	1		T188	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	93	1			T13	1		T14	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	84	1			T13	1		T191	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	278	1			T13	2		T14	3		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	33	1			T24	1		T95	1		T179	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	50	1			T103	1		T122	2		T199	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	134	1			T2	1		T4	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T53	1		T198	1		T195	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	76	1			T3	1		T78	1		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	63	1			T13	1		T78	1		T109	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	254	1			T78	2		T79	1		T188	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	38	1			T36	1		T87	1		T186	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	47	1			T13	2		T15	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	117	1			T13	1		T16	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T123	1		T107	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	95	1			T3	1		T13	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	95	1			T4	1		T13	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	270	1			T15	2		T16	3		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	37	1			T24	1		T36	1		T87	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	175	1			T3	1		T4	1		T13	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	690	1			T1	1		T4	1		T13	5
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	168	1			T3	1		T13	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	701	1			T3	1		T13	3		T79	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	175	1			T4	1		T13	3		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	623	1			T3	3		T13	4		T15	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	202	1			T13	1		T15	3		T81	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	622	1			T4	1		T13	3		T15	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	181	1			T13	2		T15	3		T48	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	395	1			T13	4		T15	4		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	177	1			T2	1		T115	1		T183	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	436	1			T13	3		T15	2		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	163	1			T13	1		T79	2		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	459	1			T13	3		T15	3		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	191	1			T4	1		T15	1		T79	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	446	1			T13	3		T15	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	150	1			T13	2		T81	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	524	1			T3	1		T13	8		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	247	1			T2	1		T4	1		T14	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	879	1			T13	3		T14	5		T15	5
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	261	1			T2	1		T13	3		T78	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	893	1			T13	1		T15	1		T78	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	251	1			T3	1		T13	2		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	882	1			T3	1		T13	5		T15	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	145	1			T13	4		T80	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	368	1			T4	1		T13	2		T15	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	267	1			T14	1		T18	1		T188	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	509	1			T13	8		T14	4		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	229	1			T3	1		T13	1		T78	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	482	1			T2	1		T4	1		T78	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	283	1			T3	1		T4	1		T13	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	482	1			T13	3		T15	3		T16	4