Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29344

1

T1

8

T2

11

T3

20

auto[1]

334

1

T79

4

T81

5

T115

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	29351	1			T1	8		T2	11		T3	20
auto[134217728:268435455]	13	1			T79	1		T125	2		T72	1
auto[268435456:402653183]	8	1			T407	1		T408	1		T309	1
auto[402653184:536870911]	6	1			T115	1		T125	1		T253	1
auto[536870912:671088639]	8	1			T336	1		T254	1		T409	1
auto[671088640:805306367]	8	1			T125	1		T336	1		T221	1
auto[805306368:939524095]	13	1			T267	1		T72	2		T336	1
auto[939524096:1073741823]	16	1			T115	1		T72	1		T257	1
auto[1073741824:1207959551]	16	1			T115	1		T125	1		T253	1
auto[1207959552:1342177279]	16	1			T115	1		T336	1		T221	1
auto[1342177280:1476395007]	10	1			T221	1		T362	1		T318	1
auto[1476395008:1610612735]	10	1			T125	1		T410	1		T411	1
auto[1610612736:1744830463]	9	1			T81	1		T407	1		T412	1
auto[1744830464:1879048191]	13	1			T125	1		T408	2		T409	1
auto[1879048192:2013265919]	6	1			T257	1		T217	1		T309	1
auto[2013265920:2147483647]	5	1			T309	1		T241	1		T413	2
auto[2147483648:2281701375]	12	1			T253	1		T407	3		T318	1
auto[2281701376:2415919103]	14	1			T125	1		T267	1		T336	1
auto[2415919104:2550136831]	15	1			T79	1		T81	1		T115	1
auto[2550136832:2684354559]	7	1			T293	1		T407	1		T318	1
auto[2684354560:2818572287]	8	1			T72	1		T409	1		T411	1
auto[2818572288:2952790015]	8	1			T309	2		T411	1		T241	1
auto[2952790016:3087007743]	13	1			T407	1		T408	1		T309	1
auto[3087007744:3221225471]	9	1			T115	1		T221	2		T407	1
auto[3221225472:3355443199]	9	1			T125	1		T72	1		T318	1
auto[3355443200:3489660927]	13	1			T81	1		T267	1		T410	1
auto[3489660928:3623878655]	8	1			T81	2		T72	1		T409	1
auto[3623878656:3758096383]	9	1			T79	1		T409	1		T414	2
auto[3758096384:3892314111]	10	1			T336	1		T298	2		T309	1
auto[3892314112:4026531839]	10	1			T79	1		T253	1		T407	1
auto[4026531840:4160749567]	13	1			T72	1		T336	1		T407	1
auto[4160749568:4294967295]	12	1			T72	1		T336	1		T362	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	29344	1			T1	8		T2	11		T3	20
auto[0:134217727]	auto[1]	7	1			T267	1		T293	1		T72	1
auto[134217728:268435455]	auto[1]	13	1			T79	1		T125	2		T72	1
auto[268435456:402653183]	auto[1]	8	1			T407	1		T408	1		T309	1
auto[402653184:536870911]	auto[1]	6	1			T115	1		T125	1		T253	1
auto[536870912:671088639]	auto[1]	8	1			T336	1		T254	1		T409	1
auto[671088640:805306367]	auto[1]	8	1			T125	1		T336	1		T221	1
auto[805306368:939524095]	auto[1]	13	1			T267	1		T72	2		T336	1
auto[939524096:1073741823]	auto[1]	16	1			T115	1		T72	1		T257	1
auto[1073741824:1207959551]	auto[1]	16	1			T115	1		T125	1		T253	1
auto[1207959552:1342177279]	auto[1]	16	1			T115	1		T336	1		T221	1
auto[1342177280:1476395007]	auto[1]	10	1			T221	1		T362	1		T318	1
auto[1476395008:1610612735]	auto[1]	10	1			T125	1		T410	1		T411	1
auto[1610612736:1744830463]	auto[1]	9	1			T81	1		T407	1		T412	1
auto[1744830464:1879048191]	auto[1]	13	1			T125	1		T408	2		T409	1
auto[1879048192:2013265919]	auto[1]	6	1			T257	1		T217	1		T309	1
auto[2013265920:2147483647]	auto[1]	5	1			T309	1		T241	1		T413	2
auto[2147483648:2281701375]	auto[1]	12	1			T253	1		T407	3		T318	1
auto[2281701376:2415919103]	auto[1]	14	1			T125	1		T267	1		T336	1
auto[2415919104:2550136831]	auto[1]	15	1			T79	1		T81	1		T115	1
auto[2550136832:2684354559]	auto[1]	7	1			T293	1		T407	1		T318	1
auto[2684354560:2818572287]	auto[1]	8	1			T72	1		T409	1		T411	1
auto[2818572288:2952790015]	auto[1]	8	1			T309	2		T411	1		T241	1
auto[2952790016:3087007743]	auto[1]	13	1			T407	1		T408	1		T309	1
auto[3087007744:3221225471]	auto[1]	9	1			T115	1		T221	2		T407	1
auto[3221225472:3355443199]	auto[1]	9	1			T125	1		T72	1		T318	1
auto[3355443200:3489660927]	auto[1]	13	1			T81	1		T267	1		T410	1
auto[3489660928:3623878655]	auto[1]	8	1			T81	2		T72	1		T409	1
auto[3623878656:3758096383]	auto[1]	9	1			T79	1		T409	1		T414	2
auto[3758096384:3892314111]	auto[1]	10	1			T336	1		T298	2		T309	1
auto[3892314112:4026531839]	auto[1]	10	1			T79	1		T253	1		T407	1
auto[4026531840:4160749567]	auto[1]	13	1			T72	1		T336	1		T407	1
auto[4160749568:4294967295]	auto[1]	12	1			T72	1		T336	1		T362	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1450

1

T1

1

T13

8

T15

12

auto[1]

1554

1

T3

4

T4

3

T13

14

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T183	1		T28	1		T103	1
auto[134217728:268435455]	85	1			T3	1		T81	1		T24	1
auto[268435456:402653183]	97	1			T4	1		T13	1		T15	1
auto[402653184:536870911]	109	1			T15	1		T61	1		T176	1
auto[536870912:671088639]	92	1			T13	1		T15	1		T115	1
auto[671088640:805306367]	93	1			T3	1		T13	2		T79	1
auto[805306368:939524095]	102	1			T15	1		T18	1		T27	1
auto[939524096:1073741823]	89	1			T15	1		T115	1		T100	1
auto[1073741824:1207959551]	73	1			T85	1		T53	1		T6	2
auto[1207959552:1342177279]	82	1			T100	1		T24	1		T103	1
auto[1342177280:1476395007]	91	1			T13	1		T79	1		T28	2
auto[1476395008:1610612735]	101	1			T13	1		T79	1		T85	1
auto[1610612736:1744830463]	85	1			T13	1		T188	1		T100	1
auto[1744830464:1879048191]	89	1			T13	1		T26	1		T393	1
auto[1879048192:2013265919]	102	1			T13	1		T15	1		T18	1
auto[2013265920:2147483647]	75	1			T15	2		T81	1		T48	1
auto[2147483648:2281701375]	95	1			T103	1		T180	1		T186	1
auto[2281701376:2415919103]	92	1			T13	1		T48	1		T24	1
auto[2415919104:2550136831]	82	1			T81	1		T188	1		T100	1
auto[2550136832:2684354559]	79	1			T15	1		T115	1		T85	1
auto[2684354560:2818572287]	111	1			T13	1		T15	1		T27	1
auto[2818572288:2952790015]	95	1			T13	1		T79	1		T115	1
auto[2952790016:3087007743]	95	1			T1	1		T103	1		T36	1
auto[3087007744:3221225471]	91	1			T4	1		T15	1		T48	1
auto[3221225472:3355443199]	103	1			T13	1		T15	2		T115	2
auto[3355443200:3489660927]	109	1			T3	1		T13	1		T15	1
auto[3489660928:3623878655]	89	1			T13	2		T180	1		T120	1
auto[3623878656:3758096383]	98	1			T13	1		T15	2		T61	1
auto[3758096384:3892314111]	87	1			T53	1		T36	1		T229	1
auto[3892314112:4026531839]	103	1			T3	1		T13	2		T15	1
auto[4026531840:4160749567]	103	1			T4	1		T13	1		T15	1
auto[4160749568:4294967295]	101	1			T13	2		T61	2		T36	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T190	1		T199	1		T179	1
auto[0:134217727]	auto[1]	61	1			T183	1		T28	1		T103	1
auto[134217728:268435455]	auto[0]	41	1			T81	1		T24	1		T103	1
auto[134217728:268435455]	auto[1]	44	1			T3	1		T32	1		T178	1
auto[268435456:402653183]	auto[0]	54	1			T13	1		T102	1		T50	1
auto[268435456:402653183]	auto[1]	43	1			T4	1		T15	1		T27	1
auto[402653184:536870911]	auto[0]	42	1			T176	1		T50	1		T6	2
auto[402653184:536870911]	auto[1]	67	1			T15	1		T61	1		T198	1
auto[536870912:671088639]	auto[0]	45	1			T15	1		T115	1		T53	1
auto[536870912:671088639]	auto[1]	47	1			T13	1		T31	1		T176	1
auto[671088640:805306367]	auto[0]	53	1			T13	1		T102	1		T87	1
auto[671088640:805306367]	auto[1]	40	1			T3	1		T13	1		T79	1
auto[805306368:939524095]	auto[0]	51	1			T15	1		T18	1		T180	1
auto[805306368:939524095]	auto[1]	51	1			T27	1		T61	1		T198	1
auto[939524096:1073741823]	auto[0]	44	1			T115	1		T100	1		T53	1
auto[939524096:1073741823]	auto[1]	45	1			T15	1		T24	1		T103	1
auto[1073741824:1207959551]	auto[0]	39	1			T85	1		T53	1		T62	1
auto[1073741824:1207959551]	auto[1]	34	1			T6	2		T263	1		T219	1
auto[1207959552:1342177279]	auto[0]	47	1			T24	1		T103	1		T25	1
auto[1207959552:1342177279]	auto[1]	35	1			T100	1		T120	1		T219	1
auto[1342177280:1476395007]	auto[0]	38	1			T79	1		T28	1		T259	1
auto[1342177280:1476395007]	auto[1]	53	1			T13	1		T28	1		T180	1
auto[1476395008:1610612735]	auto[0]	50	1			T85	1		T32	1		T6	1
auto[1476395008:1610612735]	auto[1]	51	1			T13	1		T79	1		T187	1
auto[1610612736:1744830463]	auto[0]	45	1			T13	1		T188	1		T85	1
auto[1610612736:1744830463]	auto[1]	40	1			T100	1		T32	1		T93	1
auto[1744830464:1879048191]	auto[0]	40	1			T13	1		T26	1		T62	1
auto[1744830464:1879048191]	auto[1]	49	1			T393	1		T264	1		T90	1
auto[1879048192:2013265919]	auto[0]	41	1			T15	1		T25	1		T263	1
auto[1879048192:2013265919]	auto[1]	61	1			T13	1		T18	1		T48	1
auto[2013265920:2147483647]	auto[0]	30	1			T15	1		T267	1		T175	1
auto[2013265920:2147483647]	auto[1]	45	1			T15	1		T81	1		T48	1
auto[2147483648:2281701375]	auto[0]	35	1			T62	1		T229	1		T179	1
auto[2147483648:2281701375]	auto[1]	60	1			T103	1		T180	1		T186	1
auto[2281701376:2415919103]	auto[0]	44	1			T36	1		T93	1		T330	1
auto[2281701376:2415919103]	auto[1]	48	1			T13	1		T48	1		T24	1
auto[2415919104:2550136831]	auto[0]	44	1			T81	1		T188	1		T100	1
auto[2415919104:2550136831]	auto[1]	38	1			T36	1		T50	1		T41	1
auto[2550136832:2684354559]	auto[0]	40	1			T15	1		T115	1		T85	1
auto[2550136832:2684354559]	auto[1]	39	1			T264	1		T90	1		T55	1
auto[2684354560:2818572287]	auto[0]	54	1			T180	1		T6	1		T86	1
auto[2684354560:2818572287]	auto[1]	57	1			T13	1		T15	1		T27	1
auto[2818572288:2952790015]	auto[0]	43	1			T13	1		T103	1		T383	1
auto[2818572288:2952790015]	auto[1]	52	1			T79	1		T115	1		T188	1
auto[2952790016:3087007743]	auto[0]	48	1			T1	1		T36	1		T32	1
auto[2952790016:3087007743]	auto[1]	47	1			T103	1		T198	1		T186	1
auto[3087007744:3221225471]	auto[0]	51	1			T15	1		T48	1		T176	1
auto[3087007744:3221225471]	auto[1]	40	1			T4	1		T53	1		T6	2
auto[3221225472:3355443199]	auto[0]	44	1			T15	2		T36	1		T26	1
auto[3221225472:3355443199]	auto[1]	59	1			T13	1		T115	2		T122	1
auto[3355443200:3489660927]	auto[0]	55	1			T15	1		T48	1		T103	2
auto[3355443200:3489660927]	auto[1]	54	1			T3	1		T13	1		T278	1
auto[3489660928:3623878655]	auto[0]	41	1			T13	1		T120	1		T87	1
auto[3489660928:3623878655]	auto[1]	48	1			T13	1		T180	1		T6	2
auto[3623878656:3758096383]	auto[0]	50	1			T15	2		T21	1		T87	1
auto[3623878656:3758096383]	auto[1]	48	1			T13	1		T61	1		T24	1
auto[3758096384:3892314111]	auto[0]	44	1			T53	1		T36	1		T219	1
auto[3758096384:3892314111]	auto[1]	43	1			T229	1		T201	1		T267	1
auto[3892314112:4026531839]	auto[0]	58	1			T13	1		T24	1		T53	1
auto[3892314112:4026531839]	auto[1]	45	1			T3	1		T13	1		T15	1
auto[4026531840:4160749567]	auto[0]	53	1			T15	1		T48	1		T6	2
auto[4026531840:4160749567]	auto[1]	50	1			T4	1		T13	1		T79	1
auto[4160749568:4294967295]	auto[0]	41	1			T13	1		T61	1		T36	1
auto[4160749568:4294967295]	auto[1]	60	1			T13	1		T61	1		T177	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1458

1

T1

1

T4

1

T13

9

auto[1]

1546

1

T3

4

T4

2

T13

13

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T13	2		T61	1		T26	1
auto[134217728:268435455]	91	1			T1	1		T32	1		T176	1
auto[268435456:402653183]	96	1			T13	1		T188	1		T61	1
auto[402653184:536870911]	106	1			T79	1		T115	1		T28	1
auto[536870912:671088639]	82	1			T15	1		T18	1		T115	1
auto[671088640:805306367]	101	1			T13	1		T15	1		T48	1
auto[805306368:939524095]	86	1			T27	1		T120	2		T280	1
auto[939524096:1073741823]	90	1			T3	1		T13	2		T15	1
auto[1073741824:1207959551]	97	1			T36	1		T180	1		T25	1
auto[1207959552:1342177279]	79	1			T4	1		T13	1		T15	3
auto[1342177280:1476395007]	106	1			T4	1		T15	1		T27	1
auto[1476395008:1610612735]	105	1			T13	4		T18	1		T79	1
auto[1610612736:1744830463]	95	1			T100	1		T103	1		T53	1
auto[1744830464:1879048191]	94	1			T3	1		T4	1		T24	1
auto[1879048192:2013265919]	97	1			T3	1		T81	1		T102	1
auto[2013265920:2147483647]	99	1			T48	1		T104	1		T176	1
auto[2147483648:2281701375]	92	1			T15	1		T61	1		T24	1
auto[2281701376:2415919103]	96	1			T15	1		T48	1		T28	1
auto[2415919104:2550136831]	83	1			T13	1		T15	1		T115	2
auto[2550136832:2684354559]	82	1			T13	3		T85	1		T180	1
auto[2684354560:2818572287]	85	1			T15	2		T103	1		T36	1
auto[2818572288:2952790015]	94	1			T13	1		T15	1		T79	1
auto[2952790016:3087007743]	100	1			T13	1		T15	2		T81	1
auto[3087007744:3221225471]	94	1			T15	1		T198	1		T37	1
auto[3221225472:3355443199]	91	1			T79	2		T100	1		T61	1
auto[3355443200:3489660927]	95	1			T115	1		T103	1		T53	1
auto[3489660928:3623878655]	75	1			T81	1		T103	2		T21	1
auto[3623878656:3758096383]	105	1			T13	1		T28	1		T187	1
auto[3758096384:3892314111]	104	1			T13	4		T15	1		T188	1
auto[3892314112:4026531839]	91	1			T81	1		T183	1		T61	1
auto[4026531840:4160749567]	100	1			T15	1		T103	1		T36	1
auto[4160749568:4294967295]	96	1			T3	1		T24	1		T32	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	50	1			T13	1		T61	1		T26	1
auto[0:134217727]	auto[1]	47	1			T13	1		T65	1		T199	1
auto[134217728:268435455]	auto[0]	47	1			T1	1		T32	1		T176	1
auto[134217728:268435455]	auto[1]	44	1			T356	1		T42	1		T383	1
auto[268435456:402653183]	auto[0]	46	1			T13	1		T85	1		T36	1
auto[268435456:402653183]	auto[1]	50	1			T188	1		T61	1		T24	1
auto[402653184:536870911]	auto[0]	52	1			T79	1		T115	1		T103	2
auto[402653184:536870911]	auto[1]	54	1			T28	1		T85	1		T87	1
auto[536870912:671088639]	auto[0]	37	1			T190	1		T49	1		T415	1
auto[536870912:671088639]	auto[1]	45	1			T15	1		T18	1		T115	1
auto[671088640:805306367]	auto[0]	48	1			T48	1		T100	1		T330	1
auto[671088640:805306367]	auto[1]	53	1			T13	1		T15	1		T28	1
auto[805306368:939524095]	auto[0]	43	1			T6	1		T278	1		T229	1
auto[805306368:939524095]	auto[1]	43	1			T27	1		T120	2		T280	1
auto[939524096:1073741823]	auto[0]	52	1			T13	1		T15	1		T115	1
auto[939524096:1073741823]	auto[1]	38	1			T3	1		T13	1		T120	1
auto[1073741824:1207959551]	auto[0]	51	1			T36	1		T180	1		T25	1
auto[1073741824:1207959551]	auto[1]	46	1			T50	1		T6	2		T393	1
auto[1207959552:1342177279]	auto[0]	41	1			T4	1		T15	2		T102	1
auto[1207959552:1342177279]	auto[1]	38	1			T13	1		T15	1		T226	1
auto[1342177280:1476395007]	auto[0]	58	1			T188	1		T48	1		T85	1
auto[1342177280:1476395007]	auto[1]	48	1			T4	1		T15	1		T27	1
auto[1476395008:1610612735]	auto[0]	51	1			T13	2		T18	1		T79	1
auto[1476395008:1610612735]	auto[1]	54	1			T13	2		T103	1		T53	1
auto[1610612736:1744830463]	auto[0]	39	1			T100	1		T103	1		T53	1
auto[1610612736:1744830463]	auto[1]	56	1			T36	1		T180	2		T120	1
auto[1744830464:1879048191]	auto[0]	37	1			T32	1		T86	1		T267	1
auto[1744830464:1879048191]	auto[1]	57	1			T3	1		T4	1		T24	1
auto[1879048192:2013265919]	auto[0]	47	1			T81	1		T102	1		T25	1
auto[1879048192:2013265919]	auto[1]	50	1			T3	1		T177	1		T178	1
auto[2013265920:2147483647]	auto[0]	50	1			T176	1		T6	1		T62	1
auto[2013265920:2147483647]	auto[1]	49	1			T48	1		T104	1		T6	1
auto[2147483648:2281701375]	auto[0]	40	1			T15	1		T24	1		T53	1
auto[2147483648:2281701375]	auto[1]	52	1			T61	1		T103	1		T6	2
auto[2281701376:2415919103]	auto[0]	53	1			T24	2		T103	1		T36	1
auto[2281701376:2415919103]	auto[1]	43	1			T15	1		T48	1		T28	1
auto[2415919104:2550136831]	auto[0]	45	1			T15	1		T115	1		T25	1
auto[2415919104:2550136831]	auto[1]	38	1			T13	1		T115	1		T267	1
auto[2550136832:2684354559]	auto[0]	45	1			T13	1		T85	1		T25	1
auto[2550136832:2684354559]	auto[1]	37	1			T13	2		T180	1		T37	1
auto[2684354560:2818572287]	auto[0]	40	1			T15	1		T25	1		T280	1
auto[2684354560:2818572287]	auto[1]	45	1			T15	1		T103	1		T36	1
auto[2818572288:2952790015]	auto[0]	45	1			T53	2		T416	1		T372	1
auto[2818572288:2952790015]	auto[1]	49	1			T13	1		T15	1		T79	1
auto[2952790016:3087007743]	auto[0]	49	1			T15	2		T188	1		T48	1
auto[2952790016:3087007743]	auto[1]	51	1			T13	1		T81	1		T27	1
auto[3087007744:3221225471]	auto[0]	42	1			T15	1		T198	1		T278	1
auto[3087007744:3221225471]	auto[1]	52	1			T37	1		T393	2		T19	1
auto[3221225472:3355443199]	auto[0]	40	1			T61	1		T32	1		T6	1
auto[3221225472:3355443199]	auto[1]	51	1			T79	2		T100	1		T186	1
auto[3355443200:3489660927]	auto[0]	45	1			T115	1		T53	1		T226	1
auto[3355443200:3489660927]	auto[1]	50	1			T103	1		T31	1		T352	1
auto[3489660928:3623878655]	auto[0]	33	1			T81	1		T103	1		T49	1
auto[3489660928:3623878655]	auto[1]	42	1			T103	1		T21	1		T186	1
auto[3623878656:3758096383]	auto[0]	46	1			T13	1		T28	1		T87	1
auto[3623878656:3758096383]	auto[1]	59	1			T187	1		T50	1		T6	1
auto[3758096384:3892314111]	auto[0]	42	1			T13	2		T15	1		T93	1
auto[3758096384:3892314111]	auto[1]	62	1			T13	2		T188	1		T48	1
auto[3892314112:4026531839]	auto[0]	41	1			T29	1		T41	1		T184	1
auto[3892314112:4026531839]	auto[1]	50	1			T81	1		T183	1		T61	1
auto[4026531840:4160749567]	auto[0]	53	1			T15	1		T36	1		T176	1
auto[4026531840:4160749567]	auto[1]	47	1			T103	1		T187	1		T26	1
auto[4160749568:4294967295]	auto[0]	50	1			T32	1		T50	1		T93	1
auto[4160749568:4294967295]	auto[1]	46	1			T3	1		T24	1		T176	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1454

1

T4

1

T13

8

T15

11

auto[1]

1554

1

T1

1

T3

4

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	86	1			T13	1		T15	2		T79	1
auto[134217728:268435455]	80	1			T13	1		T24	1		T36	1
auto[268435456:402653183]	81	1			T13	1		T81	1		T188	1
auto[402653184:536870911]	93	1			T27	1		T103	1		T180	2
auto[536870912:671088639]	105	1			T15	2		T61	1		T103	1
auto[671088640:805306367]	94	1			T3	1		T21	1		T180	1
auto[805306368:939524095]	102	1			T28	1		T85	1		T36	1
auto[939524096:1073741823]	112	1			T4	1		T13	1		T15	4
auto[1073741824:1207959551]	87	1			T13	1		T115	1		T103	1
auto[1207959552:1342177279]	87	1			T1	1		T3	1		T4	1
auto[1342177280:1476395007]	86	1			T13	1		T15	1		T25	1
auto[1476395008:1610612735]	99	1			T13	1		T15	1		T25	1
auto[1610612736:1744830463]	106	1			T13	2		T48	1		T24	1
auto[1744830464:1879048191]	89	1			T13	2		T103	1		T53	1
auto[1879048192:2013265919]	98	1			T3	1		T13	1		T79	1
auto[2013265920:2147483647]	99	1			T15	2		T115	1		T188	1
auto[2147483648:2281701375]	91	1			T13	1		T183	1		T53	1
auto[2281701376:2415919103]	98	1			T13	2		T15	2		T81	1
auto[2415919104:2550136831]	87	1			T13	2		T188	1		T6	1
auto[2550136832:2684354559]	107	1			T3	1		T15	1		T27	1
auto[2684354560:2818572287]	88	1			T15	1		T115	1		T32	1
auto[2818572288:2952790015]	96	1			T13	1		T24	1		T102	1
auto[2952790016:3087007743]	81	1			T103	1		T6	1		T86	1
auto[3087007744:3221225471]	103	1			T15	1		T100	1		T61	1
auto[3221225472:3355443199]	91	1			T28	1		T110	1		T102	1
auto[3355443200:3489660927]	84	1			T13	2		T18	1		T115	1
auto[3489660928:3623878655]	109	1			T48	1		T53	1		T186	1
auto[3623878656:3758096383]	95	1			T4	1		T81	1		T28	1
auto[3758096384:3892314111]	86	1			T188	1		T103	1		T53	1
auto[3892314112:4026531839]	94	1			T81	1		T48	3		T36	2
auto[4026531840:4160749567]	87	1			T24	1		T187	1		T93	1
auto[4160749568:4294967295]	107	1			T13	1		T79	1		T187	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	36	1			T13	1		T79	1		T280	1
auto[0:134217727]	auto[1]	50	1			T15	2		T27	1		T100	1
auto[134217728:268435455]	auto[0]	45	1			T24	1		T25	1		T199	2
auto[134217728:268435455]	auto[1]	35	1			T13	1		T36	1		T62	1
auto[268435456:402653183]	auto[0]	35	1			T198	1		T6	1		T86	1
auto[268435456:402653183]	auto[1]	46	1			T13	1		T81	1		T188	1
auto[402653184:536870911]	auto[0]	41	1			T103	1		T199	1		T41	1
auto[402653184:536870911]	auto[1]	52	1			T27	1		T180	2		T120	1
auto[536870912:671088639]	auto[0]	50	1			T15	1		T53	1		T87	1
auto[536870912:671088639]	auto[1]	55	1			T15	1		T61	1		T103	1
auto[671088640:805306367]	auto[0]	46	1			T21	1		T50	1		T26	1
auto[671088640:805306367]	auto[1]	48	1			T3	1		T180	1		T177	1
auto[805306368:939524095]	auto[0]	55	1			T85	1		T36	1		T62	1
auto[805306368:939524095]	auto[1]	47	1			T28	1		T199	2		T356	1
auto[939524096:1073741823]	auto[0]	56	1			T15	4		T36	1		T180	1
auto[939524096:1073741823]	auto[1]	56	1			T4	1		T13	1		T18	1
auto[1073741824:1207959551]	auto[0]	46	1			T13	1		T115	1		T103	1
auto[1073741824:1207959551]	auto[1]	41	1			T53	1		T120	1		T6	1
auto[1207959552:1342177279]	auto[0]	40	1			T15	1		T20	1		T95	1
auto[1207959552:1342177279]	auto[1]	47	1			T1	1		T3	1		T4	1
auto[1342177280:1476395007]	auto[0]	45	1			T13	1		T25	1		T32	1
auto[1342177280:1476395007]	auto[1]	41	1			T15	1		T104	1		T186	1
auto[1476395008:1610612735]	auto[0]	43	1			T15	1		T25	1		T32	1
auto[1476395008:1610612735]	auto[1]	56	1			T13	1		T226	1		T190	1
auto[1610612736:1744830463]	auto[0]	53	1			T13	1		T24	1		T102	1
auto[1610612736:1744830463]	auto[1]	53	1			T13	1		T48	1		T103	1
auto[1744830464:1879048191]	auto[0]	50	1			T13	1		T103	1		T53	1
auto[1744830464:1879048191]	auto[1]	39	1			T13	1		T189	2		T89	1
auto[1879048192:2013265919]	auto[0]	54	1			T115	2		T61	1		T198	1
auto[1879048192:2013265919]	auto[1]	44	1			T3	1		T13	1		T79	1
auto[2013265920:2147483647]	auto[0]	44	1			T15	1		T103	1		T26	1
auto[2013265920:2147483647]	auto[1]	55	1			T15	1		T115	1		T188	1
auto[2147483648:2281701375]	auto[0]	36	1			T53	1		T32	2		T199	1
auto[2147483648:2281701375]	auto[1]	55	1			T13	1		T183	1		T187	1
auto[2281701376:2415919103]	auto[0]	54	1			T13	1		T15	1		T100	1
auto[2281701376:2415919103]	auto[1]	44	1			T13	1		T15	1		T81	1
auto[2415919104:2550136831]	auto[0]	41	1			T188	1		T49	1		T253	1
auto[2415919104:2550136831]	auto[1]	46	1			T13	2		T6	1		T278	1
auto[2550136832:2684354559]	auto[0]	53	1			T15	1		T61	1		T25	1
auto[2550136832:2684354559]	auto[1]	54	1			T3	1		T27	1		T48	1
auto[2684354560:2818572287]	auto[0]	39	1			T32	1		T6	1		T62	2
auto[2684354560:2818572287]	auto[1]	49	1			T15	1		T115	1		T198	1
auto[2818572288:2952790015]	auto[0]	42	1			T102	1		T85	1		T103	1
auto[2818572288:2952790015]	auto[1]	54	1			T13	1		T24	1		T50	1
auto[2952790016:3087007743]	auto[0]	42	1			T103	1		T6	1		T86	1
auto[2952790016:3087007743]	auto[1]	39	1			T255	1		T356	1		T95	1
auto[3087007744:3221225471]	auto[0]	54	1			T15	1		T100	1		T85	1
auto[3087007744:3221225471]	auto[1]	49	1			T61	1		T103	1		T36	1
auto[3221225472:3355443199]	auto[0]	41	1			T176	1		T6	1		T189	1
auto[3221225472:3355443199]	auto[1]	50	1			T28	1		T110	1		T102	1
auto[3355443200:3489660927]	auto[0]	37	1			T13	1		T115	1		T24	1
auto[3355443200:3489660927]	auto[1]	47	1			T13	1		T18	1		T28	1
auto[3489660928:3623878655]	auto[0]	48	1			T53	1		T352	1		T263	1
auto[3489660928:3623878655]	auto[1]	61	1			T48	1		T186	1		T178	1
auto[3623878656:3758096383]	auto[0]	45	1			T4	1		T81	1		T103	1
auto[3623878656:3758096383]	auto[1]	50	1			T28	1		T120	1		T6	1
auto[3758096384:3892314111]	auto[0]	44	1			T53	1		T87	1		T6	1
auto[3758096384:3892314111]	auto[1]	42	1			T188	1		T103	1		T186	1
auto[3892314112:4026531839]	auto[0]	46	1			T81	1		T48	2		T36	2
auto[3892314112:4026531839]	auto[1]	48	1			T48	1		T37	1		T86	1
auto[4026531840:4160749567]	auto[0]	39	1			T24	1		T93	1		T179	1
auto[4026531840:4160749567]	auto[1]	48	1			T187	1		T33	1		T65	1
auto[4160749568:4294967295]	auto[0]	54	1			T13	1		T87	1		T226	1
auto[4160749568:4294967295]	auto[1]	53	1			T79	1		T187	1		T6	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1446

1

T4

1

T13

8

T15

10

auto[1]

1560

1

T1

1

T3

4

T4

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	87	1			T13	1		T15	1		T110	1
auto[134217728:268435455]	87	1			T28	1		T24	1		T103	1
auto[268435456:402653183]	86	1			T13	1		T25	1		T176	1
auto[402653184:536870911]	97	1			T79	1		T81	1		T115	1
auto[536870912:671088639]	111	1			T13	2		T15	1		T79	1
auto[671088640:805306367]	92	1			T15	3		T61	1		T32	2
auto[805306368:939524095]	92	1			T3	1		T13	1		T188	1
auto[939524096:1073741823]	102	1			T13	2		T15	2		T18	1
auto[1073741824:1207959551]	97	1			T48	1		T61	1		T85	1
auto[1207959552:1342177279]	107	1			T13	1		T15	2		T85	1
auto[1342177280:1476395007]	102	1			T3	1		T15	1		T79	1
auto[1476395008:1610612735]	81	1			T13	1		T15	1		T53	1
auto[1610612736:1744830463]	86	1			T102	1		T32	1		T176	1
auto[1744830464:1879048191]	89	1			T188	1		T180	1		T25	1
auto[1879048192:2013265919]	92	1			T13	1		T15	1		T48	1
auto[2013265920:2147483647]	100	1			T183	1		T48	1		T24	1
auto[2147483648:2281701375]	97	1			T13	1		T188	1		T103	1
auto[2281701376:2415919103]	102	1			T13	2		T81	1		T115	1
auto[2415919104:2550136831]	83	1			T61	1		T180	1		T6	1
auto[2550136832:2684354559]	84	1			T3	1		T79	1		T115	1
auto[2684354560:2818572287]	89	1			T13	2		T15	1		T27	1
auto[2818572288:2952790015]	96	1			T27	1		T103	1		T53	1
auto[2952790016:3087007743]	92	1			T4	1		T13	1		T177	1
auto[3087007744:3221225471]	104	1			T3	1		T48	1		T24	1
auto[3221225472:3355443199]	95	1			T4	1		T15	1		T81	1
auto[3355443200:3489660927]	98	1			T4	1		T79	1		T48	1
auto[3489660928:3623878655]	101	1			T13	1		T15	1		T31	1
auto[3623878656:3758096383]	97	1			T13	1		T15	2		T36	1
auto[3758096384:3892314111]	80	1			T13	1		T53	1		T37	1
auto[3892314112:4026531839]	89	1			T1	1		T13	1		T15	1
auto[4026531840:4160749567]	93	1			T13	1		T115	2		T28	1
auto[4160749568:4294967295]	98	1			T13	1		T188	1		T100	1