Unified Coverage Report :: Group Instance : attest_sw_binding_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1444

1

T1

1

T4

1

T13

9

auto[1]

1562

1

T3

4

T4

2

T13

13

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T115	1		T28	1		T24	1
auto[134217728:268435455]	97	1			T115	1		T188	1		T61	1
auto[268435456:402653183]	97	1			T15	1		T188	1		T100	1
auto[402653184:536870911]	103	1			T79	1		T27	1		T53	1
auto[536870912:671088639]	103	1			T13	3		T36	1		T178	1
auto[671088640:805306367]	89	1			T25	1		T87	1		T19	1
auto[805306368:939524095]	102	1			T15	2		T85	1		T53	1
auto[939524096:1073741823]	102	1			T81	1		T48	1		T103	1
auto[1073741824:1207959551]	82	1			T13	1		T48	2		T53	1
auto[1207959552:1342177279]	92	1			T13	1		T15	1		T115	1
auto[1342177280:1476395007]	95	1			T6	1		T190	1		T62	2
auto[1476395008:1610612735]	105	1			T3	1		T4	1		T15	3
auto[1610612736:1744830463]	83	1			T13	1		T15	1		T18	1
auto[1744830464:1879048191]	85	1			T13	2		T28	1		T85	1
auto[1879048192:2013265919]	91	1			T13	2		T27	1		T48	1
auto[2013265920:2147483647]	87	1			T15	1		T61	1		T103	1
auto[2147483648:2281701375]	107	1			T3	1		T13	1		T15	1
auto[2281701376:2415919103]	77	1			T13	1		T188	1		T36	1
auto[2415919104:2550136831]	106	1			T4	1		T100	2		T180	1
auto[2550136832:2684354559]	101	1			T115	1		T103	1		T31	1
auto[2684354560:2818572287]	103	1			T1	1		T13	1		T115	1
auto[2818572288:2952790015]	98	1			T4	1		T13	2		T15	1
auto[2952790016:3087007743]	84	1			T102	1		T103	1		T180	2
auto[3087007744:3221225471]	91	1			T3	1		T13	1		T15	1
auto[3221225472:3355443199]	96	1			T15	3		T81	1		T25	1
auto[3355443200:3489660927]	98	1			T13	1		T15	1		T115	1
auto[3489660928:3623878655]	83	1			T13	1		T61	1		T53	1
auto[3623878656:3758096383]	92	1			T13	1		T15	1		T79	1
auto[3758096384:3892314111]	90	1			T18	1		T79	1		T27	1
auto[3892314112:4026531839]	98	1			T13	2		T15	1		T24	1
auto[4026531840:4160749567]	93	1			T3	1		T79	1		T103	2
auto[4160749568:4294967295]	82	1			T13	1		T79	1		T21	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T115	1		T28	1		T50	1
auto[0:134217727]	auto[1]	46	1			T24	1		T103	1		T393	1
auto[134217728:268435455]	auto[0]	44	1			T188	1		T103	1		T26	1
auto[134217728:268435455]	auto[1]	53	1			T115	1		T61	1		T180	2
auto[268435456:402653183]	auto[0]	50	1			T188	1		T85	1		T32	1
auto[268435456:402653183]	auto[1]	47	1			T15	1		T100	1		T103	1
auto[402653184:536870911]	auto[0]	50	1			T79	1		T53	1		T32	1
auto[402653184:536870911]	auto[1]	53	1			T27	1		T186	1		T278	1
auto[536870912:671088639]	auto[0]	47	1			T13	2		T417	1		T197	1
auto[536870912:671088639]	auto[1]	56	1			T13	1		T36	1		T178	1
auto[671088640:805306367]	auto[0]	44	1			T25	1		T87	1		T19	1
auto[671088640:805306367]	auto[1]	45	1			T201	1		T415	1		T95	1
auto[805306368:939524095]	auto[0]	47	1			T15	1		T85	1		T53	1
auto[805306368:939524095]	auto[1]	55	1			T15	1		T176	1		T189	1
auto[939524096:1073741823]	auto[0]	48	1			T48	1		T32	1		T26	1
auto[939524096:1073741823]	auto[1]	54	1			T81	1		T103	1		T50	1
auto[1073741824:1207959551]	auto[0]	38	1			T48	1		T53	1		T36	1
auto[1073741824:1207959551]	auto[1]	44	1			T13	1		T48	1		T135	1
auto[1207959552:1342177279]	auto[0]	42	1			T15	1		T102	1		T86	1
auto[1207959552:1342177279]	auto[1]	50	1			T13	1		T115	1		T37	1
auto[1342177280:1476395007]	auto[0]	52	1			T62	2		T20	1		T199	1
auto[1342177280:1476395007]	auto[1]	43	1			T6	1		T190	1		T352	1
auto[1476395008:1610612735]	auto[0]	46	1			T4	1		T15	2		T85	1
auto[1476395008:1610612735]	auto[1]	59	1			T3	1		T15	1		T120	1
auto[1610612736:1744830463]	auto[0]	42	1			T13	1		T81	1		T6	1
auto[1610612736:1744830463]	auto[1]	41	1			T15	1		T18	1		T24	1
auto[1744830464:1879048191]	auto[0]	39	1			T85	1		T25	1		T197	1
auto[1744830464:1879048191]	auto[1]	46	1			T13	2		T28	1		T135	1
auto[1879048192:2013265919]	auto[0]	35	1			T13	1		T48	1		T24	1
auto[1879048192:2013265919]	auto[1]	56	1			T13	1		T27	1		T61	1
auto[2013265920:2147483647]	auto[0]	49	1			T15	1		T103	1		T53	1
auto[2013265920:2147483647]	auto[1]	38	1			T61	1		T352	1		T199	2
auto[2147483648:2281701375]	auto[0]	51	1			T15	1		T198	1		T280	1
auto[2147483648:2281701375]	auto[1]	56	1			T3	1		T13	1		T48	1
auto[2281701376:2415919103]	auto[0]	35	1			T36	1		T415	1		T73	1
auto[2281701376:2415919103]	auto[1]	42	1			T13	1		T188	1		T50	1
auto[2415919104:2550136831]	auto[0]	60	1			T100	2		T25	1		T6	1
auto[2415919104:2550136831]	auto[1]	46	1			T4	1		T180	1		T178	1
auto[2550136832:2684354559]	auto[0]	48	1			T115	1		T103	1		T87	2
auto[2550136832:2684354559]	auto[1]	53	1			T31	1		T187	1		T226	1
auto[2684354560:2818572287]	auto[0]	46	1			T1	1		T13	1		T115	1
auto[2684354560:2818572287]	auto[1]	57	1			T28	2		T103	1		T53	1
auto[2818572288:2952790015]	auto[0]	43	1			T15	1		T61	1		T103	1
auto[2818572288:2952790015]	auto[1]	55	1			T4	1		T13	2		T81	1
auto[2952790016:3087007743]	auto[0]	40	1			T102	1		T180	1		T93	1
auto[2952790016:3087007743]	auto[1]	44	1			T103	1		T180	1		T178	1
auto[3087007744:3221225471]	auto[0]	46	1			T13	1		T24	1		T176	1
auto[3087007744:3221225471]	auto[1]	45	1			T3	1		T15	1		T36	1
auto[3221225472:3355443199]	auto[0]	49	1			T15	2		T81	1		T25	1
auto[3221225472:3355443199]	auto[1]	47	1			T15	1		T6	1		T267	1
auto[3355443200:3489660927]	auto[0]	47	1			T13	1		T15	1		T6	1
auto[3355443200:3489660927]	auto[1]	51	1			T115	1		T87	1		T6	1
auto[3489660928:3623878655]	auto[0]	38	1			T393	1		T95	1		T41	1
auto[3489660928:3623878655]	auto[1]	45	1			T13	1		T61	1		T53	1
auto[3623878656:3758096383]	auto[0]	37	1			T62	1		T199	2		T184	1
auto[3623878656:3758096383]	auto[1]	55	1			T13	1		T15	1		T79	1
auto[3758096384:3892314111]	auto[0]	41	1			T18	1		T79	1		T103	1
auto[3758096384:3892314111]	auto[1]	49	1			T27	1		T176	1		T187	1
auto[3892314112:4026531839]	auto[0]	53	1			T13	1		T15	1		T24	1
auto[3892314112:4026531839]	auto[1]	45	1			T13	1		T36	1		T180	1
auto[4026531840:4160749567]	auto[0]	47	1			T103	1		T36	1		T120	1
auto[4026531840:4160749567]	auto[1]	46	1			T3	1		T79	1		T103	1
auto[4160749568:4294967295]	auto[0]	42	1			T13	1		T21	1		T176	1
auto[4160749568:4294967295]	auto[1]	40	1			T79	1		T36	1		T177	1