Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4014

1

T3

8

T4

4

T13

30

auto[1]

2004

1

T1

2

T4

2

T13

14

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	200	1			T79	2		T115	2		T180	2
auto[134217728:268435455]	170	1			T100	2		T24	2		T25	2
auto[268435456:402653183]	186	1			T79	2		T48	2		T180	2
auto[402653184:536870911]	192	1			T27	2		T100	2		T61	4
auto[536870912:671088639]	222	1			T13	2		T15	4		T18	2
auto[671088640:805306367]	182	1			T100	2		T393	2		T201	2
auto[805306368:939524095]	184	1			T15	4		T50	2		T26	2
auto[939524096:1073741823]	184	1			T4	2		T13	2		T28	2
auto[1073741824:1207959551]	190	1			T13	4		T15	2		T85	2
auto[1207959552:1342177279]	178	1			T3	2		T13	2		T85	2
auto[1342177280:1476395007]	194	1			T15	4		T79	2		T53	2
auto[1476395008:1610612735]	180	1			T13	2		T81	2		T110	2
auto[1610612736:1744830463]	164	1			T13	2		T24	2		T36	2
auto[1744830464:1879048191]	182	1			T81	2		T27	2		T115	2
auto[1879048192:2013265919]	214	1			T3	2		T4	2		T15	6
auto[2013265920:2147483647]	178	1			T13	2		T27	2		T188	4
auto[2147483648:2281701375]	198	1			T13	4		T115	2		T87	2
auto[2281701376:2415919103]	168	1			T13	4		T85	2		T103	2
auto[2415919104:2550136831]	170	1			T48	2		T28	2		T102	2
auto[2550136832:2684354559]	204	1			T13	4		T61	2		T103	2
auto[2684354560:2818572287]	198	1			T13	2		T15	2		T180	2
auto[2818572288:2952790015]	202	1			T3	2		T15	2		T18	2
auto[2952790016:3087007743]	190	1			T15	2		T81	2		T53	2
auto[3087007744:3221225471]	180	1			T13	2		T79	2		T24	2
auto[3221225472:3355443199]	202	1			T13	2		T15	4		T53	2
auto[3355443200:3489660927]	202	1			T1	2		T13	4		T48	2
auto[3489660928:3623878655]	170	1			T13	2		T28	2		T36	2
auto[3623878656:3758096383]	184	1			T3	2		T15	4		T115	2
auto[3758096384:3892314111]	180	1			T13	2		T24	2		T36	2
auto[3892314112:4026531839]	214	1			T4	2		T79	2		T115	2
auto[4026531840:4160749567]	172	1			T15	2		T48	2		T103	2
auto[4160749568:4294967295]	184	1			T13	2		T36	2		T176	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	120	1			T79	2		T180	2		T176	2
auto[0:134217727]	auto[1]	80	1			T115	2		T62	2		T229	2
auto[134217728:268435455]	auto[0]	106	1			T24	2		T120	2		T186	2
auto[134217728:268435455]	auto[1]	64	1			T100	2		T25	2		T32	2
auto[268435456:402653183]	auto[0]	130	1			T79	2		T48	2		T180	2
auto[268435456:402653183]	auto[1]	56	1			T177	2		T288	2		T267	2
auto[402653184:536870911]	auto[0]	124	1			T100	2		T61	2		T87	2
auto[402653184:536870911]	auto[1]	68	1			T27	2		T61	2		T102	2
auto[536870912:671088639]	auto[0]	144	1			T13	2		T15	4		T18	2
auto[536870912:671088639]	auto[1]	78	1			T81	2		T188	2		T28	2
auto[671088640:805306367]	auto[0]	120	1			T201	2		T199	2		T41	6
auto[671088640:805306367]	auto[1]	62	1			T100	2		T393	2		T267	2
auto[805306368:939524095]	auto[0]	136	1			T15	2		T50	2		T26	2
auto[805306368:939524095]	auto[1]	48	1			T15	2		T6	4		T201	2
auto[939524096:1073741823]	auto[0]	146	1			T4	2		T13	2		T28	2
auto[939524096:1073741823]	auto[1]	38	1			T24	2		T228	2		T417	2
auto[1073741824:1207959551]	auto[0]	132	1			T85	2		T37	2		T6	4
auto[1073741824:1207959551]	auto[1]	58	1			T13	4		T15	2		T20	2
auto[1207959552:1342177279]	auto[0]	122	1			T3	2		T85	2		T103	2
auto[1207959552:1342177279]	auto[1]	56	1			T13	2		T103	2		T352	2
auto[1342177280:1476395007]	auto[0]	106	1			T15	4		T79	2		T178	2
auto[1342177280:1476395007]	auto[1]	88	1			T53	2		T21	2		T25	2
auto[1476395008:1610612735]	auto[0]	130	1			T13	2		T110	2		T53	2
auto[1476395008:1610612735]	auto[1]	50	1			T81	2		T187	2		T264	2
auto[1610612736:1744830463]	auto[0]	112	1			T13	2		T24	2		T36	2
auto[1610612736:1744830463]	auto[1]	52	1			T104	4		T199	2		T41	2
auto[1744830464:1879048191]	auto[0]	106	1			T81	2		T27	2		T32	2
auto[1744830464:1879048191]	auto[1]	76	1			T115	2		T24	2		T103	2
auto[1879048192:2013265919]	auto[0]	136	1			T3	2		T15	2		T48	2
auto[1879048192:2013265919]	auto[1]	78	1			T4	2		T15	4		T48	2
auto[2013265920:2147483647]	auto[0]	102	1			T13	2		T188	2		T6	2
auto[2013265920:2147483647]	auto[1]	76	1			T27	2		T188	2		T178	2
auto[2147483648:2281701375]	auto[0]	138	1			T115	2		T87	2		T62	2
auto[2147483648:2281701375]	auto[1]	60	1			T13	4		T63	2		T75	2
auto[2281701376:2415919103]	auto[0]	118	1			T13	4		T85	2		T6	2
auto[2281701376:2415919103]	auto[1]	50	1			T103	2		T6	2		T29	2
auto[2415919104:2550136831]	auto[0]	108	1			T48	2		T28	2		T6	2
auto[2415919104:2550136831]	auto[1]	62	1			T102	2		T31	2		T26	2
auto[2550136832:2684354559]	auto[0]	150	1			T13	4		T103	2		T36	4
auto[2550136832:2684354559]	auto[1]	54	1			T61	2		T393	2		T255	2
auto[2684354560:2818572287]	auto[0]	138	1			T15	2		T180	2		T187	4
auto[2684354560:2818572287]	auto[1]	60	1			T13	2		T122	2		T401	2
auto[2818572288:2952790015]	auto[0]	150	1			T3	2		T15	2		T18	2
auto[2818572288:2952790015]	auto[1]	52	1			T183	2		T190	2		T62	2
auto[2952790016:3087007743]	auto[0]	110	1			T32	2		T6	2		T93	2
auto[2952790016:3087007743]	auto[1]	80	1			T15	2		T81	2		T53	2
auto[3087007744:3221225471]	auto[0]	118	1			T13	2		T79	2		T24	2
auto[3087007744:3221225471]	auto[1]	62	1			T120	2		T122	2		T189	2
auto[3221225472:3355443199]	auto[0]	116	1			T13	2		T53	2		T32	2
auto[3221225472:3355443199]	auto[1]	86	1			T15	4		T6	4		T93	2
auto[3355443200:3489660927]	auto[0]	130	1			T13	4		T48	2		T198	2
auto[3355443200:3489660927]	auto[1]	72	1			T1	2		T103	4		T53	2
auto[3489660928:3623878655]	auto[0]	122	1			T13	2		T36	2		T87	2
auto[3489660928:3623878655]	auto[1]	48	1			T28	2		T41	2		T42	2
auto[3623878656:3758096383]	auto[0]	126	1			T3	2		T15	4		T115	2
auto[3623878656:3758096383]	auto[1]	58	1			T103	2		T87	2		T228	2
auto[3758096384:3892314111]	auto[0]	130	1			T13	2		T24	2		T36	2
auto[3758096384:3892314111]	auto[1]	50	1			T356	2		T82	2		T383	2
auto[3892314112:4026531839]	auto[0]	140	1			T4	2		T115	2		T180	4
auto[3892314112:4026531839]	auto[1]	74	1			T79	2		T53	2		T87	2
auto[4026531840:4160749567]	auto[0]	120	1			T15	2		T48	2		T50	2
auto[4026531840:4160749567]	auto[1]	52	1			T103	2		T190	2		T330	2
auto[4160749568:4294967295]	auto[0]	128	1			T36	2		T176	2		T50	2
auto[4160749568:4294967295]	auto[1]	56	1			T13	2		T93	2		T384	2