Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.84 99.10 98.03 98.70 100.00 99.11 98.41 91.56


Total test records in report: 1078
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1014 /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1397913138 Mar 16 12:25:18 PM PDT 24 Mar 16 12:25:22 PM PDT 24 139825476 ps
T1015 /workspace/coverage/default/2.keymgr_custom_cm.1697604138 Mar 16 12:23:37 PM PDT 24 Mar 16 12:23:43 PM PDT 24 407854526 ps
T1016 /workspace/coverage/default/39.keymgr_kmac_rsp_err.3307801134 Mar 16 12:25:18 PM PDT 24 Mar 16 12:25:45 PM PDT 24 2364923688 ps
T317 /workspace/coverage/default/25.keymgr_kmac_rsp_err.3285427866 Mar 16 12:24:40 PM PDT 24 Mar 16 12:25:38 PM PDT 24 20998903910 ps
T1017 /workspace/coverage/default/46.keymgr_sideload_aes.3758012939 Mar 16 12:25:33 PM PDT 24 Mar 16 12:25:37 PM PDT 24 37512628 ps
T1018 /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1319439034 Mar 16 12:23:21 PM PDT 24 Mar 16 12:23:30 PM PDT 24 5264298436 ps
T1019 /workspace/coverage/default/21.keymgr_stress_all.3999369939 Mar 16 12:24:37 PM PDT 24 Mar 16 12:24:40 PM PDT 24 336909658 ps
T1020 /workspace/coverage/default/45.keymgr_hwsw_invalid_input.199525571 Mar 16 12:25:44 PM PDT 24 Mar 16 12:25:49 PM PDT 24 235421388 ps
T1021 /workspace/coverage/default/24.keymgr_cfg_regwen.1373687482 Mar 16 12:24:40 PM PDT 24 Mar 16 12:24:51 PM PDT 24 2241556835 ps
T1022 /workspace/coverage/default/12.keymgr_lc_disable.4237838310 Mar 16 12:23:58 PM PDT 24 Mar 16 12:24:01 PM PDT 24 143037269 ps
T1023 /workspace/coverage/default/30.keymgr_lc_disable.1620549024 Mar 16 12:24:53 PM PDT 24 Mar 16 12:24:56 PM PDT 24 222047806 ps
T350 /workspace/coverage/default/49.keymgr_stress_all.1593854510 Mar 16 12:25:44 PM PDT 24 Mar 16 12:31:48 PM PDT 24 12213020649 ps
T1024 /workspace/coverage/default/37.keymgr_sideload_aes.3054804983 Mar 16 12:25:14 PM PDT 24 Mar 16 12:25:32 PM PDT 24 2498702624 ps
T1025 /workspace/coverage/default/21.keymgr_direct_to_disabled.1435583653 Mar 16 12:24:27 PM PDT 24 Mar 16 12:24:32 PM PDT 24 110680076 ps
T1026 /workspace/coverage/default/29.keymgr_custom_cm.230398729 Mar 16 12:24:47 PM PDT 24 Mar 16 12:24:51 PM PDT 24 75201454 ps
T306 /workspace/coverage/default/41.keymgr_sw_invalid_input.2173640148 Mar 16 12:25:27 PM PDT 24 Mar 16 12:25:37 PM PDT 24 261310507 ps
T1027 /workspace/coverage/default/21.keymgr_sideload.3637825937 Mar 16 12:24:22 PM PDT 24 Mar 16 12:24:26 PM PDT 24 59350652 ps
T1028 /workspace/coverage/default/34.keymgr_cfg_regwen.1544582348 Mar 16 12:24:52 PM PDT 24 Mar 16 12:26:08 PM PDT 24 5745759251 ps
T1029 /workspace/coverage/default/5.keymgr_sideload_aes.2026999249 Mar 16 12:23:45 PM PDT 24 Mar 16 12:23:53 PM PDT 24 391661199 ps
T1030 /workspace/coverage/default/15.keymgr_alert_test.4226743269 Mar 16 12:24:10 PM PDT 24 Mar 16 12:24:11 PM PDT 24 15755290 ps
T1031 /workspace/coverage/default/37.keymgr_sync_async_fault_cross.360433721 Mar 16 12:25:18 PM PDT 24 Mar 16 12:25:20 PM PDT 24 36229096 ps
T23 /workspace/coverage/default/23.keymgr_custom_cm.1400137932 Mar 16 12:24:48 PM PDT 24 Mar 16 12:24:51 PM PDT 24 73460275 ps
T1032 /workspace/coverage/default/10.keymgr_lc_disable.2972476668 Mar 16 12:26:20 PM PDT 24 Mar 16 12:26:24 PM PDT 24 213696703 ps
T1033 /workspace/coverage/default/25.keymgr_sideload.3375984771 Mar 16 12:24:41 PM PDT 24 Mar 16 12:24:45 PM PDT 24 194560317 ps
T1034 /workspace/coverage/default/28.keymgr_direct_to_disabled.97113679 Mar 16 12:24:46 PM PDT 24 Mar 16 12:25:01 PM PDT 24 1467232246 ps
T1035 /workspace/coverage/default/11.keymgr_random.2177857608 Mar 16 12:23:56 PM PDT 24 Mar 16 12:24:01 PM PDT 24 116456326 ps
T1036 /workspace/coverage/default/34.keymgr_smoke.1651994479 Mar 16 12:24:55 PM PDT 24 Mar 16 12:25:03 PM PDT 24 683958289 ps
T1037 /workspace/coverage/default/7.keymgr_sideload.4199232942 Mar 16 12:23:46 PM PDT 24 Mar 16 12:23:50 PM PDT 24 221503112 ps
T1038 /workspace/coverage/default/16.keymgr_alert_test.1955002457 Mar 16 12:24:06 PM PDT 24 Mar 16 12:24:07 PM PDT 24 32231220 ps
T430 /workspace/coverage/default/2.keymgr_cfg_regwen.3193324902 Mar 16 12:23:35 PM PDT 24 Mar 16 12:23:39 PM PDT 24 58076440 ps
T1039 /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1416023352 Mar 16 12:25:40 PM PDT 24 Mar 16 12:25:43 PM PDT 24 316255487 ps
T1040 /workspace/coverage/default/23.keymgr_alert_test.4007428081 Mar 16 12:24:35 PM PDT 24 Mar 16 12:24:36 PM PDT 24 11717824 ps
T1041 /workspace/coverage/default/15.keymgr_stress_all.2554134476 Mar 16 12:24:19 PM PDT 24 Mar 16 12:24:49 PM PDT 24 5887519989 ps
T105 /workspace/coverage/default/3.keymgr_sec_cm.3292619849 Mar 16 12:23:39 PM PDT 24 Mar 16 12:24:00 PM PDT 24 926673820 ps
T1042 /workspace/coverage/default/27.keymgr_sideload_otbn.1989740635 Mar 16 12:24:40 PM PDT 24 Mar 16 12:24:41 PM PDT 24 24025417 ps
T1043 /workspace/coverage/default/7.keymgr_sideload_kmac.3925339819 Mar 16 12:23:52 PM PDT 24 Mar 16 12:23:58 PM PDT 24 220960468 ps
T315 /workspace/coverage/default/43.keymgr_kmac_rsp_err.1274319617 Mar 16 12:25:41 PM PDT 24 Mar 16 12:26:00 PM PDT 24 337247636 ps
T1044 /workspace/coverage/default/19.keymgr_sideload_otbn.3556212018 Mar 16 12:24:25 PM PDT 24 Mar 16 12:24:29 PM PDT 24 112567866 ps
T1045 /workspace/coverage/default/7.keymgr_sideload_aes.572230308 Mar 16 12:23:45 PM PDT 24 Mar 16 12:23:55 PM PDT 24 982561304 ps
T1046 /workspace/coverage/default/31.keymgr_random.1134450828 Mar 16 12:24:43 PM PDT 24 Mar 16 12:24:48 PM PDT 24 75418528 ps
T1047 /workspace/coverage/default/38.keymgr_sideload.2882012928 Mar 16 12:25:16 PM PDT 24 Mar 16 12:25:58 PM PDT 24 1777513855 ps
T1048 /workspace/coverage/default/40.keymgr_sw_invalid_input.3824832669 Mar 16 12:25:22 PM PDT 24 Mar 16 12:25:28 PM PDT 24 142273067 ps
T1049 /workspace/coverage/default/26.keymgr_cfg_regwen.71528324 Mar 16 12:24:40 PM PDT 24 Mar 16 12:24:44 PM PDT 24 108166990 ps
T1050 /workspace/coverage/default/14.keymgr_smoke.2014427514 Mar 16 12:23:59 PM PDT 24 Mar 16 12:24:03 PM PDT 24 222357932 ps
T1051 /workspace/coverage/default/21.keymgr_random.3504741844 Mar 16 12:24:24 PM PDT 24 Mar 16 12:24:30 PM PDT 24 282646864 ps
T1052 /workspace/coverage/default/4.keymgr_random.2823888623 Mar 16 12:23:42 PM PDT 24 Mar 16 12:23:47 PM PDT 24 339986108 ps
T1053 /workspace/coverage/default/31.keymgr_sideload_otbn.1617582871 Mar 16 12:26:09 PM PDT 24 Mar 16 12:26:15 PM PDT 24 299322267 ps
T1054 /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2937861243 Mar 16 12:24:01 PM PDT 24 Mar 16 12:24:03 PM PDT 24 86140788 ps
T1055 /workspace/coverage/default/16.keymgr_sideload_kmac.1751940930 Mar 16 12:24:03 PM PDT 24 Mar 16 12:24:06 PM PDT 24 51449715 ps
T1056 /workspace/coverage/default/6.keymgr_lc_disable.4261940151 Mar 16 12:23:51 PM PDT 24 Mar 16 12:23:57 PM PDT 24 131162949 ps
T1057 /workspace/coverage/default/25.keymgr_smoke.1378571418 Mar 16 12:24:31 PM PDT 24 Mar 16 12:24:35 PM PDT 24 173169512 ps
T1058 /workspace/coverage/default/33.keymgr_cfg_regwen.455907778 Mar 16 12:24:51 PM PDT 24 Mar 16 12:25:03 PM PDT 24 1914685909 ps
T1059 /workspace/coverage/default/45.keymgr_lc_disable.1844753006 Mar 16 12:25:35 PM PDT 24 Mar 16 12:25:40 PM PDT 24 238204060 ps
T161 /workspace/coverage/default/8.keymgr_sync_async_fault_cross.4289093805 Mar 16 12:23:50 PM PDT 24 Mar 16 12:23:55 PM PDT 24 78719693 ps
T1060 /workspace/coverage/default/22.keymgr_stress_all.1979272263 Mar 16 12:24:32 PM PDT 24 Mar 16 12:26:07 PM PDT 24 8811201500 ps
T1061 /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3483569942 Mar 16 12:24:03 PM PDT 24 Mar 16 12:24:05 PM PDT 24 57608916 ps
T1062 /workspace/coverage/default/41.keymgr_smoke.3057294567 Mar 16 12:25:25 PM PDT 24 Mar 16 12:25:31 PM PDT 24 457365110 ps
T1063 /workspace/coverage/default/33.keymgr_sideload_kmac.546954606 Mar 16 12:24:50 PM PDT 24 Mar 16 12:24:53 PM PDT 24 199719513 ps
T327 /workspace/coverage/default/5.keymgr_stress_all.4269676220 Mar 16 12:23:39 PM PDT 24 Mar 16 12:24:18 PM PDT 24 5038604669 ps
T1064 /workspace/coverage/default/45.keymgr_sw_invalid_input.3412334723 Mar 16 12:25:40 PM PDT 24 Mar 16 12:25:44 PM PDT 24 105073995 ps
T1065 /workspace/coverage/default/10.keymgr_sideload_protect.1275071728 Mar 16 12:23:49 PM PDT 24 Mar 16 12:23:53 PM PDT 24 72639139 ps
T1066 /workspace/coverage/default/30.keymgr_direct_to_disabled.3243574894 Mar 16 12:24:46 PM PDT 24 Mar 16 12:24:50 PM PDT 24 571995347 ps
T1067 /workspace/coverage/default/26.keymgr_sw_invalid_input.2283019651 Mar 16 12:24:47 PM PDT 24 Mar 16 12:24:53 PM PDT 24 918738703 ps
T1068 /workspace/coverage/default/1.keymgr_kmac_rsp_err.3276508986 Mar 16 12:23:38 PM PDT 24 Mar 16 12:23:46 PM PDT 24 655522074 ps
T142 /workspace/coverage/default/49.keymgr_custom_cm.3464765881 Mar 16 12:25:42 PM PDT 24 Mar 16 12:25:44 PM PDT 24 172339492 ps
T307 /workspace/coverage/default/18.keymgr_stress_all.3665070449 Mar 16 12:24:29 PM PDT 24 Mar 16 12:25:12 PM PDT 24 5636050096 ps
T1069 /workspace/coverage/default/9.keymgr_lc_disable.1108109747 Mar 16 12:26:20 PM PDT 24 Mar 16 12:26:22 PM PDT 24 29878947 ps
T1070 /workspace/coverage/default/44.keymgr_custom_cm.1149002846 Mar 16 12:25:41 PM PDT 24 Mar 16 12:25:46 PM PDT 24 525283785 ps
T1071 /workspace/coverage/default/14.keymgr_random.4237114257 Mar 16 12:24:03 PM PDT 24 Mar 16 12:25:39 PM PDT 24 10036249588 ps
T1072 /workspace/coverage/default/40.keymgr_smoke.3783042700 Mar 16 12:25:15 PM PDT 24 Mar 16 12:25:20 PM PDT 24 110558048 ps
T141 /workspace/coverage/default/6.keymgr_custom_cm.163131425 Mar 16 12:24:04 PM PDT 24 Mar 16 12:24:09 PM PDT 24 713562376 ps
T1073 /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1413675641 Mar 16 12:23:34 PM PDT 24 Mar 16 12:23:36 PM PDT 24 55825035 ps
T1074 /workspace/coverage/default/24.keymgr_sideload_otbn.366416147 Mar 16 12:24:36 PM PDT 24 Mar 16 12:24:39 PM PDT 24 261409101 ps
T1075 /workspace/coverage/default/44.keymgr_alert_test.2795053477 Mar 16 12:25:35 PM PDT 24 Mar 16 12:25:37 PM PDT 24 19582460 ps
T1076 /workspace/coverage/default/32.keymgr_sideload_protect.2423628155 Mar 16 12:24:55 PM PDT 24 Mar 16 12:24:58 PM PDT 24 225952108 ps
T1077 /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2142682072 Mar 16 12:25:19 PM PDT 24 Mar 16 12:25:22 PM PDT 24 118758154 ps
T351 /workspace/coverage/default/41.keymgr_sideload.460542253 Mar 16 12:25:27 PM PDT 24 Mar 16 12:26:31 PM PDT 24 34499894868 ps
T1078 /workspace/coverage/default/14.keymgr_custom_cm.1317424424 Mar 16 12:23:58 PM PDT 24 Mar 16 12:24:04 PM PDT 24 101831385 ps

Test location /workspace/coverage/default/33.keymgr_stress_all.2570459949
Short name T15
Test name
Test status
Simulation time 1869430430 ps
CPU time 18.55 seconds
Started Mar 16 12:24:55 PM PDT 24
Finished Mar 16 12:25:14 PM PDT 24
Peak memory 215956 kb
Host smart-0eeb0e9a-2b6c-4a3c-bb48-0785f579951e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570459949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2570459949
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2613851606
Short name T6
Test name
Test status
Simulation time 7540791346 ps
CPU time 98.59 seconds
Started Mar 16 12:25:26 PM PDT 24
Finished Mar 16 12:27:05 PM PDT 24
Peak memory 222360 kb
Host smart-579d5b81-97e9-4a82-b5e9-3680227c4647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613851606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2613851606
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1390607286
Short name T13
Test name
Test status
Simulation time 2358101716 ps
CPU time 19.3 seconds
Started Mar 16 12:25:35 PM PDT 24
Finished Mar 16 12:25:55 PM PDT 24
Peak memory 221612 kb
Host smart-0571ca16-25f0-4002-855a-bb12654869d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390607286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1390607286
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2501742312
Short name T5
Test name
Test status
Simulation time 2908034317 ps
CPU time 26.37 seconds
Started Mar 16 12:23:26 PM PDT 24
Finished Mar 16 12:23:53 PM PDT 24
Peak memory 242676 kb
Host smart-813bcd34-0c1b-40b3-9d3b-8112235fb6b2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501742312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2501742312
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2482633482
Short name T101
Test name
Test status
Simulation time 316336725 ps
CPU time 3.03 seconds
Started Mar 16 12:24:29 PM PDT 24
Finished Mar 16 12:24:33 PM PDT 24
Peak memory 222536 kb
Host smart-82ce4486-2730-4ed3-80e0-f2cc01fe1d80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482633482 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2482633482
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1238319463
Short name T45
Test name
Test status
Simulation time 6852517471 ps
CPU time 148.11 seconds
Started Mar 16 12:23:36 PM PDT 24
Finished Mar 16 12:26:04 PM PDT 24
Peak memory 214840 kb
Host smart-c2ae2a5d-ac65-424a-9bc2-a343a15ea5d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238319463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1238319463
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.978051568
Short name T103
Test name
Test status
Simulation time 496445699 ps
CPU time 10.44 seconds
Started Mar 16 12:23:59 PM PDT 24
Finished Mar 16 12:24:10 PM PDT 24
Peak memory 220880 kb
Host smart-432690ac-bb88-4968-8203-2c64653d2583
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978051568 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.978051568
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3467373341
Short name T41
Test name
Test status
Simulation time 683196668 ps
CPU time 19.11 seconds
Started Mar 16 12:24:04 PM PDT 24
Finished Mar 16 12:24:23 PM PDT 24
Peak memory 222460 kb
Host smart-8aab79ed-b6a6-46ca-bd6c-46ff6db5052a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467373341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3467373341
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2694291096
Short name T29
Test name
Test status
Simulation time 175433888 ps
CPU time 3.18 seconds
Started Mar 16 12:25:09 PM PDT 24
Finished Mar 16 12:25:12 PM PDT 24
Peak memory 214536 kb
Host smart-bf58f5ad-1527-4139-b07d-c6658433a8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694291096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2694291096
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.351377183
Short name T111
Test name
Test status
Simulation time 337742648 ps
CPU time 7.78 seconds
Started Mar 16 12:21:53 PM PDT 24
Finished Mar 16 12:22:01 PM PDT 24
Peak memory 213608 kb
Host smart-bedfde30-fa5e-48ea-babc-f8186e7d4ed7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351377183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.351377183
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.108797396
Short name T115
Test name
Test status
Simulation time 691031106 ps
CPU time 9.1 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:23:48 PM PDT 24
Peak memory 214980 kb
Host smart-027840d5-27e6-4b8c-a08a-f448f1ab7165
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=108797396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.108797396
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1762433357
Short name T411
Test name
Test status
Simulation time 21018265154 ps
CPU time 162.65 seconds
Started Mar 16 12:24:29 PM PDT 24
Finished Mar 16 12:27:13 PM PDT 24
Peak memory 222480 kb
Host smart-ab6576d7-1dc5-4f18-81c6-85cae8d74ab8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1762433357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1762433357
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1051268787
Short name T8
Test name
Test status
Simulation time 37753096 ps
CPU time 1.84 seconds
Started Mar 16 12:25:35 PM PDT 24
Finished Mar 16 12:25:38 PM PDT 24
Peak memory 219748 kb
Host smart-3dd14ba0-3cb3-4083-969f-245cb33c647b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051268787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1051268787
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3559858530
Short name T24
Test name
Test status
Simulation time 185537170 ps
CPU time 7.97 seconds
Started Mar 16 12:25:40 PM PDT 24
Finished Mar 16 12:25:48 PM PDT 24
Peak memory 214172 kb
Host smart-6123f6ed-b8a9-446c-8e54-e0ee9556ef07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559858530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3559858530
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2711191667
Short name T72
Test name
Test status
Simulation time 1367003439 ps
CPU time 38.09 seconds
Started Mar 16 12:25:34 PM PDT 24
Finished Mar 16 12:26:14 PM PDT 24
Peak memory 214536 kb
Host smart-795fc197-7cb3-4605-b464-2530a12ddb28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2711191667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2711191667
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1018382533
Short name T199
Test name
Test status
Simulation time 678526219 ps
CPU time 27.9 seconds
Started Mar 16 12:25:48 PM PDT 24
Finished Mar 16 12:26:18 PM PDT 24
Peak memory 222372 kb
Host smart-8a6f09db-49a8-43c3-a3d6-f15c6f707b01
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018382533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1018382533
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.532577404
Short name T48
Test name
Test status
Simulation time 1028720402 ps
CPU time 11.37 seconds
Started Mar 16 12:24:38 PM PDT 24
Finished Mar 16 12:24:49 PM PDT 24
Peak memory 222460 kb
Host smart-1490cee5-43b5-45b8-ada1-672d671dc2bf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532577404 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.532577404
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3449117372
Short name T413
Test name
Test status
Simulation time 326104033 ps
CPU time 13.02 seconds
Started Mar 16 12:24:45 PM PDT 24
Finished Mar 16 12:24:58 PM PDT 24
Peak memory 214960 kb
Host smart-84fe4443-096a-46c3-b010-848ed27f5c19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3449117372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3449117372
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.171159916
Short name T90
Test name
Test status
Simulation time 391514363 ps
CPU time 7.28 seconds
Started Mar 16 12:25:17 PM PDT 24
Finished Mar 16 12:25:26 PM PDT 24
Peak memory 219944 kb
Host smart-96af938b-d603-43be-ae13-b128308906e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171159916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.171159916
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3740485258
Short name T211
Test name
Test status
Simulation time 7401899944 ps
CPU time 48.71 seconds
Started Mar 16 12:25:33 PM PDT 24
Finished Mar 16 12:26:22 PM PDT 24
Peak memory 222456 kb
Host smart-23b0bd91-508d-4f1c-8ab0-1557733bfa9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740485258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3740485258
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.1815724039
Short name T118
Test name
Test status
Simulation time 107585778 ps
CPU time 2.97 seconds
Started Mar 16 12:22:02 PM PDT 24
Finished Mar 16 12:22:05 PM PDT 24
Peak memory 213500 kb
Host smart-33f59f83-d9d2-4915-bec3-d90ea12a435c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815724039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.1815724039
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1544582348
Short name T1028
Test name
Test status
Simulation time 5745759251 ps
CPU time 76.62 seconds
Started Mar 16 12:24:52 PM PDT 24
Finished Mar 16 12:26:08 PM PDT 24
Peak memory 214392 kb
Host smart-b44d3322-0155-4d92-96c2-5d4d4cad46da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1544582348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1544582348
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.4190698914
Short name T46
Test name
Test status
Simulation time 26185653369 ps
CPU time 76.45 seconds
Started Mar 16 12:24:40 PM PDT 24
Finished Mar 16 12:25:57 PM PDT 24
Peak memory 222416 kb
Host smart-e9161df9-9a98-4e74-bfb0-d52d933d2577
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190698914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.4190698914
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.269852073
Short name T32
Test name
Test status
Simulation time 161084730 ps
CPU time 5.37 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:23:45 PM PDT 24
Peak memory 210028 kb
Host smart-70b4332f-d832-4572-aa1b-9311fbd4cf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269852073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.269852073
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1359458682
Short name T88
Test name
Test status
Simulation time 447864122 ps
CPU time 3.99 seconds
Started Mar 16 12:24:27 PM PDT 24
Finished Mar 16 12:24:33 PM PDT 24
Peak memory 209092 kb
Host smart-5f799902-2118-463f-83be-a6666b711e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359458682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1359458682
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.4161004958
Short name T37
Test name
Test status
Simulation time 190934883 ps
CPU time 3.43 seconds
Started Mar 16 12:24:44 PM PDT 24
Finished Mar 16 12:24:47 PM PDT 24
Peak memory 218372 kb
Host smart-724499b9-8d9a-4788-a7e7-19a0a481c49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161004958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.4161004958
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.342301214
Short name T81
Test name
Test status
Simulation time 62218093 ps
CPU time 3.97 seconds
Started Mar 16 12:24:00 PM PDT 24
Finished Mar 16 12:24:04 PM PDT 24
Peak memory 214932 kb
Host smart-31815e58-11b3-4738-a794-d5efdfd9f423
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=342301214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.342301214
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1325534424
Short name T148
Test name
Test status
Simulation time 624409753 ps
CPU time 4.32 seconds
Started Mar 16 12:21:58 PM PDT 24
Finished Mar 16 12:22:03 PM PDT 24
Peak memory 208312 kb
Host smart-5df16ed5-8ebc-44c9-bcc6-ffa7359d7a73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325534424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1325534424
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3402078700
Short name T137
Test name
Test status
Simulation time 122210409 ps
CPU time 5.11 seconds
Started Mar 16 12:23:41 PM PDT 24
Finished Mar 16 12:23:47 PM PDT 24
Peak memory 222568 kb
Host smart-163b6e00-256d-48ac-9b85-b21bc4abeb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402078700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3402078700
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3081184867
Short name T57
Test name
Test status
Simulation time 355726704 ps
CPU time 17.55 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:50 PM PDT 24
Peak memory 222044 kb
Host smart-7c772070-8fe7-4e87-9bcb-9015617eff7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081184867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3081184867
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.213944758
Short name T309
Test name
Test status
Simulation time 304854491 ps
CPU time 15.39 seconds
Started Mar 16 12:25:05 PM PDT 24
Finished Mar 16 12:25:20 PM PDT 24
Peak memory 214996 kb
Host smart-e5913496-c0b9-424d-b29c-64f991e7d044
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=213944758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.213944758
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3704553853
Short name T233
Test name
Test status
Simulation time 674333394 ps
CPU time 8.26 seconds
Started Mar 16 12:25:36 PM PDT 24
Finished Mar 16 12:25:45 PM PDT 24
Peak memory 214188 kb
Host smart-aa4e4c10-8b5c-4c23-91c9-a81a45781309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704553853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3704553853
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.45850080
Short name T253
Test name
Test status
Simulation time 507570295 ps
CPU time 28.65 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:30 PM PDT 24
Peak memory 222440 kb
Host smart-c89d33db-a094-48e8-92e6-30f930bc0356
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=45850080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.45850080
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1629445034
Short name T87
Test name
Test status
Simulation time 182016193 ps
CPU time 5.89 seconds
Started Mar 16 12:24:35 PM PDT 24
Finished Mar 16 12:24:41 PM PDT 24
Peak memory 209932 kb
Host smart-0da46093-27a6-41ac-9d93-d3c63209dca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629445034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1629445034
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2690124693
Short name T336
Test name
Test status
Simulation time 2001454872 ps
CPU time 13.95 seconds
Started Mar 16 12:24:35 PM PDT 24
Finished Mar 16 12:24:49 PM PDT 24
Peak memory 215692 kb
Host smart-baeacba2-2165-422e-81e4-999f477a3820
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2690124693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2690124693
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2184832372
Short name T26
Test name
Test status
Simulation time 2240642598 ps
CPU time 61.22 seconds
Started Mar 16 12:24:54 PM PDT 24
Finished Mar 16 12:25:55 PM PDT 24
Peak memory 214248 kb
Host smart-bc7e40d8-e47c-45a7-8d07-e36c5e32b7fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184832372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2184832372
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.445807401
Short name T250
Test name
Test status
Simulation time 34334837 ps
CPU time 2.37 seconds
Started Mar 16 12:24:32 PM PDT 24
Finished Mar 16 12:24:35 PM PDT 24
Peak memory 207524 kb
Host smart-2faa55a4-d6da-4055-87ee-f4e3b331fb6f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445807401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.445807401
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.4027992977
Short name T610
Test name
Test status
Simulation time 21763097 ps
CPU time 0.94 seconds
Started Mar 16 12:23:54 PM PDT 24
Finished Mar 16 12:23:57 PM PDT 24
Peak memory 205764 kb
Host smart-c89101f1-3d00-438d-b95a-b75b5f7cd8f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027992977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.4027992977
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2511216435
Short name T221
Test name
Test status
Simulation time 143727747 ps
CPU time 7.8 seconds
Started Mar 16 12:24:17 PM PDT 24
Finished Mar 16 12:24:25 PM PDT 24
Peak memory 222240 kb
Host smart-7493cd86-22aa-44f9-87ff-4984a4b623b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511216435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2511216435
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.181307916
Short name T156
Test name
Test status
Simulation time 702721027 ps
CPU time 15.51 seconds
Started Mar 16 12:22:01 PM PDT 24
Finished Mar 16 12:22:16 PM PDT 24
Peak memory 213440 kb
Host smart-5c9cc1db-8fe3-4a6b-ad44-0afbb7ca38e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181307916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.181307916
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2865810930
Short name T157
Test name
Test status
Simulation time 5210818283 ps
CPU time 80.19 seconds
Started Mar 16 12:21:43 PM PDT 24
Finished Mar 16 12:23:03 PM PDT 24
Peak memory 213776 kb
Host smart-edbabc4a-b781-4dd0-b3b8-fae276f7e6d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865810930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2865810930
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2302063485
Short name T135
Test name
Test status
Simulation time 68710779 ps
CPU time 2.48 seconds
Started Mar 16 12:23:59 PM PDT 24
Finished Mar 16 12:24:02 PM PDT 24
Peak memory 217628 kb
Host smart-ddf4feff-4808-4a22-80d2-e674fe5eaf7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302063485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2302063485
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3534671614
Short name T68
Test name
Test status
Simulation time 7091756848 ps
CPU time 132.35 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:26:14 PM PDT 24
Peak memory 222388 kb
Host smart-94f15a46-3426-4baa-9693-bf25ac1ce15b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534671614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3534671614
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2404667457
Short name T382
Test name
Test status
Simulation time 75120674 ps
CPU time 4.38 seconds
Started Mar 16 12:26:10 PM PDT 24
Finished Mar 16 12:26:15 PM PDT 24
Peak memory 214156 kb
Host smart-46b6a211-8cc3-48c5-b500-0abce5c7d361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404667457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2404667457
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2789027236
Short name T241
Test name
Test status
Simulation time 573132470 ps
CPU time 15.2 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:24:56 PM PDT 24
Peak memory 214204 kb
Host smart-bb978f54-fe62-421e-9206-acf59bcecbb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2789027236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2789027236
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.856490860
Short name T319
Test name
Test status
Simulation time 458090171 ps
CPU time 5.77 seconds
Started Mar 16 12:25:37 PM PDT 24
Finished Mar 16 12:25:43 PM PDT 24
Peak memory 214400 kb
Host smart-c1e28751-94e4-4bc3-b5f1-b1a6777714d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856490860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.856490860
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2900252094
Short name T19
Test name
Test status
Simulation time 157470614 ps
CPU time 2.09 seconds
Started Mar 16 12:25:33 PM PDT 24
Finished Mar 16 12:25:35 PM PDT 24
Peak memory 208476 kb
Host smart-ed9059c4-6126-465c-a9bb-a136cedfee15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900252094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2900252094
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.163131425
Short name T141
Test name
Test status
Simulation time 713562376 ps
CPU time 3.97 seconds
Started Mar 16 12:24:04 PM PDT 24
Finished Mar 16 12:24:09 PM PDT 24
Peak memory 222604 kb
Host smart-1da92252-43ae-47bb-a54c-603ee1b53a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163131425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.163131425
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.89659453
Short name T207
Test name
Test status
Simulation time 5580428287 ps
CPU time 50.33 seconds
Started Mar 16 12:23:59 PM PDT 24
Finished Mar 16 12:24:50 PM PDT 24
Peak memory 215520 kb
Host smart-bbc57fdb-04c9-4707-828e-612bdb90d7e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89659453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.89659453
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.4213917224
Short name T412
Test name
Test status
Simulation time 439984899 ps
CPU time 6.3 seconds
Started Mar 16 12:24:32 PM PDT 24
Finished Mar 16 12:24:39 PM PDT 24
Peak memory 214184 kb
Host smart-093b07ae-f506-4473-a819-f970377f7f83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4213917224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.4213917224
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.534970948
Short name T237
Test name
Test status
Simulation time 164399315 ps
CPU time 3.82 seconds
Started Mar 16 12:24:27 PM PDT 24
Finished Mar 16 12:24:33 PM PDT 24
Peak memory 208640 kb
Host smart-66aa4886-1116-4509-baeb-723ac80e72cf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534970948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.534970948
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.262766674
Short name T267
Test name
Test status
Simulation time 61529834 ps
CPU time 4.15 seconds
Started Mar 16 12:25:06 PM PDT 24
Finished Mar 16 12:25:10 PM PDT 24
Peak memory 222440 kb
Host smart-689f39d8-9e1f-4b92-a04d-57f21ca6c70d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=262766674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.262766674
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2378854532
Short name T60
Test name
Test status
Simulation time 55035072 ps
CPU time 3.39 seconds
Started Mar 16 12:25:50 PM PDT 24
Finished Mar 16 12:25:55 PM PDT 24
Peak memory 210736 kb
Host smart-8b05d963-a11b-4671-b342-060a9b4260fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378854532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2378854532
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3239071549
Short name T146
Test name
Test status
Simulation time 124521649 ps
CPU time 4.98 seconds
Started Mar 16 12:21:56 PM PDT 24
Finished Mar 16 12:22:01 PM PDT 24
Peak memory 208712 kb
Host smart-509feee8-2186-4f62-ac3e-65bab8c5ae58
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239071549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3239071549
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2332863804
Short name T151
Test name
Test status
Simulation time 195280575 ps
CPU time 3.41 seconds
Started Mar 16 12:21:54 PM PDT 24
Finished Mar 16 12:21:58 PM PDT 24
Peak memory 208832 kb
Host smart-da15862c-a2c8-4917-9bfb-56630b08fd5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332863804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2332863804
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2139847967
Short name T40
Test name
Test status
Simulation time 2033733805 ps
CPU time 16.57 seconds
Started Mar 16 12:23:38 PM PDT 24
Finished Mar 16 12:23:55 PM PDT 24
Peak memory 231304 kb
Host smart-76317c37-9b10-48e5-81fe-17d8e57a8b24
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139847967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2139847967
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3963747736
Short name T140
Test name
Test status
Simulation time 39559164 ps
CPU time 3.17 seconds
Started Mar 16 12:25:15 PM PDT 24
Finished Mar 16 12:25:19 PM PDT 24
Peak memory 217840 kb
Host smart-38ce714b-c0ac-4d75-a1c5-56ec85735099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963747736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3963747736
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3753873716
Short name T64
Test name
Test status
Simulation time 1410143518 ps
CPU time 9.26 seconds
Started Mar 16 12:23:24 PM PDT 24
Finished Mar 16 12:23:34 PM PDT 24
Peak memory 219984 kb
Host smart-09fd7a09-04fa-4368-b738-2d4861f1d5f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753873716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3753873716
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1647187128
Short name T332
Test name
Test status
Simulation time 3265453066 ps
CPU time 77.65 seconds
Started Mar 16 12:24:19 PM PDT 24
Finished Mar 16 12:25:37 PM PDT 24
Peak memory 222132 kb
Host smart-27cfd5f3-6f57-43ac-a9a5-eba468fc079e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647187128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1647187128
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3796603701
Short name T193
Test name
Test status
Simulation time 109708828 ps
CPU time 3.01 seconds
Started Mar 16 12:24:33 PM PDT 24
Finished Mar 16 12:24:36 PM PDT 24
Peak memory 208600 kb
Host smart-d942da8f-6d19-4838-8784-802e139b5ec1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796603701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3796603701
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1609202647
Short name T4
Test name
Test status
Simulation time 40059999 ps
CPU time 2.62 seconds
Started Mar 16 12:24:37 PM PDT 24
Finished Mar 16 12:24:39 PM PDT 24
Peak memory 208400 kb
Host smart-346a0d28-585a-472a-a4fc-cd245348bdc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609202647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1609202647
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.218994590
Short name T337
Test name
Test status
Simulation time 231914754 ps
CPU time 11.99 seconds
Started Mar 16 12:25:53 PM PDT 24
Finished Mar 16 12:26:06 PM PDT 24
Peak memory 214676 kb
Host smart-81c3a995-d4b4-4cee-8933-5bb8c912e929
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218994590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.218994590
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1141203849
Short name T275
Test name
Test status
Simulation time 3762502330 ps
CPU time 10.08 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:42 PM PDT 24
Peak memory 214308 kb
Host smart-2c22a706-898d-499a-82a1-b172c12d14d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141203849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1141203849
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1274319617
Short name T315
Test name
Test status
Simulation time 337247636 ps
CPU time 13.18 seconds
Started Mar 16 12:25:41 PM PDT 24
Finished Mar 16 12:26:00 PM PDT 24
Peak memory 214140 kb
Host smart-9e4e9737-b770-40bd-baee-26da412340a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274319617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1274319617
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.478213599
Short name T296
Test name
Test status
Simulation time 17213880566 ps
CPU time 43.27 seconds
Started Mar 16 12:25:36 PM PDT 24
Finished Mar 16 12:26:20 PM PDT 24
Peak memory 209076 kb
Host smart-409ebedf-2e91-44e3-9454-8618926af41e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478213599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.478213599
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1552867207
Short name T427
Test name
Test status
Simulation time 880486073 ps
CPU time 10.19 seconds
Started Mar 16 12:23:48 PM PDT 24
Finished Mar 16 12:23:58 PM PDT 24
Peak memory 214280 kb
Host smart-52e984d3-eaf5-4c16-a5cd-36f7f7b50af3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1552867207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1552867207
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2676023744
Short name T62
Test name
Test status
Simulation time 11693149750 ps
CPU time 130.79 seconds
Started Mar 16 12:23:40 PM PDT 24
Finished Mar 16 12:25:51 PM PDT 24
Peak memory 217192 kb
Host smart-0dc40050-7a8b-4b8e-b9ad-3458d1f2d6aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676023744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2676023744
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.944161457
Short name T149
Test name
Test status
Simulation time 108944740 ps
CPU time 5.54 seconds
Started Mar 16 12:21:46 PM PDT 24
Finished Mar 16 12:21:51 PM PDT 24
Peak memory 208308 kb
Host smart-eb64e81f-e12d-44f4-a0ce-b3a45d9fb4eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944161457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
944161457
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2137981447
Short name T100
Test name
Test status
Simulation time 444480434 ps
CPU time 6.6 seconds
Started Mar 16 12:24:03 PM PDT 24
Finished Mar 16 12:24:10 PM PDT 24
Peak memory 223592 kb
Host smart-e5293592-e84c-42ff-a2ee-3584bcba6bdb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137981447 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2137981447
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3297849162
Short name T82
Test name
Test status
Simulation time 283078652 ps
CPU time 6.53 seconds
Started Mar 16 12:24:04 PM PDT 24
Finished Mar 16 12:24:10 PM PDT 24
Peak memory 220048 kb
Host smart-4b0da758-88c7-4b0c-abbe-0ecd0a45d5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297849162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3297849162
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.322259341
Short name T153
Test name
Test status
Simulation time 192812425 ps
CPU time 2.32 seconds
Started Mar 16 12:23:32 PM PDT 24
Finished Mar 16 12:23:35 PM PDT 24
Peak memory 210184 kb
Host smart-a42a8d65-0234-4fcf-8261-ec6bfb3fcdcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322259341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.322259341
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1491697499
Short name T139
Test name
Test status
Simulation time 4051279849 ps
CPU time 89.46 seconds
Started Mar 16 12:23:28 PM PDT 24
Finished Mar 16 12:24:57 PM PDT 24
Peak memory 224128 kb
Host smart-89e8becb-073b-4b1d-8605-8cd18ba4830d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491697499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1491697499
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.537863334
Short name T145
Test name
Test status
Simulation time 929045079 ps
CPU time 5.89 seconds
Started Mar 16 12:23:55 PM PDT 24
Finished Mar 16 12:24:02 PM PDT 24
Peak memory 222772 kb
Host smart-20df6b9b-101e-4ac4-9958-a0dbf53cb390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537863334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.537863334
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1960157459
Short name T136
Test name
Test status
Simulation time 1321158783 ps
CPU time 5.27 seconds
Started Mar 16 12:24:58 PM PDT 24
Finished Mar 16 12:25:03 PM PDT 24
Peak memory 222504 kb
Host smart-a66ba548-7a38-4864-ac0e-0fddab12c935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960157459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1960157459
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2079382892
Short name T138
Test name
Test status
Simulation time 145472115 ps
CPU time 6.05 seconds
Started Mar 16 12:25:18 PM PDT 24
Finished Mar 16 12:25:25 PM PDT 24
Peak memory 217024 kb
Host smart-ec34add7-2e09-49bb-8e42-b98cc06b4af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079382892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2079382892
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3464765881
Short name T142
Test name
Test status
Simulation time 172339492 ps
CPU time 2.15 seconds
Started Mar 16 12:25:42 PM PDT 24
Finished Mar 16 12:25:44 PM PDT 24
Peak memory 215964 kb
Host smart-3457cde2-bad1-4d4d-ad5f-355eeb21fce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464765881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3464765881
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1685808517
Short name T344
Test name
Test status
Simulation time 128226447 ps
CPU time 5.46 seconds
Started Mar 16 12:23:52 PM PDT 24
Finished Mar 16 12:24:00 PM PDT 24
Peak memory 222304 kb
Host smart-a4ba6caa-964d-474e-8cb5-a9e956f0bb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685808517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1685808517
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2315538844
Short name T343
Test name
Test status
Simulation time 701458758 ps
CPU time 6.71 seconds
Started Mar 16 12:24:29 PM PDT 24
Finished Mar 16 12:24:37 PM PDT 24
Peak memory 214208 kb
Host smart-bedd3313-14d6-4971-9f8a-5486323505a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315538844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2315538844
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2005856158
Short name T288
Test name
Test status
Simulation time 244020064 ps
CPU time 3.25 seconds
Started Mar 16 12:25:33 PM PDT 24
Finished Mar 16 12:25:37 PM PDT 24
Peak memory 208328 kb
Host smart-0e0fdf78-93da-452a-a0de-63ec96c1d041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005856158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2005856158
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2153081711
Short name T216
Test name
Test status
Simulation time 33842152 ps
CPU time 2.64 seconds
Started Mar 16 12:25:27 PM PDT 24
Finished Mar 16 12:25:30 PM PDT 24
Peak memory 213952 kb
Host smart-e5f0729e-b720-4809-868a-cfa418f1f5e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2153081711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2153081711
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3585742766
Short name T279
Test name
Test status
Simulation time 2115618219 ps
CPU time 55.17 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:26:27 PM PDT 24
Peak memory 214948 kb
Host smart-49d6f1a8-8984-4e00-a43b-b5d7a152ed6b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585742766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3585742766
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1034111974
Short name T349
Test name
Test status
Simulation time 8946087031 ps
CPU time 79.27 seconds
Started Mar 16 12:25:40 PM PDT 24
Finished Mar 16 12:26:59 PM PDT 24
Peak memory 222372 kb
Host smart-a79c6490-f8a3-4410-ad5f-11c73232efe6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034111974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1034111974
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.4145262100
Short name T212
Test name
Test status
Simulation time 371379862 ps
CPU time 17.72 seconds
Started Mar 16 12:25:41 PM PDT 24
Finished Mar 16 12:25:59 PM PDT 24
Peak memory 216728 kb
Host smart-63502869-0408-40b6-8b5c-c5fab7325429
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145262100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.4145262100
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3176145504
Short name T159
Test name
Test status
Simulation time 10778639358 ps
CPU time 102.19 seconds
Started Mar 16 12:21:53 PM PDT 24
Finished Mar 16 12:23:36 PM PDT 24
Peak memory 223784 kb
Host smart-d6fed747-2dce-401a-8695-4906975afadb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176145504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3176145504
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2545936466
Short name T150
Test name
Test status
Simulation time 144805967 ps
CPU time 4.37 seconds
Started Mar 16 12:22:05 PM PDT 24
Finished Mar 16 12:22:10 PM PDT 24
Peak memory 213452 kb
Host smart-74e82ca5-74a5-4534-8966-9783935f3bfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545936466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2545936466
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.771805728
Short name T163
Test name
Test status
Simulation time 10982264335 ps
CPU time 111.05 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:23:42 PM PDT 24
Peak memory 227864 kb
Host smart-22bb543d-92f6-412b-b024-b4ca5b6bc3e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771805728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
771805728
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.669782531
Short name T21
Test name
Test status
Simulation time 194887357 ps
CPU time 2.12 seconds
Started Mar 16 12:23:23 PM PDT 24
Finished Mar 16 12:23:25 PM PDT 24
Peak memory 208948 kb
Host smart-9d3e5492-443e-4c52-a376-2564cc0c91a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669782531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.669782531
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3526670131
Short name T160
Test name
Test status
Simulation time 169422240 ps
CPU time 1.62 seconds
Started Mar 16 12:23:48 PM PDT 24
Finished Mar 16 12:23:50 PM PDT 24
Peak memory 210328 kb
Host smart-61899d05-afa9-4f53-aed4-4da3ef7931d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526670131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3526670131
Directory /workspace/9.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1771070377
Short name T144
Test name
Test status
Simulation time 95851333 ps
CPU time 2.28 seconds
Started Mar 16 12:24:46 PM PDT 24
Finished Mar 16 12:24:49 PM PDT 24
Peak memory 215392 kb
Host smart-7dc1f18c-4cb5-4e5e-8eff-2469f43f7bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771070377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1771070377
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3647603505
Short name T143
Test name
Test status
Simulation time 170679784 ps
CPU time 2.97 seconds
Started Mar 16 12:24:34 PM PDT 24
Finished Mar 16 12:24:38 PM PDT 24
Peak memory 222456 kb
Host smart-877bcd14-6699-4632-a4fc-09c508bb0c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647603505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3647603505
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1976251844
Short name T776
Test name
Test status
Simulation time 1527489795 ps
CPU time 8.35 seconds
Started Mar 16 12:24:03 PM PDT 24
Finished Mar 16 12:24:12 PM PDT 24
Peak memory 210884 kb
Host smart-4538fc0b-b008-49bf-86cd-bc9b6b3a8c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976251844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1976251844
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1137292097
Short name T226
Test name
Test status
Simulation time 123532596 ps
CPU time 4.88 seconds
Started Mar 16 12:24:07 PM PDT 24
Finished Mar 16 12:24:12 PM PDT 24
Peak memory 208760 kb
Host smart-ee6bcaf9-c875-4bfa-9aa9-e75ded3b7791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137292097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1137292097
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.903568747
Short name T292
Test name
Test status
Simulation time 2700192604 ps
CPU time 86.13 seconds
Started Mar 16 12:24:24 PM PDT 24
Finished Mar 16 12:25:51 PM PDT 24
Peak memory 222552 kb
Host smart-5e55711d-1ed9-4f28-8d0c-4e3f30663d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903568747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.903568747
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3065374984
Short name T387
Test name
Test status
Simulation time 126930290 ps
CPU time 4.14 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:35 PM PDT 24
Peak memory 208404 kb
Host smart-afe9b8c3-94ca-41ec-a210-fd1f7126eac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065374984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3065374984
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2643279509
Short name T342
Test name
Test status
Simulation time 2056810955 ps
CPU time 66.69 seconds
Started Mar 16 12:24:38 PM PDT 24
Finished Mar 16 12:25:45 PM PDT 24
Peak memory 222248 kb
Host smart-1527eb05-3a66-48c0-9336-3904f56b8c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643279509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2643279509
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2521976256
Short name T89
Test name
Test status
Simulation time 41060591 ps
CPU time 2.73 seconds
Started Mar 16 12:24:45 PM PDT 24
Finished Mar 16 12:24:48 PM PDT 24
Peak memory 219684 kb
Host smart-bb647c15-788e-448e-a2c6-aeea1ed1518b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521976256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2521976256
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.552892516
Short name T58
Test name
Test status
Simulation time 1105460322 ps
CPU time 11.36 seconds
Started Mar 16 12:24:45 PM PDT 24
Finished Mar 16 12:24:57 PM PDT 24
Peak memory 220320 kb
Host smart-5ec3acb1-e768-48bb-a5cc-7505eaabb67f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552892516 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.552892516
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.4167901793
Short name T236
Test name
Test status
Simulation time 2034341878 ps
CPU time 5.78 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:53 PM PDT 24
Peak memory 222284 kb
Host smart-659d661f-4fc7-4996-a754-426e68052962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167901793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.4167901793
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1099514012
Short name T200
Test name
Test status
Simulation time 159939765 ps
CPU time 6.93 seconds
Started Mar 16 12:25:02 PM PDT 24
Finished Mar 16 12:25:09 PM PDT 24
Peak memory 221832 kb
Host smart-190a66c9-8ec7-4ceb-ba22-ffdb27ff8e64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099514012 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1099514012
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.489998169
Short name T213
Test name
Test status
Simulation time 43006990 ps
CPU time 3.11 seconds
Started Mar 16 12:24:55 PM PDT 24
Finished Mar 16 12:24:58 PM PDT 24
Peak memory 209644 kb
Host smart-c8d740e9-a5de-44d9-999c-9879bd1e0378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489998169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.489998169
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1446922231
Short name T322
Test name
Test status
Simulation time 308626531 ps
CPU time 7.27 seconds
Started Mar 16 12:25:20 PM PDT 24
Finished Mar 16 12:25:28 PM PDT 24
Peak memory 208148 kb
Host smart-41132678-ed6b-446a-a43c-2ef2e87f1a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446922231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1446922231
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_random.2517430225
Short name T326
Test name
Test status
Simulation time 74849007 ps
CPU time 4.12 seconds
Started Mar 16 12:25:34 PM PDT 24
Finished Mar 16 12:25:39 PM PDT 24
Peak memory 207316 kb
Host smart-51726e14-d97d-4711-9bd6-99b0c313c11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517430225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2517430225
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2046401374
Short name T254
Test name
Test status
Simulation time 788728716 ps
CPU time 10.46 seconds
Started Mar 16 12:25:38 PM PDT 24
Finished Mar 16 12:25:49 PM PDT 24
Peak memory 214200 kb
Host smart-24f7ef10-5c7d-4b27-a680-9c337be5559e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2046401374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2046401374
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1884025207
Short name T204
Test name
Test status
Simulation time 89204360 ps
CPU time 2.88 seconds
Started Mar 16 12:25:52 PM PDT 24
Finished Mar 16 12:25:56 PM PDT 24
Peak memory 208928 kb
Host smart-92145d99-e03e-4b23-af4e-b52ae7fc266e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884025207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1884025207
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1968771398
Short name T575
Test name
Test status
Simulation time 65637751 ps
CPU time 0.95 seconds
Started Mar 16 12:21:46 PM PDT 24
Finished Mar 16 12:21:47 PM PDT 24
Peak memory 205060 kb
Host smart-867ef7ce-5593-4a75-9960-5894b5100743
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968771398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
968771398
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3578964242
Short name T497
Test name
Test status
Simulation time 318444004 ps
CPU time 1.29 seconds
Started Mar 16 12:21:49 PM PDT 24
Finished Mar 16 12:21:51 PM PDT 24
Peak memory 213412 kb
Host smart-30645c5e-5344-42c4-a3b9-a854689a7004
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578964242 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3578964242
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.4238211763
Short name T508
Test name
Test status
Simulation time 47561237 ps
CPU time 1.4 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:21:53 PM PDT 24
Peak memory 205128 kb
Host smart-42f0f738-9131-4162-bf6d-935fe7f656c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238211763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.4238211763
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3807863978
Short name T535
Test name
Test status
Simulation time 14236514 ps
CPU time 0.72 seconds
Started Mar 16 12:21:47 PM PDT 24
Finished Mar 16 12:21:48 PM PDT 24
Peak memory 205008 kb
Host smart-2fa723f3-7be0-4980-8c8a-f3e5059e391a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807863978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3807863978
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2570022842
Short name T565
Test name
Test status
Simulation time 87382524 ps
CPU time 1.38 seconds
Started Mar 16 12:21:47 PM PDT 24
Finished Mar 16 12:21:49 PM PDT 24
Peak memory 205072 kb
Host smart-68e62e53-95d8-404d-9ac4-0324659d3f56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570022842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2570022842
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2799883596
Short name T548
Test name
Test status
Simulation time 171805403 ps
CPU time 4.73 seconds
Started Mar 16 12:21:32 PM PDT 24
Finished Mar 16 12:21:37 PM PDT 24
Peak memory 214076 kb
Host smart-6eb6bf60-b829-4790-8a34-d163afc07b0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799883596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2799883596
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.4275825681
Short name T152
Test name
Test status
Simulation time 82835279 ps
CPU time 1.42 seconds
Started Mar 16 12:21:46 PM PDT 24
Finished Mar 16 12:21:48 PM PDT 24
Peak memory 213452 kb
Host smart-e839d8d4-5b08-4508-81dd-6972734ebe1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275825681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.4275825681
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3585535326
Short name T526
Test name
Test status
Simulation time 716374699 ps
CPU time 12.19 seconds
Started Mar 16 12:21:52 PM PDT 24
Finished Mar 16 12:22:05 PM PDT 24
Peak memory 205092 kb
Host smart-706665dd-c9ef-4eba-b9fa-1f16189ce905
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585535326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
585535326
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3288698385
Short name T551
Test name
Test status
Simulation time 31566106 ps
CPU time 1.45 seconds
Started Mar 16 12:21:49 PM PDT 24
Finished Mar 16 12:21:50 PM PDT 24
Peak memory 213300 kb
Host smart-58d7b209-ad80-418e-b771-ff45ad5e21b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288698385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
288698385
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3359505170
Short name T512
Test name
Test status
Simulation time 598202008 ps
CPU time 1.39 seconds
Started Mar 16 12:21:48 PM PDT 24
Finished Mar 16 12:21:50 PM PDT 24
Peak memory 213452 kb
Host smart-5165daee-4fc9-45e4-a515-d0a1b662ddb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359505170 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3359505170
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2628796893
Short name T483
Test name
Test status
Simulation time 7957084 ps
CPU time 0.71 seconds
Started Mar 16 12:21:40 PM PDT 24
Finished Mar 16 12:21:41 PM PDT 24
Peak memory 205044 kb
Host smart-0d1f15af-602b-47fa-a068-a3a439fb5faf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628796893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2628796893
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3060442468
Short name T553
Test name
Test status
Simulation time 129159775 ps
CPU time 1.98 seconds
Started Mar 16 12:21:55 PM PDT 24
Finished Mar 16 12:21:57 PM PDT 24
Peak memory 205196 kb
Host smart-fe9fb027-6c0a-4d37-a8a6-8fe542a357aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060442468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3060442468
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.684792296
Short name T538
Test name
Test status
Simulation time 166715407 ps
CPU time 4.08 seconds
Started Mar 16 12:21:45 PM PDT 24
Finished Mar 16 12:21:50 PM PDT 24
Peak memory 213696 kb
Host smart-7b59efff-fc04-4a4c-a848-b459672fef80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684792296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.684792296
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3944525874
Short name T112
Test name
Test status
Simulation time 244216001 ps
CPU time 10.12 seconds
Started Mar 16 12:21:52 PM PDT 24
Finished Mar 16 12:22:02 PM PDT 24
Peak memory 213536 kb
Host smart-db63d450-f20a-4675-877f-57a5aae642d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944525874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3944525874
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1023946756
Short name T168
Test name
Test status
Simulation time 476058175 ps
CPU time 2.87 seconds
Started Mar 16 12:21:48 PM PDT 24
Finished Mar 16 12:21:52 PM PDT 24
Peak memory 215436 kb
Host smart-5b4fd920-8968-44eb-a941-157541d34856
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023946756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1023946756
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3383739199
Short name T540
Test name
Test status
Simulation time 29614981 ps
CPU time 1.06 seconds
Started Mar 16 12:22:02 PM PDT 24
Finished Mar 16 12:22:03 PM PDT 24
Peak memory 205236 kb
Host smart-0b93223b-89bd-4e21-bc52-10b13b4cfe8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383739199 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3383739199
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.255108970
Short name T446
Test name
Test status
Simulation time 56583747 ps
CPU time 0.96 seconds
Started Mar 16 12:21:56 PM PDT 24
Finished Mar 16 12:21:57 PM PDT 24
Peak memory 204932 kb
Host smart-418dbef8-e23e-404d-9132-132fa295ef55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255108970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.255108970
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.938895270
Short name T530
Test name
Test status
Simulation time 13409037 ps
CPU time 0.86 seconds
Started Mar 16 12:22:01 PM PDT 24
Finished Mar 16 12:22:02 PM PDT 24
Peak memory 205072 kb
Host smart-219c2b37-1a5b-4292-b23f-df340ee1810e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938895270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.938895270
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2467559473
Short name T127
Test name
Test status
Simulation time 91687260 ps
CPU time 2.84 seconds
Started Mar 16 12:21:56 PM PDT 24
Finished Mar 16 12:21:59 PM PDT 24
Peak memory 205340 kb
Host smart-77e242df-e278-4396-ac6d-035be39f5c3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467559473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2467559473
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.972000018
Short name T544
Test name
Test status
Simulation time 85534215 ps
CPU time 2.05 seconds
Started Mar 16 12:22:07 PM PDT 24
Finished Mar 16 12:22:10 PM PDT 24
Peak memory 213888 kb
Host smart-aed82613-67cd-40d1-82a8-006371175eca
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972000018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.972000018
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2599560472
Short name T571
Test name
Test status
Simulation time 234219138 ps
CPU time 9.77 seconds
Started Mar 16 12:21:54 PM PDT 24
Finished Mar 16 12:22:04 PM PDT 24
Peak memory 213516 kb
Host smart-cd36f892-7545-496d-a9c4-2bd56175afec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599560472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2599560472
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2500234848
Short name T170
Test name
Test status
Simulation time 125082131 ps
CPU time 1.91 seconds
Started Mar 16 12:21:53 PM PDT 24
Finished Mar 16 12:21:55 PM PDT 24
Peak memory 205108 kb
Host smart-b38bc9df-fc35-4560-8e0f-391488325b01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500234848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2500234848
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2035083089
Short name T154
Test name
Test status
Simulation time 710607370 ps
CPU time 5.35 seconds
Started Mar 16 12:22:02 PM PDT 24
Finished Mar 16 12:22:07 PM PDT 24
Peak memory 208716 kb
Host smart-0cf73cca-3767-4381-9381-40e78f9e8458
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035083089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2035083089
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2601375712
Short name T546
Test name
Test status
Simulation time 122686107 ps
CPU time 1.46 seconds
Started Mar 16 12:22:02 PM PDT 24
Finished Mar 16 12:22:03 PM PDT 24
Peak memory 221552 kb
Host smart-b6c0bf1f-9c81-4d76-8f32-46ce8aee4a8c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601375712 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2601375712
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3730879679
Short name T460
Test name
Test status
Simulation time 72119422 ps
CPU time 1 seconds
Started Mar 16 12:21:53 PM PDT 24
Finished Mar 16 12:21:54 PM PDT 24
Peak memory 205052 kb
Host smart-3769311c-3fad-454f-93a0-f00a849c01d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730879679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3730879679
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1771339146
Short name T468
Test name
Test status
Simulation time 115631629 ps
CPU time 0.78 seconds
Started Mar 16 12:22:08 PM PDT 24
Finished Mar 16 12:22:08 PM PDT 24
Peak memory 205148 kb
Host smart-095fb215-f00d-4b55-8893-01fb129afee7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771339146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1771339146
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.628383022
Short name T558
Test name
Test status
Simulation time 211307521 ps
CPU time 2.81 seconds
Started Mar 16 12:21:54 PM PDT 24
Finished Mar 16 12:21:57 PM PDT 24
Peak memory 213640 kb
Host smart-b4cad043-1054-4cd0-9ae4-46b65b2e6051
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628383022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.628383022
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2761929340
Short name T561
Test name
Test status
Simulation time 121144444 ps
CPU time 5.35 seconds
Started Mar 16 12:21:54 PM PDT 24
Finished Mar 16 12:22:00 PM PDT 24
Peak memory 213424 kb
Host smart-4848c61d-c6bb-4a8c-8663-0ab4935000ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761929340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2761929340
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3239157107
Short name T449
Test name
Test status
Simulation time 489040544 ps
CPU time 2.97 seconds
Started Mar 16 12:22:07 PM PDT 24
Finished Mar 16 12:22:10 PM PDT 24
Peak memory 221688 kb
Host smart-11be12fb-4a78-43c2-9fa4-c5ae1b7da383
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239157107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3239157107
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3356566720
Short name T501
Test name
Test status
Simulation time 71713518 ps
CPU time 1.45 seconds
Started Mar 16 12:22:03 PM PDT 24
Finished Mar 16 12:22:05 PM PDT 24
Peak memory 213516 kb
Host smart-82c63e96-f960-4fc1-88fd-d560d1d6c293
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356566720 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3356566720
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3104242050
Short name T510
Test name
Test status
Simulation time 48988674 ps
CPU time 0.88 seconds
Started Mar 16 12:22:01 PM PDT 24
Finished Mar 16 12:22:02 PM PDT 24
Peak memory 205028 kb
Host smart-ad9f1a03-2130-4195-830c-9fb2c4e2a146
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104242050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3104242050
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2845304241
Short name T458
Test name
Test status
Simulation time 52689001 ps
CPU time 2.14 seconds
Started Mar 16 12:22:01 PM PDT 24
Finished Mar 16 12:22:03 PM PDT 24
Peak memory 205152 kb
Host smart-9131aadc-fa36-4273-b401-c769ec0e2c3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845304241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2845304241
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2389165793
Short name T174
Test name
Test status
Simulation time 355270178 ps
CPU time 7.02 seconds
Started Mar 16 12:21:54 PM PDT 24
Finished Mar 16 12:22:01 PM PDT 24
Peak memory 213520 kb
Host smart-2cd834be-2af1-49d0-ab61-828a73038d27
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389165793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2389165793
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.531456907
Short name T469
Test name
Test status
Simulation time 235268434 ps
CPU time 8.37 seconds
Started Mar 16 12:22:07 PM PDT 24
Finished Mar 16 12:22:16 PM PDT 24
Peak memory 213820 kb
Host smart-196a77bd-ed3e-4590-adba-e87717081a57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531456907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.531456907
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.947783272
Short name T511
Test name
Test status
Simulation time 61083134 ps
CPU time 1.73 seconds
Started Mar 16 12:21:55 PM PDT 24
Finished Mar 16 12:21:56 PM PDT 24
Peak memory 213412 kb
Host smart-76e0c627-82a6-42b8-bddc-6ec847173ca3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947783272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.947783272
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2535199647
Short name T569
Test name
Test status
Simulation time 75206780 ps
CPU time 1.33 seconds
Started Mar 16 12:21:55 PM PDT 24
Finished Mar 16 12:21:57 PM PDT 24
Peak memory 205180 kb
Host smart-2a6fb13a-229e-4a74-967c-6cc043b027d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535199647 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2535199647
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2783813041
Short name T555
Test name
Test status
Simulation time 28683208 ps
CPU time 1.05 seconds
Started Mar 16 12:22:02 PM PDT 24
Finished Mar 16 12:22:03 PM PDT 24
Peak memory 205008 kb
Host smart-fa73273b-23d6-4d13-aed8-a0c2113d340b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783813041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2783813041
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.899432520
Short name T559
Test name
Test status
Simulation time 23518563 ps
CPU time 0.73 seconds
Started Mar 16 12:21:57 PM PDT 24
Finished Mar 16 12:21:58 PM PDT 24
Peak memory 205076 kb
Host smart-3efa2231-efbe-4ffa-8c6b-f018b7bc21ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899432520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.899432520
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3829392899
Short name T564
Test name
Test status
Simulation time 569709132 ps
CPU time 2.44 seconds
Started Mar 16 12:22:05 PM PDT 24
Finished Mar 16 12:22:07 PM PDT 24
Peak memory 205176 kb
Host smart-7c4a96cc-7671-4333-a8c0-5c6ed36468be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829392899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3829392899
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2060972195
Short name T485
Test name
Test status
Simulation time 161667331 ps
CPU time 2.78 seconds
Started Mar 16 12:22:09 PM PDT 24
Finished Mar 16 12:22:12 PM PDT 24
Peak memory 213592 kb
Host smart-f7bbe7c2-7a50-4348-83cb-35e2e01fa4a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060972195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2060972195
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1993869004
Short name T466
Test name
Test status
Simulation time 836164934 ps
CPU time 5.86 seconds
Started Mar 16 12:22:03 PM PDT 24
Finished Mar 16 12:22:09 PM PDT 24
Peak memory 219612 kb
Host smart-6b0c55d0-0a29-435d-ba6d-663fd874a6d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993869004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1993869004
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2691230531
Short name T472
Test name
Test status
Simulation time 64153058 ps
CPU time 2.48 seconds
Started Mar 16 12:22:07 PM PDT 24
Finished Mar 16 12:22:10 PM PDT 24
Peak memory 213420 kb
Host smart-44ac5cab-7ce2-42b8-ab35-8c3eef1326c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691230531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2691230531
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3644526604
Short name T487
Test name
Test status
Simulation time 171962768 ps
CPU time 1.59 seconds
Started Mar 16 12:22:03 PM PDT 24
Finished Mar 16 12:22:04 PM PDT 24
Peak memory 217620 kb
Host smart-f931fa2b-c749-4586-8c0c-26f94e205de5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644526604 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3644526604
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3280855855
Short name T461
Test name
Test status
Simulation time 108005226 ps
CPU time 1.13 seconds
Started Mar 16 12:22:02 PM PDT 24
Finished Mar 16 12:22:03 PM PDT 24
Peak memory 205092 kb
Host smart-e8391372-c2ad-457a-b2f6-1529f4ec4609
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280855855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3280855855
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2880620304
Short name T445
Test name
Test status
Simulation time 11975717 ps
CPU time 0.71 seconds
Started Mar 16 12:22:00 PM PDT 24
Finished Mar 16 12:22:01 PM PDT 24
Peak memory 205016 kb
Host smart-0713d2dc-a836-4aac-9355-1bc94dd37e7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880620304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2880620304
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.451607075
Short name T504
Test name
Test status
Simulation time 36872525 ps
CPU time 2.5 seconds
Started Mar 16 12:22:03 PM PDT 24
Finished Mar 16 12:22:06 PM PDT 24
Peak memory 205136 kb
Host smart-d5f32af3-a347-410d-bfae-da329ef3a9d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451607075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.451607075
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1844999939
Short name T116
Test name
Test status
Simulation time 205399529 ps
CPU time 2.65 seconds
Started Mar 16 12:22:08 PM PDT 24
Finished Mar 16 12:22:11 PM PDT 24
Peak memory 221960 kb
Host smart-fe33e052-8dac-4f28-96a0-622c2e1a5371
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844999939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1844999939
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2971441905
Short name T475
Test name
Test status
Simulation time 101677393 ps
CPU time 3.62 seconds
Started Mar 16 12:22:00 PM PDT 24
Finished Mar 16 12:22:04 PM PDT 24
Peak memory 213540 kb
Host smart-3b795b76-ed7e-4b8f-bee6-bff18aff64d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971441905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2971441905
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1660371500
Short name T550
Test name
Test status
Simulation time 712452673 ps
CPU time 4.2 seconds
Started Mar 16 12:22:05 PM PDT 24
Finished Mar 16 12:22:09 PM PDT 24
Peak memory 213460 kb
Host smart-3f276d7c-3058-43e9-a299-8783e5b0c881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660371500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1660371500
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.4200441449
Short name T506
Test name
Test status
Simulation time 97834563 ps
CPU time 1.15 seconds
Started Mar 16 12:22:02 PM PDT 24
Finished Mar 16 12:22:04 PM PDT 24
Peak memory 213540 kb
Host smart-ab883282-441e-4ee9-a7ca-16e207eead91
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200441449 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.4200441449
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1286150833
Short name T440
Test name
Test status
Simulation time 68256579 ps
CPU time 1.01 seconds
Started Mar 16 12:22:08 PM PDT 24
Finished Mar 16 12:22:09 PM PDT 24
Peak memory 205144 kb
Host smart-46b71a65-d941-4f96-a7fa-a0ba014bcf42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286150833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1286150833
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1550545670
Short name T524
Test name
Test status
Simulation time 22564320 ps
CPU time 0.77 seconds
Started Mar 16 12:21:57 PM PDT 24
Finished Mar 16 12:21:58 PM PDT 24
Peak memory 205136 kb
Host smart-de3327e0-8e2c-486d-84ac-1826afb60d90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550545670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1550545670
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3403685239
Short name T452
Test name
Test status
Simulation time 86416566 ps
CPU time 3.37 seconds
Started Mar 16 12:22:08 PM PDT 24
Finished Mar 16 12:22:11 PM PDT 24
Peak memory 213536 kb
Host smart-84579cb5-5b01-4b82-bc07-cbf82ab20a43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403685239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3403685239
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1365407644
Short name T167
Test name
Test status
Simulation time 404191741 ps
CPU time 6.36 seconds
Started Mar 16 12:21:59 PM PDT 24
Finished Mar 16 12:22:05 PM PDT 24
Peak memory 221780 kb
Host smart-bdfb7503-d46a-4516-b3e5-0b0a31f515ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365407644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1365407644
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1245316492
Short name T528
Test name
Test status
Simulation time 3909483389 ps
CPU time 8.42 seconds
Started Mar 16 12:22:01 PM PDT 24
Finished Mar 16 12:22:09 PM PDT 24
Peak memory 213880 kb
Host smart-59dee25b-3704-49fa-a629-eb3df0e31dcd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245316492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1245316492
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2688201167
Short name T505
Test name
Test status
Simulation time 367919509 ps
CPU time 3.13 seconds
Started Mar 16 12:21:59 PM PDT 24
Finished Mar 16 12:22:02 PM PDT 24
Peak memory 213492 kb
Host smart-b5d55cf3-2a8f-4282-9fbe-330791db9e49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688201167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2688201167
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3925148334
Short name T499
Test name
Test status
Simulation time 36555038 ps
CPU time 1.36 seconds
Started Mar 16 12:22:04 PM PDT 24
Finished Mar 16 12:22:05 PM PDT 24
Peak memory 213436 kb
Host smart-d15e47f3-4463-4179-8598-f578895be28d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925148334 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3925148334
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3908050308
Short name T542
Test name
Test status
Simulation time 14550979 ps
CPU time 0.89 seconds
Started Mar 16 12:22:08 PM PDT 24
Finished Mar 16 12:22:09 PM PDT 24
Peak memory 205028 kb
Host smart-b8ed7d8d-09f2-4b1c-9cb2-ba1cb62fbabe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908050308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3908050308
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2461088454
Short name T438
Test name
Test status
Simulation time 20643950 ps
CPU time 0.91 seconds
Started Mar 16 12:22:02 PM PDT 24
Finished Mar 16 12:22:03 PM PDT 24
Peak memory 204984 kb
Host smart-561787c0-d8c0-4873-9c02-be9fff5c5edf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461088454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2461088454
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.647268338
Short name T128
Test name
Test status
Simulation time 56352834 ps
CPU time 2.2 seconds
Started Mar 16 12:22:08 PM PDT 24
Finished Mar 16 12:22:10 PM PDT 24
Peak memory 205356 kb
Host smart-c57bb61f-88d5-470a-83d0-36c379f95f42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647268338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.647268338
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.4075515447
Short name T114
Test name
Test status
Simulation time 319218831 ps
CPU time 6.19 seconds
Started Mar 16 12:22:08 PM PDT 24
Finished Mar 16 12:22:14 PM PDT 24
Peak memory 213772 kb
Host smart-a16b4b7e-d820-4661-b59c-ee6dcd91be29
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075515447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.4075515447
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1838523859
Short name T533
Test name
Test status
Simulation time 680150764 ps
CPU time 7.3 seconds
Started Mar 16 12:22:09 PM PDT 24
Finished Mar 16 12:22:16 PM PDT 24
Peak memory 213636 kb
Host smart-b0472525-44ab-4070-9cc2-81a31c9f05c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838523859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1838523859
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1883976917
Short name T124
Test name
Test status
Simulation time 61842502 ps
CPU time 1.51 seconds
Started Mar 16 12:22:03 PM PDT 24
Finished Mar 16 12:22:05 PM PDT 24
Peak memory 215532 kb
Host smart-3c3aa187-03e3-4f5a-bc2b-f49c9b3add8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883976917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1883976917
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.335512969
Short name T495
Test name
Test status
Simulation time 50173183 ps
CPU time 2.01 seconds
Started Mar 16 12:22:09 PM PDT 24
Finished Mar 16 12:22:11 PM PDT 24
Peak memory 213596 kb
Host smart-c5869f24-e66f-4dd4-95c4-899c6d63bb52
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335512969 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.335512969
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3947721160
Short name T573
Test name
Test status
Simulation time 18740005 ps
CPU time 0.91 seconds
Started Mar 16 12:22:03 PM PDT 24
Finished Mar 16 12:22:04 PM PDT 24
Peak memory 205068 kb
Host smart-cb22e5e0-0ef4-4c61-860d-c69c675eccac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947721160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3947721160
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2007504947
Short name T442
Test name
Test status
Simulation time 162963704 ps
CPU time 2.23 seconds
Started Mar 16 12:22:05 PM PDT 24
Finished Mar 16 12:22:08 PM PDT 24
Peak memory 205068 kb
Host smart-fac91738-74e8-4914-a043-10ed5ab2c232
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007504947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2007504947
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1218597561
Short name T529
Test name
Test status
Simulation time 849762533 ps
CPU time 8.01 seconds
Started Mar 16 12:22:04 PM PDT 24
Finished Mar 16 12:22:12 PM PDT 24
Peak memory 219764 kb
Host smart-c8c719aa-fb10-4948-a5bb-edb8c6cd4a39
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218597561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1218597561
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.785163012
Short name T494
Test name
Test status
Simulation time 102695311 ps
CPU time 2.09 seconds
Started Mar 16 12:22:03 PM PDT 24
Finished Mar 16 12:22:05 PM PDT 24
Peak memory 214200 kb
Host smart-c3eb78ef-4efb-442e-a30c-8370c807344d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785163012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.785163012
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3407040155
Short name T164
Test name
Test status
Simulation time 473259647 ps
CPU time 4.91 seconds
Started Mar 16 12:22:06 PM PDT 24
Finished Mar 16 12:22:11 PM PDT 24
Peak memory 213512 kb
Host smart-504c126d-bd82-4a4f-a616-7732eb35c410
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407040155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3407040155
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1065548309
Short name T480
Test name
Test status
Simulation time 120322309 ps
CPU time 2.2 seconds
Started Mar 16 12:22:10 PM PDT 24
Finished Mar 16 12:22:12 PM PDT 24
Peak memory 213392 kb
Host smart-da80fa92-e97e-495b-b078-d5f69b8daefc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065548309 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1065548309
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3218101373
Short name T507
Test name
Test status
Simulation time 54353305 ps
CPU time 0.93 seconds
Started Mar 16 12:22:11 PM PDT 24
Finished Mar 16 12:22:12 PM PDT 24
Peak memory 205032 kb
Host smart-f0641828-fb4d-4a9b-967a-8606b707450a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218101373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3218101373
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.128992542
Short name T465
Test name
Test status
Simulation time 40746202 ps
CPU time 0.83 seconds
Started Mar 16 12:22:16 PM PDT 24
Finished Mar 16 12:22:17 PM PDT 24
Peak memory 204900 kb
Host smart-16dbdd62-5474-48d6-bfcd-6ab3d8098dfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128992542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.128992542
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.866316311
Short name T129
Test name
Test status
Simulation time 333560322 ps
CPU time 2.37 seconds
Started Mar 16 12:22:13 PM PDT 24
Finished Mar 16 12:22:15 PM PDT 24
Peak memory 205292 kb
Host smart-cc7fe1ad-85d1-410d-836d-e5382a0636a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866316311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.866316311
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1010098841
Short name T513
Test name
Test status
Simulation time 2595632054 ps
CPU time 11.66 seconds
Started Mar 16 12:22:08 PM PDT 24
Finished Mar 16 12:22:19 PM PDT 24
Peak memory 213856 kb
Host smart-adbe9c63-1be0-4efb-8499-eb65132daf50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010098841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1010098841
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1774937103
Short name T113
Test name
Test status
Simulation time 214802408 ps
CPU time 9.52 seconds
Started Mar 16 12:22:02 PM PDT 24
Finished Mar 16 12:22:12 PM PDT 24
Peak memory 213632 kb
Host smart-33cd0b98-841d-461c-bf5e-bd1e4aca9c73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774937103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1774937103
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.370363847
Short name T536
Test name
Test status
Simulation time 169989585 ps
CPU time 4.14 seconds
Started Mar 16 12:22:09 PM PDT 24
Finished Mar 16 12:22:13 PM PDT 24
Peak memory 213436 kb
Host smart-07b70259-57c6-4c0e-adf5-8d41c07b287a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370363847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.370363847
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3972415098
Short name T463
Test name
Test status
Simulation time 236618453 ps
CPU time 5.03 seconds
Started Mar 16 12:22:09 PM PDT 24
Finished Mar 16 12:22:14 PM PDT 24
Peak memory 208592 kb
Host smart-5b209a80-14a4-4317-84c8-28b0c52d86ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972415098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3972415098
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3825729412
Short name T519
Test name
Test status
Simulation time 49765338 ps
CPU time 1.13 seconds
Started Mar 16 12:22:19 PM PDT 24
Finished Mar 16 12:22:21 PM PDT 24
Peak memory 205280 kb
Host smart-e14e86db-9de8-467d-89ca-e37b888bdab4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825729412 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3825729412
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1934672984
Short name T134
Test name
Test status
Simulation time 12149883 ps
CPU time 1 seconds
Started Mar 16 12:22:18 PM PDT 24
Finished Mar 16 12:22:19 PM PDT 24
Peak memory 205160 kb
Host smart-1d4e3ed1-b543-4164-ab43-d1adb2c66054
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934672984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1934672984
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.704244108
Short name T478
Test name
Test status
Simulation time 11514481 ps
CPU time 0.85 seconds
Started Mar 16 12:22:22 PM PDT 24
Finished Mar 16 12:22:23 PM PDT 24
Peak memory 204996 kb
Host smart-0c44ba8b-f65e-48a0-a2b1-21769ba17542
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704244108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.704244108
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1592666219
Short name T126
Test name
Test status
Simulation time 194096364 ps
CPU time 2.65 seconds
Started Mar 16 12:22:20 PM PDT 24
Finished Mar 16 12:22:24 PM PDT 24
Peak memory 205172 kb
Host smart-3508a266-9f3c-468a-9a61-f9cdd3738b6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592666219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1592666219
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.4213810385
Short name T531
Test name
Test status
Simulation time 566250827 ps
CPU time 4.22 seconds
Started Mar 16 12:22:10 PM PDT 24
Finished Mar 16 12:22:14 PM PDT 24
Peak memory 213516 kb
Host smart-a29019ab-0ed3-457d-8ccf-08a866d04dbc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213810385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.4213810385
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2332371219
Short name T488
Test name
Test status
Simulation time 518198635 ps
CPU time 16.4 seconds
Started Mar 16 12:22:20 PM PDT 24
Finished Mar 16 12:22:37 PM PDT 24
Peak memory 213608 kb
Host smart-707fec0e-28de-42ca-8270-805b46f30042
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332371219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2332371219
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.448822382
Short name T462
Test name
Test status
Simulation time 90856918 ps
CPU time 1.59 seconds
Started Mar 16 12:22:23 PM PDT 24
Finished Mar 16 12:22:25 PM PDT 24
Peak memory 213468 kb
Host smart-a5c28b80-c890-4d6e-af17-86f7200fd036
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448822382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.448822382
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.435665086
Short name T516
Test name
Test status
Simulation time 541285515 ps
CPU time 7.35 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:21:58 PM PDT 24
Peak memory 205056 kb
Host smart-992c8a74-f2f6-428c-bcf4-ded340947bb2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435665086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.435665086
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3775417945
Short name T566
Test name
Test status
Simulation time 12150746707 ps
CPU time 23.29 seconds
Started Mar 16 12:21:53 PM PDT 24
Finished Mar 16 12:22:16 PM PDT 24
Peak memory 205120 kb
Host smart-1dc8c424-cbaa-42d0-96dd-0a7b8bef173b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775417945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
775417945
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3328373700
Short name T541
Test name
Test status
Simulation time 68680667 ps
CPU time 0.88 seconds
Started Mar 16 12:21:41 PM PDT 24
Finished Mar 16 12:21:42 PM PDT 24
Peak memory 205048 kb
Host smart-485e1fab-3a38-4810-acd9-ef20ef26beb9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328373700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
328373700
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.3292891800
Short name T525
Test name
Test status
Simulation time 112602944 ps
CPU time 2.23 seconds
Started Mar 16 12:21:42 PM PDT 24
Finished Mar 16 12:21:44 PM PDT 24
Peak memory 213360 kb
Host smart-25004977-e7e2-4b6e-b44c-de7d52543a20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292891800 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.3292891800
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3638179510
Short name T503
Test name
Test status
Simulation time 48268061 ps
CPU time 1.1 seconds
Started Mar 16 12:21:50 PM PDT 24
Finished Mar 16 12:21:51 PM PDT 24
Peak memory 205092 kb
Host smart-16ec8f15-d3db-4123-bb0f-2469af6cb357
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638179510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3638179510
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1769333063
Short name T518
Test name
Test status
Simulation time 52050091 ps
CPU time 0.87 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:21:52 PM PDT 24
Peak memory 204956 kb
Host smart-93110b87-a752-4f72-8e2e-7970c51e5490
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769333063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1769333063
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3974210472
Short name T502
Test name
Test status
Simulation time 72255213 ps
CPU time 1.43 seconds
Started Mar 16 12:21:49 PM PDT 24
Finished Mar 16 12:21:51 PM PDT 24
Peak memory 205172 kb
Host smart-bd3433ca-df11-446a-8356-aebadada65b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974210472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3974210472
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.557265112
Short name T171
Test name
Test status
Simulation time 1930556258 ps
CPU time 5.34 seconds
Started Mar 16 12:21:48 PM PDT 24
Finished Mar 16 12:21:54 PM PDT 24
Peak memory 213672 kb
Host smart-5344bc24-cac6-4686-8e78-441fde6c94a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557265112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.557265112
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2552694865
Short name T514
Test name
Test status
Simulation time 1132469637 ps
CPU time 6.51 seconds
Started Mar 16 12:21:55 PM PDT 24
Finished Mar 16 12:22:02 PM PDT 24
Peak memory 213688 kb
Host smart-242fafe1-4aff-402f-be4c-fc2c4c4b5f25
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552694865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2552694865
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2573713036
Short name T570
Test name
Test status
Simulation time 67099890 ps
CPU time 1.91 seconds
Started Mar 16 12:21:54 PM PDT 24
Finished Mar 16 12:21:56 PM PDT 24
Peak memory 213404 kb
Host smart-c37525a8-7141-4b85-aa14-a62d1e2f5bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573713036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2573713036
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1191904417
Short name T437
Test name
Test status
Simulation time 38672175 ps
CPU time 0.78 seconds
Started Mar 16 12:22:20 PM PDT 24
Finished Mar 16 12:22:21 PM PDT 24
Peak memory 205040 kb
Host smart-38aac24b-fb25-4e26-a4cb-921fd90dd957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191904417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1191904417
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2872106085
Short name T476
Test name
Test status
Simulation time 16580649 ps
CPU time 0.77 seconds
Started Mar 16 12:22:20 PM PDT 24
Finished Mar 16 12:22:22 PM PDT 24
Peak memory 205032 kb
Host smart-07aee7f9-00fa-4498-aefa-ea4e24889fd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872106085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2872106085
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.945346547
Short name T444
Test name
Test status
Simulation time 22649355 ps
CPU time 0.73 seconds
Started Mar 16 12:22:17 PM PDT 24
Finished Mar 16 12:22:19 PM PDT 24
Peak memory 205160 kb
Host smart-bae48706-1c8a-4911-94cb-ce1c821f4381
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945346547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.945346547
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3947098163
Short name T474
Test name
Test status
Simulation time 10479430 ps
CPU time 0.81 seconds
Started Mar 16 12:22:17 PM PDT 24
Finished Mar 16 12:22:18 PM PDT 24
Peak memory 205024 kb
Host smart-d1977e39-3a48-4ef2-b020-1ff15b25825d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947098163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3947098163
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.4067856025
Short name T447
Test name
Test status
Simulation time 11027476 ps
CPU time 0.84 seconds
Started Mar 16 12:22:22 PM PDT 24
Finished Mar 16 12:22:23 PM PDT 24
Peak memory 205072 kb
Host smart-22117d5f-cdec-4696-ab24-67333c02d920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067856025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.4067856025
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3984003598
Short name T443
Test name
Test status
Simulation time 40831365 ps
CPU time 0.71 seconds
Started Mar 16 12:22:19 PM PDT 24
Finished Mar 16 12:22:21 PM PDT 24
Peak memory 205040 kb
Host smart-67bff2e5-7779-44f5-b8ad-07862184ae46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984003598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3984003598
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3997461101
Short name T133
Test name
Test status
Simulation time 24376495 ps
CPU time 0.7 seconds
Started Mar 16 12:22:18 PM PDT 24
Finished Mar 16 12:22:19 PM PDT 24
Peak memory 205040 kb
Host smart-3a3a3c04-468c-4ea7-b279-5a6a60249f81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997461101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3997461101
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2889387796
Short name T486
Test name
Test status
Simulation time 8708956 ps
CPU time 0.68 seconds
Started Mar 16 12:22:15 PM PDT 24
Finished Mar 16 12:22:16 PM PDT 24
Peak memory 205028 kb
Host smart-da846bea-3402-477b-ba25-283a8f67ffe5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889387796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2889387796
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2716188839
Short name T574
Test name
Test status
Simulation time 54919809 ps
CPU time 0.81 seconds
Started Mar 16 12:22:18 PM PDT 24
Finished Mar 16 12:22:19 PM PDT 24
Peak memory 205104 kb
Host smart-8c1bbba9-d1e9-46ad-b2e6-44c74b36708d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716188839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2716188839
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2391086746
Short name T489
Test name
Test status
Simulation time 27132926 ps
CPU time 0.81 seconds
Started Mar 16 12:22:18 PM PDT 24
Finished Mar 16 12:22:20 PM PDT 24
Peak memory 205348 kb
Host smart-a471f086-21c5-420c-8488-d24173272825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391086746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2391086746
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1760884650
Short name T130
Test name
Test status
Simulation time 248537292 ps
CPU time 7.33 seconds
Started Mar 16 12:21:54 PM PDT 24
Finished Mar 16 12:22:01 PM PDT 24
Peak memory 205208 kb
Host smart-6f48154d-739f-4607-8b36-02e0d5afaeb9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760884650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
760884650
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1066274833
Short name T456
Test name
Test status
Simulation time 2395828935 ps
CPU time 12.32 seconds
Started Mar 16 12:21:52 PM PDT 24
Finished Mar 16 12:22:04 PM PDT 24
Peak memory 205220 kb
Host smart-3e64ba79-400b-42c2-8095-fa695fdf9da0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066274833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
066274833
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3857909816
Short name T490
Test name
Test status
Simulation time 70397846 ps
CPU time 0.97 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:21:52 PM PDT 24
Peak memory 205036 kb
Host smart-111ced11-61a3-4587-89e6-5c4b06b30e38
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857909816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3
857909816
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3861864543
Short name T563
Test name
Test status
Simulation time 17672355 ps
CPU time 0.99 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:21:52 PM PDT 24
Peak memory 205192 kb
Host smart-3b8e6044-432e-435c-bd11-3916918476d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861864543 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3861864543
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.846184223
Short name T537
Test name
Test status
Simulation time 50716891 ps
CPU time 1.21 seconds
Started Mar 16 12:21:50 PM PDT 24
Finished Mar 16 12:21:52 PM PDT 24
Peak memory 205040 kb
Host smart-b8240fb2-4434-4edf-9cae-99c5dd3a2d80
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846184223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.846184223
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.896592753
Short name T131
Test name
Test status
Simulation time 9817180 ps
CPU time 0.78 seconds
Started Mar 16 12:21:50 PM PDT 24
Finished Mar 16 12:21:51 PM PDT 24
Peak memory 205024 kb
Host smart-d11516ab-290e-4ac1-bcca-ad2c9402582c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896592753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.896592753
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2078673542
Short name T568
Test name
Test status
Simulation time 82900008 ps
CPU time 1.39 seconds
Started Mar 16 12:21:59 PM PDT 24
Finished Mar 16 12:22:00 PM PDT 24
Peak memory 205256 kb
Host smart-e414e3c2-78ec-46e5-91c2-91fa6380ce74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078673542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2078673542
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2372426783
Short name T119
Test name
Test status
Simulation time 153398717 ps
CPU time 2.83 seconds
Started Mar 16 12:21:56 PM PDT 24
Finished Mar 16 12:21:59 PM PDT 24
Peak memory 221760 kb
Host smart-9da3dd94-e28a-4b32-94e3-7f7c333ba3ae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372426783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2372426783
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1522547812
Short name T464
Test name
Test status
Simulation time 98995631 ps
CPU time 4.1 seconds
Started Mar 16 12:21:40 PM PDT 24
Finished Mar 16 12:21:44 PM PDT 24
Peak memory 213724 kb
Host smart-0b0bb23f-358f-4d30-bdfc-70c998576230
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522547812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1522547812
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2506135072
Short name T500
Test name
Test status
Simulation time 122973628 ps
CPU time 2 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:21:53 PM PDT 24
Peak memory 215892 kb
Host smart-7f2ab051-7ef2-4558-95fb-9be552289d15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506135072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2506135072
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3291721982
Short name T520
Test name
Test status
Simulation time 38560503 ps
CPU time 0.68 seconds
Started Mar 16 12:22:19 PM PDT 24
Finished Mar 16 12:22:19 PM PDT 24
Peak memory 205004 kb
Host smart-f711a810-5fff-47ff-adf8-7d1dcf8af7a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291721982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3291721982
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1132550480
Short name T439
Test name
Test status
Simulation time 35309306 ps
CPU time 0.85 seconds
Started Mar 16 12:22:23 PM PDT 24
Finished Mar 16 12:22:25 PM PDT 24
Peak memory 204976 kb
Host smart-3d34a1ec-bda6-4f48-ad2d-485678d12639
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132550480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1132550480
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2064131479
Short name T572
Test name
Test status
Simulation time 19548273 ps
CPU time 0.87 seconds
Started Mar 16 12:22:23 PM PDT 24
Finished Mar 16 12:22:25 PM PDT 24
Peak memory 204976 kb
Host smart-72234f53-54b8-4c3a-b1dc-7c2db36dad9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064131479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2064131479
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2494471624
Short name T509
Test name
Test status
Simulation time 29579410 ps
CPU time 0.67 seconds
Started Mar 16 12:22:15 PM PDT 24
Finished Mar 16 12:22:16 PM PDT 24
Peak memory 205016 kb
Host smart-6863724d-de44-4d34-8008-388627a5ddbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494471624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2494471624
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3124042937
Short name T552
Test name
Test status
Simulation time 9312630 ps
CPU time 0.69 seconds
Started Mar 16 12:22:18 PM PDT 24
Finished Mar 16 12:22:19 PM PDT 24
Peak memory 205004 kb
Host smart-f59255c3-4e1b-425d-a100-41bbb7797fdd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124042937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3124042937
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1110785027
Short name T436
Test name
Test status
Simulation time 30413237 ps
CPU time 0.68 seconds
Started Mar 16 12:22:17 PM PDT 24
Finished Mar 16 12:22:18 PM PDT 24
Peak memory 205008 kb
Host smart-c8ede04d-ed97-4572-afce-bea30f98bb0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110785027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1110785027
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1064281310
Short name T484
Test name
Test status
Simulation time 55958764 ps
CPU time 0.87 seconds
Started Mar 16 12:22:26 PM PDT 24
Finished Mar 16 12:22:27 PM PDT 24
Peak memory 205104 kb
Host smart-627fb942-2e71-49b8-9195-fb98d726a05d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064281310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1064281310
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2081058417
Short name T496
Test name
Test status
Simulation time 49585111 ps
CPU time 0.9 seconds
Started Mar 16 12:22:33 PM PDT 24
Finished Mar 16 12:22:34 PM PDT 24
Peak memory 205072 kb
Host smart-cd9b2f94-9cb7-46ce-bd53-a664b60f0809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081058417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2081058417
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.605431621
Short name T522
Test name
Test status
Simulation time 23931539 ps
CPU time 0.68 seconds
Started Mar 16 12:22:24 PM PDT 24
Finished Mar 16 12:22:25 PM PDT 24
Peak memory 205080 kb
Host smart-e3e3a9e5-3833-4c8f-87ad-5f1bdc9e68a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605431621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.605431621
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3240351448
Short name T482
Test name
Test status
Simulation time 38320084 ps
CPU time 0.86 seconds
Started Mar 16 12:22:28 PM PDT 24
Finished Mar 16 12:22:29 PM PDT 24
Peak memory 205148 kb
Host smart-530f3d06-2446-46fd-b85c-46fb1a532674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240351448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3240351448
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.4161549677
Short name T498
Test name
Test status
Simulation time 533740370 ps
CPU time 7.07 seconds
Started Mar 16 12:21:49 PM PDT 24
Finished Mar 16 12:21:57 PM PDT 24
Peak memory 205080 kb
Host smart-000686fb-215a-409a-99c1-06c7d0179bf3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161549677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.4
161549677
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1117640927
Short name T517
Test name
Test status
Simulation time 40676114 ps
CPU time 1.16 seconds
Started Mar 16 12:21:56 PM PDT 24
Finished Mar 16 12:21:58 PM PDT 24
Peak memory 205104 kb
Host smart-22a97a83-5107-451a-8e3a-75516196da2c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117640927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
117640927
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.785177541
Short name T539
Test name
Test status
Simulation time 61966314 ps
CPU time 1.04 seconds
Started Mar 16 12:21:55 PM PDT 24
Finished Mar 16 12:21:56 PM PDT 24
Peak memory 205248 kb
Host smart-a54ec828-268d-47bc-99e0-2f88194da767
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785177541 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.785177541
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1247807372
Short name T532
Test name
Test status
Simulation time 35686438 ps
CPU time 1.42 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:21:53 PM PDT 24
Peak memory 205104 kb
Host smart-d2d71d5d-7409-43c0-984f-da83270c571d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247807372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1247807372
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.696987287
Short name T562
Test name
Test status
Simulation time 34147197 ps
CPU time 0.81 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:21:53 PM PDT 24
Peak memory 204964 kb
Host smart-d1cebbbd-d527-4f76-9ea0-00f9108486a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696987287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.696987287
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3380225647
Short name T545
Test name
Test status
Simulation time 493551307 ps
CPU time 4.5 seconds
Started Mar 16 12:22:05 PM PDT 24
Finished Mar 16 12:22:09 PM PDT 24
Peak memory 221900 kb
Host smart-96e84736-43b7-4016-9ecc-fa98ac340401
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380225647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3380225647
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2080364231
Short name T453
Test name
Test status
Simulation time 44835075 ps
CPU time 1.54 seconds
Started Mar 16 12:21:52 PM PDT 24
Finished Mar 16 12:21:54 PM PDT 24
Peak memory 214436 kb
Host smart-3b62e2a8-af10-4076-8817-0755312a7ebf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080364231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2080364231
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1856416047
Short name T560
Test name
Test status
Simulation time 32700339 ps
CPU time 0.75 seconds
Started Mar 16 12:22:27 PM PDT 24
Finished Mar 16 12:22:28 PM PDT 24
Peak memory 204992 kb
Host smart-15e543f6-3df3-4dc4-948f-ab820ca2c9c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856416047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1856416047
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.3474194642
Short name T173
Test name
Test status
Simulation time 14395874 ps
CPU time 0.72 seconds
Started Mar 16 12:22:41 PM PDT 24
Finished Mar 16 12:22:43 PM PDT 24
Peak memory 204932 kb
Host smart-6643aa3b-45cc-4ad3-abb1-c3f47499a9c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474194642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.3474194642
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.343116225
Short name T543
Test name
Test status
Simulation time 10505823 ps
CPU time 0.74 seconds
Started Mar 16 12:22:25 PM PDT 24
Finished Mar 16 12:22:26 PM PDT 24
Peak memory 205048 kb
Host smart-03afa6c4-03d6-4ac4-951e-72c2f00670e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343116225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.343116225
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1384540713
Short name T556
Test name
Test status
Simulation time 39067261 ps
CPU time 0.78 seconds
Started Mar 16 12:22:27 PM PDT 24
Finished Mar 16 12:22:28 PM PDT 24
Peak memory 205040 kb
Host smart-bffd9ec6-0c1d-4146-9142-d2a46154efd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384540713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1384540713
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3913285520
Short name T557
Test name
Test status
Simulation time 48062058 ps
CPU time 0.74 seconds
Started Mar 16 12:22:29 PM PDT 24
Finished Mar 16 12:22:29 PM PDT 24
Peak memory 204960 kb
Host smart-2a3f07f4-5a55-4988-ba4a-27065a4dd83d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913285520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3913285520
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.511106733
Short name T450
Test name
Test status
Simulation time 14921310 ps
CPU time 0.67 seconds
Started Mar 16 12:22:25 PM PDT 24
Finished Mar 16 12:22:26 PM PDT 24
Peak memory 204964 kb
Host smart-a0d160f1-f287-4f5e-8d0f-c0099f77ff88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511106733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.511106733
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3530168111
Short name T172
Test name
Test status
Simulation time 45985577 ps
CPU time 0.79 seconds
Started Mar 16 12:22:33 PM PDT 24
Finished Mar 16 12:22:34 PM PDT 24
Peak memory 204936 kb
Host smart-21374a85-719d-40a4-98ab-2a240ece636e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530168111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3530168111
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.881920670
Short name T459
Test name
Test status
Simulation time 27456443 ps
CPU time 0.67 seconds
Started Mar 16 12:22:31 PM PDT 24
Finished Mar 16 12:22:32 PM PDT 24
Peak memory 204916 kb
Host smart-704513d0-9ead-4eef-8078-7becea77d54f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881920670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.881920670
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2030306334
Short name T534
Test name
Test status
Simulation time 20276380 ps
CPU time 0.96 seconds
Started Mar 16 12:22:32 PM PDT 24
Finished Mar 16 12:22:34 PM PDT 24
Peak memory 205124 kb
Host smart-c45a4870-f1e4-4966-a1e4-772c01cdd902
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030306334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2030306334
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3651397295
Short name T527
Test name
Test status
Simulation time 56788813 ps
CPU time 0.74 seconds
Started Mar 16 12:22:36 PM PDT 24
Finished Mar 16 12:22:37 PM PDT 24
Peak memory 205072 kb
Host smart-6c782e06-f99c-4152-86aa-f8fe34489b00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651397295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3651397295
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1710042651
Short name T477
Test name
Test status
Simulation time 39558728 ps
CPU time 1.35 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:21:53 PM PDT 24
Peak memory 205192 kb
Host smart-e08852f5-5353-4615-b0c7-7f1a73e035e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710042651 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1710042651
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3311982195
Short name T455
Test name
Test status
Simulation time 46735993 ps
CPU time 1.05 seconds
Started Mar 16 12:21:47 PM PDT 24
Finished Mar 16 12:21:49 PM PDT 24
Peak memory 205064 kb
Host smart-1ebc4ff0-2622-4901-b031-9aec7348adb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311982195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3311982195
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.756834498
Short name T491
Test name
Test status
Simulation time 9006947 ps
CPU time 0.79 seconds
Started Mar 16 12:21:53 PM PDT 24
Finished Mar 16 12:21:54 PM PDT 24
Peak memory 205024 kb
Host smart-9c69592e-4a57-4ce2-bc17-d4cd601bc41f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756834498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.756834498
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3151944938
Short name T493
Test name
Test status
Simulation time 297481899 ps
CPU time 3.03 seconds
Started Mar 16 12:21:50 PM PDT 24
Finished Mar 16 12:21:54 PM PDT 24
Peak memory 213700 kb
Host smart-4de397f0-498d-451a-b4a0-fbc686caa474
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151944938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3151944938
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.967893184
Short name T554
Test name
Test status
Simulation time 484940093 ps
CPU time 4.4 seconds
Started Mar 16 12:22:02 PM PDT 24
Finished Mar 16 12:22:06 PM PDT 24
Peak memory 213472 kb
Host smart-d2cc8853-5096-43a2-9f8d-b97e0ce10130
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967893184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.967893184
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.4138231089
Short name T165
Test name
Test status
Simulation time 34579540 ps
CPU time 0.99 seconds
Started Mar 16 12:22:00 PM PDT 24
Finished Mar 16 12:22:01 PM PDT 24
Peak memory 205020 kb
Host smart-3f865834-341e-409a-b864-f6353a0cc405
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138231089 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.4138231089
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2042520068
Short name T576
Test name
Test status
Simulation time 43762005 ps
CPU time 1 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:21:52 PM PDT 24
Peak memory 205016 kb
Host smart-4f8bcc0f-0d32-4c07-9bb1-eb37176e9f97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042520068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2042520068
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.86635709
Short name T523
Test name
Test status
Simulation time 42881465 ps
CPU time 0.8 seconds
Started Mar 16 12:21:52 PM PDT 24
Finished Mar 16 12:21:53 PM PDT 24
Peak memory 205044 kb
Host smart-ac4f1689-4178-4996-b300-310dff44fe1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86635709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.86635709
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.541025968
Short name T457
Test name
Test status
Simulation time 162329399 ps
CPU time 2.38 seconds
Started Mar 16 12:21:50 PM PDT 24
Finished Mar 16 12:21:53 PM PDT 24
Peak memory 205184 kb
Host smart-173cf5cc-91d5-40a3-894d-9583b3bb2b65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541025968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.541025968
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1517639707
Short name T117
Test name
Test status
Simulation time 199642029 ps
CPU time 3.41 seconds
Started Mar 16 12:21:58 PM PDT 24
Finished Mar 16 12:22:01 PM PDT 24
Peak memory 213508 kb
Host smart-3303f80d-245d-459f-bae0-17f97e2a581b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517639707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1517639707
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.566430556
Short name T549
Test name
Test status
Simulation time 455004145 ps
CPU time 5.63 seconds
Started Mar 16 12:21:47 PM PDT 24
Finished Mar 16 12:21:53 PM PDT 24
Peak memory 213536 kb
Host smart-ee3f7833-23a5-42de-82c6-59f41f36b81d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566430556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.566430556
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1420953883
Short name T521
Test name
Test status
Simulation time 70705388 ps
CPU time 1.84 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:21:54 PM PDT 24
Peak memory 213420 kb
Host smart-c7464cf2-3104-4976-8d1a-a70ac8cc978e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420953883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1420953883
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2526530986
Short name T454
Test name
Test status
Simulation time 88895581 ps
CPU time 1.82 seconds
Started Mar 16 12:22:00 PM PDT 24
Finished Mar 16 12:22:02 PM PDT 24
Peak memory 213448 kb
Host smart-c31deb5e-4b84-4ab5-b133-add517216a62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526530986 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2526530986
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.99475446
Short name T473
Test name
Test status
Simulation time 87900365 ps
CPU time 1.12 seconds
Started Mar 16 12:21:48 PM PDT 24
Finished Mar 16 12:21:50 PM PDT 24
Peak memory 205044 kb
Host smart-cb35fffe-efbd-4bef-bd1f-6e632ff1bb2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99475446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.99475446
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.950761953
Short name T467
Test name
Test status
Simulation time 12794902 ps
CPU time 0.69 seconds
Started Mar 16 12:21:44 PM PDT 24
Finished Mar 16 12:21:45 PM PDT 24
Peak memory 205084 kb
Host smart-b0bf39d9-ca0b-4f82-850f-9d85d63d4722
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950761953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.950761953
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.271010318
Short name T132
Test name
Test status
Simulation time 432584575 ps
CPU time 4.23 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:21:56 PM PDT 24
Peak memory 205140 kb
Host smart-ac0538e0-45c5-4a15-adf5-8a9eef10f1a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271010318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.271010318
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1809411446
Short name T448
Test name
Test status
Simulation time 416052169 ps
CPU time 4.3 seconds
Started Mar 16 12:21:52 PM PDT 24
Finished Mar 16 12:21:56 PM PDT 24
Peak memory 213580 kb
Host smart-57321b15-e4c1-41fe-801a-10f9349e20a8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809411446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1809411446
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2490543767
Short name T479
Test name
Test status
Simulation time 69862062 ps
CPU time 2.22 seconds
Started Mar 16 12:21:58 PM PDT 24
Finished Mar 16 12:22:01 PM PDT 24
Peak memory 213036 kb
Host smart-cdf32a57-d0cf-4d84-bf2d-0e8fda67272e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490543767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2490543767
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.61839051
Short name T155
Test name
Test status
Simulation time 536423675 ps
CPU time 8.33 seconds
Started Mar 16 12:21:49 PM PDT 24
Finished Mar 16 12:21:58 PM PDT 24
Peak memory 208900 kb
Host smart-b5219393-e006-4ba1-ae19-272c19c34572
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61839051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.61839051
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3434322582
Short name T166
Test name
Test status
Simulation time 89712276 ps
CPU time 1.15 seconds
Started Mar 16 12:21:52 PM PDT 24
Finished Mar 16 12:21:53 PM PDT 24
Peak memory 205192 kb
Host smart-4768b269-c51f-453e-9fd2-e2521cc5ac9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434322582 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3434322582
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1820837516
Short name T547
Test name
Test status
Simulation time 31639907 ps
CPU time 0.82 seconds
Started Mar 16 12:21:54 PM PDT 24
Finished Mar 16 12:21:55 PM PDT 24
Peak memory 205132 kb
Host smart-0aa937ca-04b0-484e-902e-b1af7d89655b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820837516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1820837516
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2389721744
Short name T567
Test name
Test status
Simulation time 60681548 ps
CPU time 2.21 seconds
Started Mar 16 12:21:54 PM PDT 24
Finished Mar 16 12:21:56 PM PDT 24
Peak memory 205156 kb
Host smart-c69e734c-a01b-4156-a455-fdaf84adafd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389721744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2389721744
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.17074410
Short name T481
Test name
Test status
Simulation time 790055819 ps
CPU time 3.41 seconds
Started Mar 16 12:21:53 PM PDT 24
Finished Mar 16 12:21:57 PM PDT 24
Peak memory 213592 kb
Host smart-5794a0dc-540f-493e-83c1-c926e11a334e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17074410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_
reg_errors.17074410
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.39018905
Short name T441
Test name
Test status
Simulation time 218325216 ps
CPU time 5.27 seconds
Started Mar 16 12:21:51 PM PDT 24
Finished Mar 16 12:21:57 PM PDT 24
Peak memory 213632 kb
Host smart-d51ec1ee-fae6-4cdc-a909-1ac63f4a8be5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39018905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.ke
ymgr_shadow_reg_errors_with_csr_rw.39018905
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3907447400
Short name T515
Test name
Test status
Simulation time 66727576 ps
CPU time 2.57 seconds
Started Mar 16 12:21:56 PM PDT 24
Finished Mar 16 12:21:59 PM PDT 24
Peak memory 213364 kb
Host smart-e979e1e6-c5c1-444e-ad3c-5dab77ca71be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907447400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3907447400
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1593702524
Short name T158
Test name
Test status
Simulation time 78507981 ps
CPU time 3.6 seconds
Started Mar 16 12:22:01 PM PDT 24
Finished Mar 16 12:22:05 PM PDT 24
Peak memory 213476 kb
Host smart-0edf9de9-cd03-4d15-9d98-b0f10b4f6e66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593702524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1593702524
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.306749912
Short name T169
Test name
Test status
Simulation time 32716256 ps
CPU time 1.2 seconds
Started Mar 16 12:22:01 PM PDT 24
Finished Mar 16 12:22:02 PM PDT 24
Peak memory 205228 kb
Host smart-d976c566-d1c7-40a7-a67c-f7e3568382ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306749912 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.306749912
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1990101744
Short name T451
Test name
Test status
Simulation time 38640795 ps
CPU time 0.68 seconds
Started Mar 16 12:21:58 PM PDT 24
Finished Mar 16 12:21:59 PM PDT 24
Peak memory 204956 kb
Host smart-2fbd7b9a-55c5-40f8-90e3-cd12d8efc79e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990101744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1990101744
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3363074766
Short name T471
Test name
Test status
Simulation time 87756536 ps
CPU time 1.53 seconds
Started Mar 16 12:21:53 PM PDT 24
Finished Mar 16 12:21:55 PM PDT 24
Peak memory 205128 kb
Host smart-32be5c0b-5354-4011-a562-52ad13dc26f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363074766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3363074766
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.156222065
Short name T492
Test name
Test status
Simulation time 425393698 ps
CPU time 3.82 seconds
Started Mar 16 12:21:56 PM PDT 24
Finished Mar 16 12:22:00 PM PDT 24
Peak memory 213672 kb
Host smart-c3cbd7f9-6cac-4ddf-94f2-4e139a06f424
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156222065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.156222065
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3608233811
Short name T470
Test name
Test status
Simulation time 215706696 ps
CPU time 2.91 seconds
Started Mar 16 12:22:00 PM PDT 24
Finished Mar 16 12:22:03 PM PDT 24
Peak memory 213240 kb
Host smart-027a3c51-6af3-4635-99f9-8a32499b568b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608233811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3608233811
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1725752575
Short name T703
Test name
Test status
Simulation time 24305191 ps
CPU time 0.76 seconds
Started Mar 16 12:23:36 PM PDT 24
Finished Mar 16 12:23:37 PM PDT 24
Peak memory 205780 kb
Host smart-1ac0d057-0686-45e9-8fb0-a53f51d881ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725752575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1725752575
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3096410928
Short name T426
Test name
Test status
Simulation time 293443879 ps
CPU time 14.9 seconds
Started Mar 16 12:23:31 PM PDT 24
Finished Mar 16 12:23:46 PM PDT 24
Peak memory 214248 kb
Host smart-44a26096-321d-4974-866c-87184cef0746
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3096410928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3096410928
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.485496399
Short name T230
Test name
Test status
Simulation time 159305481 ps
CPU time 3.69 seconds
Started Mar 16 12:23:31 PM PDT 24
Finished Mar 16 12:23:35 PM PDT 24
Peak memory 206996 kb
Host smart-73e2e905-fae2-432a-abc2-efd7dfd9ab87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485496399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.485496399
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1319439034
Short name T1018
Test name
Test status
Simulation time 5264298436 ps
CPU time 9.08 seconds
Started Mar 16 12:23:21 PM PDT 24
Finished Mar 16 12:23:30 PM PDT 24
Peak memory 209032 kb
Host smart-bc440856-2839-4fff-8896-033d574a3908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319439034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1319439034
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3593745275
Short name T364
Test name
Test status
Simulation time 2934451218 ps
CPU time 10.42 seconds
Started Mar 16 12:23:21 PM PDT 24
Finished Mar 16 12:23:31 PM PDT 24
Peak memory 214204 kb
Host smart-12ed5c93-9453-4779-be17-9a7b26c47404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593745275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3593745275
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.4123571521
Short name T50
Test name
Test status
Simulation time 41753248 ps
CPU time 2.56 seconds
Started Mar 16 12:23:31 PM PDT 24
Finished Mar 16 12:23:34 PM PDT 24
Peak memory 222388 kb
Host smart-f143546e-f92e-4851-ab5e-4e5e06245515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123571521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.4123571521
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3703447698
Short name T354
Test name
Test status
Simulation time 161362092 ps
CPU time 5.36 seconds
Started Mar 16 12:23:26 PM PDT 24
Finished Mar 16 12:23:31 PM PDT 24
Peak memory 214084 kb
Host smart-ad8c8fa8-fd17-4b18-8e3d-5502af0eb82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703447698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3703447698
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2673743781
Short name T632
Test name
Test status
Simulation time 5796397309 ps
CPU time 53.52 seconds
Started Mar 16 12:23:26 PM PDT 24
Finished Mar 16 12:24:19 PM PDT 24
Peak memory 209000 kb
Host smart-a0e8d90d-649b-4e32-8d47-146bd7f2989a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673743781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2673743781
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.978461228
Short name T283
Test name
Test status
Simulation time 521662874 ps
CPU time 4.51 seconds
Started Mar 16 12:23:23 PM PDT 24
Finished Mar 16 12:23:27 PM PDT 24
Peak memory 206796 kb
Host smart-40cd07e6-c1a6-4886-ba9e-d315ef25377f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978461228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.978461228
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.355062002
Short name T334
Test name
Test status
Simulation time 31586493 ps
CPU time 2.42 seconds
Started Mar 16 12:23:27 PM PDT 24
Finished Mar 16 12:23:29 PM PDT 24
Peak memory 206728 kb
Host smart-4f3666e0-9113-43d5-9ab0-e390b1b2579b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355062002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.355062002
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3802762177
Short name T301
Test name
Test status
Simulation time 157010175 ps
CPU time 3.63 seconds
Started Mar 16 12:23:31 PM PDT 24
Finished Mar 16 12:23:34 PM PDT 24
Peak memory 208588 kb
Host smart-b20c9269-c339-4f32-9c14-ff14c65b5517
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802762177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3802762177
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.4059840979
Short name T843
Test name
Test status
Simulation time 2735705848 ps
CPU time 22.83 seconds
Started Mar 16 12:23:20 PM PDT 24
Finished Mar 16 12:23:43 PM PDT 24
Peak memory 208888 kb
Host smart-1b6a5502-719f-4f92-bc93-be98e9ee0435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059840979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.4059840979
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.804175509
Short name T897
Test name
Test status
Simulation time 56618724 ps
CPU time 2.57 seconds
Started Mar 16 12:23:26 PM PDT 24
Finished Mar 16 12:23:28 PM PDT 24
Peak memory 206848 kb
Host smart-de7ac8bb-aa24-487f-ba34-c8e5dc6b1db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804175509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.804175509
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1472934585
Short name T67
Test name
Test status
Simulation time 742252601 ps
CPU time 3.48 seconds
Started Mar 16 12:23:25 PM PDT 24
Finished Mar 16 12:23:29 PM PDT 24
Peak memory 207260 kb
Host smart-f2a2a4bb-64d2-48eb-b8ec-2e373d99ae17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472934585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1472934585
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3845512002
Short name T205
Test name
Test status
Simulation time 65106187 ps
CPU time 4.77 seconds
Started Mar 16 12:23:31 PM PDT 24
Finished Mar 16 12:23:35 PM PDT 24
Peak memory 222628 kb
Host smart-dfe25eca-196c-4492-ac69-7ab2afaed107
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845512002 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3845512002
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1454454653
Short name T841
Test name
Test status
Simulation time 267121399 ps
CPU time 7.11 seconds
Started Mar 16 12:23:23 PM PDT 24
Finished Mar 16 12:23:30 PM PDT 24
Peak memory 208504 kb
Host smart-dcd6e7c8-bb9f-4cc7-adc0-c439f5f59101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454454653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1454454653
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1464919755
Short name T391
Test name
Test status
Simulation time 95776768 ps
CPU time 3.32 seconds
Started Mar 16 12:23:28 PM PDT 24
Finished Mar 16 12:23:31 PM PDT 24
Peak memory 210320 kb
Host smart-802e018a-c80d-42e7-87b2-0bfff9e6ba23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464919755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1464919755
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1091950997
Short name T963
Test name
Test status
Simulation time 40940603 ps
CPU time 0.68 seconds
Started Mar 16 12:23:35 PM PDT 24
Finished Mar 16 12:23:36 PM PDT 24
Peak memory 205660 kb
Host smart-942c0140-4ac6-41c1-939c-8ee7c2ee85d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091950997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1091950997
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.576858853
Short name T424
Test name
Test status
Simulation time 458050217 ps
CPU time 3.48 seconds
Started Mar 16 12:23:38 PM PDT 24
Finished Mar 16 12:23:42 PM PDT 24
Peak memory 215304 kb
Host smart-d6143bc2-e1cb-4806-9a4f-8936f3f968c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=576858853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.576858853
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3821404868
Short name T955
Test name
Test status
Simulation time 171271492 ps
CPU time 2.11 seconds
Started Mar 16 12:23:32 PM PDT 24
Finished Mar 16 12:23:35 PM PDT 24
Peak memory 206972 kb
Host smart-6f048700-d7a8-40f5-b8da-472a774ed542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821404868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3821404868
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.586079116
Short name T635
Test name
Test status
Simulation time 1152642427 ps
CPU time 8.72 seconds
Started Mar 16 12:23:36 PM PDT 24
Finished Mar 16 12:23:45 PM PDT 24
Peak memory 214204 kb
Host smart-ccc32695-0ff3-4485-a16a-8c8b9d6999f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586079116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.586079116
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3276508986
Short name T1068
Test name
Test status
Simulation time 655522074 ps
CPU time 8.1 seconds
Started Mar 16 12:23:38 PM PDT 24
Finished Mar 16 12:23:46 PM PDT 24
Peak memory 222172 kb
Host smart-441bc791-d99e-4725-bd16-b1b913e7786a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276508986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3276508986
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1600863299
Short name T914
Test name
Test status
Simulation time 137696848 ps
CPU time 4.38 seconds
Started Mar 16 12:23:41 PM PDT 24
Finished Mar 16 12:23:46 PM PDT 24
Peak memory 219600 kb
Host smart-e8cde363-3e51-40fb-aa9f-288fa9a3dfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600863299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1600863299
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3353418186
Short name T242
Test name
Test status
Simulation time 1183410888 ps
CPU time 13.51 seconds
Started Mar 16 12:23:22 PM PDT 24
Finished Mar 16 12:23:35 PM PDT 24
Peak memory 218016 kb
Host smart-fff81464-4961-4c9c-91bb-40e305ac8ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353418186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3353418186
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2867969525
Short name T746
Test name
Test status
Simulation time 56278833 ps
CPU time 2.66 seconds
Started Mar 16 12:23:36 PM PDT 24
Finished Mar 16 12:23:39 PM PDT 24
Peak memory 207112 kb
Host smart-e2f57b36-ad72-4a9b-9044-cb83069e6d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867969525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2867969525
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.971188643
Short name T619
Test name
Test status
Simulation time 691848305 ps
CPU time 8.31 seconds
Started Mar 16 12:23:20 PM PDT 24
Finished Mar 16 12:23:28 PM PDT 24
Peak memory 208840 kb
Host smart-6019d129-9055-45c4-ac82-832ce577c10e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971188643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.971188643
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.55288527
Short name T1000
Test name
Test status
Simulation time 67321408 ps
CPU time 3.35 seconds
Started Mar 16 12:23:34 PM PDT 24
Finished Mar 16 12:23:37 PM PDT 24
Peak memory 206876 kb
Host smart-eff8ac5a-ae9b-4df5-8613-06ddc4743eb8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55288527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.55288527
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.359140954
Short name T774
Test name
Test status
Simulation time 46683687 ps
CPU time 2.62 seconds
Started Mar 16 12:23:26 PM PDT 24
Finished Mar 16 12:23:28 PM PDT 24
Peak memory 208360 kb
Host smart-65ac5c53-03dd-44c9-b9bb-0f144597d7c4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359140954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.359140954
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.3793173728
Short name T677
Test name
Test status
Simulation time 8032484817 ps
CPU time 19.07 seconds
Started Mar 16 12:23:32 PM PDT 24
Finished Mar 16 12:23:51 PM PDT 24
Peak memory 219000 kb
Host smart-0fedaa8c-c102-42ea-b4a2-b1082e09f0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793173728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.3793173728
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2196352951
Short name T624
Test name
Test status
Simulation time 52816445 ps
CPU time 2.44 seconds
Started Mar 16 12:23:22 PM PDT 24
Finished Mar 16 12:23:25 PM PDT 24
Peak memory 206660 kb
Host smart-351fe7ba-a058-4105-92ec-44c2412716ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196352951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2196352951
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3570677931
Short name T907
Test name
Test status
Simulation time 285415978 ps
CPU time 4.49 seconds
Started Mar 16 12:23:38 PM PDT 24
Finished Mar 16 12:23:43 PM PDT 24
Peak memory 222600 kb
Host smart-347d194d-264c-4dcb-8c26-09abd95c8242
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570677931 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3570677931
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1699353826
Short name T931
Test name
Test status
Simulation time 158643038 ps
CPU time 5.15 seconds
Started Mar 16 12:23:35 PM PDT 24
Finished Mar 16 12:23:40 PM PDT 24
Peak memory 208944 kb
Host smart-0c0b9bc5-e426-4b09-9e6a-7ed49cc1fc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699353826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1699353826
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.537578991
Short name T937
Test name
Test status
Simulation time 38956096 ps
CPU time 2.53 seconds
Started Mar 16 12:23:42 PM PDT 24
Finished Mar 16 12:23:44 PM PDT 24
Peak memory 210184 kb
Host smart-6d50321d-96ef-4b0c-b13d-1fedb469a64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537578991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.537578991
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3814492978
Short name T79
Test name
Test status
Simulation time 55558087 ps
CPU time 3.69 seconds
Started Mar 16 12:23:56 PM PDT 24
Finished Mar 16 12:24:02 PM PDT 24
Peak memory 215416 kb
Host smart-29567cad-641c-4853-a34c-ac71565f03cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3814492978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3814492978
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.620788689
Short name T34
Test name
Test status
Simulation time 3419096278 ps
CPU time 7.45 seconds
Started Mar 16 12:23:59 PM PDT 24
Finished Mar 16 12:24:07 PM PDT 24
Peak memory 221896 kb
Host smart-b81dcb39-0c45-43f9-b36f-9d89f4427ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620788689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.620788689
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.722253644
Short name T636
Test name
Test status
Simulation time 48983977 ps
CPU time 2.65 seconds
Started Mar 16 12:23:52 PM PDT 24
Finished Mar 16 12:23:57 PM PDT 24
Peak memory 207360 kb
Host smart-8d805e55-0dec-418e-a10e-69135ad33b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722253644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.722253644
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1322824809
Short name T338
Test name
Test status
Simulation time 227936849 ps
CPU time 6.69 seconds
Started Mar 16 12:23:53 PM PDT 24
Finished Mar 16 12:24:02 PM PDT 24
Peak memory 208280 kb
Host smart-a663c4dd-9518-4d04-b504-e2324e88e4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322824809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1322824809
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2972476668
Short name T1032
Test name
Test status
Simulation time 213696703 ps
CPU time 3.56 seconds
Started Mar 16 12:26:20 PM PDT 24
Finished Mar 16 12:26:24 PM PDT 24
Peak memory 209688 kb
Host smart-6c7c1de5-ee34-4bea-b347-65dbbba8c320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972476668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2972476668
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.4057333118
Short name T1012
Test name
Test status
Simulation time 4144151950 ps
CPU time 7.5 seconds
Started Mar 16 12:23:56 PM PDT 24
Finished Mar 16 12:24:05 PM PDT 24
Peak memory 209180 kb
Host smart-dd1846d3-8bae-429b-bf9d-a922e12c48ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057333118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.4057333118
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.999579635
Short name T402
Test name
Test status
Simulation time 470199391 ps
CPU time 5.62 seconds
Started Mar 16 12:23:53 PM PDT 24
Finished Mar 16 12:24:00 PM PDT 24
Peak memory 208616 kb
Host smart-1b5bf35d-5e88-47d9-a1d6-b635a8483a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999579635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.999579635
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.4090850076
Short name T978
Test name
Test status
Simulation time 80536643 ps
CPU time 2.39 seconds
Started Mar 16 12:23:56 PM PDT 24
Finished Mar 16 12:24:00 PM PDT 24
Peak memory 206596 kb
Host smart-2c3f0c5c-5a38-41af-8c32-55ed428319a1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090850076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.4090850076
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1839485887
Short name T877
Test name
Test status
Simulation time 66115075 ps
CPU time 3.24 seconds
Started Mar 16 12:23:51 PM PDT 24
Finished Mar 16 12:23:57 PM PDT 24
Peak memory 208176 kb
Host smart-5f2e811c-bd20-4573-bf21-647dc6179476
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839485887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1839485887
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3124214268
Short name T621
Test name
Test status
Simulation time 225950902 ps
CPU time 5.86 seconds
Started Mar 16 12:24:04 PM PDT 24
Finished Mar 16 12:24:10 PM PDT 24
Peak memory 208772 kb
Host smart-fcecbe3f-bb96-40a0-9e3d-dfa7e083a7df
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124214268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3124214268
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1275071728
Short name T1065
Test name
Test status
Simulation time 72639139 ps
CPU time 3.13 seconds
Started Mar 16 12:23:49 PM PDT 24
Finished Mar 16 12:23:53 PM PDT 24
Peak memory 210140 kb
Host smart-8c4acfa4-fedb-4817-a71a-b7b0083ed976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275071728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1275071728
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3763178129
Short name T435
Test name
Test status
Simulation time 244995446 ps
CPU time 6.16 seconds
Started Mar 16 12:23:45 PM PDT 24
Finished Mar 16 12:23:51 PM PDT 24
Peak memory 207876 kb
Host smart-510fd965-fee1-4883-9011-60ba32ee1972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763178129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3763178129
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.90569932
Short name T874
Test name
Test status
Simulation time 9626029514 ps
CPU time 156.76 seconds
Started Mar 16 12:23:51 PM PDT 24
Finished Mar 16 12:26:28 PM PDT 24
Peak memory 222092 kb
Host smart-ae108e87-b261-48a1-ad4f-0602ea98a617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90569932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.90569932
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.537088451
Short name T762
Test name
Test status
Simulation time 325662382 ps
CPU time 4.2 seconds
Started Mar 16 12:24:03 PM PDT 24
Finished Mar 16 12:24:07 PM PDT 24
Peak memory 214480 kb
Host smart-4ec376cf-bbaf-4215-bc59-9a027a81f96b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537088451 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.537088451
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3683221314
Short name T358
Test name
Test status
Simulation time 611154735 ps
CPU time 8.31 seconds
Started Mar 16 12:23:54 PM PDT 24
Finished Mar 16 12:24:04 PM PDT 24
Peak memory 214164 kb
Host smart-f5c1eaaf-c2d8-4193-88a1-f901d2ecea25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683221314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3683221314
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1262759333
Short name T77
Test name
Test status
Simulation time 33144062 ps
CPU time 0.77 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:02 PM PDT 24
Peak memory 205760 kb
Host smart-9a8b7f99-58bb-49ee-ba02-ec0770624b54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262759333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1262759333
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.910569444
Short name T378
Test name
Test status
Simulation time 250541025 ps
CPU time 2.36 seconds
Started Mar 16 12:23:57 PM PDT 24
Finished Mar 16 12:24:00 PM PDT 24
Peak memory 214216 kb
Host smart-7f551366-95ec-4e0c-b1eb-d9e657d1304c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=910569444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.910569444
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.4078272122
Short name T693
Test name
Test status
Simulation time 120639296 ps
CPU time 1.78 seconds
Started Mar 16 12:23:54 PM PDT 24
Finished Mar 16 12:23:57 PM PDT 24
Peak memory 208320 kb
Host smart-58a149e9-fbb1-4508-92ca-d64cbaf4b28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078272122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.4078272122
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3369565104
Short name T85
Test name
Test status
Simulation time 540604787 ps
CPU time 3.71 seconds
Started Mar 16 12:23:53 PM PDT 24
Finished Mar 16 12:23:59 PM PDT 24
Peak memory 208772 kb
Host smart-e584f730-2aa7-4ac3-849d-391d12c0f517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369565104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3369565104
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3514067479
Short name T611
Test name
Test status
Simulation time 101167397 ps
CPU time 2.76 seconds
Started Mar 16 12:23:52 PM PDT 24
Finished Mar 16 12:23:58 PM PDT 24
Peak memory 215388 kb
Host smart-5278f814-83f3-4a88-9ca7-43d1be822495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514067479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3514067479
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2177857608
Short name T1035
Test name
Test status
Simulation time 116456326 ps
CPU time 3.67 seconds
Started Mar 16 12:23:56 PM PDT 24
Finished Mar 16 12:24:01 PM PDT 24
Peak memory 208824 kb
Host smart-e346e7d1-849f-48bc-9e3b-00a83d3fb07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177857608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2177857608
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2749260545
Short name T947
Test name
Test status
Simulation time 937518101 ps
CPU time 4.62 seconds
Started Mar 16 12:23:52 PM PDT 24
Finished Mar 16 12:23:59 PM PDT 24
Peak memory 208512 kb
Host smart-8b4aab84-847a-4096-ad33-7455fe8cc3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749260545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2749260545
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1197354292
Short name T738
Test name
Test status
Simulation time 235361680 ps
CPU time 7.93 seconds
Started Mar 16 12:23:52 PM PDT 24
Finished Mar 16 12:24:02 PM PDT 24
Peak memory 207652 kb
Host smart-fcf43bce-b031-458f-a889-f7b11d56ca67
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197354292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1197354292
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1670712964
Short name T655
Test name
Test status
Simulation time 309878738 ps
CPU time 3.25 seconds
Started Mar 16 12:23:53 PM PDT 24
Finished Mar 16 12:23:59 PM PDT 24
Peak memory 208556 kb
Host smart-6c1cdfaa-1214-428a-84c2-f9e17f2ba46d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670712964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1670712964
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2658901744
Short name T911
Test name
Test status
Simulation time 87993959 ps
CPU time 3.67 seconds
Started Mar 16 12:23:52 PM PDT 24
Finished Mar 16 12:23:58 PM PDT 24
Peak memory 207824 kb
Host smart-26fab809-fda4-4915-bf3d-2d16c2000bc7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658901744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2658901744
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.4010358228
Short name T373
Test name
Test status
Simulation time 69067647 ps
CPU time 3.44 seconds
Started Mar 16 12:24:02 PM PDT 24
Finished Mar 16 12:24:06 PM PDT 24
Peak memory 218420 kb
Host smart-c87f3277-63f4-4ac8-ad34-567c4fbf8fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010358228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.4010358228
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.324728308
Short name T617
Test name
Test status
Simulation time 75770540 ps
CPU time 2.81 seconds
Started Mar 16 12:23:50 PM PDT 24
Finished Mar 16 12:23:53 PM PDT 24
Peak memory 208512 kb
Host smart-fd416e02-28b2-4842-9d92-04a7aa0bebab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324728308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.324728308
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3721977914
Short name T661
Test name
Test status
Simulation time 205977693 ps
CPU time 4.04 seconds
Started Mar 16 12:23:59 PM PDT 24
Finished Mar 16 12:24:04 PM PDT 24
Peak memory 214364 kb
Host smart-7db9b488-fb52-4f34-9572-33e844d2ede3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721977914 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3721977914
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1510274315
Short name T779
Test name
Test status
Simulation time 36480270 ps
CPU time 2.33 seconds
Started Mar 16 12:23:50 PM PDT 24
Finished Mar 16 12:23:53 PM PDT 24
Peak memory 208180 kb
Host smart-688f78d2-3a63-489a-9758-f34f39ad596a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510274315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1510274315
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2937861243
Short name T1054
Test name
Test status
Simulation time 86140788 ps
CPU time 2.22 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:03 PM PDT 24
Peak memory 210152 kb
Host smart-074d642c-1615-429b-8330-532bc28cb06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937861243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2937861243
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1951029150
Short name T834
Test name
Test status
Simulation time 23121991 ps
CPU time 0.74 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:02 PM PDT 24
Peak memory 205708 kb
Host smart-993526a1-196a-450f-aed3-3d6536da2688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951029150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1951029150
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.813572884
Short name T407
Test name
Test status
Simulation time 222236992 ps
CPU time 11.06 seconds
Started Mar 16 12:23:58 PM PDT 24
Finished Mar 16 12:24:10 PM PDT 24
Peak memory 214252 kb
Host smart-a9747f5a-a720-42dc-a615-b35861a033a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=813572884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.813572884
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2392021389
Short name T313
Test name
Test status
Simulation time 121705287 ps
CPU time 2.01 seconds
Started Mar 16 12:23:59 PM PDT 24
Finished Mar 16 12:24:02 PM PDT 24
Peak memory 207360 kb
Host smart-cb52dcc6-1202-42fa-b8e9-7a0469001b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392021389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2392021389
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3756537056
Short name T384
Test name
Test status
Simulation time 6484604394 ps
CPU time 58.81 seconds
Started Mar 16 12:23:57 PM PDT 24
Finished Mar 16 12:24:58 PM PDT 24
Peak memory 214256 kb
Host smart-b722fb47-bd38-4be9-b6e6-b41d3d51fc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756537056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3756537056
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2974654517
Short name T295
Test name
Test status
Simulation time 825043867 ps
CPU time 6.12 seconds
Started Mar 16 12:24:04 PM PDT 24
Finished Mar 16 12:24:10 PM PDT 24
Peak memory 214216 kb
Host smart-c0517a91-3189-41f1-8eaf-07820450646f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974654517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2974654517
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.4237838310
Short name T1022
Test name
Test status
Simulation time 143037269 ps
CPU time 2.38 seconds
Started Mar 16 12:23:58 PM PDT 24
Finished Mar 16 12:24:01 PM PDT 24
Peak memory 209516 kb
Host smart-0889e83d-84eb-4ea5-aa69-d93ef5b556b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237838310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.4237838310
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1730049703
Short name T372
Test name
Test status
Simulation time 392257091 ps
CPU time 6.56 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:07 PM PDT 24
Peak memory 209536 kb
Host smart-0b52a6e3-0e94-4d0b-b5f0-ce6c3523aca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730049703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1730049703
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3884682399
Short name T588
Test name
Test status
Simulation time 5083177453 ps
CPU time 9.13 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:11 PM PDT 24
Peak memory 207924 kb
Host smart-db04626a-4bfb-4ccf-ac11-d440400a13b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884682399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3884682399
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.325696036
Short name T325
Test name
Test status
Simulation time 306534804 ps
CPU time 3.84 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:05 PM PDT 24
Peak memory 208444 kb
Host smart-74bf07c7-277d-4077-81c0-696e0c42a102
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325696036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.325696036
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.4149406539
Short name T1008
Test name
Test status
Simulation time 462652171 ps
CPU time 9.44 seconds
Started Mar 16 12:24:03 PM PDT 24
Finished Mar 16 12:24:12 PM PDT 24
Peak memory 207884 kb
Host smart-48f5376b-4959-49d8-97a2-5fcc4572faec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149406539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.4149406539
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3184512058
Short name T300
Test name
Test status
Simulation time 56266879 ps
CPU time 2.74 seconds
Started Mar 16 12:23:59 PM PDT 24
Finished Mar 16 12:24:03 PM PDT 24
Peak memory 208664 kb
Host smart-8c997f1b-1d81-4c50-88bd-905c36b5b09a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184512058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3184512058
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.422821932
Short name T330
Test name
Test status
Simulation time 8877435210 ps
CPU time 12.66 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:13 PM PDT 24
Peak memory 214332 kb
Host smart-b8fdce21-ab46-4145-a685-31c5970f3a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422821932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.422821932
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1781653559
Short name T633
Test name
Test status
Simulation time 5412851755 ps
CPU time 27.92 seconds
Started Mar 16 12:24:00 PM PDT 24
Finished Mar 16 12:24:28 PM PDT 24
Peak memory 207552 kb
Host smart-705e2ace-d4ae-4f24-9206-0a0e833c98a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781653559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1781653559
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1558798268
Short name T415
Test name
Test status
Simulation time 4177527502 ps
CPU time 25.81 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:27 PM PDT 24
Peak memory 209336 kb
Host smart-afeb7b2f-17bd-4efd-bf5b-9c826985a976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558798268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1558798268
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3483569942
Short name T1061
Test name
Test status
Simulation time 57608916 ps
CPU time 2.48 seconds
Started Mar 16 12:24:03 PM PDT 24
Finished Mar 16 12:24:05 PM PDT 24
Peak memory 209812 kb
Host smart-74bf7e02-192e-470a-afe3-ce4326349ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483569942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3483569942
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1341172149
Short name T721
Test name
Test status
Simulation time 12466646 ps
CPU time 0.76 seconds
Started Mar 16 12:24:05 PM PDT 24
Finished Mar 16 12:24:06 PM PDT 24
Peak memory 205872 kb
Host smart-3e2a1c10-4948-43af-b438-f887e105dad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341172149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1341172149
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1136831367
Short name T976
Test name
Test status
Simulation time 529075684 ps
CPU time 4.9 seconds
Started Mar 16 12:24:05 PM PDT 24
Finished Mar 16 12:24:10 PM PDT 24
Peak memory 221836 kb
Host smart-1c9951d0-8f64-47c9-ab8a-1ff653fc7e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136831367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1136831367
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3378330213
Short name T63
Test name
Test status
Simulation time 29430947 ps
CPU time 1.89 seconds
Started Mar 16 12:24:04 PM PDT 24
Finished Mar 16 12:24:06 PM PDT 24
Peak memory 214124 kb
Host smart-be83225a-3c81-4abf-8b00-90f3466db48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378330213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3378330213
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.234188831
Short name T65
Test name
Test status
Simulation time 196020366 ps
CPU time 5.18 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:06 PM PDT 24
Peak memory 214188 kb
Host smart-b2286537-ebea-4a24-92dd-3fd85c9b9c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234188831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.234188831
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.4048599124
Short name T232
Test name
Test status
Simulation time 532617322 ps
CPU time 18.68 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:20 PM PDT 24
Peak memory 210732 kb
Host smart-b7dd02df-694e-4f7a-9fdd-9a708a16f9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048599124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.4048599124
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.4025877612
Short name T665
Test name
Test status
Simulation time 86654602 ps
CPU time 4.1 seconds
Started Mar 16 12:23:58 PM PDT 24
Finished Mar 16 12:24:03 PM PDT 24
Peak memory 220348 kb
Host smart-d82300a5-ae06-4fe8-a1fc-ce5afea9ceb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025877612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.4025877612
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.359953516
Short name T829
Test name
Test status
Simulation time 194832019 ps
CPU time 4.83 seconds
Started Mar 16 12:24:02 PM PDT 24
Finished Mar 16 12:24:07 PM PDT 24
Peak memory 214204 kb
Host smart-860ca3e2-d426-46ad-a055-f72317a81c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359953516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.359953516
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1772541361
Short name T878
Test name
Test status
Simulation time 75021914 ps
CPU time 2.38 seconds
Started Mar 16 12:24:00 PM PDT 24
Finished Mar 16 12:24:03 PM PDT 24
Peak memory 206088 kb
Host smart-439b0559-d90d-441d-a8fe-cf869b5c3b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772541361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1772541361
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.541595847
Short name T684
Test name
Test status
Simulation time 603908491 ps
CPU time 4.81 seconds
Started Mar 16 12:26:23 PM PDT 24
Finished Mar 16 12:26:28 PM PDT 24
Peak memory 208396 kb
Host smart-e4ceb130-8629-432c-bdd0-b95c7755bf70
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541595847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.541595847
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.65798394
Short name T864
Test name
Test status
Simulation time 41602833 ps
CPU time 1.86 seconds
Started Mar 16 12:24:00 PM PDT 24
Finished Mar 16 12:24:02 PM PDT 24
Peak memory 207936 kb
Host smart-4fe06c7e-81c8-44ce-82d5-019fbad3d72b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65798394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.65798394
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.191641010
Short name T305
Test name
Test status
Simulation time 56482209 ps
CPU time 2.4 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:04 PM PDT 24
Peak memory 206592 kb
Host smart-865f1c93-9cb2-4543-919c-6268d1d0f940
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191641010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.191641010
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1266782051
Short name T177
Test name
Test status
Simulation time 119819677 ps
CPU time 2.34 seconds
Started Mar 16 12:23:59 PM PDT 24
Finished Mar 16 12:24:02 PM PDT 24
Peak memory 209544 kb
Host smart-92ec2aed-3e41-42c3-bbae-7a69cd543a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266782051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1266782051
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1778970378
Short name T945
Test name
Test status
Simulation time 192920871 ps
CPU time 2.37 seconds
Started Mar 16 12:24:08 PM PDT 24
Finished Mar 16 12:24:10 PM PDT 24
Peak memory 208304 kb
Host smart-70183e7d-1ac8-4448-962e-aa7b0fb315d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778970378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1778970378
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2722610120
Short name T202
Test name
Test status
Simulation time 96614937 ps
CPU time 3.23 seconds
Started Mar 16 12:24:00 PM PDT 24
Finished Mar 16 12:24:03 PM PDT 24
Peak memory 218344 kb
Host smart-d042be4c-a44b-486e-8f23-ee9dfaa12a32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722610120 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2722610120
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3295151172
Short name T761
Test name
Test status
Simulation time 862922664 ps
CPU time 9.41 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:11 PM PDT 24
Peak memory 214232 kb
Host smart-494b36f5-260d-4861-8906-d0b38dfcb81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295151172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3295151172
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3120267292
Short name T985
Test name
Test status
Simulation time 160562639 ps
CPU time 3.89 seconds
Started Mar 16 12:24:03 PM PDT 24
Finished Mar 16 12:24:07 PM PDT 24
Peak memory 210244 kb
Host smart-88718818-ad55-4768-a6a7-97f6b6b9ae1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120267292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3120267292
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3824748269
Short name T658
Test name
Test status
Simulation time 24454068 ps
CPU time 0.89 seconds
Started Mar 16 12:26:18 PM PDT 24
Finished Mar 16 12:26:19 PM PDT 24
Peak memory 205768 kb
Host smart-65f0c026-9d59-4140-9491-a30d26532733
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824748269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3824748269
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1317424424
Short name T1078
Test name
Test status
Simulation time 101831385 ps
CPU time 4.87 seconds
Started Mar 16 12:23:58 PM PDT 24
Finished Mar 16 12:24:04 PM PDT 24
Peak memory 210352 kb
Host smart-fb9dc251-8a07-4710-9c53-55d7fdcbf28c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317424424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1317424424
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3685363956
Short name T783
Test name
Test status
Simulation time 83848568 ps
CPU time 2.58 seconds
Started Mar 16 12:24:08 PM PDT 24
Finished Mar 16 12:24:11 PM PDT 24
Peak memory 208884 kb
Host smart-3295a87d-0b03-4ca8-91c0-a6d0285771fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685363956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3685363956
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2392586170
Short name T794
Test name
Test status
Simulation time 166747899 ps
CPU time 7.21 seconds
Started Mar 16 12:23:59 PM PDT 24
Finished Mar 16 12:24:07 PM PDT 24
Peak memory 220784 kb
Host smart-2a9fb3df-8fb9-4d47-b92f-c9fc7af90ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392586170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2392586170
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2164577040
Short name T346
Test name
Test status
Simulation time 235841832 ps
CPU time 4.48 seconds
Started Mar 16 12:23:59 PM PDT 24
Finished Mar 16 12:24:04 PM PDT 24
Peak memory 214180 kb
Host smart-99deff7f-8fac-4b46-9078-1ac43d37db3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164577040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2164577040
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.4199355053
Short name T734
Test name
Test status
Simulation time 61527711 ps
CPU time 3.12 seconds
Started Mar 16 12:24:05 PM PDT 24
Finished Mar 16 12:24:08 PM PDT 24
Peak memory 208932 kb
Host smart-38d6c44f-e03a-4ddb-8381-5eb0441d9b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199355053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.4199355053
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.4237114257
Short name T1071
Test name
Test status
Simulation time 10036249588 ps
CPU time 95.69 seconds
Started Mar 16 12:24:03 PM PDT 24
Finished Mar 16 12:25:39 PM PDT 24
Peak memory 218224 kb
Host smart-251d824c-1790-45d1-a925-abe64695dc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237114257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.4237114257
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.447583967
Short name T923
Test name
Test status
Simulation time 903256556 ps
CPU time 5.24 seconds
Started Mar 16 12:24:00 PM PDT 24
Finished Mar 16 12:24:06 PM PDT 24
Peak memory 206848 kb
Host smart-636e99ec-d0c2-4fed-99b8-e1fd5a3d3b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447583967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.447583967
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3066118513
Short name T108
Test name
Test status
Simulation time 57160449 ps
CPU time 1.84 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:03 PM PDT 24
Peak memory 206728 kb
Host smart-01150f31-4098-4ca4-bd5f-9d8511821cd9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066118513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3066118513
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.4033499498
Short name T725
Test name
Test status
Simulation time 3608893335 ps
CPU time 6.69 seconds
Started Mar 16 12:24:02 PM PDT 24
Finished Mar 16 12:24:09 PM PDT 24
Peak memory 207908 kb
Host smart-5f122d48-e956-4189-8c8b-6dd69dcd72b1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033499498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.4033499498
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2543848962
Short name T951
Test name
Test status
Simulation time 52310365 ps
CPU time 2.85 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:03 PM PDT 24
Peak memory 206768 kb
Host smart-71d60eff-3f93-4c1a-9781-e3ec72e01e07
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543848962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2543848962
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.4115205797
Short name T73
Test name
Test status
Simulation time 37397746 ps
CPU time 2.45 seconds
Started Mar 16 12:24:03 PM PDT 24
Finished Mar 16 12:24:05 PM PDT 24
Peak memory 207584 kb
Host smart-0a52069d-305a-4577-9297-5239565cade0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115205797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.4115205797
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2014427514
Short name T1050
Test name
Test status
Simulation time 222357932 ps
CPU time 3.73 seconds
Started Mar 16 12:23:59 PM PDT 24
Finished Mar 16 12:24:03 PM PDT 24
Peak memory 206532 kb
Host smart-ccf79589-eb48-4f12-ba90-bf1ecb11fa4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014427514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2014427514
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2773569883
Short name T1001
Test name
Test status
Simulation time 87857014 ps
CPU time 2.26 seconds
Started Mar 16 12:24:04 PM PDT 24
Finished Mar 16 12:24:06 PM PDT 24
Peak memory 206336 kb
Host smart-756b93dc-f132-4cdc-ae33-6dee2a8b5805
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773569883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2773569883
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.4088503375
Short name T683
Test name
Test status
Simulation time 835337119 ps
CPU time 3.1 seconds
Started Mar 16 12:24:01 PM PDT 24
Finished Mar 16 12:24:04 PM PDT 24
Peak memory 214296 kb
Host smart-de8d4648-5012-4a36-824c-fff8efe1be32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088503375 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.4088503375
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.1821979822
Short name T970
Test name
Test status
Simulation time 290825445 ps
CPU time 8.38 seconds
Started Mar 16 12:24:02 PM PDT 24
Finished Mar 16 12:24:11 PM PDT 24
Peak memory 208108 kb
Host smart-7bc5a4cb-787b-48c1-8d46-50fc46b62db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821979822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.1821979822
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3071144987
Short name T817
Test name
Test status
Simulation time 68151676 ps
CPU time 2.75 seconds
Started Mar 16 12:23:59 PM PDT 24
Finished Mar 16 12:24:03 PM PDT 24
Peak memory 210696 kb
Host smart-fafff162-d43d-4637-968f-9e352fd1f113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071144987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3071144987
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.4226743269
Short name T1030
Test name
Test status
Simulation time 15755290 ps
CPU time 0.77 seconds
Started Mar 16 12:24:10 PM PDT 24
Finished Mar 16 12:24:11 PM PDT 24
Peak memory 205860 kb
Host smart-8c5b32de-28dc-42ea-805a-bb8f21f13be2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226743269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.4226743269
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1833631535
Short name T222
Test name
Test status
Simulation time 135055593 ps
CPU time 2.18 seconds
Started Mar 16 12:25:17 PM PDT 24
Finished Mar 16 12:25:22 PM PDT 24
Peak memory 212060 kb
Host smart-8352b2f4-5039-4cf2-91c0-aff2279251fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1833631535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1833631535
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1566046978
Short name T416
Test name
Test status
Simulation time 253047377 ps
CPU time 4.6 seconds
Started Mar 16 12:24:04 PM PDT 24
Finished Mar 16 12:24:09 PM PDT 24
Peak memory 210552 kb
Host smart-267346d5-30c8-4b16-b0f2-0a812ab7ae26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566046978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1566046978
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2134352832
Short name T959
Test name
Test status
Simulation time 609258888 ps
CPU time 2.82 seconds
Started Mar 16 12:24:22 PM PDT 24
Finished Mar 16 12:24:25 PM PDT 24
Peak memory 209976 kb
Host smart-df3fb367-caa2-4247-9a7f-085dd8ca36d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134352832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2134352832
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3610283608
Short name T629
Test name
Test status
Simulation time 927737665 ps
CPU time 4.5 seconds
Started Mar 16 12:24:19 PM PDT 24
Finished Mar 16 12:24:24 PM PDT 24
Peak memory 208332 kb
Host smart-4cc941d8-bfb5-45de-a9cb-fd8aab3e9ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610283608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3610283608
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3649605985
Short name T952
Test name
Test status
Simulation time 137609009 ps
CPU time 4.08 seconds
Started Mar 16 12:25:30 PM PDT 24
Finished Mar 16 12:25:34 PM PDT 24
Peak memory 209764 kb
Host smart-680e4b1a-a454-4479-8f8a-eeda434bfc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649605985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3649605985
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.15352546
Short name T176
Test name
Test status
Simulation time 69115361 ps
CPU time 4.22 seconds
Started Mar 16 12:26:16 PM PDT 24
Finished Mar 16 12:26:20 PM PDT 24
Peak memory 218212 kb
Host smart-bdcee3c3-27e6-4d07-9a59-1061c43a2b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15352546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.15352546
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3075239865
Short name T370
Test name
Test status
Simulation time 79810511 ps
CPU time 2.42 seconds
Started Mar 16 12:24:05 PM PDT 24
Finished Mar 16 12:24:07 PM PDT 24
Peak memory 206592 kb
Host smart-c181d0cd-12c2-4b74-82b2-39579adf8f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075239865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3075239865
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2682614368
Short name T335
Test name
Test status
Simulation time 214981858 ps
CPU time 6.2 seconds
Started Mar 16 12:24:04 PM PDT 24
Finished Mar 16 12:24:16 PM PDT 24
Peak memory 207972 kb
Host smart-339f14f5-9d5e-419f-9ec6-8d9fd8b2357e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682614368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2682614368
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.776331025
Short name T733
Test name
Test status
Simulation time 102163887 ps
CPU time 2.11 seconds
Started Mar 16 12:24:00 PM PDT 24
Finished Mar 16 12:24:02 PM PDT 24
Peak memory 208476 kb
Host smart-2fc1a4bb-8278-4fa0-84e5-c4b353932310
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776331025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.776331025
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2024986241
Short name T699
Test name
Test status
Simulation time 100333664 ps
CPU time 2.67 seconds
Started Mar 16 12:24:04 PM PDT 24
Finished Mar 16 12:24:07 PM PDT 24
Peak memory 206636 kb
Host smart-5385803c-02de-45fa-aee7-a0f01c77aa8f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024986241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2024986241
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2483414943
Short name T628
Test name
Test status
Simulation time 73026685 ps
CPU time 2.83 seconds
Started Mar 16 12:24:06 PM PDT 24
Finished Mar 16 12:24:09 PM PDT 24
Peak memory 209024 kb
Host smart-fff01159-e0ff-4eb0-a698-23e4fa1948b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483414943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2483414943
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1844408572
Short name T638
Test name
Test status
Simulation time 2309770502 ps
CPU time 15.08 seconds
Started Mar 16 12:24:04 PM PDT 24
Finished Mar 16 12:24:19 PM PDT 24
Peak memory 207808 kb
Host smart-d4452ffb-c508-4272-9e4b-ec0aec5b5b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844408572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1844408572
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2554134476
Short name T1041
Test name
Test status
Simulation time 5887519989 ps
CPU time 30.6 seconds
Started Mar 16 12:24:19 PM PDT 24
Finished Mar 16 12:24:49 PM PDT 24
Peak memory 216772 kb
Host smart-9341dafc-052e-41f5-b91c-ff1dacdb9e66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554134476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2554134476
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2964081469
Short name T246
Test name
Test status
Simulation time 607904157 ps
CPU time 10.55 seconds
Started Mar 16 12:24:18 PM PDT 24
Finished Mar 16 12:24:28 PM PDT 24
Peak memory 219872 kb
Host smart-2192611c-a0e5-4791-a5ed-018fbb8605b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964081469 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2964081469
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.738432754
Short name T188
Test name
Test status
Simulation time 572297412 ps
CPU time 4.09 seconds
Started Mar 16 12:24:04 PM PDT 24
Finished Mar 16 12:24:09 PM PDT 24
Peak memory 214200 kb
Host smart-48ef7be3-9ca3-4ff6-bff1-2a664f859a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738432754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.738432754
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2080737766
Short name T873
Test name
Test status
Simulation time 207470352 ps
CPU time 4.28 seconds
Started Mar 16 12:24:08 PM PDT 24
Finished Mar 16 12:24:13 PM PDT 24
Peak memory 209940 kb
Host smart-3c5e3297-113b-4b21-b373-495cdb9d6726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080737766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2080737766
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1955002457
Short name T1038
Test name
Test status
Simulation time 32231220 ps
CPU time 1.04 seconds
Started Mar 16 12:24:06 PM PDT 24
Finished Mar 16 12:24:07 PM PDT 24
Peak memory 205968 kb
Host smart-65309bd1-60c9-4e4b-92c3-76813a9672ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955002457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1955002457
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.686485750
Short name T849
Test name
Test status
Simulation time 343709646 ps
CPU time 3.68 seconds
Started Mar 16 12:24:04 PM PDT 24
Finished Mar 16 12:24:08 PM PDT 24
Peak memory 209460 kb
Host smart-90b86517-2412-44b9-be6a-8661e2ac6ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686485750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.686485750
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3677850824
Short name T702
Test name
Test status
Simulation time 226032705 ps
CPU time 6.38 seconds
Started Mar 16 12:24:06 PM PDT 24
Finished Mar 16 12:24:12 PM PDT 24
Peak memory 209008 kb
Host smart-18068e89-8a1d-4a0d-b7cb-c3ac7c0a6409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677850824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3677850824
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3454882068
Short name T238
Test name
Test status
Simulation time 1369294705 ps
CPU time 30.72 seconds
Started Mar 16 12:24:17 PM PDT 24
Finished Mar 16 12:24:48 PM PDT 24
Peak memory 218972 kb
Host smart-52d58105-b56d-4a0b-99d1-556d8993a615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454882068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3454882068
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1872706992
Short name T273
Test name
Test status
Simulation time 29009818583 ps
CPU time 65.15 seconds
Started Mar 16 12:25:17 PM PDT 24
Finished Mar 16 12:26:25 PM PDT 24
Peak memory 228672 kb
Host smart-745be286-17bb-4e36-9c20-5f28e6e422a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872706992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1872706992
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2169915406
Short name T808
Test name
Test status
Simulation time 36103072 ps
CPU time 1.72 seconds
Started Mar 16 12:24:09 PM PDT 24
Finished Mar 16 12:24:10 PM PDT 24
Peak memory 214332 kb
Host smart-fae412f8-5d74-4cce-bfb2-d15082f0d44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169915406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2169915406
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2759596594
Short name T609
Test name
Test status
Simulation time 97784275 ps
CPU time 3.9 seconds
Started Mar 16 12:24:05 PM PDT 24
Finished Mar 16 12:24:10 PM PDT 24
Peak memory 207456 kb
Host smart-4f4ee03e-bebe-4c77-a464-e2afcb10ec3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759596594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2759596594
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1164765199
Short name T582
Test name
Test status
Simulation time 12932122875 ps
CPU time 29.07 seconds
Started Mar 16 12:24:06 PM PDT 24
Finished Mar 16 12:24:35 PM PDT 24
Peak memory 209104 kb
Host smart-e6712037-30d7-44e3-bf7a-35534f72eb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164765199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1164765199
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2307252199
Short name T742
Test name
Test status
Simulation time 770957938 ps
CPU time 7.08 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:40 PM PDT 24
Peak memory 208484 kb
Host smart-4334486e-35e9-41c2-8d29-77f8011bf7e6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307252199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2307252199
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1751940930
Short name T1055
Test name
Test status
Simulation time 51449715 ps
CPU time 2.73 seconds
Started Mar 16 12:24:03 PM PDT 24
Finished Mar 16 12:24:06 PM PDT 24
Peak memory 206804 kb
Host smart-3f1bf3e6-70ba-497d-8328-6c833673f3f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751940930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1751940930
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.328324621
Short name T76
Test name
Test status
Simulation time 162712054 ps
CPU time 3.6 seconds
Started Mar 16 12:24:07 PM PDT 24
Finished Mar 16 12:24:11 PM PDT 24
Peak memory 208332 kb
Host smart-ec0dabc9-e1a1-4652-8068-7e31deca641d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328324621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.328324621
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3142761635
Short name T649
Test name
Test status
Simulation time 966527864 ps
CPU time 5.72 seconds
Started Mar 16 12:26:17 PM PDT 24
Finished Mar 16 12:26:23 PM PDT 24
Peak memory 209224 kb
Host smart-81f457f3-9359-4835-b8ac-ff42d2b26739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142761635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3142761635
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1117886627
Short name T656
Test name
Test status
Simulation time 45129298 ps
CPU time 2.33 seconds
Started Mar 16 12:24:05 PM PDT 24
Finished Mar 16 12:24:07 PM PDT 24
Peak memory 206656 kb
Host smart-0c92e458-e8f5-4c3c-9899-b3e70a821256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117886627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1117886627
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2130944253
Short name T284
Test name
Test status
Simulation time 2530185951 ps
CPU time 62.45 seconds
Started Mar 16 12:24:06 PM PDT 24
Finished Mar 16 12:25:08 PM PDT 24
Peak memory 222804 kb
Host smart-c1c6b22c-5c45-42e1-a419-e1f726733974
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130944253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2130944253
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1606560385
Short name T921
Test name
Test status
Simulation time 373310314 ps
CPU time 2.53 seconds
Started Mar 16 12:24:17 PM PDT 24
Finished Mar 16 12:24:20 PM PDT 24
Peak memory 218144 kb
Host smart-6794654f-7c13-4160-a2e6-2447fdb55eb3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606560385 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1606560385
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.96774513
Short name T715
Test name
Test status
Simulation time 52726599 ps
CPU time 2.84 seconds
Started Mar 16 12:24:06 PM PDT 24
Finished Mar 16 12:24:09 PM PDT 24
Peak memory 209904 kb
Host smart-5e54cfa2-347b-423c-9fce-7c77ab6213aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96774513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.96774513
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3732969848
Short name T673
Test name
Test status
Simulation time 49792334 ps
CPU time 0.73 seconds
Started Mar 16 12:24:22 PM PDT 24
Finished Mar 16 12:24:23 PM PDT 24
Peak memory 205780 kb
Host smart-3db3c334-bf5b-4cb3-8c50-3d18c4e3e0c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732969848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3732969848
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1987389023
Short name T422
Test name
Test status
Simulation time 68055079 ps
CPU time 3.88 seconds
Started Mar 16 12:25:17 PM PDT 24
Finished Mar 16 12:25:23 PM PDT 24
Peak memory 213024 kb
Host smart-dc851c59-9e86-47f4-a427-3423a261d7b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1987389023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1987389023
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2367143288
Short name T28
Test name
Test status
Simulation time 589629566 ps
CPU time 5.65 seconds
Started Mar 16 12:25:17 PM PDT 24
Finished Mar 16 12:25:25 PM PDT 24
Peak memory 219100 kb
Host smart-80c2c9c9-0acd-48f9-b601-9ca7e6e90909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367143288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2367143288
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2278732103
Short name T885
Test name
Test status
Simulation time 126721500 ps
CPU time 2.33 seconds
Started Mar 16 12:24:25 PM PDT 24
Finished Mar 16 12:24:29 PM PDT 24
Peak memory 209428 kb
Host smart-4da9927b-03a5-4a99-b6d0-15451c989256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278732103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2278732103
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2816192254
Short name T969
Test name
Test status
Simulation time 386343514 ps
CPU time 4.08 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:37 PM PDT 24
Peak memory 219548 kb
Host smart-eacd6a6d-5d2a-4528-a7c4-a00919771a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816192254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2816192254
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2763472302
Short name T846
Test name
Test status
Simulation time 546606291 ps
CPU time 6.54 seconds
Started Mar 16 12:24:04 PM PDT 24
Finished Mar 16 12:24:10 PM PDT 24
Peak memory 218220 kb
Host smart-60d48920-5e28-4816-adf3-b75ba2238750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763472302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2763472302
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3684165180
Short name T710
Test name
Test status
Simulation time 879891007 ps
CPU time 9.64 seconds
Started Mar 16 12:24:06 PM PDT 24
Finished Mar 16 12:24:16 PM PDT 24
Peak memory 208364 kb
Host smart-f2ef3aaa-eaca-4e00-a78e-27837987f810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684165180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3684165180
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.2411375352
Short name T869
Test name
Test status
Simulation time 1956996557 ps
CPU time 14.34 seconds
Started Mar 16 12:24:15 PM PDT 24
Finished Mar 16 12:24:29 PM PDT 24
Peak memory 208712 kb
Host smart-711bda3e-9567-4db2-b41e-5c8e4adc0cc9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411375352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2411375352
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3433192832
Short name T984
Test name
Test status
Simulation time 280893374 ps
CPU time 7.11 seconds
Started Mar 16 12:24:09 PM PDT 24
Finished Mar 16 12:24:16 PM PDT 24
Peak memory 207808 kb
Host smart-539d7bba-7dc7-42e2-88f2-b986fb7948fc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433192832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3433192832
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3345431814
Short name T807
Test name
Test status
Simulation time 200868396 ps
CPU time 3.07 seconds
Started Mar 16 12:24:21 PM PDT 24
Finished Mar 16 12:24:24 PM PDT 24
Peak memory 206708 kb
Host smart-e4a31652-e74c-437a-af75-74f6bf566bc0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345431814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3345431814
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2161469009
Short name T930
Test name
Test status
Simulation time 299402229 ps
CPU time 8.83 seconds
Started Mar 16 12:24:25 PM PDT 24
Finished Mar 16 12:24:35 PM PDT 24
Peak memory 218140 kb
Host smart-0c1e35be-a15f-4885-9829-82275fbdc42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161469009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2161469009
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1526296381
Short name T737
Test name
Test status
Simulation time 23566411 ps
CPU time 1.72 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:34 PM PDT 24
Peak memory 206652 kb
Host smart-d75812b8-1392-43bd-8cf7-dbb900112de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526296381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1526296381
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1919841132
Short name T208
Test name
Test status
Simulation time 1073973139 ps
CPU time 13.24 seconds
Started Mar 16 12:24:22 PM PDT 24
Finished Mar 16 12:24:36 PM PDT 24
Peak memory 216072 kb
Host smart-e98e3418-915a-44ca-96a1-1fa560d24485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919841132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1919841132
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.1559514906
Short name T821
Test name
Test status
Simulation time 365442500 ps
CPU time 11.57 seconds
Started Mar 16 12:24:17 PM PDT 24
Finished Mar 16 12:24:29 PM PDT 24
Peak memory 222380 kb
Host smart-5bcf22d6-b348-4031-b040-1ff8d84f18cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559514906 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.1559514906
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.382936701
Short name T685
Test name
Test status
Simulation time 409276915 ps
CPU time 11.08 seconds
Started Mar 16 12:24:09 PM PDT 24
Finished Mar 16 12:24:20 PM PDT 24
Peak memory 218228 kb
Host smart-188d7a19-4cc0-4c20-9507-186fae31fa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382936701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.382936701
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2329152637
Short name T950
Test name
Test status
Simulation time 71333970 ps
CPU time 1.45 seconds
Started Mar 16 12:24:18 PM PDT 24
Finished Mar 16 12:24:19 PM PDT 24
Peak memory 208484 kb
Host smart-df556f26-7385-4abd-80ab-99e877460544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329152637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2329152637
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1483524697
Short name T903
Test name
Test status
Simulation time 21313219 ps
CPU time 0.99 seconds
Started Mar 16 12:24:22 PM PDT 24
Finished Mar 16 12:24:24 PM PDT 24
Peak memory 206024 kb
Host smart-b568f507-2818-41d0-b33a-e5aa5797bcda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483524697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1483524697
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2173053156
Short name T409
Test name
Test status
Simulation time 120654944 ps
CPU time 3.94 seconds
Started Mar 16 12:24:18 PM PDT 24
Finished Mar 16 12:24:23 PM PDT 24
Peak memory 214184 kb
Host smart-9a6b9d0d-072d-455f-90fd-8071c6b304ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2173053156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2173053156
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1453161795
Short name T38
Test name
Test status
Simulation time 931043090 ps
CPU time 6.92 seconds
Started Mar 16 12:24:22 PM PDT 24
Finished Mar 16 12:24:29 PM PDT 24
Peak memory 214232 kb
Host smart-19359375-5fbe-4d72-aa58-1192ac1f4854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453161795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1453161795
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.643729780
Short name T719
Test name
Test status
Simulation time 453950291 ps
CPU time 4.3 seconds
Started Mar 16 12:24:19 PM PDT 24
Finished Mar 16 12:24:24 PM PDT 24
Peak memory 208980 kb
Host smart-08be0b7f-e534-4df6-8231-b08d963fd0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643729780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.643729780
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2990510114
Short name T92
Test name
Test status
Simulation time 88886336 ps
CPU time 3.69 seconds
Started Mar 16 12:24:27 PM PDT 24
Finished Mar 16 12:24:33 PM PDT 24
Peak memory 208940 kb
Host smart-6c482c88-c40b-4f6f-a379-b2c7a334f7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990510114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2990510114
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.622390946
Short name T894
Test name
Test status
Simulation time 51595254 ps
CPU time 3.42 seconds
Started Mar 16 12:24:27 PM PDT 24
Finished Mar 16 12:24:33 PM PDT 24
Peak memory 220276 kb
Host smart-343f8629-7f26-4a35-9877-f5213370b091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622390946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.622390946
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1939514487
Short name T190
Test name
Test status
Simulation time 4447872168 ps
CPU time 41.43 seconds
Started Mar 16 12:24:10 PM PDT 24
Finished Mar 16 12:24:52 PM PDT 24
Peak memory 214248 kb
Host smart-ad8da8b3-275d-42f0-badb-61ff38c390f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939514487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1939514487
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3184509514
Short name T359
Test name
Test status
Simulation time 1690757062 ps
CPU time 6.51 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:37 PM PDT 24
Peak memory 208224 kb
Host smart-536cfe8f-02f9-41f4-9ee0-464beca06fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184509514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3184509514
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3519721647
Short name T587
Test name
Test status
Simulation time 643881002 ps
CPU time 7 seconds
Started Mar 16 12:24:12 PM PDT 24
Finished Mar 16 12:24:19 PM PDT 24
Peak memory 207680 kb
Host smart-9d9e3c4c-7635-4b8f-8b49-b1e29eaf90f2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519721647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3519721647
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.4217310097
Short name T949
Test name
Test status
Simulation time 3923379247 ps
CPU time 46.02 seconds
Started Mar 16 12:24:26 PM PDT 24
Finished Mar 16 12:25:15 PM PDT 24
Peak memory 208332 kb
Host smart-de0cb8fd-67dd-44c6-8c54-f73499b29694
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217310097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.4217310097
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.848870042
Short name T705
Test name
Test status
Simulation time 291413354 ps
CPU time 3.45 seconds
Started Mar 16 12:24:29 PM PDT 24
Finished Mar 16 12:24:33 PM PDT 24
Peak memory 208632 kb
Host smart-1c95d900-6b4f-4d12-ac80-8b35bd9ba9f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848870042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.848870042
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1482490399
Short name T820
Test name
Test status
Simulation time 124657750 ps
CPU time 4.49 seconds
Started Mar 16 12:24:24 PM PDT 24
Finished Mar 16 12:24:29 PM PDT 24
Peak memory 214156 kb
Host smart-997825f6-63f2-4b53-97af-afcd279829ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482490399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1482490399
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1899618076
Short name T875
Test name
Test status
Simulation time 21922169 ps
CPU time 1.87 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:33 PM PDT 24
Peak memory 206960 kb
Host smart-94fc33e7-b31d-425b-abdf-106e806def2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899618076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1899618076
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3665070449
Short name T307
Test name
Test status
Simulation time 5636050096 ps
CPU time 41.6 seconds
Started Mar 16 12:24:29 PM PDT 24
Finished Mar 16 12:25:12 PM PDT 24
Peak memory 222380 kb
Host smart-8810c15d-0c3d-4b01-9259-c4989e43127e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665070449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3665070449
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.420350090
Short name T215
Test name
Test status
Simulation time 200082662 ps
CPU time 12.06 seconds
Started Mar 16 12:24:26 PM PDT 24
Finished Mar 16 12:24:38 PM PDT 24
Peak memory 222472 kb
Host smart-b19657c8-578c-499c-82b7-21fb21854174
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420350090 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.420350090
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1333443105
Short name T791
Test name
Test status
Simulation time 73825693 ps
CPU time 2.32 seconds
Started Mar 16 12:24:11 PM PDT 24
Finished Mar 16 12:24:14 PM PDT 24
Peak memory 207644 kb
Host smart-a9fc8336-3938-46e9-8bb4-7399b2e46058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333443105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1333443105
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3462512893
Short name T651
Test name
Test status
Simulation time 52479958 ps
CPU time 2.38 seconds
Started Mar 16 12:24:22 PM PDT 24
Finished Mar 16 12:24:24 PM PDT 24
Peak memory 210092 kb
Host smart-0a2cd5d3-5fa0-4196-aea8-82e5b8e83abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462512893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3462512893
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2702821836
Short name T881
Test name
Test status
Simulation time 13774851 ps
CPU time 0.75 seconds
Started Mar 16 12:24:29 PM PDT 24
Finished Mar 16 12:24:31 PM PDT 24
Peak memory 205744 kb
Host smart-22035981-fb9f-49e3-9006-113e86e535b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702821836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2702821836
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3390238864
Short name T362
Test name
Test status
Simulation time 233030712 ps
CPU time 6.64 seconds
Started Mar 16 12:24:13 PM PDT 24
Finished Mar 16 12:24:19 PM PDT 24
Peak memory 214208 kb
Host smart-a05e7145-7edc-46a1-86e3-ddc67c62728d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3390238864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3390238864
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1779912341
Short name T980
Test name
Test status
Simulation time 442322038 ps
CPU time 3.67 seconds
Started Mar 16 12:24:19 PM PDT 24
Finished Mar 16 12:24:23 PM PDT 24
Peak memory 207492 kb
Host smart-450831f4-393c-48c6-adea-09ecfecadfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779912341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1779912341
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.4247923445
Short name T822
Test name
Test status
Simulation time 201014950 ps
CPU time 6.66 seconds
Started Mar 16 12:24:24 PM PDT 24
Finished Mar 16 12:24:32 PM PDT 24
Peak memory 214244 kb
Host smart-f450f2fa-4520-42df-ab0b-8efe641e95dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247923445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.4247923445
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1222000058
Short name T197
Test name
Test status
Simulation time 201229254 ps
CPU time 7.69 seconds
Started Mar 16 12:24:27 PM PDT 24
Finished Mar 16 12:24:37 PM PDT 24
Peak memory 211416 kb
Host smart-29677fec-a598-45fd-8eba-3fb03ca4e750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222000058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1222000058
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.527251940
Short name T825
Test name
Test status
Simulation time 223906366 ps
CPU time 3.12 seconds
Started Mar 16 12:24:29 PM PDT 24
Finished Mar 16 12:24:33 PM PDT 24
Peak memory 220204 kb
Host smart-85339237-b884-46dc-ad89-1ce4bb2477a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527251940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.527251940
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.4151759185
Short name T977
Test name
Test status
Simulation time 76241289 ps
CPU time 3.84 seconds
Started Mar 16 12:24:25 PM PDT 24
Finished Mar 16 12:24:30 PM PDT 24
Peak memory 207304 kb
Host smart-526a81cc-c2f8-41b1-87aa-eac7018ed83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151759185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.4151759185
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2533933782
Short name T606
Test name
Test status
Simulation time 69362875 ps
CPU time 3.35 seconds
Started Mar 16 12:24:17 PM PDT 24
Finished Mar 16 12:24:20 PM PDT 24
Peak memory 208468 kb
Host smart-75751b3c-4a29-40cf-b1d8-235a5058149c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533933782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2533933782
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3072113111
Short name T838
Test name
Test status
Simulation time 287134161 ps
CPU time 3.19 seconds
Started Mar 16 12:24:29 PM PDT 24
Finished Mar 16 12:24:33 PM PDT 24
Peak memory 208500 kb
Host smart-a684aa18-e4ad-40f5-a876-b9fb72e7b940
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072113111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3072113111
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3370111239
Short name T932
Test name
Test status
Simulation time 199889781 ps
CPU time 3.01 seconds
Started Mar 16 12:24:31 PM PDT 24
Finished Mar 16 12:24:34 PM PDT 24
Peak memory 206628 kb
Host smart-bf5dfe86-5424-4046-838a-c2fa46a0ed37
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370111239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3370111239
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3556212018
Short name T1044
Test name
Test status
Simulation time 112567866 ps
CPU time 3.02 seconds
Started Mar 16 12:24:25 PM PDT 24
Finished Mar 16 12:24:29 PM PDT 24
Peak memory 208592 kb
Host smart-24898f70-bcb3-4d85-8106-23d37087e7c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556212018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3556212018
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1011617861
Short name T578
Test name
Test status
Simulation time 143997076 ps
CPU time 3.85 seconds
Started Mar 16 12:24:13 PM PDT 24
Finished Mar 16 12:24:17 PM PDT 24
Peak memory 207720 kb
Host smart-2b6778c2-747a-4cd8-931a-565c4f35ed73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011617861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1011617861
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1731772723
Short name T968
Test name
Test status
Simulation time 585050996 ps
CPU time 3.78 seconds
Started Mar 16 12:25:31 PM PDT 24
Finished Mar 16 12:25:35 PM PDT 24
Peak memory 221016 kb
Host smart-cabe2783-534b-44f8-985a-d74a4e0dbe0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731772723 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1731772723
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.758158861
Short name T855
Test name
Test status
Simulation time 311931021 ps
CPU time 11.03 seconds
Started Mar 16 12:24:27 PM PDT 24
Finished Mar 16 12:24:40 PM PDT 24
Peak memory 214116 kb
Host smart-8ea48a07-5d43-4af0-bfb6-1fe826efb345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758158861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.758158861
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3707056253
Short name T681
Test name
Test status
Simulation time 431672381 ps
CPU time 7.19 seconds
Started Mar 16 12:24:27 PM PDT 24
Finished Mar 16 12:24:36 PM PDT 24
Peak memory 210352 kb
Host smart-362c278b-fe7c-4b3f-b500-bb0015848569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707056253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3707056253
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.934551121
Short name T666
Test name
Test status
Simulation time 17188000 ps
CPU time 0.8 seconds
Started Mar 16 12:23:33 PM PDT 24
Finished Mar 16 12:23:34 PM PDT 24
Peak memory 205728 kb
Host smart-bab427e6-aa39-415e-acbc-796df1ffa33a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934551121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.934551121
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3193324902
Short name T430
Test name
Test status
Simulation time 58076440 ps
CPU time 3.9 seconds
Started Mar 16 12:23:35 PM PDT 24
Finished Mar 16 12:23:39 PM PDT 24
Peak memory 215116 kb
Host smart-4431a4c3-7f0b-4daa-97b9-d371a055256d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193324902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3193324902
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.1697604138
Short name T1015
Test name
Test status
Simulation time 407854526 ps
CPU time 5.49 seconds
Started Mar 16 12:23:37 PM PDT 24
Finished Mar 16 12:23:43 PM PDT 24
Peak memory 222676 kb
Host smart-39022784-174f-45bf-bdb5-d35372c68ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697604138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1697604138
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.3781280175
Short name T381
Test name
Test status
Simulation time 338170796 ps
CPU time 3.13 seconds
Started Mar 16 12:23:41 PM PDT 24
Finished Mar 16 12:23:45 PM PDT 24
Peak memory 207824 kb
Host smart-dd00510e-43e8-4dfb-9ef8-8489ba66cb31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781280175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.3781280175
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4015047810
Short name T93
Test name
Test status
Simulation time 5500742979 ps
CPU time 30.06 seconds
Started Mar 16 12:23:26 PM PDT 24
Finished Mar 16 12:23:56 PM PDT 24
Peak memory 214260 kb
Host smart-6be0d43a-b2b7-4e88-adf4-2cba83a5d5cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015047810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4015047810
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.626888243
Short name T231
Test name
Test status
Simulation time 88828057 ps
CPU time 4.06 seconds
Started Mar 16 12:23:41 PM PDT 24
Finished Mar 16 12:23:45 PM PDT 24
Peak memory 211048 kb
Host smart-5376c7c9-680e-4479-b57d-21f65aca1cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626888243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.626888243
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1925258606
Short name T53
Test name
Test status
Simulation time 118432972 ps
CPU time 5.36 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:23:45 PM PDT 24
Peak memory 214180 kb
Host smart-fdc7c07e-0652-44ff-ab42-2ecb6a61fd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925258606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1925258606
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3455128181
Short name T780
Test name
Test status
Simulation time 14378632651 ps
CPU time 56.72 seconds
Started Mar 16 12:23:41 PM PDT 24
Finished Mar 16 12:24:38 PM PDT 24
Peak memory 208472 kb
Host smart-b64b8a07-996a-401d-a54d-eb7021e1b3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455128181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3455128181
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2986487292
Short name T11
Test name
Test status
Simulation time 651148146 ps
CPU time 18.98 seconds
Started Mar 16 12:23:42 PM PDT 24
Finished Mar 16 12:24:01 PM PDT 24
Peak memory 231552 kb
Host smart-8598b571-fcd0-45e0-bfb8-62c450150722
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986487292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2986487292
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3071759360
Short name T80
Test name
Test status
Simulation time 24073966 ps
CPU time 1.97 seconds
Started Mar 16 12:23:26 PM PDT 24
Finished Mar 16 12:23:28 PM PDT 24
Peak memory 207168 kb
Host smart-af512eb8-97ec-4374-888c-b0f033b49d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071759360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3071759360
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.3264173427
Short name T251
Test name
Test status
Simulation time 285310612 ps
CPU time 3.57 seconds
Started Mar 16 12:23:31 PM PDT 24
Finished Mar 16 12:23:34 PM PDT 24
Peak memory 206832 kb
Host smart-21750fcb-7a4c-45d5-9caa-1fd74800621d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264173427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.3264173427
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.4083390168
Short name T867
Test name
Test status
Simulation time 2738936033 ps
CPU time 15.44 seconds
Started Mar 16 12:23:29 PM PDT 24
Finished Mar 16 12:23:44 PM PDT 24
Peak memory 208468 kb
Host smart-458aac61-d1b5-43f8-a175-e5cf52c6e8bf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083390168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4083390168
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1899161911
Short name T953
Test name
Test status
Simulation time 131933295 ps
CPU time 2.94 seconds
Started Mar 16 12:23:37 PM PDT 24
Finished Mar 16 12:23:40 PM PDT 24
Peak memory 208452 kb
Host smart-220261bf-c88e-4231-8dfc-c0244b5fb72b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899161911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1899161911
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1548117402
Short name T345
Test name
Test status
Simulation time 658836431 ps
CPU time 4.74 seconds
Started Mar 16 12:23:41 PM PDT 24
Finished Mar 16 12:23:46 PM PDT 24
Peak memory 214104 kb
Host smart-456c0b2f-015b-4042-acef-5b3f912fe7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548117402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1548117402
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2719172186
Short name T434
Test name
Test status
Simulation time 73667342 ps
CPU time 3.14 seconds
Started Mar 16 12:23:44 PM PDT 24
Finished Mar 16 12:23:48 PM PDT 24
Peak memory 208420 kb
Host smart-fbc80b92-cd84-4dc3-95bb-07ec8c865fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719172186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2719172186
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3012688741
Short name T198
Test name
Test status
Simulation time 241421416 ps
CPU time 2.64 seconds
Started Mar 16 12:23:25 PM PDT 24
Finished Mar 16 12:23:28 PM PDT 24
Peak memory 207180 kb
Host smart-53fe0ec9-fb96-478e-a207-7cf080780ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012688741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3012688741
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1413675641
Short name T1073
Test name
Test status
Simulation time 55825035 ps
CPU time 1.85 seconds
Started Mar 16 12:23:34 PM PDT 24
Finished Mar 16 12:23:36 PM PDT 24
Peak memory 209820 kb
Host smart-5cd8d9c1-9fe6-4f0f-a605-5684110063bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413675641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1413675641
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.216488883
Short name T593
Test name
Test status
Simulation time 78162583 ps
CPU time 0.84 seconds
Started Mar 16 12:25:33 PM PDT 24
Finished Mar 16 12:25:35 PM PDT 24
Peak memory 205680 kb
Host smart-b91e52eb-b2ed-452e-ac8d-9c5b1306165f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216488883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.216488883
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2073311205
Short name T429
Test name
Test status
Simulation time 3974231283 ps
CPU time 98.15 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:26:08 PM PDT 24
Peak memory 215360 kb
Host smart-a530960f-a985-41b3-bcc2-09ed35ba62fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2073311205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2073311205
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2217882101
Short name T889
Test name
Test status
Simulation time 5622763643 ps
CPU time 87.07 seconds
Started Mar 16 12:24:25 PM PDT 24
Finished Mar 16 12:25:53 PM PDT 24
Peak memory 229448 kb
Host smart-11a324ed-f1c3-49f7-aea0-69185f070b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217882101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2217882101
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1127761390
Short name T870
Test name
Test status
Simulation time 23204052 ps
CPU time 1.61 seconds
Started Mar 16 12:24:29 PM PDT 24
Finished Mar 16 12:24:32 PM PDT 24
Peak memory 207104 kb
Host smart-066044aa-5328-4556-9a30-6bf5b1da86a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127761390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1127761390
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.687824914
Short name T316
Test name
Test status
Simulation time 134539342 ps
CPU time 2.93 seconds
Started Mar 16 12:25:39 PM PDT 24
Finished Mar 16 12:25:42 PM PDT 24
Peak memory 214044 kb
Host smart-e2495e79-32f5-4d74-a4aa-17ca2b284363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687824914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.687824914
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1351579849
Short name T605
Test name
Test status
Simulation time 132432454 ps
CPU time 3.77 seconds
Started Mar 16 12:24:29 PM PDT 24
Finished Mar 16 12:24:34 PM PDT 24
Peak memory 221576 kb
Host smart-a89a822c-dd36-4630-8600-cefa310d11bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351579849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1351579849
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.555342547
Short name T872
Test name
Test status
Simulation time 372722493 ps
CPU time 9.59 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:40 PM PDT 24
Peak memory 214216 kb
Host smart-369ed33d-80d2-40ad-b1d4-34a188ac171d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555342547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.555342547
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2909500664
Short name T286
Test name
Test status
Simulation time 595322125 ps
CPU time 4.84 seconds
Started Mar 16 12:24:28 PM PDT 24
Finished Mar 16 12:24:35 PM PDT 24
Peak memory 206908 kb
Host smart-1614ece9-b41e-4c69-a9ad-b0aaae25e651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909500664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2909500664
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3497741603
Short name T604
Test name
Test status
Simulation time 139123430 ps
CPU time 5.41 seconds
Started Mar 16 12:24:22 PM PDT 24
Finished Mar 16 12:24:28 PM PDT 24
Peak memory 207692 kb
Host smart-a535e9c8-e7a1-4f59-bb3c-579e24b06ce8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497741603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3497741603
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.795209174
Short name T922
Test name
Test status
Simulation time 111415742 ps
CPU time 3.13 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:34 PM PDT 24
Peak memory 208396 kb
Host smart-664d50fa-7c32-416d-9e1b-d6a5b2635905
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795209174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.795209174
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2761866587
Short name T663
Test name
Test status
Simulation time 64667962 ps
CPU time 2.39 seconds
Started Mar 16 12:24:29 PM PDT 24
Finished Mar 16 12:24:32 PM PDT 24
Peak memory 206812 kb
Host smart-9422aad8-b990-4bba-b051-3df03b9d0ee2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761866587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2761866587
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.4028841444
Short name T860
Test name
Test status
Simulation time 63152101 ps
CPU time 1.61 seconds
Started Mar 16 12:24:25 PM PDT 24
Finished Mar 16 12:24:27 PM PDT 24
Peak memory 208420 kb
Host smart-fcd9553f-9375-42a6-8f09-d0d39aad93dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028841444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4028841444
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2617069418
Short name T646
Test name
Test status
Simulation time 40888970 ps
CPU time 1.73 seconds
Started Mar 16 12:24:28 PM PDT 24
Finished Mar 16 12:24:32 PM PDT 24
Peak memory 206904 kb
Host smart-9bc02dcb-f175-41b3-ac3b-7ae87e2eec64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617069418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2617069418
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3797255473
Short name T397
Test name
Test status
Simulation time 235710649 ps
CPU time 7.31 seconds
Started Mar 16 12:24:32 PM PDT 24
Finished Mar 16 12:24:39 PM PDT 24
Peak memory 222556 kb
Host smart-31881268-2900-4fda-9ee4-647bbf517429
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797255473 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3797255473
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.13065197
Short name T966
Test name
Test status
Simulation time 68390267 ps
CPU time 3.95 seconds
Started Mar 16 12:24:32 PM PDT 24
Finished Mar 16 12:24:36 PM PDT 24
Peak memory 222296 kb
Host smart-b3179751-8944-4708-81cf-de4061cef17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13065197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.13065197
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3111119999
Short name T622
Test name
Test status
Simulation time 63280002 ps
CPU time 2.71 seconds
Started Mar 16 12:24:27 PM PDT 24
Finished Mar 16 12:24:32 PM PDT 24
Peak memory 210088 kb
Host smart-b469dfc4-c288-4b5e-8263-e31b0d9af035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111119999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3111119999
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.4049598987
Short name T979
Test name
Test status
Simulation time 7920195 ps
CPU time 0.68 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:31 PM PDT 24
Peak memory 205692 kb
Host smart-ef4d7c7c-45d3-430b-891c-c952107fe1b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049598987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.4049598987
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3892134574
Short name T898
Test name
Test status
Simulation time 876545774 ps
CPU time 6.3 seconds
Started Mar 16 12:24:33 PM PDT 24
Finished Mar 16 12:24:40 PM PDT 24
Peak memory 210560 kb
Host smart-6f2ad305-deb7-4e0b-8f9a-07446ee4324d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892134574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3892134574
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1435583653
Short name T1025
Test name
Test status
Simulation time 110680076 ps
CPU time 2.37 seconds
Started Mar 16 12:24:27 PM PDT 24
Finished Mar 16 12:24:32 PM PDT 24
Peak memory 214216 kb
Host smart-a60e4fc2-d60e-4dc2-948d-5be8eadfd030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435583653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1435583653
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.152234336
Short name T83
Test name
Test status
Simulation time 12837617743 ps
CPU time 38.18 seconds
Started Mar 16 12:24:35 PM PDT 24
Finished Mar 16 12:25:14 PM PDT 24
Peak memory 214188 kb
Host smart-66b807be-e3fa-4467-ac53-6cf02f037915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152234336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.152234336
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1392675032
Short name T194
Test name
Test status
Simulation time 45467936 ps
CPU time 3.01 seconds
Started Mar 16 12:24:32 PM PDT 24
Finished Mar 16 12:24:35 PM PDT 24
Peak memory 210880 kb
Host smart-ce9874e9-5943-4760-8f26-316515c64a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392675032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1392675032
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1694380248
Short name T759
Test name
Test status
Simulation time 68754613 ps
CPU time 3.3 seconds
Started Mar 16 12:24:29 PM PDT 24
Finished Mar 16 12:24:33 PM PDT 24
Peak memory 209568 kb
Host smart-e73babf8-df31-45a9-9248-041b0baf09b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694380248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1694380248
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3504741844
Short name T1051
Test name
Test status
Simulation time 282646864 ps
CPU time 3.85 seconds
Started Mar 16 12:24:24 PM PDT 24
Finished Mar 16 12:24:30 PM PDT 24
Peak memory 209076 kb
Host smart-0eb3eead-c7c3-4584-b71b-fb9c820456e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504741844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3504741844
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3637825937
Short name T1027
Test name
Test status
Simulation time 59350652 ps
CPU time 3.12 seconds
Started Mar 16 12:24:22 PM PDT 24
Finished Mar 16 12:24:26 PM PDT 24
Peak memory 208520 kb
Host smart-b0b23518-0d39-4df7-aa8d-b06714f86df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637825937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3637825937
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2073324112
Short name T682
Test name
Test status
Simulation time 114072231 ps
CPU time 3.81 seconds
Started Mar 16 12:24:24 PM PDT 24
Finished Mar 16 12:24:29 PM PDT 24
Peak memory 208480 kb
Host smart-a2976192-fbf4-4416-8700-4ebce7895601
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073324112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2073324112
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3798528960
Short name T196
Test name
Test status
Simulation time 1789494288 ps
CPU time 12.44 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:43 PM PDT 24
Peak memory 208240 kb
Host smart-518ea055-c220-4c3d-8d6f-e85bc55323af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798528960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3798528960
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2660836433
Short name T16
Test name
Test status
Simulation time 1541348491 ps
CPU time 23.72 seconds
Started Mar 16 12:25:31 PM PDT 24
Finished Mar 16 12:25:55 PM PDT 24
Peak memory 206600 kb
Host smart-5c9606d3-af7e-4470-a14e-0eac65d0be9f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660836433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2660836433
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3169934477
Short name T3
Test name
Test status
Simulation time 71751064 ps
CPU time 3.16 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:34 PM PDT 24
Peak memory 209468 kb
Host smart-890d4b06-8094-4fe3-baaa-75d300cbee13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169934477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3169934477
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.840188420
Short name T879
Test name
Test status
Simulation time 895410354 ps
CPU time 5.01 seconds
Started Mar 16 12:24:28 PM PDT 24
Finished Mar 16 12:24:35 PM PDT 24
Peak memory 206612 kb
Host smart-ee6b2bd9-d28c-4fae-9434-31d3ebc84ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840188420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.840188420
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3999369939
Short name T1019
Test name
Test status
Simulation time 336909658 ps
CPU time 2.72 seconds
Started Mar 16 12:24:37 PM PDT 24
Finished Mar 16 12:24:40 PM PDT 24
Peak memory 214252 kb
Host smart-d6955a74-c65d-4b90-b711-80badceb60e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999369939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3999369939
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.423261848
Short name T120
Test name
Test status
Simulation time 212468990 ps
CPU time 9.26 seconds
Started Mar 16 12:24:31 PM PDT 24
Finished Mar 16 12:24:41 PM PDT 24
Peak memory 222620 kb
Host smart-f3c9d951-43ae-4f46-bc4a-f88c72996584
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423261848 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.423261848
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3644610258
Short name T785
Test name
Test status
Simulation time 708435326 ps
CPU time 8.76 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:39 PM PDT 24
Peak memory 214152 kb
Host smart-345c1f14-1677-44c1-a0ca-0021f618964f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644610258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3644610258
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2334334153
Short name T585
Test name
Test status
Simulation time 56530710 ps
CPU time 3.12 seconds
Started Mar 16 12:24:35 PM PDT 24
Finished Mar 16 12:24:39 PM PDT 24
Peak memory 210112 kb
Host smart-aefd696b-f8cb-4e76-81e6-e576dc8a0065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334334153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2334334153
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2061357134
Short name T788
Test name
Test status
Simulation time 14102412 ps
CPU time 0.91 seconds
Started Mar 16 12:24:31 PM PDT 24
Finished Mar 16 12:24:32 PM PDT 24
Peak memory 206024 kb
Host smart-833362b8-144d-4000-8ceb-aff37933bff9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061357134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2061357134
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1506384624
Short name T1007
Test name
Test status
Simulation time 94899152 ps
CPU time 1.96 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:33 PM PDT 24
Peak memory 208836 kb
Host smart-43394a0e-835c-4c40-808d-093882aae471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506384624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1506384624
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1792246490
Short name T938
Test name
Test status
Simulation time 262951414 ps
CPU time 2.07 seconds
Started Mar 16 12:24:39 PM PDT 24
Finished Mar 16 12:24:41 PM PDT 24
Peak memory 208748 kb
Host smart-e7639e13-f286-4e6d-9f20-c6e28d55682e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792246490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1792246490
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1968548659
Short name T915
Test name
Test status
Simulation time 2640107696 ps
CPU time 66.56 seconds
Started Mar 16 12:24:35 PM PDT 24
Finished Mar 16 12:25:41 PM PDT 24
Peak memory 222312 kb
Host smart-069f9efd-e689-4b15-b0a2-bb3f8009a4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968548659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1968548659
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1435520180
Short name T234
Test name
Test status
Simulation time 488270239 ps
CPU time 11.65 seconds
Started Mar 16 12:24:23 PM PDT 24
Finished Mar 16 12:24:36 PM PDT 24
Peak memory 214212 kb
Host smart-add952f9-aee7-46ca-8ce9-f14caf94ebd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435520180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1435520180
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3538749434
Short name T816
Test name
Test status
Simulation time 201214617 ps
CPU time 3.18 seconds
Started Mar 16 12:24:39 PM PDT 24
Finished Mar 16 12:24:42 PM PDT 24
Peak memory 208284 kb
Host smart-58fa6489-8032-49f6-b3f3-ddc39fd91cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538749434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3538749434
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.3766983934
Short name T991
Test name
Test status
Simulation time 296122783 ps
CPU time 10.49 seconds
Started Mar 16 12:24:38 PM PDT 24
Finished Mar 16 12:24:48 PM PDT 24
Peak memory 218376 kb
Host smart-2836b54c-6774-4662-8a6d-2e207981c0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766983934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.3766983934
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1940294664
Short name T925
Test name
Test status
Simulation time 124903008 ps
CPU time 4.53 seconds
Started Mar 16 12:24:29 PM PDT 24
Finished Mar 16 12:24:35 PM PDT 24
Peak memory 207524 kb
Host smart-e25e3717-4883-4cdf-826a-11e59c92f806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940294664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1940294664
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3739022930
Short name T78
Test name
Test status
Simulation time 150907066 ps
CPU time 2.41 seconds
Started Mar 16 12:24:34 PM PDT 24
Finished Mar 16 12:24:36 PM PDT 24
Peak memory 206764 kb
Host smart-d0157ab2-1718-487d-8463-f62da2d3d246
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739022930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3739022930
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2735973493
Short name T944
Test name
Test status
Simulation time 75925907 ps
CPU time 2.17 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:32 PM PDT 24
Peak memory 209704 kb
Host smart-90d233c6-7226-4dde-b25d-46d51c65cd5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735973493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2735973493
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.551259340
Short name T583
Test name
Test status
Simulation time 276615627 ps
CPU time 4.22 seconds
Started Mar 16 12:24:28 PM PDT 24
Finished Mar 16 12:24:34 PM PDT 24
Peak memory 208356 kb
Host smart-801d6f9e-0009-494b-9888-119cf654079d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551259340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.551259340
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1979272263
Short name T1060
Test name
Test status
Simulation time 8811201500 ps
CPU time 94.46 seconds
Started Mar 16 12:24:32 PM PDT 24
Finished Mar 16 12:26:07 PM PDT 24
Peak memory 216348 kb
Host smart-55678ddd-a282-479f-822d-3690647d6bf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979272263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1979272263
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3320560629
Short name T201
Test name
Test status
Simulation time 287918963 ps
CPU time 8.22 seconds
Started Mar 16 12:24:33 PM PDT 24
Finished Mar 16 12:24:42 PM PDT 24
Peak memory 222448 kb
Host smart-defa8db8-e8a3-441d-924d-abc9d1cf1fef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320560629 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3320560629
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2177926027
Short name T324
Test name
Test status
Simulation time 3798606233 ps
CPU time 17.08 seconds
Started Mar 16 12:24:35 PM PDT 24
Finished Mar 16 12:24:53 PM PDT 24
Peak memory 217920 kb
Host smart-9362282a-ce43-432c-ab37-ff83a803af9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177926027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2177926027
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3303032872
Short name T399
Test name
Test status
Simulation time 103138373 ps
CPU time 1.49 seconds
Started Mar 16 12:24:38 PM PDT 24
Finished Mar 16 12:24:40 PM PDT 24
Peak memory 209536 kb
Host smart-eaa975d0-8ceb-4de9-b8bb-1a6112cca798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303032872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3303032872
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.4007428081
Short name T1040
Test name
Test status
Simulation time 11717824 ps
CPU time 0.76 seconds
Started Mar 16 12:24:35 PM PDT 24
Finished Mar 16 12:24:36 PM PDT 24
Peak memory 205116 kb
Host smart-c270f6ca-b3df-4a8c-acea-22019e395aa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007428081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.4007428081
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2952948969
Short name T408
Test name
Test status
Simulation time 90236905 ps
CPU time 5.16 seconds
Started Mar 16 12:24:39 PM PDT 24
Finished Mar 16 12:24:44 PM PDT 24
Peak memory 214224 kb
Host smart-77cc26f9-66c1-4dab-90e4-a0df15b88af8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2952948969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2952948969
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1400137932
Short name T23
Test name
Test status
Simulation time 73460275 ps
CPU time 3.24 seconds
Started Mar 16 12:24:48 PM PDT 24
Finished Mar 16 12:24:51 PM PDT 24
Peak memory 216168 kb
Host smart-5fd330d2-a6c2-46f3-9c8c-fec850c34546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400137932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1400137932
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1142943728
Short name T989
Test name
Test status
Simulation time 1437006007 ps
CPU time 13.84 seconds
Started Mar 16 12:24:34 PM PDT 24
Finished Mar 16 12:24:49 PM PDT 24
Peak memory 208324 kb
Host smart-a2dce406-5881-4cb2-b093-ca46c887a12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142943728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1142943728
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.4033603382
Short name T916
Test name
Test status
Simulation time 260807041 ps
CPU time 3.77 seconds
Started Mar 16 12:24:33 PM PDT 24
Finished Mar 16 12:24:36 PM PDT 24
Peak memory 210176 kb
Host smart-1656801c-6561-4776-adbc-1731cb2ec66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033603382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4033603382
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1411405677
Short name T974
Test name
Test status
Simulation time 1665417308 ps
CPU time 5.12 seconds
Started Mar 16 12:24:35 PM PDT 24
Finished Mar 16 12:24:41 PM PDT 24
Peak memory 207808 kb
Host smart-2d7cef54-1d63-4d22-b0d5-49e6b8a91dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411405677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1411405677
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.563108192
Short name T936
Test name
Test status
Simulation time 80856481 ps
CPU time 3.22 seconds
Started Mar 16 12:24:28 PM PDT 24
Finished Mar 16 12:24:33 PM PDT 24
Peak memory 208396 kb
Host smart-ab37a63b-956b-4a01-af53-a921323436a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563108192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.563108192
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.224501863
Short name T252
Test name
Test status
Simulation time 88209263 ps
CPU time 3.77 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:34 PM PDT 24
Peak memory 208680 kb
Host smart-5194b974-8e05-4d23-971e-0951b45bb65b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224501863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.224501863
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.181058902
Short name T771
Test name
Test status
Simulation time 21691427 ps
CPU time 1.74 seconds
Started Mar 16 12:24:33 PM PDT 24
Finished Mar 16 12:24:35 PM PDT 24
Peak memory 206836 kb
Host smart-cdfd30fc-0fe7-4a0b-9c5f-2cafc308199f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181058902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.181058902
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.414419570
Short name T852
Test name
Test status
Simulation time 470398222 ps
CPU time 3.48 seconds
Started Mar 16 12:24:31 PM PDT 24
Finished Mar 16 12:24:34 PM PDT 24
Peak memory 208792 kb
Host smart-a8731817-cbdc-4444-8224-a866638c011c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414419570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.414419570
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2692010213
Short name T602
Test name
Test status
Simulation time 137498042 ps
CPU time 3.36 seconds
Started Mar 16 12:24:35 PM PDT 24
Finished Mar 16 12:24:39 PM PDT 24
Peak memory 208160 kb
Host smart-473d10c2-645e-4e62-b239-84d910b1e719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692010213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2692010213
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.156917526
Short name T988
Test name
Test status
Simulation time 16301736088 ps
CPU time 99.7 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:26:10 PM PDT 24
Peak memory 222360 kb
Host smart-96c3b768-96a8-46ca-808e-7312b5c46068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156917526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.156917526
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3476151059
Short name T727
Test name
Test status
Simulation time 588651985 ps
CPU time 6.81 seconds
Started Mar 16 12:24:37 PM PDT 24
Finished Mar 16 12:24:44 PM PDT 24
Peak memory 208084 kb
Host smart-3e3ef045-c18b-42da-9b38-f1362c03af32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476151059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3476151059
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3179612867
Short name T910
Test name
Test status
Simulation time 7230030141 ps
CPU time 18.53 seconds
Started Mar 16 12:24:28 PM PDT 24
Finished Mar 16 12:24:48 PM PDT 24
Peak memory 221664 kb
Host smart-4cb30ab6-54bb-4944-bc76-f65c53ef4388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179612867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3179612867
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.820104448
Short name T786
Test name
Test status
Simulation time 47801207 ps
CPU time 0.89 seconds
Started Mar 16 12:24:36 PM PDT 24
Finished Mar 16 12:24:37 PM PDT 24
Peak memory 205732 kb
Host smart-42be5a98-b5e4-4fff-9dd0-e7f08089c7fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820104448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.820104448
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1373687482
Short name T1021
Test name
Test status
Simulation time 2241556835 ps
CPU time 10.52 seconds
Started Mar 16 12:24:40 PM PDT 24
Finished Mar 16 12:24:51 PM PDT 24
Peak memory 214280 kb
Host smart-a07a0782-7ff7-4d10-8d85-8a7e416462d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1373687482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1373687482
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1318860468
Short name T909
Test name
Test status
Simulation time 99524118 ps
CPU time 4.28 seconds
Started Mar 16 12:24:39 PM PDT 24
Finished Mar 16 12:24:43 PM PDT 24
Peak memory 208452 kb
Host smart-c3bf0165-5af0-48aa-bd4c-570b24eb5f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318860468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1318860468
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3773176907
Short name T312
Test name
Test status
Simulation time 1135796283 ps
CPU time 6.47 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:54 PM PDT 24
Peak memory 214204 kb
Host smart-5b4587c2-acd4-4581-bda0-90b4e99dccf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773176907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3773176907
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2138742993
Short name T22
Test name
Test status
Simulation time 1466283673 ps
CPU time 13.81 seconds
Started Mar 16 12:24:36 PM PDT 24
Finished Mar 16 12:24:50 PM PDT 24
Peak memory 209108 kb
Host smart-a7b8dc95-e155-4661-bd66-9a267258d88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138742993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2138742993
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2952638660
Short name T861
Test name
Test status
Simulation time 257791159 ps
CPU time 4.08 seconds
Started Mar 16 12:24:39 PM PDT 24
Finished Mar 16 12:24:43 PM PDT 24
Peak memory 209732 kb
Host smart-e14c9531-f17f-43cd-8518-a0ccde210951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952638660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2952638660
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2372611867
Short name T626
Test name
Test status
Simulation time 88643675 ps
CPU time 4.26 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:34 PM PDT 24
Peak memory 220236 kb
Host smart-5c544282-44eb-4e4f-bb95-1c8baae72903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372611867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2372611867
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.685957721
Short name T180
Test name
Test status
Simulation time 1736457072 ps
CPU time 11.02 seconds
Started Mar 16 12:24:32 PM PDT 24
Finished Mar 16 12:24:43 PM PDT 24
Peak memory 218300 kb
Host smart-278e7349-04c2-4c23-9d10-0a2080789da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685957721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.685957721
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3495640177
Short name T796
Test name
Test status
Simulation time 68941670 ps
CPU time 2.3 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:49 PM PDT 24
Peak memory 206704 kb
Host smart-e3069343-2272-47fb-bda1-a30994aa6952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495640177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3495640177
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2365410255
Short name T637
Test name
Test status
Simulation time 376693594 ps
CPU time 6.75 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:24:48 PM PDT 24
Peak memory 208500 kb
Host smart-e0151419-39d5-4068-8b7a-8a003cae9195
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365410255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2365410255
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2554696366
Short name T691
Test name
Test status
Simulation time 368259136 ps
CPU time 4.85 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:35 PM PDT 24
Peak memory 208476 kb
Host smart-d1916830-5628-4830-8185-683f55eb0a7c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554696366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2554696366
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.366416147
Short name T1074
Test name
Test status
Simulation time 261409101 ps
CPU time 3.2 seconds
Started Mar 16 12:24:36 PM PDT 24
Finished Mar 16 12:24:39 PM PDT 24
Peak memory 208652 kb
Host smart-8e71de5f-2bfb-48ce-af9c-7ae591001b7c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366416147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.366416147
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3021389556
Short name T670
Test name
Test status
Simulation time 125670272 ps
CPU time 3.01 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:34 PM PDT 24
Peak memory 209132 kb
Host smart-2216f1e5-b605-428b-afdd-eec3c5c91a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021389556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3021389556
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2253952455
Short name T933
Test name
Test status
Simulation time 171559453 ps
CPU time 2.49 seconds
Started Mar 16 12:24:35 PM PDT 24
Finished Mar 16 12:24:38 PM PDT 24
Peak memory 207048 kb
Host smart-11adb840-c8dc-4201-ae4e-ef08c0bfe092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253952455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2253952455
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2977477866
Short name T756
Test name
Test status
Simulation time 249159339 ps
CPU time 10.28 seconds
Started Mar 16 12:24:36 PM PDT 24
Finished Mar 16 12:24:46 PM PDT 24
Peak memory 220344 kb
Host smart-67800037-755e-4dbd-a2fd-d861bede1a48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977477866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2977477866
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.120937819
Short name T27
Test name
Test status
Simulation time 138526500 ps
CPU time 4.38 seconds
Started Mar 16 12:24:35 PM PDT 24
Finished Mar 16 12:24:40 PM PDT 24
Peak memory 208244 kb
Host smart-b9708a9c-0357-4644-b7cf-53d719e8008a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120937819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.120937819
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3714035123
Short name T591
Test name
Test status
Simulation time 207536938 ps
CPU time 1.47 seconds
Started Mar 16 12:24:31 PM PDT 24
Finished Mar 16 12:24:33 PM PDT 24
Peak memory 209744 kb
Host smart-908b239c-85a7-45f0-bd3f-c1025df96307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714035123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3714035123
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2640826635
Short name T857
Test name
Test status
Simulation time 117044725 ps
CPU time 0.87 seconds
Started Mar 16 12:24:39 PM PDT 24
Finished Mar 16 12:24:40 PM PDT 24
Peak memory 205752 kb
Host smart-db260d9c-0986-44ae-858f-876733f69fbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640826635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2640826635
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.614437230
Short name T995
Test name
Test status
Simulation time 3892557420 ps
CPU time 19.53 seconds
Started Mar 16 12:24:43 PM PDT 24
Finished Mar 16 12:25:03 PM PDT 24
Peak memory 217384 kb
Host smart-e2189c60-c401-4217-b88c-80b2e574155e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614437230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.614437230
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3040409470
Short name T323
Test name
Test status
Simulation time 129047337 ps
CPU time 4.92 seconds
Started Mar 16 12:24:39 PM PDT 24
Finished Mar 16 12:24:44 PM PDT 24
Peak memory 219148 kb
Host smart-7bf73730-c54a-4c7c-b0f2-8fdc1939c8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040409470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3040409470
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3285427866
Short name T317
Test name
Test status
Simulation time 20998903910 ps
CPU time 58.33 seconds
Started Mar 16 12:24:40 PM PDT 24
Finished Mar 16 12:25:38 PM PDT 24
Peak memory 215500 kb
Host smart-d1d59f81-0cea-46d3-a407-5e190d15d0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285427866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3285427866
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.4083921717
Short name T214
Test name
Test status
Simulation time 281681301 ps
CPU time 3.77 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:34 PM PDT 24
Peak memory 220312 kb
Host smart-41bcdc50-dda5-4c50-8570-f38092afea28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083921717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.4083921717
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3534748729
Short name T377
Test name
Test status
Simulation time 195797487 ps
CPU time 3.36 seconds
Started Mar 16 12:24:31 PM PDT 24
Finished Mar 16 12:24:35 PM PDT 24
Peak memory 207464 kb
Host smart-57e6c93d-95ae-4f9e-a8f8-2b0b969ea5a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534748729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3534748729
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3375984771
Short name T1033
Test name
Test status
Simulation time 194560317 ps
CPU time 4.36 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:24:45 PM PDT 24
Peak memory 208356 kb
Host smart-0eca32ba-92d8-4951-ba58-1761e863a6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375984771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3375984771
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1750384612
Short name T767
Test name
Test status
Simulation time 143470210 ps
CPU time 4.2 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:52 PM PDT 24
Peak memory 207952 kb
Host smart-9fea27d0-09f8-41ce-9a8e-a7e73306c83a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750384612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1750384612
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1321179062
Short name T676
Test name
Test status
Simulation time 39526083 ps
CPU time 2.47 seconds
Started Mar 16 12:24:37 PM PDT 24
Finished Mar 16 12:24:39 PM PDT 24
Peak memory 208204 kb
Host smart-f0d2ca76-c3c3-418c-83e5-8fb3c150d94b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321179062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1321179062
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.3806162300
Short name T778
Test name
Test status
Simulation time 266455344 ps
CPU time 6.01 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:24:48 PM PDT 24
Peak memory 208884 kb
Host smart-542a674b-224d-4947-9611-4f9b5629d49a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806162300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.3806162300
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3115653348
Short name T868
Test name
Test status
Simulation time 296017376 ps
CPU time 4.25 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:24:35 PM PDT 24
Peak memory 218332 kb
Host smart-8c006118-dac2-4a07-869e-19bf3d6bd052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115653348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3115653348
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1378571418
Short name T1057
Test name
Test status
Simulation time 173169512 ps
CPU time 4.7 seconds
Started Mar 16 12:24:31 PM PDT 24
Finished Mar 16 12:24:35 PM PDT 24
Peak memory 208304 kb
Host smart-5cd950e8-e0a7-431e-a432-4ed8b32ec6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378571418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1378571418
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1477640961
Short name T964
Test name
Test status
Simulation time 27357003767 ps
CPU time 234.85 seconds
Started Mar 16 12:24:30 PM PDT 24
Finished Mar 16 12:28:26 PM PDT 24
Peak memory 217164 kb
Host smart-0f373ba8-56e0-42db-907e-df7c096986af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477640961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1477640961
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2083037128
Short name T913
Test name
Test status
Simulation time 260838361 ps
CPU time 9.8 seconds
Started Mar 16 12:24:36 PM PDT 24
Finished Mar 16 12:24:46 PM PDT 24
Peak memory 222336 kb
Host smart-1be53c66-8159-4103-ade2-30c11ec20114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083037128 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2083037128
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2199086506
Short name T398
Test name
Test status
Simulation time 188132582 ps
CPU time 4.38 seconds
Started Mar 16 12:24:39 PM PDT 24
Finished Mar 16 12:24:44 PM PDT 24
Peak memory 209388 kb
Host smart-2286e04d-3338-4d51-94a9-24c886c40250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199086506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2199086506
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2745458980
Short name T883
Test name
Test status
Simulation time 119967324 ps
CPU time 2.47 seconds
Started Mar 16 12:24:42 PM PDT 24
Finished Mar 16 12:24:44 PM PDT 24
Peak memory 210328 kb
Host smart-1b3a0dd6-ffa5-4f54-8996-46c20ca978ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745458980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2745458980
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.975607122
Short name T99
Test name
Test status
Simulation time 41008513 ps
CPU time 0.87 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:48 PM PDT 24
Peak memory 205768 kb
Host smart-b0603375-4614-45fb-a159-7960215fd9b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975607122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.975607122
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.71528324
Short name T1049
Test name
Test status
Simulation time 108166990 ps
CPU time 4.22 seconds
Started Mar 16 12:24:40 PM PDT 24
Finished Mar 16 12:24:44 PM PDT 24
Peak memory 214228 kb
Host smart-dff41822-148d-423d-ae7e-d527a83d5670
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=71528324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.71528324
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3112663488
Short name T30
Test name
Test status
Simulation time 303934545 ps
CPU time 2.26 seconds
Started Mar 16 12:24:40 PM PDT 24
Finished Mar 16 12:24:42 PM PDT 24
Peak memory 217260 kb
Host smart-6ec24c77-9592-4986-846d-51ca9c54bd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112663488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3112663488
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.557002823
Short name T269
Test name
Test status
Simulation time 135753572 ps
CPU time 5.17 seconds
Started Mar 16 12:24:42 PM PDT 24
Finished Mar 16 12:24:47 PM PDT 24
Peak memory 219708 kb
Host smart-cec9fa1e-1e59-4b35-a5dc-e1d901ae860f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557002823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.557002823
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.593408379
Short name T271
Test name
Test status
Simulation time 1180426621 ps
CPU time 36 seconds
Started Mar 16 12:24:49 PM PDT 24
Finished Mar 16 12:25:25 PM PDT 24
Peak memory 214144 kb
Host smart-2fe46794-0ec9-40f5-a9a5-791da52f328c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593408379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.593408379
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_random.934801132
Short name T227
Test name
Test status
Simulation time 275120809 ps
CPU time 7.98 seconds
Started Mar 16 12:24:49 PM PDT 24
Finished Mar 16 12:24:57 PM PDT 24
Peak memory 214236 kb
Host smart-4729fc95-fd36-473a-823d-093b1497c2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934801132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.934801132
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1930164724
Short name T983
Test name
Test status
Simulation time 259122912 ps
CPU time 3.22 seconds
Started Mar 16 12:24:45 PM PDT 24
Finished Mar 16 12:24:49 PM PDT 24
Peak memory 208268 kb
Host smart-a0365ef8-b472-4b4b-a7f8-c8a0d2b69595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930164724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1930164724
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.344806476
Short name T586
Test name
Test status
Simulation time 261208612 ps
CPU time 2.88 seconds
Started Mar 16 12:24:44 PM PDT 24
Finished Mar 16 12:24:47 PM PDT 24
Peak memory 206796 kb
Host smart-e24a4a11-5b52-40e5-a873-c01446c95071
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344806476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.344806476
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1346679454
Short name T595
Test name
Test status
Simulation time 77781697 ps
CPU time 3.51 seconds
Started Mar 16 12:24:36 PM PDT 24
Finished Mar 16 12:24:40 PM PDT 24
Peak memory 208192 kb
Host smart-3dbe4092-0f0c-4f2b-894f-89fdccf6047b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346679454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1346679454
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.604181215
Short name T594
Test name
Test status
Simulation time 51637238 ps
CPU time 2.91 seconds
Started Mar 16 12:24:49 PM PDT 24
Finished Mar 16 12:24:52 PM PDT 24
Peak memory 206856 kb
Host smart-5acced6f-d182-4859-b566-9e6a40bea85a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604181215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.604181215
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.2636039580
Short name T750
Test name
Test status
Simulation time 171336568 ps
CPU time 4.82 seconds
Started Mar 16 12:24:45 PM PDT 24
Finished Mar 16 12:24:50 PM PDT 24
Peak memory 208064 kb
Host smart-8fa37196-6a0f-45bc-bdfc-bcafee4cbf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636039580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.2636039580
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.4086940870
Short name T862
Test name
Test status
Simulation time 2071196963 ps
CPU time 16.4 seconds
Started Mar 16 12:24:42 PM PDT 24
Finished Mar 16 12:24:58 PM PDT 24
Peak memory 208356 kb
Host smart-8476e296-f92b-405a-9e0a-c70e5e4433f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086940870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.4086940870
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.4182166910
Short name T957
Test name
Test status
Simulation time 13055433526 ps
CPU time 141.91 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:27:03 PM PDT 24
Peak memory 220268 kb
Host smart-101bf8ce-b977-462a-bdf7-5740700a0e8e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182166910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4182166910
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2283019651
Short name T1067
Test name
Test status
Simulation time 918738703 ps
CPU time 5.36 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:53 PM PDT 24
Peak memory 209640 kb
Host smart-5a9b4fd7-1b4c-4fed-97d6-9d9648fd9baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283019651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2283019651
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3520120880
Short name T863
Test name
Test status
Simulation time 91284960 ps
CPU time 2.27 seconds
Started Mar 16 12:24:37 PM PDT 24
Finished Mar 16 12:24:39 PM PDT 24
Peak memory 210052 kb
Host smart-c350fa1c-e65f-4e71-9f3e-2a07822a692e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520120880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3520120880
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2120233109
Short name T645
Test name
Test status
Simulation time 36419915 ps
CPU time 0.81 seconds
Started Mar 16 12:24:40 PM PDT 24
Finished Mar 16 12:24:41 PM PDT 24
Peak memory 205816 kb
Host smart-a1d22a25-c9ea-40aa-ae56-a3c82dccc4ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120233109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2120233109
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1331431868
Short name T414
Test name
Test status
Simulation time 136410788 ps
CPU time 7.69 seconds
Started Mar 16 12:24:38 PM PDT 24
Finished Mar 16 12:24:45 PM PDT 24
Peak memory 214912 kb
Host smart-64e0233b-9692-4191-88af-9b03a60d2e3c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1331431868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1331431868
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.4056706567
Short name T9
Test name
Test status
Simulation time 287323045 ps
CPU time 4.53 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:52 PM PDT 24
Peak memory 209900 kb
Host smart-17ed8f15-f134-46df-89dc-ae536d9f1154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056706567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.4056706567
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2678681153
Short name T640
Test name
Test status
Simulation time 30052299 ps
CPU time 1.5 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:24:43 PM PDT 24
Peak memory 208772 kb
Host smart-6de907d1-4a34-4ecb-856a-8e9fec30f369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678681153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2678681153
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.914384909
Short name T962
Test name
Test status
Simulation time 60472902 ps
CPU time 3.57 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:51 PM PDT 24
Peak memory 218152 kb
Host smart-3b834fed-1556-4d7c-a5d4-2e22fffe1c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914384909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.914384909
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2548484226
Short name T828
Test name
Test status
Simulation time 1430194341 ps
CPU time 5.24 seconds
Started Mar 16 12:24:38 PM PDT 24
Finished Mar 16 12:24:44 PM PDT 24
Peak memory 220296 kb
Host smart-9ef504b5-a863-467c-94ba-acf856b51f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548484226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2548484226
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.141833721
Short name T904
Test name
Test status
Simulation time 876987515 ps
CPU time 17.88 seconds
Started Mar 16 12:24:42 PM PDT 24
Finished Mar 16 12:24:59 PM PDT 24
Peak memory 208440 kb
Host smart-89ec4c0d-6de2-45e0-9231-3a52cc2aeb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141833721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.141833721
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3346376014
Short name T1010
Test name
Test status
Simulation time 175167337 ps
CPU time 3.09 seconds
Started Mar 16 12:24:40 PM PDT 24
Finished Mar 16 12:24:43 PM PDT 24
Peak memory 206764 kb
Host smart-420af678-ac07-4921-bd97-6b1bb1744078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346376014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3346376014
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1730868394
Short name T1002
Test name
Test status
Simulation time 6609499160 ps
CPU time 40.72 seconds
Started Mar 16 12:24:42 PM PDT 24
Finished Mar 16 12:25:23 PM PDT 24
Peak memory 209016 kb
Host smart-7204508c-4872-4614-82b6-8e19b28ee18d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730868394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1730868394
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2905892226
Short name T772
Test name
Test status
Simulation time 814461444 ps
CPU time 9.26 seconds
Started Mar 16 12:24:40 PM PDT 24
Finished Mar 16 12:24:50 PM PDT 24
Peak memory 208612 kb
Host smart-99c21829-5a99-4f2e-9092-c713ca9eae51
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905892226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2905892226
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1989740635
Short name T1042
Test name
Test status
Simulation time 24025417 ps
CPU time 1.8 seconds
Started Mar 16 12:24:40 PM PDT 24
Finished Mar 16 12:24:41 PM PDT 24
Peak memory 206928 kb
Host smart-ee8a09a5-09bf-4b49-b472-b988b30a0541
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989740635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1989740635
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3944502437
Short name T753
Test name
Test status
Simulation time 1439091213 ps
CPU time 7.58 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:24:49 PM PDT 24
Peak memory 209224 kb
Host smart-5ff43f9c-31a3-44b2-9098-967af76b09ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944502437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3944502437
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3293314066
Short name T614
Test name
Test status
Simulation time 84336838 ps
CPU time 2.8 seconds
Started Mar 16 12:24:40 PM PDT 24
Finished Mar 16 12:24:43 PM PDT 24
Peak memory 208624 kb
Host smart-068b2a05-8f63-4dc2-a24c-fba2846ccff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293314066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3293314066
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.672920355
Short name T49
Test name
Test status
Simulation time 896730613 ps
CPU time 8.87 seconds
Started Mar 16 12:24:39 PM PDT 24
Finished Mar 16 12:24:48 PM PDT 24
Peak memory 222424 kb
Host smart-2584d30d-6a23-41be-ad30-85ec15fde5da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672920355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.672920355
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1909816182
Short name T104
Test name
Test status
Simulation time 253444004 ps
CPU time 2.67 seconds
Started Mar 16 12:24:49 PM PDT 24
Finished Mar 16 12:24:52 PM PDT 24
Peak memory 214368 kb
Host smart-e1b02197-0b44-46e4-a005-119eb2c4a326
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909816182 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1909816182
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1008924296
Short name T823
Test name
Test status
Simulation time 253652354 ps
CPU time 4.16 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:52 PM PDT 24
Peak memory 207396 kb
Host smart-10bcfaae-6e0e-4084-b4a0-25f203f7f4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008924296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1008924296
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.510841843
Short name T181
Test name
Test status
Simulation time 303144546 ps
CPU time 2.71 seconds
Started Mar 16 12:24:38 PM PDT 24
Finished Mar 16 12:24:41 PM PDT 24
Peak memory 210148 kb
Host smart-06432ee9-432c-4528-a50c-7bcb00630568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510841843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.510841843
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.4274772363
Short name T997
Test name
Test status
Simulation time 31515241 ps
CPU time 0.7 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:24:42 PM PDT 24
Peak memory 205828 kb
Host smart-8dcedd85-de99-441b-8b84-e99192c09806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274772363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.4274772363
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.97113679
Short name T1034
Test name
Test status
Simulation time 1467232246 ps
CPU time 15.55 seconds
Started Mar 16 12:24:46 PM PDT 24
Finished Mar 16 12:25:01 PM PDT 24
Peak memory 218560 kb
Host smart-f7902469-521c-4555-8070-48cd76a62d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97113679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.97113679
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.228034578
Short name T86
Test name
Test status
Simulation time 700576370 ps
CPU time 8.05 seconds
Started Mar 16 12:24:42 PM PDT 24
Finished Mar 16 12:24:50 PM PDT 24
Peak memory 214248 kb
Host smart-ed8c0373-b945-479f-8dd6-d69812f9da93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228034578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.228034578
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1034434720
Short name T973
Test name
Test status
Simulation time 686784206 ps
CPU time 20.07 seconds
Started Mar 16 12:24:42 PM PDT 24
Finished Mar 16 12:25:02 PM PDT 24
Peak memory 214172 kb
Host smart-81202dec-4d3f-4afe-b6c2-8ada6be63908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034434720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1034434720
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.128248655
Short name T209
Test name
Test status
Simulation time 136752739 ps
CPU time 3.5 seconds
Started Mar 16 12:24:46 PM PDT 24
Finished Mar 16 12:24:49 PM PDT 24
Peak memory 219928 kb
Host smart-920c154f-1d3d-4412-9f87-c06bbb07f5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128248655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.128248655
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2695403060
Short name T218
Test name
Test status
Simulation time 190745413 ps
CPU time 3.52 seconds
Started Mar 16 12:24:43 PM PDT 24
Finished Mar 16 12:24:46 PM PDT 24
Peak memory 209096 kb
Host smart-5d770769-aebb-4564-a047-a3ff4db6bf37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695403060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2695403060
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3054929889
Short name T225
Test name
Test status
Simulation time 44834216 ps
CPU time 2.39 seconds
Started Mar 16 12:24:42 PM PDT 24
Finished Mar 16 12:24:44 PM PDT 24
Peak memory 206648 kb
Host smart-f5393dee-30b8-4170-8b4f-093a700f384f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054929889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3054929889
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1304895291
Short name T191
Test name
Test status
Simulation time 4626604605 ps
CPU time 46.66 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:25:28 PM PDT 24
Peak memory 209040 kb
Host smart-c844c3ee-5d2f-45ac-8820-ebec5975c1bf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304895291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1304895291
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2423104545
Short name T348
Test name
Test status
Simulation time 339311468 ps
CPU time 8.11 seconds
Started Mar 16 12:24:36 PM PDT 24
Finished Mar 16 12:24:45 PM PDT 24
Peak memory 208440 kb
Host smart-8d3ba4ec-2f4c-4828-b872-703d8267f478
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423104545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2423104545
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2228430843
Short name T736
Test name
Test status
Simulation time 125228496 ps
CPU time 5.14 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:24:47 PM PDT 24
Peak memory 208596 kb
Host smart-52c3fe32-66d5-43d2-bf3e-786f5dd44c7f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228430843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2228430843
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1360470420
Short name T401
Test name
Test status
Simulation time 41291361 ps
CPU time 2.08 seconds
Started Mar 16 12:24:43 PM PDT 24
Finished Mar 16 12:24:45 PM PDT 24
Peak memory 210016 kb
Host smart-b0714a8e-edf0-4641-9c1f-c2e94695f1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360470420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1360470420
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.4238872547
Short name T669
Test name
Test status
Simulation time 125145789 ps
CPU time 2.44 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:50 PM PDT 24
Peak memory 206908 kb
Host smart-2a716402-bd4f-4592-b72c-95487d241a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4238872547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.4238872547
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3921526908
Short name T243
Test name
Test status
Simulation time 224122594 ps
CPU time 5.85 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:24:47 PM PDT 24
Peak memory 209792 kb
Host smart-69098241-7a9f-42a6-8db5-76453b3a4e76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921526908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3921526908
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1416524853
Short name T797
Test name
Test status
Simulation time 2245688570 ps
CPU time 8.79 seconds
Started Mar 16 12:24:44 PM PDT 24
Finished Mar 16 12:24:53 PM PDT 24
Peak memory 222696 kb
Host smart-dfb138ba-d580-426e-96e5-d4c7067f9c25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416524853 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1416524853
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1792251734
Short name T220
Test name
Test status
Simulation time 103730337 ps
CPU time 3.31 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:50 PM PDT 24
Peak memory 207872 kb
Host smart-1184e540-487d-473f-8b33-6303955e316a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792251734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1792251734
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1600090382
Short name T942
Test name
Test status
Simulation time 939468377 ps
CPU time 8.71 seconds
Started Mar 16 12:26:15 PM PDT 24
Finished Mar 16 12:26:24 PM PDT 24
Peak memory 210792 kb
Host smart-80cfe1df-9f92-4757-ac13-9606094cb3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600090382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1600090382
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3473416670
Short name T920
Test name
Test status
Simulation time 14690362 ps
CPU time 0.79 seconds
Started Mar 16 12:24:40 PM PDT 24
Finished Mar 16 12:24:41 PM PDT 24
Peak memory 205764 kb
Host smart-b439180c-51dd-49ec-a075-9bfc11159d7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473416670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3473416670
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3193574319
Short name T290
Test name
Test status
Simulation time 28495352 ps
CPU time 2.28 seconds
Started Mar 16 12:24:40 PM PDT 24
Finished Mar 16 12:24:42 PM PDT 24
Peak memory 214148 kb
Host smart-8913b841-4255-4879-a5a5-692252a5cfe9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3193574319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3193574319
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.230398729
Short name T1026
Test name
Test status
Simulation time 75201454 ps
CPU time 3.61 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:51 PM PDT 24
Peak memory 221660 kb
Host smart-b27808c9-2c7f-454a-a167-8341d654ba6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230398729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.230398729
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3574722794
Short name T695
Test name
Test status
Simulation time 570618403 ps
CPU time 15.01 seconds
Started Mar 16 12:24:45 PM PDT 24
Finished Mar 16 12:25:00 PM PDT 24
Peak memory 209632 kb
Host smart-a1863f31-5d65-4510-8bb8-5e46c4b1153d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574722794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3574722794
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.633971453
Short name T1011
Test name
Test status
Simulation time 363153435 ps
CPU time 3.31 seconds
Started Mar 16 12:24:43 PM PDT 24
Finished Mar 16 12:24:46 PM PDT 24
Peak memory 208940 kb
Host smart-5dd2974f-2968-400f-bd0f-0cefc1d64f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633971453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.633971453
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2080852392
Short name T36
Test name
Test status
Simulation time 153353000 ps
CPU time 5.52 seconds
Started Mar 16 12:26:12 PM PDT 24
Finished Mar 16 12:26:18 PM PDT 24
Peak memory 214036 kb
Host smart-67f99513-6e3d-4f0f-bcdd-16467857e7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080852392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2080852392
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3069805630
Short name T210
Test name
Test status
Simulation time 210676509 ps
CPU time 2.37 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:24:43 PM PDT 24
Peak memory 209100 kb
Host smart-cf4c8fe7-80d4-42ff-8acf-8095a58f255f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069805630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3069805630
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3813548869
Short name T890
Test name
Test status
Simulation time 68773445 ps
CPU time 4.07 seconds
Started Mar 16 12:24:43 PM PDT 24
Finished Mar 16 12:24:47 PM PDT 24
Peak memory 218368 kb
Host smart-882482e0-2f27-4746-9f4f-938e410d35c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813548869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3813548869
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1656138801
Short name T773
Test name
Test status
Simulation time 1755619162 ps
CPU time 7.09 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:24:48 PM PDT 24
Peak memory 206756 kb
Host smart-c8e7dd4f-e9c2-4ab0-8d0e-575e351509a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656138801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1656138801
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1034407469
Short name T698
Test name
Test status
Simulation time 34179982 ps
CPU time 2.5 seconds
Started Mar 16 12:24:42 PM PDT 24
Finished Mar 16 12:24:45 PM PDT 24
Peak memory 206996 kb
Host smart-ca00bcd5-2020-4e5b-b648-b63d81d9465b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034407469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1034407469
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1353656034
Short name T648
Test name
Test status
Simulation time 567318050 ps
CPU time 9.13 seconds
Started Mar 16 12:24:44 PM PDT 24
Finished Mar 16 12:24:53 PM PDT 24
Peak memory 208236 kb
Host smart-b811e4b7-efd7-487c-813b-e00575269b40
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353656034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1353656034
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2909196534
Short name T858
Test name
Test status
Simulation time 2295345338 ps
CPU time 74.14 seconds
Started Mar 16 12:24:46 PM PDT 24
Finished Mar 16 12:26:00 PM PDT 24
Peak memory 209000 kb
Host smart-ba43b94f-6230-49e8-83f4-cbc9b9f551ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909196534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2909196534
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1407141105
Short name T282
Test name
Test status
Simulation time 253819058 ps
CPU time 10.02 seconds
Started Mar 16 12:24:44 PM PDT 24
Finished Mar 16 12:24:54 PM PDT 24
Peak memory 207864 kb
Host smart-f3a28e33-b9dd-41d6-b070-5595335eda8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407141105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1407141105
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3443501318
Short name T395
Test name
Test status
Simulation time 124873306 ps
CPU time 2.52 seconds
Started Mar 16 12:24:42 PM PDT 24
Finished Mar 16 12:24:45 PM PDT 24
Peak memory 208400 kb
Host smart-c8554219-8cc0-4e04-95b0-851325a14489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443501318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3443501318
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1018344434
Short name T706
Test name
Test status
Simulation time 5087801148 ps
CPU time 62.44 seconds
Started Mar 16 12:24:44 PM PDT 24
Finished Mar 16 12:25:47 PM PDT 24
Peak memory 218196 kb
Host smart-31152e12-b16e-48d7-a3da-6f8f2d53ae46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018344434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1018344434
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3724271334
Short name T856
Test name
Test status
Simulation time 336514888 ps
CPU time 3.45 seconds
Started Mar 16 12:24:44 PM PDT 24
Finished Mar 16 12:24:47 PM PDT 24
Peak memory 210172 kb
Host smart-0786e1d2-d7af-400c-be5e-75160e512972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724271334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3724271334
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.438064709
Short name T662
Test name
Test status
Simulation time 65265019 ps
CPU time 0.79 seconds
Started Mar 16 12:23:32 PM PDT 24
Finished Mar 16 12:23:33 PM PDT 24
Peak memory 205684 kb
Host smart-066d4087-1267-433e-afb2-cce40f8f7d7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438064709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.438064709
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2943063666
Short name T285
Test name
Test status
Simulation time 10462697034 ps
CPU time 115.81 seconds
Started Mar 16 12:23:27 PM PDT 24
Finished Mar 16 12:25:23 PM PDT 24
Peak memory 215672 kb
Host smart-9914617b-9785-44f0-9099-840d55d984c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2943063666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2943063666
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2491479411
Short name T55
Test name
Test status
Simulation time 88671900 ps
CPU time 4.05 seconds
Started Mar 16 12:23:41 PM PDT 24
Finished Mar 16 12:23:46 PM PDT 24
Peak memory 208812 kb
Host smart-2493a451-4985-435a-a6c9-86d674bca995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491479411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2491479411
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1716821034
Short name T299
Test name
Test status
Simulation time 381267829 ps
CPU time 4.01 seconds
Started Mar 16 12:23:44 PM PDT 24
Finished Mar 16 12:23:49 PM PDT 24
Peak memory 222332 kb
Host smart-f3f78528-f04d-4892-a3e0-e5fb14804736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716821034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1716821034
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2160100419
Short name T59
Test name
Test status
Simulation time 158744671 ps
CPU time 2.94 seconds
Started Mar 16 12:23:33 PM PDT 24
Finished Mar 16 12:23:36 PM PDT 24
Peak memory 220096 kb
Host smart-7426c50f-8bf3-447d-9db9-bf14a48f6936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160100419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2160100419
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.4257048372
Short name T375
Test name
Test status
Simulation time 150108581 ps
CPU time 4.21 seconds
Started Mar 16 12:23:32 PM PDT 24
Finished Mar 16 12:23:37 PM PDT 24
Peak memory 218276 kb
Host smart-8d3256d5-d7ae-4e20-b8df-a6600c545881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257048372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.4257048372
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3292619849
Short name T105
Test name
Test status
Simulation time 926673820 ps
CPU time 20.83 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:24:00 PM PDT 24
Peak memory 242008 kb
Host smart-0bd9610e-5ae7-432d-b5df-154eec9f3bb4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292619849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3292619849
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.840419947
Short name T329
Test name
Test status
Simulation time 129210566 ps
CPU time 4.41 seconds
Started Mar 16 12:23:41 PM PDT 24
Finished Mar 16 12:23:46 PM PDT 24
Peak memory 208200 kb
Host smart-462b7a79-6fce-45c2-8cd9-914a1a38922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840419947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.840419947
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.178801272
Short name T730
Test name
Test status
Simulation time 57082910 ps
CPU time 2.87 seconds
Started Mar 16 12:23:26 PM PDT 24
Finished Mar 16 12:23:29 PM PDT 24
Peak memory 208524 kb
Host smart-b93a65d1-d8d2-40bb-907a-eaa2f0bb363d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178801272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.178801272
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.86046918
Short name T700
Test name
Test status
Simulation time 183005426 ps
CPU time 4.52 seconds
Started Mar 16 12:23:41 PM PDT 24
Finished Mar 16 12:23:45 PM PDT 24
Peak memory 206656 kb
Host smart-fb0a66bc-e884-402e-bb5d-578ca77bb85f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86046918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.86046918
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1524968615
Short name T880
Test name
Test status
Simulation time 280304168 ps
CPU time 3.52 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:23:42 PM PDT 24
Peak memory 207420 kb
Host smart-e154ed53-4fae-46bc-8bc6-55a1d2345ccd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524968615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1524968615
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1101854890
Short name T948
Test name
Test status
Simulation time 145193072 ps
CPU time 3.31 seconds
Started Mar 16 12:23:34 PM PDT 24
Finished Mar 16 12:23:37 PM PDT 24
Peak memory 220100 kb
Host smart-dab93b90-302b-4fe5-82a0-803703da246a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101854890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1101854890
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1890877576
Short name T835
Test name
Test status
Simulation time 37785340 ps
CPU time 2.32 seconds
Started Mar 16 12:23:28 PM PDT 24
Finished Mar 16 12:23:30 PM PDT 24
Peak memory 208332 kb
Host smart-fb1fda57-428d-4a7b-8abd-8cdcc127d71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890877576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1890877576
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1489914885
Short name T939
Test name
Test status
Simulation time 582475273 ps
CPU time 11.99 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:23:51 PM PDT 24
Peak memory 219824 kb
Host smart-da0689d8-8c0d-4f15-b925-50cf179cedf7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489914885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1489914885
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.160736550
Short name T110
Test name
Test status
Simulation time 125050776 ps
CPU time 5.1 seconds
Started Mar 16 12:23:33 PM PDT 24
Finished Mar 16 12:23:38 PM PDT 24
Peak memory 222516 kb
Host smart-57929adc-3b82-4d1d-8a92-da951e890e3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160736550 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.160736550
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2470593141
Short name T247
Test name
Test status
Simulation time 4800342437 ps
CPU time 36.36 seconds
Started Mar 16 12:23:36 PM PDT 24
Finished Mar 16 12:24:12 PM PDT 24
Peak memory 214276 kb
Host smart-cd8de4c5-8c70-4e12-9d60-af0eb9d57761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470593141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2470593141
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2330031995
Short name T584
Test name
Test status
Simulation time 57668744 ps
CPU time 0.85 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:24:42 PM PDT 24
Peak memory 205876 kb
Host smart-5ae2f4be-b60c-4a85-844a-4720d1c9bf49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330031995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2330031995
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.514663989
Short name T298
Test name
Test status
Simulation time 52439368 ps
CPU time 3.56 seconds
Started Mar 16 12:24:45 PM PDT 24
Finished Mar 16 12:24:48 PM PDT 24
Peak memory 215608 kb
Host smart-2413ffd9-2a6e-48b4-bbe2-4fe9108cd108
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=514663989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.514663989
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.639283209
Short name T754
Test name
Test status
Simulation time 939035758 ps
CPU time 9.31 seconds
Started Mar 16 12:24:42 PM PDT 24
Finished Mar 16 12:24:52 PM PDT 24
Peak memory 209432 kb
Host smart-9b8842b0-c0b6-49b0-b1ef-5bb2e6cc2408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639283209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.639283209
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3243574894
Short name T1066
Test name
Test status
Simulation time 571995347 ps
CPU time 3.92 seconds
Started Mar 16 12:24:46 PM PDT 24
Finished Mar 16 12:24:50 PM PDT 24
Peak memory 209528 kb
Host smart-a8fe3610-16ac-4fe1-bcdd-a38f4ca7c987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243574894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3243574894
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.363932058
Short name T366
Test name
Test status
Simulation time 140247772 ps
CPU time 2.3 seconds
Started Mar 16 12:25:51 PM PDT 24
Finished Mar 16 12:25:55 PM PDT 24
Peak memory 219256 kb
Host smart-2a0161f6-b5de-4eed-9c58-935539794310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363932058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.363932058
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2362305219
Short name T235
Test name
Test status
Simulation time 438391300 ps
CPU time 12.94 seconds
Started Mar 16 12:24:42 PM PDT 24
Finished Mar 16 12:24:55 PM PDT 24
Peak memory 214152 kb
Host smart-96bf529b-0ef6-42e4-a51c-92198dbf1088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362305219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2362305219
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1620549024
Short name T1023
Test name
Test status
Simulation time 222047806 ps
CPU time 2.98 seconds
Started Mar 16 12:24:53 PM PDT 24
Finished Mar 16 12:24:56 PM PDT 24
Peak memory 220432 kb
Host smart-23f99b22-ea40-435d-b335-4af58d5915be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620549024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1620549024
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2464074530
Short name T224
Test name
Test status
Simulation time 113280241 ps
CPU time 4.4 seconds
Started Mar 16 12:25:52 PM PDT 24
Finished Mar 16 12:25:58 PM PDT 24
Peak memory 207292 kb
Host smart-de4ae1fe-4f14-4c15-b253-48cfb3e430fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464074530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2464074530
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3469178799
Short name T712
Test name
Test status
Simulation time 37309254 ps
CPU time 2.52 seconds
Started Mar 16 12:24:45 PM PDT 24
Finished Mar 16 12:24:47 PM PDT 24
Peak memory 208600 kb
Host smart-ff3edcca-c9dd-4103-b355-2679bdb2979f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469178799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3469178799
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1793666935
Short name T600
Test name
Test status
Simulation time 178025975 ps
CPU time 5.16 seconds
Started Mar 16 12:24:44 PM PDT 24
Finished Mar 16 12:24:49 PM PDT 24
Peak memory 208856 kb
Host smart-e1f545c3-ad66-4f2c-bc1e-2d4c6bbb2f57
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793666935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1793666935
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.140117202
Short name T832
Test name
Test status
Simulation time 448575322 ps
CPU time 6.79 seconds
Started Mar 16 12:24:44 PM PDT 24
Finished Mar 16 12:24:51 PM PDT 24
Peak memory 207960 kb
Host smart-9d7b977e-1da7-4ae3-9dff-c5183fedddc2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140117202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.140117202
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.926389038
Short name T639
Test name
Test status
Simulation time 279989695 ps
CPU time 3.12 seconds
Started Mar 16 12:24:41 PM PDT 24
Finished Mar 16 12:24:44 PM PDT 24
Peak memory 206648 kb
Host smart-fbfa1892-6106-48bc-bcf1-a13c49f379e8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926389038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.926389038
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.417376259
Short name T845
Test name
Test status
Simulation time 2223159254 ps
CPU time 12.04 seconds
Started Mar 16 12:26:02 PM PDT 24
Finished Mar 16 12:26:14 PM PDT 24
Peak memory 208416 kb
Host smart-efc62474-9d19-4fef-9761-730c7be583d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417376259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.417376259
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.4039499112
Short name T680
Test name
Test status
Simulation time 54395289 ps
CPU time 2.68 seconds
Started Mar 16 12:24:46 PM PDT 24
Finished Mar 16 12:24:48 PM PDT 24
Peak memory 206732 kb
Host smart-c55fa599-e2a8-4aab-a9aa-11bf847d9fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039499112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.4039499112
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.787476535
Short name T268
Test name
Test status
Simulation time 178755318761 ps
CPU time 421.18 seconds
Started Mar 16 12:24:46 PM PDT 24
Finished Mar 16 12:31:47 PM PDT 24
Peak memory 222400 kb
Host smart-735efcc6-3902-4383-b550-58f500613190
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787476535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.787476535
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.705249947
Short name T810
Test name
Test status
Simulation time 256959092 ps
CPU time 10.41 seconds
Started Mar 16 12:24:46 PM PDT 24
Finished Mar 16 12:24:56 PM PDT 24
Peak memory 222452 kb
Host smart-6b241efb-a0f7-4498-bb02-4263affd5af8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705249947 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.705249947
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3423469642
Short name T589
Test name
Test status
Simulation time 768912154 ps
CPU time 5.53 seconds
Started Mar 16 12:24:42 PM PDT 24
Finished Mar 16 12:24:47 PM PDT 24
Peak memory 218480 kb
Host smart-6de176e6-deab-4cb3-9cf3-a93096670e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423469642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3423469642
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2405595532
Short name T908
Test name
Test status
Simulation time 72294822 ps
CPU time 2.83 seconds
Started Mar 16 12:26:07 PM PDT 24
Finished Mar 16 12:26:10 PM PDT 24
Peak memory 210108 kb
Host smart-c37ae374-c3cf-45db-9dd9-1cdafd298842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405595532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2405595532
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.466411993
Short name T701
Test name
Test status
Simulation time 23236375 ps
CPU time 0.74 seconds
Started Mar 16 12:24:53 PM PDT 24
Finished Mar 16 12:24:54 PM PDT 24
Peak memory 205800 kb
Host smart-7cc3ce31-23b2-423f-ac58-d3fb0d978372
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466411993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.466411993
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.608680376
Short name T718
Test name
Test status
Simulation time 40286594 ps
CPU time 2.18 seconds
Started Mar 16 12:25:53 PM PDT 24
Finished Mar 16 12:25:56 PM PDT 24
Peak memory 216812 kb
Host smart-96ce5b50-37e2-4569-90aa-71c6f299a6e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608680376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.608680376
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.373711806
Short name T853
Test name
Test status
Simulation time 62607863 ps
CPU time 2.61 seconds
Started Mar 16 12:26:02 PM PDT 24
Finished Mar 16 12:26:05 PM PDT 24
Peak memory 208500 kb
Host smart-db10ac36-1829-4aea-bfb2-efa9646dc555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373711806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.373711806
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3788370010
Short name T263
Test name
Test status
Simulation time 215955569 ps
CPU time 5.35 seconds
Started Mar 16 12:24:53 PM PDT 24
Finished Mar 16 12:24:59 PM PDT 24
Peak memory 219896 kb
Host smart-08325d89-4e8d-41a1-9110-d2c00738fc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788370010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3788370010
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1656515140
Short name T363
Test name
Test status
Simulation time 701470715 ps
CPU time 14.71 seconds
Started Mar 16 12:25:52 PM PDT 24
Finished Mar 16 12:26:09 PM PDT 24
Peak memory 221452 kb
Host smart-e9278b5d-26eb-4c12-92de-616c958a5479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656515140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1656515140
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.4284161352
Short name T625
Test name
Test status
Simulation time 291442142 ps
CPU time 3.66 seconds
Started Mar 16 12:26:16 PM PDT 24
Finished Mar 16 12:26:19 PM PDT 24
Peak memory 206304 kb
Host smart-805e6ece-c166-46ed-bdec-9d660a85f590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284161352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.4284161352
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1134450828
Short name T1046
Test name
Test status
Simulation time 75418528 ps
CPU time 4.23 seconds
Started Mar 16 12:24:43 PM PDT 24
Finished Mar 16 12:24:48 PM PDT 24
Peak memory 214200 kb
Host smart-6b951489-26fc-49c2-9e1d-7e7c4d3171a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1134450828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1134450828
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1591104053
Short name T929
Test name
Test status
Simulation time 97622783 ps
CPU time 2.79 seconds
Started Mar 16 12:25:54 PM PDT 24
Finished Mar 16 12:25:57 PM PDT 24
Peak memory 206304 kb
Host smart-dd4b4385-6c6a-45f6-a19b-61db841385c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591104053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1591104053
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2419410909
Short name T239
Test name
Test status
Simulation time 1156450518 ps
CPU time 27 seconds
Started Mar 16 12:24:49 PM PDT 24
Finished Mar 16 12:25:16 PM PDT 24
Peak memory 208400 kb
Host smart-e747cc66-d350-4810-a73c-796036b14497
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419410909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2419410909
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1017510588
Short name T813
Test name
Test status
Simulation time 1529613025 ps
CPU time 19.08 seconds
Started Mar 16 12:24:43 PM PDT 24
Finished Mar 16 12:25:02 PM PDT 24
Peak memory 207848 kb
Host smart-a3003ebb-4884-4f83-8d10-4d80f06be2bd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017510588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1017510588
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.1617582871
Short name T1053
Test name
Test status
Simulation time 299322267 ps
CPU time 6.37 seconds
Started Mar 16 12:26:09 PM PDT 24
Finished Mar 16 12:26:15 PM PDT 24
Peak memory 206584 kb
Host smart-afc42a03-1c47-4dd6-9530-4f5bb6915413
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617582871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.1617582871
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.314593740
Short name T760
Test name
Test status
Simulation time 695588536 ps
CPU time 5.39 seconds
Started Mar 16 12:25:53 PM PDT 24
Finished Mar 16 12:25:59 PM PDT 24
Peak memory 207560 kb
Host smart-7ae84395-e142-4d28-af96-a9033aaad706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314593740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.314593740
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3069313453
Short name T926
Test name
Test status
Simulation time 120119293 ps
CPU time 2.68 seconds
Started Mar 16 12:24:49 PM PDT 24
Finished Mar 16 12:24:52 PM PDT 24
Peak memory 208540 kb
Host smart-76f53fb5-ed86-4524-82de-e1bac3d13e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069313453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3069313453
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1480848726
Short name T732
Test name
Test status
Simulation time 295696891 ps
CPU time 12.45 seconds
Started Mar 16 12:24:53 PM PDT 24
Finished Mar 16 12:25:05 PM PDT 24
Peak memory 222648 kb
Host smart-99611a7a-30e3-4eaa-8e7c-4fe54f9a0cf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480848726 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1480848726
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.29452758
Short name T361
Test name
Test status
Simulation time 587436847 ps
CPU time 4.75 seconds
Started Mar 16 12:25:52 PM PDT 24
Finished Mar 16 12:25:58 PM PDT 24
Peak memory 212772 kb
Host smart-4080656b-d83c-474a-8eee-9d4c634989a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29452758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.29452758
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3547382032
Short name T912
Test name
Test status
Simulation time 192571556 ps
CPU time 3.58 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:51 PM PDT 24
Peak memory 210392 kb
Host smart-b10be3b6-6fe6-4815-9b44-d02345bb245d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547382032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3547382032
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3691584209
Short name T990
Test name
Test status
Simulation time 45897607 ps
CPU time 0.71 seconds
Started Mar 16 12:24:52 PM PDT 24
Finished Mar 16 12:24:53 PM PDT 24
Peak memory 205768 kb
Host smart-90d9314d-f9a9-4629-8f57-baa36f94da6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691584209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3691584209
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.4069954434
Short name T125
Test name
Test status
Simulation time 65015004 ps
CPU time 4.23 seconds
Started Mar 16 12:24:50 PM PDT 24
Finished Mar 16 12:24:54 PM PDT 24
Peak memory 214220 kb
Host smart-d4334232-9980-499c-bf43-dc69d3bfa3b9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4069954434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.4069954434
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3719232025
Short name T341
Test name
Test status
Simulation time 281362804 ps
CPU time 3.38 seconds
Started Mar 16 12:24:55 PM PDT 24
Finished Mar 16 12:24:58 PM PDT 24
Peak memory 208504 kb
Host smart-4b237bb3-d7df-434d-b6ce-6fc1c9fe5529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719232025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3719232025
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.418204557
Short name T902
Test name
Test status
Simulation time 114844354 ps
CPU time 4.46 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:51 PM PDT 24
Peak memory 214144 kb
Host smart-07e9e07b-7afa-42c3-ad3f-5b1c83dfcc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418204557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.418204557
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3325625537
Short name T261
Test name
Test status
Simulation time 734683399 ps
CPU time 8.11 seconds
Started Mar 16 12:24:50 PM PDT 24
Finished Mar 16 12:24:58 PM PDT 24
Peak memory 210840 kb
Host smart-2692ab56-9d6f-4df7-9ca3-e23e6397e677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325625537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3325625537
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3130633566
Short name T7
Test name
Test status
Simulation time 108214424 ps
CPU time 3.24 seconds
Started Mar 16 12:24:51 PM PDT 24
Finished Mar 16 12:24:54 PM PDT 24
Peak memory 219664 kb
Host smart-f81c0661-bfab-46fc-ba4c-04cb7b9edd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130633566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3130633566
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3615529747
Short name T255
Test name
Test status
Simulation time 328430889 ps
CPU time 9.05 seconds
Started Mar 16 12:24:50 PM PDT 24
Finished Mar 16 12:24:59 PM PDT 24
Peak memory 214212 kb
Host smart-1b664d2b-e3c2-442e-81c2-66dbf84eb672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615529747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3615529747
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1494906939
Short name T967
Test name
Test status
Simulation time 203907595 ps
CPU time 3.8 seconds
Started Mar 16 12:24:51 PM PDT 24
Finished Mar 16 12:24:55 PM PDT 24
Peak memory 208156 kb
Host smart-14738c4b-ad87-4a0b-9bf0-dd62ba47111a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494906939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1494906939
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1767797510
Short name T192
Test name
Test status
Simulation time 235101394 ps
CPU time 5.06 seconds
Started Mar 16 12:24:49 PM PDT 24
Finished Mar 16 12:24:54 PM PDT 24
Peak memory 206800 kb
Host smart-f8f4dbf8-3940-474a-9b08-dd88813fccf3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767797510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1767797510
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1314153647
Short name T109
Test name
Test status
Simulation time 151657161 ps
CPU time 1.96 seconds
Started Mar 16 12:24:50 PM PDT 24
Finished Mar 16 12:24:52 PM PDT 24
Peak memory 206712 kb
Host smart-b88ccf5a-599c-4f77-880d-f080f43ecb44
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314153647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1314153647
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2650276651
Short name T842
Test name
Test status
Simulation time 89558783 ps
CPU time 3.17 seconds
Started Mar 16 12:24:46 PM PDT 24
Finished Mar 16 12:24:49 PM PDT 24
Peak memory 206572 kb
Host smart-b609b533-5eb3-4cf5-978d-e0d0b0209688
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650276651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2650276651
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2423628155
Short name T1076
Test name
Test status
Simulation time 225952108 ps
CPU time 3.23 seconds
Started Mar 16 12:24:55 PM PDT 24
Finished Mar 16 12:24:58 PM PDT 24
Peak memory 207500 kb
Host smart-55cfa42f-c8c9-4806-bd2b-b353951df5ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423628155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2423628155
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1913031124
Short name T743
Test name
Test status
Simulation time 4340120212 ps
CPU time 25.71 seconds
Started Mar 16 12:25:53 PM PDT 24
Finished Mar 16 12:26:19 PM PDT 24
Peak memory 206324 kb
Host smart-55acf6bb-7c9f-49d4-ab29-9f667b97194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913031124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1913031124
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3746673003
Short name T765
Test name
Test status
Simulation time 1428181182 ps
CPU time 13.83 seconds
Started Mar 16 12:24:49 PM PDT 24
Finished Mar 16 12:25:02 PM PDT 24
Peak memory 214972 kb
Host smart-aeacb251-43d7-4f50-aaae-17868d2c9243
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746673003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3746673003
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.335799120
Short name T918
Test name
Test status
Simulation time 199769011 ps
CPU time 3.97 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:51 PM PDT 24
Peak memory 219720 kb
Host smart-f768d4dc-9bdc-45ea-8bf1-bdcdf74ead55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335799120 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.335799120
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.4159836218
Short name T258
Test name
Test status
Simulation time 223350782 ps
CPU time 3.05 seconds
Started Mar 16 12:24:50 PM PDT 24
Finished Mar 16 12:24:53 PM PDT 24
Peak memory 218172 kb
Host smart-2de6268b-9fb0-42ba-99ab-bfd1a20d3b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159836218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.4159836218
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.985577218
Short name T147
Test name
Test status
Simulation time 262027527 ps
CPU time 3.54 seconds
Started Mar 16 12:24:49 PM PDT 24
Finished Mar 16 12:24:53 PM PDT 24
Peak memory 210332 kb
Host smart-899279d6-a5d7-49fa-8674-fafe7c7b4396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985577218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.985577218
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2778272346
Short name T98
Test name
Test status
Simulation time 52194024 ps
CPU time 0.89 seconds
Started Mar 16 12:24:52 PM PDT 24
Finished Mar 16 12:24:53 PM PDT 24
Peak memory 205804 kb
Host smart-0a75a48d-028e-4639-ad1d-e523dff6bcfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778272346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2778272346
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.455907778
Short name T1058
Test name
Test status
Simulation time 1914685909 ps
CPU time 12.7 seconds
Started Mar 16 12:24:51 PM PDT 24
Finished Mar 16 12:25:03 PM PDT 24
Peak memory 215516 kb
Host smart-acf1221e-c16a-4ef9-8fa3-0d63bfc38fdd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=455907778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.455907778
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3346463785
Short name T31
Test name
Test status
Simulation time 122896240 ps
CPU time 2.79 seconds
Started Mar 16 12:24:50 PM PDT 24
Finished Mar 16 12:24:53 PM PDT 24
Peak memory 208264 kb
Host smart-1e24d727-2e30-48ee-bdeb-680cf240501f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346463785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3346463785
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1967689376
Short name T18
Test name
Test status
Simulation time 69231816 ps
CPU time 1.56 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:49 PM PDT 24
Peak memory 207340 kb
Host smart-20f7c103-f2f6-491c-b7cf-9593a032faa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967689376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1967689376
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3402871025
Short name T840
Test name
Test status
Simulation time 657949735 ps
CPU time 12.62 seconds
Started Mar 16 12:24:48 PM PDT 24
Finished Mar 16 12:25:01 PM PDT 24
Peak memory 214224 kb
Host smart-de00bb81-4cb5-40b3-abd4-180add54ff2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402871025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3402871025
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2359094757
Short name T304
Test name
Test status
Simulation time 954768336 ps
CPU time 7.91 seconds
Started Mar 16 12:24:47 PM PDT 24
Finished Mar 16 12:24:55 PM PDT 24
Peak memory 222372 kb
Host smart-335b2b00-662e-4adf-ba13-0e0871bc72ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2359094757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2359094757
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1601788989
Short name T262
Test name
Test status
Simulation time 1075995367 ps
CPU time 7.4 seconds
Started Mar 16 12:24:53 PM PDT 24
Finished Mar 16 12:25:00 PM PDT 24
Peak memory 214184 kb
Host smart-f01a0ab4-d0b3-4fb6-b751-a6768a2fdf79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601788989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1601788989
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1364575515
Short name T630
Test name
Test status
Simulation time 101503436 ps
CPU time 2.1 seconds
Started Mar 16 12:24:51 PM PDT 24
Finished Mar 16 12:24:53 PM PDT 24
Peak memory 208392 kb
Host smart-8e908426-baa1-4a66-b7be-9136d36d8965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364575515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1364575515
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1596732433
Short name T599
Test name
Test status
Simulation time 3603537775 ps
CPU time 19.24 seconds
Started Mar 16 12:24:50 PM PDT 24
Finished Mar 16 12:25:09 PM PDT 24
Peak memory 207828 kb
Host smart-442f83fe-9885-4ddd-92ca-fee250f824c0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596732433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1596732433
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.546954606
Short name T1063
Test name
Test status
Simulation time 199719513 ps
CPU time 2.68 seconds
Started Mar 16 12:24:50 PM PDT 24
Finished Mar 16 12:24:53 PM PDT 24
Peak memory 208776 kb
Host smart-6a9fa4e9-0737-4caa-a430-b01033b5ccd1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546954606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.546954606
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1878807706
Short name T891
Test name
Test status
Simulation time 304929511 ps
CPU time 2.59 seconds
Started Mar 16 12:24:48 PM PDT 24
Finished Mar 16 12:24:51 PM PDT 24
Peak memory 206672 kb
Host smart-bba83e31-f12d-44a6-b01c-e9dcf24b0e2d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878807706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1878807706
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2448810409
Short name T745
Test name
Test status
Simulation time 285169516 ps
CPU time 7.33 seconds
Started Mar 16 12:24:51 PM PDT 24
Finished Mar 16 12:24:58 PM PDT 24
Peak memory 207912 kb
Host smart-8476b3c3-6f73-4995-b10a-519f4d0a9c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448810409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2448810409
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.514538793
Short name T848
Test name
Test status
Simulation time 38200748 ps
CPU time 2.49 seconds
Started Mar 16 12:24:49 PM PDT 24
Finished Mar 16 12:24:52 PM PDT 24
Peak memory 206820 kb
Host smart-b31447c2-65d5-48d8-a3ce-2b1f75fb1839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514538793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.514538793
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.416202817
Short name T379
Test name
Test status
Simulation time 128193659 ps
CPU time 3.42 seconds
Started Mar 16 12:24:50 PM PDT 24
Finished Mar 16 12:24:54 PM PDT 24
Peak memory 207120 kb
Host smart-3bb9bf23-542e-4304-8bb8-d6cb63d0ad8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416202817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.416202817
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2931319409
Short name T603
Test name
Test status
Simulation time 330631044 ps
CPU time 2.49 seconds
Started Mar 16 12:24:51 PM PDT 24
Finished Mar 16 12:24:58 PM PDT 24
Peak memory 210296 kb
Host smart-3f7d9ada-a958-4bcd-bb35-45d54c8d5815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931319409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2931319409
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2419566737
Short name T801
Test name
Test status
Simulation time 121381038 ps
CPU time 0.77 seconds
Started Mar 16 12:25:12 PM PDT 24
Finished Mar 16 12:25:13 PM PDT 24
Peak memory 205780 kb
Host smart-539ad1af-92e9-4d2b-bb44-03166da398c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419566737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2419566737
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3344939130
Short name T39
Test name
Test status
Simulation time 544257640 ps
CPU time 10.82 seconds
Started Mar 16 12:24:55 PM PDT 24
Finished Mar 16 12:25:06 PM PDT 24
Peak memory 217600 kb
Host smart-46845ad7-4441-47ca-99d7-668fabda3f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344939130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3344939130
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3895850061
Short name T54
Test name
Test status
Simulation time 32571640 ps
CPU time 2.07 seconds
Started Mar 16 12:24:55 PM PDT 24
Finished Mar 16 12:24:57 PM PDT 24
Peak memory 208220 kb
Host smart-6aae3e23-f202-4c71-a1cb-35f47ebadb61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895850061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3895850061
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2135859833
Short name T272
Test name
Test status
Simulation time 42682317 ps
CPU time 2.8 seconds
Started Mar 16 12:24:53 PM PDT 24
Finished Mar 16 12:24:56 PM PDT 24
Peak memory 208660 kb
Host smart-b5e866ef-dcc3-48c2-8de8-9233e3126136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135859833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2135859833
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_random.1340241011
Short name T735
Test name
Test status
Simulation time 654167662 ps
CPU time 6 seconds
Started Mar 16 12:24:54 PM PDT 24
Finished Mar 16 12:25:00 PM PDT 24
Peak memory 207376 kb
Host smart-71a673ca-087e-4900-bdbc-91b2c009687d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340241011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1340241011
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3731286081
Short name T256
Test name
Test status
Simulation time 192947276 ps
CPU time 2.76 seconds
Started Mar 16 12:24:55 PM PDT 24
Finished Mar 16 12:24:57 PM PDT 24
Peak memory 208436 kb
Host smart-6df22b3f-0bad-4000-b4cf-a7f3ff12496c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731286081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3731286081
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2697827332
Short name T859
Test name
Test status
Simulation time 141101778 ps
CPU time 4.41 seconds
Started Mar 16 12:24:53 PM PDT 24
Finished Mar 16 12:24:58 PM PDT 24
Peak memory 206708 kb
Host smart-37adb099-98c0-4825-b889-ef367f58cf02
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697827332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2697827332
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.4065409977
Short name T697
Test name
Test status
Simulation time 73951983 ps
CPU time 2.63 seconds
Started Mar 16 12:25:10 PM PDT 24
Finished Mar 16 12:25:13 PM PDT 24
Peak memory 208428 kb
Host smart-c6ceb8d8-f70d-4991-88ee-2fccefabee98
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065409977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4065409977
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2723492001
Short name T396
Test name
Test status
Simulation time 35224344493 ps
CPU time 78.55 seconds
Started Mar 16 12:24:53 PM PDT 24
Finished Mar 16 12:26:12 PM PDT 24
Peak memory 208184 kb
Host smart-10727e83-cbce-4771-8a58-b1030ba65fe7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723492001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2723492001
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.499733003
Short name T844
Test name
Test status
Simulation time 252625079 ps
CPU time 3.26 seconds
Started Mar 16 12:24:52 PM PDT 24
Finished Mar 16 12:24:56 PM PDT 24
Peak memory 208840 kb
Host smart-35860fdf-103b-40a1-8c17-e6939cd69968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499733003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.499733003
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1651994479
Short name T1036
Test name
Test status
Simulation time 683958289 ps
CPU time 7.88 seconds
Started Mar 16 12:24:55 PM PDT 24
Finished Mar 16 12:25:03 PM PDT 24
Peak memory 208152 kb
Host smart-8d4e32de-b780-4af1-9248-80e751799be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651994479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1651994479
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3309092635
Short name T328
Test name
Test status
Simulation time 531739501 ps
CPU time 20.51 seconds
Started Mar 16 12:25:00 PM PDT 24
Finished Mar 16 12:25:20 PM PDT 24
Peak memory 214808 kb
Host smart-ba202c30-3a22-4dd2-94a4-54cbe58fa77d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309092635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3309092635
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3259231334
Short name T668
Test name
Test status
Simulation time 86414553 ps
CPU time 3.48 seconds
Started Mar 16 12:25:13 PM PDT 24
Finished Mar 16 12:25:16 PM PDT 24
Peak memory 218716 kb
Host smart-c7a44789-6315-49a7-94a3-ceb18ee1ead5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259231334 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3259231334
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.655993162
Short name T331
Test name
Test status
Simulation time 925721095 ps
CPU time 11.7 seconds
Started Mar 16 12:25:11 PM PDT 24
Finished Mar 16 12:25:23 PM PDT 24
Peak memory 209424 kb
Host smart-0a016930-40d5-4ae6-9074-1ae6542375b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655993162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.655993162
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1397913138
Short name T1014
Test name
Test status
Simulation time 139825476 ps
CPU time 3.35 seconds
Started Mar 16 12:25:18 PM PDT 24
Finished Mar 16 12:25:22 PM PDT 24
Peak memory 210540 kb
Host smart-1a90faa7-dc61-44e7-b1f8-e47c4a002d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397913138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1397913138
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.4162393441
Short name T641
Test name
Test status
Simulation time 148426873 ps
CPU time 0.89 seconds
Started Mar 16 12:25:12 PM PDT 24
Finished Mar 16 12:25:13 PM PDT 24
Peak memory 205692 kb
Host smart-9d96b898-5159-4576-8b20-4958b6686c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162393441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.4162393441
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2105973148
Short name T928
Test name
Test status
Simulation time 40726804 ps
CPU time 2.68 seconds
Started Mar 16 12:24:59 PM PDT 24
Finished Mar 16 12:25:02 PM PDT 24
Peak memory 209760 kb
Host smart-e36ec6cc-932d-4520-b9f2-33e1115d6fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105973148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2105973148
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3891908645
Short name T1006
Test name
Test status
Simulation time 389295048 ps
CPU time 7.26 seconds
Started Mar 16 12:25:00 PM PDT 24
Finished Mar 16 12:25:07 PM PDT 24
Peak memory 214192 kb
Host smart-e20b9c63-8659-4da0-bfd8-5d578b8176d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891908645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3891908645
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.3685040607
Short name T314
Test name
Test status
Simulation time 155641766 ps
CPU time 2.94 seconds
Started Mar 16 12:25:01 PM PDT 24
Finished Mar 16 12:25:04 PM PDT 24
Peak memory 210448 kb
Host smart-eacad5f6-724f-4769-ae09-5758449340d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685040607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3685040607
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2032011083
Short name T740
Test name
Test status
Simulation time 1212667332 ps
CPU time 6.64 seconds
Started Mar 16 12:25:02 PM PDT 24
Finished Mar 16 12:25:09 PM PDT 24
Peak memory 219852 kb
Host smart-7264866a-b043-483e-8bcd-5faf5ba9094a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032011083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2032011083
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3044197252
Short name T394
Test name
Test status
Simulation time 497875809 ps
CPU time 5.67 seconds
Started Mar 16 12:25:09 PM PDT 24
Finished Mar 16 12:25:15 PM PDT 24
Peak memory 209488 kb
Host smart-d9f49ab8-e684-4e5f-a43f-73285d039077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044197252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3044197252
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2863179247
Short name T265
Test name
Test status
Simulation time 77457246 ps
CPU time 3.28 seconds
Started Mar 16 12:25:06 PM PDT 24
Finished Mar 16 12:25:09 PM PDT 24
Peak memory 208508 kb
Host smart-908e3d6d-7d89-4eff-bb3b-4cc2f5fb4171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863179247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2863179247
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1230999410
Short name T598
Test name
Test status
Simulation time 213425029 ps
CPU time 3.41 seconds
Started Mar 16 12:25:05 PM PDT 24
Finished Mar 16 12:25:09 PM PDT 24
Peak memory 206720 kb
Host smart-ffea7890-05d0-434b-8b75-dcfbfb3d003e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230999410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1230999410
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3003852549
Short name T714
Test name
Test status
Simulation time 1194705669 ps
CPU time 14.73 seconds
Started Mar 16 12:25:03 PM PDT 24
Finished Mar 16 12:25:18 PM PDT 24
Peak memory 208668 kb
Host smart-bf34bb9b-131e-4e6d-8cef-6fe09310054b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003852549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3003852549
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.458715532
Short name T404
Test name
Test status
Simulation time 173368015 ps
CPU time 2.95 seconds
Started Mar 16 12:25:02 PM PDT 24
Finished Mar 16 12:25:05 PM PDT 24
Peak memory 207148 kb
Host smart-40dd6a1d-c6a3-4393-af82-5cbef0fc9827
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458715532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.458715532
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.144405743
Short name T75
Test name
Test status
Simulation time 401503413 ps
CPU time 3.4 seconds
Started Mar 16 12:24:57 PM PDT 24
Finished Mar 16 12:25:00 PM PDT 24
Peak memory 207932 kb
Host smart-3e8a194a-032e-4da2-919e-153c85410242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144405743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.144405743
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.744627212
Short name T590
Test name
Test status
Simulation time 476235021 ps
CPU time 5.76 seconds
Started Mar 16 12:24:59 PM PDT 24
Finished Mar 16 12:25:05 PM PDT 24
Peak memory 208328 kb
Host smart-06654df8-8a95-4ca5-bdc5-2c7c4a6573f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744627212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.744627212
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2404937165
Short name T310
Test name
Test status
Simulation time 285243201 ps
CPU time 12.48 seconds
Started Mar 16 12:25:13 PM PDT 24
Finished Mar 16 12:25:26 PM PDT 24
Peak memory 220704 kb
Host smart-2658ec8e-9ffd-4d7b-b545-0df6d35f4c72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404937165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2404937165
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.4197555702
Short name T248
Test name
Test status
Simulation time 320381442 ps
CPU time 18.58 seconds
Started Mar 16 12:25:06 PM PDT 24
Finished Mar 16 12:25:24 PM PDT 24
Peak memory 222472 kb
Host smart-026accbf-2c1d-45d5-87f7-6c00c5b1da8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197555702 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.4197555702
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2372638569
Short name T934
Test name
Test status
Simulation time 169905184 ps
CPU time 6.62 seconds
Started Mar 16 12:25:00 PM PDT 24
Finished Mar 16 12:25:07 PM PDT 24
Peak memory 206968 kb
Host smart-a3b14cd7-1cbe-4487-90fe-2668b432e8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372638569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2372638569
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3017491267
Short name T946
Test name
Test status
Simulation time 105284266 ps
CPU time 2.98 seconds
Started Mar 16 12:25:12 PM PDT 24
Finished Mar 16 12:25:15 PM PDT 24
Peak memory 210296 kb
Host smart-a38cc765-ce06-49ae-aa07-ee05e6ee3c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017491267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3017491267
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3129909819
Short name T627
Test name
Test status
Simulation time 9875484 ps
CPU time 0.83 seconds
Started Mar 16 12:25:08 PM PDT 24
Finished Mar 16 12:25:09 PM PDT 24
Peak memory 205816 kb
Host smart-fa54363f-fe17-4ac0-b9ff-8b6d7fe11d50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129909819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3129909819
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1174610020
Short name T650
Test name
Test status
Simulation time 22693224 ps
CPU time 1.77 seconds
Started Mar 16 12:25:09 PM PDT 24
Finished Mar 16 12:25:11 PM PDT 24
Peak memory 207120 kb
Host smart-c28f0006-0c05-4141-a70d-a70eba16ac76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174610020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1174610020
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2305434451
Short name T91
Test name
Test status
Simulation time 3327338581 ps
CPU time 34.99 seconds
Started Mar 16 12:25:11 PM PDT 24
Finished Mar 16 12:25:46 PM PDT 24
Peak memory 214260 kb
Host smart-41fde8ca-f834-4543-917a-2a06a9521e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305434451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2305434451
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.875368321
Short name T924
Test name
Test status
Simulation time 103008691 ps
CPU time 5.17 seconds
Started Mar 16 12:25:11 PM PDT 24
Finished Mar 16 12:25:16 PM PDT 24
Peak memory 211228 kb
Host smart-847fe5b2-f1ea-4504-9662-10d64926357d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875368321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.875368321
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2977557108
Short name T905
Test name
Test status
Simulation time 346422805 ps
CPU time 3.13 seconds
Started Mar 16 12:25:14 PM PDT 24
Finished Mar 16 12:25:18 PM PDT 24
Peak memory 216460 kb
Host smart-e6050294-5e51-48f1-a252-4ae1ee0eed9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977557108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2977557108
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.4169396942
Short name T376
Test name
Test status
Simulation time 155537089 ps
CPU time 4.01 seconds
Started Mar 16 12:25:12 PM PDT 24
Finished Mar 16 12:25:16 PM PDT 24
Peak memory 209284 kb
Host smart-62fa11a4-717c-495b-9a11-b98a89beb2f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169396942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.4169396942
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3276961591
Short name T851
Test name
Test status
Simulation time 923033632 ps
CPU time 27.62 seconds
Started Mar 16 12:25:28 PM PDT 24
Finished Mar 16 12:25:56 PM PDT 24
Peak memory 207804 kb
Host smart-29ec2f8a-ee1c-4f59-bd27-a622d828b663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276961591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3276961591
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2151796926
Short name T687
Test name
Test status
Simulation time 504072095 ps
CPU time 9.97 seconds
Started Mar 16 12:25:12 PM PDT 24
Finished Mar 16 12:25:22 PM PDT 24
Peak memory 208104 kb
Host smart-57a16f8c-cbee-4797-8c8f-d9bb176cc0b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151796926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2151796926
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.587568636
Short name T770
Test name
Test status
Simulation time 121232048 ps
CPU time 2 seconds
Started Mar 16 12:25:15 PM PDT 24
Finished Mar 16 12:25:18 PM PDT 24
Peak memory 206720 kb
Host smart-8eda77ab-9d1e-4dab-b00a-adda6ad761ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587568636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.587568636
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.793463736
Short name T824
Test name
Test status
Simulation time 57871156 ps
CPU time 2.88 seconds
Started Mar 16 12:25:11 PM PDT 24
Finished Mar 16 12:25:15 PM PDT 24
Peak memory 208336 kb
Host smart-e9e00cc4-9b4b-43a0-8667-6f862e7bf439
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793463736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.793463736
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1583882660
Short name T367
Test name
Test status
Simulation time 481134028 ps
CPU time 5.14 seconds
Started Mar 16 12:25:11 PM PDT 24
Finished Mar 16 12:25:16 PM PDT 24
Peak memory 218100 kb
Host smart-d469d2f6-493a-4b5f-99da-13564ba9dcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583882660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1583882660
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.945622643
Short name T758
Test name
Test status
Simulation time 8686540746 ps
CPU time 38.5 seconds
Started Mar 16 12:25:12 PM PDT 24
Finished Mar 16 12:25:51 PM PDT 24
Peak memory 208868 kb
Host smart-152cd5a5-aba4-45b7-9928-d39d31c2cecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945622643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.945622643
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.176626707
Short name T47
Test name
Test status
Simulation time 5601159111 ps
CPU time 34.6 seconds
Started Mar 16 12:25:14 PM PDT 24
Finished Mar 16 12:25:49 PM PDT 24
Peak memory 214804 kb
Host smart-3cbf7c19-7c73-4a8f-a447-b382691eabf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176626707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.176626707
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1067165489
Short name T228
Test name
Test status
Simulation time 95194559 ps
CPU time 4.62 seconds
Started Mar 16 12:25:07 PM PDT 24
Finished Mar 16 12:25:11 PM PDT 24
Peak memory 209336 kb
Host smart-403f4861-9dd6-4c08-bf98-e3575785bcb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067165489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1067165489
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2210911625
Short name T121
Test name
Test status
Simulation time 45305478 ps
CPU time 2.16 seconds
Started Mar 16 12:25:12 PM PDT 24
Finished Mar 16 12:25:14 PM PDT 24
Peak memory 209536 kb
Host smart-c16cf243-5a8f-4b99-b81b-bf92f50e4ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210911625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2210911625
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3342473804
Short name T678
Test name
Test status
Simulation time 50830632 ps
CPU time 0.75 seconds
Started Mar 16 12:25:23 PM PDT 24
Finished Mar 16 12:25:24 PM PDT 24
Peak memory 205804 kb
Host smart-2acd1843-d059-4f87-8a65-57583664d059
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342473804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3342473804
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1419771937
Short name T318
Test name
Test status
Simulation time 64407794 ps
CPU time 4.75 seconds
Started Mar 16 12:25:11 PM PDT 24
Finished Mar 16 12:25:16 PM PDT 24
Peak memory 215072 kb
Host smart-5e60220a-30cb-4e94-a16b-bb8af6e629d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1419771937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1419771937
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.452198089
Short name T790
Test name
Test status
Simulation time 238695686 ps
CPU time 5.68 seconds
Started Mar 16 12:25:13 PM PDT 24
Finished Mar 16 12:25:19 PM PDT 24
Peak memory 207740 kb
Host smart-3418d9c8-f71e-4f8b-a669-a8affee43530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452198089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.452198089
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2142682072
Short name T1077
Test name
Test status
Simulation time 118758154 ps
CPU time 2.41 seconds
Started Mar 16 12:25:19 PM PDT 24
Finished Mar 16 12:25:22 PM PDT 24
Peak memory 208448 kb
Host smart-f6096523-4ca7-4766-99fe-dbc9a1c70b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142682072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2142682072
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3671389693
Short name T660
Test name
Test status
Simulation time 74283105 ps
CPU time 3.1 seconds
Started Mar 16 12:25:14 PM PDT 24
Finished Mar 16 12:25:17 PM PDT 24
Peak memory 208992 kb
Host smart-da07300a-0fae-4c7c-b6b6-668cce289091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671389693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3671389693
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1936972438
Short name T175
Test name
Test status
Simulation time 410735452 ps
CPU time 3.76 seconds
Started Mar 16 12:25:08 PM PDT 24
Finished Mar 16 12:25:12 PM PDT 24
Peak memory 214060 kb
Host smart-aade4d94-ab40-48d9-ae6c-1780d09985d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936972438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1936972438
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.844768573
Short name T291
Test name
Test status
Simulation time 235605736 ps
CPU time 5.27 seconds
Started Mar 16 12:25:08 PM PDT 24
Finished Mar 16 12:25:13 PM PDT 24
Peak memory 208028 kb
Host smart-2c4261cb-2058-4771-9a50-5f9490a43291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844768573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.844768573
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.289347910
Short name T652
Test name
Test status
Simulation time 72865685 ps
CPU time 2.91 seconds
Started Mar 16 12:25:09 PM PDT 24
Finished Mar 16 12:25:12 PM PDT 24
Peak memory 208252 kb
Host smart-a2e22428-1ab0-4bb9-a376-fdbcd45cedfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289347910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.289347910
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3054804983
Short name T1024
Test name
Test status
Simulation time 2498702624 ps
CPU time 17.52 seconds
Started Mar 16 12:25:14 PM PDT 24
Finished Mar 16 12:25:32 PM PDT 24
Peak memory 208512 kb
Host smart-08c5d7de-7d01-4121-afe2-4ea0e1b38cff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054804983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3054804983
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3843561190
Short name T781
Test name
Test status
Simulation time 99650250 ps
CPU time 2.25 seconds
Started Mar 16 12:25:11 PM PDT 24
Finished Mar 16 12:25:13 PM PDT 24
Peak memory 208536 kb
Host smart-eedcf9a4-6106-49df-88d1-6c9484ac4c54
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843561190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3843561190
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1196385427
Short name T266
Test name
Test status
Simulation time 65277117 ps
CPU time 3.21 seconds
Started Mar 16 12:25:14 PM PDT 24
Finished Mar 16 12:25:17 PM PDT 24
Peak memory 208284 kb
Host smart-46006274-989b-4b94-9549-f42aa717386f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196385427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1196385427
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3757222758
Short name T895
Test name
Test status
Simulation time 145043668 ps
CPU time 2.71 seconds
Started Mar 16 12:25:23 PM PDT 24
Finished Mar 16 12:25:26 PM PDT 24
Peak memory 215908 kb
Host smart-32532766-8a17-4ac2-bed2-f358858d578b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757222758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3757222758
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.915209813
Short name T694
Test name
Test status
Simulation time 9452098419 ps
CPU time 43.18 seconds
Started Mar 16 12:25:06 PM PDT 24
Finished Mar 16 12:25:49 PM PDT 24
Peak memory 208856 kb
Host smart-65785b28-a3a8-450d-b124-278beb41fac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915209813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.915209813
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3694148906
Short name T986
Test name
Test status
Simulation time 9486004733 ps
CPU time 27.32 seconds
Started Mar 16 12:25:16 PM PDT 24
Finished Mar 16 12:25:44 PM PDT 24
Peak memory 222440 kb
Host smart-1e0a98af-7769-4740-8110-c5249b6fff32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694148906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3694148906
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.4271883406
Short name T245
Test name
Test status
Simulation time 238965192 ps
CPU time 6.2 seconds
Started Mar 16 12:25:07 PM PDT 24
Finished Mar 16 12:25:13 PM PDT 24
Peak memory 208944 kb
Host smart-0e52fc94-e9bc-4b50-a02d-e3417dab1b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271883406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.4271883406
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.360433721
Short name T1031
Test name
Test status
Simulation time 36229096 ps
CPU time 1.15 seconds
Started Mar 16 12:25:18 PM PDT 24
Finished Mar 16 12:25:20 PM PDT 24
Peak memory 208516 kb
Host smart-0ce41a24-1208-4b10-aaed-9b468797df10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360433721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.360433721
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1366787622
Short name T97
Test name
Test status
Simulation time 12146862 ps
CPU time 0.85 seconds
Started Mar 16 12:25:20 PM PDT 24
Finished Mar 16 12:25:22 PM PDT 24
Peak memory 205736 kb
Host smart-7eedf956-6275-45c1-afec-36581ce34f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366787622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1366787622
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3715669271
Short name T433
Test name
Test status
Simulation time 9024225602 ps
CPU time 52.67 seconds
Started Mar 16 12:25:16 PM PDT 24
Finished Mar 16 12:26:10 PM PDT 24
Peak memory 222464 kb
Host smart-5928b176-e91a-4f80-8831-36ab22546ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715669271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3715669271
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2730049407
Short name T1005
Test name
Test status
Simulation time 44176930 ps
CPU time 2.07 seconds
Started Mar 16 12:25:15 PM PDT 24
Finished Mar 16 12:25:18 PM PDT 24
Peak memory 207808 kb
Host smart-66b04cb9-827a-49ab-a48b-d9c39bf8e331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730049407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2730049407
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1270514855
Short name T388
Test name
Test status
Simulation time 156685309 ps
CPU time 5.08 seconds
Started Mar 16 12:25:30 PM PDT 24
Finished Mar 16 12:25:35 PM PDT 24
Peak memory 208972 kb
Host smart-bfda320c-3229-4b27-9e48-bfaf657fed82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270514855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1270514855
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1534540257
Short name T184
Test name
Test status
Simulation time 2022206740 ps
CPU time 11.89 seconds
Started Mar 16 12:25:24 PM PDT 24
Finished Mar 16 12:25:36 PM PDT 24
Peak memory 222372 kb
Host smart-e2b61bcc-5b9d-479a-a8c9-2836056250cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534540257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1534540257
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3512365849
Short name T644
Test name
Test status
Simulation time 34141235 ps
CPU time 2.62 seconds
Started Mar 16 12:25:15 PM PDT 24
Finished Mar 16 12:25:18 PM PDT 24
Peak memory 214248 kb
Host smart-492a58a3-fd8b-4ae3-a777-d14fd2ba4b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512365849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3512365849
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.748235081
Short name T383
Test name
Test status
Simulation time 1305848773 ps
CPU time 9.27 seconds
Started Mar 16 12:25:28 PM PDT 24
Finished Mar 16 12:25:37 PM PDT 24
Peak memory 210104 kb
Host smart-2d202280-10b9-4aab-8469-6e14991cd0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748235081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.748235081
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2882012928
Short name T1047
Test name
Test status
Simulation time 1777513855 ps
CPU time 42.34 seconds
Started Mar 16 12:25:16 PM PDT 24
Finished Mar 16 12:25:58 PM PDT 24
Peak memory 208264 kb
Host smart-74f4fc07-b49b-4a67-8a3f-881d9e0e7eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882012928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2882012928
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2220758747
Short name T987
Test name
Test status
Simulation time 68091904 ps
CPU time 3.36 seconds
Started Mar 16 12:25:13 PM PDT 24
Finished Mar 16 12:25:17 PM PDT 24
Peak memory 208412 kb
Host smart-7a413e17-b199-44fa-8e67-9b20f78760f8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220758747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2220758747
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.300994508
Short name T612
Test name
Test status
Simulation time 331768092 ps
CPU time 3.2 seconds
Started Mar 16 12:25:17 PM PDT 24
Finished Mar 16 12:25:21 PM PDT 24
Peak memory 206736 kb
Host smart-1ac9e823-cbcd-4eeb-9f2a-5b7db8e077cb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300994508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.300994508
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3650032564
Short name T107
Test name
Test status
Simulation time 57153496 ps
CPU time 2.83 seconds
Started Mar 16 12:25:25 PM PDT 24
Finished Mar 16 12:25:29 PM PDT 24
Peak memory 207936 kb
Host smart-7185009a-6fc4-433d-a650-2a0dc034b472
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650032564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3650032564
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.929890989
Short name T189
Test name
Test status
Simulation time 19886999 ps
CPU time 1.83 seconds
Started Mar 16 12:25:11 PM PDT 24
Finished Mar 16 12:25:13 PM PDT 24
Peak memory 214200 kb
Host smart-fc16be03-47b4-4d43-aad9-d1da86072026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929890989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.929890989
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1858790948
Short name T886
Test name
Test status
Simulation time 175418854 ps
CPU time 2.58 seconds
Started Mar 16 12:25:25 PM PDT 24
Finished Mar 16 12:25:29 PM PDT 24
Peak memory 208184 kb
Host smart-33d82772-ae84-4a21-9af4-21d0bc85c1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858790948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1858790948
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3777134358
Short name T1009
Test name
Test status
Simulation time 429595981 ps
CPU time 9.56 seconds
Started Mar 16 12:25:27 PM PDT 24
Finished Mar 16 12:25:37 PM PDT 24
Peak memory 215828 kb
Host smart-0a144ffb-8b0b-4b61-8614-0ab9fad38e74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777134358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3777134358
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.2690301164
Short name T850
Test name
Test status
Simulation time 386732291 ps
CPU time 7.74 seconds
Started Mar 16 12:25:13 PM PDT 24
Finished Mar 16 12:25:22 PM PDT 24
Peak memory 219900 kb
Host smart-1125b6d0-ea2b-435e-88f6-2e838723ce1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690301164 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.2690301164
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3725108018
Short name T900
Test name
Test status
Simulation time 2439295701 ps
CPU time 23.62 seconds
Started Mar 16 12:25:23 PM PDT 24
Finished Mar 16 12:25:48 PM PDT 24
Peak memory 209248 kb
Host smart-915a308a-edc6-4121-8229-a5f907815ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725108018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3725108018
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2298323450
Short name T2
Test name
Test status
Simulation time 932153854 ps
CPU time 2.86 seconds
Started Mar 16 12:25:26 PM PDT 24
Finished Mar 16 12:25:29 PM PDT 24
Peak memory 209692 kb
Host smart-8017f694-5c4d-4474-a9ba-270589b80dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298323450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2298323450
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.4162616569
Short name T960
Test name
Test status
Simulation time 20580364 ps
CPU time 0.82 seconds
Started Mar 16 12:25:16 PM PDT 24
Finished Mar 16 12:25:18 PM PDT 24
Peak memory 205764 kb
Host smart-0fee38b6-61ab-4339-8de3-484fc829c2de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162616569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.4162616569
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1886004586
Short name T420
Test name
Test status
Simulation time 137295011 ps
CPU time 2.69 seconds
Started Mar 16 12:25:20 PM PDT 24
Finished Mar 16 12:25:25 PM PDT 24
Peak memory 215160 kb
Host smart-2ea9dbf1-02ee-4e72-b4d4-679745e9da5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1886004586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1886004586
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1572506475
Short name T33
Test name
Test status
Simulation time 351000735 ps
CPU time 3.27 seconds
Started Mar 16 12:25:14 PM PDT 24
Finished Mar 16 12:25:18 PM PDT 24
Peak memory 207700 kb
Host smart-e76179e5-6d8f-4c8c-a4c0-1edcc79a42c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572506475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1572506475
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.35738891
Short name T917
Test name
Test status
Simulation time 72156199 ps
CPU time 3.06 seconds
Started Mar 16 12:25:19 PM PDT 24
Finished Mar 16 12:25:22 PM PDT 24
Peak memory 208412 kb
Host smart-e39a3ddf-bbe0-4ecf-af71-3f3e7483ccb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35738891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.35738891
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3307801134
Short name T1016
Test name
Test status
Simulation time 2364923688 ps
CPU time 25.39 seconds
Started Mar 16 12:25:18 PM PDT 24
Finished Mar 16 12:25:45 PM PDT 24
Peak memory 214388 kb
Host smart-1e1c9fc5-16a1-4cce-9515-29e184dc6e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307801134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3307801134
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3887559215
Short name T353
Test name
Test status
Simulation time 384708956 ps
CPU time 3.28 seconds
Started Mar 16 12:25:17 PM PDT 24
Finished Mar 16 12:25:22 PM PDT 24
Peak memory 220148 kb
Host smart-dcd0b403-0094-4fa9-84fa-a116aad71159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887559215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3887559215
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1424347972
Short name T972
Test name
Test status
Simulation time 1136423551 ps
CPU time 3.44 seconds
Started Mar 16 12:25:14 PM PDT 24
Finished Mar 16 12:25:18 PM PDT 24
Peak memory 207436 kb
Host smart-3ee61cd3-1f65-4378-94e9-f63a747feffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424347972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1424347972
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2846495074
Short name T802
Test name
Test status
Simulation time 246101748 ps
CPU time 4.05 seconds
Started Mar 16 12:25:24 PM PDT 24
Finished Mar 16 12:25:29 PM PDT 24
Peak memory 208608 kb
Host smart-ac3414a7-72cb-4647-b268-389440371f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846495074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2846495074
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2349694789
Short name T811
Test name
Test status
Simulation time 1474806770 ps
CPU time 27.72 seconds
Started Mar 16 12:25:19 PM PDT 24
Finished Mar 16 12:25:48 PM PDT 24
Peak memory 208600 kb
Host smart-8a55e712-973d-4beb-b1e5-5e81a15d2abc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349694789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2349694789
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1212119877
Short name T347
Test name
Test status
Simulation time 34628769 ps
CPU time 2.36 seconds
Started Mar 16 12:25:21 PM PDT 24
Finished Mar 16 12:25:24 PM PDT 24
Peak memory 207232 kb
Host smart-1a533aea-4ab6-48fe-874b-d1dfe9ab47d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212119877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1212119877
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.4289489332
Short name T580
Test name
Test status
Simulation time 329824526 ps
CPU time 4.17 seconds
Started Mar 16 12:25:19 PM PDT 24
Finished Mar 16 12:25:24 PM PDT 24
Peak memory 207444 kb
Host smart-759bf566-6b7c-4127-b933-37843a744aa5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289489332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.4289489332
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2556970806
Short name T393
Test name
Test status
Simulation time 92837852 ps
CPU time 2.56 seconds
Started Mar 16 12:25:13 PM PDT 24
Finished Mar 16 12:25:16 PM PDT 24
Peak memory 214180 kb
Host smart-453ea8a6-a6c1-4ac3-9ebf-4e7859d866c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556970806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2556970806
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1911859638
Short name T720
Test name
Test status
Simulation time 68001355 ps
CPU time 2.97 seconds
Started Mar 16 12:25:20 PM PDT 24
Finished Mar 16 12:25:25 PM PDT 24
Peak memory 207628 kb
Host smart-fd8b247e-92d2-4075-9755-e953f23881a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911859638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1911859638
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.1239839357
Short name T815
Test name
Test status
Simulation time 88168439 ps
CPU time 3.07 seconds
Started Mar 16 12:25:20 PM PDT 24
Finished Mar 16 12:25:24 PM PDT 24
Peak memory 222408 kb
Host smart-065b0782-eaf4-4927-8876-ca6b875f694b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239839357 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.1239839357
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.929518860
Short name T763
Test name
Test status
Simulation time 376464550 ps
CPU time 10.49 seconds
Started Mar 16 12:25:11 PM PDT 24
Finished Mar 16 12:25:22 PM PDT 24
Peak memory 214256 kb
Host smart-6b8b6ce7-7ad5-4d21-ac10-7e143febbb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929518860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.929518860
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.265963008
Short name T392
Test name
Test status
Simulation time 85384829 ps
CPU time 1.9 seconds
Started Mar 16 12:25:23 PM PDT 24
Finished Mar 16 12:25:25 PM PDT 24
Peak memory 209852 kb
Host smart-97dac671-34a6-4551-9df8-687a3980ad74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265963008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.265963008
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.4234534786
Short name T812
Test name
Test status
Simulation time 56507479 ps
CPU time 0.74 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:23:40 PM PDT 24
Peak memory 205772 kb
Host smart-63c7769c-d32f-4d79-820b-23ffd5a16d6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234534786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.4234534786
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3813853228
Short name T836
Test name
Test status
Simulation time 88336225 ps
CPU time 2.59 seconds
Started Mar 16 12:23:42 PM PDT 24
Finished Mar 16 12:23:44 PM PDT 24
Peak memory 208984 kb
Host smart-0d27f38d-fa07-4b0e-94a6-f491d1ed6d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813853228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3813853228
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2839258789
Short name T229
Test name
Test status
Simulation time 1270783566 ps
CPU time 7.15 seconds
Started Mar 16 12:23:42 PM PDT 24
Finished Mar 16 12:23:49 PM PDT 24
Peak memory 209300 kb
Host smart-b0ceb377-a0ef-4b35-8df8-ddae0641f79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839258789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2839258789
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.4064478657
Short name T374
Test name
Test status
Simulation time 44133719 ps
CPU time 2.85 seconds
Started Mar 16 12:23:40 PM PDT 24
Finished Mar 16 12:23:43 PM PDT 24
Peak memory 214188 kb
Host smart-84a11ecf-bc36-4917-b291-d4ab5e8b3217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4064478657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.4064478657
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.565839691
Short name T42
Test name
Test status
Simulation time 324763789 ps
CPU time 3.01 seconds
Started Mar 16 12:23:50 PM PDT 24
Finished Mar 16 12:23:53 PM PDT 24
Peak memory 222284 kb
Host smart-30a0e91c-fcf9-41d5-ab08-beee250138b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565839691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.565839691
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2823888623
Short name T1052
Test name
Test status
Simulation time 339986108 ps
CPU time 4.84 seconds
Started Mar 16 12:23:42 PM PDT 24
Finished Mar 16 12:23:47 PM PDT 24
Peak memory 210004 kb
Host smart-09baa8e0-0954-49aa-8cf4-ea9f05477e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823888623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2823888623
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3866110766
Short name T12
Test name
Test status
Simulation time 10857243647 ps
CPU time 125.59 seconds
Started Mar 16 12:23:33 PM PDT 24
Finished Mar 16 12:25:39 PM PDT 24
Peak memory 250288 kb
Host smart-141c9168-c5fc-4a32-aa1a-93269f8897df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866110766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3866110766
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2038159274
Short name T369
Test name
Test status
Simulation time 67150690 ps
CPU time 1.88 seconds
Started Mar 16 12:23:50 PM PDT 24
Finished Mar 16 12:23:52 PM PDT 24
Peak memory 207240 kb
Host smart-593d4f9b-f371-474c-bfb9-fd2979343708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038159274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2038159274
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1722398093
Short name T752
Test name
Test status
Simulation time 30549692 ps
CPU time 2.25 seconds
Started Mar 16 12:23:45 PM PDT 24
Finished Mar 16 12:23:47 PM PDT 24
Peak memory 206620 kb
Host smart-26fbe880-fc44-4691-9fbf-6c361aa1f943
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722398093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1722398093
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.574654970
Short name T195
Test name
Test status
Simulation time 70262712 ps
CPU time 3.42 seconds
Started Mar 16 12:23:34 PM PDT 24
Finished Mar 16 12:23:38 PM PDT 24
Peak memory 208760 kb
Host smart-4e1eb963-0c3d-4c13-9538-ae748dbb7f1a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574654970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.574654970
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2994720122
Short name T799
Test name
Test status
Simulation time 111577151 ps
CPU time 2.17 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:23:41 PM PDT 24
Peak memory 208704 kb
Host smart-8af62e07-0a04-46fa-a4fe-130409ee0be4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994720122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2994720122
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3918934047
Short name T777
Test name
Test status
Simulation time 41301261 ps
CPU time 1.84 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:23:41 PM PDT 24
Peak memory 207764 kb
Host smart-1f556014-cc87-43cd-a671-64e004091937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918934047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3918934047
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2077976952
Short name T601
Test name
Test status
Simulation time 242248130 ps
CPU time 2.75 seconds
Started Mar 16 12:23:31 PM PDT 24
Finished Mar 16 12:23:34 PM PDT 24
Peak memory 206584 kb
Host smart-b88cf4ab-760f-4ca3-b4cb-9a754d014999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077976952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2077976952
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.96983894
Short name T806
Test name
Test status
Simulation time 726884226 ps
CPU time 7.62 seconds
Started Mar 16 12:23:50 PM PDT 24
Finished Mar 16 12:23:58 PM PDT 24
Peak memory 215096 kb
Host smart-853f2e06-3612-4e22-8b5f-d083f29241b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96983894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.96983894
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.4038487905
Short name T122
Test name
Test status
Simulation time 616449426 ps
CPU time 4.78 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:23:44 PM PDT 24
Peak memory 222624 kb
Host smart-a3a2ab54-2652-4cdd-9824-bfc8ddf7b63a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038487905 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.4038487905
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1119490156
Short name T287
Test name
Test status
Simulation time 937899833 ps
CPU time 7.45 seconds
Started Mar 16 12:23:41 PM PDT 24
Finished Mar 16 12:23:48 PM PDT 24
Peak memory 208024 kb
Host smart-b0896944-ef26-44a4-ad8d-666bdd9b5e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119490156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1119490156
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2799801080
Short name T406
Test name
Test status
Simulation time 999066691 ps
CPU time 2.92 seconds
Started Mar 16 12:23:33 PM PDT 24
Finished Mar 16 12:23:36 PM PDT 24
Peak memory 210060 kb
Host smart-6abfb9d4-9ae1-4421-9e98-6f84643dcd71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799801080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2799801080
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3615575290
Short name T814
Test name
Test status
Simulation time 35389070 ps
CPU time 0.76 seconds
Started Mar 16 12:25:25 PM PDT 24
Finished Mar 16 12:25:26 PM PDT 24
Peak memory 205744 kb
Host smart-a4b13083-d4cc-44de-b0a3-d8c11cb72441
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615575290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3615575290
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2799226549
Short name T425
Test name
Test status
Simulation time 292599799 ps
CPU time 17.11 seconds
Started Mar 16 12:25:13 PM PDT 24
Finished Mar 16 12:25:30 PM PDT 24
Peak memory 215244 kb
Host smart-dbc24eb8-3b0b-4571-9460-d182774c1442
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2799226549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2799226549
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3428504797
Short name T69
Test name
Test status
Simulation time 203923632 ps
CPU time 2.09 seconds
Started Mar 16 12:25:14 PM PDT 24
Finished Mar 16 12:25:16 PM PDT 24
Peak memory 209212 kb
Host smart-8e236f0d-33cb-41c8-97ac-2d1e74fabdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428504797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3428504797
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1934883261
Short name T365
Test name
Test status
Simulation time 725700050 ps
CPU time 7.24 seconds
Started Mar 16 12:25:26 PM PDT 24
Finished Mar 16 12:25:34 PM PDT 24
Peak memory 222364 kb
Host smart-1cc35c0d-64d1-4a89-bb51-a052545a8a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934883261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1934883261
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.424737210
Short name T52
Test name
Test status
Simulation time 61254618 ps
CPU time 2.87 seconds
Started Mar 16 12:25:27 PM PDT 24
Finished Mar 16 12:25:31 PM PDT 24
Peak memory 216376 kb
Host smart-fad1a53c-65a2-4805-8532-d5ec2dd7d0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424737210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.424737210
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1699617832
Short name T240
Test name
Test status
Simulation time 440557899 ps
CPU time 5.57 seconds
Started Mar 16 12:25:21 PM PDT 24
Finished Mar 16 12:25:27 PM PDT 24
Peak memory 207808 kb
Host smart-cefa7956-f940-4ec0-b75f-85b592def8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699617832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1699617832
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.619927109
Short name T679
Test name
Test status
Simulation time 58957336 ps
CPU time 2.99 seconds
Started Mar 16 12:25:23 PM PDT 24
Finished Mar 16 12:25:27 PM PDT 24
Peak memory 206892 kb
Host smart-faa8468d-7f84-4bc3-9f58-e50507168ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619927109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.619927109
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1062698994
Short name T596
Test name
Test status
Simulation time 2157380559 ps
CPU time 54.59 seconds
Started Mar 16 12:25:17 PM PDT 24
Finished Mar 16 12:26:13 PM PDT 24
Peak memory 208472 kb
Host smart-9aab654e-197e-4dda-81d2-70967a9e5730
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062698994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1062698994
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.117623915
Short name T956
Test name
Test status
Simulation time 1646379897 ps
CPU time 52.85 seconds
Started Mar 16 12:25:22 PM PDT 24
Finished Mar 16 12:26:15 PM PDT 24
Peak memory 208008 kb
Host smart-9f440330-8825-4d81-bc1a-d89e7f267df8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117623915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.117623915
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2000712573
Short name T899
Test name
Test status
Simulation time 768473679 ps
CPU time 5.85 seconds
Started Mar 16 12:25:15 PM PDT 24
Finished Mar 16 12:25:22 PM PDT 24
Peak memory 208744 kb
Host smart-09bb230c-7421-4120-8ad1-84c66b1ad938
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000712573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2000712573
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2704793919
Short name T689
Test name
Test status
Simulation time 77841998 ps
CPU time 2.26 seconds
Started Mar 16 12:25:18 PM PDT 24
Finished Mar 16 12:25:21 PM PDT 24
Peak memory 209032 kb
Host smart-40e804b9-0b6a-4a34-8b00-9742c9c0ef40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704793919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2704793919
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3783042700
Short name T1072
Test name
Test status
Simulation time 110558048 ps
CPU time 4.31 seconds
Started Mar 16 12:25:15 PM PDT 24
Finished Mar 16 12:25:20 PM PDT 24
Peak memory 206856 kb
Host smart-a4e6e36c-c687-431b-a9ba-029131a0c710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783042700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3783042700
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2851961405
Short name T303
Test name
Test status
Simulation time 114796387 ps
CPU time 3.78 seconds
Started Mar 16 12:25:13 PM PDT 24
Finished Mar 16 12:25:17 PM PDT 24
Peak memory 208996 kb
Host smart-f7e319b0-355b-493f-baa1-a65caf437fc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851961405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2851961405
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1805005373
Short name T102
Test name
Test status
Simulation time 716438995 ps
CPU time 5.81 seconds
Started Mar 16 12:25:22 PM PDT 24
Finished Mar 16 12:25:28 PM PDT 24
Peak memory 222488 kb
Host smart-4b00f2e7-4af0-4684-9ede-31bd2b0d146d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805005373 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1805005373
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3824832669
Short name T1048
Test name
Test status
Simulation time 142273067 ps
CPU time 5.61 seconds
Started Mar 16 12:25:22 PM PDT 24
Finished Mar 16 12:25:28 PM PDT 24
Peak memory 214228 kb
Host smart-8ba9eb2e-1dc8-4667-87a4-03913e37e982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824832669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3824832669
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.554067063
Short name T390
Test name
Test status
Simulation time 1156211157 ps
CPU time 22.74 seconds
Started Mar 16 12:25:20 PM PDT 24
Finished Mar 16 12:25:45 PM PDT 24
Peak memory 211144 kb
Host smart-6095e991-f751-4724-ae56-5b1f678f72c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554067063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.554067063
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1125296332
Short name T1004
Test name
Test status
Simulation time 123947606 ps
CPU time 0.73 seconds
Started Mar 16 12:25:33 PM PDT 24
Finished Mar 16 12:25:35 PM PDT 24
Peak memory 205616 kb
Host smart-c9d43b60-d918-47bd-bbe5-ac8a417e424d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125296332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1125296332
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3799875048
Short name T418
Test name
Test status
Simulation time 2192781306 ps
CPU time 62.26 seconds
Started Mar 16 12:25:24 PM PDT 24
Finished Mar 16 12:26:27 PM PDT 24
Peak memory 222324 kb
Host smart-480c1463-d222-450b-aa81-08f000c50f29
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3799875048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3799875048
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.4205160382
Short name T996
Test name
Test status
Simulation time 56987813 ps
CPU time 1.51 seconds
Started Mar 16 12:25:20 PM PDT 24
Finished Mar 16 12:25:22 PM PDT 24
Peak memory 216460 kb
Host smart-72a747f5-7e37-4b80-bdbe-b1087c2ca855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205160382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.4205160382
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1411748128
Short name T865
Test name
Test status
Simulation time 241493824 ps
CPU time 3.14 seconds
Started Mar 16 12:25:24 PM PDT 24
Finished Mar 16 12:25:28 PM PDT 24
Peak memory 207844 kb
Host smart-7d5ea53f-3ad8-4a33-9a76-ccee6db5ffbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411748128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1411748128
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2365769826
Short name T766
Test name
Test status
Simulation time 81472263 ps
CPU time 3.71 seconds
Started Mar 16 12:25:13 PM PDT 24
Finished Mar 16 12:25:18 PM PDT 24
Peak memory 214120 kb
Host smart-62676395-5180-4f24-9402-ed4ef4c66702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365769826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2365769826
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2869547163
Short name T768
Test name
Test status
Simulation time 2151084116 ps
CPU time 18.19 seconds
Started Mar 16 12:25:21 PM PDT 24
Finished Mar 16 12:25:40 PM PDT 24
Peak memory 214324 kb
Host smart-525e5564-10c3-4006-891c-48d986ffd604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869547163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2869547163
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.4149916781
Short name T833
Test name
Test status
Simulation time 836216433 ps
CPU time 2.87 seconds
Started Mar 16 12:25:24 PM PDT 24
Finished Mar 16 12:25:27 PM PDT 24
Peak memory 219980 kb
Host smart-2a3e1ef0-1fbb-4aef-b918-f6a7f8e2aa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149916781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.4149916781
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.11988791
Short name T360
Test name
Test status
Simulation time 379536717 ps
CPU time 4.54 seconds
Started Mar 16 12:25:27 PM PDT 24
Finished Mar 16 12:25:32 PM PDT 24
Peak memory 208632 kb
Host smart-da2111a5-251d-4650-8a68-023bc2c95d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11988791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.11988791
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.460542253
Short name T351
Test name
Test status
Simulation time 34499894868 ps
CPU time 63.44 seconds
Started Mar 16 12:25:27 PM PDT 24
Finished Mar 16 12:26:31 PM PDT 24
Peak memory 208480 kb
Host smart-c6aca695-6c05-4aa0-aa98-f0b5631812c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460542253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.460542253
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3566467680
Short name T709
Test name
Test status
Simulation time 264908541 ps
CPU time 5.68 seconds
Started Mar 16 12:25:24 PM PDT 24
Finished Mar 16 12:25:31 PM PDT 24
Peak memory 208800 kb
Host smart-268bb80d-283b-4b35-9859-3e056c06189f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566467680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3566467680
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.757262895
Short name T355
Test name
Test status
Simulation time 49443438 ps
CPU time 2.6 seconds
Started Mar 16 12:25:28 PM PDT 24
Finished Mar 16 12:25:31 PM PDT 24
Peak memory 207740 kb
Host smart-a5f79414-c8b1-4df8-9271-1527821eefeb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757262895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.757262895
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2902887572
Short name T123
Test name
Test status
Simulation time 270614503 ps
CPU time 3.15 seconds
Started Mar 16 12:25:24 PM PDT 24
Finished Mar 16 12:25:29 PM PDT 24
Peak memory 206644 kb
Host smart-9a7310c0-5326-4bde-94ea-92bdbb2e1317
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902887572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2902887572
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3813103820
Short name T405
Test name
Test status
Simulation time 401084753 ps
CPU time 2.99 seconds
Started Mar 16 12:25:16 PM PDT 24
Finished Mar 16 12:25:20 PM PDT 24
Peak memory 207908 kb
Host smart-3a3da9fa-5836-49b8-8ca3-a6a9d50770d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813103820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3813103820
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3057294567
Short name T1062
Test name
Test status
Simulation time 457365110 ps
CPU time 5.38 seconds
Started Mar 16 12:25:25 PM PDT 24
Finished Mar 16 12:25:31 PM PDT 24
Peak memory 207112 kb
Host smart-c930a30c-3592-459c-8d9e-df0c40471d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057294567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3057294567
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2666475308
Short name T206
Test name
Test status
Simulation time 235368218 ps
CPU time 7.56 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:40 PM PDT 24
Peak memory 222524 kb
Host smart-5650e9b4-653d-40cb-ab3e-740cb483e31c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666475308 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2666475308
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2173640148
Short name T306
Test name
Test status
Simulation time 261310507 ps
CPU time 9.78 seconds
Started Mar 16 12:25:27 PM PDT 24
Finished Mar 16 12:25:37 PM PDT 24
Peak memory 214268 kb
Host smart-ab6dbbac-d02d-4e4e-bedd-15c9b152dfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173640148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2173640148
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2087376236
Short name T722
Test name
Test status
Simulation time 39283814 ps
CPU time 2.34 seconds
Started Mar 16 12:25:31 PM PDT 24
Finished Mar 16 12:25:33 PM PDT 24
Peak memory 210224 kb
Host smart-b0ef8b6e-4339-4359-be6b-720e6205f856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087376236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2087376236
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2768963061
Short name T893
Test name
Test status
Simulation time 35703201 ps
CPU time 0.73 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:33 PM PDT 24
Peak memory 205772 kb
Host smart-494f1f1c-6c30-463d-89c1-5be293b516cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768963061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2768963061
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.862954199
Short name T410
Test name
Test status
Simulation time 1445781520 ps
CPU time 10.41 seconds
Started Mar 16 12:25:29 PM PDT 24
Finished Mar 16 12:25:40 PM PDT 24
Peak memory 214220 kb
Host smart-b6dcb8d4-a11b-4cd7-818a-561c27681822
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=862954199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.862954199
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3118584656
Short name T276
Test name
Test status
Simulation time 773058799 ps
CPU time 21.32 seconds
Started Mar 16 12:25:31 PM PDT 24
Finished Mar 16 12:25:53 PM PDT 24
Peak memory 220584 kb
Host smart-9fe610d1-cd75-4a31-b922-524c9bf916d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118584656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3118584656
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.154871574
Short name T704
Test name
Test status
Simulation time 21381032 ps
CPU time 1.54 seconds
Started Mar 16 12:25:31 PM PDT 24
Finished Mar 16 12:25:32 PM PDT 24
Peak memory 214280 kb
Host smart-1f73a146-e124-4fd9-8e2f-1db9d0d7e8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154871574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.154871574
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2002474831
Short name T25
Test name
Test status
Simulation time 286009298 ps
CPU time 7.45 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:39 PM PDT 24
Peak memory 220924 kb
Host smart-a0273ccd-a348-4155-8aa5-2eefd1e1093d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002474831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2002474831
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.653211941
Short name T44
Test name
Test status
Simulation time 736006980 ps
CPU time 3.84 seconds
Started Mar 16 12:25:30 PM PDT 24
Finished Mar 16 12:25:34 PM PDT 24
Peak memory 216632 kb
Host smart-cc7150e5-9e68-4ce3-be35-a8d08d789760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653211941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.653211941
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2194208669
Short name T800
Test name
Test status
Simulation time 2406776299 ps
CPU time 33.21 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:26:06 PM PDT 24
Peak memory 208192 kb
Host smart-68bb77ae-2c2e-4c55-89fc-45525df5b015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194208669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2194208669
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4193813546
Short name T837
Test name
Test status
Simulation time 250081283 ps
CPU time 8.53 seconds
Started Mar 16 12:25:31 PM PDT 24
Finished Mar 16 12:25:39 PM PDT 24
Peak memory 206752 kb
Host smart-1ad246c8-f72f-471b-b222-e39dea924733
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193813546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4193813546
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3825609749
Short name T400
Test name
Test status
Simulation time 678500489 ps
CPU time 6.55 seconds
Started Mar 16 12:25:34 PM PDT 24
Finished Mar 16 12:25:42 PM PDT 24
Peak memory 207872 kb
Host smart-0eda845a-6861-4612-9a83-2a7d376b3994
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825609749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3825609749
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1649043027
Short name T764
Test name
Test status
Simulation time 56611209 ps
CPU time 2.96 seconds
Started Mar 16 12:25:34 PM PDT 24
Finished Mar 16 12:25:37 PM PDT 24
Peak memory 208752 kb
Host smart-02462d77-68fe-4caf-b5df-525e3738692d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649043027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1649043027
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2679803030
Short name T356
Test name
Test status
Simulation time 519217585 ps
CPU time 3.24 seconds
Started Mar 16 12:25:33 PM PDT 24
Finished Mar 16 12:25:36 PM PDT 24
Peak memory 209036 kb
Host smart-90a1a941-394b-428f-bd1a-aaa4ff2b3fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679803030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2679803030
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2945192659
Short name T1013
Test name
Test status
Simulation time 3712630268 ps
CPU time 33.99 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:26:06 PM PDT 24
Peak memory 208744 kb
Host smart-a04e6fd9-4766-46a1-ae87-08002b430212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945192659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2945192659
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.2304195365
Short name T249
Test name
Test status
Simulation time 582480726 ps
CPU time 7.5 seconds
Started Mar 16 12:25:40 PM PDT 24
Finished Mar 16 12:25:53 PM PDT 24
Peak memory 222592 kb
Host smart-2e649f86-2121-4461-8ca4-aa13df2d17e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304195365 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.2304195365
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1061433883
Short name T741
Test name
Test status
Simulation time 140256600 ps
CPU time 4.68 seconds
Started Mar 16 12:25:34 PM PDT 24
Finished Mar 16 12:25:40 PM PDT 24
Peak memory 208208 kb
Host smart-1297248a-0dc2-4aa8-aa3f-f0234334598c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061433883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1061433883
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2793208538
Short name T708
Test name
Test status
Simulation time 51255751 ps
CPU time 2.38 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:34 PM PDT 24
Peak memory 210460 kb
Host smart-815005b5-0ac6-4f2d-89f4-6e3afe550ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793208538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2793208538
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2892327089
Short name T787
Test name
Test status
Simulation time 38933440 ps
CPU time 0.72 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:33 PM PDT 24
Peak memory 205772 kb
Host smart-292e3c0f-5d75-4fbe-9be1-2648d02e5dc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892327089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2892327089
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3468086534
Short name T302
Test name
Test status
Simulation time 231805187 ps
CPU time 4.15 seconds
Started Mar 16 12:25:29 PM PDT 24
Finished Mar 16 12:25:33 PM PDT 24
Peak memory 215372 kb
Host smart-4375965d-eef0-40f7-87aa-911bdedd1524
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3468086534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3468086534
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.4103578868
Short name T20
Test name
Test status
Simulation time 1003849443 ps
CPU time 3.61 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:36 PM PDT 24
Peak memory 214464 kb
Host smart-18b96548-b2a4-4b4e-8efa-0202a3fc0958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103578868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.4103578868
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2332722793
Short name T66
Test name
Test status
Simulation time 144475960 ps
CPU time 3.56 seconds
Started Mar 16 12:25:31 PM PDT 24
Finished Mar 16 12:25:34 PM PDT 24
Peak memory 209472 kb
Host smart-6e0621d8-e006-40c9-a777-9222bb669c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332722793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2332722793
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.4011063339
Short name T876
Test name
Test status
Simulation time 84882931 ps
CPU time 4.13 seconds
Started Mar 16 12:25:33 PM PDT 24
Finished Mar 16 12:25:37 PM PDT 24
Peak memory 216560 kb
Host smart-b6bbd56d-83e0-4303-90f6-c00ac1459d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011063339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.4011063339
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3970930696
Short name T278
Test name
Test status
Simulation time 72444278 ps
CPU time 2.85 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:36 PM PDT 24
Peak memory 214204 kb
Host smart-86aae2a9-6e57-4cea-8d78-8f7597fa4792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970930696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3970930696
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1983958569
Short name T994
Test name
Test status
Simulation time 136249488 ps
CPU time 2.45 seconds
Started Mar 16 12:25:33 PM PDT 24
Finished Mar 16 12:25:37 PM PDT 24
Peak memory 206708 kb
Host smart-8176acf8-62e4-4c13-9d4d-f06c88643aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983958569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1983958569
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.4277518597
Short name T809
Test name
Test status
Simulation time 5107197916 ps
CPU time 48.74 seconds
Started Mar 16 12:25:35 PM PDT 24
Finished Mar 16 12:26:24 PM PDT 24
Peak memory 208520 kb
Host smart-1d8dff85-4fba-42ce-aeef-b1da15428e14
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277518597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4277518597
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1828215557
Short name T798
Test name
Test status
Simulation time 223567409 ps
CPU time 3.09 seconds
Started Mar 16 12:25:31 PM PDT 24
Finished Mar 16 12:25:34 PM PDT 24
Peak memory 207896 kb
Host smart-190b706b-05ec-4629-95db-b44d41460a84
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828215557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1828215557
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.4041203290
Short name T993
Test name
Test status
Simulation time 813674052 ps
CPU time 5.3 seconds
Started Mar 16 12:25:36 PM PDT 24
Finished Mar 16 12:25:42 PM PDT 24
Peak memory 206724 kb
Host smart-852fa562-e563-4696-8d78-f28685f92f4a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041203290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.4041203290
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3623978923
Short name T739
Test name
Test status
Simulation time 5966616132 ps
CPU time 11.58 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:44 PM PDT 24
Peak memory 216672 kb
Host smart-2cafbf37-6b1f-4fd1-9fb3-ae5fb889eafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623978923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3623978923
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.706447596
Short name T182
Test name
Test status
Simulation time 72318991 ps
CPU time 3.14 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:36 PM PDT 24
Peak memory 208152 kb
Host smart-f7ee32a8-9163-4981-bd23-4a00c28e41a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706447596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.706447596
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.4127232114
Short name T941
Test name
Test status
Simulation time 252920229 ps
CPU time 4.72 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:37 PM PDT 24
Peak memory 218728 kb
Host smart-433d4087-4008-4dc8-a91d-3f19714deb20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127232114 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.4127232114
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2086802814
Short name T178
Test name
Test status
Simulation time 112513689 ps
CPU time 4.64 seconds
Started Mar 16 12:25:41 PM PDT 24
Finished Mar 16 12:25:45 PM PDT 24
Peak memory 218040 kb
Host smart-6493a580-99b1-4c5e-8ea6-c6aacda8d941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086802814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2086802814
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.305574949
Short name T96
Test name
Test status
Simulation time 33299463 ps
CPU time 1.83 seconds
Started Mar 16 12:25:31 PM PDT 24
Finished Mar 16 12:25:33 PM PDT 24
Peak memory 209676 kb
Host smart-477f6216-dc63-40e4-ba30-f8a5c87e5fb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305574949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.305574949
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2795053477
Short name T1075
Test name
Test status
Simulation time 19582460 ps
CPU time 0.93 seconds
Started Mar 16 12:25:35 PM PDT 24
Finished Mar 16 12:25:37 PM PDT 24
Peak memory 205888 kb
Host smart-f7d25e80-2ed8-4075-9b38-583b94b62585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795053477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2795053477
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2104073730
Short name T419
Test name
Test status
Simulation time 119417678 ps
CPU time 6.23 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:38 PM PDT 24
Peak memory 214196 kb
Host smart-4b978570-9e07-4e3c-99a0-312a1d1ddd5f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2104073730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2104073730
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1149002846
Short name T1070
Test name
Test status
Simulation time 525283785 ps
CPU time 5.23 seconds
Started Mar 16 12:25:41 PM PDT 24
Finished Mar 16 12:25:46 PM PDT 24
Peak memory 221620 kb
Host smart-fea2bf18-af4f-4120-b057-f15fc8710416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149002846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1149002846
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1729649769
Short name T1
Test name
Test status
Simulation time 147465598 ps
CPU time 1.66 seconds
Started Mar 16 12:25:35 PM PDT 24
Finished Mar 16 12:25:38 PM PDT 24
Peak memory 208748 kb
Host smart-8c1090c2-7e54-4ab5-ade3-a4693d0ca94b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729649769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1729649769
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2316739117
Short name T744
Test name
Test status
Simulation time 204518782 ps
CPU time 3.76 seconds
Started Mar 16 12:25:38 PM PDT 24
Finished Mar 16 12:25:42 PM PDT 24
Peak memory 219520 kb
Host smart-c3b15f54-6397-426c-8642-529996dc948f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316739117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2316739117
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3155793968
Short name T608
Test name
Test status
Simulation time 128104518 ps
CPU time 5.21 seconds
Started Mar 16 12:25:38 PM PDT 24
Finished Mar 16 12:25:43 PM PDT 24
Peak memory 219844 kb
Host smart-125cd6b0-187e-4dce-8931-cfe6ea00c4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155793968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3155793968
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1438552437
Short name T308
Test name
Test status
Simulation time 588521954 ps
CPU time 12.31 seconds
Started Mar 16 12:25:33 PM PDT 24
Finished Mar 16 12:25:46 PM PDT 24
Peak memory 209804 kb
Host smart-304518ec-0774-4107-a585-4382ee87b508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438552437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1438552437
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3609325709
Short name T717
Test name
Test status
Simulation time 38108890 ps
CPU time 2.38 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:34 PM PDT 24
Peak memory 206864 kb
Host smart-89e5775a-ce08-4eae-9d61-033e08fa4b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609325709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3609325709
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1869949888
Short name T716
Test name
Test status
Simulation time 126074461 ps
CPU time 5.29 seconds
Started Mar 16 12:25:35 PM PDT 24
Finished Mar 16 12:25:41 PM PDT 24
Peak memory 208280 kb
Host smart-e05e584e-4350-41e2-816b-c1dab8082c77
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869949888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1869949888
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.4257033314
Short name T321
Test name
Test status
Simulation time 268950223 ps
CPU time 2.6 seconds
Started Mar 16 12:25:36 PM PDT 24
Finished Mar 16 12:25:39 PM PDT 24
Peak memory 208604 kb
Host smart-577a4cfa-efd2-45b0-917c-af300a2c8004
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257033314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.4257033314
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.250725886
Short name T981
Test name
Test status
Simulation time 206710082 ps
CPU time 3.62 seconds
Started Mar 16 12:25:32 PM PDT 24
Finished Mar 16 12:25:35 PM PDT 24
Peak memory 208320 kb
Host smart-681bc75b-7ad3-4c63-9d14-a02d929dbbdb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250725886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.250725886
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1169172599
Short name T831
Test name
Test status
Simulation time 55393651 ps
CPU time 1.8 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:25:47 PM PDT 24
Peak memory 214216 kb
Host smart-04ad3154-9ced-4aad-8ce0-223b72e702b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169172599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1169172599
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3921846391
Short name T748
Test name
Test status
Simulation time 314791316 ps
CPU time 8.3 seconds
Started Mar 16 12:25:30 PM PDT 24
Finished Mar 16 12:25:39 PM PDT 24
Peak memory 207704 kb
Host smart-e4d64f41-f543-4437-94dc-4e0963b4af7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921846391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3921846391
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.3090574347
Short name T804
Test name
Test status
Simulation time 979747028 ps
CPU time 9.16 seconds
Started Mar 16 12:25:35 PM PDT 24
Finished Mar 16 12:25:45 PM PDT 24
Peak memory 222536 kb
Host smart-6434d62b-ca11-4eb9-a9a9-66f6716ff1ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090574347 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.3090574347
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3056080155
Short name T264
Test name
Test status
Simulation time 13366344355 ps
CPU time 66.17 seconds
Started Mar 16 12:25:36 PM PDT 24
Finished Mar 16 12:26:43 PM PDT 24
Peak memory 209156 kb
Host smart-78f88e6d-1aaf-49cc-9807-96485466a820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056080155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3056080155
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1574123575
Short name T162
Test name
Test status
Simulation time 337935124 ps
CPU time 10.54 seconds
Started Mar 16 12:25:44 PM PDT 24
Finished Mar 16 12:25:55 PM PDT 24
Peak memory 210552 kb
Host smart-66bde71d-45d0-4a97-b977-8ffb387372c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574123575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1574123575
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1062127609
Short name T805
Test name
Test status
Simulation time 142488068 ps
CPU time 0.93 seconds
Started Mar 16 12:25:38 PM PDT 24
Finished Mar 16 12:25:39 PM PDT 24
Peak memory 205808 kb
Host smart-f8d068a3-b2a1-4669-984c-80959a976ab1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062127609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1062127609
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.528205301
Short name T659
Test name
Test status
Simulation time 1582455671 ps
CPU time 5.34 seconds
Started Mar 16 12:25:34 PM PDT 24
Finished Mar 16 12:25:41 PM PDT 24
Peak memory 208884 kb
Host smart-f2b9af07-13b1-44a5-9f60-9a2101207731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528205301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.528205301
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.199525571
Short name T1020
Test name
Test status
Simulation time 235421388 ps
CPU time 5.68 seconds
Started Mar 16 12:25:44 PM PDT 24
Finished Mar 16 12:25:49 PM PDT 24
Peak memory 214344 kb
Host smart-a1da8f9b-c1a0-4dae-af14-fb1a667378c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199525571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.199525571
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2440376308
Short name T179
Test name
Test status
Simulation time 152960781 ps
CPU time 6.24 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:25:53 PM PDT 24
Peak memory 222240 kb
Host smart-a82b5dd8-1253-43f0-8b23-af367f7f75c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440376308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2440376308
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1844753006
Short name T1059
Test name
Test status
Simulation time 238204060 ps
CPU time 3.86 seconds
Started Mar 16 12:25:35 PM PDT 24
Finished Mar 16 12:25:40 PM PDT 24
Peak memory 220224 kb
Host smart-0204e80f-b89f-4ae6-8d4d-be9d60ed7ec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844753006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1844753006
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2849244061
Short name T368
Test name
Test status
Simulation time 312640893 ps
CPU time 9.02 seconds
Started Mar 16 12:25:40 PM PDT 24
Finished Mar 16 12:25:50 PM PDT 24
Peak memory 208668 kb
Host smart-b956a594-f8b4-4ce9-abe2-a5c488431bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849244061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2849244061
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1446787384
Short name T274
Test name
Test status
Simulation time 790357217 ps
CPU time 13.57 seconds
Started Mar 16 12:25:44 PM PDT 24
Finished Mar 16 12:25:58 PM PDT 24
Peak memory 208668 kb
Host smart-fd2ed4f1-5d8d-4a8a-a5d2-ab23d136461c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446787384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1446787384
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2446081729
Short name T14
Test name
Test status
Simulation time 2569709103 ps
CPU time 41.09 seconds
Started Mar 16 12:25:44 PM PDT 24
Finished Mar 16 12:26:25 PM PDT 24
Peak memory 208276 kb
Host smart-b15fcd40-aaf1-442b-a94d-c4f0da1c3ad6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446081729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2446081729
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1900092510
Short name T729
Test name
Test status
Simulation time 667886157 ps
CPU time 10.03 seconds
Started Mar 16 12:25:37 PM PDT 24
Finished Mar 16 12:25:48 PM PDT 24
Peak memory 208588 kb
Host smart-cbe3c596-a156-46ed-9c99-bac6167f4ab3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900092510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1900092510
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.1491540520
Short name T244
Test name
Test status
Simulation time 264864296 ps
CPU time 3.01 seconds
Started Mar 16 12:25:39 PM PDT 24
Finished Mar 16 12:25:42 PM PDT 24
Peak memory 208376 kb
Host smart-18e779b6-0b21-47a7-a0d2-4676f4aa8a9e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491540520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.1491540520
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.790753799
Short name T421
Test name
Test status
Simulation time 59362248 ps
CPU time 2.01 seconds
Started Mar 16 12:25:38 PM PDT 24
Finished Mar 16 12:25:40 PM PDT 24
Peak memory 214156 kb
Host smart-dafac7c0-0a64-4671-8887-7fd626ecb439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790753799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.790753799
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1289296849
Short name T667
Test name
Test status
Simulation time 70939432 ps
CPU time 3.08 seconds
Started Mar 16 12:25:36 PM PDT 24
Finished Mar 16 12:25:39 PM PDT 24
Peak memory 208388 kb
Host smart-abdcd345-2607-46e3-a8e2-2134d6fc7038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289296849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1289296849
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2415452629
Short name T615
Test name
Test status
Simulation time 247318350 ps
CPU time 4.84 seconds
Started Mar 16 12:25:44 PM PDT 24
Finished Mar 16 12:25:49 PM PDT 24
Peak memory 222020 kb
Host smart-e296cc9f-0c4c-4770-a28f-bf40f3e729c0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415452629 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2415452629
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3412334723
Short name T1064
Test name
Test status
Simulation time 105073995 ps
CPU time 2.99 seconds
Started Mar 16 12:25:40 PM PDT 24
Finished Mar 16 12:25:44 PM PDT 24
Peak memory 206828 kb
Host smart-e42a1a96-eae8-4cdc-b0fe-8f2c122d6905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412334723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3412334723
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1591166947
Short name T671
Test name
Test status
Simulation time 68639957 ps
CPU time 2.21 seconds
Started Mar 16 12:25:38 PM PDT 24
Finished Mar 16 12:25:40 PM PDT 24
Peak memory 210020 kb
Host smart-c4a41cc4-0000-40da-8481-2ab01e972b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591166947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1591166947
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1248378302
Short name T692
Test name
Test status
Simulation time 49042641 ps
CPU time 0.9 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:25:48 PM PDT 24
Peak memory 205764 kb
Host smart-e0006d90-eab5-44d3-a503-ad5e45017db5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248378302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1248378302
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3804664763
Short name T747
Test name
Test status
Simulation time 1021420359 ps
CPU time 6.7 seconds
Started Mar 16 12:25:37 PM PDT 24
Finished Mar 16 12:25:44 PM PDT 24
Peak memory 209868 kb
Host smart-61f65173-02dd-4c61-888f-d5617f04a2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804664763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3804664763
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3439171920
Short name T769
Test name
Test status
Simulation time 256118341 ps
CPU time 3.4 seconds
Started Mar 16 12:25:44 PM PDT 24
Finished Mar 16 12:25:48 PM PDT 24
Peak memory 207176 kb
Host smart-a44220d1-ec59-4559-b926-6811fa3e09f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439171920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3439171920
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1649584833
Short name T389
Test name
Test status
Simulation time 199981505 ps
CPU time 5.56 seconds
Started Mar 16 12:25:38 PM PDT 24
Finished Mar 16 12:25:44 PM PDT 24
Peak memory 220128 kb
Host smart-1598b81a-0e01-429f-8da0-ed063d91bf9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649584833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1649584833
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.4165952445
Short name T43
Test name
Test status
Simulation time 118393923 ps
CPU time 2.37 seconds
Started Mar 16 12:25:39 PM PDT 24
Finished Mar 16 12:25:41 PM PDT 24
Peak memory 220064 kb
Host smart-8e8dd583-7715-4a54-91e5-91d282630d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165952445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.4165952445
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.561478783
Short name T971
Test name
Test status
Simulation time 4926490216 ps
CPU time 64.95 seconds
Started Mar 16 12:25:44 PM PDT 24
Finished Mar 16 12:26:49 PM PDT 24
Peak memory 208728 kb
Host smart-6a7d2cbc-9c5c-493e-97ec-f68f55ebc5e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561478783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.561478783
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3142373702
Short name T281
Test name
Test status
Simulation time 64671538 ps
CPU time 3.09 seconds
Started Mar 16 12:25:35 PM PDT 24
Finished Mar 16 12:25:39 PM PDT 24
Peak memory 208672 kb
Host smart-f6d2adce-788c-403b-957f-0881b6c2e603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142373702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3142373702
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3758012939
Short name T1017
Test name
Test status
Simulation time 37512628 ps
CPU time 2.67 seconds
Started Mar 16 12:25:33 PM PDT 24
Finished Mar 16 12:25:37 PM PDT 24
Peak memory 208516 kb
Host smart-894fc468-c006-4ef2-8248-c0f91021621c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758012939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3758012939
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.4211116873
Short name T882
Test name
Test status
Simulation time 141793981 ps
CPU time 2.66 seconds
Started Mar 16 12:25:40 PM PDT 24
Finished Mar 16 12:25:43 PM PDT 24
Peak memory 206784 kb
Host smart-d78dd0fc-8760-4ff3-b6de-eb3d1e83928b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211116873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.4211116873
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1900317801
Short name T1003
Test name
Test status
Simulation time 1835357253 ps
CPU time 60.78 seconds
Started Mar 16 12:25:36 PM PDT 24
Finished Mar 16 12:26:37 PM PDT 24
Peak memory 208832 kb
Host smart-dcc7c97d-621f-46d3-b743-7cf2a76fbf6a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900317801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1900317801
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2414466873
Short name T731
Test name
Test status
Simulation time 332705313 ps
CPU time 2.87 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:25:50 PM PDT 24
Peak memory 209964 kb
Host smart-20ca5920-7d12-4a5f-825c-3f5453915706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414466873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2414466873
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2163647976
Short name T943
Test name
Test status
Simulation time 376558163 ps
CPU time 5.02 seconds
Started Mar 16 12:25:44 PM PDT 24
Finished Mar 16 12:25:50 PM PDT 24
Peak memory 208368 kb
Host smart-79ccbea6-5d06-4c87-a328-e402bca57189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163647976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2163647976
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3332022513
Short name T954
Test name
Test status
Simulation time 84183529 ps
CPU time 2.84 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:25:49 PM PDT 24
Peak memory 214280 kb
Host smart-7eed3fc8-08c1-470f-a1bf-9721710e2a18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332022513 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3332022513
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2894224663
Short name T958
Test name
Test status
Simulation time 196789128 ps
CPU time 7.64 seconds
Started Mar 16 12:25:36 PM PDT 24
Finished Mar 16 12:25:44 PM PDT 24
Peak memory 214152 kb
Host smart-e6884425-7a03-4caa-9eff-7d8ca9e16c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894224663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2894224663
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.626257750
Short name T35
Test name
Test status
Simulation time 240554788 ps
CPU time 2.05 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:25:48 PM PDT 24
Peak memory 209792 kb
Host smart-5c58db3a-6e00-499c-8f44-9fd43b62da67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626257750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.626257750
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.184237923
Short name T690
Test name
Test status
Simulation time 108490594 ps
CPU time 0.83 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:25:48 PM PDT 24
Peak memory 205708 kb
Host smart-deda5933-6f98-4713-bdad-a6a3e2d35d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184237923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.184237923
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3459656704
Short name T431
Test name
Test status
Simulation time 2269393946 ps
CPU time 66.58 seconds
Started Mar 16 12:25:39 PM PDT 24
Finished Mar 16 12:26:46 PM PDT 24
Peak memory 222356 kb
Host smart-cdeeefbf-0c3e-441b-b369-e78acb1aaf15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3459656704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3459656704
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.27198181
Short name T871
Test name
Test status
Simulation time 507929324 ps
CPU time 4.27 seconds
Started Mar 16 12:25:42 PM PDT 24
Finished Mar 16 12:25:46 PM PDT 24
Peak memory 214624 kb
Host smart-9e85a767-19a8-426d-96aa-5280bd676d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27198181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.27198181
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.121919309
Short name T56
Test name
Test status
Simulation time 135935914 ps
CPU time 4.34 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:25:49 PM PDT 24
Peak memory 207796 kb
Host smart-816c90ef-c13e-4c0c-965e-50057c0f4c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121919309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.121919309
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1962579950
Short name T94
Test name
Test status
Simulation time 41343649 ps
CPU time 3.23 seconds
Started Mar 16 12:25:53 PM PDT 24
Finished Mar 16 12:25:57 PM PDT 24
Peak memory 220540 kb
Host smart-12336dc0-066a-4ca6-a1e8-da74f236235a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962579950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1962579950
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3997671909
Short name T186
Test name
Test status
Simulation time 109354340 ps
CPU time 5.04 seconds
Started Mar 16 12:25:48 PM PDT 24
Finished Mar 16 12:25:54 PM PDT 24
Peak memory 222356 kb
Host smart-1bf585cc-8beb-401c-9757-8a84055ee5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997671909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3997671909
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2589855362
Short name T61
Test name
Test status
Simulation time 49986933 ps
CPU time 3.66 seconds
Started Mar 16 12:25:44 PM PDT 24
Finished Mar 16 12:25:48 PM PDT 24
Peak memory 209404 kb
Host smart-c2b7f18a-f242-4072-8eb0-b545d308e0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589855362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2589855362
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1959639675
Short name T340
Test name
Test status
Simulation time 2295790405 ps
CPU time 50.22 seconds
Started Mar 16 12:25:40 PM PDT 24
Finished Mar 16 12:26:30 PM PDT 24
Peak memory 208300 kb
Host smart-4822b550-f8fe-4b2d-93da-2e706290df3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959639675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1959639675
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.15642925
Short name T755
Test name
Test status
Simulation time 124724900 ps
CPU time 3.32 seconds
Started Mar 16 12:25:40 PM PDT 24
Finished Mar 16 12:25:44 PM PDT 24
Peak memory 206568 kb
Host smart-ecacee9a-38dd-4e1c-a87e-b61852db8d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15642925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.15642925
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3973937173
Short name T839
Test name
Test status
Simulation time 223701212 ps
CPU time 6.03 seconds
Started Mar 16 12:25:44 PM PDT 24
Finished Mar 16 12:25:50 PM PDT 24
Peak memory 207668 kb
Host smart-fe2302f7-40af-478c-8339-6e81ece3734d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973937173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3973937173
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1880865123
Short name T647
Test name
Test status
Simulation time 43185189 ps
CPU time 2.53 seconds
Started Mar 16 12:25:38 PM PDT 24
Finished Mar 16 12:25:41 PM PDT 24
Peak memory 206624 kb
Host smart-24702a9b-b953-4094-87c3-aae46bd4bd3c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880865123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1880865123
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2461803031
Short name T961
Test name
Test status
Simulation time 110252270 ps
CPU time 2.65 seconds
Started Mar 16 12:25:40 PM PDT 24
Finished Mar 16 12:25:42 PM PDT 24
Peak memory 208592 kb
Host smart-261639ef-339d-4431-94ff-251331584d3b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461803031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2461803031
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2343440781
Short name T417
Test name
Test status
Simulation time 47068563 ps
CPU time 1.94 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:25:49 PM PDT 24
Peak memory 207312 kb
Host smart-4c4c35ef-fcc4-4cee-9744-4134f31be74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343440781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2343440781
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1604522095
Short name T618
Test name
Test status
Simulation time 1707087422 ps
CPU time 19.92 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:26:07 PM PDT 24
Peak memory 207924 kb
Host smart-32d52620-586b-475a-88ae-6f07160e961f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604522095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1604522095
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2251822738
Short name T696
Test name
Test status
Simulation time 42881807 ps
CPU time 2.64 seconds
Started Mar 16 12:25:42 PM PDT 24
Finished Mar 16 12:25:45 PM PDT 24
Peak memory 208864 kb
Host smart-2107c5de-69e2-4d4f-a4d6-2f84be258479
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251822738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2251822738
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2911862112
Short name T999
Test name
Test status
Simulation time 366355843 ps
CPU time 6.62 seconds
Started Mar 16 12:25:50 PM PDT 24
Finished Mar 16 12:25:58 PM PDT 24
Peak memory 222312 kb
Host smart-a60c1243-4000-4e05-b338-a8fbed043eec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911862112 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2911862112
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.21982969
Short name T74
Test name
Test status
Simulation time 53474265 ps
CPU time 3.05 seconds
Started Mar 16 12:25:38 PM PDT 24
Finished Mar 16 12:25:41 PM PDT 24
Peak memory 209024 kb
Host smart-344d30ff-f762-420b-8c42-07e1cdd23a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21982969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.21982969
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2919206034
Short name T757
Test name
Test status
Simulation time 539002846 ps
CPU time 3.36 seconds
Started Mar 16 12:25:42 PM PDT 24
Finished Mar 16 12:25:46 PM PDT 24
Peak memory 210980 kb
Host smart-0c1b1297-bf58-4daa-89d7-c1550e10e65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919206034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2919206034
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2598895068
Short name T749
Test name
Test status
Simulation time 43638760 ps
CPU time 0.74 seconds
Started Mar 16 12:25:38 PM PDT 24
Finished Mar 16 12:25:39 PM PDT 24
Peak memory 205820 kb
Host smart-0100a4b8-d1ff-411d-9982-0cde76651e64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598895068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2598895068
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1108675762
Short name T257
Test name
Test status
Simulation time 1676748217 ps
CPU time 7.93 seconds
Started Mar 16 12:25:43 PM PDT 24
Finished Mar 16 12:25:51 PM PDT 24
Peak memory 214192 kb
Host smart-39ad6214-2820-4573-8a9c-2834f818921a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1108675762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1108675762
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1501010866
Short name T927
Test name
Test status
Simulation time 482849900 ps
CPU time 4.24 seconds
Started Mar 16 12:25:52 PM PDT 24
Finished Mar 16 12:25:57 PM PDT 24
Peak memory 214112 kb
Host smart-d40bc559-6c75-4c82-b7de-6445e83a3808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501010866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1501010866
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2391053349
Short name T919
Test name
Test status
Simulation time 46428908 ps
CPU time 1.65 seconds
Started Mar 16 12:25:43 PM PDT 24
Finished Mar 16 12:25:50 PM PDT 24
Peak memory 208260 kb
Host smart-263f1568-1cde-481b-af86-f6e7f19854e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391053349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2391053349
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1650925117
Short name T371
Test name
Test status
Simulation time 785304357 ps
CPU time 5.58 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:25:51 PM PDT 24
Peak memory 214124 kb
Host smart-bf3286d8-185a-4cbd-9d4e-8c4eec19791e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650925117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1650925117
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.4262605286
Short name T819
Test name
Test status
Simulation time 85722132 ps
CPU time 2.95 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:25:49 PM PDT 24
Peak memory 214132 kb
Host smart-e403c2b3-af44-4070-9696-6157c8a6bbf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262605286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.4262605286
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1075672581
Short name T385
Test name
Test status
Simulation time 218122838 ps
CPU time 3.21 seconds
Started Mar 16 12:25:43 PM PDT 24
Finished Mar 16 12:25:46 PM PDT 24
Peak memory 207524 kb
Host smart-6f2031b9-7df0-453b-ad28-446cf70562a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075672581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1075672581
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.290625908
Short name T826
Test name
Test status
Simulation time 876715557 ps
CPU time 12.9 seconds
Started Mar 16 12:25:50 PM PDT 24
Finished Mar 16 12:26:04 PM PDT 24
Peak memory 208684 kb
Host smart-49f6d477-d28e-4954-b28d-459c662b5ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290625908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.290625908
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.4133240272
Short name T784
Test name
Test status
Simulation time 220355960 ps
CPU time 4.3 seconds
Started Mar 16 12:25:42 PM PDT 24
Finished Mar 16 12:25:46 PM PDT 24
Peak memory 207336 kb
Host smart-c831ba78-abff-48ff-b289-742f35da6e8f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133240272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4133240272
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2196882614
Short name T847
Test name
Test status
Simulation time 41065415 ps
CPU time 1.78 seconds
Started Mar 16 12:25:52 PM PDT 24
Finished Mar 16 12:25:55 PM PDT 24
Peak memory 206780 kb
Host smart-40468bdc-19d0-46b7-8eed-507e8efe580d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196882614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2196882614
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.848944157
Short name T183
Test name
Test status
Simulation time 659704689 ps
CPU time 13.16 seconds
Started Mar 16 12:25:50 PM PDT 24
Finished Mar 16 12:26:05 PM PDT 24
Peak memory 208092 kb
Host smart-86b93d37-beb2-44f6-a619-158f688cad3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848944157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.848944157
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.148958116
Short name T597
Test name
Test status
Simulation time 179125180 ps
CPU time 2.46 seconds
Started Mar 16 12:25:35 PM PDT 24
Finished Mar 16 12:25:38 PM PDT 24
Peak memory 208324 kb
Host smart-1058781f-663a-4566-bdd2-ab009d8d57e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148958116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.148958116
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1349795872
Short name T106
Test name
Test status
Simulation time 158804550 ps
CPU time 3.07 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:25:49 PM PDT 24
Peak memory 216468 kb
Host smart-e71c07aa-44ae-4c79-9682-0d4a35a81ed8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349795872 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1349795872
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2210380834
Short name T187
Test name
Test status
Simulation time 328910396 ps
CPU time 7.96 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:25:54 PM PDT 24
Peak memory 209036 kb
Host smart-eba298dd-3092-4c10-909b-a4f30eafeeaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210380834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2210380834
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1416023352
Short name T1039
Test name
Test status
Simulation time 316255487 ps
CPU time 3.52 seconds
Started Mar 16 12:25:40 PM PDT 24
Finished Mar 16 12:25:43 PM PDT 24
Peak memory 209784 kb
Host smart-62c63df9-e6b2-4b63-9610-9bab4c710804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416023352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1416023352
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3866579746
Short name T613
Test name
Test status
Simulation time 13952208 ps
CPU time 0.73 seconds
Started Mar 16 12:25:42 PM PDT 24
Finished Mar 16 12:25:43 PM PDT 24
Peak memory 205740 kb
Host smart-64ea2f48-55f9-4fce-988c-52e0f885183f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866579746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3866579746
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1246582441
Short name T217
Test name
Test status
Simulation time 294950017 ps
CPU time 9.02 seconds
Started Mar 16 12:25:43 PM PDT 24
Finished Mar 16 12:25:52 PM PDT 24
Peak memory 214088 kb
Host smart-b52e450a-6085-49ef-b6dd-c1c3b87290f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1246582441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1246582441
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.726257448
Short name T642
Test name
Test status
Simulation time 480014296 ps
CPU time 12.47 seconds
Started Mar 16 12:25:43 PM PDT 24
Finished Mar 16 12:25:55 PM PDT 24
Peak memory 208952 kb
Host smart-79df1312-ca86-4e63-a375-480bfe963813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=726257448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.726257448
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.830271385
Short name T297
Test name
Test status
Simulation time 1201337770 ps
CPU time 7.02 seconds
Started Mar 16 12:26:09 PM PDT 24
Finished Mar 16 12:26:17 PM PDT 24
Peak memory 208296 kb
Host smart-e8d9c541-6b39-4ba6-b7d7-da395fa6749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830271385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.830271385
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.270183361
Short name T724
Test name
Test status
Simulation time 1546231665 ps
CPU time 17.39 seconds
Started Mar 16 12:25:54 PM PDT 24
Finished Mar 16 12:26:12 PM PDT 24
Peak memory 214204 kb
Host smart-8c84c4b0-02d1-4611-a011-4952069c5344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270183361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.270183361
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_random.2051131868
Short name T352
Test name
Test status
Simulation time 818886092 ps
CPU time 8.88 seconds
Started Mar 16 12:25:41 PM PDT 24
Finished Mar 16 12:25:50 PM PDT 24
Peak memory 218048 kb
Host smart-390d1f43-bba8-4654-987c-95458ac7bcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051131868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2051131868
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.169274897
Short name T333
Test name
Test status
Simulation time 126795556 ps
CPU time 2.13 seconds
Started Mar 16 12:25:59 PM PDT 24
Finished Mar 16 12:26:01 PM PDT 24
Peak memory 206644 kb
Host smart-ad372a2f-3f72-43c9-a8e7-e37ca759f8d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169274897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.169274897
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2888764231
Short name T711
Test name
Test status
Simulation time 68618370 ps
CPU time 3.08 seconds
Started Mar 16 12:26:01 PM PDT 24
Finished Mar 16 12:26:04 PM PDT 24
Peak memory 206908 kb
Host smart-d573c9f2-81ed-4ab3-9263-46148bd112ea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888764231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2888764231
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.686630844
Short name T775
Test name
Test status
Simulation time 59773070 ps
CPU time 2.27 seconds
Started Mar 16 12:25:42 PM PDT 24
Finished Mar 16 12:25:44 PM PDT 24
Peak memory 206708 kb
Host smart-95d61e93-8a99-4f85-9bd9-85c1e79a878b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686630844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.686630844
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.260502611
Short name T803
Test name
Test status
Simulation time 79190707 ps
CPU time 2.94 seconds
Started Mar 16 12:25:53 PM PDT 24
Finished Mar 16 12:25:57 PM PDT 24
Peak memory 206916 kb
Host smart-8f89a7ab-f812-4774-8742-7d4e1131f4ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260502611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.260502611
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2191539276
Short name T686
Test name
Test status
Simulation time 193021088 ps
CPU time 1.72 seconds
Started Mar 16 12:25:42 PM PDT 24
Finished Mar 16 12:25:43 PM PDT 24
Peak memory 208264 kb
Host smart-5820ffc1-9a98-42cf-a18b-24eba3d18267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191539276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2191539276
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.4183798913
Short name T906
Test name
Test status
Simulation time 710059391 ps
CPU time 7.47 seconds
Started Mar 16 12:26:10 PM PDT 24
Finished Mar 16 12:26:17 PM PDT 24
Peak memory 208352 kb
Host smart-77346d60-85ee-4baa-932d-f8eebd46d684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183798913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.4183798913
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1593854510
Short name T350
Test name
Test status
Simulation time 12213020649 ps
CPU time 363.95 seconds
Started Mar 16 12:25:44 PM PDT 24
Finished Mar 16 12:31:48 PM PDT 24
Peak memory 223344 kb
Host smart-431d4d01-f893-4ad1-91e2-c86c7a67e5a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593854510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1593854510
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3451433610
Short name T320
Test name
Test status
Simulation time 299461171 ps
CPU time 5.32 seconds
Started Mar 16 12:25:45 PM PDT 24
Finished Mar 16 12:25:52 PM PDT 24
Peak memory 219136 kb
Host smart-016a7157-a9b3-43da-b78d-2cde19e0cbe2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451433610 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3451433610
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1023667779
Short name T728
Test name
Test status
Simulation time 438631303 ps
CPU time 5.09 seconds
Started Mar 16 12:25:54 PM PDT 24
Finished Mar 16 12:26:00 PM PDT 24
Peak memory 208000 kb
Host smart-2beb1be4-057b-40ec-a0e5-d7a534586aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023667779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1023667779
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2879986498
Short name T726
Test name
Test status
Simulation time 2319943729 ps
CPU time 5.85 seconds
Started Mar 16 12:25:40 PM PDT 24
Finished Mar 16 12:25:46 PM PDT 24
Peak memory 210336 kb
Host smart-a3d18ebf-e4d3-44f1-a7e3-acbbe5503097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879986498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2879986498
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2653729217
Short name T577
Test name
Test status
Simulation time 14180108 ps
CPU time 0.77 seconds
Started Mar 16 12:23:44 PM PDT 24
Finished Mar 16 12:23:45 PM PDT 24
Peak memory 205756 kb
Host smart-5d607586-8d7a-4a5c-ab5c-3621544cb3ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653729217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2653729217
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.605237347
Short name T380
Test name
Test status
Simulation time 759831435 ps
CPU time 7.72 seconds
Started Mar 16 12:23:45 PM PDT 24
Finished Mar 16 12:23:52 PM PDT 24
Peak memory 214268 kb
Host smart-a093e927-bbcf-4471-a49a-245d1b736d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605237347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.605237347
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1302253713
Short name T888
Test name
Test status
Simulation time 63106825 ps
CPU time 2.47 seconds
Started Mar 16 12:23:40 PM PDT 24
Finished Mar 16 12:23:43 PM PDT 24
Peak memory 214292 kb
Host smart-578c5fc9-3e74-4291-9268-0fb9d1939446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302253713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1302253713
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1391337806
Short name T270
Test name
Test status
Simulation time 1427860690 ps
CPU time 5.41 seconds
Started Mar 16 12:23:50 PM PDT 24
Finished Mar 16 12:23:55 PM PDT 24
Peak memory 214108 kb
Host smart-62b4e841-1779-493e-9629-fa3a8ff50e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391337806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1391337806
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.495383500
Short name T432
Test name
Test status
Simulation time 242364662 ps
CPU time 3.64 seconds
Started Mar 16 12:23:34 PM PDT 24
Finished Mar 16 12:23:37 PM PDT 24
Peak memory 206248 kb
Host smart-764650af-2892-4ced-accb-6b035e5df842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495383500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.495383500
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3663354485
Short name T657
Test name
Test status
Simulation time 283840649 ps
CPU time 6.56 seconds
Started Mar 16 12:23:45 PM PDT 24
Finished Mar 16 12:23:51 PM PDT 24
Peak memory 214124 kb
Host smart-2dfd1600-58f3-4477-b963-f237a9f77611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663354485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3663354485
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2481837739
Short name T935
Test name
Test status
Simulation time 122748243 ps
CPU time 2.64 seconds
Started Mar 16 12:23:46 PM PDT 24
Finished Mar 16 12:23:49 PM PDT 24
Peak memory 207052 kb
Host smart-aa69f5e0-6852-4d72-971d-5fb3281601de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481837739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2481837739
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2026999249
Short name T1029
Test name
Test status
Simulation time 391661199 ps
CPU time 7.94 seconds
Started Mar 16 12:23:45 PM PDT 24
Finished Mar 16 12:23:53 PM PDT 24
Peak memory 208028 kb
Host smart-9c8d3688-3fe1-43a8-951b-da0ca40c0a52
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026999249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2026999249
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.603908656
Short name T631
Test name
Test status
Simulation time 47967641 ps
CPU time 2.16 seconds
Started Mar 16 12:23:45 PM PDT 24
Finished Mar 16 12:23:47 PM PDT 24
Peak memory 208612 kb
Host smart-0f86a5e2-165c-4fb6-aeac-e92ba44bdd8b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603908656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.603908656
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3676802628
Short name T723
Test name
Test status
Simulation time 340233471 ps
CPU time 3.85 seconds
Started Mar 16 12:23:50 PM PDT 24
Finished Mar 16 12:23:54 PM PDT 24
Peak memory 208516 kb
Host smart-014c09f3-db68-4606-990f-7bbd27ff6dcf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676802628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3676802628
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3917822564
Short name T688
Test name
Test status
Simulation time 104125730 ps
CPU time 2.38 seconds
Started Mar 16 12:23:36 PM PDT 24
Finished Mar 16 12:23:39 PM PDT 24
Peak memory 215696 kb
Host smart-d17b8a5e-bb3c-456b-bc85-67adc2938559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917822564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3917822564
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.528746365
Short name T965
Test name
Test status
Simulation time 1728643234 ps
CPU time 40.22 seconds
Started Mar 16 12:23:45 PM PDT 24
Finished Mar 16 12:24:25 PM PDT 24
Peak memory 207724 kb
Host smart-bf6bdc06-a504-44d0-a4a9-a5714a3b519b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528746365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.528746365
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.4269676220
Short name T327
Test name
Test status
Simulation time 5038604669 ps
CPU time 38.75 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:24:18 PM PDT 24
Peak memory 215192 kb
Host smart-8a4114f7-1d31-4965-a3f5-e9c82bd05060
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269676220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.4269676220
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.320251566
Short name T896
Test name
Test status
Simulation time 354356181 ps
CPU time 2.92 seconds
Started Mar 16 12:23:43 PM PDT 24
Finished Mar 16 12:23:46 PM PDT 24
Peak memory 222392 kb
Host smart-879039a2-9315-417a-8351-5ad304aa2f74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320251566 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.320251566
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1657867716
Short name T854
Test name
Test status
Simulation time 686913816 ps
CPU time 8 seconds
Started Mar 16 12:23:49 PM PDT 24
Finished Mar 16 12:23:57 PM PDT 24
Peak memory 208972 kb
Host smart-fb891077-4837-4e7f-9020-148ad3c06080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657867716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1657867716
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2497290922
Short name T51
Test name
Test status
Simulation time 82861180 ps
CPU time 3.23 seconds
Started Mar 16 12:23:43 PM PDT 24
Finished Mar 16 12:23:46 PM PDT 24
Peak memory 209912 kb
Host smart-2254f62d-4e9d-4971-a137-84c81a4d38dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497290922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2497290922
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1509564397
Short name T751
Test name
Test status
Simulation time 44016117 ps
CPU time 0.68 seconds
Started Mar 16 12:23:57 PM PDT 24
Finished Mar 16 12:23:59 PM PDT 24
Peak memory 205784 kb
Host smart-4ba54b28-c031-4479-ac2b-e85dbcb99d88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509564397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1509564397
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1503572333
Short name T293
Test name
Test status
Simulation time 128259548 ps
CPU time 4.1 seconds
Started Mar 16 12:23:47 PM PDT 24
Finished Mar 16 12:23:52 PM PDT 24
Peak memory 214280 kb
Host smart-4ba62d99-1ef1-4a32-8e64-63059d1e8533
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1503572333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1503572333
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.93931355
Short name T866
Test name
Test status
Simulation time 973849802 ps
CPU time 4.36 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:23:43 PM PDT 24
Peak memory 207848 kb
Host smart-54438644-3d7a-47d7-9a75-df635ca97947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93931355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.93931355
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1443188149
Short name T675
Test name
Test status
Simulation time 321710337 ps
CPU time 3.62 seconds
Started Mar 16 12:23:38 PM PDT 24
Finished Mar 16 12:23:42 PM PDT 24
Peak memory 210028 kb
Host smart-c6774b11-f3bd-4c62-ab2c-d4810ebc02eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443188149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1443188149
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.578491139
Short name T95
Test name
Test status
Simulation time 214843529 ps
CPU time 5.09 seconds
Started Mar 16 12:23:46 PM PDT 24
Finished Mar 16 12:23:52 PM PDT 24
Peak memory 209728 kb
Host smart-afe76113-91b3-4ae8-b571-009020d3b472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578491139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.578491139
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.4261940151
Short name T1056
Test name
Test status
Simulation time 131162949 ps
CPU time 3.88 seconds
Started Mar 16 12:23:51 PM PDT 24
Finished Mar 16 12:23:57 PM PDT 24
Peak memory 214216 kb
Host smart-3253ed64-3b47-49da-a6b8-d751174dadf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261940151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.4261940151
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3728957120
Short name T789
Test name
Test status
Simulation time 308498343 ps
CPU time 7.87 seconds
Started Mar 16 12:23:50 PM PDT 24
Finished Mar 16 12:23:58 PM PDT 24
Peak memory 214192 kb
Host smart-c4f2619d-1a03-4a4f-8a4a-608589cb4211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728957120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3728957120
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3444260829
Short name T607
Test name
Test status
Simulation time 2649006725 ps
CPU time 26.08 seconds
Started Mar 16 12:23:46 PM PDT 24
Finished Mar 16 12:24:13 PM PDT 24
Peak memory 207784 kb
Host smart-3f76caf4-503b-4466-aa40-af9e4441e8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444260829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3444260829
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1960396748
Short name T643
Test name
Test status
Simulation time 34475963 ps
CPU time 1.93 seconds
Started Mar 16 12:23:37 PM PDT 24
Finished Mar 16 12:23:39 PM PDT 24
Peak memory 208652 kb
Host smart-7d2dbbbd-9e29-4abc-a251-b3ad7e3785b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960396748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1960396748
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2504835791
Short name T998
Test name
Test status
Simulation time 354762839 ps
CPU time 3.24 seconds
Started Mar 16 12:23:50 PM PDT 24
Finished Mar 16 12:23:53 PM PDT 24
Peak memory 206756 kb
Host smart-bd263800-922e-43ba-a4c8-d238e6398dbe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504835791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2504835791
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.217722319
Short name T581
Test name
Test status
Simulation time 119589584 ps
CPU time 2.84 seconds
Started Mar 16 12:23:40 PM PDT 24
Finished Mar 16 12:23:43 PM PDT 24
Peak memory 206660 kb
Host smart-dfbb5eba-5ccb-4b27-9bf7-05a96618761d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217722319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.217722319
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.450488318
Short name T830
Test name
Test status
Simulation time 1877704540 ps
CPU time 5.29 seconds
Started Mar 16 12:23:38 PM PDT 24
Finished Mar 16 12:23:44 PM PDT 24
Peak memory 215616 kb
Host smart-3fc895a7-4e61-4f50-b8e7-7a69ba1a7551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450488318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.450488318
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1081678444
Short name T620
Test name
Test status
Simulation time 80999497 ps
CPU time 3.47 seconds
Started Mar 16 12:23:47 PM PDT 24
Finished Mar 16 12:23:51 PM PDT 24
Peak memory 207600 kb
Host smart-a4112d74-e5f2-4e48-aaab-7372a17fe57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081678444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1081678444
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2360685062
Short name T71
Test name
Test status
Simulation time 1262013232 ps
CPU time 46.47 seconds
Started Mar 16 12:23:38 PM PDT 24
Finished Mar 16 12:24:25 PM PDT 24
Peak memory 222336 kb
Host smart-892438ca-4715-4130-8db0-9ebb76900cb7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360685062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2360685062
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.4183987847
Short name T219
Test name
Test status
Simulation time 535304077 ps
CPU time 4.45 seconds
Started Mar 16 12:23:48 PM PDT 24
Finished Mar 16 12:23:52 PM PDT 24
Peak memory 207716 kb
Host smart-4f8c8699-3945-4c3f-987e-dfecfeb4edfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183987847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.4183987847
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.83284365
Short name T827
Test name
Test status
Simulation time 116329817 ps
CPU time 4.13 seconds
Started Mar 16 12:23:40 PM PDT 24
Finished Mar 16 12:23:44 PM PDT 24
Peak memory 210668 kb
Host smart-2ba1f81a-8dea-48a4-935e-c1ff4496e678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83284365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.83284365
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3417948163
Short name T707
Test name
Test status
Simulation time 48771911 ps
CPU time 0.76 seconds
Started Mar 16 12:23:38 PM PDT 24
Finished Mar 16 12:23:39 PM PDT 24
Peak memory 205888 kb
Host smart-b5244b43-0761-47a7-9e5d-b41348a25a58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417948163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3417948163
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2737714083
Short name T428
Test name
Test status
Simulation time 213373075 ps
CPU time 3.74 seconds
Started Mar 16 12:23:49 PM PDT 24
Finished Mar 16 12:23:53 PM PDT 24
Peak memory 215008 kb
Host smart-ed5e7839-1d73-4684-b324-e746836d1db2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2737714083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2737714083
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.999642916
Short name T403
Test name
Test status
Simulation time 188603209 ps
CPU time 2.77 seconds
Started Mar 16 12:23:59 PM PDT 24
Finished Mar 16 12:24:03 PM PDT 24
Peak memory 208872 kb
Host smart-e0609f97-0a69-4094-a908-15f87575c368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999642916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.999642916
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1476020820
Short name T70
Test name
Test status
Simulation time 83920399 ps
CPU time 1.76 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:23:40 PM PDT 24
Peak memory 207316 kb
Host smart-ad580e12-27c8-4a11-b506-d34000e8fac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476020820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1476020820
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3575067034
Short name T277
Test name
Test status
Simulation time 211149556 ps
CPU time 2.92 seconds
Started Mar 16 12:23:44 PM PDT 24
Finished Mar 16 12:23:48 PM PDT 24
Peak memory 208072 kb
Host smart-8709c332-528a-4e11-9ea1-e36143b4fac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575067034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3575067034
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1618579707
Short name T260
Test name
Test status
Simulation time 359377442 ps
CPU time 4.86 seconds
Started Mar 16 12:23:49 PM PDT 24
Finished Mar 16 12:23:54 PM PDT 24
Peak memory 214184 kb
Host smart-52762209-acae-4c3c-ad4d-c5a0f608e148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618579707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1618579707
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1519745616
Short name T664
Test name
Test status
Simulation time 48487400 ps
CPU time 2.94 seconds
Started Mar 16 12:23:38 PM PDT 24
Finished Mar 16 12:23:41 PM PDT 24
Peak memory 208288 kb
Host smart-5f3f9b92-64ff-47b2-a2c9-1e0aa6caf089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519745616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1519745616
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.229253146
Short name T386
Test name
Test status
Simulation time 179425602 ps
CPU time 5.1 seconds
Started Mar 16 12:23:58 PM PDT 24
Finished Mar 16 12:24:04 PM PDT 24
Peak memory 207996 kb
Host smart-7b449075-ede0-4725-b3d4-9d056ab8b69e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229253146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.229253146
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.4199232942
Short name T1037
Test name
Test status
Simulation time 221503112 ps
CPU time 3.55 seconds
Started Mar 16 12:23:46 PM PDT 24
Finished Mar 16 12:23:50 PM PDT 24
Peak memory 207164 kb
Host smart-060ca7be-4f24-44a0-89f1-178f8e4ebafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199232942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.4199232942
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.572230308
Short name T1045
Test name
Test status
Simulation time 982561304 ps
CPU time 10.2 seconds
Started Mar 16 12:23:45 PM PDT 24
Finished Mar 16 12:23:55 PM PDT 24
Peak memory 206704 kb
Host smart-57e9c3f7-6f88-4f80-a299-7446b12bc931
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572230308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.572230308
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3925339819
Short name T1043
Test name
Test status
Simulation time 220960468 ps
CPU time 3.15 seconds
Started Mar 16 12:23:52 PM PDT 24
Finished Mar 16 12:23:58 PM PDT 24
Peak memory 207440 kb
Host smart-e6887bcf-7533-445e-a1a7-46bae2a5ca93
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925339819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3925339819
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3858612086
Short name T339
Test name
Test status
Simulation time 239870923 ps
CPU time 3.14 seconds
Started Mar 16 12:23:37 PM PDT 24
Finished Mar 16 12:23:40 PM PDT 24
Peak memory 206816 kb
Host smart-373523f8-2245-4cf0-87e6-18069ff82a2e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858612086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3858612086
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3862985580
Short name T280
Test name
Test status
Simulation time 107262693 ps
CPU time 4.26 seconds
Started Mar 16 12:23:41 PM PDT 24
Finished Mar 16 12:23:46 PM PDT 24
Peak memory 218524 kb
Host smart-88b6e751-a615-46f5-a6e7-ed4e6c7ea6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862985580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3862985580
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.324773052
Short name T793
Test name
Test status
Simulation time 2023712156 ps
CPU time 6.23 seconds
Started Mar 16 12:23:53 PM PDT 24
Finished Mar 16 12:24:02 PM PDT 24
Peak memory 208192 kb
Host smart-f80a02c7-4fd1-4262-8273-8e58e0533b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324773052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.324773052
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1214171740
Short name T357
Test name
Test status
Simulation time 433782018 ps
CPU time 5.01 seconds
Started Mar 16 12:23:47 PM PDT 24
Finished Mar 16 12:23:53 PM PDT 24
Peak memory 208500 kb
Host smart-ef117dec-85a6-496b-be27-3842fc2bcac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214171740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1214171740
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3828139239
Short name T884
Test name
Test status
Simulation time 469298730 ps
CPU time 4.84 seconds
Started Mar 16 12:23:46 PM PDT 24
Finished Mar 16 12:23:52 PM PDT 24
Peak memory 210064 kb
Host smart-f43f1d57-63a5-4363-9580-8750d14c00cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828139239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3828139239
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1788556143
Short name T616
Test name
Test status
Simulation time 9171248 ps
CPU time 0.74 seconds
Started Mar 16 12:23:45 PM PDT 24
Finished Mar 16 12:23:46 PM PDT 24
Peak memory 205888 kb
Host smart-1cd71923-3068-4419-9b5d-1f8cbc4a0971
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788556143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1788556143
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3070054684
Short name T892
Test name
Test status
Simulation time 220253649 ps
CPU time 3.22 seconds
Started Mar 16 12:23:41 PM PDT 24
Finished Mar 16 12:23:45 PM PDT 24
Peak memory 214252 kb
Host smart-b30d492b-3e60-480c-9503-bbaffff559ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070054684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3070054684
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.41296387
Short name T782
Test name
Test status
Simulation time 218812838 ps
CPU time 4.93 seconds
Started Mar 16 12:26:13 PM PDT 24
Finished Mar 16 12:26:18 PM PDT 24
Peak memory 214580 kb
Host smart-cdbc087d-7a0f-45c0-a52e-04d67ec64982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41296387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.41296387
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1130306242
Short name T795
Test name
Test status
Simulation time 307402048 ps
CPU time 2.99 seconds
Started Mar 16 12:23:47 PM PDT 24
Finished Mar 16 12:23:51 PM PDT 24
Peak memory 218072 kb
Host smart-57a75695-0cbe-41ee-ae0f-e67411a65512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130306242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1130306242
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.657513919
Short name T654
Test name
Test status
Simulation time 196000727 ps
CPU time 4.32 seconds
Started Mar 16 12:23:55 PM PDT 24
Finished Mar 16 12:24:05 PM PDT 24
Peak memory 218420 kb
Host smart-bc4339c3-7158-4a71-841e-06d23b94a217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657513919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.657513919
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3156498084
Short name T84
Test name
Test status
Simulation time 7299172514 ps
CPU time 64.74 seconds
Started Mar 16 12:24:00 PM PDT 24
Finished Mar 16 12:25:05 PM PDT 24
Peak memory 222472 kb
Host smart-3760f500-bca9-4d58-bce6-9c70a4135246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156498084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3156498084
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1896121523
Short name T203
Test name
Test status
Simulation time 10805895819 ps
CPU time 48.78 seconds
Started Mar 16 12:23:47 PM PDT 24
Finished Mar 16 12:24:36 PM PDT 24
Peak memory 217560 kb
Host smart-81e9a077-6370-4859-b240-b251b7fb9d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896121523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1896121523
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2959019944
Short name T674
Test name
Test status
Simulation time 528925508 ps
CPU time 6.46 seconds
Started Mar 16 12:23:49 PM PDT 24
Finished Mar 16 12:23:55 PM PDT 24
Peak memory 218080 kb
Host smart-a5f61169-c5a6-4334-b1b8-253a800a9106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959019944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2959019944
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3517851030
Short name T992
Test name
Test status
Simulation time 430920926 ps
CPU time 10.6 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:23:49 PM PDT 24
Peak memory 208820 kb
Host smart-cecab6c4-db67-4e74-a745-1bafddf26622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517851030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3517851030
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.502929394
Short name T818
Test name
Test status
Simulation time 416151780 ps
CPU time 2.11 seconds
Started Mar 16 12:23:39 PM PDT 24
Finished Mar 16 12:23:41 PM PDT 24
Peak memory 208560 kb
Host smart-2ac775ac-716f-4c67-bf65-f786e2bcb278
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502929394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.502929394
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1336906705
Short name T592
Test name
Test status
Simulation time 193567354 ps
CPU time 3.79 seconds
Started Mar 16 12:23:37 PM PDT 24
Finished Mar 16 12:23:41 PM PDT 24
Peak memory 206772 kb
Host smart-7d88c0cb-4e20-4a78-8541-edae99527523
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336906705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1336906705
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.115081177
Short name T792
Test name
Test status
Simulation time 190288669 ps
CPU time 2.58 seconds
Started Mar 16 12:23:48 PM PDT 24
Finished Mar 16 12:23:51 PM PDT 24
Peak memory 206844 kb
Host smart-87d70699-8449-4540-8ed6-cc717b88b005
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115081177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.115081177
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3883434115
Short name T623
Test name
Test status
Simulation time 118932609 ps
CPU time 1.73 seconds
Started Mar 16 12:23:57 PM PDT 24
Finished Mar 16 12:24:00 PM PDT 24
Peak memory 207900 kb
Host smart-f84dddb2-1d2e-43c8-ba5b-4feabffd0011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883434115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3883434115
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.4036217660
Short name T185
Test name
Test status
Simulation time 511419224 ps
CPU time 6.45 seconds
Started Mar 16 12:23:40 PM PDT 24
Finished Mar 16 12:23:47 PM PDT 24
Peak memory 208432 kb
Host smart-a44a0f58-6b32-4614-96ef-765d47b92bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036217660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.4036217660
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.4248630796
Short name T223
Test name
Test status
Simulation time 1835855155 ps
CPU time 11.38 seconds
Started Mar 16 12:23:46 PM PDT 24
Finished Mar 16 12:23:58 PM PDT 24
Peak memory 214944 kb
Host smart-c6a494ff-eba3-4f0e-925a-785077b4af50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248630796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.4248630796
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.171901695
Short name T634
Test name
Test status
Simulation time 862526638 ps
CPU time 7.53 seconds
Started Mar 16 12:23:56 PM PDT 24
Finished Mar 16 12:24:05 PM PDT 24
Peak memory 219716 kb
Host smart-bbcda87c-da68-4f10-ba22-ce943376a0b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171901695 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.171901695
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3765714019
Short name T311
Test name
Test status
Simulation time 204995071 ps
CPU time 3.53 seconds
Started Mar 16 12:23:48 PM PDT 24
Finished Mar 16 12:23:52 PM PDT 24
Peak memory 209016 kb
Host smart-f79e961f-f13b-44cd-8042-c26979895358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765714019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3765714019
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.4289093805
Short name T161
Test name
Test status
Simulation time 78719693 ps
CPU time 3.49 seconds
Started Mar 16 12:23:50 PM PDT 24
Finished Mar 16 12:23:55 PM PDT 24
Peak memory 210104 kb
Host smart-9017441f-c323-4c66-a1a6-6e3330e662ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289093805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.4289093805
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1546860995
Short name T579
Test name
Test status
Simulation time 22051749 ps
CPU time 0.85 seconds
Started Mar 16 12:23:51 PM PDT 24
Finished Mar 16 12:23:53 PM PDT 24
Peak memory 205724 kb
Host smart-6074e861-2fbf-4e6e-9269-62dc5c5b52ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546860995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1546860995
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.47241120
Short name T423
Test name
Test status
Simulation time 358347920 ps
CPU time 17.29 seconds
Started Mar 16 12:23:53 PM PDT 24
Finished Mar 16 12:24:13 PM PDT 24
Peak memory 214140 kb
Host smart-f8cdb8b8-5dce-4add-8370-893ab93497cf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=47241120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.47241120
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3462175919
Short name T10
Test name
Test status
Simulation time 595323573 ps
CPU time 6.32 seconds
Started Mar 16 12:23:51 PM PDT 24
Finished Mar 16 12:23:57 PM PDT 24
Peak memory 209664 kb
Host smart-c40ea86e-997b-47ab-9db7-b2f6bf25b497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462175919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3462175919
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3187121939
Short name T294
Test name
Test status
Simulation time 439784500 ps
CPU time 3.55 seconds
Started Mar 16 12:23:49 PM PDT 24
Finished Mar 16 12:23:53 PM PDT 24
Peak memory 222372 kb
Host smart-1f736614-2ce2-4662-a2a5-e5229f6452e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187121939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3187121939
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1361166704
Short name T672
Test name
Test status
Simulation time 109117790 ps
CPU time 4.38 seconds
Started Mar 16 12:23:48 PM PDT 24
Finished Mar 16 12:23:52 PM PDT 24
Peak memory 208468 kb
Host smart-70451e96-f29c-461e-9e74-e12deef5da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361166704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1361166704
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1108109747
Short name T1069
Test name
Test status
Simulation time 29878947 ps
CPU time 1.88 seconds
Started Mar 16 12:26:20 PM PDT 24
Finished Mar 16 12:26:22 PM PDT 24
Peak memory 214124 kb
Host smart-fd14b8b9-69ba-4f0d-9a0f-877eca8642e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108109747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1108109747
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1819139422
Short name T259
Test name
Test status
Simulation time 145933116 ps
CPU time 2.84 seconds
Started Mar 16 12:23:50 PM PDT 24
Finished Mar 16 12:23:54 PM PDT 24
Peak memory 207512 kb
Host smart-51bca9d0-c68f-4989-b5f7-816746d9562c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819139422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1819139422
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3523937839
Short name T289
Test name
Test status
Simulation time 162831871 ps
CPU time 2.67 seconds
Started Mar 16 12:26:06 PM PDT 24
Finished Mar 16 12:26:08 PM PDT 24
Peak memory 206724 kb
Host smart-4569e959-c861-440c-911c-8b6c3821369e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523937839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3523937839
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.799425646
Short name T653
Test name
Test status
Simulation time 114200781 ps
CPU time 3.13 seconds
Started Mar 16 12:23:49 PM PDT 24
Finished Mar 16 12:23:52 PM PDT 24
Peak memory 208776 kb
Host smart-1979fbda-007c-4ff3-827c-a1b845161662
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799425646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.799425646
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2478705497
Short name T713
Test name
Test status
Simulation time 1305189338 ps
CPU time 8.33 seconds
Started Mar 16 12:23:49 PM PDT 24
Finished Mar 16 12:23:57 PM PDT 24
Peak memory 208364 kb
Host smart-219f0aa5-4804-4868-9707-87acbbdbde92
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478705497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2478705497
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3538112595
Short name T17
Test name
Test status
Simulation time 3243617073 ps
CPU time 22.67 seconds
Started Mar 16 12:23:56 PM PDT 24
Finished Mar 16 12:24:20 PM PDT 24
Peak memory 208120 kb
Host smart-23859239-3f19-4c0a-82b7-af4505a3f43c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538112595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3538112595
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3240755145
Short name T940
Test name
Test status
Simulation time 4595601823 ps
CPU time 27.16 seconds
Started Mar 16 12:23:56 PM PDT 24
Finished Mar 16 12:24:24 PM PDT 24
Peak memory 209600 kb
Host smart-2786521d-9af5-4e44-95b3-010ce359297a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240755145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3240755145
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1218317173
Short name T975
Test name
Test status
Simulation time 278393059 ps
CPU time 2.46 seconds
Started Mar 16 12:23:59 PM PDT 24
Finished Mar 16 12:24:02 PM PDT 24
Peak memory 207224 kb
Host smart-aff5752d-9ed2-4c2e-8703-3a63e7b3e10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218317173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1218317173
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3931165948
Short name T982
Test name
Test status
Simulation time 4131599011 ps
CPU time 114.15 seconds
Started Mar 16 12:23:43 PM PDT 24
Finished Mar 16 12:25:38 PM PDT 24
Peak memory 220736 kb
Host smart-0a43c22a-d66f-41f5-a7f8-7d30dd2c53a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931165948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3931165948
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.525919054
Short name T901
Test name
Test status
Simulation time 90473259 ps
CPU time 6.21 seconds
Started Mar 16 12:26:16 PM PDT 24
Finished Mar 16 12:26:22 PM PDT 24
Peak memory 221836 kb
Host smart-25da13c9-e833-4279-a012-e2fc905deff5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525919054 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.525919054
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.20784541
Short name T887
Test name
Test status
Simulation time 112403080 ps
CPU time 4.9 seconds
Started Mar 16 12:26:20 PM PDT 24
Finished Mar 16 12:26:25 PM PDT 24
Peak memory 208712 kb
Host smart-b5a77e37-ee51-4aec-8978-9332acdcbd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20784541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.20784541
Directory /workspace/9.keymgr_sw_invalid_input/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%