Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	87	1			T5	2		T42	1		T43	1
auto[OpGenId]	21	1			T30	1		T197	1		T61	1
auto[OpGenSwOut]	19	1			T25	1		T48	1		T198	1
auto[OpGenHwOut]	32	1			T5	1		T6	1		T7	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1755	1			T5	1		T42	1		T43	2
auto[StInit]	146	1			T5	3		T25	1		T26	1
auto[StCreatorRootKey]	60	1			T5	1		T6	1		T28	1
auto[StOwnerIntKey]	43	1			T33	1		T7	1		T36	1
auto[StOwnerKey]	29	1			T2	1		T8	1		T57	1
auto[StDisabled]	340	1			T5	11		T43	16		T100	1
auto[StInvalid]	48	1			T34	1		T35	1		T98	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3340

1

T1

1

T2

2

T3

1

auto[1]

159

1

T5

3

T25

1

T42

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1737	1			T5	1		T43	2		T81	3
auto[StReset]	auto[1]	18	1			T42	1		T37	1		T198	2
auto[StInit]	auto[0]	61	1			T5	1		T26	1		T81	2
auto[StInit]	auto[1]	85	1			T5	2		T25	1		T48	1
auto[StCreatorRootKey]	auto[0]	40	1			T28	1		T104	1		T60	1
auto[StCreatorRootKey]	auto[1]	20	1			T5	1		T6	1		T52	1
auto[StOwnerIntKey]	auto[0]	26	1			T33	1		T36	1		T55	1
auto[StOwnerIntKey]	auto[1]	17	1			T7	1		T43	1		T103	1
auto[StOwnerKey]	auto[0]	26	1			T2	1		T8	1		T57	1
auto[StOwnerKey]	auto[1]	3	1			T59	1		T199	1		T170	1
auto[StDisabled]	auto[0]	324	1			T5	11		T43	15		T100	1
auto[StDisabled]	auto[1]	16	1			T43	1		T29	1		T104	1
auto[StInvalid]	auto[0]	48	1			T34	1		T35	1		T98	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut]]	--	--	2
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	17	1			T42	1		T198	2		T46	1
auto[StReset]	auto[OpGenHwOut]	1	1			T37	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	42	1			T5	1		T101	1		T166	1
auto[StInit]	auto[OpGenId]	15	1			T30	1		T197	1		T61	1
auto[StInit]	auto[OpGenSwOut]	11	1			T25	1		T48	1		T198	1
auto[StInit]	auto[OpGenHwOut]	17	1			T5	1		T49	1		T200	1
auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T5	1		T52	1		T201	1
auto[StCreatorRootKey]	auto[OpGenId]	2	1			T202	1		T203	1		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T204	1		T205	1		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	5	1			T6	1		T206	1		T207	1
auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T43	1		T103	1		T57	1
auto[StOwnerIntKey]	auto[OpGenId]	2	1			T47	1		T208	1		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T209	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	5	1			T7	1		T57	1		T210	1
auto[StOwnerKey]	auto[OpAdvance]	1	1			T199	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenId]	1	1			T170	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T59	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	7	1			T29	1		T104	1		T47	1
auto[StDisabled]	auto[OpGenId]	1	1			T211	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	4	1			T197	1		T212	1		T213	1
auto[StDisabled]	auto[OpGenHwOut]	4	1			T43	1		T214	1		T215	1