Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11143

1

T1

12

T2

4

T3

8

auto[Attestation]

7612

1

T1

12

T2

4

T3

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2764	1			T1	5		T2	2		T3	1
auto[Aes]	3318	1			T1	3		T2	2		T3	1
auto[Kmac]	3369	1			T1	7		T3	2		T4	4
auto[Otbn]	3452	1			T1	2		T2	2		T3	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7463	1			T1	8		T2	4		T3	8
auto[OpGenId]	5852	1			T1	7		T2	2		T3	7
auto[OpGenSwOut]	5802	1			T1	6		T2	2		T3	5
auto[OpGenHwOut]	7101	1			T1	11		T2	4		T4	12
auto[OpDisable]	107	1			T14	1		T44	1		T45	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9630

1

T1

16

T2

11

T3

8

auto[OpDoneFail]

16695

1

T1

16

T2

1

T3

12

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6404	1			T1	1		T2	1		T3	5
auto[StInit]	4262	1			T1	6		T2	2		T3	2
auto[StCreatorRootKey]	2779	1			T1	3		T2	2		T3	2
auto[StOwnerIntKey]	2563	1			T1	5		T2	4		T3	2
auto[StOwnerKey]	2221	1			T1	6		T2	3		T3	2
auto[StDisabled]	7035	1			T1	11		T3	7		T4	7
auto[StInvalid]	1061	1			T34	26		T35	18		T98	23

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	314	1			T5	3		T181	1		T26	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	122	1			T8	1		T5	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	83	1			T2	1		T5	3		T181	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	57	1			T33	1		T5	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	47	1			T89	1		T131	1		T123	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	215	1			T1	2		T3	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	29	1			T34	2		T35	1		T98	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	307	1			T3	1		T82	2		T5	6
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	111	1			T2	1		T5	2		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	74	1			T8	1		T5	2		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	62	1			T1	1		T8	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	55	1			T5	1		T182	1		T126	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	149	1			T5	5		T183	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	41	1			T34	1		T35	2		T98	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	315	1			T82	1		T5	6		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	95	1			T16	2		T21	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	65	1			T44	1		T126	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	61	1			T43	1		T100	1		T55	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	52	1			T5	2		T43	1		T99	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	186	1			T1	1		T5	5		T181	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	27	1			T34	1		T94	1		T121	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	323	1			T82	2		T5	4		T181	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	128	1			T16	1		T21	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	63	1			T8	1		T5	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	61	1			T82	1		T5	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	44	1			T5	1		T104	1		T184	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	195	1			T3	1		T4	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	27	1			T121	2		T50	3		T185	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	64	1			T5	1		T94	2		T57	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	123	1			T5	1		T181	1		T91	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	80	1			T14	1		T181	1		T186	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T5	2		T102	1		T123	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	69	1			T5	4		T183	1		T187	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	200	1			T4	1		T16	1		T5	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	41	1			T50	1		T93	1		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	92	1			T5	1		T43	6		T103	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	107	1			T21	2		T5	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	88	1			T16	1		T5	2		T127	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	47	1			T43	1		T133	1		T188	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	64	1			T5	1		T189	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	172	1			T14	1		T16	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	33	1			T34	1		T98	1		T94	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	71	1			T5	3		T43	3		T103	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	127	1			T1	1		T21	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	71	1			T3	1		T186	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	61	1			T5	1		T128	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	53	1			T5	3		T183	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	218	1			T3	1		T5	6		T43	6
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	28	1			T34	1		T35	1		T98	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	64	1			T5	1		T43	1		T94	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	129	1			T1	1		T5	1		T22	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	77	1			T5	5		T7	2		T182	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	76	1			T181	1		T43	2		T187	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	53	1			T82	1		T5	1		T127	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	190	1			T16	1		T5	3		T181	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	33	1			T94	1		T121	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	259	1			T4	1		T23	3		T186	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	127	1			T4	1		T33	1		T21	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	55	1			T186	1		T74	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	56	1			T1	1		T16	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	41	1			T56	1		T75	1		T77	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	165	1			T5	3		T181	1		T126	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	34	1			T34	1		T98	1		T121	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	499	1			T17	1		T5	3		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	152	1			T15	1		T16	1		T21	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	104	1			T15	1		T17	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	106	1			T1	1		T2	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	84	1			T15	1		T17	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	235	1			T4	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	29	1			T34	4		T98	1		T93	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	507	1			T4	3		T18	3		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	132	1			T1	1		T18	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	118	1			T18	1		T5	4		T190	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	103	1			T18	1		T145	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	77	1			T5	5		T191	1		T189	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	242	1			T1	1		T18	1		T40	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	38	1			T34	1		T35	1		T121	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	516	1			T4	2		T82	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	146	1			T16	1		T82	1		T21	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	97	1			T8	3		T24	1		T125	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	96	1			T33	1		T5	4		T183	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	78	1			T56	1		T192	1		T193	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	260	1			T14	1		T16	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	36	1			T34	1		T121	1		T185	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	64	1			T43	3		T57	4		T104	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	113	1			T1	1		T21	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	41	1			T24	1		T5	1		T75	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	68	1			T2	1		T8	1		T103	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	48	1			T1	1		T4	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	156	1			T16	1		T5	5		T194	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	30	1			T34	1		T35	1		T94	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	45	1			T5	2		T57	2		T104	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	121	1			T17	1		T195	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	91	1			T4	1		T195	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	86	1			T14	1		T15	1		T195	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	75	1			T1	1		T195	1		T189	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	259	1			T4	1		T15	3		T17	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	30	1			T98	1		T121	2		T93	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	47	1			T94	1		T57	2		T46	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	115	1			T40	1		T21	1		T145	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	102	1			T1	1		T40	1		T145	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T4	1		T40	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	91	1			T1	2		T18	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	252	1			T18	3		T40	1		T24	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	23	1			T98	1		T94	1		T95	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	53	1			T43	1		T94	1		T57	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	122	1			T14	1		T23	1		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	99	1			T196	1		T192	1		T43	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T2	1		T189	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	86	1			T1	1		T2	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	272	1			T14	1		T5	4		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	37	1			T35	1		T98	1		T94	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	178	1			T2	1		T33	1		T5	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	689	1			T1	2		T3	1		T8	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	179	1			T1	1		T8	3		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	620	1			T2	1		T3	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	165	1			T5	2		T44	1		T43	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	636	1			T1	1		T16	2		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	158	1			T8	1		T82	1		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	683	1			T3	1		T4	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	193	1			T14	1		T5	6		T181	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	447	1			T4	1		T16	1		T5	6
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	181	1			T16	1		T5	3		T189	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	422	1			T14	1		T16	1		T21	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	167	1			T3	1		T5	4		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	462	1			T1	1		T3	1		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	195	1			T82	1		T5	6		T181	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	427	1			T1	1		T16	1		T5	5
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	144	1			T1	1		T16	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	593	1			T4	2		T33	1		T21	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	272	1			T1	1		T2	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	937	1			T4	1		T15	2		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	287	1			T18	2		T145	1		T5	9
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	930	1			T1	2		T4	3		T18	5
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	260	1			T8	3		T24	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	969	1			T4	2		T14	1		T16	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	147	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	373	1			T1	1		T16	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	235	1			T1	1		T4	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	472	1			T4	1		T15	3		T17	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	276	1			T1	3		T4	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	446	1			T18	3		T40	2		T24	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	259	1			T1	1		T2	2		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	501	1			T14	2		T24	1		T5	4