Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30209

1

T1

34

T2

14

T3

22

auto[1]

269

1

T77

10

T79

9

T221

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30217	1			T1	34		T2	14		T3	22
auto[134217728:268435455]	10	1			T77	2		T79	1		T225	1
auto[268435456:402653183]	9	1			T77	1		T251	1		T278	1
auto[402653184:536870911]	7	1			T77	1		T278	1		T405	1
auto[536870912:671088639]	8	1			T252	1		T238	1		T278	1
auto[671088640:805306367]	9	1			T77	1		T79	1		T221	1
auto[805306368:939524095]	5	1			T77	1		T284	2		T298	1
auto[939524096:1073741823]	8	1			T225	1		T252	1		T366	1
auto[1073741824:1207959551]	17	1			T79	1		T221	1		T225	2
auto[1207959552:1342177279]	13	1			T381	1		T288	1		T238	1
auto[1342177280:1476395007]	10	1			T77	1		T79	1		T406	1
auto[1476395008:1610612735]	8	1			T79	1		T225	1		T303	1
auto[1610612736:1744830463]	14	1			T77	1		T278	1		T405	4
auto[1744830464:1879048191]	6	1			T77	1		T327	1		T298	2
auto[1879048192:2013265919]	12	1			T224	1		T288	1		T399	1
auto[2013265920:2147483647]	5	1			T407	1		T408	1		T343	2
auto[2147483648:2281701375]	7	1			T224	1		T238	1		T399	1
auto[2281701376:2415919103]	7	1			T221	1		T225	1		T327	1
auto[2415919104:2550136831]	10	1			T327	1		T303	1		T284	1
auto[2550136832:2684354559]	6	1			T288	2		T340	1		T407	1
auto[2684354560:2818572287]	12	1			T79	1		T238	1		T409	1
auto[2818572288:2952790015]	8	1			T221	1		T278	1		T399	1
auto[2952790016:3087007743]	8	1			T278	1		T406	1		T366	1
auto[3087007744:3221225471]	9	1			T225	1		T410	1		T340	1
auto[3221225472:3355443199]	5	1			T79	1		T411	1		T407	1
auto[3355443200:3489660927]	7	1			T79	1		T327	1		T244	1
auto[3489660928:3623878655]	10	1			T221	2		T410	2		T407	1
auto[3623878656:3758096383]	3	1			T303	1		T340	1		T298	1
auto[3758096384:3892314111]	7	1			T224	1		T284	1		T412	1
auto[3892314112:4026531839]	11	1			T224	1		T399	3		T284	1
auto[4026531840:4160749567]	6	1			T288	1		T238	1		T406	1
auto[4160749568:4294967295]	4	1			T77	1		T331	1		T413	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30209	1			T1	34		T2	14		T3	22
auto[0:134217727]	auto[1]	8	1			T79	1		T221	1		T399	1
auto[134217728:268435455]	auto[1]	10	1			T77	2		T79	1		T225	1
auto[268435456:402653183]	auto[1]	9	1			T77	1		T251	1		T278	1
auto[402653184:536870911]	auto[1]	7	1			T77	1		T278	1		T405	1
auto[536870912:671088639]	auto[1]	8	1			T252	1		T238	1		T278	1
auto[671088640:805306367]	auto[1]	9	1			T77	1		T79	1		T221	1
auto[805306368:939524095]	auto[1]	5	1			T77	1		T284	2		T298	1
auto[939524096:1073741823]	auto[1]	8	1			T225	1		T252	1		T366	1
auto[1073741824:1207959551]	auto[1]	17	1			T79	1		T221	1		T225	2
auto[1207959552:1342177279]	auto[1]	13	1			T381	1		T288	1		T238	1
auto[1342177280:1476395007]	auto[1]	10	1			T77	1		T79	1		T406	1
auto[1476395008:1610612735]	auto[1]	8	1			T79	1		T225	1		T303	1
auto[1610612736:1744830463]	auto[1]	14	1			T77	1		T278	1		T405	4
auto[1744830464:1879048191]	auto[1]	6	1			T77	1		T327	1		T298	2
auto[1879048192:2013265919]	auto[1]	12	1			T224	1		T288	1		T399	1
auto[2013265920:2147483647]	auto[1]	5	1			T407	1		T408	1		T343	2
auto[2147483648:2281701375]	auto[1]	7	1			T224	1		T238	1		T399	1
auto[2281701376:2415919103]	auto[1]	7	1			T221	1		T225	1		T327	1
auto[2415919104:2550136831]	auto[1]	10	1			T327	1		T303	1		T284	1
auto[2550136832:2684354559]	auto[1]	6	1			T288	2		T340	1		T407	1
auto[2684354560:2818572287]	auto[1]	12	1			T79	1		T238	1		T409	1
auto[2818572288:2952790015]	auto[1]	8	1			T221	1		T278	1		T399	1
auto[2952790016:3087007743]	auto[1]	8	1			T278	1		T406	1		T366	1
auto[3087007744:3221225471]	auto[1]	9	1			T225	1		T410	1		T340	1
auto[3221225472:3355443199]	auto[1]	5	1			T79	1		T411	1		T407	1
auto[3355443200:3489660927]	auto[1]	7	1			T79	1		T327	1		T244	1
auto[3489660928:3623878655]	auto[1]	10	1			T221	2		T410	2		T407	1
auto[3623878656:3758096383]	auto[1]	3	1			T303	1		T340	1		T298	1
auto[3758096384:3892314111]	auto[1]	7	1			T224	1		T284	1		T412	1
auto[3892314112:4026531839]	auto[1]	11	1			T224	1		T399	3		T284	1
auto[4026531840:4160749567]	auto[1]	6	1			T288	1		T238	1		T406	1
auto[4160749568:4294967295]	auto[1]	4	1			T77	1		T331	1		T413	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1468

1

T1

2

T14

1

T16

2

auto[1]

1611

1

T1

3

T14

1

T8

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	119	1			T16	2		T33	1		T5	4
auto[134217728:268435455]	109	1			T5	3		T7	1		T26	1
auto[268435456:402653183]	81	1			T42	2		T186	1		T183	1
auto[402653184:536870911]	103	1			T16	1		T24	2		T5	2
auto[536870912:671088639]	88	1			T194	1		T74	1		T100	1
auto[671088640:805306367]	102	1			T5	2		T42	1		T43	1
auto[805306368:939524095]	110	1			T24	1		T5	3		T6	1
auto[939524096:1073741823]	94	1			T14	1		T5	1		T25	1
auto[1073741824:1207959551]	97	1			T1	2		T6	1		T26	1
auto[1207959552:1342177279]	80	1			T1	1		T23	1		T43	1
auto[1342177280:1476395007]	111	1			T5	3		T43	2		T81	1
auto[1476395008:1610612735]	89	1			T5	1		T181	1		T43	2
auto[1610612736:1744830463]	89	1			T16	1		T5	3		T56	1
auto[1744830464:1879048191]	116	1			T33	1		T5	3		T25	1
auto[1879048192:2013265919]	87	1			T1	1		T21	1		T5	2
auto[2013265920:2147483647]	78	1			T21	1		T5	2		T45	1
auto[2147483648:2281701375]	101	1			T5	3		T22	2		T91	1
auto[2281701376:2415919103]	108	1			T5	2		T126	1		T43	1
auto[2415919104:2550136831]	109	1			T21	1		T5	3		T22	1
auto[2550136832:2684354559]	83	1			T183	1		T43	2		T98	1
auto[2684354560:2818572287]	98	1			T5	1		T22	1		T42	1
auto[2818572288:2952790015]	85	1			T5	1		T100	1		T57	1
auto[2952790016:3087007743]	107	1			T14	1		T5	4		T43	1
auto[3087007744:3221225471]	100	1			T5	1		T23	1		T186	1
auto[3221225472:3355443199]	92	1			T5	2		T44	1		T189	1
auto[3355443200:3489660927]	97	1			T24	1		T5	2		T181	1
auto[3489660928:3623878655]	86	1			T126	1		T43	1		T74	1
auto[3623878656:3758096383]	94	1			T8	1		T24	1		T5	1
auto[3758096384:3892314111]	92	1			T16	1		T24	1		T21	1
auto[3892314112:4026531839]	91	1			T5	1		T181	1		T43	1
auto[4026531840:4160749567]	79	1			T1	1		T24	1		T33	1
auto[4160749568:4294967295]	104	1			T8	1		T5	1		T181	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	57	1			T16	1		T5	2		T25	1
auto[0:134217727]	auto[1]	62	1			T16	1		T33	1		T5	2
auto[134217728:268435455]	auto[0]	42	1			T5	1		T91	1		T75	1
auto[134217728:268435455]	auto[1]	67	1			T5	2		T7	1		T26	1
auto[268435456:402653183]	auto[0]	39	1			T42	2		T34	1		T55	1
auto[268435456:402653183]	auto[1]	42	1			T186	1		T183	1		T43	1
auto[402653184:536870911]	auto[0]	48	1			T24	1		T5	2		T183	1
auto[402653184:536870911]	auto[1]	55	1			T16	1		T24	1		T56	1
auto[536870912:671088639]	auto[0]	46	1			T100	1		T101	2		T121	1
auto[536870912:671088639]	auto[1]	42	1			T194	1		T74	1		T300	1
auto[671088640:805306367]	auto[0]	52	1			T5	1		T42	1		T43	1
auto[671088640:805306367]	auto[1]	50	1			T5	1		T78	1		T101	1
auto[805306368:939524095]	auto[0]	53	1			T24	1		T5	1		T126	1
auto[805306368:939524095]	auto[1]	57	1			T5	2		T6	1		T94	1
auto[939524096:1073741823]	auto[0]	40	1			T5	1		T25	1		T181	1
auto[939524096:1073741823]	auto[1]	54	1			T14	1		T102	1		T57	1
auto[1073741824:1207959551]	auto[0]	48	1			T1	1		T26	1		T34	1
auto[1073741824:1207959551]	auto[1]	49	1			T1	1		T6	1		T79	1
auto[1207959552:1342177279]	auto[0]	34	1			T23	1		T43	1		T102	1
auto[1207959552:1342177279]	auto[1]	46	1			T1	1		T99	1		T102	1
auto[1342177280:1476395007]	auto[0]	49	1			T5	3		T123	1		T188	1
auto[1342177280:1476395007]	auto[1]	62	1			T43	2		T81	1		T48	1
auto[1476395008:1610612735]	auto[0]	53	1			T181	1		T43	1		T94	1
auto[1476395008:1610612735]	auto[1]	36	1			T5	1		T43	1		T52	1
auto[1610612736:1744830463]	auto[0]	31	1			T5	1		T56	1		T43	1
auto[1610612736:1744830463]	auto[1]	58	1			T16	1		T5	2		T29	1
auto[1744830464:1879048191]	auto[0]	54	1			T5	1		T42	1		T186	1
auto[1744830464:1879048191]	auto[1]	62	1			T33	1		T5	2		T25	1
auto[1879048192:2013265919]	auto[0]	47	1			T1	1		T21	1		T5	2
auto[1879048192:2013265919]	auto[1]	40	1			T181	1		T183	1		T56	1
auto[2013265920:2147483647]	auto[0]	39	1			T21	1		T5	2		T56	1
auto[2013265920:2147483647]	auto[1]	39	1			T45	1		T28	1		T89	1
auto[2147483648:2281701375]	auto[0]	46	1			T5	2		T98	1		T123	1
auto[2147483648:2281701375]	auto[1]	55	1			T5	1		T22	2		T91	1
auto[2281701376:2415919103]	auto[0]	52	1			T126	1		T102	1		T83	1
auto[2281701376:2415919103]	auto[1]	56	1			T5	2		T43	1		T99	1
auto[2415919104:2550136831]	auto[0]	58	1			T21	1		T5	2		T22	1
auto[2415919104:2550136831]	auto[1]	51	1			T5	1		T7	1		T194	1
auto[2550136832:2684354559]	auto[0]	45	1			T98	1		T121	1		T57	2
auto[2550136832:2684354559]	auto[1]	38	1			T183	1		T43	2		T188	1
auto[2684354560:2818572287]	auto[0]	48	1			T5	1		T22	1		T23	1
auto[2684354560:2818572287]	auto[1]	50	1			T42	1		T7	1		T26	1
auto[2818572288:2952790015]	auto[0]	37	1			T5	1		T100	1		T57	1
auto[2818572288:2952790015]	auto[1]	48	1			T83	1		T270	1		T289	1
auto[2952790016:3087007743]	auto[0]	53	1			T14	1		T5	1		T43	1
auto[2952790016:3087007743]	auto[1]	54	1			T5	3		T75	1		T77	1
auto[3087007744:3221225471]	auto[0]	50	1			T23	1		T74	1		T98	1
auto[3087007744:3221225471]	auto[1]	50	1			T5	1		T186	1		T194	1
auto[3221225472:3355443199]	auto[0]	39	1			T5	1		T98	1		T49	1
auto[3221225472:3355443199]	auto[1]	53	1			T5	1		T44	1		T189	1
auto[3355443200:3489660927]	auto[0]	47	1			T5	1		T91	1		T43	1
auto[3355443200:3489660927]	auto[1]	50	1			T24	1		T5	1		T181	1
auto[3489660928:3623878655]	auto[0]	42	1			T49	1		T57	1		T104	1
auto[3489660928:3623878655]	auto[1]	44	1			T126	1		T43	1		T74	1
auto[3623878656:3758096383]	auto[0]	42	1			T22	1		T26	1		T43	1
auto[3623878656:3758096383]	auto[1]	52	1			T8	1		T24	1		T5	1
auto[3758096384:3892314111]	auto[0]	37	1			T16	1		T24	1		T91	1
auto[3758096384:3892314111]	auto[1]	55	1			T21	1		T5	1		T354	1
auto[3892314112:4026531839]	auto[0]	47	1			T5	1		T181	1		T100	1
auto[3892314112:4026531839]	auto[1]	44	1			T43	1		T48	1		T29	1
auto[4026531840:4160749567]	auto[0]	38	1			T186	1		T104	1		T83	1
auto[4026531840:4160749567]	auto[1]	41	1			T1	1		T24	1		T33	1
auto[4160749568:4294967295]	auto[0]	55	1			T5	1		T181	1		T43	1
auto[4160749568:4294967295]	auto[1]	49	1			T8	1		T126	1		T43	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1459

1

T1

2

T14

1

T16

1

auto[1]

1626

1

T1

3

T14

1

T8

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T5	1		T181	2		T42	1
auto[134217728:268435455]	89	1			T24	2		T21	1		T5	1
auto[268435456:402653183]	77	1			T1	1		T24	1		T5	1
auto[402653184:536870911]	108	1			T1	1		T16	1		T21	1
auto[536870912:671088639]	98	1			T1	1		T14	1		T5	2
auto[671088640:805306367]	91	1			T1	1		T23	1		T103	1
auto[805306368:939524095]	99	1			T8	1		T5	1		T22	1
auto[939524096:1073741823]	92	1			T5	3		T56	1		T7	1
auto[1073741824:1207959551]	105	1			T8	1		T5	1		T44	1
auto[1207959552:1342177279]	110	1			T5	3		T186	1		T26	1
auto[1342177280:1476395007]	84	1			T5	5		T23	1		T183	1
auto[1476395008:1610612735]	96	1			T181	1		T43	1		T48	1
auto[1610612736:1744830463]	103	1			T16	1		T24	1		T5	3
auto[1744830464:1879048191]	91	1			T16	1		T5	1		T22	1
auto[1879048192:2013265919]	84	1			T24	1		T33	1		T5	3
auto[2013265920:2147483647]	109	1			T14	1		T24	2		T5	1
auto[2147483648:2281701375]	115	1			T16	1		T42	1		T74	1
auto[2281701376:2415919103]	98	1			T21	1		T5	1		T186	1
auto[2415919104:2550136831]	105	1			T45	1		T6	1		T28	1
auto[2550136832:2684354559]	97	1			T16	1		T21	1		T5	2
auto[2684354560:2818572287]	74	1			T42	1		T43	2		T77	1
auto[2818572288:2952790015]	85	1			T5	1		T181	1		T23	1
auto[2952790016:3087007743]	93	1			T33	1		T5	2		T181	1
auto[3087007744:3221225471]	107	1			T5	1		T183	1		T125	1
auto[3221225472:3355443199]	93	1			T5	3		T194	1		T28	1
auto[3355443200:3489660927]	96	1			T5	1		T43	2		T74	1
auto[3489660928:3623878655]	100	1			T5	2		T25	1		T74	1
auto[3623878656:3758096383]	93	1			T33	1		T42	1		T43	2
auto[3758096384:3892314111]	106	1			T5	6		T25	2		T91	2
auto[3892314112:4026531839]	104	1			T1	1		T5	2		T189	1
auto[4026531840:4160749567]	96	1			T5	1		T181	1		T183	1
auto[4160749568:4294967295]	81	1			T5	2		T189	1		T42	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T181	1		T42	1		T23	1
auto[0:134217727]	auto[1]	60	1			T5	1		T181	1		T183	1
auto[134217728:268435455]	auto[0]	44	1			T24	1		T21	1		T22	1
auto[134217728:268435455]	auto[1]	45	1			T24	1		T5	1		T186	1
auto[268435456:402653183]	auto[0]	34	1			T1	1		T121	1		T224	1
auto[268435456:402653183]	auto[1]	43	1			T24	1		T5	1		T22	1
auto[402653184:536870911]	auto[0]	48	1			T16	1		T22	1		T94	1
auto[402653184:536870911]	auto[1]	60	1			T1	1		T21	1		T5	2
auto[536870912:671088639]	auto[0]	42	1			T1	1		T5	1		T43	2
auto[536870912:671088639]	auto[1]	56	1			T14	1		T5	1		T45	1
auto[671088640:805306367]	auto[0]	50	1			T23	1		T300	1		T233	1
auto[671088640:805306367]	auto[1]	41	1			T1	1		T103	1		T37	1
auto[805306368:939524095]	auto[0]	51	1			T22	1		T193	1		T65	1
auto[805306368:939524095]	auto[1]	48	1			T8	1		T5	1		T43	1
auto[939524096:1073741823]	auto[0]	44	1			T5	2		T55	1		T60	1
auto[939524096:1073741823]	auto[1]	48	1			T5	1		T56	1		T7	1
auto[1073741824:1207959551]	auto[0]	51	1			T44	1		T56	1		T55	1
auto[1073741824:1207959551]	auto[1]	54	1			T8	1		T5	1		T126	1
auto[1207959552:1342177279]	auto[0]	57	1			T5	2		T26	1		T126	1
auto[1207959552:1342177279]	auto[1]	53	1			T5	1		T186	1		T43	1
auto[1342177280:1476395007]	auto[0]	37	1			T5	3		T23	1		T83	2
auto[1342177280:1476395007]	auto[1]	47	1			T5	2		T183	1		T43	1
auto[1476395008:1610612735]	auto[0]	32	1			T49	1		T121	1		T46	1
auto[1476395008:1610612735]	auto[1]	64	1			T181	1		T43	1		T48	1
auto[1610612736:1744830463]	auto[0]	45	1			T186	1		T26	1		T133	1
auto[1610612736:1744830463]	auto[1]	58	1			T16	1		T24	1		T5	3
auto[1744830464:1879048191]	auto[0]	46	1			T5	1		T22	1		T23	1
auto[1744830464:1879048191]	auto[1]	45	1			T16	1		T194	1		T75	1
auto[1879048192:2013265919]	auto[0]	43	1			T24	1		T5	2		T43	1
auto[1879048192:2013265919]	auto[1]	41	1			T33	1		T5	1		T181	1
auto[2013265920:2147483647]	auto[0]	54	1			T14	1		T24	1		T5	1
auto[2013265920:2147483647]	auto[1]	55	1			T24	1		T43	1		T79	1
auto[2147483648:2281701375]	auto[0]	56	1			T42	1		T35	1		T98	1
auto[2147483648:2281701375]	auto[1]	59	1			T16	1		T74	1		T79	1
auto[2281701376:2415919103]	auto[0]	46	1			T21	1		T5	1		T186	1
auto[2281701376:2415919103]	auto[1]	52	1			T102	1		T57	1		T381	1
auto[2415919104:2550136831]	auto[0]	42	1			T60	1		T46	1		T222	1
auto[2415919104:2550136831]	auto[1]	63	1			T45	1		T6	1		T28	1
auto[2550136832:2684354559]	auto[0]	39	1			T21	1		T5	1		T100	1
auto[2550136832:2684354559]	auto[1]	58	1			T16	1		T5	1		T7	1
auto[2684354560:2818572287]	auto[0]	30	1			T77	1		T123	1		T27	1
auto[2684354560:2818572287]	auto[1]	44	1			T42	1		T43	2		T89	1
auto[2818572288:2952790015]	auto[0]	45	1			T5	1		T181	1		T23	1
auto[2818572288:2952790015]	auto[1]	40	1			T89	1		T64	1		T220	1
auto[2952790016:3087007743]	auto[0]	39	1			T5	1		T181	1		T219	1
auto[2952790016:3087007743]	auto[1]	54	1			T33	1		T5	1		T194	1
auto[3087007744:3221225471]	auto[0]	51	1			T126	1		T34	1		T77	1
auto[3087007744:3221225471]	auto[1]	56	1			T5	1		T183	1		T125	1
auto[3221225472:3355443199]	auto[0]	52	1			T5	2		T94	1		T60	1
auto[3221225472:3355443199]	auto[1]	41	1			T5	1		T194	1		T28	1
auto[3355443200:3489660927]	auto[0]	47	1			T5	1		T43	1		T101	2
auto[3355443200:3489660927]	auto[1]	49	1			T43	1		T74	1		T79	1
auto[3489660928:3623878655]	auto[0]	52	1			T5	2		T25	1		T74	1
auto[3489660928:3623878655]	auto[1]	48	1			T193	1		T57	1		T313	1
auto[3623878656:3758096383]	auto[0]	40	1			T42	1		T98	1		T354	1
auto[3623878656:3758096383]	auto[1]	53	1			T33	1		T43	2		T102	1
auto[3758096384:3892314111]	auto[0]	61	1			T5	5		T25	1		T91	1
auto[3758096384:3892314111]	auto[1]	45	1			T5	1		T25	1		T91	1
auto[3892314112:4026531839]	auto[0]	55	1			T5	1		T189	1		T7	1
auto[3892314112:4026531839]	auto[1]	49	1			T1	1		T5	1		T6	1
auto[4026531840:4160749567]	auto[0]	42	1			T181	1		T43	1		T34	1
auto[4026531840:4160749567]	auto[1]	54	1			T5	1		T183	1		T78	1
auto[4160749568:4294967295]	auto[0]	38	1			T5	1		T42	1		T77	1
auto[4160749568:4294967295]	auto[1]	43	1			T5	1		T189	1		T7	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1452

1

T1

2

T14

1

T16

1

auto[1]

1631

1

T1

3

T14

1

T8

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T24	2		T26	1		T43	1
auto[134217728:268435455]	94	1			T1	1		T5	3		T23	1
auto[268435456:402653183]	79	1			T7	1		T194	1		T126	1
auto[402653184:536870911]	89	1			T5	2		T25	1		T22	1
auto[536870912:671088639]	90	1			T14	1		T91	1		T43	1
auto[671088640:805306367]	108	1			T21	1		T5	1		T183	1
auto[805306368:939524095]	96	1			T16	3		T5	3		T181	1
auto[939524096:1073741823]	97	1			T24	1		T33	1		T21	1
auto[1073741824:1207959551]	106	1			T8	1		T5	2		T181	1
auto[1207959552:1342177279]	91	1			T33	1		T5	3		T56	2
auto[1342177280:1476395007]	91	1			T24	1		T5	1		T7	1
auto[1476395008:1610612735]	98	1			T24	1		T5	1		T28	1
auto[1610612736:1744830463]	112	1			T24	1		T5	1		T22	1
auto[1744830464:1879048191]	76	1			T5	2		T126	1		T43	1
auto[1879048192:2013265919]	105	1			T1	1		T5	2		T23	1
auto[2013265920:2147483647]	84	1			T8	1		T16	1		T5	3
auto[2147483648:2281701375]	96	1			T5	2		T22	2		T43	1
auto[2281701376:2415919103]	114	1			T1	1		T5	2		T42	1
auto[2415919104:2550136831]	109	1			T21	2		T183	1		T126	1
auto[2550136832:2684354559]	101	1			T5	2		T194	1		T43	1
auto[2684354560:2818572287]	87	1			T24	1		T5	2		T102	1
auto[2818572288:2952790015]	87	1			T1	1		T16	1		T26	2
auto[2952790016:3087007743]	87	1			T5	1		T45	1		T28	1
auto[3087007744:3221225471]	92	1			T14	1		T5	3		T56	1
auto[3221225472:3355443199]	100	1			T5	3		T25	1		T189	1
auto[3355443200:3489660927]	123	1			T1	1		T5	4		T23	1
auto[3489660928:3623878655]	100	1			T5	1		T22	1		T181	3
auto[3623878656:3758096383]	94	1			T181	1		T48	1		T101	1
auto[3758096384:3892314111]	108	1			T42	1		T186	1		T194	1
auto[3892314112:4026531839]	84	1			T33	1		T5	2		T25	1
auto[4026531840:4160749567]	93	1			T5	4		T181	1		T44	1
auto[4160749568:4294967295]	94	1			T33	1		T23	1		T183	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T24	2		T26	1		T34	1
auto[0:134217727]	auto[1]	53	1			T43	1		T94	1		T193	1
auto[134217728:268435455]	auto[0]	44	1			T1	1		T5	2		T23	1
auto[134217728:268435455]	auto[1]	50	1			T5	1		T183	1		T28	1
auto[268435456:402653183]	auto[0]	38	1			T194	1		T126	1		T49	1
auto[268435456:402653183]	auto[1]	41	1			T7	1		T35	1		T49	1
auto[402653184:536870911]	auto[0]	49	1			T5	1		T22	1		T43	2
auto[402653184:536870911]	auto[1]	40	1			T5	1		T25	1		T74	1
auto[536870912:671088639]	auto[0]	46	1			T14	1		T91	1		T43	1
auto[536870912:671088639]	auto[1]	44	1			T50	1		T193	1		T188	1
auto[671088640:805306367]	auto[0]	43	1			T21	1		T5	1		T48	1
auto[671088640:805306367]	auto[1]	65	1			T183	1		T43	1		T75	1
auto[805306368:939524095]	auto[0]	45	1			T16	1		T5	3		T181	1
auto[805306368:939524095]	auto[1]	51	1			T16	2		T45	1		T183	1
auto[939524096:1073741823]	auto[0]	44	1			T21	1		T5	1		T91	1
auto[939524096:1073741823]	auto[1]	53	1			T24	1		T33	1		T5	1
auto[1073741824:1207959551]	auto[0]	49	1			T181	1		T43	1		T55	1
auto[1073741824:1207959551]	auto[1]	57	1			T8	1		T5	2		T74	1
auto[1207959552:1342177279]	auto[0]	41	1			T56	1		T75	1		T57	1
auto[1207959552:1342177279]	auto[1]	50	1			T33	1		T5	3		T56	1
auto[1342177280:1476395007]	auto[0]	36	1			T5	1		T43	2		T49	1
auto[1342177280:1476395007]	auto[1]	55	1			T24	1		T7	1		T43	1
auto[1476395008:1610612735]	auto[0]	49	1			T5	1		T34	1		T78	1
auto[1476395008:1610612735]	auto[1]	49	1			T24	1		T28	1		T348	1
auto[1610612736:1744830463]	auto[0]	50	1			T22	1		T123	1		T27	1
auto[1610612736:1744830463]	auto[1]	62	1			T24	1		T5	1		T43	2
auto[1744830464:1879048191]	auto[0]	46	1			T5	1		T101	1		T246	1
auto[1744830464:1879048191]	auto[1]	30	1			T5	1		T126	1		T43	1
auto[1879048192:2013265919]	auto[0]	45	1			T5	1		T23	1		T126	1
auto[1879048192:2013265919]	auto[1]	60	1			T1	1		T5	1		T7	1
auto[2013265920:2147483647]	auto[0]	40	1			T5	2		T186	1		T91	1
auto[2013265920:2147483647]	auto[1]	44	1			T8	1		T16	1		T5	1
auto[2147483648:2281701375]	auto[0]	45	1			T5	2		T98	1		T55	1
auto[2147483648:2281701375]	auto[1]	51	1			T22	2		T43	1		T50	1
auto[2281701376:2415919103]	auto[0]	45	1			T5	1		T42	1		T23	1
auto[2281701376:2415919103]	auto[1]	69	1			T1	1		T5	1		T6	1
auto[2415919104:2550136831]	auto[0]	52	1			T21	1		T126	1		T34	1
auto[2415919104:2550136831]	auto[1]	57	1			T21	1		T183	1		T79	1
auto[2550136832:2684354559]	auto[0]	55	1			T5	1		T194	1		T34	1
auto[2550136832:2684354559]	auto[1]	46	1			T5	1		T43	1		T123	1
auto[2684354560:2818572287]	auto[0]	39	1			T24	1		T5	1		T300	1
auto[2684354560:2818572287]	auto[1]	48	1			T5	1		T102	1		T313	1
auto[2818572288:2952790015]	auto[0]	50	1			T26	1		T100	1		T83	1
auto[2818572288:2952790015]	auto[1]	37	1			T1	1		T16	1		T26	1
auto[2952790016:3087007743]	auto[0]	42	1			T5	1		T74	1		T100	1
auto[2952790016:3087007743]	auto[1]	45	1			T45	1		T28	1		T43	1
auto[3087007744:3221225471]	auto[0]	52	1			T5	3		T125	1		T94	1
auto[3087007744:3221225471]	auto[1]	40	1			T14	1		T56	1		T194	1
auto[3221225472:3355443199]	auto[0]	46	1			T5	1		T26	1		T77	1
auto[3221225472:3355443199]	auto[1]	54	1			T5	2		T25	1		T189	1
auto[3355443200:3489660927]	auto[0]	62	1			T1	1		T5	3		T23	1
auto[3355443200:3489660927]	auto[1]	61	1			T5	1		T74	1		T77	1
auto[3489660928:3623878655]	auto[0]	47	1			T22	1		T181	2		T94	1
auto[3489660928:3623878655]	auto[1]	53	1			T5	1		T181	1		T56	1
auto[3623878656:3758096383]	auto[0]	40	1			T101	1		T102	1		T121	1
auto[3623878656:3758096383]	auto[1]	54	1			T181	1		T48	1		T65	1
auto[3758096384:3892314111]	auto[0]	43	1			T42	1		T50	1		T57	1
auto[3758096384:3892314111]	auto[1]	65	1			T186	1		T194	1		T43	1
auto[3892314112:4026531839]	auto[0]	41	1			T25	1		T91	1		T43	2
auto[3892314112:4026531839]	auto[1]	43	1			T33	1		T5	2		T43	2
auto[4026531840:4160749567]	auto[0]	41	1			T5	2		T181	1		T42	1
auto[4026531840:4160749567]	auto[1]	52	1			T5	2		T44	1		T189	1
auto[4160749568:4294967295]	auto[0]	42	1			T121	1		T123	1		T46	1
auto[4160749568:4294967295]	auto[1]	52	1			T33	1		T23	1		T183	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1432

1

T1

2

T14

1

T16

1

auto[1]

1643

1

T1

3

T14

1

T8

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T24	1		T33	1		T5	3
auto[134217728:268435455]	99	1			T16	2		T5	2		T189	1
auto[268435456:402653183]	98	1			T5	1		T7	1		T26	1
auto[402653184:536870911]	93	1			T16	1		T22	1		T7	1
auto[536870912:671088639]	103	1			T14	1		T24	1		T181	2
auto[671088640:805306367]	108	1			T5	2		T75	2		T77	2
auto[805306368:939524095]	99	1			T33	1		T5	1		T186	2
auto[939524096:1073741823]	83	1			T181	1		T43	1		T78	1
auto[1073741824:1207959551]	98	1			T16	1		T5	2		T181	2
auto[1207959552:1342177279]	78	1			T8	1		T5	3		T22	1
auto[1342177280:1476395007]	77	1			T49	1		T121	1		T89	1
auto[1476395008:1610612735]	92	1			T33	1		T5	2		T23	1
auto[1610612736:1744830463]	88	1			T5	1		T181	1		T43	1
auto[1744830464:1879048191]	86	1			T21	1		T44	1		T183	1
auto[1879048192:2013265919]	85	1			T5	1		T25	1		T23	1
auto[2013265920:2147483647]	105	1			T8	1		T5	2		T25	2
auto[2147483648:2281701375]	91	1			T5	4		T42	2		T26	1
auto[2281701376:2415919103]	102	1			T5	1		T23	1		T43	2
auto[2415919104:2550136831]	96	1			T5	5		T22	1		T183	1
auto[2550136832:2684354559]	101	1			T1	1		T14	1		T24	1
auto[2684354560:2818572287]	93	1			T5	2		T23	2		T194	1
auto[2818572288:2952790015]	87	1			T1	1		T16	1		T5	3
auto[2952790016:3087007743]	115	1			T1	1		T24	1		T21	1
auto[3087007744:3221225471]	95	1			T5	1		T126	1		T43	1
auto[3221225472:3355443199]	113	1			T5	4		T22	1		T101	1
auto[3355443200:3489660927]	94	1			T24	1		T21	1		T22	1
auto[3489660928:3623878655]	95	1			T5	1		T43	2		T75	1
auto[3623878656:3758096383]	87	1			T5	2		T181	1		T42	1
auto[3758096384:3892314111]	96	1			T7	1		T98	1		T100	1
auto[3892314112:4026531839]	105	1			T24	1		T5	1		T45	1
auto[4026531840:4160749567]	104	1			T1	1		T24	1		T5	1
auto[4160749568:4294967295]	105	1			T1	1		T21	1		T5	4