Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2711

1

T1

5

T14

2

T8

1

auto[1]

255

1

T75

2

T77

6

T79

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T5	3		T43	1		T79	1
auto[134217728:268435455]	96	1			T5	1		T7	1		T43	1
auto[268435456:402653183]	89	1			T14	1		T5	2		T23	1
auto[402653184:536870911]	89	1			T16	1		T5	2		T7	1
auto[536870912:671088639]	96	1			T1	1		T16	1		T5	1
auto[671088640:805306367]	92	1			T5	1		T125	1		T43	1
auto[805306368:939524095]	98	1			T16	1		T33	1		T5	2
auto[939524096:1073741823]	91	1			T33	1		T126	1		T29	1
auto[1073741824:1207959551]	101	1			T16	1		T24	2		T183	1
auto[1207959552:1342177279]	96	1			T43	1		T79	1		T94	1
auto[1342177280:1476395007]	90	1			T21	1		T181	1		T91	2
auto[1476395008:1610612735]	100	1			T22	1		T181	1		T186	1
auto[1610612736:1744830463]	101	1			T1	1		T21	1		T181	1
auto[1744830464:1879048191]	100	1			T24	1		T5	2		T25	1
auto[1879048192:2013265919]	94	1			T5	2		T181	2		T183	1
auto[2013265920:2147483647]	107	1			T24	1		T21	1		T25	1
auto[2147483648:2281701375]	71	1			T24	1		T5	3		T34	1
auto[2281701376:2415919103]	82	1			T5	3		T77	1		T104	1
auto[2415919104:2550136831]	90	1			T5	3		T42	1		T103	1
auto[2550136832:2684354559]	88	1			T194	1		T98	1		T100	1
auto[2684354560:2818572287]	88	1			T5	2		T28	1		T94	1
auto[2818572288:2952790015]	84	1			T5	2		T181	1		T6	1
auto[2952790016:3087007743]	86	1			T5	1		T23	2		T26	1
auto[3087007744:3221225471]	87	1			T16	1		T24	1		T25	1
auto[3221225472:3355443199]	79	1			T44	1		T43	1		T74	1
auto[3355443200:3489660927]	107	1			T183	1		T91	1		T75	1
auto[3489660928:3623878655]	74	1			T22	2		T181	1		T45	1
auto[3623878656:3758096383]	99	1			T1	1		T14	1		T5	1
auto[3758096384:3892314111]	119	1			T24	1		T45	1		T183	1
auto[3892314112:4026531839]	90	1			T1	1		T21	1		T22	1
auto[4026531840:4160749567]	100	1			T5	1		T126	1		T43	1
auto[4160749568:4294967295]	87	1			T1	1		T8	1		T5	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	88	1			T5	3		T43	1		T79	1
auto[0:134217727]	auto[1]	7	1			T224	1		T399	1		T405	1
auto[134217728:268435455]	auto[0]	89	1			T5	1		T7	1		T43	1
auto[134217728:268435455]	auto[1]	7	1			T225	2		T340	1		T406	1
auto[268435456:402653183]	auto[0]	80	1			T14	1		T5	2		T23	1
auto[268435456:402653183]	auto[1]	9	1			T381	2		T327	1		T399	1
auto[402653184:536870911]	auto[0]	82	1			T16	1		T5	2		T7	1
auto[402653184:536870911]	auto[1]	7	1			T221	1		T340	2		T406	1
auto[536870912:671088639]	auto[0]	85	1			T1	1		T16	1		T5	1
auto[536870912:671088639]	auto[1]	11	1			T77	1		T327	3		T399	1
auto[671088640:805306367]	auto[0]	82	1			T5	1		T125	1		T43	1
auto[671088640:805306367]	auto[1]	10	1			T224	1		T238	1		T410	1
auto[805306368:939524095]	auto[0]	92	1			T16	1		T33	1		T5	2
auto[805306368:939524095]	auto[1]	6	1			T75	1		T251	1		T405	2
auto[939524096:1073741823]	auto[0]	81	1			T33	1		T126	1		T29	1
auto[939524096:1073741823]	auto[1]	10	1			T221	1		T381	1		T252	1
auto[1073741824:1207959551]	auto[0]	88	1			T16	1		T24	2		T183	1
auto[1073741824:1207959551]	auto[1]	13	1			T79	1		T224	1		T225	3
auto[1207959552:1342177279]	auto[0]	87	1			T43	1		T79	1		T94	1
auto[1207959552:1342177279]	auto[1]	9	1			T221	1		T381	1		T327	1
auto[1342177280:1476395007]	auto[0]	83	1			T21	1		T181	1		T91	2
auto[1342177280:1476395007]	auto[1]	7	1			T77	1		T284	1		T340	1
auto[1476395008:1610612735]	auto[0]	95	1			T22	1		T181	1		T186	1
auto[1476395008:1610612735]	auto[1]	5	1			T221	1		T327	1		T399	1
auto[1610612736:1744830463]	auto[0]	95	1			T1	1		T21	1		T181	1
auto[1610612736:1744830463]	auto[1]	6	1			T399	1		T405	1		T355	1
auto[1744830464:1879048191]	auto[0]	88	1			T24	1		T5	2		T25	1
auto[1744830464:1879048191]	auto[1]	12	1			T77	2		T327	1		T303	2
auto[1879048192:2013265919]	auto[0]	88	1			T5	2		T181	2		T183	1
auto[1879048192:2013265919]	auto[1]	6	1			T366	1		T426	1		T343	1
auto[2013265920:2147483647]	auto[0]	103	1			T24	1		T21	1		T25	1
auto[2013265920:2147483647]	auto[1]	4	1			T278	1		T405	1		T426	1
auto[2147483648:2281701375]	auto[0]	66	1			T24	1		T5	3		T34	1
auto[2147483648:2281701375]	auto[1]	5	1			T303	1		T405	1		T298	1
auto[2281701376:2415919103]	auto[0]	76	1			T5	3		T104	1		T223	1
auto[2281701376:2415919103]	auto[1]	6	1			T77	1		T343	1		T427	1
auto[2415919104:2550136831]	auto[0]	86	1			T5	3		T42	1		T103	1
auto[2415919104:2550136831]	auto[1]	4	1			T221	1		T327	1		T238	1
auto[2550136832:2684354559]	auto[0]	75	1			T194	1		T98	1		T100	1
auto[2550136832:2684354559]	auto[1]	13	1			T303	1		T406	1		T298	1
auto[2684354560:2818572287]	auto[0]	81	1			T5	2		T28	1		T94	1
auto[2684354560:2818572287]	auto[1]	7	1			T327	2		T303	1		T405	1
auto[2818572288:2952790015]	auto[0]	80	1			T5	2		T181	1		T6	1
auto[2818572288:2952790015]	auto[1]	4	1			T225	1		T407	1		T413	2
auto[2952790016:3087007743]	auto[0]	77	1			T5	1		T23	2		T26	1
auto[2952790016:3087007743]	auto[1]	9	1			T368	1		T284	2		T340	1
auto[3087007744:3221225471]	auto[0]	83	1			T16	1		T24	1		T25	1
auto[3087007744:3221225471]	auto[1]	4	1			T225	1		T298	1		T427	1
auto[3221225472:3355443199]	auto[0]	67	1			T44	1		T43	1		T74	1
auto[3221225472:3355443199]	auto[1]	12	1			T381	1		T224	1		T399	1
auto[3355443200:3489660927]	auto[0]	93	1			T183	1		T91	1		T75	1
auto[3355443200:3489660927]	auto[1]	14	1			T77	1		T221	1		T224	1
auto[3489660928:3623878655]	auto[0]	66	1			T22	2		T181	1		T45	1
auto[3489660928:3623878655]	auto[1]	8	1			T288	1		T303	1		T252	1
auto[3623878656:3758096383]	auto[0]	97	1			T1	1		T14	1		T5	1
auto[3623878656:3758096383]	auto[1]	2	1			T238	1		T428	1		-	-
auto[3758096384:3892314111]	auto[0]	110	1			T24	1		T45	1		T183	1
auto[3758096384:3892314111]	auto[1]	9	1			T288	1		T410	1		T405	1
auto[3892314112:4026531839]	auto[0]	81	1			T1	1		T21	1		T22	1
auto[3892314112:4026531839]	auto[1]	9	1			T79	1		T381	1		T327	1
auto[4026531840:4160749567]	auto[0]	86	1			T5	1		T126	1		T43	1
auto[4026531840:4160749567]	auto[1]	14	1			T75	1		T288	1		T327	1
auto[4160749568:4294967295]	auto[0]	81	1			T1	1		T8	1		T5	2
auto[4160749568:4294967295]	auto[1]	6	1			T224	1		T238	1		T284	2