Unified Coverage Report :: Group Instance : sealing_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1459

1

T1

1

T14

1

T16

1

auto[1]

1620

1

T1

4

T14

1

T8

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T5	4		T22	1		T194	1
auto[134217728:268435455]	104	1			T5	1		T181	1		T6	1
auto[268435456:402653183]	88	1			T33	1		T5	2		T42	1
auto[402653184:536870911]	101	1			T75	1		T193	1		T57	1
auto[536870912:671088639]	85	1			T5	4		T91	1		T43	1
auto[671088640:805306367]	104	1			T5	1		T22	1		T75	1
auto[805306368:939524095]	93	1			T16	1		T23	2		T183	1
auto[939524096:1073741823]	108	1			T24	1		T5	2		T45	1
auto[1073741824:1207959551]	85	1			T5	1		T22	1		T23	1
auto[1207959552:1342177279]	78	1			T5	2		T91	1		T43	1
auto[1342177280:1476395007]	82	1			T1	1		T5	1		T181	1
auto[1476395008:1610612735]	85	1			T1	1		T5	3		T25	1
auto[1610612736:1744830463]	101	1			T21	1		T5	2		T186	1
auto[1744830464:1879048191]	91	1			T21	1		T5	1		T25	1
auto[1879048192:2013265919]	107	1			T1	1		T16	1		T24	2
auto[2013265920:2147483647]	116	1			T5	3		T194	1		T43	1
auto[2147483648:2281701375]	108	1			T5	3		T181	1		T42	1
auto[2281701376:2415919103]	107	1			T1	1		T14	1		T24	1
auto[2415919104:2550136831]	101	1			T16	1		T24	1		T5	2
auto[2550136832:2684354559]	93	1			T8	1		T5	2		T42	1
auto[2684354560:2818572287]	87	1			T24	1		T5	2		T186	1
auto[2818572288:2952790015]	98	1			T16	1		T5	1		T186	1
auto[2952790016:3087007743]	102	1			T1	1		T33	1		T5	4
auto[3087007744:3221225471]	89	1			T5	1		T181	1		T7	2
auto[3221225472:3355443199]	104	1			T5	1		T189	1		T43	2
auto[3355443200:3489660927]	101	1			T5	2		T26	1		T43	2
auto[3489660928:3623878655]	113	1			T22	1		T181	1		T189	1
auto[3623878656:3758096383]	91	1			T8	1		T16	1		T5	2
auto[3758096384:3892314111]	93	1			T181	1		T23	1		T183	1
auto[3892314112:4026531839]	85	1			T14	1		T5	1		T22	1
auto[4026531840:4160749567]	85	1			T21	1		T5	1		T181	1
auto[4160749568:4294967295]	94	1			T24	1		T33	1		T5	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T5	2		T22	1		T43	1
auto[0:134217727]	auto[1]	47	1			T5	2		T194	1		T37	1
auto[134217728:268435455]	auto[0]	51	1			T5	1		T7	1		T98	1
auto[134217728:268435455]	auto[1]	53	1			T181	1		T6	1		T74	1
auto[268435456:402653183]	auto[0]	47	1			T42	1		T48	1		T101	2
auto[268435456:402653183]	auto[1]	41	1			T33	1		T5	2		T126	1
auto[402653184:536870911]	auto[0]	46	1			T193	1		T86	1		T93	1
auto[402653184:536870911]	auto[1]	55	1			T75	1		T57	1		T220	1
auto[536870912:671088639]	auto[0]	47	1			T5	3		T91	1		T43	1
auto[536870912:671088639]	auto[1]	38	1			T5	1		T9	1		T60	1
auto[671088640:805306367]	auto[0]	48	1			T89	1		T57	2		T60	1
auto[671088640:805306367]	auto[1]	56	1			T5	1		T22	1		T75	1
auto[805306368:939524095]	auto[0]	42	1			T23	2		T74	1		T94	1
auto[805306368:939524095]	auto[1]	51	1			T16	1		T183	1		T43	1
auto[939524096:1073741823]	auto[0]	48	1			T24	1		T100	1		T101	1
auto[939524096:1073741823]	auto[1]	60	1			T5	2		T45	1		T92	1
auto[1073741824:1207959551]	auto[0]	45	1			T5	1		T22	1		T23	1
auto[1073741824:1207959551]	auto[1]	40	1			T37	1		T57	1		T230	1
auto[1207959552:1342177279]	auto[0]	40	1			T5	2		T91	1		T43	1
auto[1207959552:1342177279]	auto[1]	38	1			T74	1		T354	1		T55	1
auto[1342177280:1476395007]	auto[0]	38	1			T181	1		T43	1		T75	1
auto[1342177280:1476395007]	auto[1]	44	1			T1	1		T5	1		T99	1
auto[1476395008:1610612735]	auto[0]	39	1			T1	1		T5	1		T43	1
auto[1476395008:1610612735]	auto[1]	46	1			T5	2		T25	1		T28	1
auto[1610612736:1744830463]	auto[0]	52	1			T21	1		T5	1		T43	1
auto[1610612736:1744830463]	auto[1]	49	1			T5	1		T186	1		T43	2
auto[1744830464:1879048191]	auto[0]	38	1			T5	1		T25	1		T77	1
auto[1744830464:1879048191]	auto[1]	53	1			T21	1		T45	1		T43	1
auto[1879048192:2013265919]	auto[0]	44	1			T25	1		T186	1		T126	1
auto[1879048192:2013265919]	auto[1]	63	1			T1	1		T16	1		T24	2
auto[2013265920:2147483647]	auto[0]	57	1			T5	1		T77	1		T27	1
auto[2013265920:2147483647]	auto[1]	59	1			T5	2		T194	1		T43	1
auto[2147483648:2281701375]	auto[0]	48	1			T5	2		T181	1		T42	1
auto[2147483648:2281701375]	auto[1]	60	1			T5	1		T23	1		T194	1
auto[2281701376:2415919103]	auto[0]	49	1			T21	1		T91	1		T77	1
auto[2281701376:2415919103]	auto[1]	58	1			T1	1		T14	1		T24	1
auto[2415919104:2550136831]	auto[0]	47	1			T16	1		T5	2		T98	1
auto[2415919104:2550136831]	auto[1]	54	1			T24	1		T183	1		T56	1
auto[2550136832:2684354559]	auto[0]	43	1			T5	1		T42	1		T43	1
auto[2550136832:2684354559]	auto[1]	50	1			T8	1		T5	1		T57	1
auto[2684354560:2818572287]	auto[0]	44	1			T24	1		T5	1		T100	1
auto[2684354560:2818572287]	auto[1]	43	1			T5	1		T186	1		T43	2
auto[2818572288:2952790015]	auto[0]	49	1			T5	1		T186	1		T56	1
auto[2818572288:2952790015]	auto[1]	49	1			T16	1		T43	1		T50	1
auto[2952790016:3087007743]	auto[0]	40	1			T5	2		T94	1		T121	1
auto[2952790016:3087007743]	auto[1]	62	1			T1	1		T33	1		T5	2
auto[3087007744:3221225471]	auto[0]	41	1			T181	1		T43	1		T133	1
auto[3087007744:3221225471]	auto[1]	48	1			T5	1		T7	2		T43	1
auto[3221225472:3355443199]	auto[0]	43	1			T5	1		T43	1		T77	1
auto[3221225472:3355443199]	auto[1]	61	1			T189	1		T43	1		T29	1
auto[3355443200:3489660927]	auto[0]	64	1			T5	2		T26	1		T100	1
auto[3355443200:3489660927]	auto[1]	37	1			T43	2		T75	1		T102	1
auto[3489660928:3623878655]	auto[0]	50	1			T22	1		T181	1		T42	1
auto[3489660928:3623878655]	auto[1]	63	1			T189	1		T126	1		T79	1
auto[3623878656:3758096383]	auto[0]	43	1			T5	1		T91	1		T43	1
auto[3623878656:3758096383]	auto[1]	48	1			T8	1		T16	1		T5	1
auto[3758096384:3892314111]	auto[0]	34	1			T23	1		T125	1		T35	1
auto[3758096384:3892314111]	auto[1]	59	1			T181	1		T183	1		T43	2
auto[3892314112:4026531839]	auto[0]	42	1			T14	1		T5	1		T22	1
auto[3892314112:4026531839]	auto[1]	43	1			T79	1		T218	1		T46	1
auto[4026531840:4160749567]	auto[0]	43	1			T21	1		T5	1		T43	1
auto[4026531840:4160749567]	auto[1]	42	1			T181	1		T219	1		T231	2
auto[4160749568:4294967295]	auto[0]	44	1			T24	1		T5	1		T42	1
auto[4160749568:4294967295]	auto[1]	50	1			T33	1		T44	1		T43	1