Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4018

1

T16

6

T24

14

T21

4

auto[1]

2149

1

T1

10

T14

4

T8

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	152	1			T5	2		T189	2		T7	2
auto[134217728:268435455]	194	1			T43	2		T98	2		T50	2
auto[268435456:402653183]	158	1			T181	2		T7	2		T79	2
auto[402653184:536870911]	160	1			T8	2		T16	2		T24	2
auto[536870912:671088639]	216	1			T5	2		T45	2		T186	2
auto[671088640:805306367]	212	1			T1	2		T24	4		T5	6
auto[805306368:939524095]	238	1			T8	2		T5	4		T22	2
auto[939524096:1073741823]	182	1			T26	2		T28	2		T34	2
auto[1073741824:1207959551]	200	1			T16	2		T33	2		T5	2
auto[1207959552:1342177279]	197	1			T24	2		T22	2		T23	2
auto[1342177280:1476395007]	170	1			T5	2		T44	2		T194	2
auto[1476395008:1610612735]	186	1			T24	2		T5	2		T23	2
auto[1610612736:1744830463]	208	1			T21	2		T5	6		T22	2
auto[1744830464:1879048191]	152	1			T1	2		T43	2		T77	2
auto[1879048192:2013265919]	158	1			T33	2		T181	2		T43	6
auto[2013265920:2147483647]	194	1			T33	2		T5	4		T42	2
auto[2147483648:2281701375]	216	1			T24	2		T194	2		T125	2
auto[2281701376:2415919103]	196	1			T16	2		T5	4		T56	2
auto[2415919104:2550136831]	184	1			T21	2		T5	4		T25	4
auto[2550136832:2684354559]	212	1			T14	2		T5	6		T74	2
auto[2684354560:2818572287]	226	1			T1	2		T5	6		T22	2
auto[2818572288:2952790015]	160	1			T5	4		T91	2		T94	2
auto[2952790016:3087007743]	218	1			T21	4		T5	4		T99	2
auto[3087007744:3221225471]	234	1			T33	2		T5	6		T181	2
auto[3221225472:3355443199]	196	1			T1	2		T24	2		T5	4
auto[3355443200:3489660927]	194	1			T16	2		T5	6		T23	2
auto[3489660928:3623878655]	186	1			T5	10		T22	2		T23	2
auto[3623878656:3758096383]	180	1			T16	2		T5	2		T25	2
auto[3758096384:3892314111]	188	1			T14	2		T5	2		T183	2
auto[3892314112:4026531839]	204	1			T5	4		T186	2		T28	2
auto[4026531840:4160749567]	200	1			T5	2		T181	2		T183	2
auto[4160749568:4294967295]	196	1			T1	2		T5	8		T181	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	98	1			T189	2		T43	2		T89	2
auto[0:134217727]	auto[1]	54	1			T5	2		T7	2		T91	2
auto[134217728:268435455]	auto[0]	130	1			T50	2		T188	2		T300	2
auto[134217728:268435455]	auto[1]	64	1			T43	2		T98	2		T89	2
auto[268435456:402653183]	auto[0]	108	1			T181	2		T7	2		T79	2
auto[268435456:402653183]	auto[1]	50	1			T48	2		T50	2		T419	2
auto[402653184:536870911]	auto[0]	96	1			T16	2		T24	2		T5	2
auto[402653184:536870911]	auto[1]	64	1			T8	2		T43	2		T48	2
auto[536870912:671088639]	auto[0]	150	1			T45	2		T186	2		T43	2
auto[536870912:671088639]	auto[1]	66	1			T5	2		T75	2		T78	2
auto[671088640:805306367]	auto[0]	162	1			T24	4		T5	6		T181	2
auto[671088640:805306367]	auto[1]	50	1			T1	2		T23	2		T43	2
auto[805306368:939524095]	auto[0]	148	1			T5	4		T22	2		T45	2
auto[805306368:939524095]	auto[1]	90	1			T8	2		T43	2		T77	2
auto[939524096:1073741823]	auto[0]	86	1			T49	2		T89	6		T57	2
auto[939524096:1073741823]	auto[1]	96	1			T26	2		T28	2		T34	2
auto[1073741824:1207959551]	auto[0]	122	1			T16	2		T5	2		T42	2
auto[1073741824:1207959551]	auto[1]	78	1			T33	2		T56	2		T43	4
auto[1207959552:1342177279]	auto[0]	126	1			T24	2		T22	2		T43	2
auto[1207959552:1342177279]	auto[1]	71	1			T23	2		T7	2		T26	2
auto[1342177280:1476395007]	auto[0]	118	1			T5	2		T194	2		T100	2
auto[1342177280:1476395007]	auto[1]	52	1			T44	2		T420	2		T59	2
auto[1476395008:1610612735]	auto[0]	122	1			T24	2		T5	2		T23	2
auto[1476395008:1610612735]	auto[1]	64	1			T121	2		T381	2		T52	2
auto[1610612736:1744830463]	auto[0]	128	1			T5	4		T183	2		T43	4
auto[1610612736:1744830463]	auto[1]	80	1			T21	2		T5	2		T22	2
auto[1744830464:1879048191]	auto[0]	100	1			T102	2		T52	2		T233	2
auto[1744830464:1879048191]	auto[1]	52	1			T1	2		T43	2		T77	2
auto[1879048192:2013265919]	auto[0]	118	1			T181	2		T43	6		T354	2
auto[1879048192:2013265919]	auto[1]	40	1			T33	2		T83	2		T376	2
auto[2013265920:2147483647]	auto[0]	130	1			T5	4		T56	2		T74	4
auto[2013265920:2147483647]	auto[1]	64	1			T33	2		T42	2		T81	2
auto[2147483648:2281701375]	auto[0]	144	1			T24	2		T194	2		T125	2
auto[2147483648:2281701375]	auto[1]	72	1			T43	4		T35	2		T92	2
auto[2281701376:2415919103]	auto[0]	148	1			T16	2		T5	4		T56	2
auto[2281701376:2415919103]	auto[1]	48	1			T26	2		T98	2		T200	2
auto[2415919104:2550136831]	auto[0]	106	1			T21	2		T5	2		T25	2
auto[2415919104:2550136831]	auto[1]	78	1			T5	2		T25	2		T77	2
auto[2550136832:2684354559]	auto[0]	152	1			T5	2		T74	2		T29	2
auto[2550136832:2684354559]	auto[1]	60	1			T14	2		T5	4		T57	2
auto[2684354560:2818572287]	auto[0]	142	1			T5	6		T22	2		T183	2
auto[2684354560:2818572287]	auto[1]	84	1			T1	2		T126	2		T77	2
auto[2818572288:2952790015]	auto[0]	112	1			T5	2		T94	2		T49	2
auto[2818572288:2952790015]	auto[1]	48	1			T5	2		T91	2		T102	2
auto[2952790016:3087007743]	auto[0]	138	1			T21	2		T5	4		T99	2
auto[2952790016:3087007743]	auto[1]	80	1			T21	2		T121	2		T55	2
auto[3087007744:3221225471]	auto[0]	140	1			T181	2		T57	4		T218	2
auto[3087007744:3221225471]	auto[1]	94	1			T33	2		T5	6		T189	2
auto[3221225472:3355443199]	auto[0]	140	1			T24	2		T5	4		T181	2
auto[3221225472:3355443199]	auto[1]	56	1			T1	2		T42	2		T43	2
auto[3355443200:3489660927]	auto[0]	120	1			T5	4		T23	2		T43	2
auto[3355443200:3489660927]	auto[1]	74	1			T16	2		T5	2		T6	2
auto[3489660928:3623878655]	auto[0]	110	1			T5	6		T22	2		T7	2
auto[3489660928:3623878655]	auto[1]	76	1			T5	4		T23	2		T186	2
auto[3623878656:3758096383]	auto[0]	114	1			T5	2		T25	2		T55	2
auto[3623878656:3758096383]	auto[1]	66	1			T16	2		T186	2		T183	2
auto[3758096384:3892314111]	auto[0]	124	1			T5	2		T183	2		T26	2
auto[3758096384:3892314111]	auto[1]	64	1			T14	2		T77	2		T233	2
auto[3892314112:4026531839]	auto[0]	132	1			T5	4		T43	2		T79	2
auto[3892314112:4026531839]	auto[1]	72	1			T186	2		T28	2		T98	2
auto[4026531840:4160749567]	auto[0]	116	1			T5	2		T181	2		T183	2
auto[4026531840:4160749567]	auto[1]	84	1			T43	2		T50	2		T104	2
auto[4160749568:4294967295]	auto[0]	138	1			T5	6		T181	2		T126	2
auto[4160749568:4294967295]	auto[1]	58	1			T1	2		T5	2		T6	2