Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.82 99.10 98.03 98.46 100.00 99.11 98.41 91.66


Total test records in report: 1078
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T1013 /workspace/coverage/default/44.keymgr_sideload_aes.1958189259 Mar 23 04:02:17 PM PDT 24 Mar 23 04:02:21 PM PDT 24 110177739 ps
T162 /workspace/coverage/default/16.keymgr_sync_async_fault_cross.571245881 Mar 23 04:00:43 PM PDT 24 Mar 23 04:00:47 PM PDT 24 331226029 ps
T1014 /workspace/coverage/default/0.keymgr_sync_async_fault_cross.75428190 Mar 23 03:59:24 PM PDT 24 Mar 23 03:59:28 PM PDT 24 308052251 ps
T413 /workspace/coverage/default/8.keymgr_cfg_regwen.4084716234 Mar 23 04:00:10 PM PDT 24 Mar 23 04:02:49 PM PDT 24 40705456433 ps
T1015 /workspace/coverage/default/35.keymgr_sw_invalid_input.3941112011 Mar 23 04:01:47 PM PDT 24 Mar 23 04:01:54 PM PDT 24 180076951 ps
T352 /workspace/coverage/default/11.keymgr_kmac_rsp_err.2198067551 Mar 23 04:00:25 PM PDT 24 Mar 23 04:01:37 PM PDT 24 6040496186 ps
T1016 /workspace/coverage/default/43.keymgr_custom_cm.166114184 Mar 23 04:02:23 PM PDT 24 Mar 23 04:02:26 PM PDT 24 302068485 ps
T1017 /workspace/coverage/default/23.keymgr_stress_all.2263538646 Mar 23 04:01:08 PM PDT 24 Mar 23 04:01:19 PM PDT 24 705305348 ps
T1018 /workspace/coverage/default/35.keymgr_alert_test.3793824296 Mar 23 04:01:50 PM PDT 24 Mar 23 04:01:51 PM PDT 24 161467797 ps
T1019 /workspace/coverage/default/13.keymgr_sideload.4194288180 Mar 23 04:00:36 PM PDT 24 Mar 23 04:00:39 PM PDT 24 96552527 ps
T1020 /workspace/coverage/default/4.keymgr_custom_cm.927892215 Mar 23 03:59:57 PM PDT 24 Mar 23 04:00:02 PM PDT 24 96358438 ps
T1021 /workspace/coverage/default/6.keymgr_sync_async_fault_cross.40944628 Mar 23 04:00:12 PM PDT 24 Mar 23 04:00:16 PM PDT 24 189824655 ps
T1022 /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3754793910 Mar 23 04:02:29 PM PDT 24 Mar 23 04:02:37 PM PDT 24 1157749987 ps
T1023 /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.859733092 Mar 23 04:00:27 PM PDT 24 Mar 23 04:00:41 PM PDT 24 1284450356 ps
T1024 /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2475330767 Mar 23 04:01:49 PM PDT 24 Mar 23 04:02:07 PM PDT 24 2655574888 ps
T1025 /workspace/coverage/default/3.keymgr_sideload.2644992588 Mar 23 03:59:46 PM PDT 24 Mar 23 03:59:55 PM PDT 24 2006557333 ps
T1026 /workspace/coverage/default/2.keymgr_lc_disable.1286421873 Mar 23 03:59:44 PM PDT 24 Mar 23 03:59:50 PM PDT 24 91561243 ps
T1027 /workspace/coverage/default/12.keymgr_sideload_protect.822093534 Mar 23 04:00:26 PM PDT 24 Mar 23 04:00:29 PM PDT 24 587035792 ps
T1028 /workspace/coverage/default/27.keymgr_sideload_protect.1529008661 Mar 23 04:01:20 PM PDT 24 Mar 23 04:01:57 PM PDT 24 1370675260 ps
T1029 /workspace/coverage/default/47.keymgr_sideload_otbn.2055268396 Mar 23 04:02:30 PM PDT 24 Mar 23 04:02:36 PM PDT 24 1868157416 ps
T1030 /workspace/coverage/default/17.keymgr_custom_cm.240306846 Mar 23 04:00:48 PM PDT 24 Mar 23 04:00:53 PM PDT 24 217557422 ps
T1031 /workspace/coverage/default/24.keymgr_sideload_protect.346339307 Mar 23 04:01:10 PM PDT 24 Mar 23 04:01:14 PM PDT 24 217316974 ps
T1032 /workspace/coverage/default/44.keymgr_random.1204376780 Mar 23 04:02:22 PM PDT 24 Mar 23 04:02:26 PM PDT 24 103854365 ps
T1033 /workspace/coverage/default/14.keymgr_sideload_otbn.2223310912 Mar 23 04:00:37 PM PDT 24 Mar 23 04:00:40 PM PDT 24 35746054 ps
T1034 /workspace/coverage/default/28.keymgr_sideload.2953578078 Mar 23 04:01:20 PM PDT 24 Mar 23 04:01:28 PM PDT 24 307017630 ps
T1035 /workspace/coverage/default/16.keymgr_sideload_otbn.3928913212 Mar 23 04:00:39 PM PDT 24 Mar 23 04:00:44 PM PDT 24 108763009 ps
T1036 /workspace/coverage/default/33.keymgr_cfg_regwen.697681196 Mar 23 04:01:40 PM PDT 24 Mar 23 04:01:44 PM PDT 24 167155162 ps
T1037 /workspace/coverage/default/15.keymgr_random.437055643 Mar 23 04:00:39 PM PDT 24 Mar 23 04:00:45 PM PDT 24 236876659 ps
T1038 /workspace/coverage/default/24.keymgr_sideload.4035501464 Mar 23 04:01:06 PM PDT 24 Mar 23 04:01:11 PM PDT 24 1863629234 ps
T1039 /workspace/coverage/default/16.keymgr_smoke.2311440893 Mar 23 04:00:36 PM PDT 24 Mar 23 04:00:39 PM PDT 24 102314027 ps
T1040 /workspace/coverage/default/15.keymgr_sideload_kmac.1692592207 Mar 23 04:00:37 PM PDT 24 Mar 23 04:00:40 PM PDT 24 135552166 ps
T1041 /workspace/coverage/default/41.keymgr_direct_to_disabled.4287374813 Mar 23 04:02:08 PM PDT 24 Mar 23 04:02:10 PM PDT 24 39248172 ps
T1042 /workspace/coverage/default/25.keymgr_sync_async_fault_cross.680156683 Mar 23 04:01:19 PM PDT 24 Mar 23 04:01:22 PM PDT 24 111178147 ps
T1043 /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3716211245 Mar 23 04:01:37 PM PDT 24 Mar 23 04:01:39 PM PDT 24 223741904 ps
T1044 /workspace/coverage/default/34.keymgr_sideload_aes.3653180412 Mar 23 04:01:35 PM PDT 24 Mar 23 04:01:39 PM PDT 24 65421109 ps
T1045 /workspace/coverage/default/3.keymgr_lc_disable.290119491 Mar 23 03:59:44 PM PDT 24 Mar 23 03:59:54 PM PDT 24 1135394916 ps
T1046 /workspace/coverage/default/27.keymgr_stress_all.1060179774 Mar 23 04:01:22 PM PDT 24 Mar 23 04:01:38 PM PDT 24 1065823163 ps
T1047 /workspace/coverage/default/14.keymgr_sw_invalid_input.2411239313 Mar 23 04:00:39 PM PDT 24 Mar 23 04:01:24 PM PDT 24 6487729997 ps
T1048 /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3361518312 Mar 23 04:01:04 PM PDT 24 Mar 23 04:01:14 PM PDT 24 1278888094 ps
T1049 /workspace/coverage/default/46.keymgr_sideload_otbn.2015400252 Mar 23 04:02:28 PM PDT 24 Mar 23 04:02:34 PM PDT 24 241897989 ps
T1050 /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1808804307 Mar 23 04:00:35 PM PDT 24 Mar 23 04:00:40 PM PDT 24 491525487 ps
T1051 /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2431048975 Mar 23 04:01:51 PM PDT 24 Mar 23 04:01:53 PM PDT 24 120541317 ps
T1052 /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1901051575 Mar 23 04:02:03 PM PDT 24 Mar 23 04:02:07 PM PDT 24 72138044 ps
T1053 /workspace/coverage/default/47.keymgr_random.2342409586 Mar 23 04:02:28 PM PDT 24 Mar 23 04:02:37 PM PDT 24 1053880335 ps
T1054 /workspace/coverage/default/25.keymgr_sideload_kmac.2048198405 Mar 23 04:01:22 PM PDT 24 Mar 23 04:02:12 PM PDT 24 6844584192 ps
T1055 /workspace/coverage/default/7.keymgr_sync_async_fault_cross.509911955 Mar 23 04:00:12 PM PDT 24 Mar 23 04:00:15 PM PDT 24 82433784 ps
T208 /workspace/coverage/default/28.keymgr_custom_cm.1914543837 Mar 23 04:01:35 PM PDT 24 Mar 23 04:01:38 PM PDT 24 87830803 ps
T240 /workspace/coverage/default/21.keymgr_lc_disable.1508265978 Mar 23 04:01:04 PM PDT 24 Mar 23 04:01:09 PM PDT 24 424647697 ps
T1056 /workspace/coverage/default/41.keymgr_kmac_rsp_err.3155760322 Mar 23 04:01:57 PM PDT 24 Mar 23 04:02:03 PM PDT 24 317893032 ps
T1057 /workspace/coverage/default/23.keymgr_sideload.2451124249 Mar 23 04:01:01 PM PDT 24 Mar 23 04:01:15 PM PDT 24 3496881734 ps
T325 /workspace/coverage/default/12.keymgr_kmac_rsp_err.1442917797 Mar 23 04:00:22 PM PDT 24 Mar 23 04:00:57 PM PDT 24 5512359726 ps
T1058 /workspace/coverage/default/18.keymgr_lc_disable.1838478054 Mar 23 04:00:52 PM PDT 24 Mar 23 04:00:59 PM PDT 24 321303133 ps
T1059 /workspace/coverage/default/8.keymgr_custom_cm.1803953023 Mar 23 04:00:16 PM PDT 24 Mar 23 04:00:21 PM PDT 24 88071726 ps
T1060 /workspace/coverage/default/28.keymgr_stress_all.2100847603 Mar 23 04:01:37 PM PDT 24 Mar 23 04:02:20 PM PDT 24 1352719257 ps
T1061 /workspace/coverage/default/26.keymgr_sideload_kmac.1939515020 Mar 23 04:01:21 PM PDT 24 Mar 23 04:02:06 PM PDT 24 1874018154 ps
T429 /workspace/coverage/default/1.keymgr_cfg_regwen.819207585 Mar 23 03:59:39 PM PDT 24 Mar 23 03:59:54 PM PDT 24 245383393 ps
T1062 /workspace/coverage/default/40.keymgr_smoke.1236061083 Mar 23 04:02:04 PM PDT 24 Mar 23 04:02:08 PM PDT 24 265511790 ps
T1063 /workspace/coverage/default/1.keymgr_smoke.2918329462 Mar 23 03:59:37 PM PDT 24 Mar 23 03:59:41 PM PDT 24 367242007 ps
T326 /workspace/coverage/default/5.keymgr_kmac_rsp_err.2704064329 Mar 23 04:00:06 PM PDT 24 Mar 23 04:00:16 PM PDT 24 214030460 ps
T1064 /workspace/coverage/default/33.keymgr_sw_invalid_input.1121746213 Mar 23 04:01:40 PM PDT 24 Mar 23 04:01:44 PM PDT 24 115001134 ps
T1065 /workspace/coverage/default/40.keymgr_lc_disable.375032566 Mar 23 04:02:04 PM PDT 24 Mar 23 04:02:09 PM PDT 24 252941902 ps
T386 /workspace/coverage/default/11.keymgr_hwsw_invalid_input.568045545 Mar 23 04:00:25 PM PDT 24 Mar 23 04:00:28 PM PDT 24 88119534 ps
T1066 /workspace/coverage/default/0.keymgr_sideload.1441927435 Mar 23 03:59:29 PM PDT 24 Mar 23 03:59:33 PM PDT 24 115202107 ps
T1067 /workspace/coverage/default/35.keymgr_random.2326508427 Mar 23 04:01:53 PM PDT 24 Mar 23 04:01:59 PM PDT 24 385168271 ps
T1068 /workspace/coverage/default/10.keymgr_sideload.417994309 Mar 23 04:00:25 PM PDT 24 Mar 23 04:00:27 PM PDT 24 287163029 ps
T1069 /workspace/coverage/default/3.keymgr_sideload_otbn.791499525 Mar 23 03:59:46 PM PDT 24 Mar 23 04:00:32 PM PDT 24 1983789286 ps
T428 /workspace/coverage/default/17.keymgr_cfg_regwen.2746229174 Mar 23 04:00:45 PM PDT 24 Mar 23 04:01:33 PM PDT 24 1095314124 ps
T1070 /workspace/coverage/default/11.keymgr_cfg_regwen.787373161 Mar 23 04:00:23 PM PDT 24 Mar 23 04:00:29 PM PDT 24 331940127 ps
T1071 /workspace/coverage/default/33.keymgr_sideload_protect.2493962927 Mar 23 04:01:40 PM PDT 24 Mar 23 04:01:43 PM PDT 24 183853228 ps
T333 /workspace/coverage/default/11.keymgr_sw_invalid_input.3347061485 Mar 23 04:00:24 PM PDT 24 Mar 23 04:00:29 PM PDT 24 345995036 ps
T1072 /workspace/coverage/default/11.keymgr_sideload.2177607373 Mar 23 04:00:25 PM PDT 24 Mar 23 04:00:35 PM PDT 24 1407211004 ps
T1073 /workspace/coverage/default/47.keymgr_direct_to_disabled.690594250 Mar 23 04:02:27 PM PDT 24 Mar 23 04:02:33 PM PDT 24 491784192 ps
T250 /workspace/coverage/default/47.keymgr_sideload.1252890874 Mar 23 04:02:26 PM PDT 24 Mar 23 04:02:33 PM PDT 24 149859328 ps
T1074 /workspace/coverage/default/26.keymgr_kmac_rsp_err.1861120701 Mar 23 04:01:22 PM PDT 24 Mar 23 04:01:30 PM PDT 24 488376990 ps
T1075 /workspace/coverage/default/45.keymgr_sideload_aes.2337377716 Mar 23 04:02:16 PM PDT 24 Mar 23 04:02:19 PM PDT 24 117011273 ps
T1076 /workspace/coverage/default/31.keymgr_sideload_aes.1493619096 Mar 23 04:01:40 PM PDT 24 Mar 23 04:01:45 PM PDT 24 329760310 ps
T1077 /workspace/coverage/default/40.keymgr_sw_invalid_input.738856896 Mar 23 04:02:00 PM PDT 24 Mar 23 04:02:23 PM PDT 24 3395189792 ps
T1078 /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3511581298 Mar 23 03:59:58 PM PDT 24 Mar 23 04:00:09 PM PDT 24 2629369968 ps

Test location /workspace/coverage/default/9.keymgr_custom_cm.1000396486
Short name T8
Test name
Test status
Simulation time 57262229 ps
CPU time 3.38 seconds
Started Mar 23 04:00:23 PM PDT 24
Finished Mar 23 04:00:27 PM PDT 24
Peak memory 217248 kb
Host smart-c7a4fa6e-a85e-46ba-a82a-302d5955a78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000396486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1000396486
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.959295389
Short name T5
Test name
Test status
Simulation time 3064137150 ps
CPU time 109.21 seconds
Started Mar 23 04:00:10 PM PDT 24
Finished Mar 23 04:01:59 PM PDT 24
Peak memory 222456 kb
Host smart-d92877ff-4fba-4c2e-a41a-e8ee718e1f17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959295389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.959295389
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.613955510
Short name T43
Test name
Test status
Simulation time 1951147937 ps
CPU time 41.36 seconds
Started Mar 23 04:01:35 PM PDT 24
Finished Mar 23 04:02:17 PM PDT 24
Peak memory 222528 kb
Host smart-64d49710-24bc-4d1a-84d2-f515baea126a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613955510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.613955510
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2517874197
Short name T104
Test name
Test status
Simulation time 1435796863 ps
CPU time 6.54 seconds
Started Mar 23 04:02:26 PM PDT 24
Finished Mar 23 04:02:34 PM PDT 24
Peak memory 222556 kb
Host smart-618613c0-044c-42cc-a4e2-21bd4338ef1c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517874197 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2517874197
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.572400850
Short name T39
Test name
Test status
Simulation time 1557581116 ps
CPU time 19.36 seconds
Started Mar 23 04:00:00 PM PDT 24
Finished Mar 23 04:00:20 PM PDT 24
Peak memory 231704 kb
Host smart-071fc8d0-5f78-4221-8bc2-42027df69997
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572400850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.572400850
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3784306582
Short name T46
Test name
Test status
Simulation time 1320293764 ps
CPU time 48.66 seconds
Started Mar 23 04:00:35 PM PDT 24
Finished Mar 23 04:01:25 PM PDT 24
Peak memory 222620 kb
Host smart-d232f619-6e4e-45aa-ad32-7d4eaddaf00c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784306582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3784306582
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.311843549
Short name T24
Test name
Test status
Simulation time 111349550 ps
CPU time 4.93 seconds
Started Mar 23 04:00:23 PM PDT 24
Finished Mar 23 04:00:28 PM PDT 24
Peak memory 209396 kb
Host smart-af1eb38f-fd0e-4e96-8661-d862d34058b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311843549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.311843549
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2657327163
Short name T60
Test name
Test status
Simulation time 2046250523 ps
CPU time 21.18 seconds
Started Mar 23 03:59:59 PM PDT 24
Finished Mar 23 04:00:20 PM PDT 24
Peak memory 215452 kb
Host smart-51417d37-e059-46cc-ae82-47f04d7a0e6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657327163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2657327163
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1665610190
Short name T107
Test name
Test status
Simulation time 118385032 ps
CPU time 6.15 seconds
Started Mar 23 01:56:31 PM PDT 24
Finished Mar 23 01:56:38 PM PDT 24
Peak memory 213712 kb
Host smart-021c2360-0c5c-4c5e-a207-4d17ad6e45fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665610190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1665610190
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.636076079
Short name T77
Test name
Test status
Simulation time 226090812 ps
CPU time 12.44 seconds
Started Mar 23 04:02:29 PM PDT 24
Finished Mar 23 04:02:43 PM PDT 24
Peak memory 214272 kb
Host smart-23da4948-b54c-47c8-8b8d-b76ee9163533
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=636076079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.636076079
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2635492963
Short name T23
Test name
Test status
Simulation time 46698102 ps
CPU time 3.56 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:26 PM PDT 24
Peak memory 219380 kb
Host smart-7dce8415-101f-4afe-b55d-9a2083d9fa1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635492963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2635492963
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1608902714
Short name T340
Test name
Test status
Simulation time 7080347946 ps
CPU time 175.42 seconds
Started Mar 23 04:01:35 PM PDT 24
Finished Mar 23 04:04:30 PM PDT 24
Peak memory 214972 kb
Host smart-41d10027-05aa-4941-92ce-7111829c490d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608902714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1608902714
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.452220396
Short name T59
Test name
Test status
Simulation time 908007644 ps
CPU time 38.21 seconds
Started Mar 23 04:01:01 PM PDT 24
Finished Mar 23 04:01:40 PM PDT 24
Peak memory 217556 kb
Host smart-24656089-c370-4101-994b-f298c3706a33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452220396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.452220396
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2693368097
Short name T284
Test name
Test status
Simulation time 4662540691 ps
CPU time 61.5 seconds
Started Mar 23 04:00:00 PM PDT 24
Finished Mar 23 04:01:02 PM PDT 24
Peak memory 215120 kb
Host smart-e9d1160f-c7f7-4b4a-9602-0f4841a1e3ce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2693368097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2693368097
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.4026050493
Short name T57
Test name
Test status
Simulation time 1179614720 ps
CPU time 38.21 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:02:15 PM PDT 24
Peak memory 217316 kb
Host smart-b4c040d8-c3e7-4ccb-929b-2238bf18e730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026050493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.4026050493
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1174183696
Short name T114
Test name
Test status
Simulation time 156733371 ps
CPU time 5.13 seconds
Started Mar 23 01:56:31 PM PDT 24
Finished Mar 23 01:56:36 PM PDT 24
Peak memory 221932 kb
Host smart-5235bb4a-6c4a-4320-9cde-e745771c26f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174183696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1174183696
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3216258951
Short name T121
Test name
Test status
Simulation time 77790850 ps
CPU time 3.64 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:40 PM PDT 24
Peak memory 210456 kb
Host smart-1024bc4e-d00d-43c1-9419-dd638d0f3460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216258951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3216258951
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3025651894
Short name T120
Test name
Test status
Simulation time 724615091 ps
CPU time 2.81 seconds
Started Mar 23 01:56:26 PM PDT 24
Finished Mar 23 01:56:29 PM PDT 24
Peak memory 213664 kb
Host smart-6231cb3e-74c8-4e2b-b8a9-46dcd0a9ad14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025651894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3025651894
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2746229174
Short name T428
Test name
Test status
Simulation time 1095314124 ps
CPU time 48.48 seconds
Started Mar 23 04:00:45 PM PDT 24
Finished Mar 23 04:01:33 PM PDT 24
Peak memory 214268 kb
Host smart-0518ff3b-f8d9-477a-8e6b-f68709e2d9b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2746229174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2746229174
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1130267878
Short name T146
Test name
Test status
Simulation time 359120684 ps
CPU time 5.9 seconds
Started Mar 23 01:56:37 PM PDT 24
Finished Mar 23 01:56:43 PM PDT 24
Peak memory 208952 kb
Host smart-0a4be8b0-3af6-4764-8c94-f9cf3428e9b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130267878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1130267878
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2893964058
Short name T327
Test name
Test status
Simulation time 119043319 ps
CPU time 6.34 seconds
Started Mar 23 04:00:39 PM PDT 24
Finished Mar 23 04:00:45 PM PDT 24
Peak memory 215204 kb
Host smart-a3cac4ff-a00f-49a0-b2b0-47a5bdf4a1d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2893964058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2893964058
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2699625930
Short name T298
Test name
Test status
Simulation time 4709717373 ps
CPU time 116.41 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:02:44 PM PDT 24
Peak memory 222348 kb
Host smart-938eafde-a434-4809-9349-3b142d254d6b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2699625930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2699625930
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.4209415900
Short name T33
Test name
Test status
Simulation time 394017499 ps
CPU time 4.87 seconds
Started Mar 23 04:00:36 PM PDT 24
Finished Mar 23 04:00:41 PM PDT 24
Peak memory 209440 kb
Host smart-89cfa262-bfff-46ba-a944-2b2895a21cb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209415900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.4209415900
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1434353269
Short name T263
Test name
Test status
Simulation time 7605853088 ps
CPU time 68.48 seconds
Started Mar 23 04:02:13 PM PDT 24
Finished Mar 23 04:03:22 PM PDT 24
Peak memory 216912 kb
Host smart-662c4f53-5247-481c-bae7-a4bc311c91c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434353269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1434353269
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.6785082
Short name T90
Test name
Test status
Simulation time 558047131 ps
CPU time 4.65 seconds
Started Mar 23 03:59:29 PM PDT 24
Finished Mar 23 03:59:35 PM PDT 24
Peak memory 220356 kb
Host smart-47071d28-c31e-4e4a-bc47-e3635bae95c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6785082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.6785082
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2425359500
Short name T238
Test name
Test status
Simulation time 10485334994 ps
CPU time 134.39 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:03:54 PM PDT 24
Peak memory 214916 kb
Host smart-00fba35e-39bc-4975-b629-6d624ca5ac8a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2425359500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2425359500
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2098114838
Short name T30
Test name
Test status
Simulation time 667252902 ps
CPU time 7.78 seconds
Started Mar 23 04:00:46 PM PDT 24
Finished Mar 23 04:00:54 PM PDT 24
Peak memory 214340 kb
Host smart-0e89daa9-1e29-477d-bad8-34019d7b6623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098114838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2098114838
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1839919813
Short name T94
Test name
Test status
Simulation time 924341478 ps
CPU time 7.36 seconds
Started Mar 23 04:01:48 PM PDT 24
Finished Mar 23 04:01:56 PM PDT 24
Peak memory 214328 kb
Host smart-1301984e-d965-4883-a261-5857bea2c029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839919813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1839919813
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.834725441
Short name T407
Test name
Test status
Simulation time 2133189985 ps
CPU time 57.53 seconds
Started Mar 23 04:00:35 PM PDT 24
Finished Mar 23 04:01:34 PM PDT 24
Peak memory 214368 kb
Host smart-db00504a-d7fa-4e93-8124-98c7a6853c15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=834725441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.834725441
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3516806948
Short name T168
Test name
Test status
Simulation time 81814988 ps
CPU time 3.3 seconds
Started Mar 23 03:59:47 PM PDT 24
Finished Mar 23 03:59:50 PM PDT 24
Peak memory 222616 kb
Host smart-68e22118-81eb-4f00-a471-260b3dc00194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516806948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3516806948
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3267737586
Short name T884
Test name
Test status
Simulation time 40902778 ps
CPU time 2.33 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:39 PM PDT 24
Peak memory 214660 kb
Host smart-fe93d556-c9dd-47d2-90be-b64469642419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267737586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3267737586
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2855536864
Short name T72
Test name
Test status
Simulation time 28894976415 ps
CPU time 173.34 seconds
Started Mar 23 03:59:59 PM PDT 24
Finished Mar 23 04:02:52 PM PDT 24
Peak memory 217216 kb
Host smart-a2c43521-6146-4418-bf39-03e9dd3ca882
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855536864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2855536864
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.4236056260
Short name T98
Test name
Test status
Simulation time 141553914 ps
CPU time 3.27 seconds
Started Mar 23 04:02:13 PM PDT 24
Finished Mar 23 04:02:17 PM PDT 24
Peak memory 222464 kb
Host smart-51afd5d4-2b93-4dfe-a58c-caacd2d8fc5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236056260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.4236056260
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2898306292
Short name T76
Test name
Test status
Simulation time 37743022 ps
CPU time 0.74 seconds
Started Mar 23 04:00:39 PM PDT 24
Finished Mar 23 04:00:40 PM PDT 24
Peak memory 205828 kb
Host smart-9c59662f-931f-4084-bae3-aafbb3c44e75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898306292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2898306292
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1963933595
Short name T331
Test name
Test status
Simulation time 64113790 ps
CPU time 4.12 seconds
Started Mar 23 04:00:23 PM PDT 24
Finished Mar 23 04:00:27 PM PDT 24
Peak memory 214648 kb
Host smart-41effbac-409e-4291-bd34-9ce89fa546c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1963933595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1963933595
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1182508853
Short name T150
Test name
Test status
Simulation time 1140100318 ps
CPU time 37.15 seconds
Started Mar 23 01:56:05 PM PDT 24
Finished Mar 23 01:56:43 PM PDT 24
Peak memory 213456 kb
Host smart-4e37d33e-d7d1-457e-b5e4-dc373f54cdbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182508853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1182508853
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1780351972
Short name T350
Test name
Test status
Simulation time 3697317796 ps
CPU time 26.38 seconds
Started Mar 23 04:00:52 PM PDT 24
Finished Mar 23 04:01:18 PM PDT 24
Peak memory 220088 kb
Host smart-fdf3fda3-cec2-4489-83c0-97bf2492a078
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780351972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1780351972
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1518115478
Short name T231
Test name
Test status
Simulation time 8808406025 ps
CPU time 116.12 seconds
Started Mar 23 04:00:51 PM PDT 24
Finished Mar 23 04:02:47 PM PDT 24
Peak memory 216836 kb
Host smart-33ae9223-6b4d-436a-b6c3-ecf3a1c04e53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518115478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1518115478
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3554158304
Short name T53
Test name
Test status
Simulation time 65636575 ps
CPU time 2.83 seconds
Started Mar 23 04:00:22 PM PDT 24
Finished Mar 23 04:00:25 PM PDT 24
Peak memory 211804 kb
Host smart-d1cc742e-e572-4442-9793-b5e3e24d5282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554158304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3554158304
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.226701145
Short name T268
Test name
Test status
Simulation time 52397671652 ps
CPU time 398.31 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:08:14 PM PDT 24
Peak memory 217484 kb
Host smart-12943ec0-d9b7-497e-9981-98e66d329fad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226701145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.226701145
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3662803951
Short name T186
Test name
Test status
Simulation time 207700295 ps
CPU time 5.17 seconds
Started Mar 23 04:02:11 PM PDT 24
Finished Mar 23 04:02:17 PM PDT 24
Peak memory 210196 kb
Host smart-706e06b8-32b6-414b-9747-6bd2642f796e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662803951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3662803951
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3464122203
Short name T170
Test name
Test status
Simulation time 337999058 ps
CPU time 15.95 seconds
Started Mar 23 04:02:12 PM PDT 24
Finished Mar 23 04:02:28 PM PDT 24
Peak memory 218232 kb
Host smart-1f333174-bd3e-4638-8daf-cd3524e6b062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464122203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3464122203
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2603189134
Short name T320
Test name
Test status
Simulation time 374169672 ps
CPU time 6 seconds
Started Mar 23 04:01:53 PM PDT 24
Finished Mar 23 04:01:59 PM PDT 24
Peak memory 214264 kb
Host smart-4cc87287-ca9e-40e6-9162-51dc19949e51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2603189134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2603189134
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1233120411
Short name T294
Test name
Test status
Simulation time 11785313754 ps
CPU time 64.86 seconds
Started Mar 23 04:02:12 PM PDT 24
Finished Mar 23 04:03:17 PM PDT 24
Peak memory 223064 kb
Host smart-d9c46092-1538-434f-93f2-a6b23bf3c8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233120411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1233120411
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1459735508
Short name T278
Test name
Test status
Simulation time 42644082 ps
CPU time 3.19 seconds
Started Mar 23 04:02:27 PM PDT 24
Finished Mar 23 04:02:31 PM PDT 24
Peak memory 215340 kb
Host smart-5f447e15-7011-4027-944f-995636dec22f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1459735508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1459735508
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3522741661
Short name T66
Test name
Test status
Simulation time 423872116 ps
CPU time 4.02 seconds
Started Mar 23 04:01:39 PM PDT 24
Finished Mar 23 04:01:43 PM PDT 24
Peak memory 215852 kb
Host smart-b9eeb5ca-e922-4c99-9c62-2bb360a269f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522741661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3522741661
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2262410408
Short name T384
Test name
Test status
Simulation time 65333655 ps
CPU time 3.7 seconds
Started Mar 23 04:00:25 PM PDT 24
Finished Mar 23 04:00:29 PM PDT 24
Peak memory 214344 kb
Host smart-d7932965-8ff0-4d21-b56d-11b256f2b0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262410408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2262410408
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1146805247
Short name T291
Test name
Test status
Simulation time 332319297 ps
CPU time 12.01 seconds
Started Mar 23 03:59:47 PM PDT 24
Finished Mar 23 03:59:59 PM PDT 24
Peak memory 210652 kb
Host smart-2671dd37-b8a9-40bb-878d-fa91ca4eadc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146805247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1146805247
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1004589801
Short name T22
Test name
Test status
Simulation time 133310273 ps
CPU time 5.07 seconds
Started Mar 23 04:01:35 PM PDT 24
Finished Mar 23 04:01:41 PM PDT 24
Peak memory 208248 kb
Host smart-429c1e5d-ce5f-46f8-ae7f-2a246711f835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004589801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1004589801
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.1423220508
Short name T271
Test name
Test status
Simulation time 833382815 ps
CPU time 32.27 seconds
Started Mar 23 04:02:27 PM PDT 24
Finished Mar 23 04:03:01 PM PDT 24
Peak memory 222504 kb
Host smart-ac22e964-85df-4871-8017-af7d94491e2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423220508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.1423220508
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1650677267
Short name T436
Test name
Test status
Simulation time 290260296 ps
CPU time 2.94 seconds
Started Mar 23 01:55:55 PM PDT 24
Finished Mar 23 01:55:58 PM PDT 24
Peak memory 213692 kb
Host smart-f135ab5f-3861-45ec-aff5-6ab9e7dad46c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650677267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1650677267
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.3302859902
Short name T124
Test name
Test status
Simulation time 377920416 ps
CPU time 6.51 seconds
Started Mar 23 01:56:31 PM PDT 24
Finished Mar 23 01:56:38 PM PDT 24
Peak memory 209024 kb
Host smart-ffb4f49d-eafe-4c0d-8307-247e8b0658be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302859902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.3302859902
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3169975692
Short name T20
Test name
Test status
Simulation time 76084598 ps
CPU time 2.91 seconds
Started Mar 23 04:00:26 PM PDT 24
Finished Mar 23 04:00:29 PM PDT 24
Peak memory 214724 kb
Host smart-5d516b3b-6531-400a-b051-49cdcef76475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169975692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3169975692
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2718971473
Short name T167
Test name
Test status
Simulation time 72705866 ps
CPU time 3.17 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:00:17 PM PDT 24
Peak memory 217876 kb
Host smart-6dac149d-ce68-4084-b66e-cf47369baf0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718971473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2718971473
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2198067551
Short name T352
Test name
Test status
Simulation time 6040496186 ps
CPU time 71.18 seconds
Started Mar 23 04:00:25 PM PDT 24
Finished Mar 23 04:01:37 PM PDT 24
Peak memory 221616 kb
Host smart-1bf7cb92-49d9-4294-8a1a-fcb4c8a95340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198067551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2198067551
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3548311857
Short name T195
Test name
Test status
Simulation time 641402642 ps
CPU time 9.5 seconds
Started Mar 23 04:01:26 PM PDT 24
Finished Mar 23 04:01:36 PM PDT 24
Peak memory 208784 kb
Host smart-1bf9442a-4c8f-4b55-9fbc-0b70b2e4d04e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548311857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3548311857
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.440530151
Short name T357
Test name
Test status
Simulation time 238755856 ps
CPU time 5.99 seconds
Started Mar 23 04:01:47 PM PDT 24
Finished Mar 23 04:01:53 PM PDT 24
Peak memory 214360 kb
Host smart-6171d245-e07f-42dc-8034-d1ea88460822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440530151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.440530151
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1746430267
Short name T370
Test name
Test status
Simulation time 18341055598 ps
CPU time 128.59 seconds
Started Mar 23 04:01:53 PM PDT 24
Finished Mar 23 04:04:01 PM PDT 24
Peak memory 222592 kb
Host smart-7323b55d-fa13-482f-8a05-6eb60af088ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746430267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1746430267
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2639391921
Short name T233
Test name
Test status
Simulation time 279448877 ps
CPU time 3.5 seconds
Started Mar 23 04:00:14 PM PDT 24
Finished Mar 23 04:00:18 PM PDT 24
Peak memory 209148 kb
Host smart-ab60792f-b573-487a-9521-258c938d4a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639391921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2639391921
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.4084716234
Short name T413
Test name
Test status
Simulation time 40705456433 ps
CPU time 159.82 seconds
Started Mar 23 04:00:10 PM PDT 24
Finished Mar 23 04:02:49 PM PDT 24
Peak memory 220980 kb
Host smart-0360a0b4-86aa-4b1e-97cd-5288ebd53138
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4084716234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.4084716234
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.4109353783
Short name T610
Test name
Test status
Simulation time 170777208 ps
CPU time 1.77 seconds
Started Mar 23 03:59:39 PM PDT 24
Finished Mar 23 03:59:42 PM PDT 24
Peak memory 209352 kb
Host smart-2499830d-38a3-42b0-bd67-33cdd932d63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109353783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.4109353783
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1111302330
Short name T86
Test name
Test status
Simulation time 161674864 ps
CPU time 2.98 seconds
Started Mar 23 04:02:31 PM PDT 24
Finished Mar 23 04:02:35 PM PDT 24
Peak memory 208728 kb
Host smart-9c11fa54-068a-45aa-afd5-430148a85a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111302330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1111302330
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3996998931
Short name T169
Test name
Test status
Simulation time 808932564 ps
CPU time 4.62 seconds
Started Mar 23 04:00:34 PM PDT 24
Finished Mar 23 04:00:40 PM PDT 24
Peak memory 222656 kb
Host smart-5ac94198-62fd-4ba2-9351-e42737ad5968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996998931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3996998931
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.410274974
Short name T56
Test name
Test status
Simulation time 438840578 ps
CPU time 4.11 seconds
Started Mar 23 04:00:26 PM PDT 24
Finished Mar 23 04:00:30 PM PDT 24
Peak memory 210016 kb
Host smart-e54d2eea-ecb5-40aa-baa7-963299fb0897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410274974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.410274974
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2263200465
Short name T351
Test name
Test status
Simulation time 1020853698 ps
CPU time 8.74 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:58 PM PDT 24
Peak memory 222460 kb
Host smart-c0537ef2-891e-446a-815e-362792d6e67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263200465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2263200465
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.4206194077
Short name T34
Test name
Test status
Simulation time 677784054 ps
CPU time 15.18 seconds
Started Mar 23 04:01:04 PM PDT 24
Finished Mar 23 04:01:20 PM PDT 24
Peak memory 210000 kb
Host smart-954b553d-9cd0-406e-acfb-97fccdbb3fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206194077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.4206194077
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.276682874
Short name T385
Test name
Test status
Simulation time 11551994311 ps
CPU time 76.04 seconds
Started Mar 23 04:01:21 PM PDT 24
Finished Mar 23 04:02:37 PM PDT 24
Peak memory 220104 kb
Host smart-7f99083a-2052-4b9d-ad28-2762923887eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276682874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.276682874
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.249391100
Short name T293
Test name
Test status
Simulation time 185061643 ps
CPU time 8.14 seconds
Started Mar 23 04:01:38 PM PDT 24
Finished Mar 23 04:01:46 PM PDT 24
Peak memory 214228 kb
Host smart-6f08c57d-4338-4efb-8929-05c966886a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249391100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.249391100
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2597992128
Short name T332
Test name
Test status
Simulation time 3705082086 ps
CPU time 6.15 seconds
Started Mar 23 04:01:59 PM PDT 24
Finished Mar 23 04:02:05 PM PDT 24
Peak memory 208576 kb
Host smart-90f7c17d-fa43-4479-9b53-fb313afe207c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597992128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2597992128
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2770474063
Short name T199
Test name
Test status
Simulation time 205841544 ps
CPU time 4.62 seconds
Started Mar 23 04:02:26 PM PDT 24
Finished Mar 23 04:02:32 PM PDT 24
Peak memory 209940 kb
Host smart-c95f7f7d-da7c-424f-a0a8-d44b09a7fa2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770474063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2770474063
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.593765088
Short name T297
Test name
Test status
Simulation time 127267731 ps
CPU time 4.33 seconds
Started Mar 23 04:00:14 PM PDT 24
Finished Mar 23 04:00:18 PM PDT 24
Peak memory 221416 kb
Host smart-0efe7748-3adc-4195-8c45-b4dfab29b778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593765088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.593765088
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.451521200
Short name T154
Test name
Test status
Simulation time 881183724 ps
CPU time 9.73 seconds
Started Mar 23 01:55:56 PM PDT 24
Finished Mar 23 01:56:06 PM PDT 24
Peak memory 213528 kb
Host smart-2465fb76-ff9a-4198-b0fd-2d9c24e83e0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451521200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
451521200
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1453079973
Short name T152
Test name
Test status
Simulation time 494859427 ps
CPU time 9.65 seconds
Started Mar 23 01:56:30 PM PDT 24
Finished Mar 23 01:56:40 PM PDT 24
Peak memory 220596 kb
Host smart-9b2a3acd-6d89-4599-afab-d16bb8ceff9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453079973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1453079973
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1389668344
Short name T129
Test name
Test status
Simulation time 2252004253 ps
CPU time 10.3 seconds
Started Mar 23 01:56:47 PM PDT 24
Finished Mar 23 01:56:57 PM PDT 24
Peak memory 213536 kb
Host smart-bc8b65d8-eb60-4097-847f-80fb25e8f2b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389668344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1389668344
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.571245881
Short name T162
Test name
Test status
Simulation time 331226029 ps
CPU time 3.49 seconds
Started Mar 23 04:00:43 PM PDT 24
Finished Mar 23 04:00:47 PM PDT 24
Peak memory 210464 kb
Host smart-2f7e4aad-e780-44b7-9e34-bfc7e730ff46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571245881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.571245881
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1474525756
Short name T153
Test name
Test status
Simulation time 308071272 ps
CPU time 1.74 seconds
Started Mar 23 04:00:47 PM PDT 24
Finished Mar 23 04:00:50 PM PDT 24
Peak memory 210032 kb
Host smart-a709a294-bd94-417a-80d0-e057502bec68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474525756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1474525756
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1878315069
Short name T159
Test name
Test status
Simulation time 157922065 ps
CPU time 2.34 seconds
Started Mar 23 04:01:08 PM PDT 24
Finished Mar 23 04:01:10 PM PDT 24
Peak memory 210376 kb
Host smart-ee2f32c4-3d22-4d9c-bbd9-7db0963d39b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878315069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1878315069
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.55786741
Short name T166
Test name
Test status
Simulation time 657925266 ps
CPU time 12.5 seconds
Started Mar 23 04:00:53 PM PDT 24
Finished Mar 23 04:01:06 PM PDT 24
Peak memory 216160 kb
Host smart-27bfe071-e05c-4ccb-aae5-6e4023f8a575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55786741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.55786741
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1739367032
Short name T211
Test name
Test status
Simulation time 241206441 ps
CPU time 2.58 seconds
Started Mar 23 03:59:24 PM PDT 24
Finished Mar 23 03:59:27 PM PDT 24
Peak memory 209396 kb
Host smart-5247a2ac-dc33-4d54-ae6e-0aecbe9be150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739367032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1739367032
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.4018298011
Short name T304
Test name
Test status
Simulation time 90004088 ps
CPU time 2.45 seconds
Started Mar 23 03:59:28 PM PDT 24
Finished Mar 23 03:59:31 PM PDT 24
Peak memory 217864 kb
Host smart-9578f680-1c91-4052-b453-ac9d6c130e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018298011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.4018298011
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2725309988
Short name T126
Test name
Test status
Simulation time 854835658 ps
CPU time 4.61 seconds
Started Mar 23 03:59:25 PM PDT 24
Finished Mar 23 03:59:30 PM PDT 24
Peak memory 208168 kb
Host smart-3670e714-a5ab-4e57-b9b8-9216d9bfa9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725309988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2725309988
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3907967810
Short name T296
Test name
Test status
Simulation time 482755704 ps
CPU time 8.99 seconds
Started Mar 23 04:00:22 PM PDT 24
Finished Mar 23 04:00:32 PM PDT 24
Peak memory 214208 kb
Host smart-9f4e01bf-43fe-4710-9acc-a1418bd9362d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907967810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3907967810
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.320063023
Short name T2
Test name
Test status
Simulation time 544011099 ps
CPU time 12.06 seconds
Started Mar 23 04:00:22 PM PDT 24
Finished Mar 23 04:00:34 PM PDT 24
Peak memory 210404 kb
Host smart-17f30b62-8b0d-4356-95ad-3775f5df0ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320063023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.320063023
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1442917797
Short name T325
Test name
Test status
Simulation time 5512359726 ps
CPU time 34.35 seconds
Started Mar 23 04:00:22 PM PDT 24
Finished Mar 23 04:00:57 PM PDT 24
Peak memory 230736 kb
Host smart-90868892-42d0-46a6-8545-c473a7e06030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442917797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1442917797
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_random.832361847
Short name T365
Test name
Test status
Simulation time 112889801 ps
CPU time 4.95 seconds
Started Mar 23 04:00:33 PM PDT 24
Finished Mar 23 04:00:39 PM PDT 24
Peak memory 218248 kb
Host smart-cf9dd2ab-2639-4a34-ab97-363c8f9b340f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832361847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.832361847
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3750386138
Short name T232
Test name
Test status
Simulation time 64805749 ps
CPU time 3.36 seconds
Started Mar 23 04:00:37 PM PDT 24
Finished Mar 23 04:00:41 PM PDT 24
Peak memory 209040 kb
Host smart-07db30c0-835a-4b2a-a7f1-dae777ee6a38
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750386138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3750386138
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1086407502
Short name T850
Test name
Test status
Simulation time 153083724 ps
CPU time 3.03 seconds
Started Mar 23 04:00:45 PM PDT 24
Finished Mar 23 04:00:49 PM PDT 24
Peak memory 208988 kb
Host smart-53082df0-8c78-445c-99ce-f7c8a9d400dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086407502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1086407502
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1286421873
Short name T1026
Test name
Test status
Simulation time 91561243 ps
CPU time 4.44 seconds
Started Mar 23 03:59:44 PM PDT 24
Finished Mar 23 03:59:50 PM PDT 24
Peak memory 208992 kb
Host smart-ad5b3ca6-2418-4556-9e40-6bd6f746dab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286421873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1286421873
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2205282947
Short name T205
Test name
Test status
Simulation time 188864966 ps
CPU time 4 seconds
Started Mar 23 04:00:52 PM PDT 24
Finished Mar 23 04:00:56 PM PDT 24
Peak memory 220176 kb
Host smart-b7142090-e079-4583-8d4a-f60a245525b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205282947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2205282947
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3629395307
Short name T362
Test name
Test status
Simulation time 216592897 ps
CPU time 4.03 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:52 PM PDT 24
Peak memory 206668 kb
Host smart-578cfe2b-a074-42ae-8cf2-1e490befda4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629395307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3629395307
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.180569439
Short name T37
Test name
Test status
Simulation time 784315804 ps
CPU time 6.29 seconds
Started Mar 23 04:01:04 PM PDT 24
Finished Mar 23 04:01:11 PM PDT 24
Peak memory 220344 kb
Host smart-81d1f274-b073-409c-b082-3c0861677b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180569439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.180569439
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2835991338
Short name T366
Test name
Test status
Simulation time 224753913 ps
CPU time 13.12 seconds
Started Mar 23 04:01:20 PM PDT 24
Finished Mar 23 04:01:33 PM PDT 24
Peak memory 214348 kb
Host smart-d042bac4-4ce1-4c21-8ca5-db4d0225a651
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2835991338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2835991338
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2259478373
Short name T202
Test name
Test status
Simulation time 222181809 ps
CPU time 2.53 seconds
Started Mar 23 04:01:20 PM PDT 24
Finished Mar 23 04:01:23 PM PDT 24
Peak memory 220872 kb
Host smart-219caddc-90d0-4c64-a9cd-8312373b6f2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259478373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2259478373
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1060179774
Short name T1046
Test name
Test status
Simulation time 1065823163 ps
CPU time 15.17 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:38 PM PDT 24
Peak memory 208968 kb
Host smart-877036c5-e3c8-41dc-a2f7-ae9eded83adb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060179774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1060179774
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1914543837
Short name T208
Test name
Test status
Simulation time 87830803 ps
CPU time 3.03 seconds
Started Mar 23 04:01:35 PM PDT 24
Finished Mar 23 04:01:38 PM PDT 24
Peak memory 209016 kb
Host smart-9b33af4e-6c71-42b3-8e94-72f27b3e08c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914543837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1914543837
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.908049391
Short name T418
Test name
Test status
Simulation time 53747278 ps
CPU time 3.96 seconds
Started Mar 23 03:59:45 PM PDT 24
Finished Mar 23 03:59:50 PM PDT 24
Peak memory 214660 kb
Host smart-10152acb-5805-4233-9d0f-3e086b0f8190
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=908049391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.908049391
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2726862015
Short name T209
Test name
Test status
Simulation time 1420281564 ps
CPU time 6.28 seconds
Started Mar 23 04:01:39 PM PDT 24
Finished Mar 23 04:01:46 PM PDT 24
Peak memory 214696 kb
Host smart-f5e6178d-fe93-402c-92ca-9a4500ac4985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726862015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2726862015
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1313036298
Short name T276
Test name
Test status
Simulation time 73272402 ps
CPU time 4 seconds
Started Mar 23 04:01:48 PM PDT 24
Finished Mar 23 04:01:52 PM PDT 24
Peak memory 210124 kb
Host smart-0e3cf945-f8e6-40d5-80c8-a8a0057d0043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313036298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1313036298
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2565378634
Short name T265
Test name
Test status
Simulation time 1618077048 ps
CPU time 7.62 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:56 PM PDT 24
Peak memory 214252 kb
Host smart-48fb0d18-0d59-4686-9ba3-42e7133265d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565378634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2565378634
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2597084293
Short name T307
Test name
Test status
Simulation time 10715771546 ps
CPU time 45.67 seconds
Started Mar 23 04:01:56 PM PDT 24
Finished Mar 23 04:02:41 PM PDT 24
Peak memory 216480 kb
Host smart-75d48d4f-17a0-441f-8e61-241c296814ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597084293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2597084293
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1354253183
Short name T248
Test name
Test status
Simulation time 40256747 ps
CPU time 2.49 seconds
Started Mar 23 04:02:04 PM PDT 24
Finished Mar 23 04:02:07 PM PDT 24
Peak memory 206772 kb
Host smart-b017813a-5d23-411a-819e-0a170ac6eecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354253183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1354253183
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3129843311
Short name T453
Test name
Test status
Simulation time 198685928 ps
CPU time 4.06 seconds
Started Mar 23 01:55:57 PM PDT 24
Finished Mar 23 01:56:01 PM PDT 24
Peak memory 205276 kb
Host smart-ba2c5676-ec9b-4e30-b2a1-7c13891c511e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129843311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
129843311
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2589184457
Short name T135
Test name
Test status
Simulation time 536251807 ps
CPU time 8.6 seconds
Started Mar 23 01:55:59 PM PDT 24
Finished Mar 23 01:56:08 PM PDT 24
Peak memory 205180 kb
Host smart-15ba9ea3-27c6-4509-9292-d714e29b5b0c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589184457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
589184457
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.370877447
Short name T508
Test name
Test status
Simulation time 164024578 ps
CPU time 0.97 seconds
Started Mar 23 01:55:56 PM PDT 24
Finished Mar 23 01:55:58 PM PDT 24
Peak memory 205048 kb
Host smart-c6a17dbf-2588-43f8-940e-504c70c5bf9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370877447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.370877447
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2274488906
Short name T105
Test name
Test status
Simulation time 20971769 ps
CPU time 1.66 seconds
Started Mar 23 01:55:55 PM PDT 24
Finished Mar 23 01:55:57 PM PDT 24
Peak memory 213692 kb
Host smart-cbc905a7-2290-417c-88c2-6cd2f400251d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274488906 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2274488906
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3980976284
Short name T480
Test name
Test status
Simulation time 255648418 ps
CPU time 1.61 seconds
Started Mar 23 01:55:57 PM PDT 24
Finished Mar 23 01:55:58 PM PDT 24
Peak memory 205180 kb
Host smart-37db137a-f3c8-4f98-88e1-98442297ba56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980976284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3980976284
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2751116312
Short name T543
Test name
Test status
Simulation time 36278921 ps
CPU time 0.83 seconds
Started Mar 23 01:55:59 PM PDT 24
Finished Mar 23 01:56:00 PM PDT 24
Peak memory 205188 kb
Host smart-40d9c19c-2589-40f9-811f-ec53e0ba820f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751116312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2751116312
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3190361477
Short name T498
Test name
Test status
Simulation time 245636867 ps
CPU time 2.53 seconds
Started Mar 23 01:55:55 PM PDT 24
Finished Mar 23 01:55:58 PM PDT 24
Peak memory 213472 kb
Host smart-0aa43a14-67bd-46a6-94c8-d22e7e982527
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190361477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3190361477
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1986904065
Short name T526
Test name
Test status
Simulation time 101628104 ps
CPU time 3.21 seconds
Started Mar 23 01:55:47 PM PDT 24
Finished Mar 23 01:55:51 PM PDT 24
Peak memory 213788 kb
Host smart-e29bef0c-15b6-4779-bda9-f979e24e5579
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986904065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1986904065
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.930112886
Short name T472
Test name
Test status
Simulation time 2014603081 ps
CPU time 8.61 seconds
Started Mar 23 01:55:47 PM PDT 24
Finished Mar 23 01:55:56 PM PDT 24
Peak memory 213784 kb
Host smart-d858dd84-e7ed-4893-b352-42b22ddf1900
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930112886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.930112886
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2184792520
Short name T559
Test name
Test status
Simulation time 112469768 ps
CPU time 2.06 seconds
Started Mar 23 01:55:55 PM PDT 24
Finished Mar 23 01:55:58 PM PDT 24
Peak memory 213520 kb
Host smart-98ffd1bd-63ea-49ce-9257-57910802bdad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184792520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2184792520
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.163615962
Short name T175
Test name
Test status
Simulation time 494665086 ps
CPU time 8.04 seconds
Started Mar 23 01:55:54 PM PDT 24
Finished Mar 23 01:56:03 PM PDT 24
Peak memory 205236 kb
Host smart-816b96d3-bf08-4e34-ba83-95522f3e4d12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163615962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.163615962
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1519312572
Short name T141
Test name
Test status
Simulation time 30190645 ps
CPU time 1.43 seconds
Started Mar 23 01:55:56 PM PDT 24
Finished Mar 23 01:55:57 PM PDT 24
Peak memory 205260 kb
Host smart-4683af5f-02c7-4979-8a74-e1d5b4f4d826
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519312572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
519312572
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1097454172
Short name T467
Test name
Test status
Simulation time 20879676 ps
CPU time 1.43 seconds
Started Mar 23 01:55:54 PM PDT 24
Finished Mar 23 01:55:56 PM PDT 24
Peak memory 205484 kb
Host smart-d577caf7-b85c-48cc-b3a3-cff4a4080f1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097454172 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1097454172
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.273557704
Short name T134
Test name
Test status
Simulation time 13439543 ps
CPU time 0.98 seconds
Started Mar 23 01:55:59 PM PDT 24
Finished Mar 23 01:56:00 PM PDT 24
Peak memory 205180 kb
Host smart-7b74d5f6-f30e-4776-812f-56588d1c3835
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273557704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.273557704
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1675972043
Short name T461
Test name
Test status
Simulation time 27858036 ps
CPU time 0.74 seconds
Started Mar 23 01:55:58 PM PDT 24
Finished Mar 23 01:55:59 PM PDT 24
Peak memory 205108 kb
Host smart-b6c82b2f-c209-499e-8130-e5d50429c81c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675972043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1675972043
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3771492333
Short name T138
Test name
Test status
Simulation time 76640104 ps
CPU time 1.74 seconds
Started Mar 23 01:55:56 PM PDT 24
Finished Mar 23 01:55:58 PM PDT 24
Peak memory 205236 kb
Host smart-73320761-534e-4bca-86b3-7fb6ca41a6ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771492333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3771492333
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.865809228
Short name T180
Test name
Test status
Simulation time 161690918 ps
CPU time 3.05 seconds
Started Mar 23 01:56:02 PM PDT 24
Finished Mar 23 01:56:06 PM PDT 24
Peak memory 213816 kb
Host smart-68cc75c1-3c8e-450a-a265-bf5375e0ac4c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865809228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.865809228
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3805000184
Short name T112
Test name
Test status
Simulation time 204428872 ps
CPU time 10.25 seconds
Started Mar 23 01:55:55 PM PDT 24
Finished Mar 23 01:56:06 PM PDT 24
Peak memory 213724 kb
Host smart-f2515398-d91a-49d8-935f-f9cc14bbf969
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805000184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3805000184
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3454207408
Short name T463
Test name
Test status
Simulation time 24476472 ps
CPU time 1.42 seconds
Started Mar 23 01:56:29 PM PDT 24
Finished Mar 23 01:56:31 PM PDT 24
Peak memory 213524 kb
Host smart-b0bdc703-bc36-4595-b5f2-a099b4be5986
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454207408 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3454207408
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2356424866
Short name T440
Test name
Test status
Simulation time 34747747 ps
CPU time 0.88 seconds
Started Mar 23 01:56:25 PM PDT 24
Finished Mar 23 01:56:26 PM PDT 24
Peak memory 205148 kb
Host smart-9f072d5e-7177-41e5-98c7-4826c23c796e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356424866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2356424866
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2009323665
Short name T488
Test name
Test status
Simulation time 88227685 ps
CPU time 1.53 seconds
Started Mar 23 01:56:27 PM PDT 24
Finished Mar 23 01:56:28 PM PDT 24
Peak memory 205264 kb
Host smart-b8f7ad2c-8904-49c0-aac4-673ffaa25ac5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009323665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2009323665
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.181680009
Short name T473
Test name
Test status
Simulation time 402251155 ps
CPU time 3.57 seconds
Started Mar 23 01:56:27 PM PDT 24
Finished Mar 23 01:56:30 PM PDT 24
Peak memory 213504 kb
Host smart-eee4c3e8-0008-42b4-acbc-e447fa7feb2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181680009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.181680009
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.4072227454
Short name T173
Test name
Test status
Simulation time 203412277 ps
CPU time 1.13 seconds
Started Mar 23 01:56:30 PM PDT 24
Finished Mar 23 01:56:31 PM PDT 24
Peak memory 213620 kb
Host smart-84d36456-9896-463a-bb02-81bbbca18811
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072227454 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.4072227454
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2115524147
Short name T558
Test name
Test status
Simulation time 113590814 ps
CPU time 0.89 seconds
Started Mar 23 01:56:27 PM PDT 24
Finished Mar 23 01:56:28 PM PDT 24
Peak memory 205212 kb
Host smart-5fd2020a-a488-4881-bf6c-7f533080e5fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115524147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2115524147
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1566902589
Short name T470
Test name
Test status
Simulation time 15833588 ps
CPU time 0.75 seconds
Started Mar 23 01:56:28 PM PDT 24
Finished Mar 23 01:56:28 PM PDT 24
Peak memory 205204 kb
Host smart-9e39ebd9-261d-4710-b78c-31637ea9a0a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566902589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1566902589
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.360354675
Short name T144
Test name
Test status
Simulation time 81038807 ps
CPU time 1.66 seconds
Started Mar 23 01:56:32 PM PDT 24
Finished Mar 23 01:56:34 PM PDT 24
Peak memory 205332 kb
Host smart-def8f2a2-0548-4450-abfb-3dfc963cd99b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360354675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.360354675
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.23842225
Short name T113
Test name
Test status
Simulation time 291127120 ps
CPU time 2.94 seconds
Started Mar 23 01:56:31 PM PDT 24
Finished Mar 23 01:56:34 PM PDT 24
Peak memory 213856 kb
Host smart-891a264b-58d2-41bd-b8aa-e153f7e9e198
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23842225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow
_reg_errors.23842225
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.546776383
Short name T529
Test name
Test status
Simulation time 258408350 ps
CPU time 5.16 seconds
Started Mar 23 01:56:30 PM PDT 24
Finished Mar 23 01:56:35 PM PDT 24
Peak memory 213696 kb
Host smart-f37949e3-7499-4cdc-aee1-7b588aa226bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546776383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.546776383
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.772126595
Short name T483
Test name
Test status
Simulation time 148884101 ps
CPU time 1.95 seconds
Started Mar 23 01:56:27 PM PDT 24
Finished Mar 23 01:56:29 PM PDT 24
Peak memory 213648 kb
Host smart-2578bd70-aa37-44c2-b912-30ba24e4a7fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772126595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.772126595
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2233631190
Short name T155
Test name
Test status
Simulation time 289286049 ps
CPU time 4.37 seconds
Started Mar 23 01:56:25 PM PDT 24
Finished Mar 23 01:56:30 PM PDT 24
Peak memory 208832 kb
Host smart-ac6c5487-6bcb-4f41-bb36-c319c1ebad9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233631190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2233631190
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1983076922
Short name T172
Test name
Test status
Simulation time 305471500 ps
CPU time 1.21 seconds
Started Mar 23 01:56:25 PM PDT 24
Finished Mar 23 01:56:27 PM PDT 24
Peak memory 205352 kb
Host smart-0f02a3c9-052e-44c4-aad4-ae667ce526ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983076922 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1983076922
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.4249546888
Short name T466
Test name
Test status
Simulation time 22159790 ps
CPU time 1.44 seconds
Started Mar 23 01:56:27 PM PDT 24
Finished Mar 23 01:56:29 PM PDT 24
Peak memory 205316 kb
Host smart-d0f91dd9-992e-4b17-a8a1-0a48d684985b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249546888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.4249546888
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3907604369
Short name T528
Test name
Test status
Simulation time 59183928 ps
CPU time 0.88 seconds
Started Mar 23 01:56:27 PM PDT 24
Finished Mar 23 01:56:28 PM PDT 24
Peak memory 205200 kb
Host smart-dc1defd0-b165-4dac-889f-8fbea800c93f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907604369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3907604369
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2684610208
Short name T540
Test name
Test status
Simulation time 44021693 ps
CPU time 1.4 seconds
Started Mar 23 01:56:30 PM PDT 24
Finished Mar 23 01:56:32 PM PDT 24
Peak memory 205380 kb
Host smart-0882ecbb-ebf5-4470-9b1d-f2d9d358b1f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684610208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2684610208
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.935537045
Short name T530
Test name
Test status
Simulation time 149272838 ps
CPU time 3.73 seconds
Started Mar 23 01:56:30 PM PDT 24
Finished Mar 23 01:56:34 PM PDT 24
Peak memory 213776 kb
Host smart-079574bc-fd4b-4eae-89ca-09089bc33bf9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935537045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.935537045
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3407000876
Short name T449
Test name
Test status
Simulation time 125450577 ps
CPU time 4.85 seconds
Started Mar 23 01:56:26 PM PDT 24
Finished Mar 23 01:56:31 PM PDT 24
Peak memory 213752 kb
Host smart-9440a3fd-0804-48f1-9f14-016f2791dc95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407000876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3407000876
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.4232723038
Short name T119
Test name
Test status
Simulation time 568197404 ps
CPU time 2.73 seconds
Started Mar 23 01:56:25 PM PDT 24
Finished Mar 23 01:56:28 PM PDT 24
Peak memory 213596 kb
Host smart-74f4ab5d-96d4-4cf9-ac0e-3702bf26d3a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232723038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.4232723038
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3185139218
Short name T118
Test name
Test status
Simulation time 28460659 ps
CPU time 1.94 seconds
Started Mar 23 01:56:31 PM PDT 24
Finished Mar 23 01:56:33 PM PDT 24
Peak memory 213652 kb
Host smart-5d47cffc-7ff7-4190-aa03-e4179495c04b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185139218 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3185139218
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.440048224
Short name T522
Test name
Test status
Simulation time 59745459 ps
CPU time 1.11 seconds
Started Mar 23 01:56:27 PM PDT 24
Finished Mar 23 01:56:29 PM PDT 24
Peak memory 205292 kb
Host smart-0854ee7b-7a08-4806-9157-9a5b7c1b4905
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440048224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.440048224
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2573857298
Short name T493
Test name
Test status
Simulation time 8582461 ps
CPU time 0.8 seconds
Started Mar 23 01:56:27 PM PDT 24
Finished Mar 23 01:56:28 PM PDT 24
Peak memory 205088 kb
Host smart-aefe9b27-ca21-4afe-a07d-218a5535254f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573857298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2573857298
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4098123485
Short name T469
Test name
Test status
Simulation time 121827070 ps
CPU time 1.71 seconds
Started Mar 23 01:56:28 PM PDT 24
Finished Mar 23 01:56:30 PM PDT 24
Peak memory 205336 kb
Host smart-a290ea79-3f61-434f-a637-64ca5fc17ce7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098123485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.4098123485
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4186107046
Short name T489
Test name
Test status
Simulation time 609438656 ps
CPU time 2.68 seconds
Started Mar 23 01:56:30 PM PDT 24
Finished Mar 23 01:56:33 PM PDT 24
Peak memory 213668 kb
Host smart-bdff9a2a-356f-4b03-824c-9417965b50dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186107046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.4186107046
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3482638029
Short name T562
Test name
Test status
Simulation time 421462086 ps
CPU time 6 seconds
Started Mar 23 01:56:30 PM PDT 24
Finished Mar 23 01:56:36 PM PDT 24
Peak memory 213780 kb
Host smart-c3520356-780e-43e0-bdf6-742b8a776e62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482638029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3482638029
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.751027941
Short name T117
Test name
Test status
Simulation time 276073231 ps
CPU time 3.87 seconds
Started Mar 23 01:56:28 PM PDT 24
Finished Mar 23 01:56:32 PM PDT 24
Peak memory 213528 kb
Host smart-354ff5f1-722f-4789-b0d4-1384947b93a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751027941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.751027941
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3023051847
Short name T147
Test name
Test status
Simulation time 110744465 ps
CPU time 4.74 seconds
Started Mar 23 01:56:31 PM PDT 24
Finished Mar 23 01:56:36 PM PDT 24
Peak memory 208628 kb
Host smart-7d5de3a8-ea63-4953-b57c-9fe0e421d6f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023051847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3023051847
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.648435513
Short name T439
Test name
Test status
Simulation time 105296542 ps
CPU time 1.98 seconds
Started Mar 23 01:56:40 PM PDT 24
Finished Mar 23 01:56:42 PM PDT 24
Peak memory 213516 kb
Host smart-9078c53c-93fb-4d95-96c2-87a07b25c4ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648435513 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.648435513
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2485768105
Short name T560
Test name
Test status
Simulation time 12039950 ps
CPU time 1.01 seconds
Started Mar 23 01:56:35 PM PDT 24
Finished Mar 23 01:56:36 PM PDT 24
Peak memory 205100 kb
Host smart-5e25df17-8813-4fc1-a5e6-79efcb020584
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485768105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2485768105
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.665879845
Short name T537
Test name
Test status
Simulation time 12701163 ps
CPU time 0.74 seconds
Started Mar 23 01:56:37 PM PDT 24
Finished Mar 23 01:56:38 PM PDT 24
Peak memory 205120 kb
Host smart-97e0c395-793b-43a5-bf39-150d1d3f2d34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665879845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.665879845
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.778843694
Short name T474
Test name
Test status
Simulation time 98212685 ps
CPU time 1.54 seconds
Started Mar 23 01:56:37 PM PDT 24
Finished Mar 23 01:56:39 PM PDT 24
Peak memory 205324 kb
Host smart-7c2e6d15-132d-43ef-8f78-76e78630278d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778843694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.778843694
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1315623257
Short name T111
Test name
Test status
Simulation time 91292897 ps
CPU time 3.24 seconds
Started Mar 23 01:56:37 PM PDT 24
Finished Mar 23 01:56:40 PM PDT 24
Peak memory 213752 kb
Host smart-5b97f9b5-16ef-4e89-b1fd-1bae5a16cab8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315623257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1315623257
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1925993538
Short name T443
Test name
Test status
Simulation time 121841990 ps
CPU time 4.7 seconds
Started Mar 23 01:56:37 PM PDT 24
Finished Mar 23 01:56:41 PM PDT 24
Peak memory 213800 kb
Host smart-5e66783a-eee8-4ae4-bcea-312a277d3683
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925993538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1925993538
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.319924108
Short name T438
Test name
Test status
Simulation time 29990850 ps
CPU time 2.18 seconds
Started Mar 23 01:56:36 PM PDT 24
Finished Mar 23 01:56:38 PM PDT 24
Peak memory 213584 kb
Host smart-a85c58f7-bcf2-46c3-bd60-8c1020eff547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319924108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.319924108
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1312377752
Short name T490
Test name
Test status
Simulation time 83397367 ps
CPU time 1.43 seconds
Started Mar 23 01:56:41 PM PDT 24
Finished Mar 23 01:56:42 PM PDT 24
Peak memory 205032 kb
Host smart-0eadd319-dfc7-454c-a35d-510b525dc31b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312377752 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1312377752
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.95770763
Short name T437
Test name
Test status
Simulation time 21551160 ps
CPU time 1.41 seconds
Started Mar 23 01:56:38 PM PDT 24
Finished Mar 23 01:56:40 PM PDT 24
Peak memory 205244 kb
Host smart-1dc87deb-5eb2-43ef-b1f6-e8e95750d65c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95770763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.95770763
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.88894371
Short name T532
Test name
Test status
Simulation time 14168269 ps
CPU time 0.72 seconds
Started Mar 23 01:56:36 PM PDT 24
Finished Mar 23 01:56:37 PM PDT 24
Peak memory 205104 kb
Host smart-00dc1728-b88a-4122-baab-9e80bea6cbe8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88894371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.88894371
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.600921496
Short name T142
Test name
Test status
Simulation time 35445845 ps
CPU time 1.97 seconds
Started Mar 23 01:56:38 PM PDT 24
Finished Mar 23 01:56:40 PM PDT 24
Peak memory 205228 kb
Host smart-f4a3c238-17a5-4921-8c37-88ecefb98557
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600921496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.600921496
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1094201008
Short name T492
Test name
Test status
Simulation time 578187985 ps
CPU time 6.5 seconds
Started Mar 23 01:56:36 PM PDT 24
Finished Mar 23 01:56:43 PM PDT 24
Peak memory 213760 kb
Host smart-8e827495-8636-4d9b-b0d1-e8c6992891ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094201008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1094201008
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3281152342
Short name T551
Test name
Test status
Simulation time 1205810146 ps
CPU time 10.25 seconds
Started Mar 23 01:56:41 PM PDT 24
Finished Mar 23 01:56:51 PM PDT 24
Peak memory 213752 kb
Host smart-77f33617-b1ae-4483-886d-96f7648f4078
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281152342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3281152342
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2454962091
Short name T556
Test name
Test status
Simulation time 1221811769 ps
CPU time 4.09 seconds
Started Mar 23 01:56:35 PM PDT 24
Finished Mar 23 01:56:40 PM PDT 24
Peak memory 215908 kb
Host smart-46e2e46d-3766-4f03-9879-f2cd5287f49c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454962091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2454962091
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.9678584
Short name T444
Test name
Test status
Simulation time 45865100 ps
CPU time 1.17 seconds
Started Mar 23 01:56:52 PM PDT 24
Finished Mar 23 01:56:54 PM PDT 24
Peak memory 213564 kb
Host smart-e04f0ddf-11d4-4e36-8542-e54f30ce6265
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9678584 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.9678584
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.306569284
Short name T446
Test name
Test status
Simulation time 63822439 ps
CPU time 0.99 seconds
Started Mar 23 01:56:41 PM PDT 24
Finished Mar 23 01:56:42 PM PDT 24
Peak memory 205156 kb
Host smart-1d280829-fbce-402c-8c45-31e58e6de2a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306569284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.306569284
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3328866658
Short name T478
Test name
Test status
Simulation time 26207165 ps
CPU time 0.77 seconds
Started Mar 23 01:56:40 PM PDT 24
Finished Mar 23 01:56:41 PM PDT 24
Peak memory 205184 kb
Host smart-24931f1e-add2-4813-81e3-42a519881b6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328866658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3328866658
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2020238510
Short name T515
Test name
Test status
Simulation time 289258768 ps
CPU time 2.93 seconds
Started Mar 23 01:56:41 PM PDT 24
Finished Mar 23 01:56:44 PM PDT 24
Peak memory 213420 kb
Host smart-e366a2eb-c72c-4380-a22f-3953780f5633
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020238510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2020238510
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3787926155
Short name T455
Test name
Test status
Simulation time 524462738 ps
CPU time 17.77 seconds
Started Mar 23 01:56:36 PM PDT 24
Finished Mar 23 01:56:54 PM PDT 24
Peak memory 221436 kb
Host smart-997b39f2-cf73-47c1-ac50-680b340d9a13
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787926155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3787926155
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3785395568
Short name T547
Test name
Test status
Simulation time 77112640 ps
CPU time 3.02 seconds
Started Mar 23 01:56:37 PM PDT 24
Finished Mar 23 01:56:40 PM PDT 24
Peak memory 213524 kb
Host smart-b6d2ffdd-53ea-43db-b8ee-4bdb169ee60b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785395568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3785395568
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1552768640
Short name T156
Test name
Test status
Simulation time 257271725 ps
CPU time 8.96 seconds
Started Mar 23 01:56:40 PM PDT 24
Finished Mar 23 01:56:49 PM PDT 24
Peak memory 213568 kb
Host smart-1f0f7911-080d-4d85-9b28-883055cbc54b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552768640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1552768640
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2651941136
Short name T527
Test name
Test status
Simulation time 287993462 ps
CPU time 1.38 seconds
Started Mar 23 01:56:52 PM PDT 24
Finished Mar 23 01:56:53 PM PDT 24
Peak memory 213584 kb
Host smart-7341a015-bcd8-4f9f-9645-ec2005d95059
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651941136 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2651941136
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1012437474
Short name T521
Test name
Test status
Simulation time 56173270 ps
CPU time 1.07 seconds
Started Mar 23 01:56:49 PM PDT 24
Finished Mar 23 01:56:50 PM PDT 24
Peak memory 205244 kb
Host smart-2596b81a-1c75-4f6a-b366-4fcb1fe55f0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012437474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1012437474
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2449522351
Short name T507
Test name
Test status
Simulation time 45333369 ps
CPU time 0.71 seconds
Started Mar 23 01:56:47 PM PDT 24
Finished Mar 23 01:56:48 PM PDT 24
Peak memory 205096 kb
Host smart-cd5d12ca-4660-4f40-8b5e-cfecf4ea9b77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449522351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2449522351
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3948713098
Short name T539
Test name
Test status
Simulation time 40208266 ps
CPU time 2.09 seconds
Started Mar 23 01:56:46 PM PDT 24
Finished Mar 23 01:56:48 PM PDT 24
Peak memory 205300 kb
Host smart-b3a1925e-7cf6-4df4-818b-4183ccd1a090
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948713098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3948713098
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3384656361
Short name T545
Test name
Test status
Simulation time 513561792 ps
CPU time 4.81 seconds
Started Mar 23 01:56:47 PM PDT 24
Finished Mar 23 01:56:52 PM PDT 24
Peak memory 213716 kb
Host smart-c23c5abf-05e2-4714-a958-c596b1adc829
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384656361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3384656361
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.740765980
Short name T548
Test name
Test status
Simulation time 89489636 ps
CPU time 3.53 seconds
Started Mar 23 01:56:56 PM PDT 24
Finished Mar 23 01:57:00 PM PDT 24
Peak memory 213568 kb
Host smart-c38b28bf-d636-4009-85f1-b61f413049c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740765980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.740765980
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2667375467
Short name T157
Test name
Test status
Simulation time 242605173 ps
CPU time 4.44 seconds
Started Mar 23 01:56:45 PM PDT 24
Finished Mar 23 01:56:50 PM PDT 24
Peak memory 208884 kb
Host smart-b1cf5e9a-bfd7-4494-a7a2-4140ffd3df17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667375467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2667375467
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1581193599
Short name T434
Test name
Test status
Simulation time 18628777 ps
CPU time 1.04 seconds
Started Mar 23 01:56:57 PM PDT 24
Finished Mar 23 01:56:58 PM PDT 24
Peak memory 205284 kb
Host smart-1253f81b-a4de-41f3-ba2c-940b9e3b8bbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581193599 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1581193599
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1503831366
Short name T506
Test name
Test status
Simulation time 46759420 ps
CPU time 0.91 seconds
Started Mar 23 01:56:50 PM PDT 24
Finished Mar 23 01:56:51 PM PDT 24
Peak memory 205176 kb
Host smart-4e385c11-1a8f-41d9-b7c3-80b74cbf647b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503831366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1503831366
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.4145788933
Short name T475
Test name
Test status
Simulation time 84566005 ps
CPU time 1.38 seconds
Started Mar 23 01:56:49 PM PDT 24
Finished Mar 23 01:56:51 PM PDT 24
Peak memory 205320 kb
Host smart-c263abcf-5ff9-47b5-82a3-74373b5e7562
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145788933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.4145788933
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4095700459
Short name T109
Test name
Test status
Simulation time 1267939402 ps
CPU time 5.31 seconds
Started Mar 23 01:56:48 PM PDT 24
Finished Mar 23 01:56:54 PM PDT 24
Peak memory 213840 kb
Host smart-7029a890-76fc-4e17-8b4c-f94053bd5fb0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095700459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.4095700459
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1825607149
Short name T531
Test name
Test status
Simulation time 202977935 ps
CPU time 11.15 seconds
Started Mar 23 01:56:56 PM PDT 24
Finished Mar 23 01:57:08 PM PDT 24
Peak memory 213672 kb
Host smart-6a7ce3c7-4a89-4564-9386-4804af23dddd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825607149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1825607149
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.435018279
Short name T110
Test name
Test status
Simulation time 770109105 ps
CPU time 4.41 seconds
Started Mar 23 01:56:45 PM PDT 24
Finished Mar 23 01:56:50 PM PDT 24
Peak memory 213516 kb
Host smart-61548ece-30d0-440e-ade3-078ad7935c60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435018279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.435018279
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3745549353
Short name T441
Test name
Test status
Simulation time 17533435 ps
CPU time 1.36 seconds
Started Mar 23 01:56:49 PM PDT 24
Finished Mar 23 01:56:50 PM PDT 24
Peak memory 213672 kb
Host smart-d5261504-89fe-439a-8ee4-46784fc4d07e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745549353 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3745549353
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.535855843
Short name T524
Test name
Test status
Simulation time 45573735 ps
CPU time 0.87 seconds
Started Mar 23 01:56:46 PM PDT 24
Finished Mar 23 01:56:47 PM PDT 24
Peak memory 205368 kb
Host smart-d1042926-18e1-4b73-9a22-31b2eeae74a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535855843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.535855843
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4228137291
Short name T468
Test name
Test status
Simulation time 21316700 ps
CPU time 1.47 seconds
Started Mar 23 01:56:46 PM PDT 24
Finished Mar 23 01:56:48 PM PDT 24
Peak memory 205216 kb
Host smart-c6db8093-8cf2-4d4d-a210-e7b93562ab4b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228137291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.4228137291
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.4247944445
Short name T462
Test name
Test status
Simulation time 114985669 ps
CPU time 2.76 seconds
Started Mar 23 01:56:46 PM PDT 24
Finished Mar 23 01:56:49 PM PDT 24
Peak memory 213824 kb
Host smart-0b4d4712-6279-4faa-85f6-787fa479dfb9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247944445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.4247944445
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1201357315
Short name T445
Test name
Test status
Simulation time 215230237 ps
CPU time 7.45 seconds
Started Mar 23 01:56:46 PM PDT 24
Finished Mar 23 01:56:53 PM PDT 24
Peak memory 213812 kb
Host smart-ae615927-a7a1-4b4a-88e3-a6be7f402270
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201357315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1201357315
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2848054610
Short name T549
Test name
Test status
Simulation time 60253424 ps
CPU time 4.26 seconds
Started Mar 23 01:56:50 PM PDT 24
Finished Mar 23 01:56:54 PM PDT 24
Peak memory 216004 kb
Host smart-7dc50d35-d6b2-42d9-9de0-5709b6a72678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848054610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2848054610
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3002587102
Short name T554
Test name
Test status
Simulation time 1543279463 ps
CPU time 7.09 seconds
Started Mar 23 01:56:46 PM PDT 24
Finished Mar 23 01:56:53 PM PDT 24
Peak memory 208992 kb
Host smart-54f60c4e-ce32-43ed-b78e-02ec38ce0019
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002587102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3002587102
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3258239933
Short name T485
Test name
Test status
Simulation time 296286877 ps
CPU time 4.25 seconds
Started Mar 23 01:56:03 PM PDT 24
Finished Mar 23 01:56:08 PM PDT 24
Peak memory 205232 kb
Host smart-95f05c30-9333-4b15-98ad-17c15d425f59
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258239933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
258239933
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.487259830
Short name T482
Test name
Test status
Simulation time 368035617 ps
CPU time 1.64 seconds
Started Mar 23 01:56:07 PM PDT 24
Finished Mar 23 01:56:09 PM PDT 24
Peak memory 205292 kb
Host smart-fe09c8ea-cc31-4b3b-93be-e6498bc024c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487259830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.487259830
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2024727237
Short name T177
Test name
Test status
Simulation time 292208434 ps
CPU time 1.37 seconds
Started Mar 23 01:56:05 PM PDT 24
Finished Mar 23 01:56:06 PM PDT 24
Peak memory 213716 kb
Host smart-c0e38b9f-fb4a-4db9-8052-9a4bef5d6341
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024727237 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2024727237
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.4128523103
Short name T137
Test name
Test status
Simulation time 18963323 ps
CPU time 1.22 seconds
Started Mar 23 01:56:05 PM PDT 24
Finished Mar 23 01:56:07 PM PDT 24
Peak memory 205160 kb
Host smart-d9502154-c8f9-42ef-a019-a206ffb81e20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128523103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.4128523103
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2601220308
Short name T448
Test name
Test status
Simulation time 88988541 ps
CPU time 0.73 seconds
Started Mar 23 01:55:58 PM PDT 24
Finished Mar 23 01:55:59 PM PDT 24
Peak memory 205100 kb
Host smart-f841708e-51f6-4be7-b2d0-b148638d0077
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601220308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2601220308
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.632766494
Short name T165
Test name
Test status
Simulation time 204101995 ps
CPU time 5.6 seconds
Started Mar 23 01:56:02 PM PDT 24
Finished Mar 23 01:56:08 PM PDT 24
Peak memory 213852 kb
Host smart-082485c4-22d3-4b87-822c-febd09d6f45f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632766494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.632766494
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1673472278
Short name T106
Test name
Test status
Simulation time 249453682 ps
CPU time 1.67 seconds
Started Mar 23 01:55:58 PM PDT 24
Finished Mar 23 01:56:00 PM PDT 24
Peak memory 213604 kb
Host smart-c550ba23-328d-4c73-812c-f72637162955
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673472278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1673472278
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1590393481
Short name T149
Test name
Test status
Simulation time 2974921544 ps
CPU time 32.37 seconds
Started Mar 23 01:55:57 PM PDT 24
Finished Mar 23 01:56:30 PM PDT 24
Peak memory 213560 kb
Host smart-8aa10f03-e1aa-4c9d-b601-28ee0d103ee2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590393481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1590393481
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1123909840
Short name T541
Test name
Test status
Simulation time 66982979 ps
CPU time 0.94 seconds
Started Mar 23 01:56:50 PM PDT 24
Finished Mar 23 01:56:51 PM PDT 24
Peak memory 205204 kb
Host smart-0f421c41-8702-48d8-8107-66751cf83e4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123909840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1123909840
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1248745540
Short name T502
Test name
Test status
Simulation time 16353316 ps
CPU time 0.74 seconds
Started Mar 23 01:56:49 PM PDT 24
Finished Mar 23 01:56:50 PM PDT 24
Peak memory 205104 kb
Host smart-d66aeb5a-20a3-4b40-bef7-73964759a429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248745540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1248745540
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.550872596
Short name T382
Test name
Test status
Simulation time 7656335 ps
CPU time 0.73 seconds
Started Mar 23 01:56:50 PM PDT 24
Finished Mar 23 01:56:51 PM PDT 24
Peak memory 205132 kb
Host smart-fd1f65e9-24a1-48f6-bb14-8356abf3eac2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550872596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.550872596
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3320725572
Short name T481
Test name
Test status
Simulation time 28703754 ps
CPU time 0.71 seconds
Started Mar 23 01:56:52 PM PDT 24
Finished Mar 23 01:56:53 PM PDT 24
Peak memory 205108 kb
Host smart-e133d62b-8124-4c76-aa1c-43a37b343dac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320725572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3320725572
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1018514242
Short name T497
Test name
Test status
Simulation time 116657230 ps
CPU time 0.72 seconds
Started Mar 23 01:56:47 PM PDT 24
Finished Mar 23 01:56:48 PM PDT 24
Peak memory 205072 kb
Host smart-40d4dbb3-2328-4571-99a8-e7bb69467403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018514242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1018514242
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2524999680
Short name T500
Test name
Test status
Simulation time 40656123 ps
CPU time 0.91 seconds
Started Mar 23 01:56:56 PM PDT 24
Finished Mar 23 01:56:57 PM PDT 24
Peak memory 205072 kb
Host smart-036a4ae4-c48e-4707-b63f-6f5003e51e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524999680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2524999680
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2660378626
Short name T512
Test name
Test status
Simulation time 63298537 ps
CPU time 0.81 seconds
Started Mar 23 01:56:47 PM PDT 24
Finished Mar 23 01:56:48 PM PDT 24
Peak memory 205148 kb
Host smart-1f48198a-12f9-42f4-92c7-db25aab31beb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660378626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2660378626
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.4131749585
Short name T491
Test name
Test status
Simulation time 12380878 ps
CPU time 0.76 seconds
Started Mar 23 01:56:52 PM PDT 24
Finished Mar 23 01:56:53 PM PDT 24
Peak memory 205184 kb
Host smart-e5064d02-0c18-456b-985e-5f755de29c4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131749585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.4131749585
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3672012555
Short name T479
Test name
Test status
Simulation time 20656043 ps
CPU time 0.82 seconds
Started Mar 23 01:56:47 PM PDT 24
Finished Mar 23 01:56:48 PM PDT 24
Peak memory 205056 kb
Host smart-b4b0705a-c824-460b-bd95-d3708131404f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672012555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3672012555
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1591392342
Short name T561
Test name
Test status
Simulation time 18704330 ps
CPU time 0.76 seconds
Started Mar 23 01:56:55 PM PDT 24
Finished Mar 23 01:56:56 PM PDT 24
Peak memory 205368 kb
Host smart-403b5078-1880-43a1-a442-04814258fe7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591392342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1591392342
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1955652349
Short name T557
Test name
Test status
Simulation time 396245028 ps
CPU time 10.17 seconds
Started Mar 23 01:56:17 PM PDT 24
Finished Mar 23 01:56:28 PM PDT 24
Peak memory 205288 kb
Host smart-4f077330-0e27-4152-95fa-52a85f0de7b6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955652349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
955652349
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.974528005
Short name T494
Test name
Test status
Simulation time 73827305 ps
CPU time 0.97 seconds
Started Mar 23 01:56:05 PM PDT 24
Finished Mar 23 01:56:06 PM PDT 24
Peak memory 205104 kb
Host smart-fe793114-e24c-4e4a-83f0-338e74208cbb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974528005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.974528005
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2614266644
Short name T171
Test name
Test status
Simulation time 22194395 ps
CPU time 1.13 seconds
Started Mar 23 01:56:18 PM PDT 24
Finished Mar 23 01:56:19 PM PDT 24
Peak memory 205320 kb
Host smart-006b3734-ed57-4683-badd-aa79354cc67a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614266644 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2614266644
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2735394365
Short name T433
Test name
Test status
Simulation time 64279814 ps
CPU time 0.97 seconds
Started Mar 23 01:56:05 PM PDT 24
Finished Mar 23 01:56:06 PM PDT 24
Peak memory 205124 kb
Host smart-c14c46f7-e23e-4d80-8fab-fc485c805115
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735394365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2735394365
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1323042520
Short name T465
Test name
Test status
Simulation time 16817131 ps
CPU time 0.8 seconds
Started Mar 23 01:56:06 PM PDT 24
Finished Mar 23 01:56:07 PM PDT 24
Peak memory 205072 kb
Host smart-1f0220af-f392-48f1-9ea5-416738ba5f2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323042520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1323042520
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3592939844
Short name T514
Test name
Test status
Simulation time 92794566 ps
CPU time 3.5 seconds
Started Mar 23 01:56:18 PM PDT 24
Finished Mar 23 01:56:22 PM PDT 24
Peak memory 205224 kb
Host smart-221bd631-9811-4abd-9fb0-1b73522d804b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592939844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3592939844
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1268492799
Short name T451
Test name
Test status
Simulation time 801012165 ps
CPU time 6.07 seconds
Started Mar 23 01:56:06 PM PDT 24
Finished Mar 23 01:56:12 PM PDT 24
Peak memory 213840 kb
Host smart-3b914b1a-7ee9-4976-9610-27f122388d25
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268492799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1268492799
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.418814840
Short name T115
Test name
Test status
Simulation time 461999339 ps
CPU time 16.99 seconds
Started Mar 23 01:56:06 PM PDT 24
Finished Mar 23 01:56:23 PM PDT 24
Peak memory 213892 kb
Host smart-ffc72f39-ea14-4167-b591-46edeb0a8266
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418814840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.418814840
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1417225614
Short name T176
Test name
Test status
Simulation time 908087875 ps
CPU time 2.9 seconds
Started Mar 23 01:56:05 PM PDT 24
Finished Mar 23 01:56:08 PM PDT 24
Peak memory 216040 kb
Host smart-68cbc99a-c34e-4f0b-89c3-567958644a95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417225614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1417225614
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.252684013
Short name T510
Test name
Test status
Simulation time 29199224 ps
CPU time 0.79 seconds
Started Mar 23 01:56:59 PM PDT 24
Finished Mar 23 01:57:00 PM PDT 24
Peak memory 205200 kb
Host smart-9fb2281d-ddf5-4f98-a2d0-634244cd25bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252684013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.252684013
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1891359866
Short name T516
Test name
Test status
Simulation time 34023284 ps
CPU time 0.77 seconds
Started Mar 23 01:56:58 PM PDT 24
Finished Mar 23 01:56:59 PM PDT 24
Peak memory 204920 kb
Host smart-2e7aee42-1548-4fea-9225-1bf1751aaadc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891359866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1891359866
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.41177402
Short name T525
Test name
Test status
Simulation time 9133516 ps
CPU time 0.83 seconds
Started Mar 23 01:56:57 PM PDT 24
Finished Mar 23 01:56:58 PM PDT 24
Peak memory 205104 kb
Host smart-9b5182d5-8c2a-468d-877f-ede24f59bd28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41177402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.41177402
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2973117469
Short name T503
Test name
Test status
Simulation time 44757833 ps
CPU time 0.76 seconds
Started Mar 23 01:56:58 PM PDT 24
Finished Mar 23 01:56:59 PM PDT 24
Peak memory 204736 kb
Host smart-248f61aa-adb0-4a6b-8d64-58e4179f6e27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973117469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2973117469
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3163991354
Short name T486
Test name
Test status
Simulation time 17427160 ps
CPU time 0.71 seconds
Started Mar 23 01:56:58 PM PDT 24
Finished Mar 23 01:56:59 PM PDT 24
Peak memory 205208 kb
Host smart-1a45e744-53cf-4e80-a8d0-e7cd2f771359
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163991354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3163991354
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.799881378
Short name T431
Test name
Test status
Simulation time 12277968 ps
CPU time 0.75 seconds
Started Mar 23 01:56:56 PM PDT 24
Finished Mar 23 01:56:57 PM PDT 24
Peak memory 205036 kb
Host smart-0cc45f35-8a68-4557-b08b-5d2947df8948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799881378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.799881378
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.419573674
Short name T533
Test name
Test status
Simulation time 34838244 ps
CPU time 0.73 seconds
Started Mar 23 01:56:59 PM PDT 24
Finished Mar 23 01:57:00 PM PDT 24
Peak memory 205080 kb
Host smart-8c96f6f4-2c71-4c36-8133-5033221dd3b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419573674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.419573674
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.47000019
Short name T518
Test name
Test status
Simulation time 30804185 ps
CPU time 0.7 seconds
Started Mar 23 01:56:56 PM PDT 24
Finished Mar 23 01:56:57 PM PDT 24
Peak memory 205180 kb
Host smart-beebd435-edcf-4f09-a2d3-c8192a024604
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47000019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.47000019
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2696529735
Short name T487
Test name
Test status
Simulation time 14263739 ps
CPU time 0.9 seconds
Started Mar 23 01:56:57 PM PDT 24
Finished Mar 23 01:56:58 PM PDT 24
Peak memory 205248 kb
Host smart-e0130325-a7e0-435b-b53d-77a519695a34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696529735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2696529735
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3797452002
Short name T517
Test name
Test status
Simulation time 21570573 ps
CPU time 0.74 seconds
Started Mar 23 01:56:57 PM PDT 24
Finished Mar 23 01:56:58 PM PDT 24
Peak memory 205196 kb
Host smart-5e0998cc-5176-44fa-bec7-5bd044278872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797452002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3797452002
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1875854480
Short name T538
Test name
Test status
Simulation time 1231109007 ps
CPU time 14.17 seconds
Started Mar 23 01:56:16 PM PDT 24
Finished Mar 23 01:56:30 PM PDT 24
Peak memory 205156 kb
Host smart-e8d846dd-e8e3-4701-b8ea-cd35d66d157e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875854480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
875854480
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.247302911
Short name T535
Test name
Test status
Simulation time 14768369 ps
CPU time 1.03 seconds
Started Mar 23 01:56:16 PM PDT 24
Finished Mar 23 01:56:17 PM PDT 24
Peak memory 205080 kb
Host smart-e8697488-6b00-4492-8733-d4c39062544e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247302911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.247302911
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.2102882904
Short name T459
Test name
Test status
Simulation time 18560177 ps
CPU time 1.16 seconds
Started Mar 23 01:56:16 PM PDT 24
Finished Mar 23 01:56:18 PM PDT 24
Peak memory 205404 kb
Host smart-a225f01c-2c58-49d6-b92b-096b70d244e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102882904 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.2102882904
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1871673518
Short name T136
Test name
Test status
Simulation time 29300121 ps
CPU time 1.23 seconds
Started Mar 23 01:56:16 PM PDT 24
Finished Mar 23 01:56:17 PM PDT 24
Peak memory 205040 kb
Host smart-3fda0601-19ff-40cc-b0a2-248ac00ae622
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871673518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1871673518
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3339360001
Short name T178
Test name
Test status
Simulation time 163301412 ps
CPU time 0.75 seconds
Started Mar 23 01:56:16 PM PDT 24
Finished Mar 23 01:56:17 PM PDT 24
Peak memory 205212 kb
Host smart-6313e6f3-35f8-4223-b657-c9b0d6299af2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339360001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3339360001
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1048288019
Short name T476
Test name
Test status
Simulation time 95246358 ps
CPU time 2.12 seconds
Started Mar 23 01:56:18 PM PDT 24
Finished Mar 23 01:56:20 PM PDT 24
Peak memory 205256 kb
Host smart-46e735fc-4868-42ff-b474-d79586d6a1c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048288019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1048288019
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1313309274
Short name T519
Test name
Test status
Simulation time 674623303 ps
CPU time 6.48 seconds
Started Mar 23 01:56:16 PM PDT 24
Finished Mar 23 01:56:23 PM PDT 24
Peak memory 213748 kb
Host smart-24221a7a-8ee4-456f-829e-617b215a4135
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313309274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1313309274
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1288942069
Short name T553
Test name
Test status
Simulation time 65792622 ps
CPU time 2.81 seconds
Started Mar 23 01:56:16 PM PDT 24
Finished Mar 23 01:56:19 PM PDT 24
Peak memory 213644 kb
Host smart-e09501cf-513b-4ab9-8bbf-0ffc48f09789
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288942069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1288942069
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2000986529
Short name T546
Test name
Test status
Simulation time 206178551 ps
CPU time 3.19 seconds
Started Mar 23 01:56:17 PM PDT 24
Finished Mar 23 01:56:21 PM PDT 24
Peak memory 208772 kb
Host smart-9ab0e971-4fdd-40f5-bce2-365bbe6d58be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000986529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2000986529
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1907108604
Short name T563
Test name
Test status
Simulation time 19080804 ps
CPU time 0.91 seconds
Started Mar 23 01:56:59 PM PDT 24
Finished Mar 23 01:57:00 PM PDT 24
Peak memory 205020 kb
Host smart-0112b3cd-731d-49bb-adf6-d5948ae24492
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907108604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1907108604
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2622384184
Short name T435
Test name
Test status
Simulation time 8847811 ps
CPU time 0.71 seconds
Started Mar 23 01:56:57 PM PDT 24
Finished Mar 23 01:56:58 PM PDT 24
Peak memory 205096 kb
Host smart-12ec47f2-ab67-4fcc-a23d-9edfcc90fc4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622384184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2622384184
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.408338698
Short name T552
Test name
Test status
Simulation time 47892364 ps
CPU time 0.75 seconds
Started Mar 23 01:56:56 PM PDT 24
Finished Mar 23 01:56:57 PM PDT 24
Peak memory 205056 kb
Host smart-169709e3-c9fe-4524-8924-38117eb9389d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408338698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.408338698
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3221503590
Short name T454
Test name
Test status
Simulation time 118902104 ps
CPU time 0.69 seconds
Started Mar 23 01:56:56 PM PDT 24
Finished Mar 23 01:56:57 PM PDT 24
Peak memory 205112 kb
Host smart-cf9a333d-e6bf-48ee-92ff-4a83482d7b5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221503590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3221503590
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2780476147
Short name T179
Test name
Test status
Simulation time 39487723 ps
CPU time 0.86 seconds
Started Mar 23 01:56:59 PM PDT 24
Finished Mar 23 01:57:00 PM PDT 24
Peak memory 205196 kb
Host smart-d1c6df31-9503-4c8a-a86d-c51c308e4115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780476147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2780476147
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3085092907
Short name T501
Test name
Test status
Simulation time 44146368 ps
CPU time 0.87 seconds
Started Mar 23 01:56:59 PM PDT 24
Finished Mar 23 01:57:00 PM PDT 24
Peak memory 205096 kb
Host smart-6d9747e0-44cd-4d2a-8a6d-96968bca8454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085092907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3085092907
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3195148520
Short name T432
Test name
Test status
Simulation time 23273977 ps
CPU time 0.85 seconds
Started Mar 23 01:56:56 PM PDT 24
Finished Mar 23 01:56:57 PM PDT 24
Peak memory 205100 kb
Host smart-fc967e75-ef47-4442-bff8-03842d3ddb55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195148520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3195148520
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.4143507426
Short name T447
Test name
Test status
Simulation time 88155361 ps
CPU time 0.82 seconds
Started Mar 23 01:56:57 PM PDT 24
Finished Mar 23 01:56:58 PM PDT 24
Peak memory 205180 kb
Host smart-45ee748b-bff4-4c0a-96e2-98541b294a1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143507426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.4143507426
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.4020917010
Short name T534
Test name
Test status
Simulation time 73096142 ps
CPU time 0.69 seconds
Started Mar 23 01:56:56 PM PDT 24
Finished Mar 23 01:56:57 PM PDT 24
Peak memory 205168 kb
Host smart-5432883d-253a-4991-8908-35caa10860fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020917010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.4020917010
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.60763708
Short name T464
Test name
Test status
Simulation time 10529619 ps
CPU time 0.82 seconds
Started Mar 23 01:56:56 PM PDT 24
Finished Mar 23 01:56:57 PM PDT 24
Peak memory 205152 kb
Host smart-3fdd131b-968e-4891-8cfd-c4020593ecad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60763708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.60763708
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3044697269
Short name T550
Test name
Test status
Simulation time 101123573 ps
CPU time 1.7 seconds
Started Mar 23 01:56:16 PM PDT 24
Finished Mar 23 01:56:18 PM PDT 24
Peak memory 213776 kb
Host smart-4d343c1c-acf6-463d-b9b0-655f029f89b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044697269 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3044697269
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.617804475
Short name T139
Test name
Test status
Simulation time 18096179 ps
CPU time 1.25 seconds
Started Mar 23 01:56:18 PM PDT 24
Finished Mar 23 01:56:19 PM PDT 24
Peak memory 205264 kb
Host smart-4fd45dea-3be1-46d1-8d6f-4450275c296e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617804475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.617804475
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3250657722
Short name T496
Test name
Test status
Simulation time 16288253 ps
CPU time 0.84 seconds
Started Mar 23 01:56:18 PM PDT 24
Finished Mar 23 01:56:20 PM PDT 24
Peak memory 205200 kb
Host smart-e5aae96e-a1d8-43d2-8ca8-0552feec728e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250657722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3250657722
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1150225862
Short name T143
Test name
Test status
Simulation time 130095850 ps
CPU time 2.5 seconds
Started Mar 23 01:56:16 PM PDT 24
Finished Mar 23 01:56:19 PM PDT 24
Peak memory 205316 kb
Host smart-2d664620-cec8-4225-a59b-44d301ec15a6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150225862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1150225862
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3614058801
Short name T495
Test name
Test status
Simulation time 580494109 ps
CPU time 12.14 seconds
Started Mar 23 01:56:19 PM PDT 24
Finished Mar 23 01:56:31 PM PDT 24
Peak memory 213840 kb
Host smart-3711096f-7e41-4b85-aca3-f43b0a46d9d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614058801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3614058801
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2644752393
Short name T509
Test name
Test status
Simulation time 230818933 ps
CPU time 2.43 seconds
Started Mar 23 01:56:18 PM PDT 24
Finished Mar 23 01:56:20 PM PDT 24
Peak memory 214836 kb
Host smart-f25af19c-3bec-4f99-a121-b8fca865280b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644752393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2644752393
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3697213512
Short name T151
Test name
Test status
Simulation time 382291737 ps
CPU time 6.93 seconds
Started Mar 23 01:56:17 PM PDT 24
Finished Mar 23 01:56:24 PM PDT 24
Peak memory 213596 kb
Host smart-7731c1b8-0d3c-4660-abae-f1a829dd8efd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697213512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3697213512
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1395440134
Short name T477
Test name
Test status
Simulation time 27913113 ps
CPU time 1.19 seconds
Started Mar 23 01:56:17 PM PDT 24
Finished Mar 23 01:56:19 PM PDT 24
Peak memory 205308 kb
Host smart-7b1c993f-d397-4cd6-a2b5-de927e6c341c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395440134 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1395440134
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3664896166
Short name T505
Test name
Test status
Simulation time 16384519 ps
CPU time 1.29 seconds
Started Mar 23 01:56:18 PM PDT 24
Finished Mar 23 01:56:20 PM PDT 24
Peak memory 205212 kb
Host smart-68da84f8-325b-41f5-8c4a-922d57d9263b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664896166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3664896166
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.622628686
Short name T520
Test name
Test status
Simulation time 26754138 ps
CPU time 0.76 seconds
Started Mar 23 01:56:15 PM PDT 24
Finished Mar 23 01:56:16 PM PDT 24
Peak memory 205148 kb
Host smart-70745962-b635-4ff5-a100-b98b46aa04c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622628686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.622628686
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.4285097631
Short name T513
Test name
Test status
Simulation time 116367427 ps
CPU time 1.9 seconds
Started Mar 23 01:56:18 PM PDT 24
Finished Mar 23 01:56:21 PM PDT 24
Peak memory 213548 kb
Host smart-f917f967-1848-4f5d-afe1-058ceeb2944e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285097631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.4285097631
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1782278507
Short name T536
Test name
Test status
Simulation time 3899221373 ps
CPU time 9.31 seconds
Started Mar 23 01:56:18 PM PDT 24
Finished Mar 23 01:56:27 PM PDT 24
Peak memory 213752 kb
Host smart-2cf37588-48ff-477c-89df-7cba58919480
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782278507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1782278507
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.4252458197
Short name T450
Test name
Test status
Simulation time 211652835 ps
CPU time 10.38 seconds
Started Mar 23 01:56:15 PM PDT 24
Finished Mar 23 01:56:26 PM PDT 24
Peak memory 213792 kb
Host smart-f80307c8-dc46-4951-9d49-fc7fcef2ea4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252458197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.4252458197
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3163156593
Short name T442
Test name
Test status
Simulation time 102478837 ps
CPU time 1.76 seconds
Started Mar 23 01:56:16 PM PDT 24
Finished Mar 23 01:56:18 PM PDT 24
Peak memory 213604 kb
Host smart-1ecf3581-f19e-466d-bbf1-57f873084dfe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163156593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3163156593
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2341879217
Short name T163
Test name
Test status
Simulation time 231102446 ps
CPU time 4.97 seconds
Started Mar 23 01:56:17 PM PDT 24
Finished Mar 23 01:56:22 PM PDT 24
Peak memory 209084 kb
Host smart-491a5485-02fc-4f84-9b56-730696126cae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341879217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2341879217
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.456216451
Short name T174
Test name
Test status
Simulation time 69119740 ps
CPU time 1.69 seconds
Started Mar 23 01:56:25 PM PDT 24
Finished Mar 23 01:56:27 PM PDT 24
Peak memory 213540 kb
Host smart-167db1c0-0f87-4b6b-a67c-db2e43c17c8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456216451 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.456216451
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1770725529
Short name T456
Test name
Test status
Simulation time 46058357 ps
CPU time 0.88 seconds
Started Mar 23 01:56:26 PM PDT 24
Finished Mar 23 01:56:27 PM PDT 24
Peak memory 205184 kb
Host smart-93f27e26-7ca9-4771-8ae0-71c89c5539e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770725529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1770725529
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.717715259
Short name T457
Test name
Test status
Simulation time 51014506 ps
CPU time 2.11 seconds
Started Mar 23 01:56:32 PM PDT 24
Finished Mar 23 01:56:34 PM PDT 24
Peak memory 205416 kb
Host smart-ba8977be-a4f8-42f3-9aab-02c456f1fb42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717715259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.717715259
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2118500583
Short name T544
Test name
Test status
Simulation time 1448956035 ps
CPU time 2.88 seconds
Started Mar 23 01:56:19 PM PDT 24
Finished Mar 23 01:56:22 PM PDT 24
Peak memory 213880 kb
Host smart-e7ab65ee-a663-4340-af5c-244947b66696
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118500583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2118500583
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3179743209
Short name T504
Test name
Test status
Simulation time 434206159 ps
CPU time 16.23 seconds
Started Mar 23 01:56:17 PM PDT 24
Finished Mar 23 01:56:34 PM PDT 24
Peak memory 213784 kb
Host smart-0d82db99-4e2e-4e07-912a-26315524c647
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179743209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3179743209
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.711061438
Short name T542
Test name
Test status
Simulation time 67897233 ps
CPU time 2.23 seconds
Started Mar 23 01:56:16 PM PDT 24
Finished Mar 23 01:56:19 PM PDT 24
Peak memory 213536 kb
Host smart-caafb857-16c8-41fc-bbe6-d76887d8e274
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711061438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.711061438
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.659171964
Short name T116
Test name
Test status
Simulation time 23331607 ps
CPU time 1.27 seconds
Started Mar 23 01:56:25 PM PDT 24
Finished Mar 23 01:56:27 PM PDT 24
Peak memory 205400 kb
Host smart-a72f1a31-7705-48cd-9324-3b08763f75b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659171964 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.659171964
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2320321731
Short name T471
Test name
Test status
Simulation time 65155899 ps
CPU time 1.2 seconds
Started Mar 23 01:56:26 PM PDT 24
Finished Mar 23 01:56:27 PM PDT 24
Peak memory 205344 kb
Host smart-776d3f4a-08d1-462b-a91d-0a692fb82986
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320321731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2320321731
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1470502539
Short name T140
Test name
Test status
Simulation time 13776461 ps
CPU time 0.72 seconds
Started Mar 23 01:56:27 PM PDT 24
Finished Mar 23 01:56:28 PM PDT 24
Peak memory 205112 kb
Host smart-c2c39a6c-dfb8-47f7-87a6-7e23e187a94c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470502539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1470502539
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3843142935
Short name T555
Test name
Test status
Simulation time 372318901 ps
CPU time 2.87 seconds
Started Mar 23 01:56:27 PM PDT 24
Finished Mar 23 01:56:30 PM PDT 24
Peak memory 205260 kb
Host smart-19f5e256-0194-40a5-a369-c068e0554b63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843142935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3843142935
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1418915143
Short name T458
Test name
Test status
Simulation time 543599656 ps
CPU time 2.71 seconds
Started Mar 23 01:56:25 PM PDT 24
Finished Mar 23 01:56:28 PM PDT 24
Peak memory 213816 kb
Host smart-609c0725-8419-4c61-ac09-0165aaf92350
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418915143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1418915143
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.4034865506
Short name T108
Test name
Test status
Simulation time 352582704 ps
CPU time 5.05 seconds
Started Mar 23 01:56:26 PM PDT 24
Finished Mar 23 01:56:31 PM PDT 24
Peak memory 213732 kb
Host smart-db9c4f10-3b47-42f1-a62c-efe7e46b2e1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034865506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.4034865506
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1068721602
Short name T452
Test name
Test status
Simulation time 459293756 ps
CPU time 3.54 seconds
Started Mar 23 01:56:26 PM PDT 24
Finished Mar 23 01:56:29 PM PDT 24
Peak memory 213520 kb
Host smart-4a2df89c-3cf1-49d7-8a1c-0748c767411d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068721602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1068721602
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.943780219
Short name T460
Test name
Test status
Simulation time 29265282 ps
CPU time 2.02 seconds
Started Mar 23 01:56:27 PM PDT 24
Finished Mar 23 01:56:29 PM PDT 24
Peak memory 213648 kb
Host smart-e37f633c-a3e7-4143-8ce9-417faa326ba8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943780219 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.943780219
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1080521846
Short name T511
Test name
Test status
Simulation time 75419697 ps
CPU time 1.19 seconds
Started Mar 23 01:56:27 PM PDT 24
Finished Mar 23 01:56:28 PM PDT 24
Peak memory 205164 kb
Host smart-d985338d-0f50-4dba-b817-dfd8f2569cc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080521846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1080521846
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2979505888
Short name T484
Test name
Test status
Simulation time 12877979 ps
CPU time 0.89 seconds
Started Mar 23 01:56:31 PM PDT 24
Finished Mar 23 01:56:32 PM PDT 24
Peak memory 205208 kb
Host smart-96c80114-7d22-407a-b378-6eefbdfc8b28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979505888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2979505888
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.120719646
Short name T499
Test name
Test status
Simulation time 337564680 ps
CPU time 3.45 seconds
Started Mar 23 01:56:26 PM PDT 24
Finished Mar 23 01:56:30 PM PDT 24
Peak memory 205228 kb
Host smart-815c9977-b9fa-45d7-91bb-515472ec199a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120719646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.120719646
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.4253251123
Short name T164
Test name
Test status
Simulation time 268251862 ps
CPU time 2.68 seconds
Started Mar 23 01:56:25 PM PDT 24
Finished Mar 23 01:56:28 PM PDT 24
Peak memory 213684 kb
Host smart-3b60d642-57a5-4a03-b166-ba5d31938a60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253251123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.4253251123
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3604255689
Short name T523
Test name
Test status
Simulation time 349736668 ps
CPU time 6.02 seconds
Started Mar 23 01:56:31 PM PDT 24
Finished Mar 23 01:56:37 PM PDT 24
Peak memory 213720 kb
Host smart-7bbcfe25-4b31-4172-aee8-825ba282f5c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604255689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3604255689
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.755819659
Short name T148
Test name
Test status
Simulation time 6608431938 ps
CPU time 60.87 seconds
Started Mar 23 01:56:27 PM PDT 24
Finished Mar 23 01:57:28 PM PDT 24
Peak memory 213628 kb
Host smart-fcbc7508-e290-43f0-abde-60d428049b26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755819659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
755819659
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2532859789
Short name T676
Test name
Test status
Simulation time 12572397 ps
CPU time 0.78 seconds
Started Mar 23 03:59:42 PM PDT 24
Finished Mar 23 03:59:44 PM PDT 24
Peak memory 206056 kb
Host smart-f0e83902-21f6-46cb-b18a-1e69ba22b04d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532859789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2532859789
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.939704058
Short name T405
Test name
Test status
Simulation time 6352126949 ps
CPU time 83.8 seconds
Started Mar 23 03:59:25 PM PDT 24
Finished Mar 23 04:00:49 PM PDT 24
Peak memory 214876 kb
Host smart-050a8092-bec6-4928-8113-c098885741a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=939704058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.939704058
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1260779789
Short name T777
Test name
Test status
Simulation time 40169401 ps
CPU time 2.16 seconds
Started Mar 23 03:59:23 PM PDT 24
Finished Mar 23 03:59:26 PM PDT 24
Peak memory 207344 kb
Host smart-cab1c51c-5358-4682-b46d-c065276289d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260779789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1260779789
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.501750122
Short name T965
Test name
Test status
Simulation time 496397278 ps
CPU time 7.63 seconds
Started Mar 23 03:59:23 PM PDT 24
Finished Mar 23 03:59:31 PM PDT 24
Peak memory 211348 kb
Host smart-c49f465d-7d87-4733-ad1b-647db424c5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501750122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.501750122
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.796105251
Short name T280
Test name
Test status
Simulation time 510222484 ps
CPU time 6.13 seconds
Started Mar 23 03:59:21 PM PDT 24
Finished Mar 23 03:59:27 PM PDT 24
Peak memory 217700 kb
Host smart-3f0be810-1fd3-4770-b422-b562ae0bd8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796105251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.796105251
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.741478504
Short name T733
Test name
Test status
Simulation time 361282453 ps
CPU time 4.14 seconds
Started Mar 23 03:59:23 PM PDT 24
Finished Mar 23 03:59:28 PM PDT 24
Peak memory 207984 kb
Host smart-d011057e-1511-45b9-960d-d5b0f38c86ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741478504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.741478504
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.571646920
Short name T12
Test name
Test status
Simulation time 3288980602 ps
CPU time 26.46 seconds
Started Mar 23 03:59:30 PM PDT 24
Finished Mar 23 03:59:57 PM PDT 24
Peak memory 243828 kb
Host smart-6282e02e-2cf9-41fc-bc36-da467f5209f8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571646920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.571646920
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1441927435
Short name T1066
Test name
Test status
Simulation time 115202107 ps
CPU time 3.08 seconds
Started Mar 23 03:59:29 PM PDT 24
Finished Mar 23 03:59:33 PM PDT 24
Peak memory 208424 kb
Host smart-9b68bcf9-9ae4-4e38-b677-ff86e37d6947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441927435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1441927435
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3841705756
Short name T972
Test name
Test status
Simulation time 254816904 ps
CPU time 6.72 seconds
Started Mar 23 03:59:25 PM PDT 24
Finished Mar 23 03:59:32 PM PDT 24
Peak memory 208672 kb
Host smart-c083b4be-8173-45a6-8474-cd3846e578a0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841705756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3841705756
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.4200388638
Short name T924
Test name
Test status
Simulation time 2377313745 ps
CPU time 40.09 seconds
Started Mar 23 03:59:21 PM PDT 24
Finished Mar 23 04:00:02 PM PDT 24
Peak memory 208440 kb
Host smart-6ffd4e67-7288-4cb1-8f54-4ca31bb92a67
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200388638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.4200388638
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.774386986
Short name T919
Test name
Test status
Simulation time 542455347 ps
CPU time 2.93 seconds
Started Mar 23 03:59:29 PM PDT 24
Finished Mar 23 03:59:33 PM PDT 24
Peak memory 206900 kb
Host smart-4929cfe4-9723-412e-9834-5c8743068ef7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774386986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.774386986
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1861969154
Short name T931
Test name
Test status
Simulation time 256212820 ps
CPU time 5.84 seconds
Started Mar 23 03:59:22 PM PDT 24
Finished Mar 23 03:59:28 PM PDT 24
Peak memory 208576 kb
Host smart-877a7bc7-ddc2-4a4a-b090-0e0626d33c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861969154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1861969154
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2008653998
Short name T945
Test name
Test status
Simulation time 2673499513 ps
CPU time 93.97 seconds
Started Mar 23 03:59:42 PM PDT 24
Finished Mar 23 04:01:16 PM PDT 24
Peak memory 222808 kb
Host smart-1e2d5493-488d-4bb4-aae0-f1c16b806590
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008653998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2008653998
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1458300719
Short name T821
Test name
Test status
Simulation time 817167000 ps
CPU time 12.73 seconds
Started Mar 23 03:59:31 PM PDT 24
Finished Mar 23 03:59:44 PM PDT 24
Peak memory 222648 kb
Host smart-1e9c0378-b51a-4068-b327-61a0103cb7d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458300719 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1458300719
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.75428190
Short name T1014
Test name
Test status
Simulation time 308052251 ps
CPU time 3.99 seconds
Started Mar 23 03:59:24 PM PDT 24
Finished Mar 23 03:59:28 PM PDT 24
Peak memory 210580 kb
Host smart-33920ae8-1b19-478d-b535-27257ae02b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75428190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.75428190
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3621773641
Short name T594
Test name
Test status
Simulation time 11450963 ps
CPU time 0.71 seconds
Started Mar 23 03:59:42 PM PDT 24
Finished Mar 23 03:59:44 PM PDT 24
Peak memory 206060 kb
Host smart-2cd17964-ce6f-4637-bcd5-1ba16689a487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621773641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3621773641
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.819207585
Short name T429
Test name
Test status
Simulation time 245383393 ps
CPU time 13.17 seconds
Started Mar 23 03:59:39 PM PDT 24
Finished Mar 23 03:59:54 PM PDT 24
Peak memory 215328 kb
Host smart-e4640341-0d69-4e38-8b3b-887357a94470
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=819207585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.819207585
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3839093869
Short name T718
Test name
Test status
Simulation time 1065796901 ps
CPU time 27.95 seconds
Started Mar 23 03:59:33 PM PDT 24
Finished Mar 23 04:00:01 PM PDT 24
Peak memory 222576 kb
Host smart-4f05b845-3a67-4c48-9996-585381b50bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839093869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3839093869
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2826275829
Short name T69
Test name
Test status
Simulation time 263531090 ps
CPU time 2.4 seconds
Started Mar 23 03:59:32 PM PDT 24
Finished Mar 23 03:59:34 PM PDT 24
Peak memory 207512 kb
Host smart-bb0b2462-3a6a-40a8-b725-d53b1b6ddfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826275829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2826275829
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.654686244
Short name T765
Test name
Test status
Simulation time 120740660 ps
CPU time 4.14 seconds
Started Mar 23 03:59:34 PM PDT 24
Finished Mar 23 03:59:38 PM PDT 24
Peak memory 209500 kb
Host smart-7e89f6f9-8b0c-40ee-aae8-4fe6775da25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654686244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.654686244
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3287377360
Short name T664
Test name
Test status
Simulation time 965522836 ps
CPU time 3.96 seconds
Started Mar 23 03:59:40 PM PDT 24
Finished Mar 23 03:59:45 PM PDT 24
Peak memory 209780 kb
Host smart-2e7cfeaa-2632-43b0-b056-1552e7c86cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287377360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3287377360
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2437411449
Short name T305
Test name
Test status
Simulation time 421209120 ps
CPU time 4.3 seconds
Started Mar 23 03:59:31 PM PDT 24
Finished Mar 23 03:59:36 PM PDT 24
Peak memory 220124 kb
Host smart-a898e38c-a01c-4321-a818-5e7ca3df05b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437411449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2437411449
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.608171008
Short name T995
Test name
Test status
Simulation time 51716596 ps
CPU time 3.33 seconds
Started Mar 23 03:59:34 PM PDT 24
Finished Mar 23 03:59:37 PM PDT 24
Peak memory 207528 kb
Host smart-ce2d2dda-86b5-4bcd-8e7b-c29f711f46f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608171008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.608171008
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.973556056
Short name T41
Test name
Test status
Simulation time 1201775258 ps
CPU time 27.8 seconds
Started Mar 23 03:59:39 PM PDT 24
Finished Mar 23 04:00:08 PM PDT 24
Peak memory 231896 kb
Host smart-1fd627db-4e12-4157-99da-2dd69bfceb05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973556056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.973556056
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3660348261
Short name T745
Test name
Test status
Simulation time 1352485963 ps
CPU time 7.57 seconds
Started Mar 23 03:59:31 PM PDT 24
Finished Mar 23 03:59:39 PM PDT 24
Peak memory 206860 kb
Host smart-b08ca7e3-d481-4a4f-a10f-a438dbf67489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660348261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3660348261
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3119568966
Short name T285
Test name
Test status
Simulation time 200713849 ps
CPU time 3.25 seconds
Started Mar 23 03:59:39 PM PDT 24
Finished Mar 23 03:59:44 PM PDT 24
Peak memory 208696 kb
Host smart-679ad996-db99-4136-b365-0f623c5f5335
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119568966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3119568966
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3764995012
Short name T832
Test name
Test status
Simulation time 1026839748 ps
CPU time 8.2 seconds
Started Mar 23 03:59:42 PM PDT 24
Finished Mar 23 03:59:50 PM PDT 24
Peak memory 208484 kb
Host smart-13c75fb9-5c2d-48c5-a0b5-25a78532aae1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764995012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3764995012
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3742931231
Short name T644
Test name
Test status
Simulation time 159508360 ps
CPU time 5.66 seconds
Started Mar 23 03:59:34 PM PDT 24
Finished Mar 23 03:59:40 PM PDT 24
Peak memory 207928 kb
Host smart-0d700cdc-b106-4979-8db8-ccd2dbdc5bb5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742931231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3742931231
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.308153760
Short name T790
Test name
Test status
Simulation time 675277527 ps
CPU time 4.91 seconds
Started Mar 23 03:59:37 PM PDT 24
Finished Mar 23 03:59:42 PM PDT 24
Peak memory 207476 kb
Host smart-364fd40f-1757-4aa9-be6c-fc7903735d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308153760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.308153760
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2918329462
Short name T1063
Test name
Test status
Simulation time 367242007 ps
CPU time 3.7 seconds
Started Mar 23 03:59:37 PM PDT 24
Finished Mar 23 03:59:41 PM PDT 24
Peak memory 208576 kb
Host smart-54add63a-2d0e-4841-91c6-a861eff8cf7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918329462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2918329462
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1493059650
Short name T841
Test name
Test status
Simulation time 11568111019 ps
CPU time 46.81 seconds
Started Mar 23 03:59:40 PM PDT 24
Finished Mar 23 04:00:28 PM PDT 24
Peak memory 222496 kb
Host smart-64a49976-707c-43f2-bf44-e63c79ed6d38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493059650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1493059650
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3000039719
Short name T81
Test name
Test status
Simulation time 466845702 ps
CPU time 4.09 seconds
Started Mar 23 03:59:39 PM PDT 24
Finished Mar 23 03:59:45 PM PDT 24
Peak memory 222692 kb
Host smart-287ce5a2-50c6-4dde-a5b5-120765132a0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000039719 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3000039719
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.55300235
Short name T677
Test name
Test status
Simulation time 532938091 ps
CPU time 16.32 seconds
Started Mar 23 03:59:30 PM PDT 24
Finished Mar 23 03:59:46 PM PDT 24
Peak memory 209236 kb
Host smart-615d19ea-36e8-4c12-a9eb-08b2746fc6df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55300235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.55300235
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3157686432
Short name T595
Test name
Test status
Simulation time 14225812 ps
CPU time 0.76 seconds
Started Mar 23 04:00:30 PM PDT 24
Finished Mar 23 04:00:31 PM PDT 24
Peak memory 205836 kb
Host smart-36fa710e-12e6-420a-84b1-fb71a642fb01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157686432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3157686432
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2370156411
Short name T922
Test name
Test status
Simulation time 75505812 ps
CPU time 3.53 seconds
Started Mar 23 04:00:24 PM PDT 24
Finished Mar 23 04:00:28 PM PDT 24
Peak memory 210024 kb
Host smart-1ea022a9-389e-4a1b-96ff-0e630b382a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370156411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2370156411
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1710700307
Short name T720
Test name
Test status
Simulation time 50621470 ps
CPU time 2.81 seconds
Started Mar 23 04:00:35 PM PDT 24
Finished Mar 23 04:00:39 PM PDT 24
Peak memory 215320 kb
Host smart-e081be4b-68c3-464f-a59f-124964179bac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710700307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1710700307
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1333226379
Short name T289
Test name
Test status
Simulation time 460387531 ps
CPU time 14.13 seconds
Started Mar 23 04:00:24 PM PDT 24
Finished Mar 23 04:00:38 PM PDT 24
Peak memory 207604 kb
Host smart-efcc751f-d71a-4e17-b388-c65215a12451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333226379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1333226379
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.417994309
Short name T1068
Test name
Test status
Simulation time 287163029 ps
CPU time 2.57 seconds
Started Mar 23 04:00:25 PM PDT 24
Finished Mar 23 04:00:27 PM PDT 24
Peak memory 206864 kb
Host smart-ddb95ab3-e792-493b-860b-e638693a33ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417994309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.417994309
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2513698826
Short name T900
Test name
Test status
Simulation time 632828547 ps
CPU time 4.17 seconds
Started Mar 23 04:00:26 PM PDT 24
Finished Mar 23 04:00:30 PM PDT 24
Peak memory 208764 kb
Host smart-c3836476-da17-409b-9e4b-d4cfcd3d3806
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513698826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2513698826
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.953316747
Short name T40
Test name
Test status
Simulation time 540324663 ps
CPU time 6.36 seconds
Started Mar 23 04:00:28 PM PDT 24
Finished Mar 23 04:00:35 PM PDT 24
Peak memory 208472 kb
Host smart-176bf04e-d4c4-4bfb-b7fe-a9cfad46c159
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953316747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.953316747
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1534313225
Short name T737
Test name
Test status
Simulation time 945402800 ps
CPU time 7.49 seconds
Started Mar 23 04:00:26 PM PDT 24
Finished Mar 23 04:00:34 PM PDT 24
Peak memory 208604 kb
Host smart-e2f62ed9-e6b1-4bc7-9ecd-6fb964aa08e6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534313225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1534313225
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.202163246
Short name T958
Test name
Test status
Simulation time 431949042 ps
CPU time 3.05 seconds
Started Mar 23 04:00:25 PM PDT 24
Finished Mar 23 04:00:28 PM PDT 24
Peak memory 215708 kb
Host smart-01c67db1-72e3-4d9d-98e6-b56c5fcbee77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202163246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.202163246
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.53250812
Short name T818
Test name
Test status
Simulation time 170675274 ps
CPU time 4.79 seconds
Started Mar 23 04:00:34 PM PDT 24
Finished Mar 23 04:00:40 PM PDT 24
Peak memory 208172 kb
Host smart-1a3229b6-52ef-48b8-b29b-6da8c5452171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53250812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.53250812
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.859733092
Short name T1023
Test name
Test status
Simulation time 1284450356 ps
CPU time 13.48 seconds
Started Mar 23 04:00:27 PM PDT 24
Finished Mar 23 04:00:41 PM PDT 24
Peak memory 222640 kb
Host smart-97a05a28-5af3-4323-99f2-fa7f71ce6620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859733092 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.859733092
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.690996116
Short name T102
Test name
Test status
Simulation time 292543613 ps
CPU time 8.28 seconds
Started Mar 23 04:00:21 PM PDT 24
Finished Mar 23 04:00:30 PM PDT 24
Peak memory 209264 kb
Host smart-2cb00c27-bb7a-4a88-aa89-02ad60a94cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690996116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.690996116
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3523013259
Short name T895
Test name
Test status
Simulation time 127766753 ps
CPU time 2.09 seconds
Started Mar 23 04:00:26 PM PDT 24
Finished Mar 23 04:00:28 PM PDT 24
Peak memory 210088 kb
Host smart-a82419b3-16d3-45ff-884f-97d8cd9e36c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523013259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3523013259
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2792200850
Short name T864
Test name
Test status
Simulation time 10937341 ps
CPU time 0.71 seconds
Started Mar 23 04:00:26 PM PDT 24
Finished Mar 23 04:00:27 PM PDT 24
Peak memory 205828 kb
Host smart-eee592a6-cb5a-414c-949f-053ebca08fa4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792200850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2792200850
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.787373161
Short name T1070
Test name
Test status
Simulation time 331940127 ps
CPU time 5.73 seconds
Started Mar 23 04:00:23 PM PDT 24
Finished Mar 23 04:00:29 PM PDT 24
Peak memory 214376 kb
Host smart-d96f730b-d464-483f-b3d9-d6265f9a4405
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=787373161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.787373161
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1762622977
Short name T869
Test name
Test status
Simulation time 294718388 ps
CPU time 3.85 seconds
Started Mar 23 04:00:24 PM PDT 24
Finished Mar 23 04:00:28 PM PDT 24
Peak memory 207936 kb
Host smart-505b74e3-ce74-4d4b-af7d-d612c81e12ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762622977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1762622977
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.568045545
Short name T386
Test name
Test status
Simulation time 88119534 ps
CPU time 3.07 seconds
Started Mar 23 04:00:25 PM PDT 24
Finished Mar 23 04:00:28 PM PDT 24
Peak memory 214256 kb
Host smart-9d313fcb-c0e3-4571-9229-72b499d435dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568045545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.568045545
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3286675599
Short name T48
Test name
Test status
Simulation time 82131397 ps
CPU time 2.71 seconds
Started Mar 23 04:00:26 PM PDT 24
Finished Mar 23 04:00:29 PM PDT 24
Peak memory 222484 kb
Host smart-d665da71-5358-4ec9-a47a-ac1cd367b9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286675599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3286675599
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1069723331
Short name T854
Test name
Test status
Simulation time 57384940 ps
CPU time 3.7 seconds
Started Mar 23 04:00:27 PM PDT 24
Finished Mar 23 04:00:31 PM PDT 24
Peak memory 210376 kb
Host smart-0b1ba68f-4108-4b4c-bd1d-1087c1bb5c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069723331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1069723331
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2177607373
Short name T1072
Test name
Test status
Simulation time 1407211004 ps
CPU time 9.18 seconds
Started Mar 23 04:00:25 PM PDT 24
Finished Mar 23 04:00:35 PM PDT 24
Peak memory 208724 kb
Host smart-c9ac17ec-bc4f-433a-8d06-637bea83dbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177607373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2177607373
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3618302847
Short name T804
Test name
Test status
Simulation time 258579314 ps
CPU time 3.5 seconds
Started Mar 23 04:00:24 PM PDT 24
Finished Mar 23 04:00:28 PM PDT 24
Peak memory 206904 kb
Host smart-edaf90d5-88fb-48e9-970c-a30e81bc6cf2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618302847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3618302847
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.4118332289
Short name T612
Test name
Test status
Simulation time 172774623 ps
CPU time 5.06 seconds
Started Mar 23 04:00:27 PM PDT 24
Finished Mar 23 04:00:32 PM PDT 24
Peak memory 208580 kb
Host smart-a53c466b-6210-4f5b-b642-592004358ed5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118332289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.4118332289
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3529110310
Short name T596
Test name
Test status
Simulation time 2321997814 ps
CPU time 53.03 seconds
Started Mar 23 04:00:25 PM PDT 24
Finished Mar 23 04:01:18 PM PDT 24
Peak memory 208476 kb
Host smart-09cdeffd-efc2-4d1d-ae8a-94553b33fff8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529110310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3529110310
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3701910797
Short name T811
Test name
Test status
Simulation time 3027127715 ps
CPU time 29.71 seconds
Started Mar 23 04:00:22 PM PDT 24
Finished Mar 23 04:00:52 PM PDT 24
Peak memory 214392 kb
Host smart-ede237b9-9338-4c3a-97ec-96cb61cfc5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701910797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3701910797
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3549657358
Short name T885
Test name
Test status
Simulation time 247131596 ps
CPU time 6.15 seconds
Started Mar 23 04:00:26 PM PDT 24
Finished Mar 23 04:00:33 PM PDT 24
Peak memory 208072 kb
Host smart-12acb6e0-52b8-4c07-8da5-4ee8d2aac092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549657358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3549657358
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.645210809
Short name T73
Test name
Test status
Simulation time 1170231520 ps
CPU time 23.27 seconds
Started Mar 23 04:00:26 PM PDT 24
Finished Mar 23 04:00:49 PM PDT 24
Peak memory 216884 kb
Host smart-ad12a2d8-265c-415f-994e-d4bb17e9c6ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645210809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.645210809
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3023236101
Short name T198
Test name
Test status
Simulation time 216505673 ps
CPU time 5.79 seconds
Started Mar 23 04:00:31 PM PDT 24
Finished Mar 23 04:00:37 PM PDT 24
Peak memory 222576 kb
Host smart-3fcea539-6613-449f-a720-1153266ac05a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023236101 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3023236101
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3347061485
Short name T333
Test name
Test status
Simulation time 345995036 ps
CPU time 4.73 seconds
Started Mar 23 04:00:24 PM PDT 24
Finished Mar 23 04:00:29 PM PDT 24
Peak memory 209916 kb
Host smart-d5e031b7-8010-49a6-99d8-f742b3f57b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347061485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3347061485
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2757681504
Short name T959
Test name
Test status
Simulation time 35843136677 ps
CPU time 145.97 seconds
Started Mar 23 04:00:28 PM PDT 24
Finished Mar 23 04:02:54 PM PDT 24
Peak memory 216724 kb
Host smart-5a4124ef-dc39-4265-ab81-6031054b5383
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2757681504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2757681504
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1063281889
Short name T599
Test name
Test status
Simulation time 351911728 ps
CPU time 4.98 seconds
Started Mar 23 04:00:22 PM PDT 24
Finished Mar 23 04:00:27 PM PDT 24
Peak memory 208616 kb
Host smart-25269dbf-8852-4de9-9b41-9baba2cd3877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063281889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1063281889
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2199944484
Short name T638
Test name
Test status
Simulation time 51669730 ps
CPU time 2.13 seconds
Started Mar 23 04:00:25 PM PDT 24
Finished Mar 23 04:00:28 PM PDT 24
Peak memory 218340 kb
Host smart-caeaa04a-a4f8-4dca-aa92-599d9c3d7780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199944484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2199944484
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2732930771
Short name T820
Test name
Test status
Simulation time 75895076 ps
CPU time 3.46 seconds
Started Mar 23 04:00:25 PM PDT 24
Finished Mar 23 04:00:28 PM PDT 24
Peak memory 208644 kb
Host smart-5fa516b0-3adb-42b7-b0f9-013033b00037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732930771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2732930771
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1949886817
Short name T697
Test name
Test status
Simulation time 409766030 ps
CPU time 4.88 seconds
Started Mar 23 04:00:25 PM PDT 24
Finished Mar 23 04:00:30 PM PDT 24
Peak memory 210256 kb
Host smart-bc5341a2-9dbb-46d4-8c67-70015aaa450b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949886817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1949886817
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3963363694
Short name T310
Test name
Test status
Simulation time 6004564852 ps
CPU time 37.38 seconds
Started Mar 23 04:00:27 PM PDT 24
Finished Mar 23 04:01:05 PM PDT 24
Peak memory 209284 kb
Host smart-b04b96fd-a3b8-4564-9127-4d92e5138f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963363694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3963363694
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2832674728
Short name T328
Test name
Test status
Simulation time 536989112 ps
CPU time 5.03 seconds
Started Mar 23 04:00:27 PM PDT 24
Finished Mar 23 04:00:33 PM PDT 24
Peak memory 208452 kb
Host smart-4a7b122f-e048-4c41-a21d-bcb1325cfaca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832674728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2832674728
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.78164770
Short name T762
Test name
Test status
Simulation time 149805565 ps
CPU time 3.72 seconds
Started Mar 23 04:00:23 PM PDT 24
Finished Mar 23 04:00:27 PM PDT 24
Peak memory 208692 kb
Host smart-babe45ea-086c-44f4-ae0b-535c431bab12
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78164770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.78164770
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.469043493
Short name T868
Test name
Test status
Simulation time 96402179 ps
CPU time 2.16 seconds
Started Mar 23 04:00:31 PM PDT 24
Finished Mar 23 04:00:33 PM PDT 24
Peak memory 206912 kb
Host smart-712da65b-271b-4735-bea8-8fabe90984a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469043493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.469043493
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1917021906
Short name T907
Test name
Test status
Simulation time 323901587 ps
CPU time 5.06 seconds
Started Mar 23 04:00:26 PM PDT 24
Finished Mar 23 04:00:31 PM PDT 24
Peak memory 208860 kb
Host smart-627fb614-1b0e-4f78-a1d5-132ebd4987f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917021906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1917021906
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.822093534
Short name T1027
Test name
Test status
Simulation time 587035792 ps
CPU time 2.43 seconds
Started Mar 23 04:00:26 PM PDT 24
Finished Mar 23 04:00:29 PM PDT 24
Peak memory 214332 kb
Host smart-32627445-4302-4f3a-aef8-26329d7d22a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822093534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.822093534
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3097733211
Short name T624
Test name
Test status
Simulation time 272416035 ps
CPU time 3.82 seconds
Started Mar 23 04:00:25 PM PDT 24
Finished Mar 23 04:00:29 PM PDT 24
Peak memory 206808 kb
Host smart-6c5eb959-a507-46b2-83a5-4ce1d1a490bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097733211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3097733211
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3389054380
Short name T290
Test name
Test status
Simulation time 458079508 ps
CPU time 18.24 seconds
Started Mar 23 04:00:38 PM PDT 24
Finished Mar 23 04:00:56 PM PDT 24
Peak memory 219064 kb
Host smart-e4815caf-3a2d-45fd-b7fd-b96333913f1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389054380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3389054380
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.496707196
Short name T974
Test name
Test status
Simulation time 150522375 ps
CPU time 4.13 seconds
Started Mar 23 04:00:34 PM PDT 24
Finished Mar 23 04:00:39 PM PDT 24
Peak memory 222736 kb
Host smart-1c805b5e-93fe-4129-addb-5a396acb6524
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496707196 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.496707196
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1724474252
Short name T794
Test name
Test status
Simulation time 42820462 ps
CPU time 2.47 seconds
Started Mar 23 04:00:34 PM PDT 24
Finished Mar 23 04:00:38 PM PDT 24
Peak memory 210248 kb
Host smart-8fed4353-48ed-453a-9892-24f4b85439b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724474252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1724474252
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1282956451
Short name T567
Test name
Test status
Simulation time 44667258 ps
CPU time 0.83 seconds
Started Mar 23 04:00:40 PM PDT 24
Finished Mar 23 04:00:41 PM PDT 24
Peak memory 205916 kb
Host smart-e85c52a0-34de-426e-b691-f4ac797018d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282956451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1282956451
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2229791719
Short name T417
Test name
Test status
Simulation time 209803500 ps
CPU time 4.07 seconds
Started Mar 23 04:00:34 PM PDT 24
Finished Mar 23 04:00:39 PM PDT 24
Peak memory 215676 kb
Host smart-1c3ea043-e023-4888-9da3-9d196c5b536e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2229791719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2229791719
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3298537528
Short name T63
Test name
Test status
Simulation time 1319794486 ps
CPU time 24.96 seconds
Started Mar 23 04:00:34 PM PDT 24
Finished Mar 23 04:01:00 PM PDT 24
Peak memory 208688 kb
Host smart-2ef09106-57a5-45c5-806b-e18bd11e3096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298537528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3298537528
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2416545916
Short name T988
Test name
Test status
Simulation time 95341505 ps
CPU time 4.58 seconds
Started Mar 23 04:00:35 PM PDT 24
Finished Mar 23 04:00:41 PM PDT 24
Peak memory 220448 kb
Host smart-c58ad573-8abe-45b1-9ca7-a786264b450f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416545916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2416545916
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1901879229
Short name T380
Test name
Test status
Simulation time 653160602 ps
CPU time 5.98 seconds
Started Mar 23 04:00:35 PM PDT 24
Finished Mar 23 04:00:42 PM PDT 24
Peak memory 222564 kb
Host smart-d5774a9b-6afa-49b1-a214-7f3b3d17e55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901879229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1901879229
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.601252176
Short name T756
Test name
Test status
Simulation time 119719630 ps
CPU time 3.13 seconds
Started Mar 23 04:00:35 PM PDT 24
Finished Mar 23 04:00:39 PM PDT 24
Peak memory 214400 kb
Host smart-edb9c11d-7979-476b-88e7-b6513b300ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601252176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.601252176
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_sideload.4194288180
Short name T1019
Test name
Test status
Simulation time 96552527 ps
CPU time 3.07 seconds
Started Mar 23 04:00:36 PM PDT 24
Finished Mar 23 04:00:39 PM PDT 24
Peak memory 206928 kb
Host smart-d1b6a7e8-2013-4be3-8603-d21d19151a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194288180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.4194288180
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3205903639
Short name T377
Test name
Test status
Simulation time 154965417 ps
CPU time 5.25 seconds
Started Mar 23 04:00:33 PM PDT 24
Finished Mar 23 04:00:39 PM PDT 24
Peak memory 206908 kb
Host smart-2df21ed9-d4dd-4c5c-a8d2-7bf55d24eb31
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205903639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3205903639
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2130158957
Short name T911
Test name
Test status
Simulation time 240656380 ps
CPU time 6.12 seconds
Started Mar 23 04:00:37 PM PDT 24
Finished Mar 23 04:00:43 PM PDT 24
Peak memory 208088 kb
Host smart-f0e420d0-4b94-4717-a92a-9be43300bcfc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130158957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2130158957
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3605310151
Short name T870
Test name
Test status
Simulation time 446304990 ps
CPU time 10.65 seconds
Started Mar 23 04:00:39 PM PDT 24
Finished Mar 23 04:00:49 PM PDT 24
Peak memory 208472 kb
Host smart-60044e4b-14f3-449c-9b98-77781127f6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605310151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3605310151
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2510540625
Short name T946
Test name
Test status
Simulation time 483596471 ps
CPU time 3.85 seconds
Started Mar 23 04:00:36 PM PDT 24
Finished Mar 23 04:00:40 PM PDT 24
Peak memory 206716 kb
Host smart-9a7710db-11a0-4c65-bb5d-43ca25d6b3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510540625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2510540625
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2236930220
Short name T301
Test name
Test status
Simulation time 109796382 ps
CPU time 5.06 seconds
Started Mar 23 04:00:44 PM PDT 24
Finished Mar 23 04:00:49 PM PDT 24
Peak memory 214956 kb
Host smart-349c5847-9eff-43a2-8ae7-35b1c6dc0b16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236930220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2236930220
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.267229753
Short name T200
Test name
Test status
Simulation time 377117687 ps
CPU time 6.63 seconds
Started Mar 23 04:00:37 PM PDT 24
Finished Mar 23 04:00:43 PM PDT 24
Peak memory 220144 kb
Host smart-9246e5be-30b1-4a88-a318-217f6dfd3a28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267229753 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.267229753
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2963193235
Short name T266
Test name
Test status
Simulation time 193231938 ps
CPU time 3.22 seconds
Started Mar 23 04:00:35 PM PDT 24
Finished Mar 23 04:00:39 PM PDT 24
Peak memory 207388 kb
Host smart-a5b506ff-e2e1-4130-92b5-032d05729792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963193235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2963193235
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1808804307
Short name T1050
Test name
Test status
Simulation time 491525487 ps
CPU time 3.88 seconds
Started Mar 23 04:00:35 PM PDT 24
Finished Mar 23 04:00:40 PM PDT 24
Peak memory 210548 kb
Host smart-c22ce9cc-2440-4b0d-ba3a-7923c09427ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808804307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1808804307
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.131300948
Short name T926
Test name
Test status
Simulation time 25964158 ps
CPU time 0.98 seconds
Started Mar 23 04:00:34 PM PDT 24
Finished Mar 23 04:00:37 PM PDT 24
Peak memory 206056 kb
Host smart-15ff576d-817c-4e5a-9fb5-a5f9483d15da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131300948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.131300948
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2228863684
Short name T408
Test name
Test status
Simulation time 167359118 ps
CPU time 9.4 seconds
Started Mar 23 04:00:40 PM PDT 24
Finished Mar 23 04:00:50 PM PDT 24
Peak memory 213884 kb
Host smart-0a3ff001-48f1-4bd3-8265-dfd7ed36b68d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2228863684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2228863684
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.893110610
Short name T753
Test name
Test status
Simulation time 604934500 ps
CPU time 3.6 seconds
Started Mar 23 04:00:35 PM PDT 24
Finished Mar 23 04:00:40 PM PDT 24
Peak memory 214352 kb
Host smart-84cbae54-d73e-4a3d-98df-992bc68dcc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893110610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.893110610
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3913652801
Short name T834
Test name
Test status
Simulation time 82028609 ps
CPU time 2.07 seconds
Started Mar 23 04:00:35 PM PDT 24
Finished Mar 23 04:00:38 PM PDT 24
Peak memory 207420 kb
Host smart-14dc3365-9b3d-4f52-b3b7-6006089420c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913652801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3913652801
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1429688691
Short name T88
Test name
Test status
Simulation time 190774917 ps
CPU time 5.08 seconds
Started Mar 23 04:00:38 PM PDT 24
Finished Mar 23 04:00:43 PM PDT 24
Peak memory 209844 kb
Host smart-cedf328e-000d-4d4b-be27-7a699f4078ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429688691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1429688691
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2199583152
Short name T50
Test name
Test status
Simulation time 1160258248 ps
CPU time 10.09 seconds
Started Mar 23 04:00:36 PM PDT 24
Finished Mar 23 04:00:47 PM PDT 24
Peak memory 214188 kb
Host smart-eeb29e1a-99fe-4882-89a6-d9a9e1cdedaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199583152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2199583152
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1024501096
Short name T391
Test name
Test status
Simulation time 106937502 ps
CPU time 4.49 seconds
Started Mar 23 04:00:34 PM PDT 24
Finished Mar 23 04:00:40 PM PDT 24
Peak memory 209372 kb
Host smart-d558df45-8639-49e5-a618-80807da5f4aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024501096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1024501096
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.49070256
Short name T619
Test name
Test status
Simulation time 63027065 ps
CPU time 3.85 seconds
Started Mar 23 04:00:37 PM PDT 24
Finished Mar 23 04:00:41 PM PDT 24
Peak memory 214312 kb
Host smart-0cc6f0f5-c5f2-4063-8cad-ac2648a55bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49070256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.49070256
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3724326682
Short name T774
Test name
Test status
Simulation time 47963950 ps
CPU time 1.88 seconds
Started Mar 23 04:00:34 PM PDT 24
Finished Mar 23 04:00:37 PM PDT 24
Peak memory 208580 kb
Host smart-2dc434fc-8995-43d5-9a1c-24b2fd469bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724326682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3724326682
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2603399367
Short name T747
Test name
Test status
Simulation time 86039756 ps
CPU time 4.47 seconds
Started Mar 23 04:00:39 PM PDT 24
Finished Mar 23 04:00:43 PM PDT 24
Peak memory 209080 kb
Host smart-8f2fa84a-4387-4404-a3ee-0abd6f4cc54e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603399367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2603399367
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1627015604
Short name T640
Test name
Test status
Simulation time 145378975 ps
CPU time 5.68 seconds
Started Mar 23 04:00:37 PM PDT 24
Finished Mar 23 04:00:42 PM PDT 24
Peak memory 208408 kb
Host smart-e4fe8697-453c-4126-bf4c-8979ed189966
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627015604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1627015604
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2223310912
Short name T1033
Test name
Test status
Simulation time 35746054 ps
CPU time 1.94 seconds
Started Mar 23 04:00:37 PM PDT 24
Finished Mar 23 04:00:40 PM PDT 24
Peak memory 206760 kb
Host smart-8057edae-9c8b-4fe3-99f2-9cbee46f82b8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223310912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2223310912
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2749766958
Short name T712
Test name
Test status
Simulation time 146852151 ps
CPU time 4 seconds
Started Mar 23 04:00:35 PM PDT 24
Finished Mar 23 04:00:40 PM PDT 24
Peak memory 208472 kb
Host smart-8463b006-5f71-43ef-9eeb-f026d4db417a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749766958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2749766958
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.4200924847
Short name T128
Test name
Test status
Simulation time 64170740 ps
CPU time 2.44 seconds
Started Mar 23 04:00:36 PM PDT 24
Finished Mar 23 04:00:39 PM PDT 24
Peak memory 207040 kb
Host smart-09555a0b-9745-4f64-a23b-873f959afc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200924847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.4200924847
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2957631873
Short name T588
Test name
Test status
Simulation time 184532273 ps
CPU time 5.35 seconds
Started Mar 23 04:00:37 PM PDT 24
Finished Mar 23 04:00:43 PM PDT 24
Peak memory 222544 kb
Host smart-5e8ec727-3f13-418b-866b-b0064a8885eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957631873 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2957631873
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2411239313
Short name T1047
Test name
Test status
Simulation time 6487729997 ps
CPU time 44.61 seconds
Started Mar 23 04:00:39 PM PDT 24
Finished Mar 23 04:01:24 PM PDT 24
Peak memory 208632 kb
Host smart-81237e7a-25d9-478a-94fb-b326b72dc58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411239313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2411239313
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.429731056
Short name T158
Test name
Test status
Simulation time 29814431 ps
CPU time 1.7 seconds
Started Mar 23 04:00:38 PM PDT 24
Finished Mar 23 04:00:40 PM PDT 24
Peak memory 209852 kb
Host smart-e0721ec8-329b-445f-8f1a-299d8042374c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429731056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.429731056
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.396743692
Short name T673
Test name
Test status
Simulation time 17126582 ps
CPU time 0.92 seconds
Started Mar 23 04:00:39 PM PDT 24
Finished Mar 23 04:00:40 PM PDT 24
Peak memory 206084 kb
Host smart-71e94788-f242-4360-ad98-3df93d582b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396743692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.396743692
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2381878504
Short name T67
Test name
Test status
Simulation time 4870882571 ps
CPU time 61.67 seconds
Started Mar 23 04:00:40 PM PDT 24
Finished Mar 23 04:01:42 PM PDT 24
Peak memory 208616 kb
Host smart-9138b50d-e336-4e70-ab43-59d3ded42743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381878504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2381878504
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2969652598
Short name T383
Test name
Test status
Simulation time 526277648 ps
CPU time 7.37 seconds
Started Mar 23 04:00:43 PM PDT 24
Finished Mar 23 04:00:50 PM PDT 24
Peak memory 214328 kb
Host smart-35c24459-aacf-4176-9f75-98fd5225ebb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969652598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2969652598
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2527848222
Short name T858
Test name
Test status
Simulation time 120731530 ps
CPU time 5.63 seconds
Started Mar 23 04:00:37 PM PDT 24
Finished Mar 23 04:00:43 PM PDT 24
Peak memory 214280 kb
Host smart-f3b349d2-4ab7-4c12-8304-9dffaddec8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527848222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2527848222
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.40028440
Short name T881
Test name
Test status
Simulation time 68537380 ps
CPU time 3.35 seconds
Started Mar 23 04:00:39 PM PDT 24
Finished Mar 23 04:00:42 PM PDT 24
Peak memory 209808 kb
Host smart-7dfc8865-78a2-46e2-8507-7a38c395ac26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40028440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.40028440
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.437055643
Short name T1037
Test name
Test status
Simulation time 236876659 ps
CPU time 5.82 seconds
Started Mar 23 04:00:39 PM PDT 24
Finished Mar 23 04:00:45 PM PDT 24
Peak memory 210432 kb
Host smart-381756e2-99ec-49b3-95f1-099eec1176fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437055643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.437055643
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1255741976
Short name T4
Test name
Test status
Simulation time 1694045005 ps
CPU time 32.75 seconds
Started Mar 23 04:00:37 PM PDT 24
Finished Mar 23 04:01:10 PM PDT 24
Peak memory 208540 kb
Host smart-b2db4ecb-bf23-4088-99b2-ed0c01d46091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255741976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1255741976
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3841628525
Short name T633
Test name
Test status
Simulation time 256963460 ps
CPU time 3.55 seconds
Started Mar 23 04:00:38 PM PDT 24
Finished Mar 23 04:00:42 PM PDT 24
Peak memory 208888 kb
Host smart-93651714-b3fd-4420-bced-b86014025ead
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841628525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3841628525
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1692592207
Short name T1040
Test name
Test status
Simulation time 135552166 ps
CPU time 2.2 seconds
Started Mar 23 04:00:37 PM PDT 24
Finished Mar 23 04:00:40 PM PDT 24
Peak memory 208824 kb
Host smart-496ea984-df4b-47a8-947f-73d08ebc82d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692592207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1692592207
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.781219821
Short name T886
Test name
Test status
Simulation time 288186357 ps
CPU time 3.18 seconds
Started Mar 23 04:00:36 PM PDT 24
Finished Mar 23 04:00:40 PM PDT 24
Peak memory 207136 kb
Host smart-52d2bab7-8992-4a7a-9a0a-2cf5aeac00c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781219821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.781219821
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2986522024
Short name T300
Test name
Test status
Simulation time 3797171756 ps
CPU time 23.75 seconds
Started Mar 23 04:00:36 PM PDT 24
Finished Mar 23 04:01:00 PM PDT 24
Peak memory 218520 kb
Host smart-aa415167-f256-414d-8e5c-421aa645c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986522024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2986522024
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2734497252
Short name T914
Test name
Test status
Simulation time 1476706832 ps
CPU time 3.62 seconds
Started Mar 23 04:00:40 PM PDT 24
Finished Mar 23 04:00:43 PM PDT 24
Peak memory 208696 kb
Host smart-9a562049-5d1a-4211-a1f7-1d537160b5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734497252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2734497252
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1259369802
Short name T341
Test name
Test status
Simulation time 1749269387 ps
CPU time 45.2 seconds
Started Mar 23 04:00:43 PM PDT 24
Finished Mar 23 04:01:28 PM PDT 24
Peak memory 222508 kb
Host smart-2a2453f0-efea-4b63-9c58-4fa094c71176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259369802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1259369802
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.970478571
Short name T230
Test name
Test status
Simulation time 142938751 ps
CPU time 8.24 seconds
Started Mar 23 04:00:43 PM PDT 24
Finished Mar 23 04:00:51 PM PDT 24
Peak memory 223548 kb
Host smart-cbf5d66a-7244-47e2-ab42-019a97e64959
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970478571 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.970478571
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.157797524
Short name T335
Test name
Test status
Simulation time 2699869037 ps
CPU time 16.61 seconds
Started Mar 23 04:00:36 PM PDT 24
Finished Mar 23 04:00:53 PM PDT 24
Peak memory 214360 kb
Host smart-d173860e-aa18-43d5-b8ec-de98c57cf3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157797524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.157797524
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1672543447
Short name T607
Test name
Test status
Simulation time 1060348630 ps
CPU time 8.22 seconds
Started Mar 23 04:00:40 PM PDT 24
Finished Mar 23 04:00:48 PM PDT 24
Peak memory 211276 kb
Host smart-bcce1fcf-31ed-448a-b25f-926199a661ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672543447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1672543447
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.4200356539
Short name T576
Test name
Test status
Simulation time 56457247 ps
CPU time 0.87 seconds
Started Mar 23 04:00:43 PM PDT 24
Finished Mar 23 04:00:43 PM PDT 24
Peak memory 205812 kb
Host smart-3f3280bb-87c2-4082-995c-da4c8d71a5d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200356539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.4200356539
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.356359810
Short name T788
Test name
Test status
Simulation time 476631774 ps
CPU time 1.97 seconds
Started Mar 23 04:00:45 PM PDT 24
Finished Mar 23 04:00:48 PM PDT 24
Peak memory 207828 kb
Host smart-7fb7885e-156d-4961-9947-4d37d1ee0cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356359810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.356359810
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2304786426
Short name T937
Test name
Test status
Simulation time 1064192236 ps
CPU time 25.61 seconds
Started Mar 23 04:00:46 PM PDT 24
Finished Mar 23 04:01:11 PM PDT 24
Peak memory 220244 kb
Host smart-bdfd5214-9c8c-43bc-a2ec-c3af3e0afa1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304786426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2304786426
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.662855871
Short name T295
Test name
Test status
Simulation time 560350587 ps
CPU time 8.67 seconds
Started Mar 23 04:00:46 PM PDT 24
Finished Mar 23 04:00:55 PM PDT 24
Peak memory 214272 kb
Host smart-7c39cee2-a704-4e66-a176-1b592631a2d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662855871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.662855871
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.86186972
Short name T830
Test name
Test status
Simulation time 136843322 ps
CPU time 3.8 seconds
Started Mar 23 04:00:43 PM PDT 24
Finished Mar 23 04:00:47 PM PDT 24
Peak memory 209408 kb
Host smart-66880f02-e18f-4af8-a2fe-4619d84e658a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86186972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.86186972
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3398532840
Short name T807
Test name
Test status
Simulation time 84192213 ps
CPU time 4.66 seconds
Started Mar 23 04:00:41 PM PDT 24
Finished Mar 23 04:00:46 PM PDT 24
Peak memory 208816 kb
Host smart-55eae6f2-e48f-4784-b24f-797dc35e1eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398532840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3398532840
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1669951426
Short name T360
Test name
Test status
Simulation time 196359760 ps
CPU time 3.01 seconds
Started Mar 23 04:00:44 PM PDT 24
Finished Mar 23 04:00:47 PM PDT 24
Peak memory 209016 kb
Host smart-0f1488fb-a709-47ef-93bc-bf5fb78f748f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669951426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1669951426
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.487524837
Short name T758
Test name
Test status
Simulation time 230799224 ps
CPU time 4.31 seconds
Started Mar 23 04:00:40 PM PDT 24
Finished Mar 23 04:00:45 PM PDT 24
Peak memory 208628 kb
Host smart-069ef9d7-c8f6-4891-92e6-0d85cc33c984
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487524837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.487524837
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1369996957
Short name T866
Test name
Test status
Simulation time 90287447 ps
CPU time 3.87 seconds
Started Mar 23 04:00:36 PM PDT 24
Finished Mar 23 04:00:40 PM PDT 24
Peak memory 208852 kb
Host smart-6b8b6f31-de82-489b-82c1-a2c2fb1e12d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369996957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1369996957
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3928913212
Short name T1035
Test name
Test status
Simulation time 108763009 ps
CPU time 4.29 seconds
Started Mar 23 04:00:39 PM PDT 24
Finished Mar 23 04:00:44 PM PDT 24
Peak memory 208900 kb
Host smart-b2c92298-4f85-4844-b83f-297b34cde5c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928913212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3928913212
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2405434723
Short name T802
Test name
Test status
Simulation time 155084389 ps
CPU time 4.15 seconds
Started Mar 23 04:00:39 PM PDT 24
Finished Mar 23 04:00:43 PM PDT 24
Peak memory 208872 kb
Host smart-93ceb534-0737-462a-9c42-0287610ec259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405434723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2405434723
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2311440893
Short name T1039
Test name
Test status
Simulation time 102314027 ps
CPU time 3.11 seconds
Started Mar 23 04:00:36 PM PDT 24
Finished Mar 23 04:00:39 PM PDT 24
Peak memory 206884 kb
Host smart-77992663-9263-44e2-b184-c70cccb59302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311440893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2311440893
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3141404077
Short name T217
Test name
Test status
Simulation time 9365617418 ps
CPU time 211.83 seconds
Started Mar 23 04:00:44 PM PDT 24
Finished Mar 23 04:04:16 PM PDT 24
Peak memory 220992 kb
Host smart-77824d40-61ba-411f-b756-6a9cf9534fd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141404077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3141404077
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.2882998501
Short name T650
Test name
Test status
Simulation time 298869618 ps
CPU time 3.31 seconds
Started Mar 23 04:00:43 PM PDT 24
Finished Mar 23 04:00:47 PM PDT 24
Peak memory 222780 kb
Host smart-417fac9c-db77-4f69-aa20-af9a9d6b1a8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882998501 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.2882998501
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.625479864
Short name T348
Test name
Test status
Simulation time 333432665 ps
CPU time 9.43 seconds
Started Mar 23 04:00:46 PM PDT 24
Finished Mar 23 04:00:55 PM PDT 24
Peak memory 209204 kb
Host smart-611863a6-888e-41e7-b524-1acfc8c6d48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625479864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.625479864
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.891483712
Short name T645
Test name
Test status
Simulation time 24149282 ps
CPU time 0.8 seconds
Started Mar 23 04:00:52 PM PDT 24
Finished Mar 23 04:00:53 PM PDT 24
Peak memory 205912 kb
Host smart-0725d3a5-b279-4b3c-aa0a-aee5eaa824d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891483712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.891483712
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.240306846
Short name T1030
Test name
Test status
Simulation time 217557422 ps
CPU time 3.92 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:53 PM PDT 24
Peak memory 216968 kb
Host smart-eb607b78-e42e-46c4-a2f5-1997e707d657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240306846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.240306846
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1460561334
Short name T890
Test name
Test status
Simulation time 1394869678 ps
CPU time 41.93 seconds
Started Mar 23 04:00:50 PM PDT 24
Finished Mar 23 04:01:32 PM PDT 24
Peak memory 208092 kb
Host smart-c20f3edd-8b57-47c4-a996-573de3fc803e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460561334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1460561334
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3833396899
Short name T256
Test name
Test status
Simulation time 224733599 ps
CPU time 5.59 seconds
Started Mar 23 04:00:47 PM PDT 24
Finished Mar 23 04:00:53 PM PDT 24
Peak memory 214268 kb
Host smart-6071a08b-0783-4ffe-b72f-2b842a1a1a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833396899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3833396899
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1111923720
Short name T201
Test name
Test status
Simulation time 197622078 ps
CPU time 4.3 seconds
Started Mar 23 04:00:51 PM PDT 24
Finished Mar 23 04:00:55 PM PDT 24
Peak memory 222492 kb
Host smart-7ad210ed-4839-440d-92bb-39eadc7f6fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111923720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1111923720
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1860525728
Short name T246
Test name
Test status
Simulation time 1201403869 ps
CPU time 6.26 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:55 PM PDT 24
Peak memory 214296 kb
Host smart-4b6d17fc-53bb-4c78-8fc1-e117716cdb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860525728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1860525728
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2340419181
Short name T637
Test name
Test status
Simulation time 394982908 ps
CPU time 3.67 seconds
Started Mar 23 04:00:47 PM PDT 24
Finished Mar 23 04:00:51 PM PDT 24
Peak memory 206968 kb
Host smart-d1e9b1de-9da5-4a79-8bb6-abe3ce78cd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340419181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2340419181
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1975441013
Short name T963
Test name
Test status
Simulation time 394321537 ps
CPU time 3.96 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:52 PM PDT 24
Peak memory 208588 kb
Host smart-803b30c3-321a-4a46-a8e6-e5ecbc3633be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975441013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1975441013
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1502602746
Short name T243
Test name
Test status
Simulation time 3855017216 ps
CPU time 53.26 seconds
Started Mar 23 04:00:49 PM PDT 24
Finished Mar 23 04:01:42 PM PDT 24
Peak memory 207996 kb
Host smart-d9f74d7b-1edf-400d-a7a7-73a8a1e12235
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502602746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1502602746
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1289427033
Short name T627
Test name
Test status
Simulation time 401630528 ps
CPU time 7.41 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:55 PM PDT 24
Peak memory 208764 kb
Host smart-2a6e5ea9-1827-4b63-b928-f0c49ace1ca7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289427033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1289427033
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1595745410
Short name T364
Test name
Test status
Simulation time 83796179 ps
CPU time 4.17 seconds
Started Mar 23 04:00:52 PM PDT 24
Finished Mar 23 04:00:56 PM PDT 24
Peak memory 209120 kb
Host smart-cb07d1c5-da65-4c6f-9331-0e23ce7bf5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595745410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1595745410
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3541706819
Short name T603
Test name
Test status
Simulation time 207738221 ps
CPU time 3.04 seconds
Started Mar 23 04:00:49 PM PDT 24
Finished Mar 23 04:00:52 PM PDT 24
Peak memory 208588 kb
Host smart-46e3b3b2-29ae-4076-848e-4480a13f7edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541706819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3541706819
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.735259686
Short name T309
Test name
Test status
Simulation time 885639233 ps
CPU time 7.51 seconds
Started Mar 23 04:00:51 PM PDT 24
Finished Mar 23 04:00:58 PM PDT 24
Peak memory 206880 kb
Host smart-aeca3e79-2033-4c2e-bb2f-223e782a247e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735259686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.735259686
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3045466669
Short name T980
Test name
Test status
Simulation time 191521464 ps
CPU time 2.23 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:51 PM PDT 24
Peak memory 214504 kb
Host smart-14cbb47a-9847-4244-8b9c-94ff173ff731
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045466669 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3045466669
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.598349553
Short name T913
Test name
Test status
Simulation time 82536028 ps
CPU time 4.3 seconds
Started Mar 23 04:00:49 PM PDT 24
Finished Mar 23 04:00:53 PM PDT 24
Peak memory 207380 kb
Host smart-e660e821-49b6-4109-a37e-a4b9cb00b61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598349553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.598349553
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2870342160
Short name T658
Test name
Test status
Simulation time 448062513 ps
CPU time 3.44 seconds
Started Mar 23 04:00:55 PM PDT 24
Finished Mar 23 04:00:58 PM PDT 24
Peak memory 210696 kb
Host smart-d294b71a-62c0-4c60-ae23-c9c9633e9afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870342160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2870342160
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2918046293
Short name T1006
Test name
Test status
Simulation time 22477254 ps
CPU time 0.8 seconds
Started Mar 23 04:00:47 PM PDT 24
Finished Mar 23 04:00:48 PM PDT 24
Peak memory 205844 kb
Host smart-c63c11f9-5c5e-419f-b642-76d37b10dc4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918046293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2918046293
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1564821361
Short name T422
Test name
Test status
Simulation time 63293783 ps
CPU time 2.55 seconds
Started Mar 23 04:00:51 PM PDT 24
Finished Mar 23 04:00:54 PM PDT 24
Peak memory 214312 kb
Host smart-f9dbf16d-47de-40c5-a852-02c803bc1052
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1564821361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1564821361
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2017084791
Short name T815
Test name
Test status
Simulation time 71031431 ps
CPU time 1.84 seconds
Started Mar 23 04:00:55 PM PDT 24
Finished Mar 23 04:00:56 PM PDT 24
Peak memory 206892 kb
Host smart-fa4b8df2-69f3-4be4-b3f3-8c48f7636e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017084791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2017084791
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3966473791
Short name T1010
Test name
Test status
Simulation time 1342539271 ps
CPU time 9.67 seconds
Started Mar 23 04:00:46 PM PDT 24
Finished Mar 23 04:00:57 PM PDT 24
Peak memory 209280 kb
Host smart-667ad5f9-da79-4486-b940-128baa1a3b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966473791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3966473791
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1838478054
Short name T1058
Test name
Test status
Simulation time 321303133 ps
CPU time 6.96 seconds
Started Mar 23 04:00:52 PM PDT 24
Finished Mar 23 04:00:59 PM PDT 24
Peak memory 214344 kb
Host smart-54791e8b-ae42-4b58-baf2-140a38255798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838478054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1838478054
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3977101066
Short name T226
Test name
Test status
Simulation time 325054130 ps
CPU time 7.93 seconds
Started Mar 23 04:00:44 PM PDT 24
Finished Mar 23 04:00:52 PM PDT 24
Peak memory 218444 kb
Host smart-3f972f53-8618-4502-b9aa-74483890650a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977101066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3977101066
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1605732858
Short name T716
Test name
Test status
Simulation time 44823033 ps
CPU time 2.61 seconds
Started Mar 23 04:00:46 PM PDT 24
Finished Mar 23 04:00:49 PM PDT 24
Peak memory 208368 kb
Host smart-6fa2521e-8255-40f3-98d9-4095fd4325d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605732858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1605732858
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1999611382
Short name T15
Test name
Test status
Simulation time 197478998 ps
CPU time 3.05 seconds
Started Mar 23 04:00:51 PM PDT 24
Finished Mar 23 04:00:54 PM PDT 24
Peak memory 206860 kb
Host smart-3925fdfd-c19b-4d98-9da1-9b335ff741d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999611382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1999611382
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1230874625
Short name T750
Test name
Test status
Simulation time 298277041 ps
CPU time 3.73 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:52 PM PDT 24
Peak memory 208544 kb
Host smart-ab78dc86-a397-401c-881f-5f3e460040db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230874625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1230874625
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.674906495
Short name T782
Test name
Test status
Simulation time 52832705 ps
CPU time 2.87 seconds
Started Mar 23 04:00:51 PM PDT 24
Finished Mar 23 04:00:54 PM PDT 24
Peak memory 206848 kb
Host smart-2d967e60-cd92-4b4a-bc0c-a559347b69eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674906495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.674906495
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1410477710
Short name T625
Test name
Test status
Simulation time 61410249 ps
CPU time 1.57 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:51 PM PDT 24
Peak memory 206964 kb
Host smart-bf69f158-7e54-46aa-bd72-fd3142338169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410477710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1410477710
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1425880481
Short name T754
Test name
Test status
Simulation time 916227727 ps
CPU time 7.38 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:55 PM PDT 24
Peak memory 206864 kb
Host smart-4cd59ec9-a419-45d6-9898-835a070cb0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425880481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1425880481
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.737419954
Short name T690
Test name
Test status
Simulation time 432623325 ps
CPU time 9.94 seconds
Started Mar 23 04:00:50 PM PDT 24
Finished Mar 23 04:01:00 PM PDT 24
Peak memory 218160 kb
Host smart-95921b4a-49e4-4316-b8a7-2ea740984fe9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737419954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.737419954
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2324928208
Short name T421
Test name
Test status
Simulation time 578982835 ps
CPU time 3.76 seconds
Started Mar 23 04:00:47 PM PDT 24
Finished Mar 23 04:00:51 PM PDT 24
Peak memory 222724 kb
Host smart-99ba9de6-509c-49a6-a8f6-132b51aa3b74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324928208 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2324928208
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2638602491
Short name T378
Test name
Test status
Simulation time 640173523 ps
CPU time 8.5 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:58 PM PDT 24
Peak memory 209128 kb
Host smart-6f158a69-8d61-4b17-815d-fa55c081f18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638602491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2638602491
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.795747178
Short name T160
Test name
Test status
Simulation time 54482571 ps
CPU time 2.54 seconds
Started Mar 23 04:00:49 PM PDT 24
Finished Mar 23 04:00:52 PM PDT 24
Peak memory 210064 kb
Host smart-1d248959-05ba-4c25-8709-0a4a4f1740d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795747178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.795747178
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.177248079
Short name T696
Test name
Test status
Simulation time 230085701 ps
CPU time 1.08 seconds
Started Mar 23 04:00:52 PM PDT 24
Finished Mar 23 04:00:54 PM PDT 24
Peak memory 206108 kb
Host smart-571f56c5-5178-4fd2-90f6-d8473c4a4aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177248079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.177248079
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3306370187
Short name T842
Test name
Test status
Simulation time 588503088 ps
CPU time 7.94 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:56 PM PDT 24
Peak memory 221412 kb
Host smart-62cbe080-cd86-4e02-a6b7-af2644692bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306370187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3306370187
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.974464765
Short name T797
Test name
Test status
Simulation time 204367271 ps
CPU time 2.71 seconds
Started Mar 23 04:00:50 PM PDT 24
Finished Mar 23 04:00:53 PM PDT 24
Peak memory 207892 kb
Host smart-2de225a8-f42c-4654-9d66-69ba73053cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974464765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.974464765
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2806462906
Short name T701
Test name
Test status
Simulation time 359782080 ps
CPU time 10.33 seconds
Started Mar 23 04:00:49 PM PDT 24
Finished Mar 23 04:00:59 PM PDT 24
Peak memory 214500 kb
Host smart-dc9b7fad-a4b8-4d5e-b1e3-358ef4ca9464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806462906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2806462906
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.4168792849
Short name T847
Test name
Test status
Simulation time 124591961 ps
CPU time 5.83 seconds
Started Mar 23 04:01:08 PM PDT 24
Finished Mar 23 04:01:14 PM PDT 24
Peak memory 220228 kb
Host smart-f7fc54b2-d4e5-4fcf-9f6b-eb98e285971d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168792849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4168792849
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.907597829
Short name T646
Test name
Test status
Simulation time 165316201 ps
CPU time 4.93 seconds
Started Mar 23 04:00:46 PM PDT 24
Finished Mar 23 04:00:52 PM PDT 24
Peak memory 208344 kb
Host smart-0d31c83d-5c25-48c3-b739-f39491acbbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907597829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.907597829
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1061347311
Short name T688
Test name
Test status
Simulation time 100715169 ps
CPU time 2.65 seconds
Started Mar 23 04:00:44 PM PDT 24
Finished Mar 23 04:00:47 PM PDT 24
Peak memory 206836 kb
Host smart-179c8e05-7fff-4798-bb8b-3cfda896c5ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061347311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1061347311
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1171642441
Short name T987
Test name
Test status
Simulation time 67307429 ps
CPU time 3.42 seconds
Started Mar 23 04:00:50 PM PDT 24
Finished Mar 23 04:00:53 PM PDT 24
Peak memory 209056 kb
Host smart-4160f9a2-19a0-42d6-a7c2-9b1efe0e28c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171642441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1171642441
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1596734586
Short name T783
Test name
Test status
Simulation time 221679561 ps
CPU time 3.34 seconds
Started Mar 23 04:00:46 PM PDT 24
Finished Mar 23 04:00:50 PM PDT 24
Peak memory 208864 kb
Host smart-03040095-63b2-44a5-95c0-67f1079762dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596734586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1596734586
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2603094835
Short name T962
Test name
Test status
Simulation time 573255338 ps
CPU time 4.81 seconds
Started Mar 23 04:00:49 PM PDT 24
Finished Mar 23 04:00:54 PM PDT 24
Peak memory 208564 kb
Host smart-40bf5ced-e0d4-4604-99fc-730db37f557f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603094835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2603094835
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3525009067
Short name T957
Test name
Test status
Simulation time 81478129 ps
CPU time 2.26 seconds
Started Mar 23 04:00:51 PM PDT 24
Finished Mar 23 04:00:53 PM PDT 24
Peak memory 214252 kb
Host smart-dbbe7cb2-f2d5-4e19-931f-da13a7d7fa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525009067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3525009067
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2940539633
Short name T942
Test name
Test status
Simulation time 436268131 ps
CPU time 4.28 seconds
Started Mar 23 04:00:50 PM PDT 24
Finished Mar 23 04:00:55 PM PDT 24
Peak memory 208572 kb
Host smart-989ca204-320e-4213-b304-a4f2c95e76a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940539633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2940539633
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3802382136
Short name T245
Test name
Test status
Simulation time 732175274 ps
CPU time 5.83 seconds
Started Mar 23 04:00:47 PM PDT 24
Finished Mar 23 04:00:53 PM PDT 24
Peak memory 208044 kb
Host smart-0fb1c1c5-d015-4b1a-aa2c-41ef8454e543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802382136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3802382136
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3856427770
Short name T564
Test name
Test status
Simulation time 11940401 ps
CPU time 0.83 seconds
Started Mar 23 03:59:44 PM PDT 24
Finished Mar 23 03:59:46 PM PDT 24
Peak memory 205912 kb
Host smart-8154a419-1ab5-4e94-90a0-93c95f3b0586
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856427770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3856427770
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3676805190
Short name T251
Test name
Test status
Simulation time 171206646 ps
CPU time 3.13 seconds
Started Mar 23 03:59:46 PM PDT 24
Finished Mar 23 03:59:50 PM PDT 24
Peak memory 214304 kb
Host smart-3a40955e-9012-4c9f-9d7f-5cdfed137896
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3676805190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3676805190
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1821402221
Short name T281
Test name
Test status
Simulation time 63802936 ps
CPU time 3.11 seconds
Started Mar 23 03:59:47 PM PDT 24
Finished Mar 23 03:59:50 PM PDT 24
Peak memory 208708 kb
Host smart-df10acf4-1691-4139-8c7d-4dcf35b656b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821402221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1821402221
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.1426361203
Short name T1005
Test name
Test status
Simulation time 85432856 ps
CPU time 3.76 seconds
Started Mar 23 03:59:44 PM PDT 24
Finished Mar 23 03:59:49 PM PDT 24
Peak memory 214320 kb
Host smart-7579e743-345e-464e-8685-758a8b07c64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426361203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.1426361203
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_random.518633045
Short name T713
Test name
Test status
Simulation time 239075097 ps
CPU time 7.52 seconds
Started Mar 23 03:59:46 PM PDT 24
Finished Mar 23 03:59:54 PM PDT 24
Peak memory 207816 kb
Host smart-d84b9619-b396-4b21-9a87-3fde73c45393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518633045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.518633045
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.4229656232
Short name T11
Test name
Test status
Simulation time 287415677 ps
CPU time 10.11 seconds
Started Mar 23 03:59:45 PM PDT 24
Finished Mar 23 03:59:56 PM PDT 24
Peak memory 233700 kb
Host smart-36c361d7-2663-46af-a8b7-3b6bf94dada9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229656232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.4229656232
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2294072096
Short name T318
Test name
Test status
Simulation time 2277857085 ps
CPU time 32.39 seconds
Started Mar 23 03:59:42 PM PDT 24
Finished Mar 23 04:00:16 PM PDT 24
Peak memory 208680 kb
Host smart-f8f63449-9c0b-444f-9a81-dd2867ffe6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294072096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2294072096
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.98538152
Short name T775
Test name
Test status
Simulation time 163078415 ps
CPU time 5.65 seconds
Started Mar 23 03:59:37 PM PDT 24
Finished Mar 23 03:59:43 PM PDT 24
Peak memory 208492 kb
Host smart-f355ba6f-1bbe-495c-afdc-20462f7b82ac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98538152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.98538152
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.4135874702
Short name T894
Test name
Test status
Simulation time 104327376 ps
CPU time 3.57 seconds
Started Mar 23 03:59:39 PM PDT 24
Finished Mar 23 03:59:45 PM PDT 24
Peak memory 206676 kb
Host smart-625cfdfc-340a-4c24-9ed6-407d031a7ccf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135874702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4135874702
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2082612526
Short name T730
Test name
Test status
Simulation time 77476216 ps
CPU time 1.85 seconds
Started Mar 23 03:59:47 PM PDT 24
Finished Mar 23 03:59:49 PM PDT 24
Peak memory 206936 kb
Host smart-aa1edf17-59ea-4da7-b13d-dd666a730419
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082612526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2082612526
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1445331087
Short name T629
Test name
Test status
Simulation time 45350290 ps
CPU time 2.31 seconds
Started Mar 23 03:59:45 PM PDT 24
Finished Mar 23 03:59:48 PM PDT 24
Peak memory 216076 kb
Host smart-12e5860c-2550-4c16-ba32-2e68bac54bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445331087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1445331087
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1868247621
Short name T749
Test name
Test status
Simulation time 3864439961 ps
CPU time 22.38 seconds
Started Mar 23 03:59:37 PM PDT 24
Finished Mar 23 04:00:00 PM PDT 24
Peak memory 208400 kb
Host smart-96950c7d-c521-4d4e-9af3-5d794c17c79b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868247621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1868247621
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2300906922
Short name T727
Test name
Test status
Simulation time 4599830734 ps
CPU time 46.41 seconds
Started Mar 23 03:59:44 PM PDT 24
Finished Mar 23 04:00:32 PM PDT 24
Peak memory 217184 kb
Host smart-f746ecfa-64cb-44c1-984b-455143339a99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300906922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2300906922
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.826091127
Short name T793
Test name
Test status
Simulation time 98782021 ps
CPU time 4.38 seconds
Started Mar 23 03:59:47 PM PDT 24
Finished Mar 23 03:59:52 PM PDT 24
Peak memory 222688 kb
Host smart-0a97a9c6-a42b-4886-9c44-a9448cf42252
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826091127 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.826091127
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.781367013
Short name T220
Test name
Test status
Simulation time 323828333 ps
CPU time 7.14 seconds
Started Mar 23 03:59:47 PM PDT 24
Finished Mar 23 03:59:54 PM PDT 24
Peak memory 218380 kb
Host smart-58f055ef-02b1-4162-a239-43d2c027f623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781367013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.781367013
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3789944495
Short name T714
Test name
Test status
Simulation time 490184682 ps
CPU time 3.27 seconds
Started Mar 23 03:59:45 PM PDT 24
Finished Mar 23 03:59:49 PM PDT 24
Peak memory 210548 kb
Host smart-c9c8385e-4b75-424d-a0d8-3428949ff5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789944495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3789944495
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1469922594
Short name T581
Test name
Test status
Simulation time 46172591 ps
CPU time 0.96 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:49 PM PDT 24
Peak memory 206028 kb
Host smart-30215524-ba74-4486-b646-67cbc05e3996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469922594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1469922594
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2396372577
Short name T343
Test name
Test status
Simulation time 118979374 ps
CPU time 6.8 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:56 PM PDT 24
Peak memory 215396 kb
Host smart-1cb6c843-1047-4bcd-8c9b-f389e38e7df0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2396372577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2396372577
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1410294113
Short name T780
Test name
Test status
Simulation time 270495678 ps
CPU time 3.36 seconds
Started Mar 23 04:00:49 PM PDT 24
Finished Mar 23 04:00:52 PM PDT 24
Peak memory 216676 kb
Host smart-8e49e46b-4733-45a2-80ea-d90ed5318b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410294113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1410294113
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4154920698
Short name T44
Test name
Test status
Simulation time 144027341 ps
CPU time 2.19 seconds
Started Mar 23 04:00:44 PM PDT 24
Finished Mar 23 04:00:47 PM PDT 24
Peak memory 207240 kb
Host smart-c6bf42e2-5ec0-443c-abbf-a08e8f0b42a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154920698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4154920698
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2918239380
Short name T83
Test name
Test status
Simulation time 16108400817 ps
CPU time 25.36 seconds
Started Mar 23 04:00:52 PM PDT 24
Finished Mar 23 04:01:18 PM PDT 24
Peak memory 221536 kb
Host smart-e7b6e29f-ba51-463e-af74-387dc36aae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918239380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2918239380
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3062509104
Short name T732
Test name
Test status
Simulation time 621803854 ps
CPU time 6.61 seconds
Started Mar 23 04:00:52 PM PDT 24
Finished Mar 23 04:00:59 PM PDT 24
Peak memory 214204 kb
Host smart-91bd0da8-309f-4d15-8f0f-baecd9cfb3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062509104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3062509104
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_random.1984110549
Short name T861
Test name
Test status
Simulation time 8905799214 ps
CPU time 20.41 seconds
Started Mar 23 04:00:49 PM PDT 24
Finished Mar 23 04:01:10 PM PDT 24
Peak memory 208096 kb
Host smart-64ac5f37-a216-48d3-bc79-6c422301b42d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984110549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1984110549
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.556074469
Short name T566
Test name
Test status
Simulation time 338803181 ps
CPU time 3.75 seconds
Started Mar 23 04:00:50 PM PDT 24
Finished Mar 23 04:00:53 PM PDT 24
Peak memory 208496 kb
Host smart-a0f6dfcf-d2a2-41f5-adba-43f4d289e9d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556074469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.556074469
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.4254763429
Short name T981
Test name
Test status
Simulation time 86506551 ps
CPU time 3.39 seconds
Started Mar 23 04:00:54 PM PDT 24
Finished Mar 23 04:00:57 PM PDT 24
Peak memory 208632 kb
Host smart-6428cf86-eb24-4b33-b76f-78865137b490
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254763429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4254763429
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1553774759
Short name T674
Test name
Test status
Simulation time 9160682109 ps
CPU time 40.51 seconds
Started Mar 23 04:00:50 PM PDT 24
Finished Mar 23 04:01:30 PM PDT 24
Peak memory 208180 kb
Host smart-86fa3fe1-4b77-4648-9f15-c29992e4d9de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553774759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1553774759
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1255269408
Short name T354
Test name
Test status
Simulation time 351634899 ps
CPU time 3.44 seconds
Started Mar 23 04:00:49 PM PDT 24
Finished Mar 23 04:00:53 PM PDT 24
Peak memory 209988 kb
Host smart-3d6fbfb9-7231-47c5-a5fb-134f97987534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255269408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1255269408
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.4039960683
Short name T665
Test name
Test status
Simulation time 137646251 ps
CPU time 1.76 seconds
Started Mar 23 04:00:51 PM PDT 24
Finished Mar 23 04:00:53 PM PDT 24
Peak memory 207016 kb
Host smart-d3f75097-96a8-4c3b-8ae6-b47ce7592b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039960683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.4039960683
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.3986265660
Short name T760
Test name
Test status
Simulation time 443010167 ps
CPU time 2.71 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:52 PM PDT 24
Peak memory 218232 kb
Host smart-325b73b7-66d6-47d8-9ff1-c956195ab282
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986265660 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.3986265660
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2110542949
Short name T916
Test name
Test status
Simulation time 535816440 ps
CPU time 7.84 seconds
Started Mar 23 04:00:51 PM PDT 24
Finished Mar 23 04:00:59 PM PDT 24
Peak memory 209024 kb
Host smart-442fef51-57c9-4d8a-a085-27d96a706dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110542949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2110542949
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.925972959
Short name T711
Test name
Test status
Simulation time 129193574 ps
CPU time 2.66 seconds
Started Mar 23 04:00:49 PM PDT 24
Finished Mar 23 04:00:52 PM PDT 24
Peak memory 210464 kb
Host smart-e9f3b867-7f88-4da8-86e1-b905386b73c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925972959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.925972959
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1885888179
Short name T719
Test name
Test status
Simulation time 18957606 ps
CPU time 0.9 seconds
Started Mar 23 04:01:04 PM PDT 24
Finished Mar 23 04:01:06 PM PDT 24
Peak memory 205916 kb
Host smart-b6c214bc-e7ac-47c2-aa68-2df602fa43b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885888179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1885888179
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1185399324
Short name T381
Test name
Test status
Simulation time 51145320 ps
CPU time 4.01 seconds
Started Mar 23 04:01:10 PM PDT 24
Finished Mar 23 04:01:14 PM PDT 24
Peak memory 214324 kb
Host smart-c709e135-e294-44f5-a506-bb89bcce6ef4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1185399324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1185399324
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3451349406
Short name T825
Test name
Test status
Simulation time 7963108058 ps
CPU time 13.22 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:17 PM PDT 24
Peak memory 222960 kb
Host smart-f62f754a-a91b-44d8-8d75-5c99886fe98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451349406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3451349406
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3611278945
Short name T844
Test name
Test status
Simulation time 238169724 ps
CPU time 3.17 seconds
Started Mar 23 04:01:04 PM PDT 24
Finished Mar 23 04:01:08 PM PDT 24
Peak memory 219476 kb
Host smart-00e1de1c-aa77-4176-b67f-ab99cf55efac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611278945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3611278945
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2755467578
Short name T89
Test name
Test status
Simulation time 222051714 ps
CPU time 7.17 seconds
Started Mar 23 04:01:02 PM PDT 24
Finished Mar 23 04:01:10 PM PDT 24
Peak memory 220668 kb
Host smart-c0845b2b-f38d-4cff-b22d-7eae2763a35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755467578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2755467578
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1508265978
Short name T240
Test name
Test status
Simulation time 424647697 ps
CPU time 3.53 seconds
Started Mar 23 04:01:04 PM PDT 24
Finished Mar 23 04:01:09 PM PDT 24
Peak memory 214512 kb
Host smart-99092779-5d14-4aae-9a60-40c49fddc1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508265978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1508265978
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3583719221
Short name T597
Test name
Test status
Simulation time 98268918 ps
CPU time 4.35 seconds
Started Mar 23 04:01:02 PM PDT 24
Finished Mar 23 04:01:07 PM PDT 24
Peak memory 209304 kb
Host smart-d7e35c10-d9e1-4494-8812-4f387b84143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583719221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3583719221
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.4041749453
Short name T631
Test name
Test status
Simulation time 81252303 ps
CPU time 2.91 seconds
Started Mar 23 04:00:53 PM PDT 24
Finished Mar 23 04:00:56 PM PDT 24
Peak memory 206804 kb
Host smart-be6ffd68-2f2d-4bbf-b99b-239f756a5b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041749453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.4041749453
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.152065665
Short name T971
Test name
Test status
Simulation time 1429224744 ps
CPU time 9.94 seconds
Started Mar 23 04:00:48 PM PDT 24
Finished Mar 23 04:00:59 PM PDT 24
Peak memory 207956 kb
Host smart-5c5912f1-6ab2-499e-8eb5-24cbbc036636
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152065665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.152065665
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2213243219
Short name T778
Test name
Test status
Simulation time 347309556 ps
CPU time 11.11 seconds
Started Mar 23 04:00:49 PM PDT 24
Finished Mar 23 04:01:00 PM PDT 24
Peak memory 208960 kb
Host smart-857e26b9-3eca-4e3b-b915-b27b310fa94b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213243219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2213243219
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1223627209
Short name T602
Test name
Test status
Simulation time 203111960 ps
CPU time 3.38 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:08 PM PDT 24
Peak memory 208524 kb
Host smart-0630c370-8083-427c-902e-0d30d281e171
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223627209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1223627209
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3745312692
Short name T609
Test name
Test status
Simulation time 205307820 ps
CPU time 4.31 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:09 PM PDT 24
Peak memory 210200 kb
Host smart-b31389a1-0184-4356-8645-bae94be94cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745312692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3745312692
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.101038520
Short name T724
Test name
Test status
Simulation time 2663494576 ps
CPU time 27.15 seconds
Started Mar 23 04:00:51 PM PDT 24
Finished Mar 23 04:01:18 PM PDT 24
Peak memory 208544 kb
Host smart-f0bf3da8-c4c4-47ad-af1b-24a6d0810dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101038520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.101038520
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1093959582
Short name T339
Test name
Test status
Simulation time 2710144007 ps
CPU time 7.27 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:11 PM PDT 24
Peak memory 209880 kb
Host smart-c123274e-07c7-46dd-9145-845361acefef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093959582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1093959582
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.4047581292
Short name T888
Test name
Test status
Simulation time 297873781 ps
CPU time 15.34 seconds
Started Mar 23 04:00:59 PM PDT 24
Finished Mar 23 04:01:15 PM PDT 24
Peak memory 222812 kb
Host smart-420de8e1-9113-4614-8865-d00dfe817a4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047581292 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.4047581292
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.488963481
Short name T419
Test name
Test status
Simulation time 94386433 ps
CPU time 4.1 seconds
Started Mar 23 04:01:07 PM PDT 24
Finished Mar 23 04:01:11 PM PDT 24
Peak memory 210048 kb
Host smart-7dd7d3d7-8929-4047-ae7a-acd5db3a5699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488963481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.488963481
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3806973881
Short name T36
Test name
Test status
Simulation time 529210050 ps
CPU time 3.98 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:08 PM PDT 24
Peak memory 219300 kb
Host smart-d78cdfd7-d09c-4a2c-83a7-0ae1908da855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806973881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3806973881
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3188908031
Short name T966
Test name
Test status
Simulation time 27803391 ps
CPU time 0.9 seconds
Started Mar 23 04:01:06 PM PDT 24
Finished Mar 23 04:01:07 PM PDT 24
Peak memory 206024 kb
Host smart-fb964207-7e13-4aa8-9a04-dbaf7ee5e283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188908031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3188908031
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3095971995
Short name T967
Test name
Test status
Simulation time 45569092 ps
CPU time 3.21 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:08 PM PDT 24
Peak memory 215560 kb
Host smart-a905a133-8e53-4d92-9fa6-984f60bb5b2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3095971995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3095971995
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2122130923
Short name T10
Test name
Test status
Simulation time 137666886 ps
CPU time 2.63 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:07 PM PDT 24
Peak memory 214748 kb
Host smart-a30c75db-61bb-4b9b-beea-49a94c64aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122130923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2122130923
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3117926919
Short name T770
Test name
Test status
Simulation time 36772768 ps
CPU time 1.94 seconds
Started Mar 23 04:01:04 PM PDT 24
Finished Mar 23 04:01:07 PM PDT 24
Peak memory 208620 kb
Host smart-9e35d440-fd5f-43ab-bb07-b24dbc310837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117926919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3117926919
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3008827589
Short name T84
Test name
Test status
Simulation time 185159260 ps
CPU time 5.91 seconds
Started Mar 23 04:01:02 PM PDT 24
Finished Mar 23 04:01:09 PM PDT 24
Peak memory 209164 kb
Host smart-e22b4a1a-28ea-49a1-b2d0-469a34a57a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008827589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3008827589
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2826252791
Short name T292
Test name
Test status
Simulation time 49984000 ps
CPU time 3.1 seconds
Started Mar 23 04:01:02 PM PDT 24
Finished Mar 23 04:01:06 PM PDT 24
Peak memory 210660 kb
Host smart-7fd0febe-ce55-46b7-bb7c-e4d9b295733b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826252791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2826252791
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1525649887
Short name T948
Test name
Test status
Simulation time 68523107 ps
CPU time 3.74 seconds
Started Mar 23 04:01:05 PM PDT 24
Finished Mar 23 04:01:10 PM PDT 24
Peak memory 209940 kb
Host smart-ddfbe91c-2a69-4e30-9873-7c714c7245e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525649887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1525649887
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.4289540448
Short name T598
Test name
Test status
Simulation time 130747660 ps
CPU time 4.89 seconds
Started Mar 23 04:01:06 PM PDT 24
Finished Mar 23 04:01:11 PM PDT 24
Peak memory 214372 kb
Host smart-78aeffcf-9e8e-46ed-93d3-dca80a78fbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289540448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.4289540448
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3845137197
Short name T1011
Test name
Test status
Simulation time 59185430 ps
CPU time 2.45 seconds
Started Mar 23 04:00:59 PM PDT 24
Finished Mar 23 04:01:03 PM PDT 24
Peak memory 206932 kb
Host smart-9792c742-0aa8-4fe1-bdab-8eaadf453163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845137197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3845137197
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.499209290
Short name T657
Test name
Test status
Simulation time 7206748205 ps
CPU time 47.69 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:52 PM PDT 24
Peak memory 208496 kb
Host smart-198c1c8b-2295-4a15-966d-70662f3b6135
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499209290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.499209290
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3914094610
Short name T927
Test name
Test status
Simulation time 241799904 ps
CPU time 9.53 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:14 PM PDT 24
Peak memory 208728 kb
Host smart-2c20c815-bf9e-41e3-b22e-6faad718f997
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914094610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3914094610
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3785684789
Short name T734
Test name
Test status
Simulation time 75821617 ps
CPU time 2.51 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:07 PM PDT 24
Peak memory 206900 kb
Host smart-dbc3e49c-7472-4a83-8aa6-f730d0bab2f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785684789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3785684789
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.298434907
Short name T189
Test name
Test status
Simulation time 1475373638 ps
CPU time 32.75 seconds
Started Mar 23 04:01:02 PM PDT 24
Finished Mar 23 04:01:36 PM PDT 24
Peak memory 208716 kb
Host smart-80a4e9a0-bae4-40ea-80a2-1283a0e7b4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298434907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.298434907
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.4293242925
Short name T614
Test name
Test status
Simulation time 189667667 ps
CPU time 2.64 seconds
Started Mar 23 04:00:59 PM PDT 24
Finished Mar 23 04:01:04 PM PDT 24
Peak memory 206788 kb
Host smart-b655e2a8-ff27-4c3f-a560-5a5066eefa10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293242925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.4293242925
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3481119748
Short name T589
Test name
Test status
Simulation time 32985356 ps
CPU time 2.43 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:07 PM PDT 24
Peak memory 207732 kb
Host smart-a59e534f-34d0-4fab-a36d-5b7c74036937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481119748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3481119748
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.644865679
Short name T591
Test name
Test status
Simulation time 452127411 ps
CPU time 3.41 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:08 PM PDT 24
Peak memory 210616 kb
Host smart-f4eb3ad6-fa5a-4c43-a9b2-f473d20983a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644865679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.644865679
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.996106271
Short name T568
Test name
Test status
Simulation time 11740359 ps
CPU time 0.75 seconds
Started Mar 23 04:01:04 PM PDT 24
Finished Mar 23 04:01:06 PM PDT 24
Peak memory 205876 kb
Host smart-4988142b-f372-4013-8987-cfad9417ceda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996106271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.996106271
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.4225093358
Short name T406
Test name
Test status
Simulation time 6305151905 ps
CPU time 84.12 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:02:28 PM PDT 24
Peak memory 215224 kb
Host smart-ca8e85cb-01d1-482f-9472-d70c003e1f4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4225093358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4225093358
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2899821993
Short name T878
Test name
Test status
Simulation time 314624724 ps
CPU time 3.36 seconds
Started Mar 23 04:01:02 PM PDT 24
Finished Mar 23 04:01:06 PM PDT 24
Peak memory 209412 kb
Host smart-714f0a41-7027-4595-bba9-4747a210a9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899821993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2899821993
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1869372335
Short name T833
Test name
Test status
Simulation time 795464796 ps
CPU time 4.8 seconds
Started Mar 23 04:01:10 PM PDT 24
Finished Mar 23 04:01:15 PM PDT 24
Peak memory 214404 kb
Host smart-0230c315-3051-46bb-94be-fb12a5ec074b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869372335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1869372335
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.396955397
Short name T801
Test name
Test status
Simulation time 177620283 ps
CPU time 7 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:11 PM PDT 24
Peak memory 222520 kb
Host smart-2d4fc790-c315-4438-b3f6-8abfe6569c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396955397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.396955397
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1058138118
Short name T49
Test name
Test status
Simulation time 546776165 ps
CPU time 4.79 seconds
Started Mar 23 04:01:02 PM PDT 24
Finished Mar 23 04:01:08 PM PDT 24
Peak memory 209780 kb
Host smart-8f99e542-9997-40f9-9720-77f7776d027e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058138118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1058138118
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2346109240
Short name T222
Test name
Test status
Simulation time 678423340 ps
CPU time 9.25 seconds
Started Mar 23 04:01:07 PM PDT 24
Finished Mar 23 04:01:16 PM PDT 24
Peak memory 214416 kb
Host smart-27207ef7-3992-46aa-a40c-7dabdf8fc47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346109240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2346109240
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2451124249
Short name T1057
Test name
Test status
Simulation time 3496881734 ps
CPU time 11.72 seconds
Started Mar 23 04:01:01 PM PDT 24
Finished Mar 23 04:01:15 PM PDT 24
Peak memory 207952 kb
Host smart-97661fe5-5685-4af9-be52-aedd284f2b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451124249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2451124249
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.322956467
Short name T671
Test name
Test status
Simulation time 124026728 ps
CPU time 3.34 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:08 PM PDT 24
Peak memory 206980 kb
Host smart-79480f43-d77c-48fe-a992-a8380434d23d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322956467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.322956467
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.507139501
Short name T682
Test name
Test status
Simulation time 287160565 ps
CPU time 8.5 seconds
Started Mar 23 04:01:02 PM PDT 24
Finished Mar 23 04:01:12 PM PDT 24
Peak memory 208812 kb
Host smart-6f5715ec-b28d-40c9-88e5-06fb5f5e1201
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507139501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.507139501
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.401346644
Short name T337
Test name
Test status
Simulation time 3374642770 ps
CPU time 33.97 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:38 PM PDT 24
Peak memory 208308 kb
Host smart-20ee252d-b055-4027-9146-dbdffcfb2f1a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401346644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.401346644
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1393432127
Short name T420
Test name
Test status
Simulation time 223721946 ps
CPU time 3 seconds
Started Mar 23 04:01:01 PM PDT 24
Finished Mar 23 04:01:06 PM PDT 24
Peak memory 208252 kb
Host smart-8eec10ca-f607-4487-875e-ad4dd71aeb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393432127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1393432127
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2191036566
Short name T721
Test name
Test status
Simulation time 544649539 ps
CPU time 3.94 seconds
Started Mar 23 04:01:02 PM PDT 24
Finished Mar 23 04:01:07 PM PDT 24
Peak memory 208488 kb
Host smart-97f120c5-2957-48ca-92d3-d80f09dafef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191036566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2191036566
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2263538646
Short name T1017
Test name
Test status
Simulation time 705305348 ps
CPU time 11.02 seconds
Started Mar 23 04:01:08 PM PDT 24
Finished Mar 23 04:01:19 PM PDT 24
Peak memory 215528 kb
Host smart-35176daa-eb12-4fb8-ae8c-d64222f3430c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263538646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2263538646
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.419242109
Short name T928
Test name
Test status
Simulation time 943414478 ps
CPU time 9.79 seconds
Started Mar 23 04:01:05 PM PDT 24
Finished Mar 23 04:01:16 PM PDT 24
Peak memory 222628 kb
Host smart-dbccf7ad-9945-405e-abe5-e13cef9a34b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419242109 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.419242109
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.956415950
Short name T78
Test name
Test status
Simulation time 109683472 ps
CPU time 4.42 seconds
Started Mar 23 04:01:01 PM PDT 24
Finished Mar 23 04:01:07 PM PDT 24
Peak memory 214432 kb
Host smart-b04bb09f-9fa8-4ed3-9442-c4abdc2aeafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956415950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.956415950
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2456889435
Short name T683
Test name
Test status
Simulation time 66920333 ps
CPU time 2.31 seconds
Started Mar 23 04:01:04 PM PDT 24
Finished Mar 23 04:01:08 PM PDT 24
Peak memory 214352 kb
Host smart-62959e1e-8814-4d23-b89d-68c8a8f88e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456889435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2456889435
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2034358887
Short name T565
Test name
Test status
Simulation time 11177001 ps
CPU time 0.9 seconds
Started Mar 23 04:01:21 PM PDT 24
Finished Mar 23 04:01:22 PM PDT 24
Peak memory 205856 kb
Host smart-d742f1f1-b53e-4e0d-a330-c59331b5ba8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034358887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2034358887
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.2212915141
Short name T423
Test name
Test status
Simulation time 243293283 ps
CPU time 4.17 seconds
Started Mar 23 04:01:03 PM PDT 24
Finished Mar 23 04:01:08 PM PDT 24
Peak memory 215028 kb
Host smart-24636df9-ebf8-47ca-95a7-bade6c3e5d41
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2212915141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2212915141
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.4035379693
Short name T859
Test name
Test status
Simulation time 188561927 ps
CPU time 5.99 seconds
Started Mar 23 04:01:04 PM PDT 24
Finished Mar 23 04:01:11 PM PDT 24
Peak memory 209572 kb
Host smart-ba944a65-f009-4bab-a5b5-304b9af58c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035379693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.4035379693
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2635691522
Short name T856
Test name
Test status
Simulation time 166287864 ps
CPU time 1.98 seconds
Started Mar 23 04:01:07 PM PDT 24
Finished Mar 23 04:01:09 PM PDT 24
Peak memory 207124 kb
Host smart-f9578158-a851-4063-aa77-5a10ee58bf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635691522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2635691522
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3361518312
Short name T1048
Test name
Test status
Simulation time 1278888094 ps
CPU time 9.01 seconds
Started Mar 23 04:01:04 PM PDT 24
Finished Mar 23 04:01:14 PM PDT 24
Peak memory 214344 kb
Host smart-f31efd02-c80a-4f2c-b5fa-f554afdc348f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361518312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3361518312
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2813257487
Short name T353
Test name
Test status
Simulation time 45388403 ps
CPU time 3.3 seconds
Started Mar 23 04:01:05 PM PDT 24
Finished Mar 23 04:01:10 PM PDT 24
Peak memory 211048 kb
Host smart-3ac8bc5c-6af3-4e93-a4dd-e8f4671817fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813257487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2813257487
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.4157341751
Short name T953
Test name
Test status
Simulation time 436437232 ps
CPU time 5.15 seconds
Started Mar 23 04:01:05 PM PDT 24
Finished Mar 23 04:01:11 PM PDT 24
Peak memory 216304 kb
Host smart-c2020669-ab11-4153-b844-8d88b2481e56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157341751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.4157341751
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2521121482
Short name T853
Test name
Test status
Simulation time 387390116 ps
CPU time 4.9 seconds
Started Mar 23 04:01:10 PM PDT 24
Finished Mar 23 04:01:15 PM PDT 24
Peak memory 207140 kb
Host smart-17b7e5c1-db30-48cf-8257-6a01f5c35d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521121482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2521121482
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.4035501464
Short name T1038
Test name
Test status
Simulation time 1863629234 ps
CPU time 4.64 seconds
Started Mar 23 04:01:06 PM PDT 24
Finished Mar 23 04:01:11 PM PDT 24
Peak memory 208904 kb
Host smart-66f5d25a-efdd-4f3b-ba43-9f320131bcd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035501464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.4035501464
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3346209067
Short name T686
Test name
Test status
Simulation time 306084674 ps
CPU time 3.15 seconds
Started Mar 23 04:01:02 PM PDT 24
Finished Mar 23 04:01:06 PM PDT 24
Peak memory 206896 kb
Host smart-459e6fa2-aa62-46a8-8f97-c50902cb467f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346209067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3346209067
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1102808913
Short name T903
Test name
Test status
Simulation time 909585403 ps
CPU time 4.71 seconds
Started Mar 23 04:01:04 PM PDT 24
Finished Mar 23 04:01:11 PM PDT 24
Peak memory 206752 kb
Host smart-b6cc7b18-1859-4841-877e-8df7f5238f7b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102808913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1102808913
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1525354415
Short name T921
Test name
Test status
Simulation time 2490268267 ps
CPU time 9.62 seconds
Started Mar 23 04:01:05 PM PDT 24
Finished Mar 23 04:01:15 PM PDT 24
Peak memory 208772 kb
Host smart-8ffe9875-0ef8-4527-822d-69740505e137
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525354415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1525354415
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.346339307
Short name T1031
Test name
Test status
Simulation time 217316974 ps
CPU time 3.24 seconds
Started Mar 23 04:01:10 PM PDT 24
Finished Mar 23 04:01:14 PM PDT 24
Peak memory 209224 kb
Host smart-4c4fabb1-9d34-4076-8050-1ff1310fd11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346339307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.346339307
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.168908100
Short name T398
Test name
Test status
Simulation time 312018643 ps
CPU time 6.66 seconds
Started Mar 23 04:01:02 PM PDT 24
Finished Mar 23 04:01:10 PM PDT 24
Peak memory 208516 kb
Host smart-22aa8d4c-4034-436d-a0ef-df325d6179a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168908100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.168908100
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.9802088
Short name T260
Test name
Test status
Simulation time 3384128440 ps
CPU time 32.01 seconds
Started Mar 23 04:01:10 PM PDT 24
Finished Mar 23 04:01:42 PM PDT 24
Peak memory 217048 kb
Host smart-6cd18c01-56ad-4728-ae54-40a532281cc3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9802088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.9802088
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2803453031
Short name T998
Test name
Test status
Simulation time 184065502 ps
CPU time 7.91 seconds
Started Mar 23 04:01:00 PM PDT 24
Finished Mar 23 04:01:09 PM PDT 24
Peak memory 220868 kb
Host smart-a5b850f2-fada-4b9d-8a1d-ac33a92a1d3c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803453031 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2803453031
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.771151135
Short name T723
Test name
Test status
Simulation time 1522736556 ps
CPU time 6.81 seconds
Started Mar 23 04:01:05 PM PDT 24
Finished Mar 23 04:01:13 PM PDT 24
Peak memory 207556 kb
Host smart-22fda338-ba3b-49d6-bb79-6395e852089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771151135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.771151135
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2717279184
Short name T944
Test name
Test status
Simulation time 27300001 ps
CPU time 0.92 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:23 PM PDT 24
Peak memory 205920 kb
Host smart-465dfd67-c428-418b-8a06-cf6e74888065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717279184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2717279184
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.167422481
Short name T75
Test name
Test status
Simulation time 129628613 ps
CPU time 2.91 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:25 PM PDT 24
Peak memory 214320 kb
Host smart-b94c92a3-b653-42d2-a968-12eac7c0c1b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=167422481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.167422481
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2724675947
Short name T28
Test name
Test status
Simulation time 173095980 ps
CPU time 2.36 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:24 PM PDT 24
Peak memory 214308 kb
Host smart-b0bf309f-b577-42c0-9fb9-7c3bc2982114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724675947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2724675947
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.182586652
Short name T748
Test name
Test status
Simulation time 52119060 ps
CPU time 2.66 seconds
Started Mar 23 04:01:21 PM PDT 24
Finished Mar 23 04:01:23 PM PDT 24
Peak memory 207492 kb
Host smart-269d0df4-e60d-4664-9173-070d205a35e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182586652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.182586652
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1209748521
Short name T92
Test name
Test status
Simulation time 648391788 ps
CPU time 3.91 seconds
Started Mar 23 04:01:21 PM PDT 24
Finished Mar 23 04:01:25 PM PDT 24
Peak memory 208608 kb
Host smart-d87c78bc-a618-46ea-9489-a8287a0252df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209748521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1209748521
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.2775470957
Short name T275
Test name
Test status
Simulation time 54093081 ps
CPU time 3.28 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:26 PM PDT 24
Peak memory 210604 kb
Host smart-09db7b53-ccbe-4b5c-990a-18f7304a7bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775470957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.2775470957
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1519638895
Short name T52
Test name
Test status
Simulation time 157667472 ps
CPU time 3.86 seconds
Started Mar 23 04:01:26 PM PDT 24
Finished Mar 23 04:01:30 PM PDT 24
Peak memory 222528 kb
Host smart-8e0de3cf-4036-4d2a-a55a-2a20d4cbb2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519638895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1519638895
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3162699493
Short name T123
Test name
Test status
Simulation time 199729644 ps
CPU time 6 seconds
Started Mar 23 04:01:25 PM PDT 24
Finished Mar 23 04:01:31 PM PDT 24
Peak memory 214320 kb
Host smart-6b780026-02de-4cda-a255-863328c8675e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162699493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3162699493
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.492101375
Short name T577
Test name
Test status
Simulation time 1513609931 ps
CPU time 4.96 seconds
Started Mar 23 04:01:21 PM PDT 24
Finished Mar 23 04:01:26 PM PDT 24
Peak memory 206808 kb
Host smart-804c6152-ba57-4843-82ba-11e0fdeefb2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492101375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.492101375
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3630821390
Short name T743
Test name
Test status
Simulation time 3496723445 ps
CPU time 26.58 seconds
Started Mar 23 04:01:20 PM PDT 24
Finished Mar 23 04:01:47 PM PDT 24
Peak memory 208336 kb
Host smart-6e2944cd-fd32-490d-8de3-f55010cc6528
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630821390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3630821390
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2048198405
Short name T1054
Test name
Test status
Simulation time 6844584192 ps
CPU time 49.83 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:02:12 PM PDT 24
Peak memory 208852 kb
Host smart-3d9441d8-da3d-4c1b-9e3f-0e2d1e662b1e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048198405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2048198405
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.937700885
Short name T622
Test name
Test status
Simulation time 377951747 ps
CPU time 6.98 seconds
Started Mar 23 04:01:23 PM PDT 24
Finished Mar 23 04:01:30 PM PDT 24
Peak memory 207988 kb
Host smart-bef69ae9-3e9b-4607-b964-11d582d59cef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937700885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.937700885
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.157693965
Short name T317
Test name
Test status
Simulation time 101489776 ps
CPU time 2.2 seconds
Started Mar 23 04:01:20 PM PDT 24
Finished Mar 23 04:01:22 PM PDT 24
Peak memory 209260 kb
Host smart-37d5e232-df24-4eb1-8941-f60374e682ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157693965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.157693965
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2542681165
Short name T127
Test name
Test status
Simulation time 66134958 ps
CPU time 3.28 seconds
Started Mar 23 04:01:21 PM PDT 24
Finished Mar 23 04:01:24 PM PDT 24
Peak memory 208776 kb
Host smart-c1e5bb0e-376b-4951-8117-4eb392fec028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542681165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2542681165
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2491440243
Short name T739
Test name
Test status
Simulation time 1012896867 ps
CPU time 19.53 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:42 PM PDT 24
Peak memory 215680 kb
Host smart-67041e48-5f3b-401c-aa76-ff6489f25148
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491440243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2491440243
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2589386051
Short name T949
Test name
Test status
Simulation time 1182059192 ps
CPU time 13.41 seconds
Started Mar 23 04:01:20 PM PDT 24
Finished Mar 23 04:01:33 PM PDT 24
Peak memory 219992 kb
Host smart-56d2ced9-ec37-4a7d-a4d4-4442b46a1ecd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589386051 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2589386051
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2850677212
Short name T902
Test name
Test status
Simulation time 3676319921 ps
CPU time 65.47 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:02:27 PM PDT 24
Peak memory 219784 kb
Host smart-233a3941-4e1d-431f-bb17-44e7aed8ca60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850677212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2850677212
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.680156683
Short name T1042
Test name
Test status
Simulation time 111178147 ps
CPU time 3.83 seconds
Started Mar 23 04:01:19 PM PDT 24
Finished Mar 23 04:01:22 PM PDT 24
Peak memory 210852 kb
Host smart-4a289187-158c-462e-ab7f-d4ba3f6e5eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680156683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.680156683
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2174595660
Short name T80
Test name
Test status
Simulation time 13122956 ps
CPU time 0.79 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:22 PM PDT 24
Peak memory 205884 kb
Host smart-d0ff3a37-748c-49e7-9be3-3ccde0bf37b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174595660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2174595660
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3237491904
Short name T837
Test name
Test status
Simulation time 3607857307 ps
CPU time 22.29 seconds
Started Mar 23 04:01:20 PM PDT 24
Finished Mar 23 04:01:43 PM PDT 24
Peak memory 209532 kb
Host smart-59b1381a-fcdf-479f-8a96-126528ffad23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237491904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3237491904
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2727415700
Short name T227
Test name
Test status
Simulation time 892187845 ps
CPU time 3.29 seconds
Started Mar 23 04:01:24 PM PDT 24
Finished Mar 23 04:01:28 PM PDT 24
Peak memory 206820 kb
Host smart-752fba05-76d4-4b31-b7d3-663d7f3a7f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727415700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2727415700
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1861120701
Short name T1074
Test name
Test status
Simulation time 488376990 ps
CPU time 8.3 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:30 PM PDT 24
Peak memory 222428 kb
Host smart-2943e44c-7e2e-447c-ba24-e3811b4b11f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861120701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1861120701
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_random.2062244473
Short name T218
Test name
Test status
Simulation time 316277506 ps
CPU time 5.28 seconds
Started Mar 23 04:01:20 PM PDT 24
Finished Mar 23 04:01:25 PM PDT 24
Peak memory 207284 kb
Host smart-158a3da6-e7d6-47af-8c5d-da4a2b2b05ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062244473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2062244473
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1393892647
Short name T575
Test name
Test status
Simulation time 92365310 ps
CPU time 3.05 seconds
Started Mar 23 04:01:25 PM PDT 24
Finished Mar 23 04:01:28 PM PDT 24
Peak memory 207084 kb
Host smart-356b2cfa-0706-45af-8923-44355dd0300e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393892647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1393892647
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3271033772
Short name T702
Test name
Test status
Simulation time 8407087423 ps
CPU time 81.53 seconds
Started Mar 23 04:01:23 PM PDT 24
Finished Mar 23 04:02:44 PM PDT 24
Peak memory 208440 kb
Host smart-e3bb4988-9ab3-4099-8a77-97ffc851dd52
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271033772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3271033772
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1939515020
Short name T1061
Test name
Test status
Simulation time 1874018154 ps
CPU time 45.08 seconds
Started Mar 23 04:01:21 PM PDT 24
Finished Mar 23 04:02:06 PM PDT 24
Peak memory 208744 kb
Host smart-2bea7c9a-03ea-42ac-a9c7-d26e723c2f4d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939515020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1939515020
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.642375722
Short name T379
Test name
Test status
Simulation time 165765046 ps
CPU time 1.93 seconds
Started Mar 23 04:01:18 PM PDT 24
Finished Mar 23 04:01:20 PM PDT 24
Peak memory 206788 kb
Host smart-dc719c90-82ee-4361-b28c-bc411ea81249
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642375722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.642375722
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1872581841
Short name T312
Test name
Test status
Simulation time 147873742 ps
CPU time 2.25 seconds
Started Mar 23 04:01:21 PM PDT 24
Finished Mar 23 04:01:24 PM PDT 24
Peak memory 215696 kb
Host smart-7b0c581a-9158-4b0e-abf5-00cff4057418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872581841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1872581841
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.773870362
Short name T872
Test name
Test status
Simulation time 154921392 ps
CPU time 1.84 seconds
Started Mar 23 04:01:24 PM PDT 24
Finished Mar 23 04:01:26 PM PDT 24
Peak memory 207056 kb
Host smart-114999fc-04ac-4eb9-95c5-5351f81be507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773870362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.773870362
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1844203234
Short name T71
Test name
Test status
Simulation time 622453044 ps
CPU time 25.21 seconds
Started Mar 23 04:01:23 PM PDT 24
Finished Mar 23 04:01:49 PM PDT 24
Peak memory 215184 kb
Host smart-2d6ac91b-c5af-4e17-8048-b7be1a26a08f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844203234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1844203234
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.417507054
Short name T103
Test name
Test status
Simulation time 221592893 ps
CPU time 5.13 seconds
Started Mar 23 04:01:23 PM PDT 24
Finished Mar 23 04:01:28 PM PDT 24
Peak memory 222604 kb
Host smart-79f1d043-ca6e-4ca8-8f35-99122ba02c4c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417507054 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.417507054
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3899804231
Short name T74
Test name
Test status
Simulation time 258888406 ps
CPU time 5.98 seconds
Started Mar 23 04:01:23 PM PDT 24
Finished Mar 23 04:01:29 PM PDT 24
Peak memory 208760 kb
Host smart-366e86a5-e282-47db-9a85-b7934d3f6548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899804231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3899804231
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.4138658224
Short name T779
Test name
Test status
Simulation time 304239900 ps
CPU time 2.79 seconds
Started Mar 23 04:01:23 PM PDT 24
Finished Mar 23 04:01:26 PM PDT 24
Peak memory 209944 kb
Host smart-97fff381-27a0-4751-b1c4-e64b5b26255d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138658224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.4138658224
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2506394386
Short name T699
Test name
Test status
Simulation time 34206993 ps
CPU time 0.76 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:23 PM PDT 24
Peak memory 205904 kb
Host smart-f28d5cdb-9a09-4a81-b8d2-93d16ab23615
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506394386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2506394386
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.988780287
Short name T224
Test name
Test status
Simulation time 59589887 ps
CPU time 4.08 seconds
Started Mar 23 04:01:21 PM PDT 24
Finished Mar 23 04:01:26 PM PDT 24
Peak memory 214316 kb
Host smart-66e21226-1c9d-46fc-9981-a45ea4a35515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=988780287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.988780287
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1180763313
Short name T204
Test name
Test status
Simulation time 246724445 ps
CPU time 5.1 seconds
Started Mar 23 04:01:18 PM PDT 24
Finished Mar 23 04:01:24 PM PDT 24
Peak memory 218880 kb
Host smart-c1855f62-3263-4079-bf35-f0a700728e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180763313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1180763313
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1396813161
Short name T763
Test name
Test status
Simulation time 135675371 ps
CPU time 2.71 seconds
Started Mar 23 04:01:23 PM PDT 24
Finished Mar 23 04:01:26 PM PDT 24
Peak memory 207532 kb
Host smart-168829a9-1322-4ac1-9209-3c1d8ad466e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396813161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1396813161
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.4200069656
Short name T21
Test name
Test status
Simulation time 192968130 ps
CPU time 3.66 seconds
Started Mar 23 04:01:19 PM PDT 24
Finished Mar 23 04:01:23 PM PDT 24
Peak memory 218428 kb
Host smart-fb2fd9b7-5627-4869-9195-0ff0133927c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200069656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.4200069656
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1937561385
Short name T35
Test name
Test status
Simulation time 452652438 ps
CPU time 5.97 seconds
Started Mar 23 04:01:26 PM PDT 24
Finished Mar 23 04:01:32 PM PDT 24
Peak memory 210172 kb
Host smart-5d9674d8-9675-4255-b11e-834abbc247d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937561385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1937561385
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2963143699
Short name T1004
Test name
Test status
Simulation time 991499881 ps
CPU time 5.96 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:28 PM PDT 24
Peak memory 215696 kb
Host smart-4f611c36-3c88-4619-b468-ed0c2b4fda10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963143699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2963143699
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.741624485
Short name T961
Test name
Test status
Simulation time 808724543 ps
CPU time 6.01 seconds
Started Mar 23 04:01:24 PM PDT 24
Finished Mar 23 04:01:30 PM PDT 24
Peak memory 209660 kb
Host smart-fca5f749-5895-4ad0-b07c-58b0955392a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741624485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.741624485
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1444994455
Short name T234
Test name
Test status
Simulation time 4493423202 ps
CPU time 84.28 seconds
Started Mar 23 04:01:25 PM PDT 24
Finished Mar 23 04:02:49 PM PDT 24
Peak memory 208884 kb
Host smart-0d848d3b-0435-4b8f-ac32-58a6b7f71615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444994455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1444994455
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3182142878
Short name T97
Test name
Test status
Simulation time 135136394 ps
CPU time 2.44 seconds
Started Mar 23 04:01:19 PM PDT 24
Finished Mar 23 04:01:22 PM PDT 24
Peak memory 206860 kb
Host smart-b43639bd-54bb-4abe-abe2-cab14a880eba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182142878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3182142878
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.718258395
Short name T190
Test name
Test status
Simulation time 36449037 ps
CPU time 2.37 seconds
Started Mar 23 04:01:21 PM PDT 24
Finished Mar 23 04:01:23 PM PDT 24
Peak memory 208680 kb
Host smart-f5732560-0d8a-4d53-802b-c2c4272a7d73
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718258395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.718258395
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1608683181
Short name T810
Test name
Test status
Simulation time 131182525 ps
CPU time 3.33 seconds
Started Mar 23 04:01:24 PM PDT 24
Finished Mar 23 04:01:28 PM PDT 24
Peak memory 207868 kb
Host smart-29a3806a-0e50-4653-a43f-f0619308e5a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608683181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1608683181
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1529008661
Short name T1028
Test name
Test status
Simulation time 1370675260 ps
CPU time 37.18 seconds
Started Mar 23 04:01:20 PM PDT 24
Finished Mar 23 04:01:57 PM PDT 24
Peak memory 208584 kb
Host smart-8dfcc7da-707c-4831-8f4f-f5449cc7e327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529008661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1529008661
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.677138935
Short name T936
Test name
Test status
Simulation time 73229143 ps
CPU time 1.71 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:23 PM PDT 24
Peak memory 206644 kb
Host smart-801cd298-5855-4fca-b719-44c4fba0e44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677138935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.677138935
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1601935364
Short name T334
Test name
Test status
Simulation time 311277685 ps
CPU time 6.6 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:28 PM PDT 24
Peak memory 208920 kb
Host smart-30fc2599-aafb-44f0-85c4-e262ff7f0662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601935364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1601935364
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.774070145
Short name T766
Test name
Test status
Simulation time 1342026321 ps
CPU time 26.04 seconds
Started Mar 23 04:01:21 PM PDT 24
Finished Mar 23 04:01:47 PM PDT 24
Peak memory 211048 kb
Host smart-085c5c58-12bc-4dfb-b60c-70625d14f79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774070145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.774070145
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3354192597
Short name T606
Test name
Test status
Simulation time 91753404 ps
CPU time 0.84 seconds
Started Mar 23 04:01:38 PM PDT 24
Finished Mar 23 04:01:39 PM PDT 24
Peak memory 205884 kb
Host smart-57e1c356-b664-47d0-aa94-ed0b0ce7401f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354192597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3354192597
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1835641986
Short name T410
Test name
Test status
Simulation time 46221243 ps
CPU time 3.38 seconds
Started Mar 23 04:01:19 PM PDT 24
Finished Mar 23 04:01:22 PM PDT 24
Peak memory 214320 kb
Host smart-4ccf0f80-e253-44a8-bdec-b89bfdd051f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835641986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1835641986
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.472876385
Short name T65
Test name
Test status
Simulation time 247448857 ps
CPU time 1.77 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:24 PM PDT 24
Peak memory 208696 kb
Host smart-0d65c313-80ae-42b5-a456-841aa086ff24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472876385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.472876385
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1236717549
Short name T259
Test name
Test status
Simulation time 1040974578 ps
CPU time 5.1 seconds
Started Mar 23 04:01:19 PM PDT 24
Finished Mar 23 04:01:24 PM PDT 24
Peak memory 222472 kb
Host smart-48cfe978-9b28-4234-bc73-c5e007052c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236717549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1236717549
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2640736240
Short name T693
Test name
Test status
Simulation time 543939326 ps
CPU time 3.96 seconds
Started Mar 23 04:01:19 PM PDT 24
Finished Mar 23 04:01:23 PM PDT 24
Peak memory 218832 kb
Host smart-43417702-ab85-4b75-9e27-42f6ad2c4441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640736240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2640736240
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1911477976
Short name T918
Test name
Test status
Simulation time 10083529931 ps
CPU time 74.61 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:02:36 PM PDT 24
Peak memory 214404 kb
Host smart-9e56e1cc-d73e-44ff-9662-b74d7af5153e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911477976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1911477976
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2953578078
Short name T1034
Test name
Test status
Simulation time 307017630 ps
CPU time 7.34 seconds
Started Mar 23 04:01:20 PM PDT 24
Finished Mar 23 04:01:28 PM PDT 24
Peak memory 208588 kb
Host smart-df3d0378-7e15-47d1-96b0-77aec44d4fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953578078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2953578078
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1558465326
Short name T687
Test name
Test status
Simulation time 199377242 ps
CPU time 2.98 seconds
Started Mar 23 04:01:24 PM PDT 24
Finished Mar 23 04:01:27 PM PDT 24
Peak memory 206964 kb
Host smart-f8bcd354-23d1-427d-b2d6-50c918efaa66
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558465326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1558465326
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3775348344
Short name T192
Test name
Test status
Simulation time 43611355 ps
CPU time 2.74 seconds
Started Mar 23 04:01:21 PM PDT 24
Finished Mar 23 04:01:24 PM PDT 24
Peak memory 208008 kb
Host smart-539e67d8-2cc8-48ad-9156-37f86c256710
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775348344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3775348344
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.4169092856
Short name T985
Test name
Test status
Simulation time 514886969 ps
CPU time 3.56 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:39 PM PDT 24
Peak memory 209312 kb
Host smart-2b9f9f73-36c2-4c84-937d-b52f21367c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169092856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.4169092856
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3660926969
Short name T910
Test name
Test status
Simulation time 2562259799 ps
CPU time 25.18 seconds
Started Mar 23 04:01:24 PM PDT 24
Finished Mar 23 04:01:49 PM PDT 24
Peak memory 208824 kb
Host smart-025a09e9-b8a0-4afe-9ae2-196b58b62432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660926969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3660926969
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2100847603
Short name T1060
Test name
Test status
Simulation time 1352719257 ps
CPU time 43.8 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:02:20 PM PDT 24
Peak memory 222516 kb
Host smart-655cb1ac-715c-4755-aa85-767c414fd828
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100847603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2100847603
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2424296373
Short name T213
Test name
Test status
Simulation time 386905396 ps
CPU time 6.85 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:43 PM PDT 24
Peak memory 222544 kb
Host smart-70a8d06e-fd9c-4c77-90b2-b32b1fb747ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424296373 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2424296373
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1779819092
Short name T283
Test name
Test status
Simulation time 39816484 ps
CPU time 2.97 seconds
Started Mar 23 04:01:22 PM PDT 24
Finished Mar 23 04:01:25 PM PDT 24
Peak memory 214340 kb
Host smart-ad4542bc-c616-45c0-b129-598fe6990d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779819092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1779819092
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1172768232
Short name T839
Test name
Test status
Simulation time 75649783 ps
CPU time 1.49 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:38 PM PDT 24
Peak memory 209480 kb
Host smart-4c784980-f757-4e8d-8feb-98aab669f8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172768232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1172768232
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1859283715
Short name T611
Test name
Test status
Simulation time 15467380 ps
CPU time 0.71 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:37 PM PDT 24
Peak memory 205900 kb
Host smart-435b8c55-55da-494e-bfb7-5d31ba000846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859283715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1859283715
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.605847597
Short name T25
Test name
Test status
Simulation time 674079902 ps
CPU time 20.39 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:57 PM PDT 24
Peak memory 214644 kb
Host smart-feac01a9-f7bf-46be-bba8-9f1cc0ce0465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605847597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.605847597
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.658356023
Short name T968
Test name
Test status
Simulation time 181346347 ps
CPU time 4.67 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:42 PM PDT 24
Peak memory 208408 kb
Host smart-84d6d830-b780-485e-9f28-f08684d45f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658356023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.658356023
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3104915357
Short name T684
Test name
Test status
Simulation time 3479959512 ps
CPU time 33.46 seconds
Started Mar 23 04:01:38 PM PDT 24
Finished Mar 23 04:02:11 PM PDT 24
Peak memory 214320 kb
Host smart-53b14f8b-8158-4540-869c-99f6d13b82f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104915357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3104915357
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1142948112
Short name T212
Test name
Test status
Simulation time 203919155 ps
CPU time 3.83 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:40 PM PDT 24
Peak memory 207544 kb
Host smart-19d0fffb-9e26-4296-94d1-f4d4a9f93568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142948112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1142948112
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3691641830
Short name T904
Test name
Test status
Simulation time 177050586 ps
CPU time 4.56 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:40 PM PDT 24
Peak memory 208836 kb
Host smart-98ab344d-ca99-43d0-851f-455e7099bd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691641830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3691641830
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3021756262
Short name T781
Test name
Test status
Simulation time 260039323 ps
CPU time 3.14 seconds
Started Mar 23 04:01:34 PM PDT 24
Finished Mar 23 04:01:37 PM PDT 24
Peak memory 207284 kb
Host smart-238933f4-d184-48fb-9467-57111248ac83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021756262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3021756262
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.418950178
Short name T984
Test name
Test status
Simulation time 89024806 ps
CPU time 3.99 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:40 PM PDT 24
Peak memory 208852 kb
Host smart-a0cbb4ae-9f7b-40e3-81fd-94b766a688be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418950178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.418950178
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1979725336
Short name T838
Test name
Test status
Simulation time 1059022447 ps
CPU time 9.88 seconds
Started Mar 23 04:01:33 PM PDT 24
Finished Mar 23 04:01:43 PM PDT 24
Peak memory 208176 kb
Host smart-0e7c7ed7-31d9-44e4-8b88-ce92948e794d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979725336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1979725336
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.204687527
Short name T346
Test name
Test status
Simulation time 21152311 ps
CPU time 1.88 seconds
Started Mar 23 04:01:34 PM PDT 24
Finished Mar 23 04:01:36 PM PDT 24
Peak memory 206776 kb
Host smart-62bf35c6-46e6-4096-823a-a62efabb2c9c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204687527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.204687527
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.694670085
Short name T722
Test name
Test status
Simulation time 34819208 ps
CPU time 2.17 seconds
Started Mar 23 04:01:35 PM PDT 24
Finished Mar 23 04:01:38 PM PDT 24
Peak memory 215420 kb
Host smart-2cef0caa-a6bb-41f7-9b86-3e8594801031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694670085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.694670085
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2819667212
Short name T675
Test name
Test status
Simulation time 14209632412 ps
CPU time 72.49 seconds
Started Mar 23 04:01:34 PM PDT 24
Finished Mar 23 04:02:47 PM PDT 24
Peak memory 208960 kb
Host smart-9ad1ba36-58b8-44a6-8894-59b18bda2e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819667212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2819667212
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3162833158
Short name T678
Test name
Test status
Simulation time 305604883 ps
CPU time 4.15 seconds
Started Mar 23 04:01:38 PM PDT 24
Finished Mar 23 04:01:42 PM PDT 24
Peak memory 222656 kb
Host smart-e0c5d4da-5af7-4d2f-a3cc-4efa0f2ce896
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162833158 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3162833158
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.755576425
Short name T183
Test name
Test status
Simulation time 4226635141 ps
CPU time 31.81 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:02:08 PM PDT 24
Peak memory 208408 kb
Host smart-9d0ddb02-f75c-4074-8425-eb4b91f43b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755576425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.755576425
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3716211245
Short name T1043
Test name
Test status
Simulation time 223741904 ps
CPU time 2.14 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:39 PM PDT 24
Peak memory 209732 kb
Host smart-280f93a4-28dd-402c-85b8-039452e26239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716211245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3716211245
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.3158467050
Short name T759
Test name
Test status
Simulation time 25879506 ps
CPU time 0.91 seconds
Started Mar 23 04:00:06 PM PDT 24
Finished Mar 23 04:00:07 PM PDT 24
Peak memory 205912 kb
Host smart-3922babe-7fe3-48b1-86b5-e4111a234191
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158467050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3158467050
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2225823601
Short name T361
Test name
Test status
Simulation time 81354752 ps
CPU time 3.47 seconds
Started Mar 23 03:59:58 PM PDT 24
Finished Mar 23 04:00:02 PM PDT 24
Peak memory 208804 kb
Host smart-cfd02dcd-5c80-479e-9261-cd337718e676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225823601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2225823601
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.4024581961
Short name T68
Test name
Test status
Simulation time 529372820 ps
CPU time 4.12 seconds
Started Mar 23 03:59:47 PM PDT 24
Finished Mar 23 03:59:52 PM PDT 24
Peak memory 218456 kb
Host smart-0cbfa843-3c5c-4a46-ba14-00f2e556ed2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024581961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.4024581961
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2159097868
Short name T235
Test name
Test status
Simulation time 66790386 ps
CPU time 2.59 seconds
Started Mar 23 03:59:45 PM PDT 24
Finished Mar 23 03:59:49 PM PDT 24
Peak memory 214324 kb
Host smart-7f8a2acc-378e-401b-aa8a-fa606171d4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159097868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2159097868
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3088589332
Short name T709
Test name
Test status
Simulation time 109628503 ps
CPU time 2.61 seconds
Started Mar 23 03:59:47 PM PDT 24
Finished Mar 23 03:59:50 PM PDT 24
Peak memory 210828 kb
Host smart-e55bf0d1-bfc3-4201-8c30-4de2329d6387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088589332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3088589332
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.290119491
Short name T1045
Test name
Test status
Simulation time 1135394916 ps
CPU time 8.46 seconds
Started Mar 23 03:59:44 PM PDT 24
Finished Mar 23 03:59:54 PM PDT 24
Peak memory 209880 kb
Host smart-0e33e992-ff79-4687-be18-e80708359773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290119491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.290119491
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2140476089
Short name T668
Test name
Test status
Simulation time 183005850 ps
CPU time 4.36 seconds
Started Mar 23 03:59:47 PM PDT 24
Finished Mar 23 03:59:52 PM PDT 24
Peak memory 207432 kb
Host smart-88b59568-8e2a-4053-84e4-18fea759d32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140476089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2140476089
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2644992588
Short name T1025
Test name
Test status
Simulation time 2006557333 ps
CPU time 8.78 seconds
Started Mar 23 03:59:46 PM PDT 24
Finished Mar 23 03:59:55 PM PDT 24
Peak memory 206880 kb
Host smart-4e8a09df-308d-4010-90c6-3d1cff61ebbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644992588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2644992588
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2547414499
Short name T970
Test name
Test status
Simulation time 272933211 ps
CPU time 4.41 seconds
Started Mar 23 03:59:50 PM PDT 24
Finished Mar 23 03:59:55 PM PDT 24
Peak memory 208540 kb
Host smart-b7fdb073-ace1-45db-a81a-bfdded1680b9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547414499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2547414499
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2394479278
Short name T641
Test name
Test status
Simulation time 289715403 ps
CPU time 4.46 seconds
Started Mar 23 03:59:43 PM PDT 24
Finished Mar 23 03:59:50 PM PDT 24
Peak memory 208544 kb
Host smart-f4aee8e4-c6c3-4777-aa44-17e5b6709db8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394479278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2394479278
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.791499525
Short name T1069
Test name
Test status
Simulation time 1983789286 ps
CPU time 45.46 seconds
Started Mar 23 03:59:46 PM PDT 24
Finished Mar 23 04:00:32 PM PDT 24
Peak memory 208840 kb
Host smart-3c7167d5-fc69-4425-9233-99255a032284
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791499525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.791499525
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3967688476
Short name T786
Test name
Test status
Simulation time 205383669 ps
CPU time 4.26 seconds
Started Mar 23 03:59:58 PM PDT 24
Finished Mar 23 04:00:03 PM PDT 24
Peak memory 208720 kb
Host smart-10a4b33b-f5cf-4309-8250-eafea8e1a3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967688476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3967688476
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.658097888
Short name T896
Test name
Test status
Simulation time 1775253029 ps
CPU time 7.56 seconds
Started Mar 23 03:59:44 PM PDT 24
Finished Mar 23 03:59:53 PM PDT 24
Peak memory 208792 kb
Host smart-0dbb7ce9-c21d-4da2-8d4e-be9af76bf4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658097888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.658097888
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2561996934
Short name T908
Test name
Test status
Simulation time 361771600 ps
CPU time 6.25 seconds
Started Mar 23 03:59:58 PM PDT 24
Finished Mar 23 04:00:04 PM PDT 24
Peak memory 223664 kb
Host smart-084e8c4a-7a08-432f-b91b-bdc5f0da544b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561996934 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2561996934
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1114041680
Short name T367
Test name
Test status
Simulation time 618437357 ps
CPU time 5.7 seconds
Started Mar 23 03:59:44 PM PDT 24
Finished Mar 23 03:59:51 PM PDT 24
Peak memory 208392 kb
Host smart-73aeebda-8d73-4465-aab7-72002bce3788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114041680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1114041680
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3914883393
Short name T865
Test name
Test status
Simulation time 19661574 ps
CPU time 0.85 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:01:41 PM PDT 24
Peak memory 205800 kb
Host smart-36ed4d9f-3510-488f-b905-4a2058e5174a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914883393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3914883393
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2138236086
Short name T269
Test name
Test status
Simulation time 462920122 ps
CPU time 4.43 seconds
Started Mar 23 04:01:34 PM PDT 24
Finished Mar 23 04:01:38 PM PDT 24
Peak memory 214428 kb
Host smart-ab4748c1-8dd6-49b7-ba5c-548ee37a7d9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138236086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2138236086
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.4024215178
Short name T689
Test name
Test status
Simulation time 153355349 ps
CPU time 2.59 seconds
Started Mar 23 04:01:34 PM PDT 24
Finished Mar 23 04:01:37 PM PDT 24
Peak memory 218264 kb
Host smart-b3306f22-6721-467c-a153-ec3d41d6da07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024215178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.4024215178
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3937295453
Short name T371
Test name
Test status
Simulation time 438658978 ps
CPU time 2.34 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:38 PM PDT 24
Peak memory 209060 kb
Host smart-4b3a400a-fcae-4810-94e9-8dad5f9b1c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937295453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3937295453
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2947582597
Short name T274
Test name
Test status
Simulation time 110765457 ps
CPU time 4.75 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:01:45 PM PDT 24
Peak memory 222340 kb
Host smart-8a25ae5d-c10c-41ed-a55a-a37e4275bd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947582597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2947582597
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3113774614
Short name T374
Test name
Test status
Simulation time 403485441 ps
CPU time 3.27 seconds
Started Mar 23 04:01:35 PM PDT 24
Finished Mar 23 04:01:39 PM PDT 24
Peak memory 214264 kb
Host smart-4f42a1e6-5ae5-498f-bc52-4d14c0bb5532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113774614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3113774614
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2760054914
Short name T1
Test name
Test status
Simulation time 260643350 ps
CPU time 3.81 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:40 PM PDT 24
Peak memory 208224 kb
Host smart-4cc86036-eed0-4d0f-9311-be03be883683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760054914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2760054914
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1314783775
Short name T277
Test name
Test status
Simulation time 229142237 ps
CPU time 6.31 seconds
Started Mar 23 04:01:38 PM PDT 24
Finished Mar 23 04:01:44 PM PDT 24
Peak memory 208468 kb
Host smart-a9fcc843-e7fe-4f11-8de2-07d9128841fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314783775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1314783775
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3557651289
Short name T336
Test name
Test status
Simulation time 84912800 ps
CPU time 1.95 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:39 PM PDT 24
Peak memory 207412 kb
Host smart-f0fc586a-92cf-49fc-aa75-b7f57bae0cbf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557651289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3557651289
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1661767489
Short name T401
Test name
Test status
Simulation time 490171547 ps
CPU time 8.8 seconds
Started Mar 23 04:01:35 PM PDT 24
Finished Mar 23 04:01:44 PM PDT 24
Peak memory 208740 kb
Host smart-a2a487eb-40a8-467f-b3c9-0f40865019ef
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661767489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1661767489
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3462547918
Short name T681
Test name
Test status
Simulation time 2445535491 ps
CPU time 40.43 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:02:20 PM PDT 24
Peak memory 209020 kb
Host smart-2c0bbae2-957b-42f9-a00b-0981c3dc027a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462547918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3462547918
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.959379573
Short name T430
Test name
Test status
Simulation time 547833811 ps
CPU time 9.49 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:47 PM PDT 24
Peak memory 208708 kb
Host smart-35e5c030-3f7b-4838-a227-03bd3c29a012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959379573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.959379573
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2007954018
Short name T608
Test name
Test status
Simulation time 148986915 ps
CPU time 2.23 seconds
Started Mar 23 04:01:35 PM PDT 24
Finished Mar 23 04:01:37 PM PDT 24
Peak memory 206760 kb
Host smart-0b562e1a-6ee3-41d9-a68a-4092c949f7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007954018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2007954018
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.778725760
Short name T964
Test name
Test status
Simulation time 977066683 ps
CPU time 10.76 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:01:50 PM PDT 24
Peak memory 222936 kb
Host smart-b889bcbd-2e58-4822-b7f2-dfa0f5a7c8a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778725760 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.778725760
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.570208560
Short name T647
Test name
Test status
Simulation time 2986290839 ps
CPU time 73.36 seconds
Started Mar 23 04:01:38 PM PDT 24
Finished Mar 23 04:02:51 PM PDT 24
Peak memory 209000 kb
Host smart-36fdca68-89f7-4e58-88be-03c1713804c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570208560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.570208560
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.4042183024
Short name T592
Test name
Test status
Simulation time 309517067 ps
CPU time 1.67 seconds
Started Mar 23 04:01:35 PM PDT 24
Finished Mar 23 04:01:37 PM PDT 24
Peak memory 210624 kb
Host smart-de8ef5dd-1b5e-4397-8059-76a412c141f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042183024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.4042183024
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1676705464
Short name T887
Test name
Test status
Simulation time 50755408 ps
CPU time 0.8 seconds
Started Mar 23 04:01:38 PM PDT 24
Finished Mar 23 04:01:39 PM PDT 24
Peak memory 205920 kb
Host smart-4e4d06bd-9a28-400b-805d-c6a71b64c68a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676705464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1676705464
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2204451228
Short name T221
Test name
Test status
Simulation time 293383996 ps
CPU time 4.64 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:01:44 PM PDT 24
Peak memory 214328 kb
Host smart-0a65bd55-3708-44b3-9d44-f6c30a6946fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2204451228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2204451228
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1650162252
Short name T826
Test name
Test status
Simulation time 280638308 ps
CPU time 8.31 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:01:49 PM PDT 24
Peak memory 214372 kb
Host smart-5b675360-1aee-4868-b0a9-b9a34f35c942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650162252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1650162252
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2045022246
Short name T7
Test name
Test status
Simulation time 76346345 ps
CPU time 3.17 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:39 PM PDT 24
Peak memory 209580 kb
Host smart-03b92064-9383-4391-bdea-ca1a85a18656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045022246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2045022246
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1888756953
Short name T835
Test name
Test status
Simulation time 235203601 ps
CPU time 3.45 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:40 PM PDT 24
Peak memory 207320 kb
Host smart-db3b8342-d7ba-45cb-a673-f45755851234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888756953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1888756953
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2964706394
Short name T661
Test name
Test status
Simulation time 82789406 ps
CPU time 1.92 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:38 PM PDT 24
Peak memory 206824 kb
Host smart-4b55408c-3821-40dd-9028-9838700bb4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964706394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2964706394
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1493619096
Short name T1076
Test name
Test status
Simulation time 329760310 ps
CPU time 5.1 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:01:45 PM PDT 24
Peak memory 208744 kb
Host smart-609361fa-4ab4-4dcf-a371-ad2d5125f1a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493619096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1493619096
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.24121614
Short name T617
Test name
Test status
Simulation time 591250841 ps
CPU time 3.8 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:41 PM PDT 24
Peak memory 208780 kb
Host smart-b88a89fa-63f7-415f-9aa5-bfad2811bea9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24121614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.24121614
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3826989644
Short name T586
Test name
Test status
Simulation time 301846233 ps
CPU time 3.74 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:40 PM PDT 24
Peak memory 206968 kb
Host smart-9e95bd84-de88-4f90-ab27-1c0d04c57946
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826989644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3826989644
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.4054942752
Short name T906
Test name
Test status
Simulation time 134232766 ps
CPU time 3.28 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:39 PM PDT 24
Peak memory 209396 kb
Host smart-c75432dc-8d55-489d-95ed-99dab3008a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054942752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.4054942752
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2684926162
Short name T573
Test name
Test status
Simulation time 209659598 ps
CPU time 4.78 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:40 PM PDT 24
Peak memory 208792 kb
Host smart-3c2944d7-a83a-46d8-abdb-61a6b33ff34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684926162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2684926162
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.428264051
Short name T613
Test name
Test status
Simulation time 847978484 ps
CPU time 8.35 seconds
Started Mar 23 04:01:38 PM PDT 24
Finished Mar 23 04:01:47 PM PDT 24
Peak memory 223016 kb
Host smart-0737ce1e-e06b-4fb5-b2dd-39306625903b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428264051 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.428264051
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2414150222
Short name T229
Test name
Test status
Simulation time 63068237 ps
CPU time 3.84 seconds
Started Mar 23 04:01:35 PM PDT 24
Finished Mar 23 04:01:39 PM PDT 24
Peak memory 214332 kb
Host smart-e7fda99c-5dac-464d-bf86-a3329624f620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414150222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2414150222
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1249190222
Short name T54
Test name
Test status
Simulation time 292854476 ps
CPU time 2.6 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:38 PM PDT 24
Peak memory 210076 kb
Host smart-f69a8f62-e62c-4484-ba6b-1db85a0ae7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249190222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1249190222
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.214032403
Short name T768
Test name
Test status
Simulation time 22176628 ps
CPU time 0.78 seconds
Started Mar 23 04:01:47 PM PDT 24
Finished Mar 23 04:01:48 PM PDT 24
Peak memory 205912 kb
Host smart-a919b1eb-18f3-42e5-9c47-9a28700a703e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214032403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.214032403
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3081578190
Short name T628
Test name
Test status
Simulation time 608880302 ps
CPU time 5.01 seconds
Started Mar 23 04:01:42 PM PDT 24
Finished Mar 23 04:01:47 PM PDT 24
Peak memory 218072 kb
Host smart-07480369-c3f9-44bb-8c8e-b3a30ad1e1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081578190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3081578190
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.421234751
Short name T91
Test name
Test status
Simulation time 670242813 ps
CPU time 7.87 seconds
Started Mar 23 04:01:38 PM PDT 24
Finished Mar 23 04:01:46 PM PDT 24
Peak memory 209068 kb
Host smart-efaca69e-e13d-494d-ba41-0eb5fbb29f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421234751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.421234751
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.57340674
Short name T258
Test name
Test status
Simulation time 290452203 ps
CPU time 4.9 seconds
Started Mar 23 04:01:31 PM PDT 24
Finished Mar 23 04:01:36 PM PDT 24
Peak memory 222452 kb
Host smart-9d0772ba-5ff0-4a14-aa07-7abcc1fe1b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57340674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.57340674
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.625639129
Short name T583
Test name
Test status
Simulation time 90376030 ps
CPU time 2.64 seconds
Started Mar 23 04:01:42 PM PDT 24
Finished Mar 23 04:01:44 PM PDT 24
Peak memory 220080 kb
Host smart-fd3b3da9-27e5-4cd8-b875-a9087a09a11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625639129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.625639129
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3447423227
Short name T729
Test name
Test status
Simulation time 70263235 ps
CPU time 4.57 seconds
Started Mar 23 04:01:35 PM PDT 24
Finished Mar 23 04:01:39 PM PDT 24
Peak memory 218240 kb
Host smart-30924c88-98bd-4ec6-88d0-350bd1d7868e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447423227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3447423227
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2599827425
Short name T795
Test name
Test status
Simulation time 89473378 ps
CPU time 1.89 seconds
Started Mar 23 04:01:39 PM PDT 24
Finished Mar 23 04:01:41 PM PDT 24
Peak memory 206812 kb
Host smart-d08fa00e-536c-4a39-b7ae-3e2cfa43099e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599827425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2599827425
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.4066173493
Short name T670
Test name
Test status
Simulation time 1195367373 ps
CPU time 6.18 seconds
Started Mar 23 04:01:38 PM PDT 24
Finished Mar 23 04:01:44 PM PDT 24
Peak memory 208836 kb
Host smart-c28de740-538a-4e41-bbf7-e7ecab19e9de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066173493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.4066173493
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.828367068
Short name T757
Test name
Test status
Simulation time 2702633600 ps
CPU time 5.66 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:43 PM PDT 24
Peak memory 207020 kb
Host smart-0d0283ef-ef44-488f-840e-165641fe458e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828367068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.828367068
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3725798167
Short name T321
Test name
Test status
Simulation time 44418203 ps
CPU time 2.04 seconds
Started Mar 23 04:01:38 PM PDT 24
Finished Mar 23 04:01:40 PM PDT 24
Peak memory 208672 kb
Host smart-d2068288-671c-4e74-a0d2-4f31646dc293
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725798167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3725798167
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3073841981
Short name T831
Test name
Test status
Simulation time 3556722764 ps
CPU time 21.55 seconds
Started Mar 23 04:01:42 PM PDT 24
Finished Mar 23 04:02:03 PM PDT 24
Peak memory 209480 kb
Host smart-d64020ac-3642-4561-a741-33623871281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073841981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3073841981
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2628555650
Short name T630
Test name
Test status
Simulation time 46318993 ps
CPU time 2.56 seconds
Started Mar 23 04:01:39 PM PDT 24
Finished Mar 23 04:01:42 PM PDT 24
Peak memory 208520 kb
Host smart-e6f4a7f8-589c-401f-b254-c819eb805a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628555650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2628555650
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3754271509
Short name T848
Test name
Test status
Simulation time 1343849507 ps
CPU time 25.81 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:02:06 PM PDT 24
Peak memory 222420 kb
Host smart-cffd7d4c-66b9-4079-865c-896391b16a15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754271509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3754271509
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1258900453
Short name T648
Test name
Test status
Simulation time 1559227896 ps
CPU time 35.73 seconds
Started Mar 23 04:01:41 PM PDT 24
Finished Mar 23 04:02:16 PM PDT 24
Peak memory 209308 kb
Host smart-4600c5d6-6d89-486d-9319-b4b8dd10251f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258900453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1258900453
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3539235624
Short name T669
Test name
Test status
Simulation time 114984448 ps
CPU time 3.83 seconds
Started Mar 23 04:01:39 PM PDT 24
Finished Mar 23 04:01:43 PM PDT 24
Peak memory 209912 kb
Host smart-0c6b79dd-4855-47b1-832b-b261860b0a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539235624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3539235624
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.468238565
Short name T857
Test name
Test status
Simulation time 10228535 ps
CPU time 0.77 seconds
Started Mar 23 04:01:39 PM PDT 24
Finished Mar 23 04:01:40 PM PDT 24
Peak memory 205908 kb
Host smart-21127f1a-3c73-4c41-a732-8def1049d552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468238565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.468238565
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.697681196
Short name T1036
Test name
Test status
Simulation time 167155162 ps
CPU time 3.38 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:01:44 PM PDT 24
Peak memory 215140 kb
Host smart-3b6d4ac6-fb2a-4615-abc2-8a9f90a2e78c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=697681196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.697681196
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3546160710
Short name T61
Test name
Test status
Simulation time 392280269 ps
CPU time 10.17 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:47 PM PDT 24
Peak memory 210032 kb
Host smart-c39de9b7-f27b-4dfc-8686-027a1ff52c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546160710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3546160710
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.676735242
Short name T45
Test name
Test status
Simulation time 2512286369 ps
CPU time 4.47 seconds
Started Mar 23 04:01:47 PM PDT 24
Finished Mar 23 04:01:51 PM PDT 24
Peak memory 208240 kb
Host smart-a6d68f84-2ae9-4edd-9f05-e2c49ac77c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676735242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.676735242
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2678000577
Short name T372
Test name
Test status
Simulation time 120356148 ps
CPU time 4.84 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:01:45 PM PDT 24
Peak memory 214440 kb
Host smart-decdf03e-3a4c-4525-b3a8-a4bf99b52c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678000577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2678000577
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3004844247
Short name T843
Test name
Test status
Simulation time 665294724 ps
CPU time 11.87 seconds
Started Mar 23 04:01:42 PM PDT 24
Finished Mar 23 04:01:54 PM PDT 24
Peak memory 214196 kb
Host smart-0f24975b-52c4-4e42-9910-c85ed3a8278a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004844247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3004844247
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2966637520
Short name T101
Test name
Test status
Simulation time 60283285 ps
CPU time 3.02 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:40 PM PDT 24
Peak memory 209476 kb
Host smart-cc5072ea-7256-410c-b554-a53c03bb9191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966637520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2966637520
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.223998201
Short name T311
Test name
Test status
Simulation time 537282016 ps
CPU time 6.02 seconds
Started Mar 23 04:01:47 PM PDT 24
Finished Mar 23 04:01:53 PM PDT 24
Peak memory 208828 kb
Host smart-a37b63cd-a102-4e3c-867d-95d63494606c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223998201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.223998201
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1018323897
Short name T710
Test name
Test status
Simulation time 179824465 ps
CPU time 6.18 seconds
Started Mar 23 04:01:46 PM PDT 24
Finished Mar 23 04:01:53 PM PDT 24
Peak memory 208296 kb
Host smart-5b57b208-3499-4978-af6d-cfc499f0840e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018323897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1018323897
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2374969195
Short name T935
Test name
Test status
Simulation time 301224528 ps
CPU time 3.84 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:01:44 PM PDT 24
Peak memory 208956 kb
Host smart-f6892bcd-e010-441d-943d-0b2a3892a2c8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374969195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2374969195
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2009593454
Short name T791
Test name
Test status
Simulation time 449044838 ps
CPU time 7.34 seconds
Started Mar 23 04:01:42 PM PDT 24
Finished Mar 23 04:01:50 PM PDT 24
Peak memory 208152 kb
Host smart-3de0f203-d00b-44a1-b74c-3b3b5c3cf2cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009593454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2009593454
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1886122266
Short name T656
Test name
Test status
Simulation time 83808227 ps
CPU time 3.23 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:01:43 PM PDT 24
Peak memory 206876 kb
Host smart-d6169966-7f6c-4925-b7e6-e543951f1c7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886122266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1886122266
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2493962927
Short name T1071
Test name
Test status
Simulation time 183853228 ps
CPU time 2.58 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:01:43 PM PDT 24
Peak memory 215148 kb
Host smart-d597e46f-bf7a-480b-a70c-01af606883e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493962927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2493962927
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3797789451
Short name T920
Test name
Test status
Simulation time 247504248 ps
CPU time 3.12 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:40 PM PDT 24
Peak memory 208156 kb
Host smart-7a46aff3-bda9-44ff-9cd1-fefe995a45b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797789451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3797789451
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1385280936
Short name T849
Test name
Test status
Simulation time 304517104 ps
CPU time 11.45 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:01:52 PM PDT 24
Peak memory 216588 kb
Host smart-96d619f4-79f8-46bb-826e-be5fee8d9b4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385280936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1385280936
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.191501293
Short name T769
Test name
Test status
Simulation time 234326628 ps
CPU time 2.93 seconds
Started Mar 23 04:01:36 PM PDT 24
Finished Mar 23 04:01:39 PM PDT 24
Peak memory 222552 kb
Host smart-205bafe8-70a7-46dd-a61f-0eb6f58802ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191501293 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.191501293
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1121746213
Short name T1064
Test name
Test status
Simulation time 115001134 ps
CPU time 3.95 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:01:44 PM PDT 24
Peak memory 208724 kb
Host smart-612f1b09-b216-4bf1-add5-b4ec56cd3bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121746213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1121746213
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.4291265547
Short name T923
Test name
Test status
Simulation time 163075227 ps
CPU time 3.38 seconds
Started Mar 23 04:01:40 PM PDT 24
Finished Mar 23 04:01:44 PM PDT 24
Peak memory 210364 kb
Host smart-89c1756d-793d-446b-b6a2-88e7fd4339ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291265547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.4291265547
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3548486437
Short name T827
Test name
Test status
Simulation time 34869936 ps
CPU time 0.78 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:50 PM PDT 24
Peak memory 205844 kb
Host smart-cd55598b-0ae7-4542-8851-b44905345729
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548486437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3548486437
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2784764703
Short name T409
Test name
Test status
Simulation time 60814017 ps
CPU time 3.17 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:52 PM PDT 24
Peak memory 214304 kb
Host smart-137f06fe-89ab-4c0f-8147-db798be5414e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2784764703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2784764703
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1157931606
Short name T210
Test name
Test status
Simulation time 340456425 ps
CPU time 4.16 seconds
Started Mar 23 04:01:48 PM PDT 24
Finished Mar 23 04:01:52 PM PDT 24
Peak memory 209688 kb
Host smart-2d3b578b-9a1b-401c-be8e-d23601875ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157931606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1157931606
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2860002523
Short name T70
Test name
Test status
Simulation time 52403996 ps
CPU time 1.56 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:51 PM PDT 24
Peak memory 208328 kb
Host smart-e6d654b7-74b8-4bd7-bcce-d8f7a9e8355c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860002523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2860002523
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1948149436
Short name T330
Test name
Test status
Simulation time 58208461 ps
CPU time 3.74 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:53 PM PDT 24
Peak memory 220788 kb
Host smart-8c66805e-523f-48cd-abc9-8d148fa2fc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948149436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1948149436
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1364133646
Short name T991
Test name
Test status
Simulation time 93026120 ps
CPU time 1.8 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:51 PM PDT 24
Peak memory 206264 kb
Host smart-d14ecedf-4a86-4665-91b9-ee13121645f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364133646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1364133646
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.357364388
Short name T652
Test name
Test status
Simulation time 155168609 ps
CPU time 6.51 seconds
Started Mar 23 04:01:47 PM PDT 24
Finished Mar 23 04:01:54 PM PDT 24
Peak memory 207772 kb
Host smart-d018fe5d-287c-4b4a-b059-3221eed346e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357364388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.357364388
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.698675683
Short name T947
Test name
Test status
Simulation time 76276285 ps
CPU time 1.93 seconds
Started Mar 23 04:01:41 PM PDT 24
Finished Mar 23 04:01:43 PM PDT 24
Peak memory 207364 kb
Host smart-c8e5b1ff-5be4-4138-b37b-c83ddd80b653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698675683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.698675683
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3653180412
Short name T1044
Test name
Test status
Simulation time 65421109 ps
CPU time 3.4 seconds
Started Mar 23 04:01:35 PM PDT 24
Finished Mar 23 04:01:39 PM PDT 24
Peak memory 208784 kb
Host smart-ce0bc9f1-4c12-4270-9f0e-6da399c01e46
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653180412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3653180412
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2233197952
Short name T18
Test name
Test status
Simulation time 456728192 ps
CPU time 7.14 seconds
Started Mar 23 04:01:39 PM PDT 24
Finished Mar 23 04:01:46 PM PDT 24
Peak memory 208452 kb
Host smart-aa3dff79-84ab-45e6-8099-bff28fb1a42e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233197952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2233197952
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.957910260
Short name T626
Test name
Test status
Simulation time 112525029 ps
CPU time 3.5 seconds
Started Mar 23 04:01:37 PM PDT 24
Finished Mar 23 04:01:40 PM PDT 24
Peak memory 208480 kb
Host smart-b388a408-4f14-4f44-9f01-31002120f8cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957910260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.957910260
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.327917262
Short name T823
Test name
Test status
Simulation time 113224516 ps
CPU time 1.89 seconds
Started Mar 23 04:01:50 PM PDT 24
Finished Mar 23 04:01:52 PM PDT 24
Peak memory 208212 kb
Host smart-90cd8117-f9ef-46bd-90c7-7071b25ac6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327917262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.327917262
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3855892428
Short name T840
Test name
Test status
Simulation time 107581065 ps
CPU time 4.12 seconds
Started Mar 23 04:01:41 PM PDT 24
Finished Mar 23 04:01:46 PM PDT 24
Peak memory 206592 kb
Host smart-92279d4e-fe46-4751-80cf-78e8a62c2d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855892428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3855892428
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.4180717377
Short name T207
Test name
Test status
Simulation time 160664214 ps
CPU time 5.57 seconds
Started Mar 23 04:01:51 PM PDT 24
Finished Mar 23 04:01:57 PM PDT 24
Peak memory 222952 kb
Host smart-1ef00f00-16b0-495d-adec-0b6a9bd9d61f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180717377 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.4180717377
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.1971044729
Short name T1009
Test name
Test status
Simulation time 10546041953 ps
CPU time 70.77 seconds
Started Mar 23 04:01:51 PM PDT 24
Finished Mar 23 04:03:02 PM PDT 24
Peak memory 210036 kb
Host smart-322cc73c-08a2-4220-b993-1e61092d4bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971044729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.1971044729
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3548691081
Short name T808
Test name
Test status
Simulation time 84254682 ps
CPU time 3.15 seconds
Started Mar 23 04:01:47 PM PDT 24
Finished Mar 23 04:01:51 PM PDT 24
Peak memory 210572 kb
Host smart-85e0a2d8-0ac9-45c3-ace8-88b202647e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548691081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3548691081
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3793824296
Short name T1018
Test name
Test status
Simulation time 161467797 ps
CPU time 0.75 seconds
Started Mar 23 04:01:50 PM PDT 24
Finished Mar 23 04:01:51 PM PDT 24
Peak memory 205868 kb
Host smart-9ac3204e-94d0-4206-845c-bc40dffd779e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793824296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3793824296
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.495855316
Short name T412
Test name
Test status
Simulation time 2117988219 ps
CPU time 10.34 seconds
Started Mar 23 04:01:47 PM PDT 24
Finished Mar 23 04:01:57 PM PDT 24
Peak memory 215392 kb
Host smart-d4708865-0aaf-4982-884a-3d6107326b6f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=495855316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.495855316
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2498285765
Short name T27
Test name
Test status
Simulation time 140716890 ps
CPU time 5 seconds
Started Mar 23 04:01:50 PM PDT 24
Finished Mar 23 04:01:55 PM PDT 24
Peak memory 214628 kb
Host smart-27d8be88-8bc3-4395-a036-bc3c2d6e7f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498285765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2498285765
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.7068548
Short name T731
Test name
Test status
Simulation time 469658216 ps
CPU time 3.7 seconds
Started Mar 23 04:01:51 PM PDT 24
Finished Mar 23 04:01:54 PM PDT 24
Peak memory 209816 kb
Host smart-6f4979e9-f4be-4dd5-bbb9-eebe1f9b3037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7068548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.7068548
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.713001009
Short name T93
Test name
Test status
Simulation time 116359810 ps
CPU time 2.53 seconds
Started Mar 23 04:01:48 PM PDT 24
Finished Mar 23 04:01:50 PM PDT 24
Peak memory 211320 kb
Host smart-630dabe7-b684-4386-9e04-8a6d74c4d12c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713001009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.713001009
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3171812459
Short name T860
Test name
Test status
Simulation time 97456465 ps
CPU time 3.61 seconds
Started Mar 23 04:01:56 PM PDT 24
Finished Mar 23 04:02:00 PM PDT 24
Peak memory 215628 kb
Host smart-fd7fd789-5497-4791-87c7-9f4b141d58ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171812459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3171812459
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2326508427
Short name T1067
Test name
Test status
Simulation time 385168271 ps
CPU time 6.51 seconds
Started Mar 23 04:01:53 PM PDT 24
Finished Mar 23 04:01:59 PM PDT 24
Peak memory 210556 kb
Host smart-d18b54d5-36c9-40e2-aad4-6fe9ef06d716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326508427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2326508427
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3445935142
Short name T798
Test name
Test status
Simulation time 257510704 ps
CPU time 5.98 seconds
Started Mar 23 04:01:48 PM PDT 24
Finished Mar 23 04:01:54 PM PDT 24
Peak memory 206928 kb
Host smart-86c29f12-e668-4ca5-a3e9-4962fc45f2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445935142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3445935142
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2644036575
Short name T236
Test name
Test status
Simulation time 105790803 ps
CPU time 5.13 seconds
Started Mar 23 04:01:50 PM PDT 24
Finished Mar 23 04:01:55 PM PDT 24
Peak memory 208560 kb
Host smart-577b6a41-0513-4fb0-b14b-32af5f744475
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644036575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2644036575
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.812761228
Short name T322
Test name
Test status
Simulation time 1089024200 ps
CPU time 8.28 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:57 PM PDT 24
Peak memory 208600 kb
Host smart-a82eed85-d89a-4b4f-a605-ece6db339758
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812761228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.812761228
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.190923647
Short name T943
Test name
Test status
Simulation time 142793741 ps
CPU time 3.51 seconds
Started Mar 23 04:01:47 PM PDT 24
Finished Mar 23 04:01:50 PM PDT 24
Peak memory 208608 kb
Host smart-88d3a27f-6b50-42d2-be16-1d43a33fbf59
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190923647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.190923647
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3386001122
Short name T388
Test name
Test status
Simulation time 872022877 ps
CPU time 8.37 seconds
Started Mar 23 04:01:50 PM PDT 24
Finished Mar 23 04:01:58 PM PDT 24
Peak memory 214420 kb
Host smart-740693d6-6d8e-42b3-8583-374d9d771c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386001122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3386001122
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.4172827100
Short name T876
Test name
Test status
Simulation time 186875312 ps
CPU time 5.26 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:54 PM PDT 24
Peak memory 206976 kb
Host smart-78c5c43c-87dc-4d21-9c0a-1191723e81d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172827100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.4172827100
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3941112011
Short name T1015
Test name
Test status
Simulation time 180076951 ps
CPU time 6.82 seconds
Started Mar 23 04:01:47 PM PDT 24
Finished Mar 23 04:01:54 PM PDT 24
Peak memory 218076 kb
Host smart-948a28ca-588a-4a44-9a9f-eb6de2080020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941112011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3941112011
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2475330767
Short name T1024
Test name
Test status
Simulation time 2655574888 ps
CPU time 17.84 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:02:07 PM PDT 24
Peak memory 210476 kb
Host smart-1b2179e6-f37a-4634-aa45-dad355068633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475330767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2475330767
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3521497616
Short name T579
Test name
Test status
Simulation time 23802697 ps
CPU time 0.89 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:50 PM PDT 24
Peak memory 205864 kb
Host smart-26e01279-7cab-4344-80a2-5ea4478b4962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521497616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3521497616
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2421725122
Short name T9
Test name
Test status
Simulation time 600397937 ps
CPU time 3.54 seconds
Started Mar 23 04:01:47 PM PDT 24
Finished Mar 23 04:01:50 PM PDT 24
Peak memory 221108 kb
Host smart-7af2b8ac-6f77-49c2-856a-7d262becfd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421725122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2421725122
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3615465288
Short name T319
Test name
Test status
Simulation time 186618774 ps
CPU time 5.1 seconds
Started Mar 23 04:01:48 PM PDT 24
Finished Mar 23 04:01:53 PM PDT 24
Peak memory 214404 kb
Host smart-3cc49048-024f-4c30-a538-ae7e29217c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615465288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3615465288
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2468768764
Short name T373
Test name
Test status
Simulation time 4248326254 ps
CPU time 11.42 seconds
Started Mar 23 04:01:56 PM PDT 24
Finished Mar 23 04:02:08 PM PDT 24
Peak memory 222508 kb
Host smart-2a7a0fb6-a5b0-4239-8217-8c3ba731d359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468768764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2468768764
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3661412617
Short name T215
Test name
Test status
Simulation time 121256885 ps
CPU time 3.44 seconds
Started Mar 23 04:01:55 PM PDT 24
Finished Mar 23 04:01:58 PM PDT 24
Peak memory 214328 kb
Host smart-6f007148-abd1-4a50-8f30-d8c09ea91577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661412617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3661412617
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.504730869
Short name T755
Test name
Test status
Simulation time 436964356 ps
CPU time 4.08 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:54 PM PDT 24
Peak memory 207448 kb
Host smart-30bd6a8c-5e8d-4e72-a05a-e51d171786ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504730869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.504730869
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1070778136
Short name T187
Test name
Test status
Simulation time 27113448 ps
CPU time 2.07 seconds
Started Mar 23 04:01:50 PM PDT 24
Finished Mar 23 04:01:53 PM PDT 24
Peak memory 208704 kb
Host smart-5b86e86f-32db-4d2f-9139-9fe2532bebcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070778136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1070778136
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.689648895
Short name T666
Test name
Test status
Simulation time 165759377 ps
CPU time 4.8 seconds
Started Mar 23 04:01:48 PM PDT 24
Finished Mar 23 04:01:53 PM PDT 24
Peak memory 208404 kb
Host smart-4d1b5d15-58b4-40e3-aa88-1abc37a00ecf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689648895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.689648895
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1656284198
Short name T122
Test name
Test status
Simulation time 672842969 ps
CPU time 4.41 seconds
Started Mar 23 04:01:47 PM PDT 24
Finished Mar 23 04:01:52 PM PDT 24
Peak memory 208752 kb
Host smart-8d1162ba-5d11-4cec-b82c-cdc37d44db90
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656284198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1656284198
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1034458822
Short name T585
Test name
Test status
Simulation time 70389456 ps
CPU time 2.6 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:51 PM PDT 24
Peak memory 206964 kb
Host smart-b1b38825-4488-4606-b673-a273ef94e4f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034458822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1034458822
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.451371634
Short name T667
Test name
Test status
Simulation time 22079846 ps
CPU time 1.8 seconds
Started Mar 23 04:01:51 PM PDT 24
Finished Mar 23 04:01:53 PM PDT 24
Peak memory 209444 kb
Host smart-ababe95e-910c-40f3-a798-574b94567692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451371634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.451371634
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.151067872
Short name T785
Test name
Test status
Simulation time 195578208 ps
CPU time 3.55 seconds
Started Mar 23 04:01:56 PM PDT 24
Finished Mar 23 04:01:59 PM PDT 24
Peak memory 206852 kb
Host smart-2f1c75c7-28ae-4166-a9f7-c18795a2afdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151067872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.151067872
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.4208122555
Short name T705
Test name
Test status
Simulation time 1750044626 ps
CPU time 8.34 seconds
Started Mar 23 04:01:48 PM PDT 24
Finished Mar 23 04:01:56 PM PDT 24
Peak memory 222476 kb
Host smart-dbaa1ab0-26d0-49f3-a38f-1e564ebcd200
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208122555 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.4208122555
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2431048975
Short name T1051
Test name
Test status
Simulation time 120541317 ps
CPU time 2.62 seconds
Started Mar 23 04:01:51 PM PDT 24
Finished Mar 23 04:01:53 PM PDT 24
Peak memory 210300 kb
Host smart-3cfb314d-0ef2-417d-bae1-aac218e8a4af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431048975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2431048975
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3689784829
Short name T954
Test name
Test status
Simulation time 57065997 ps
CPU time 0.94 seconds
Started Mar 23 04:01:52 PM PDT 24
Finished Mar 23 04:01:53 PM PDT 24
Peak memory 205988 kb
Host smart-64ff6f37-132a-4a3d-b398-34fd2dc86c4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689784829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3689784829
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1321279647
Short name T399
Test name
Test status
Simulation time 69971402 ps
CPU time 4.78 seconds
Started Mar 23 04:01:55 PM PDT 24
Finished Mar 23 04:01:59 PM PDT 24
Peak memory 215476 kb
Host smart-981247ab-42af-4ced-bcc4-48f0ad683275
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1321279647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1321279647
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1183493719
Short name T1003
Test name
Test status
Simulation time 98438520 ps
CPU time 3.87 seconds
Started Mar 23 04:01:53 PM PDT 24
Finished Mar 23 04:01:57 PM PDT 24
Peak memory 216728 kb
Host smart-d74e8720-31b5-4235-b889-2ce7a020add2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183493719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1183493719
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.4188806176
Short name T323
Test name
Test status
Simulation time 87039630 ps
CPU time 3.04 seconds
Started Mar 23 04:01:53 PM PDT 24
Finished Mar 23 04:01:56 PM PDT 24
Peak memory 207468 kb
Host smart-a2d15e55-3469-478f-9dbe-c8cfe05aa603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188806176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4188806176
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3413863312
Short name T262
Test name
Test status
Simulation time 436041055 ps
CPU time 5.63 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:54 PM PDT 24
Peak memory 214388 kb
Host smart-912aff09-8015-4ebc-bc3b-2776653a6c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413863312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3413863312
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2857995330
Short name T58
Test name
Test status
Simulation time 156316394 ps
CPU time 3.85 seconds
Started Mar 23 04:01:52 PM PDT 24
Finished Mar 23 04:01:56 PM PDT 24
Peak memory 220428 kb
Host smart-2c6913d7-16fe-4e2d-9337-e4a5e941abda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857995330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2857995330
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2729819084
Short name T822
Test name
Test status
Simulation time 706237714 ps
CPU time 8.11 seconds
Started Mar 23 04:01:50 PM PDT 24
Finished Mar 23 04:01:59 PM PDT 24
Peak memory 218284 kb
Host smart-176bd094-d468-4d19-8087-3d836e4a285b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729819084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2729819084
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2506301717
Short name T799
Test name
Test status
Simulation time 560222273 ps
CPU time 6.48 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:56 PM PDT 24
Peak memory 207212 kb
Host smart-bd28a5e7-300d-405e-9929-7dd5700da643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506301717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2506301717
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1604708238
Short name T578
Test name
Test status
Simulation time 1668870375 ps
CPU time 21.47 seconds
Started Mar 23 04:01:48 PM PDT 24
Finished Mar 23 04:02:10 PM PDT 24
Peak memory 209064 kb
Host smart-4378e9b0-69a1-4feb-9363-4a807423397e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604708238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1604708238
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.4143589980
Short name T933
Test name
Test status
Simulation time 3380322884 ps
CPU time 25.93 seconds
Started Mar 23 04:01:47 PM PDT 24
Finished Mar 23 04:02:13 PM PDT 24
Peak memory 208276 kb
Host smart-a1176dbb-82ec-4f2e-9aca-82cda56853d3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143589980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.4143589980
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.937785503
Short name T951
Test name
Test status
Simulation time 62337176 ps
CPU time 3.1 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:52 PM PDT 24
Peak memory 209076 kb
Host smart-ef891991-fd65-437c-a9e8-7372daf54886
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937785503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.937785503
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2666043159
Short name T692
Test name
Test status
Simulation time 45289850 ps
CPU time 2.18 seconds
Started Mar 23 04:01:53 PM PDT 24
Finished Mar 23 04:01:55 PM PDT 24
Peak memory 216100 kb
Host smart-915aaa94-dce4-4752-9972-8e3df5f65204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666043159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2666043159
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1956935209
Short name T939
Test name
Test status
Simulation time 84420452 ps
CPU time 2.56 seconds
Started Mar 23 04:01:52 PM PDT 24
Finished Mar 23 04:01:55 PM PDT 24
Peak memory 207160 kb
Host smart-719033c5-ba08-4ce4-83c4-1587e56ad0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956935209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1956935209
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2903856031
Short name T47
Test name
Test status
Simulation time 1604414038 ps
CPU time 12.85 seconds
Started Mar 23 04:01:50 PM PDT 24
Finished Mar 23 04:02:03 PM PDT 24
Peak memory 222680 kb
Host smart-9302a93f-2df1-4687-a97a-257093646839
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903856031 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2903856031
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1901771872
Short name T237
Test name
Test status
Simulation time 1460429686 ps
CPU time 10.47 seconds
Started Mar 23 04:01:54 PM PDT 24
Finished Mar 23 04:02:04 PM PDT 24
Peak memory 218580 kb
Host smart-7dd6f1f6-ebdc-43c5-9bc2-2ca7d0f8eb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901771872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1901771872
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.55365000
Short name T899
Test name
Test status
Simulation time 169942502 ps
CPU time 2.86 seconds
Started Mar 23 04:01:55 PM PDT 24
Finished Mar 23 04:01:58 PM PDT 24
Peak memory 209952 kb
Host smart-6a358e78-6040-4ec2-8d5c-74a59386accc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55365000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.55365000
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1100763254
Short name T741
Test name
Test status
Simulation time 84023223 ps
CPU time 1.01 seconds
Started Mar 23 04:02:06 PM PDT 24
Finished Mar 23 04:02:07 PM PDT 24
Peak memory 205884 kb
Host smart-d3b089d4-128d-4adb-90be-cc1aa3b768dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100763254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1100763254
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.4060324885
Short name T416
Test name
Test status
Simulation time 50225181 ps
CPU time 3.68 seconds
Started Mar 23 04:01:59 PM PDT 24
Finished Mar 23 04:02:03 PM PDT 24
Peak memory 215232 kb
Host smart-99a5f75c-b969-4e76-a1c2-e958132d1033
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4060324885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.4060324885
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3838596904
Short name T19
Test name
Test status
Simulation time 131650328 ps
CPU time 3.55 seconds
Started Mar 23 04:02:03 PM PDT 24
Finished Mar 23 04:02:08 PM PDT 24
Peak memory 214592 kb
Host smart-fa60c37e-7f5b-4726-8a6d-96cce86067ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838596904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3838596904
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2880275675
Short name T651
Test name
Test status
Simulation time 176639804 ps
CPU time 2.17 seconds
Started Mar 23 04:01:59 PM PDT 24
Finished Mar 23 04:02:01 PM PDT 24
Peak memory 207864 kb
Host smart-bd4c8d45-6ba3-4c77-8e44-493b20e26791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880275675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2880275675
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3158404835
Short name T315
Test name
Test status
Simulation time 246410812 ps
CPU time 3.31 seconds
Started Mar 23 04:01:59 PM PDT 24
Finished Mar 23 04:02:02 PM PDT 24
Peak memory 218404 kb
Host smart-6afcf90d-4ffa-44a6-bd12-223e1f3abf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158404835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3158404835
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3284644508
Short name T95
Test name
Test status
Simulation time 283607910 ps
CPU time 8.83 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:09 PM PDT 24
Peak memory 210140 kb
Host smart-cd48e010-8b70-4f69-8987-1238b0815d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284644508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3284644508
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.796419093
Short name T55
Test name
Test status
Simulation time 56806754 ps
CPU time 4.07 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:04 PM PDT 24
Peak memory 220100 kb
Host smart-7d3f4ca2-79b9-43e8-b4c2-9276c5adbc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796419093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.796419093
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3822400910
Short name T193
Test name
Test status
Simulation time 3924220732 ps
CPU time 54.37 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:54 PM PDT 24
Peak memory 218560 kb
Host smart-351fceb1-3121-4239-989f-63b153b4e5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822400910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3822400910
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3133725482
Short name T941
Test name
Test status
Simulation time 185927436 ps
CPU time 5.61 seconds
Started Mar 23 04:01:49 PM PDT 24
Finished Mar 23 04:01:55 PM PDT 24
Peak memory 208428 kb
Host smart-ededf28e-5f16-46ac-809e-555b3b9dce50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133725482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3133725482
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.4273319795
Short name T615
Test name
Test status
Simulation time 53262428 ps
CPU time 2.69 seconds
Started Mar 23 04:01:58 PM PDT 24
Finished Mar 23 04:02:01 PM PDT 24
Peak memory 208480 kb
Host smart-00dbeb2c-0b3d-4bae-a8c0-5023af152ec7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273319795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.4273319795
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.922735635
Short name T191
Test name
Test status
Simulation time 79866726 ps
CPU time 3.08 seconds
Started Mar 23 04:01:51 PM PDT 24
Finished Mar 23 04:01:54 PM PDT 24
Peak memory 206908 kb
Host smart-723b4915-1895-4b54-beea-5db79c9deb08
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922735635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.922735635
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.469783699
Short name T569
Test name
Test status
Simulation time 63415622 ps
CPU time 1.54 seconds
Started Mar 23 04:02:01 PM PDT 24
Finished Mar 23 04:02:04 PM PDT 24
Peak memory 208164 kb
Host smart-0f6ef478-78b9-428b-b019-bffab3c61214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469783699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.469783699
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1957205322
Short name T184
Test name
Test status
Simulation time 72028520 ps
CPU time 1.87 seconds
Started Mar 23 04:01:51 PM PDT 24
Finished Mar 23 04:01:53 PM PDT 24
Peak memory 206872 kb
Host smart-7abb542b-10c2-43c1-8566-07b74ee8c81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957205322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1957205322
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.562205974
Short name T239
Test name
Test status
Simulation time 1503964407 ps
CPU time 31.26 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:32 PM PDT 24
Peak memory 222420 kb
Host smart-158aae15-8a15-4236-8fcf-fa5eebebee8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562205974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.562205974
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3115578040
Short name T787
Test name
Test status
Simulation time 164564830 ps
CPU time 6.53 seconds
Started Mar 23 04:02:06 PM PDT 24
Finished Mar 23 04:02:13 PM PDT 24
Peak memory 222480 kb
Host smart-f5592f8d-3dca-4a66-a650-4ec4f8c81e21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115578040 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3115578040
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.108183603
Short name T707
Test name
Test status
Simulation time 830313873 ps
CPU time 6.85 seconds
Started Mar 23 04:02:04 PM PDT 24
Finished Mar 23 04:02:12 PM PDT 24
Peak memory 209100 kb
Host smart-d5b0d9f6-835e-41aa-8d26-57a65f5ce3eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108183603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.108183603
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1901051575
Short name T1052
Test name
Test status
Simulation time 72138044 ps
CPU time 2.8 seconds
Started Mar 23 04:02:03 PM PDT 24
Finished Mar 23 04:02:07 PM PDT 24
Peak memory 210408 kb
Host smart-18442478-3bbc-4223-bea1-b7f4c1d40cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901051575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1901051575
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3764716563
Short name T616
Test name
Test status
Simulation time 34446796 ps
CPU time 0.8 seconds
Started Mar 23 04:02:04 PM PDT 24
Finished Mar 23 04:02:06 PM PDT 24
Peak memory 206056 kb
Host smart-d0d25c69-9236-43fc-9daf-624caccdfa58
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764716563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3764716563
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2318217044
Short name T225
Test name
Test status
Simulation time 236427689 ps
CPU time 4.74 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:06 PM PDT 24
Peak memory 215412 kb
Host smart-89b9232e-7d57-49a7-84a7-c052f0c18a38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2318217044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2318217044
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1934534963
Short name T691
Test name
Test status
Simulation time 174874362 ps
CPU time 2.18 seconds
Started Mar 23 04:02:02 PM PDT 24
Finished Mar 23 04:02:04 PM PDT 24
Peak memory 220572 kb
Host smart-9a9cb266-6ac6-4999-babd-2a7beae74329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934534963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1934534963
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1102178949
Short name T932
Test name
Test status
Simulation time 114269302 ps
CPU time 2.04 seconds
Started Mar 23 04:02:04 PM PDT 24
Finished Mar 23 04:02:07 PM PDT 24
Peak memory 208204 kb
Host smart-485e6a21-9873-4b3d-ad60-a4106f1b0b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102178949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1102178949
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1786253239
Short name T660
Test name
Test status
Simulation time 1459457362 ps
CPU time 8.71 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:09 PM PDT 24
Peak memory 208476 kb
Host smart-8a08ee68-5117-47c4-9ffc-598424e95625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786253239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1786253239
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2380089869
Short name T254
Test name
Test status
Simulation time 173616794 ps
CPU time 5.54 seconds
Started Mar 23 04:01:58 PM PDT 24
Finished Mar 23 04:02:03 PM PDT 24
Peak memory 222428 kb
Host smart-5efba1bf-c3a9-4f44-b849-e24b683c95e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380089869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2380089869
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.4273160147
Short name T704
Test name
Test status
Simulation time 124861219 ps
CPU time 2.79 seconds
Started Mar 23 04:02:02 PM PDT 24
Finished Mar 23 04:02:05 PM PDT 24
Peak memory 209660 kb
Host smart-cca26e8e-3210-451c-a815-5ae5455f2a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273160147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.4273160147
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1265405020
Short name T133
Test name
Test status
Simulation time 113251750 ps
CPU time 3.74 seconds
Started Mar 23 04:02:06 PM PDT 24
Finished Mar 23 04:02:10 PM PDT 24
Peak memory 207720 kb
Host smart-ebf53f76-d550-4386-a86a-1afea2770aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265405020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1265405020
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1278872451
Short name T82
Test name
Test status
Simulation time 358191950 ps
CPU time 4.2 seconds
Started Mar 23 04:02:02 PM PDT 24
Finished Mar 23 04:02:07 PM PDT 24
Peak memory 208584 kb
Host smart-2066f1cb-7e2f-4dba-a096-83c0e134e1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278872451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1278872451
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.52335804
Short name T132
Test name
Test status
Simulation time 272905299 ps
CPU time 6.63 seconds
Started Mar 23 04:01:59 PM PDT 24
Finished Mar 23 04:02:05 PM PDT 24
Peak memory 208532 kb
Host smart-6e810e4a-64c2-45aa-9427-87b3fa02725d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52335804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.52335804
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2086207009
Short name T925
Test name
Test status
Simulation time 307515202 ps
CPU time 5.05 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:06 PM PDT 24
Peak memory 208160 kb
Host smart-a6c46f0a-fe92-4ffc-b5d6-d97620486244
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086207009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2086207009
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.3728803985
Short name T196
Test name
Test status
Simulation time 175886480 ps
CPU time 5.39 seconds
Started Mar 23 04:02:02 PM PDT 24
Finished Mar 23 04:02:09 PM PDT 24
Peak memory 208324 kb
Host smart-dc3bfc1b-398d-41cd-bcc8-80775c53462f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728803985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.3728803985
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1497545656
Short name T363
Test name
Test status
Simulation time 63687351 ps
CPU time 1.66 seconds
Started Mar 23 04:02:08 PM PDT 24
Finished Mar 23 04:02:09 PM PDT 24
Peak memory 207756 kb
Host smart-e6150fc2-bc38-43c5-89bc-8bf225b45d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497545656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1497545656
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2142883088
Short name T893
Test name
Test status
Simulation time 6219314285 ps
CPU time 33.19 seconds
Started Mar 23 04:02:04 PM PDT 24
Finished Mar 23 04:02:38 PM PDT 24
Peak memory 208080 kb
Host smart-e8019248-a4f3-410c-bbbc-d41a7731f17a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142883088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2142883088
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2289939689
Short name T891
Test name
Test status
Simulation time 28187110293 ps
CPU time 51.64 seconds
Started Mar 23 04:02:04 PM PDT 24
Finished Mar 23 04:02:57 PM PDT 24
Peak memory 216316 kb
Host smart-56e727d7-4cae-40b8-8d0f-b93691d53c03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289939689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2289939689
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3524780270
Short name T694
Test name
Test status
Simulation time 150288542 ps
CPU time 5 seconds
Started Mar 23 04:01:59 PM PDT 24
Finished Mar 23 04:02:04 PM PDT 24
Peak memory 222584 kb
Host smart-ed34466c-c36c-4021-bde4-e4ff84d97aa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524780270 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3524780270
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.284451214
Short name T16
Test name
Test status
Simulation time 280288057 ps
CPU time 6.59 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:07 PM PDT 24
Peak memory 208012 kb
Host smart-4be12ec5-bf02-45a8-b452-23d36cc0ce94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284451214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.284451214
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.4157726316
Short name T934
Test name
Test status
Simulation time 83056920 ps
CPU time 3.36 seconds
Started Mar 23 04:02:09 PM PDT 24
Finished Mar 23 04:02:13 PM PDT 24
Peak memory 214244 kb
Host smart-a423fb1d-6afd-4bfa-a9b6-60e43cef8d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157726316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.4157726316
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2297071631
Short name T812
Test name
Test status
Simulation time 14474583 ps
CPU time 0.71 seconds
Started Mar 23 03:59:57 PM PDT 24
Finished Mar 23 03:59:58 PM PDT 24
Peak memory 205860 kb
Host smart-a89acea4-88c4-4ef8-bac1-bd28cdcb9a06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297071631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2297071631
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.927892215
Short name T1020
Test name
Test status
Simulation time 96358438 ps
CPU time 4.37 seconds
Started Mar 23 03:59:57 PM PDT 24
Finished Mar 23 04:00:02 PM PDT 24
Peak memory 214684 kb
Host smart-7fc23234-d41b-46c6-b15d-5b4d1591e6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927892215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.927892215
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3511494273
Short name T14
Test name
Test status
Simulation time 105491909 ps
CPU time 2.15 seconds
Started Mar 23 04:00:06 PM PDT 24
Finished Mar 23 04:00:09 PM PDT 24
Peak memory 207644 kb
Host smart-9c08cab7-3b5e-4dbc-9e1f-e50622cfc756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511494273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3511494273
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.2230572506
Short name T909
Test name
Test status
Simulation time 707590383 ps
CPU time 8.28 seconds
Started Mar 23 04:00:06 PM PDT 24
Finished Mar 23 04:00:14 PM PDT 24
Peak memory 209060 kb
Host smart-f69aa624-c03f-46b0-91d2-bf896be4d14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230572506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.2230572506
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.627861679
Short name T751
Test name
Test status
Simulation time 397304627 ps
CPU time 4.08 seconds
Started Mar 23 04:00:00 PM PDT 24
Finished Mar 23 04:00:04 PM PDT 24
Peak memory 212272 kb
Host smart-70d8fb23-30e6-411e-9551-661e882c92bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627861679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.627861679
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3953637614
Short name T6
Test name
Test status
Simulation time 75049529 ps
CPU time 3.95 seconds
Started Mar 23 03:59:56 PM PDT 24
Finished Mar 23 04:00:00 PM PDT 24
Peak memory 218020 kb
Host smart-11e3740e-f8a0-462a-a635-2c4699464915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953637614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3953637614
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2890076785
Short name T194
Test name
Test status
Simulation time 241557448 ps
CPU time 3.07 seconds
Started Mar 23 03:59:56 PM PDT 24
Finished Mar 23 03:59:59 PM PDT 24
Peak memory 207504 kb
Host smart-c6c07ab6-b01f-4f55-a22c-e0da73d05dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890076785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2890076785
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2678907879
Short name T13
Test name
Test status
Simulation time 622066024 ps
CPU time 12.08 seconds
Started Mar 23 04:00:00 PM PDT 24
Finished Mar 23 04:00:12 PM PDT 24
Peak memory 230752 kb
Host smart-d58f12e2-0580-48ac-a2f5-861efca63cd2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678907879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2678907879
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2966661740
Short name T584
Test name
Test status
Simulation time 430441748 ps
CPU time 2.97 seconds
Started Mar 23 04:00:06 PM PDT 24
Finished Mar 23 04:00:09 PM PDT 24
Peak memory 206936 kb
Host smart-de6787f2-0626-455c-939f-4d8d47fb80d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966661740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2966661740
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2444557225
Short name T582
Test name
Test status
Simulation time 109716230 ps
CPU time 2.77 seconds
Started Mar 23 03:59:58 PM PDT 24
Finished Mar 23 04:00:01 PM PDT 24
Peak memory 208676 kb
Host smart-a8a87da2-73d7-4cab-9e7f-8f3633ee1c3f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444557225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2444557225
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3851660209
Short name T345
Test name
Test status
Simulation time 23712619 ps
CPU time 2 seconds
Started Mar 23 04:00:06 PM PDT 24
Finished Mar 23 04:00:08 PM PDT 24
Peak memory 207460 kb
Host smart-68205cc2-9271-436e-8a96-0ff5caa4ebf6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851660209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3851660209
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2705938431
Short name T728
Test name
Test status
Simulation time 2649571227 ps
CPU time 32.76 seconds
Started Mar 23 03:59:59 PM PDT 24
Finished Mar 23 04:00:32 PM PDT 24
Peak memory 208684 kb
Host smart-d3c7b0b5-be69-4e44-9529-773c342c3da1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705938431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2705938431
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.68843539
Short name T219
Test name
Test status
Simulation time 31880417 ps
CPU time 2.39 seconds
Started Mar 23 03:59:58 PM PDT 24
Finished Mar 23 04:00:00 PM PDT 24
Peak memory 209784 kb
Host smart-bf5dd766-88ec-401f-9e6a-364ce80bbf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68843539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.68843539
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2575605470
Short name T845
Test name
Test status
Simulation time 31145227 ps
CPU time 2.05 seconds
Started Mar 23 03:59:58 PM PDT 24
Finished Mar 23 04:00:01 PM PDT 24
Peak memory 208332 kb
Host smart-935caa42-493d-4b0c-9eb0-83f05c6a9c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575605470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2575605470
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.942949344
Short name T375
Test name
Test status
Simulation time 3289530544 ps
CPU time 26.68 seconds
Started Mar 23 04:00:10 PM PDT 24
Finished Mar 23 04:00:37 PM PDT 24
Peak memory 221604 kb
Host smart-e40ab08f-b3ee-4222-bd13-9b05c32bc746
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942949344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.942949344
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.896266496
Short name T740
Test name
Test status
Simulation time 76989569 ps
CPU time 2.25 seconds
Started Mar 23 03:59:58 PM PDT 24
Finished Mar 23 04:00:00 PM PDT 24
Peak memory 220908 kb
Host smart-c367e661-0f0d-4c52-a8eb-b16e87eb7220
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896266496 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.896266496
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3843700056
Short name T228
Test name
Test status
Simulation time 304119304 ps
CPU time 9.16 seconds
Started Mar 23 04:00:08 PM PDT 24
Finished Mar 23 04:00:17 PM PDT 24
Peak memory 218220 kb
Host smart-8a7cbdc9-7d82-4b84-9402-3d75aec73586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843700056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3843700056
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3511581298
Short name T1078
Test name
Test status
Simulation time 2629369968 ps
CPU time 11.55 seconds
Started Mar 23 03:59:58 PM PDT 24
Finished Mar 23 04:00:09 PM PDT 24
Peak memory 211256 kb
Host smart-bd6f1737-3d17-4120-8da1-a82b5b7b0871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511581298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3511581298
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2874128834
Short name T605
Test name
Test status
Simulation time 46530921 ps
CPU time 0.9 seconds
Started Mar 23 04:02:01 PM PDT 24
Finished Mar 23 04:02:03 PM PDT 24
Peak memory 205884 kb
Host smart-51a638e1-5ec7-43d5-8729-4d9a0f79209a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874128834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2874128834
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.2262769173
Short name T303
Test name
Test status
Simulation time 58716620 ps
CPU time 4.15 seconds
Started Mar 23 04:02:09 PM PDT 24
Finished Mar 23 04:02:13 PM PDT 24
Peak memory 215404 kb
Host smart-885f8f5f-b196-4e72-9b0a-5f3e07d9b98f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2262769173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.2262769173
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2707921847
Short name T203
Test name
Test status
Simulation time 646250281 ps
CPU time 5.03 seconds
Started Mar 23 04:02:01 PM PDT 24
Finished Mar 23 04:02:07 PM PDT 24
Peak memory 214640 kb
Host smart-35ba4d32-3e15-40df-b754-5eb9d3efacfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707921847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2707921847
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2424251617
Short name T803
Test name
Test status
Simulation time 90081197 ps
CPU time 4.36 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:05 PM PDT 24
Peak memory 218304 kb
Host smart-8e6bf1b2-0cfb-45ff-b0b5-093fa4067844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424251617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2424251617
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1921285428
Short name T241
Test name
Test status
Simulation time 309232819 ps
CPU time 5.47 seconds
Started Mar 23 04:02:05 PM PDT 24
Finished Mar 23 04:02:11 PM PDT 24
Peak memory 218276 kb
Host smart-fa01a775-d0c3-4515-bf46-d2d652ce4dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921285428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1921285428
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2324906962
Short name T185
Test name
Test status
Simulation time 344011023 ps
CPU time 11.32 seconds
Started Mar 23 04:02:08 PM PDT 24
Finished Mar 23 04:02:20 PM PDT 24
Peak memory 214260 kb
Host smart-97af9412-7680-4fa0-818a-527a38fe07d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324906962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2324906962
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.375032566
Short name T1065
Test name
Test status
Simulation time 252941902 ps
CPU time 4.33 seconds
Started Mar 23 04:02:04 PM PDT 24
Finished Mar 23 04:02:09 PM PDT 24
Peak memory 214348 kb
Host smart-60e93dd4-f975-44e2-af15-6456619d918b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375032566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.375032566
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.956305277
Short name T829
Test name
Test status
Simulation time 309766194 ps
CPU time 3.85 seconds
Started Mar 23 04:01:58 PM PDT 24
Finished Mar 23 04:02:02 PM PDT 24
Peak memory 209952 kb
Host smart-1905af3e-9aca-4221-8385-5ac1a512d681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956305277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.956305277
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.230153794
Short name T863
Test name
Test status
Simulation time 1118246778 ps
CPU time 28.35 seconds
Started Mar 23 04:01:58 PM PDT 24
Finished Mar 23 04:02:26 PM PDT 24
Peak memory 208688 kb
Host smart-facce70c-a347-493f-b155-ebba3d2fc129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230153794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.230153794
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3082203855
Short name T784
Test name
Test status
Simulation time 438192878 ps
CPU time 3.79 seconds
Started Mar 23 04:02:05 PM PDT 24
Finished Mar 23 04:02:10 PM PDT 24
Peak memory 206972 kb
Host smart-05a5cc94-f9c9-47d0-86f0-f23ce0b419f2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082203855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3082203855
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2121980181
Short name T145
Test name
Test status
Simulation time 221736196 ps
CPU time 3.98 seconds
Started Mar 23 04:02:02 PM PDT 24
Finished Mar 23 04:02:08 PM PDT 24
Peak memory 208676 kb
Host smart-6188c986-fddc-45f6-9f79-bd7c1b3ce8fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121980181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2121980181
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2751892974
Short name T978
Test name
Test status
Simulation time 546643188 ps
CPU time 5.13 seconds
Started Mar 23 04:02:07 PM PDT 24
Finished Mar 23 04:02:13 PM PDT 24
Peak memory 206996 kb
Host smart-2445b49b-8810-406e-a2ac-40add77f8b04
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751892974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2751892974
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.619535958
Short name T600
Test name
Test status
Simulation time 124433306 ps
CPU time 1.62 seconds
Started Mar 23 04:01:59 PM PDT 24
Finished Mar 23 04:02:01 PM PDT 24
Peak memory 208232 kb
Host smart-85494743-b044-4c82-95bd-1b1eee004b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619535958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.619535958
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1236061083
Short name T1062
Test name
Test status
Simulation time 265511790 ps
CPU time 3.44 seconds
Started Mar 23 04:02:04 PM PDT 24
Finished Mar 23 04:02:08 PM PDT 24
Peak memory 208536 kb
Host smart-66515d1b-20ca-4cbf-8a21-4e68013c5570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236061083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1236061083
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1590662888
Short name T708
Test name
Test status
Simulation time 83746520 ps
CPU time 3.2 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:04 PM PDT 24
Peak memory 221312 kb
Host smart-ff0cd158-683f-4137-afc1-20bc835b4912
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590662888 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1590662888
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.738856896
Short name T1077
Test name
Test status
Simulation time 3395189792 ps
CPU time 23.6 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:23 PM PDT 24
Peak memory 209564 kb
Host smart-cca50a89-0a7f-4a8a-bdd1-822d847bc0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738856896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.738856896
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.307891556
Short name T402
Test name
Test status
Simulation time 105748398 ps
CPU time 2.45 seconds
Started Mar 23 04:02:06 PM PDT 24
Finished Mar 23 04:02:09 PM PDT 24
Peak memory 210308 kb
Host smart-e6b8cf9a-0bc2-4b71-9289-ebe1ba58cbeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307891556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.307891556
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1059420276
Short name T738
Test name
Test status
Simulation time 49525225 ps
CPU time 0.76 seconds
Started Mar 23 04:02:05 PM PDT 24
Finished Mar 23 04:02:07 PM PDT 24
Peak memory 205892 kb
Host smart-ab9f4fd6-c89b-46f5-b314-d643f065b160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059420276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1059420276
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2851265078
Short name T355
Test name
Test status
Simulation time 736612953 ps
CPU time 10.9 seconds
Started Mar 23 04:02:05 PM PDT 24
Finished Mar 23 04:02:17 PM PDT 24
Peak memory 214968 kb
Host smart-5a76418e-8650-4572-9b5d-8c897e17c28b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2851265078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2851265078
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3742574631
Short name T26
Test name
Test status
Simulation time 129071337 ps
CPU time 3.6 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:03 PM PDT 24
Peak memory 209296 kb
Host smart-31584e15-24c2-4083-aff2-013bad242d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742574631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3742574631
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.4287374813
Short name T1041
Test name
Test status
Simulation time 39248172 ps
CPU time 2.08 seconds
Started Mar 23 04:02:08 PM PDT 24
Finished Mar 23 04:02:10 PM PDT 24
Peak memory 214308 kb
Host smart-45902bdb-3be3-4bdb-becd-bd0753f142ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287374813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.4287374813
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3523912720
Short name T87
Test name
Test status
Simulation time 1001526345 ps
CPU time 10.86 seconds
Started Mar 23 04:01:59 PM PDT 24
Finished Mar 23 04:02:10 PM PDT 24
Peak memory 209620 kb
Host smart-c831061e-7857-4d0a-8011-1114e722492b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523912720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3523912720
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3155760322
Short name T1056
Test name
Test status
Simulation time 317893032 ps
CPU time 5.74 seconds
Started Mar 23 04:01:57 PM PDT 24
Finished Mar 23 04:02:03 PM PDT 24
Peak memory 222392 kb
Host smart-366dc08c-9ca4-4167-bccd-a0a3fbcb500e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155760322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3155760322
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2666268728
Short name T395
Test name
Test status
Simulation time 195644987 ps
CPU time 3.1 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:03 PM PDT 24
Peak memory 219796 kb
Host smart-fca7f7c2-ff89-4383-98cc-9ecd8c785df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666268728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2666268728
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1686674748
Short name T242
Test name
Test status
Simulation time 124628211 ps
CPU time 5.97 seconds
Started Mar 23 04:02:09 PM PDT 24
Finished Mar 23 04:02:15 PM PDT 24
Peak memory 210224 kb
Host smart-889cce56-334f-4427-8012-71fa3d2b80ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686674748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1686674748
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1682573882
Short name T623
Test name
Test status
Simulation time 48855853 ps
CPU time 2.87 seconds
Started Mar 23 04:02:02 PM PDT 24
Finished Mar 23 04:02:06 PM PDT 24
Peak memory 206900 kb
Host smart-23d2270b-2077-4422-9bf6-3dcffd02c55d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682573882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1682573882
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1072722556
Short name T632
Test name
Test status
Simulation time 187836398 ps
CPU time 2.66 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:02 PM PDT 24
Peak memory 207384 kb
Host smart-ed30c7fb-6eb6-4dd1-aa90-7228b10ed3d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072722556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1072722556
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2395082606
Short name T618
Test name
Test status
Simulation time 23938843 ps
CPU time 2.02 seconds
Started Mar 23 04:02:03 PM PDT 24
Finished Mar 23 04:02:06 PM PDT 24
Peak memory 206932 kb
Host smart-14422a55-c070-4e77-b7a2-695d7b32008b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395082606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2395082606
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1612007089
Short name T223
Test name
Test status
Simulation time 124927855 ps
CPU time 3.15 seconds
Started Mar 23 04:02:04 PM PDT 24
Finished Mar 23 04:02:08 PM PDT 24
Peak memory 208492 kb
Host smart-a904886d-a214-4073-b8f4-d6372f55b15a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612007089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1612007089
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1169011821
Short name T394
Test name
Test status
Simulation time 105931330 ps
CPU time 2.73 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:03 PM PDT 24
Peak memory 208584 kb
Host smart-05522250-a0ed-440c-85e5-ac9ee11d23e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169011821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1169011821
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.825893990
Short name T883
Test name
Test status
Simulation time 536809130 ps
CPU time 24.39 seconds
Started Mar 23 04:02:06 PM PDT 24
Finished Mar 23 04:02:32 PM PDT 24
Peak memory 215868 kb
Host smart-43b315b6-31de-4e20-b873-fcc4602093aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825893990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.825893990
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2661333580
Short name T389
Test name
Test status
Simulation time 161454686 ps
CPU time 5.39 seconds
Started Mar 23 04:02:04 PM PDT 24
Finished Mar 23 04:02:10 PM PDT 24
Peak memory 219296 kb
Host smart-c4888c2d-cf06-4361-a549-7303d4b59404
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661333580 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2661333580
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2829183784
Short name T347
Test name
Test status
Simulation time 619266465 ps
CPU time 7.14 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:08 PM PDT 24
Peak memory 209364 kb
Host smart-b1211b13-b31d-4dc4-82dd-86de866f8623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829183784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2829183784
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2750850152
Short name T51
Test name
Test status
Simulation time 3082039565 ps
CPU time 6.42 seconds
Started Mar 23 04:02:08 PM PDT 24
Finished Mar 23 04:02:14 PM PDT 24
Peak memory 211052 kb
Host smart-084297d5-1ed7-4bdf-8742-176f49ca0c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750850152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2750850152
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1348670641
Short name T580
Test name
Test status
Simulation time 11253561 ps
CPU time 0.89 seconds
Started Mar 23 04:02:13 PM PDT 24
Finished Mar 23 04:02:14 PM PDT 24
Peak memory 205860 kb
Host smart-8c95cad5-4da7-48eb-b561-aeeaeb89e3ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348670641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1348670641
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.8053610
Short name T426
Test name
Test status
Simulation time 734584192 ps
CPU time 18.7 seconds
Started Mar 23 04:02:16 PM PDT 24
Finished Mar 23 04:02:36 PM PDT 24
Peak memory 215788 kb
Host smart-4bcca127-a072-4ae4-abda-2cce66d7a8ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=8053610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.8053610
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3988924000
Short name T62
Test name
Test status
Simulation time 1759190699 ps
CPU time 10.83 seconds
Started Mar 23 04:02:11 PM PDT 24
Finished Mar 23 04:02:22 PM PDT 24
Peak memory 214596 kb
Host smart-323a3568-78a5-4cbd-923d-68677b1ddb93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988924000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3988924000
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3330374274
Short name T990
Test name
Test status
Simulation time 26522287 ps
CPU time 1.91 seconds
Started Mar 23 04:02:14 PM PDT 24
Finished Mar 23 04:02:16 PM PDT 24
Peak memory 209480 kb
Host smart-27737b0c-a008-47b8-bab7-326c87fc3ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330374274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3330374274
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.558923325
Short name T329
Test name
Test status
Simulation time 156602490 ps
CPU time 4.12 seconds
Started Mar 23 04:02:13 PM PDT 24
Finished Mar 23 04:02:17 PM PDT 24
Peak memory 214372 kb
Host smart-cb9de8e0-747c-4f14-99fd-0f0311bacb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558923325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.558923325
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3037356316
Short name T273
Test name
Test status
Simulation time 121604196 ps
CPU time 3.84 seconds
Started Mar 23 04:02:23 PM PDT 24
Finished Mar 23 04:02:26 PM PDT 24
Peak memory 214292 kb
Host smart-90675aa4-0a75-4c4b-9692-0475c09b0a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037356316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3037356316
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.2751785265
Short name T813
Test name
Test status
Simulation time 131368261 ps
CPU time 3.83 seconds
Started Mar 23 04:02:11 PM PDT 24
Finished Mar 23 04:02:15 PM PDT 24
Peak memory 220004 kb
Host smart-4181a74d-b3f9-4001-8e08-21d0b90c93aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751785265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2751785265
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3090925628
Short name T654
Test name
Test status
Simulation time 97157851 ps
CPU time 4.85 seconds
Started Mar 23 04:02:03 PM PDT 24
Finished Mar 23 04:02:09 PM PDT 24
Peak memory 208236 kb
Host smart-47291cfe-6e29-48c2-a40d-be91991e9a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090925628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3090925628
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.156744302
Short name T130
Test name
Test status
Simulation time 86597367 ps
CPU time 1.82 seconds
Started Mar 23 04:02:03 PM PDT 24
Finished Mar 23 04:02:05 PM PDT 24
Peak memory 207172 kb
Host smart-264e251e-3130-4a69-b4d3-659a14d74d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156744302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.156744302
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.255544495
Short name T397
Test name
Test status
Simulation time 428029516 ps
CPU time 6.72 seconds
Started Mar 23 04:02:09 PM PDT 24
Finished Mar 23 04:02:16 PM PDT 24
Peak memory 207716 kb
Host smart-a452113e-16b5-4090-8a70-03c3b35a042f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255544495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.255544495
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.267244947
Short name T871
Test name
Test status
Simulation time 6684140258 ps
CPU time 39.68 seconds
Started Mar 23 04:02:00 PM PDT 24
Finished Mar 23 04:02:40 PM PDT 24
Peak memory 208376 kb
Host smart-3529b132-e085-4dde-803c-228a4c4d63e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267244947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.267244947
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3269911362
Short name T700
Test name
Test status
Simulation time 1095589323 ps
CPU time 7.85 seconds
Started Mar 23 04:02:08 PM PDT 24
Finished Mar 23 04:02:16 PM PDT 24
Peak memory 207884 kb
Host smart-9233d5f8-ccc1-49b6-b9ee-7face9dcddb0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269911362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3269911362
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2502667864
Short name T862
Test name
Test status
Simulation time 60094778 ps
CPU time 1.68 seconds
Started Mar 23 04:02:10 PM PDT 24
Finished Mar 23 04:02:12 PM PDT 24
Peak memory 207936 kb
Host smart-75d9a596-5f08-41f2-81da-ea539db50314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502667864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2502667864
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.689144835
Short name T715
Test name
Test status
Simulation time 35080683 ps
CPU time 2.52 seconds
Started Mar 23 04:02:06 PM PDT 24
Finished Mar 23 04:02:09 PM PDT 24
Peak memory 206688 kb
Host smart-539df3b8-971a-4f19-b2d3-5f93c654336b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689144835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.689144835
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3599046017
Short name T197
Test name
Test status
Simulation time 304370049 ps
CPU time 8.88 seconds
Started Mar 23 04:02:14 PM PDT 24
Finished Mar 23 04:02:23 PM PDT 24
Peak memory 220996 kb
Host smart-ee5cf573-a406-4462-a55e-94ce01563a00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599046017 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3599046017
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3630123413
Short name T744
Test name
Test status
Simulation time 280285227 ps
CPU time 7.07 seconds
Started Mar 23 04:02:12 PM PDT 24
Finished Mar 23 04:02:19 PM PDT 24
Peak memory 209376 kb
Host smart-bbcf8650-f2d7-431d-8949-b743d4a40966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630123413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3630123413
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3727612524
Short name T977
Test name
Test status
Simulation time 687935519 ps
CPU time 4.17 seconds
Started Mar 23 04:02:14 PM PDT 24
Finished Mar 23 04:02:19 PM PDT 24
Peak memory 210448 kb
Host smart-7246fb4a-ad57-4bf7-9af3-8c77053abc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727612524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3727612524
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2277768637
Short name T773
Test name
Test status
Simulation time 22565603 ps
CPU time 0.92 seconds
Started Mar 23 04:02:13 PM PDT 24
Finished Mar 23 04:02:14 PM PDT 24
Peak memory 205888 kb
Host smart-1a47c561-8d50-401c-adb1-71cf35ba0046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277768637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2277768637
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1241293524
Short name T425
Test name
Test status
Simulation time 175902861 ps
CPU time 3.44 seconds
Started Mar 23 04:02:16 PM PDT 24
Finished Mar 23 04:02:20 PM PDT 24
Peak memory 214276 kb
Host smart-f07b5782-5de4-44e2-88de-6145a16f4dfc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1241293524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1241293524
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.166114184
Short name T1016
Test name
Test status
Simulation time 302068485 ps
CPU time 3.28 seconds
Started Mar 23 04:02:23 PM PDT 24
Finished Mar 23 04:02:26 PM PDT 24
Peak memory 209780 kb
Host smart-8d8da272-dc83-4eb6-b0ff-98260c0d6fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166114184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.166114184
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.611149261
Short name T64
Test name
Test status
Simulation time 271603930 ps
CPU time 7.06 seconds
Started Mar 23 04:02:11 PM PDT 24
Finished Mar 23 04:02:18 PM PDT 24
Peak memory 214244 kb
Host smart-cb4d3406-ad11-4cb0-8a00-7637564d6a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611149261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.611149261
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.411644986
Short name T767
Test name
Test status
Simulation time 41940830 ps
CPU time 2.77 seconds
Started Mar 23 04:02:13 PM PDT 24
Finished Mar 23 04:02:16 PM PDT 24
Peak memory 208716 kb
Host smart-b682c01d-91cb-4818-bba3-c21cd0c1ce7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411644986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.411644986
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.852077474
Short name T764
Test name
Test status
Simulation time 59227169 ps
CPU time 3.03 seconds
Started Mar 23 04:02:13 PM PDT 24
Finished Mar 23 04:02:16 PM PDT 24
Peak memory 219792 kb
Host smart-ebfd8d78-17b3-4604-a109-d10e5d1e3259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852077474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.852077474
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3843385249
Short name T181
Test name
Test status
Simulation time 168222151 ps
CPU time 6.78 seconds
Started Mar 23 04:02:14 PM PDT 24
Finished Mar 23 04:02:21 PM PDT 24
Peak memory 209816 kb
Host smart-e41ac3aa-32d4-4c49-b8f3-734180470791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843385249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3843385249
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2707255621
Short name T679
Test name
Test status
Simulation time 30262969 ps
CPU time 2.31 seconds
Started Mar 23 04:02:11 PM PDT 24
Finished Mar 23 04:02:13 PM PDT 24
Peak memory 206896 kb
Host smart-8a39bdc6-a839-413e-bbf7-3d0868214e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707255621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2707255621
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.3743087378
Short name T960
Test name
Test status
Simulation time 46158533 ps
CPU time 1.92 seconds
Started Mar 23 04:02:16 PM PDT 24
Finished Mar 23 04:02:19 PM PDT 24
Peak memory 207592 kb
Host smart-c5df1620-b238-4591-975e-40d4bd0effdc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743087378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.3743087378
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3514205002
Short name T338
Test name
Test status
Simulation time 91600429 ps
CPU time 2.15 seconds
Started Mar 23 04:02:12 PM PDT 24
Finished Mar 23 04:02:14 PM PDT 24
Peak memory 208728 kb
Host smart-5679b8df-92e8-4c48-9c1b-bbd4fc6d2084
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514205002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3514205002
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1044584341
Short name T726
Test name
Test status
Simulation time 57466216 ps
CPU time 2.97 seconds
Started Mar 23 04:02:15 PM PDT 24
Finished Mar 23 04:02:19 PM PDT 24
Peak memory 208936 kb
Host smart-73adabf4-6029-4ebf-8801-08e83150af5e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044584341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1044584341
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.4129649756
Short name T717
Test name
Test status
Simulation time 88991945 ps
CPU time 2.65 seconds
Started Mar 23 04:02:12 PM PDT 24
Finished Mar 23 04:02:15 PM PDT 24
Peak memory 209240 kb
Host smart-0c6feb4d-71dc-44b2-91a3-bcb36f8571c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129649756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.4129649756
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2485906
Short name T952
Test name
Test status
Simulation time 608143863 ps
CPU time 13.83 seconds
Started Mar 23 04:02:11 PM PDT 24
Finished Mar 23 04:02:25 PM PDT 24
Peak memory 207764 kb
Host smart-4e0acfda-529b-47d9-91bc-a055e2815381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2485906
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2328193
Short name T100
Test name
Test status
Simulation time 115370786 ps
CPU time 5.46 seconds
Started Mar 23 04:02:13 PM PDT 24
Finished Mar 23 04:02:19 PM PDT 24
Peak memory 214320 kb
Host smart-2d973c66-99c8-4bfd-af05-a493d56c5f25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2328193
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3981615809
Short name T214
Test name
Test status
Simulation time 773049097 ps
CPU time 12.85 seconds
Started Mar 23 04:02:12 PM PDT 24
Finished Mar 23 04:02:25 PM PDT 24
Peak memory 222596 kb
Host smart-8fe79daa-09c9-4132-a1c4-5a57291db5e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981615809 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3981615809
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2808446938
Short name T404
Test name
Test status
Simulation time 114869849 ps
CPU time 2.62 seconds
Started Mar 23 04:02:14 PM PDT 24
Finished Mar 23 04:02:17 PM PDT 24
Peak memory 209900 kb
Host smart-c396f11a-de38-4bf1-be3f-12eb9882e8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808446938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2808446938
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2547485474
Short name T643
Test name
Test status
Simulation time 151902767 ps
CPU time 0.85 seconds
Started Mar 23 04:02:09 PM PDT 24
Finished Mar 23 04:02:10 PM PDT 24
Peak memory 205848 kb
Host smart-142b3d15-84ca-427c-91eb-b90b6bb954f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547485474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2547485474
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2423309100
Short name T79
Test name
Test status
Simulation time 2524102691 ps
CPU time 10.58 seconds
Started Mar 23 04:02:14 PM PDT 24
Finished Mar 23 04:02:25 PM PDT 24
Peak memory 222672 kb
Host smart-00e3f5c9-07c7-483b-8858-e9584d0fe75f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2423309100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2423309100
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1803902963
Short name T905
Test name
Test status
Simulation time 45135061 ps
CPU time 1.9 seconds
Started Mar 23 04:02:12 PM PDT 24
Finished Mar 23 04:02:14 PM PDT 24
Peak memory 206916 kb
Host smart-8faffdbb-a4f0-450d-88ab-4c58a80a4acf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803902963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1803902963
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3451149182
Short name T261
Test name
Test status
Simulation time 169249122 ps
CPU time 6.19 seconds
Started Mar 23 04:02:14 PM PDT 24
Finished Mar 23 04:02:20 PM PDT 24
Peak memory 214384 kb
Host smart-89c79463-9892-4d4a-b273-d48f5f07475f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451149182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3451149182
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1191710228
Short name T993
Test name
Test status
Simulation time 149809216 ps
CPU time 2.71 seconds
Started Mar 23 04:02:13 PM PDT 24
Finished Mar 23 04:02:16 PM PDT 24
Peak memory 214408 kb
Host smart-106d714e-ef66-4957-af1b-7b8e47474e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191710228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1191710228
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1204376780
Short name T1032
Test name
Test status
Simulation time 103854365 ps
CPU time 3.61 seconds
Started Mar 23 04:02:22 PM PDT 24
Finished Mar 23 04:02:26 PM PDT 24
Peak memory 207772 kb
Host smart-d1f03a3a-06df-4aa2-923d-5bbd32921915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204376780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1204376780
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3697180587
Short name T369
Test name
Test status
Simulation time 236647115 ps
CPU time 7.3 seconds
Started Mar 23 04:02:22 PM PDT 24
Finished Mar 23 04:02:29 PM PDT 24
Peak memory 208372 kb
Host smart-d80140bf-e92f-40f9-a36e-f02597a2efde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697180587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3697180587
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1958189259
Short name T1013
Test name
Test status
Simulation time 110177739 ps
CPU time 2.95 seconds
Started Mar 23 04:02:17 PM PDT 24
Finished Mar 23 04:02:21 PM PDT 24
Peak memory 206964 kb
Host smart-f241e455-0179-490c-a34b-beaa5d51be62
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958189259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1958189259
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1418672959
Short name T973
Test name
Test status
Simulation time 149263539 ps
CPU time 2.64 seconds
Started Mar 23 04:02:14 PM PDT 24
Finished Mar 23 04:02:16 PM PDT 24
Peak memory 206880 kb
Host smart-6a03a37d-b997-4360-a496-10de97a36c88
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418672959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1418672959
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.412295859
Short name T299
Test name
Test status
Simulation time 839836290 ps
CPU time 4.88 seconds
Started Mar 23 04:02:22 PM PDT 24
Finished Mar 23 04:02:27 PM PDT 24
Peak memory 208516 kb
Host smart-e3ab33a8-d359-47a9-a7d2-3f9d0123be43
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412295859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.412295859
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1958304014
Short name T414
Test name
Test status
Simulation time 142212623 ps
CPU time 2.56 seconds
Started Mar 23 04:02:13 PM PDT 24
Finished Mar 23 04:02:16 PM PDT 24
Peak memory 208036 kb
Host smart-6a29e635-16db-4fcd-b9e4-e4852f5a5cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958304014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1958304014
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1266404244
Short name T642
Test name
Test status
Simulation time 118330358 ps
CPU time 2.55 seconds
Started Mar 23 04:02:13 PM PDT 24
Finished Mar 23 04:02:16 PM PDT 24
Peak memory 206828 kb
Host smart-e83481d1-b7f8-451b-83d2-0c5b68496a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266404244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1266404244
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2932725549
Short name T282
Test name
Test status
Simulation time 4809693286 ps
CPU time 35.81 seconds
Started Mar 23 04:02:22 PM PDT 24
Finished Mar 23 04:02:58 PM PDT 24
Peak memory 217156 kb
Host smart-24f5e562-ba3e-4fe7-8eb4-b4c90d477286
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932725549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2932725549
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.2245072135
Short name T855
Test name
Test status
Simulation time 614902986 ps
CPU time 12.95 seconds
Started Mar 23 04:02:11 PM PDT 24
Finished Mar 23 04:02:24 PM PDT 24
Peak memory 220412 kb
Host smart-997f0624-069d-4a5a-b70c-ec22bc2d799d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245072135 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.2245072135
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.593696378
Short name T915
Test name
Test status
Simulation time 1614450152 ps
CPU time 11.83 seconds
Started Mar 23 04:02:13 PM PDT 24
Finished Mar 23 04:02:25 PM PDT 24
Peak memory 218436 kb
Host smart-fc7c83c2-7fd4-49ea-8493-85a78f0880e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593696378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.593696378
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.898019979
Short name T846
Test name
Test status
Simulation time 94438392 ps
CPU time 3.58 seconds
Started Mar 23 04:02:13 PM PDT 24
Finished Mar 23 04:02:17 PM PDT 24
Peak memory 210444 kb
Host smart-362a5a6b-2ccb-41ef-9060-ee176de2efd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898019979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.898019979
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2394434342
Short name T1007
Test name
Test status
Simulation time 9954930 ps
CPU time 0.81 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:31 PM PDT 24
Peak memory 205920 kb
Host smart-58cbbdb3-5e78-4ca1-a89a-b0b91a2b66f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394434342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2394434342
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3116716791
Short name T288
Test name
Test status
Simulation time 108832570 ps
CPU time 4.13 seconds
Started Mar 23 04:02:13 PM PDT 24
Finished Mar 23 04:02:17 PM PDT 24
Peak memory 215468 kb
Host smart-8b8fa768-2c31-41a8-b535-7544b327317d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3116716791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3116716791
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.115773337
Short name T38
Test name
Test status
Simulation time 145340401 ps
CPU time 2.92 seconds
Started Mar 23 04:02:27 PM PDT 24
Finished Mar 23 04:02:31 PM PDT 24
Peak memory 220552 kb
Host smart-607c0580-cee9-42b5-aa86-d74835df8148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115773337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.115773337
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2190699462
Short name T272
Test name
Test status
Simulation time 220658646 ps
CPU time 5.08 seconds
Started Mar 23 04:02:14 PM PDT 24
Finished Mar 23 04:02:19 PM PDT 24
Peak memory 214344 kb
Host smart-61e6f4a7-74f5-4402-8460-b1fd57a5509d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190699462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2190699462
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1082562301
Short name T999
Test name
Test status
Simulation time 3938716142 ps
CPU time 28 seconds
Started Mar 23 04:02:10 PM PDT 24
Finished Mar 23 04:02:38 PM PDT 24
Peak memory 209036 kb
Host smart-3954be51-4070-437c-a48d-54ef2a8f03f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082562301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1082562301
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.82152652
Short name T986
Test name
Test status
Simulation time 218661231 ps
CPU time 4.24 seconds
Started Mar 23 04:02:31 PM PDT 24
Finished Mar 23 04:02:36 PM PDT 24
Peak memory 214336 kb
Host smart-91067501-4cda-4c24-a1df-d58a162da174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82152652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.82152652
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2625321335
Short name T805
Test name
Test status
Simulation time 161988900 ps
CPU time 6.32 seconds
Started Mar 23 04:02:22 PM PDT 24
Finished Mar 23 04:02:29 PM PDT 24
Peak memory 209848 kb
Host smart-8f969eb3-ec81-4a2c-b474-9c61f223a7ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625321335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2625321335
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.91441762
Short name T898
Test name
Test status
Simulation time 1125657676 ps
CPU time 8.62 seconds
Started Mar 23 04:02:23 PM PDT 24
Finished Mar 23 04:02:31 PM PDT 24
Peak memory 208148 kb
Host smart-25743529-d70e-4a42-aa5f-1533ae7a3407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91441762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.91441762
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2352988652
Short name T182
Test name
Test status
Simulation time 422034276 ps
CPU time 5.87 seconds
Started Mar 23 04:02:22 PM PDT 24
Finished Mar 23 04:02:28 PM PDT 24
Peak memory 206864 kb
Host smart-c920c0d5-59f9-4510-b22e-0ccb06fc6e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352988652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2352988652
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2337377716
Short name T1075
Test name
Test status
Simulation time 117011273 ps
CPU time 3.05 seconds
Started Mar 23 04:02:16 PM PDT 24
Finished Mar 23 04:02:19 PM PDT 24
Peak memory 208588 kb
Host smart-f8db9668-5856-4eac-8604-0f6c6f9433fd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337377716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2337377716
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3272677502
Short name T287
Test name
Test status
Simulation time 30394372 ps
CPU time 2.29 seconds
Started Mar 23 04:02:14 PM PDT 24
Finished Mar 23 04:02:16 PM PDT 24
Peak memory 209028 kb
Host smart-edc8b73c-5c7f-49f2-bc21-3810f53eaa08
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272677502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3272677502
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.183974262
Short name T703
Test name
Test status
Simulation time 360351986 ps
CPU time 5.77 seconds
Started Mar 23 04:02:21 PM PDT 24
Finished Mar 23 04:02:27 PM PDT 24
Peak memory 208748 kb
Host smart-3760fdbc-3c81-478f-a71a-397798b78372
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183974262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.183974262
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3805268585
Short name T873
Test name
Test status
Simulation time 7695399488 ps
CPU time 26.36 seconds
Started Mar 23 04:02:25 PM PDT 24
Finished Mar 23 04:02:54 PM PDT 24
Peak memory 221100 kb
Host smart-1b6b08ce-e737-4a97-a136-95fbda1af09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805268585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3805268585
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3409220575
Short name T131
Test name
Test status
Simulation time 67619273 ps
CPU time 3.18 seconds
Started Mar 23 04:02:17 PM PDT 24
Finished Mar 23 04:02:21 PM PDT 24
Peak memory 208476 kb
Host smart-74b2bb3d-a603-43a4-b030-4890fdfba109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409220575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3409220575
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3810739832
Short name T308
Test name
Test status
Simulation time 2958270580 ps
CPU time 14.28 seconds
Started Mar 23 04:02:26 PM PDT 24
Finished Mar 23 04:02:41 PM PDT 24
Peak memory 215816 kb
Host smart-5efd8332-66ea-4f20-aef9-193738152aa9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810739832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3810739832
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2989094732
Short name T659
Test name
Test status
Simulation time 180074063 ps
CPU time 6.11 seconds
Started Mar 23 04:02:29 PM PDT 24
Finished Mar 23 04:02:37 PM PDT 24
Peak memory 223740 kb
Host smart-d4738d69-4988-4e43-990a-2f3ff460c60e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989094732 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2989094732
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.4095793825
Short name T376
Test name
Test status
Simulation time 204827817 ps
CPU time 6.89 seconds
Started Mar 23 04:02:22 PM PDT 24
Finished Mar 23 04:02:29 PM PDT 24
Peak memory 208560 kb
Host smart-4dc27029-31b3-436c-add7-9a2835684165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095793825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.4095793825
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3754793910
Short name T1022
Test name
Test status
Simulation time 1157749987 ps
CPU time 6.94 seconds
Started Mar 23 04:02:29 PM PDT 24
Finished Mar 23 04:02:37 PM PDT 24
Peak memory 210584 kb
Host smart-a7ce2261-e6d9-4196-a9db-89bbc022ac3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754793910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3754793910
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1636364530
Short name T938
Test name
Test status
Simulation time 28846903 ps
CPU time 0.7 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:32 PM PDT 24
Peak memory 205836 kb
Host smart-f731a5d4-013c-4236-a8e8-905068fadfb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636364530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1636364530
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.354198275
Short name T368
Test name
Test status
Simulation time 113572381 ps
CPU time 2.69 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:34 PM PDT 24
Peak memory 214288 kb
Host smart-368c3e1e-947d-48c7-9e09-65a2f4d46ef3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354198275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.354198275
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.890952785
Short name T912
Test name
Test status
Simulation time 108241844 ps
CPU time 2.39 seconds
Started Mar 23 04:02:32 PM PDT 24
Finished Mar 23 04:02:34 PM PDT 24
Peak memory 214352 kb
Host smart-2337d14f-6453-4b61-b3ba-8ea95b3e3152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890952785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.890952785
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2676369177
Short name T188
Test name
Test status
Simulation time 1452275466 ps
CPU time 7.81 seconds
Started Mar 23 04:02:32 PM PDT 24
Finished Mar 23 04:02:40 PM PDT 24
Peak memory 218576 kb
Host smart-fe1a768f-4dda-47ec-bbab-d582e1536db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676369177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2676369177
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.4218237734
Short name T917
Test name
Test status
Simulation time 962994355 ps
CPU time 10.14 seconds
Started Mar 23 04:02:26 PM PDT 24
Finished Mar 23 04:02:38 PM PDT 24
Peak memory 214360 kb
Host smart-42198c45-75bf-4095-b2b3-e4690bbf66e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218237734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.4218237734
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.349901860
Short name T663
Test name
Test status
Simulation time 221619072 ps
CPU time 4.01 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:34 PM PDT 24
Peak memory 214212 kb
Host smart-5194c659-65ed-4331-a40b-61cea25e4336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349901860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.349901860
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_random.4205326958
Short name T698
Test name
Test status
Simulation time 135870992 ps
CPU time 5.65 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:37 PM PDT 24
Peak memory 208324 kb
Host smart-586b05d1-4b7d-4aea-a8b4-57f8c01b80fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205326958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.4205326958
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.48038313
Short name T680
Test name
Test status
Simulation time 75283561 ps
CPU time 3.93 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:35 PM PDT 24
Peak memory 208600 kb
Host smart-13b324d9-7f53-4e30-ab63-686df1d6e8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48038313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.48038313
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.4131515656
Short name T969
Test name
Test status
Simulation time 487456437 ps
CPU time 4.78 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:34 PM PDT 24
Peak memory 208804 kb
Host smart-88a95a9b-5711-4c7f-b402-7772ef2f8cfd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131515656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.4131515656
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.387035714
Short name T897
Test name
Test status
Simulation time 290056559 ps
CPU time 3.5 seconds
Started Mar 23 04:02:27 PM PDT 24
Finished Mar 23 04:02:32 PM PDT 24
Peak memory 208516 kb
Host smart-310201e0-d826-4c05-b57b-956a094ab89d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387035714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.387035714
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2015400252
Short name T1049
Test name
Test status
Simulation time 241897989 ps
CPU time 3.26 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:34 PM PDT 24
Peak memory 206908 kb
Host smart-cd3fcdbb-5210-4f9c-9e31-6cd457b8a475
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015400252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2015400252
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2026509869
Short name T279
Test name
Test status
Simulation time 133463544 ps
CPU time 2.87 seconds
Started Mar 23 04:02:27 PM PDT 24
Finished Mar 23 04:02:31 PM PDT 24
Peak memory 209116 kb
Host smart-edce7be4-49b9-46d3-a682-f6edf359fbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026509869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2026509869
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.767805002
Short name T879
Test name
Test status
Simulation time 1037984130 ps
CPU time 3.92 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:36 PM PDT 24
Peak memory 208608 kb
Host smart-06951245-30d4-4714-ae2b-db561f1b066a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767805002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.767805002
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3797587849
Short name T359
Test name
Test status
Simulation time 3685730333 ps
CPU time 36.08 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:03:06 PM PDT 24
Peak memory 217020 kb
Host smart-10e4c7d7-3be2-4db6-bed3-30916368b20f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797587849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3797587849
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.265857404
Short name T621
Test name
Test status
Simulation time 1132092867 ps
CPU time 6.74 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:36 PM PDT 24
Peak memory 208940 kb
Host smart-6f5dbcef-fe40-4d82-b4cc-0a362cddb7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265857404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.265857404
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.67487218
Short name T403
Test name
Test status
Simulation time 33987196 ps
CPU time 2.17 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:34 PM PDT 24
Peak memory 209864 kb
Host smart-f4cacbca-bd7e-434e-ab41-db5c6c42af79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67487218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.67487218
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.2804286024
Short name T792
Test name
Test status
Simulation time 12762183 ps
CPU time 0.89 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:30 PM PDT 24
Peak memory 205780 kb
Host smart-b31af686-3c6c-45db-82ed-67e245a650ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804286024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.2804286024
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1455868231
Short name T32
Test name
Test status
Simulation time 117729413 ps
CPU time 3.79 seconds
Started Mar 23 04:02:26 PM PDT 24
Finished Mar 23 04:02:30 PM PDT 24
Peak memory 209996 kb
Host smart-0fa4d37e-ec68-4b48-8bd8-c9975f8c5cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455868231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1455868231
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.690594250
Short name T1073
Test name
Test status
Simulation time 491784192 ps
CPU time 3.61 seconds
Started Mar 23 04:02:27 PM PDT 24
Finished Mar 23 04:02:33 PM PDT 24
Peak memory 219684 kb
Host smart-a2487f61-cf8a-4da0-88c6-945cd8eee34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690594250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.690594250
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1770924538
Short name T875
Test name
Test status
Simulation time 399182741 ps
CPU time 10.33 seconds
Started Mar 23 04:02:29 PM PDT 24
Finished Mar 23 04:02:41 PM PDT 24
Peak memory 214340 kb
Host smart-b48020c9-c6c1-4008-8131-19077f776b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770924538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1770924538
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.638384711
Short name T324
Test name
Test status
Simulation time 134600116 ps
CPU time 6.37 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:38 PM PDT 24
Peak memory 214272 kb
Host smart-dc18834e-aa16-4737-bc9d-36ff1bb5cce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638384711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.638384711
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3503937923
Short name T392
Test name
Test status
Simulation time 279259733 ps
CPU time 6.14 seconds
Started Mar 23 04:02:26 PM PDT 24
Finished Mar 23 04:02:33 PM PDT 24
Peak memory 222468 kb
Host smart-92e2c596-4577-4355-b1aa-a7599f79c079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503937923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3503937923
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2342409586
Short name T1053
Test name
Test status
Simulation time 1053880335 ps
CPU time 7.72 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:37 PM PDT 24
Peak memory 209276 kb
Host smart-9e5383f8-ffc1-46fc-8891-fa7641c8a8fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342409586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2342409586
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1252890874
Short name T250
Test name
Test status
Simulation time 149859328 ps
CPU time 4.35 seconds
Started Mar 23 04:02:26 PM PDT 24
Finished Mar 23 04:02:33 PM PDT 24
Peak memory 206828 kb
Host smart-ed9922a0-827b-4401-85c7-628a41140819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252890874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1252890874
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.886190088
Short name T1002
Test name
Test status
Simulation time 50967659 ps
CPU time 2.86 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:33 PM PDT 24
Peak memory 206940 kb
Host smart-bc9e54dc-8c9c-4102-9c14-9c5cab6ea070
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886190088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.886190088
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2086662836
Short name T1000
Test name
Test status
Simulation time 68866040 ps
CPU time 2.74 seconds
Started Mar 23 04:02:26 PM PDT 24
Finished Mar 23 04:02:30 PM PDT 24
Peak memory 206788 kb
Host smart-a59b8b1b-5147-4fa4-9905-956f05cc22c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086662836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2086662836
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2055268396
Short name T1029
Test name
Test status
Simulation time 1868157416 ps
CPU time 4.45 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:36 PM PDT 24
Peak memory 209148 kb
Host smart-3ae9b6b3-b0e6-459d-8ea9-d63682131f56
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055268396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2055268396
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3562256150
Short name T99
Test name
Test status
Simulation time 1712933292 ps
CPU time 28.63 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:58 PM PDT 24
Peak memory 208252 kb
Host smart-c8e6bf57-6747-4dcb-83af-10e769e24b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562256150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3562256150
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2828495422
Short name T940
Test name
Test status
Simulation time 87460134 ps
CPU time 1.95 seconds
Started Mar 23 04:02:27 PM PDT 24
Finished Mar 23 04:02:31 PM PDT 24
Peak memory 206884 kb
Host smart-eb2512b4-68d6-4ce7-9b73-74751bf2408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828495422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2828495422
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.1886541053
Short name T653
Test name
Test status
Simulation time 1233988730 ps
CPU time 3.51 seconds
Started Mar 23 04:02:29 PM PDT 24
Finished Mar 23 04:02:34 PM PDT 24
Peak memory 222652 kb
Host smart-e46dd51e-cc52-445f-bc3a-43b33fe28fdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886541053 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.1886541053
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1396228648
Short name T979
Test name
Test status
Simulation time 202161763 ps
CPU time 4.83 seconds
Started Mar 23 04:02:26 PM PDT 24
Finished Mar 23 04:02:31 PM PDT 24
Peak memory 207360 kb
Host smart-78a3665a-d99c-4bbf-8758-ebdb198f81bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396228648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1396228648
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2454171759
Short name T695
Test name
Test status
Simulation time 128527695 ps
CPU time 2.32 seconds
Started Mar 23 04:02:27 PM PDT 24
Finished Mar 23 04:02:32 PM PDT 24
Peak memory 210612 kb
Host smart-7516774d-90d3-4d7e-b29d-ab1d43254c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454171759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2454171759
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.560827404
Short name T1008
Test name
Test status
Simulation time 50509779 ps
CPU time 0.9 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:32 PM PDT 24
Peak memory 205856 kb
Host smart-9ad45eaa-a44c-4cbf-9843-c692b839d199
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560827404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.560827404
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1218703677
Short name T252
Test name
Test status
Simulation time 104022796 ps
CPU time 3.76 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:35 PM PDT 24
Peak memory 214332 kb
Host smart-fd46f56d-c086-4282-9b00-78f8630688be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1218703677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1218703677
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3855746464
Short name T874
Test name
Test status
Simulation time 565929178 ps
CPU time 8.45 seconds
Started Mar 23 04:02:27 PM PDT 24
Finished Mar 23 04:02:37 PM PDT 24
Peak memory 214716 kb
Host smart-f486b2f1-27f3-4f0b-af5f-4458f513bd48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855746464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3855746464
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.4163667952
Short name T587
Test name
Test status
Simulation time 99043956 ps
CPU time 3.49 seconds
Started Mar 23 04:02:31 PM PDT 24
Finished Mar 23 04:02:35 PM PDT 24
Peak memory 214428 kb
Host smart-d5b9122f-0307-4af4-a729-adc9ec656bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163667952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.4163667952
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1237773355
Short name T892
Test name
Test status
Simulation time 138220753 ps
CPU time 2.34 seconds
Started Mar 23 04:02:26 PM PDT 24
Finished Mar 23 04:02:29 PM PDT 24
Peak memory 209164 kb
Host smart-3cb47edb-c55a-4cc3-a36d-7e7fc0bce4a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237773355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1237773355
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3478058299
Short name T313
Test name
Test status
Simulation time 581816920 ps
CPU time 4.29 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:35 PM PDT 24
Peak memory 207436 kb
Host smart-0b2dc4ce-01a9-4763-a670-cd86920c9e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478058299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3478058299
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2265100304
Short name T725
Test name
Test status
Simulation time 124057833 ps
CPU time 2.44 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:32 PM PDT 24
Peak memory 206888 kb
Host smart-81d962fb-90bb-4d76-9c64-703f545bf5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265100304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2265100304
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.899556777
Short name T571
Test name
Test status
Simulation time 178534965 ps
CPU time 5.32 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:35 PM PDT 24
Peak memory 208076 kb
Host smart-6a2c74da-e0d6-40c3-85d9-b9c99a81b0fd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899556777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.899556777
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1493490113
Short name T852
Test name
Test status
Simulation time 1055057297 ps
CPU time 3.43 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:35 PM PDT 24
Peak memory 208656 kb
Host smart-866e9c1f-a704-45ad-aed6-5e99248f2aae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493490113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1493490113
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2896484043
Short name T390
Test name
Test status
Simulation time 838386969 ps
CPU time 16.91 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:48 PM PDT 24
Peak memory 207808 kb
Host smart-d8b649c2-d883-436f-b4bb-b654afa44a1a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896484043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2896484043
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2556104154
Short name T358
Test name
Test status
Simulation time 275131242 ps
CPU time 3.52 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:33 PM PDT 24
Peak memory 214328 kb
Host smart-1b65fa6b-8e60-461a-9d26-202172eda8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556104154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2556104154
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1007077960
Short name T3
Test name
Test status
Simulation time 62745508 ps
CPU time 2.41 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:32 PM PDT 24
Peak memory 207088 kb
Host smart-fce65ca6-15ca-4b2c-ab65-22d5a135af8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007077960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1007077960
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.741043065
Short name T836
Test name
Test status
Simulation time 4537300130 ps
CPU time 40.52 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:03:12 PM PDT 24
Peak memory 220648 kb
Host smart-f22c76e7-ad8d-41c8-aff3-2c547fa29cc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741043065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.741043065
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2960924186
Short name T789
Test name
Test status
Simulation time 2467163950 ps
CPU time 6.91 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:38 PM PDT 24
Peak memory 220276 kb
Host smart-2fdb61c6-9834-4123-a3af-7881fea23bd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960924186 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2960924186
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2760585820
Short name T634
Test name
Test status
Simulation time 11517970834 ps
CPU time 37.58 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:03:08 PM PDT 24
Peak memory 210132 kb
Host smart-b604ae4e-159f-4e44-9d89-0d276bfa227d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760585820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2760585820
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.721802804
Short name T950
Test name
Test status
Simulation time 239876192 ps
CPU time 5.07 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:35 PM PDT 24
Peak memory 210324 kb
Host smart-f1fe7d9f-3b64-4b8b-81e6-55f066dc6854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721802804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.721802804
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3140152375
Short name T824
Test name
Test status
Simulation time 35701991 ps
CPU time 0.73 seconds
Started Mar 23 04:02:26 PM PDT 24
Finished Mar 23 04:02:28 PM PDT 24
Peak memory 205912 kb
Host smart-baf452da-6237-4220-8702-c2d6a0a7b797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140152375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3140152375
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.3432627339
Short name T29
Test name
Test status
Simulation time 81693643 ps
CPU time 4.15 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:36 PM PDT 24
Peak memory 208112 kb
Host smart-e1c79fd3-6315-417e-b96c-9efe32010850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432627339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.3432627339
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2642958530
Short name T929
Test name
Test status
Simulation time 104144133 ps
CPU time 3.01 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:33 PM PDT 24
Peak memory 207428 kb
Host smart-5998473e-fe37-49e5-afff-f7fc45fcea08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642958530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2642958530
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1565374984
Short name T356
Test name
Test status
Simulation time 496765579 ps
CPU time 7.81 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:39 PM PDT 24
Peak memory 214292 kb
Host smart-3f38c6eb-4b06-4d6b-b887-c1bbd8551a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565374984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1565374984
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.102186164
Short name T983
Test name
Test status
Simulation time 139793882 ps
CPU time 4.57 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:36 PM PDT 24
Peak memory 214228 kb
Host smart-95a49db2-6013-4c8f-b50b-7aa4d841ed34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102186164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.102186164
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1817201337
Short name T975
Test name
Test status
Simulation time 384927628 ps
CPU time 10.65 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:40 PM PDT 24
Peak memory 222420 kb
Host smart-3a9c65d2-2db9-4e2d-8f7a-99550f72773f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817201337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1817201337
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3785343167
Short name T867
Test name
Test status
Simulation time 247571677 ps
CPU time 4.34 seconds
Started Mar 23 04:02:29 PM PDT 24
Finished Mar 23 04:02:35 PM PDT 24
Peak memory 208088 kb
Host smart-37159748-68f0-4a5c-a2f9-dc777ef6dde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785343167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3785343167
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2574417575
Short name T574
Test name
Test status
Simulation time 59842638 ps
CPU time 2.93 seconds
Started Mar 23 04:02:27 PM PDT 24
Finished Mar 23 04:02:31 PM PDT 24
Peak memory 208420 kb
Host smart-d06f42ed-e21c-4b20-b33d-f3e79ce4daa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574417575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2574417575
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1650521328
Short name T735
Test name
Test status
Simulation time 80447104 ps
CPU time 3.45 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:35 PM PDT 24
Peak memory 208516 kb
Host smart-e9b8379f-5f2f-4267-9bc7-787949c3cab6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650521328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1650521328
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.608021269
Short name T349
Test name
Test status
Simulation time 652934721 ps
CPU time 16.7 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:47 PM PDT 24
Peak memory 208792 kb
Host smart-bad1ee74-292b-4393-b9db-e4650807401b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608021269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.608021269
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1752637635
Short name T286
Test name
Test status
Simulation time 102786644 ps
CPU time 2.06 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:32 PM PDT 24
Peak memory 208880 kb
Host smart-96ddd4a2-6799-46e3-98fe-f17b4f141c60
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752637635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1752637635
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1552774281
Short name T761
Test name
Test status
Simulation time 32066919 ps
CPU time 1.51 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:33 PM PDT 24
Peak memory 207380 kb
Host smart-510a2500-9892-4ad3-87f8-449dd8811231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552774281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1552774281
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.762707421
Short name T1012
Test name
Test status
Simulation time 327887074 ps
CPU time 3.6 seconds
Started Mar 23 04:02:28 PM PDT 24
Finished Mar 23 04:02:34 PM PDT 24
Peak memory 206716 kb
Host smart-1e3ed60b-c2e3-451f-8f8f-23d363f1f8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762707421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.762707421
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3453133022
Short name T206
Test name
Test status
Simulation time 6960189349 ps
CPU time 228.2 seconds
Started Mar 23 04:02:29 PM PDT 24
Finished Mar 23 04:06:19 PM PDT 24
Peak memory 222556 kb
Host smart-6961443c-f470-405f-85a1-1678ed3246a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453133022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3453133022
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2992050503
Short name T604
Test name
Test status
Simulation time 452956035 ps
CPU time 5.62 seconds
Started Mar 23 04:02:30 PM PDT 24
Finished Mar 23 04:02:37 PM PDT 24
Peak memory 207936 kb
Host smart-1700bd16-bcc6-4e04-9691-238cdfba70e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992050503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2992050503
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.854040661
Short name T772
Test name
Test status
Simulation time 369006684 ps
CPU time 2.64 seconds
Started Mar 23 04:02:31 PM PDT 24
Finished Mar 23 04:02:34 PM PDT 24
Peak memory 210672 kb
Host smart-c0db9ed0-a2a8-4278-ad05-5528a7d13e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854040661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.854040661
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1792126199
Short name T570
Test name
Test status
Simulation time 9797998 ps
CPU time 0.75 seconds
Started Mar 23 03:59:59 PM PDT 24
Finished Mar 23 04:00:00 PM PDT 24
Peak memory 205884 kb
Host smart-92fda94c-ff95-4d14-8d90-faf970ac4b46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792126199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1792126199
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3778635073
Short name T427
Test name
Test status
Simulation time 2488145435 ps
CPU time 7.71 seconds
Started Mar 23 04:00:04 PM PDT 24
Finished Mar 23 04:00:12 PM PDT 24
Peak memory 215928 kb
Host smart-ed80ce23-a638-4f8e-b857-339e4bd25a30
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3778635073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3778635073
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2614965480
Short name T742
Test name
Test status
Simulation time 6207405322 ps
CPU time 20.03 seconds
Started Mar 23 03:59:59 PM PDT 24
Finished Mar 23 04:00:20 PM PDT 24
Peak memory 216008 kb
Host smart-882087f3-b230-47fc-883b-caff2de40f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614965480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2614965480
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.456864303
Short name T1001
Test name
Test status
Simulation time 37383589 ps
CPU time 1.43 seconds
Started Mar 23 04:00:00 PM PDT 24
Finished Mar 23 04:00:02 PM PDT 24
Peak memory 206980 kb
Host smart-b2e91389-f656-4b28-a480-4c5053184c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456864303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.456864303
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.101192014
Short name T706
Test name
Test status
Simulation time 178761794 ps
CPU time 3.59 seconds
Started Mar 23 03:59:58 PM PDT 24
Finished Mar 23 04:00:02 PM PDT 24
Peak memory 208388 kb
Host smart-878ebbf9-55d8-4a8c-83dd-fe7e5c113c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101192014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.101192014
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2704064329
Short name T326
Test name
Test status
Simulation time 214030460 ps
CPU time 9.3 seconds
Started Mar 23 04:00:06 PM PDT 24
Finished Mar 23 04:00:16 PM PDT 24
Peak memory 222440 kb
Host smart-990279d0-2e37-406b-9fae-c792a40b0b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704064329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2704064329
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.402211350
Short name T736
Test name
Test status
Simulation time 165869622 ps
CPU time 3.76 seconds
Started Mar 23 03:59:59 PM PDT 24
Finished Mar 23 04:00:04 PM PDT 24
Peak memory 214040 kb
Host smart-d6ce597f-5a91-4c01-900f-aeec3b60684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402211350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.402211350
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2350348769
Short name T989
Test name
Test status
Simulation time 444800700 ps
CPU time 5 seconds
Started Mar 23 04:00:10 PM PDT 24
Finished Mar 23 04:00:15 PM PDT 24
Peak memory 209916 kb
Host smart-ac9fd60c-d0a9-416c-a11a-7ce588e4ec05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350348769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2350348769
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.333487126
Short name T636
Test name
Test status
Simulation time 252766100 ps
CPU time 3.45 seconds
Started Mar 23 03:59:59 PM PDT 24
Finished Mar 23 04:00:03 PM PDT 24
Peak memory 208384 kb
Host smart-abd12063-43e5-4ec9-84a4-82b945fa2aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333487126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.333487126
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1345476142
Short name T851
Test name
Test status
Simulation time 904408111 ps
CPU time 6.91 seconds
Started Mar 23 03:59:59 PM PDT 24
Finished Mar 23 04:00:07 PM PDT 24
Peak memory 208192 kb
Host smart-21448c4b-c3cb-41b7-95f9-b41c0119f054
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345476142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1345476142
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3987800452
Short name T996
Test name
Test status
Simulation time 491412728 ps
CPU time 4.85 seconds
Started Mar 23 04:00:00 PM PDT 24
Finished Mar 23 04:00:05 PM PDT 24
Peak memory 208848 kb
Host smart-43c22ec3-9ece-40c0-b976-2b7314d914bb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987800452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3987800452
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3462227683
Short name T572
Test name
Test status
Simulation time 269803358 ps
CPU time 9.35 seconds
Started Mar 23 04:00:00 PM PDT 24
Finished Mar 23 04:00:10 PM PDT 24
Peak memory 208432 kb
Host smart-994d5a60-91c3-4fe5-aaab-5b509689dfac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462227683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3462227683
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1295518195
Short name T776
Test name
Test status
Simulation time 65653772 ps
CPU time 2.66 seconds
Started Mar 23 03:59:57 PM PDT 24
Finished Mar 23 04:00:00 PM PDT 24
Peak memory 207392 kb
Host smart-11ba9727-1b56-4fba-b529-58c49bac3b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295518195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1295518195
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3742731826
Short name T882
Test name
Test status
Simulation time 154676884 ps
CPU time 5.6 seconds
Started Mar 23 03:59:57 PM PDT 24
Finished Mar 23 04:00:03 PM PDT 24
Peak memory 208528 kb
Host smart-584073dd-004d-4720-a96e-5862fb8d9773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742731826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3742731826
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3695540233
Short name T685
Test name
Test status
Simulation time 84184369 ps
CPU time 5.94 seconds
Started Mar 23 03:59:58 PM PDT 24
Finished Mar 23 04:00:04 PM PDT 24
Peak memory 222816 kb
Host smart-510852d6-615a-4361-88a9-3f06bc4ecb62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695540233 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3695540233
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.4117962953
Short name T809
Test name
Test status
Simulation time 148071836 ps
CPU time 3.84 seconds
Started Mar 23 04:00:04 PM PDT 24
Finished Mar 23 04:00:08 PM PDT 24
Peak memory 208816 kb
Host smart-994d8a8f-39af-4deb-a7e3-fee902f9114d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117962953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.4117962953
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1635543145
Short name T796
Test name
Test status
Simulation time 40003805 ps
CPU time 2.11 seconds
Started Mar 23 04:00:05 PM PDT 24
Finished Mar 23 04:00:07 PM PDT 24
Peak memory 210076 kb
Host smart-62878645-f93d-4496-8c74-9ba06a8e1a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635543145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1635543145
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2360900832
Short name T96
Test name
Test status
Simulation time 17315233 ps
CPU time 0.84 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:00:14 PM PDT 24
Peak memory 205888 kb
Host smart-c9075592-883f-4b20-b45f-a4d03421b5dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360900832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2360900832
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2068032269
Short name T411
Test name
Test status
Simulation time 29844761 ps
CPU time 2.62 seconds
Started Mar 23 04:00:11 PM PDT 24
Finished Mar 23 04:00:14 PM PDT 24
Peak memory 214280 kb
Host smart-5f0071f7-811f-492b-ae2d-e75cf63d117c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2068032269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2068032269
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2698073056
Short name T31
Test name
Test status
Simulation time 770624153 ps
CPU time 7.69 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:00:21 PM PDT 24
Peak memory 214628 kb
Host smart-b2f87902-de15-4a00-910b-069d3f10abf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698073056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2698073056
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2644841856
Short name T800
Test name
Test status
Simulation time 126601973 ps
CPU time 3.63 seconds
Started Mar 23 04:00:16 PM PDT 24
Finished Mar 23 04:00:20 PM PDT 24
Peak memory 214360 kb
Host smart-57b8fd75-d4f1-4956-8199-3b670a6ed513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644841856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2644841856
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.740738426
Short name T255
Test name
Test status
Simulation time 56741531 ps
CPU time 3.57 seconds
Started Mar 23 04:00:12 PM PDT 24
Finished Mar 23 04:00:16 PM PDT 24
Peak memory 209876 kb
Host smart-f419c581-40a4-4593-90e3-c0c3929923af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740738426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.740738426
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2495571813
Short name T42
Test name
Test status
Simulation time 532098280 ps
CPU time 3.23 seconds
Started Mar 23 04:00:12 PM PDT 24
Finished Mar 23 04:00:15 PM PDT 24
Peak memory 206140 kb
Host smart-67b35654-12d2-4285-98fc-e14afc22d84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495571813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2495571813
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1071238993
Short name T816
Test name
Test status
Simulation time 202801536 ps
CPU time 4.89 seconds
Started Mar 23 04:00:12 PM PDT 24
Finished Mar 23 04:00:17 PM PDT 24
Peak memory 214344 kb
Host smart-6d246e21-e036-4051-a7c7-eecb53cf9c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071238993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1071238993
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3265593857
Short name T930
Test name
Test status
Simulation time 61531093 ps
CPU time 3.3 seconds
Started Mar 23 04:00:17 PM PDT 24
Finished Mar 23 04:00:20 PM PDT 24
Peak memory 208532 kb
Host smart-af115e06-b237-4f80-a547-7ec09e5be4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265593857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3265593857
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2447005335
Short name T620
Test name
Test status
Simulation time 1189455363 ps
CPU time 6.68 seconds
Started Mar 23 04:00:11 PM PDT 24
Finished Mar 23 04:00:18 PM PDT 24
Peak memory 208160 kb
Host smart-60c0c2e0-f244-4da5-9717-5de71e200539
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447005335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2447005335
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.4028707428
Short name T877
Test name
Test status
Simulation time 158976163 ps
CPU time 2.58 seconds
Started Mar 23 04:00:15 PM PDT 24
Finished Mar 23 04:00:18 PM PDT 24
Peak memory 208460 kb
Host smart-1e0b5dad-978a-4ac9-b07f-65be546aa1cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028707428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.4028707428
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3608285069
Short name T400
Test name
Test status
Simulation time 633785588 ps
CPU time 6.83 seconds
Started Mar 23 04:00:12 PM PDT 24
Finished Mar 23 04:00:18 PM PDT 24
Peak memory 208008 kb
Host smart-fbf6acb9-eab9-4eb6-befd-ee6836a43d32
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608285069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3608285069
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1393797138
Short name T125
Test name
Test status
Simulation time 118779051 ps
CPU time 1.67 seconds
Started Mar 23 04:00:14 PM PDT 24
Finished Mar 23 04:00:16 PM PDT 24
Peak memory 209260 kb
Host smart-bc5c0c2f-ace7-484d-ac3b-b1118d763098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393797138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1393797138
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1879515873
Short name T817
Test name
Test status
Simulation time 132260987 ps
CPU time 2.45 seconds
Started Mar 23 04:00:12 PM PDT 24
Finished Mar 23 04:00:15 PM PDT 24
Peak memory 206756 kb
Host smart-09836322-725e-4d6f-baac-9307a89f993d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879515873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1879515873
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1251669225
Short name T746
Test name
Test status
Simulation time 181036185 ps
CPU time 6.38 seconds
Started Mar 23 04:00:11 PM PDT 24
Finished Mar 23 04:00:17 PM PDT 24
Peak memory 222712 kb
Host smart-d9d27548-35f3-4abe-8313-f7413263886b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251669225 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1251669225
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3238984250
Short name T976
Test name
Test status
Simulation time 7489030567 ps
CPU time 82.67 seconds
Started Mar 23 04:00:14 PM PDT 24
Finished Mar 23 04:01:37 PM PDT 24
Peak memory 209776 kb
Host smart-f37671c5-aa99-4e1c-815f-7b907353c9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238984250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3238984250
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.40944628
Short name T1021
Test name
Test status
Simulation time 189824655 ps
CPU time 4.12 seconds
Started Mar 23 04:00:12 PM PDT 24
Finished Mar 23 04:00:16 PM PDT 24
Peak memory 210352 kb
Host smart-8431e48f-e4b8-49c4-b326-0eb8d2bdada0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40944628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.40944628
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1785577745
Short name T819
Test name
Test status
Simulation time 36359836 ps
CPU time 0.95 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:00:14 PM PDT 24
Peak memory 206004 kb
Host smart-27fa686c-a648-43d1-a94d-6bf47a3b81af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785577745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1785577745
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2973033556
Short name T244
Test name
Test status
Simulation time 144220493 ps
CPU time 3.24 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:00:16 PM PDT 24
Peak memory 214460 kb
Host smart-3adf37f1-57c9-41bc-9113-aa9ec4aae993
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2973033556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2973033556
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3420980784
Short name T306
Test name
Test status
Simulation time 81874165 ps
CPU time 1.62 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:00:15 PM PDT 24
Peak memory 207764 kb
Host smart-bc00d37c-f45d-4435-ac43-db9ee13e3c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420980784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3420980784
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3211774748
Short name T85
Test name
Test status
Simulation time 797330144 ps
CPU time 5.14 seconds
Started Mar 23 04:00:11 PM PDT 24
Finished Mar 23 04:00:16 PM PDT 24
Peak memory 214364 kb
Host smart-c5409d89-3e4a-4a4e-a1ae-e6b1a08fb1d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211774748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3211774748
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3911222524
Short name T257
Test name
Test status
Simulation time 9499536393 ps
CPU time 51.42 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:01:05 PM PDT 24
Peak memory 222564 kb
Host smart-b8dc911b-feec-42a0-affc-c9e9ed57dd43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911222524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3911222524
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.3324468459
Short name T649
Test name
Test status
Simulation time 377152282 ps
CPU time 4.88 seconds
Started Mar 23 04:00:14 PM PDT 24
Finished Mar 23 04:00:19 PM PDT 24
Peak memory 219932 kb
Host smart-8351ec8c-b256-457d-a9cf-d58c2e1e3ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324468459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.3324468459
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3108451416
Short name T316
Test name
Test status
Simulation time 91163871 ps
CPU time 2.1 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:00:16 PM PDT 24
Peak memory 214312 kb
Host smart-ae906d3f-f9f3-4a19-a238-87e3bac5fb5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108451416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3108451416
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3556061952
Short name T314
Test name
Test status
Simulation time 91619929 ps
CPU time 3.8 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:00:17 PM PDT 24
Peak memory 208620 kb
Host smart-b85709c8-1146-4149-becc-a86b0d52e8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556061952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3556061952
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3722880456
Short name T17
Test name
Test status
Simulation time 55489022 ps
CPU time 3.04 seconds
Started Mar 23 04:00:11 PM PDT 24
Finished Mar 23 04:00:14 PM PDT 24
Peak memory 207368 kb
Host smart-774c7495-9e2b-4e3e-8790-7fdfbb84b61c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722880456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3722880456
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.911543363
Short name T639
Test name
Test status
Simulation time 225577420 ps
CPU time 3.09 seconds
Started Mar 23 04:00:14 PM PDT 24
Finished Mar 23 04:00:17 PM PDT 24
Peak memory 208500 kb
Host smart-a3f09c1f-54ad-40e6-82e4-ca8e770433ff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911543363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.911543363
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2148981127
Short name T956
Test name
Test status
Simulation time 74681227 ps
CPU time 3.35 seconds
Started Mar 23 04:00:11 PM PDT 24
Finished Mar 23 04:00:14 PM PDT 24
Peak memory 208952 kb
Host smart-ea4994b2-7d24-4274-a279-a758d81f1db3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148981127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2148981127
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.4123633495
Short name T216
Test name
Test status
Simulation time 229856039 ps
CPU time 4.19 seconds
Started Mar 23 04:00:14 PM PDT 24
Finished Mar 23 04:00:18 PM PDT 24
Peak memory 209216 kb
Host smart-bf06bdcd-9bec-4b5d-aada-10733217fb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123633495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4123633495
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1290917835
Short name T814
Test name
Test status
Simulation time 288268377 ps
CPU time 4.2 seconds
Started Mar 23 04:00:12 PM PDT 24
Finished Mar 23 04:00:16 PM PDT 24
Peak memory 208396 kb
Host smart-25a89736-0af0-4581-9047-d35da623b872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290917835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1290917835
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2624931649
Short name T344
Test name
Test status
Simulation time 4841072031 ps
CPU time 33.41 seconds
Started Mar 23 04:00:10 PM PDT 24
Finished Mar 23 04:00:44 PM PDT 24
Peak memory 214428 kb
Host smart-52bd489f-7a57-4cc9-97eb-d90797cb7c4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624931649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2624931649
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.85370732
Short name T264
Test name
Test status
Simulation time 975153990 ps
CPU time 11.81 seconds
Started Mar 23 04:00:18 PM PDT 24
Finished Mar 23 04:00:30 PM PDT 24
Peak memory 220780 kb
Host smart-33020d3f-f046-4eb1-9175-63266fdbc434
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85370732 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.85370732
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.708610933
Short name T387
Test name
Test status
Simulation time 1505134001 ps
CPU time 33.75 seconds
Started Mar 23 04:00:10 PM PDT 24
Finished Mar 23 04:00:44 PM PDT 24
Peak memory 209684 kb
Host smart-9cb017d5-0e0c-4031-ad37-fbce40e412bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708610933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.708610933
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.509911955
Short name T1055
Test name
Test status
Simulation time 82433784 ps
CPU time 3.32 seconds
Started Mar 23 04:00:12 PM PDT 24
Finished Mar 23 04:00:15 PM PDT 24
Peak memory 210352 kb
Host smart-8b7b68aa-0527-4e4b-b01e-f80cea911a3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509911955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.509911955
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.938405602
Short name T880
Test name
Test status
Simulation time 41828401 ps
CPU time 0.86 seconds
Started Mar 23 04:00:12 PM PDT 24
Finished Mar 23 04:00:12 PM PDT 24
Peak memory 205860 kb
Host smart-b43e9568-597d-4b2a-8240-c134a1b781a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938405602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.938405602
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1803953023
Short name T1059
Test name
Test status
Simulation time 88071726 ps
CPU time 3.82 seconds
Started Mar 23 04:00:16 PM PDT 24
Finished Mar 23 04:00:21 PM PDT 24
Peak memory 208484 kb
Host smart-7a5ff3b0-2210-4412-9848-7a1de2326e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803953023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1803953023
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1976675982
Short name T253
Test name
Test status
Simulation time 86053502 ps
CPU time 2.74 seconds
Started Mar 23 04:00:16 PM PDT 24
Finished Mar 23 04:00:19 PM PDT 24
Peak memory 218248 kb
Host smart-bc5483e0-07bc-47db-9551-d8d153dd4c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976675982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1976675982
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.265915774
Short name T302
Test name
Test status
Simulation time 1350643199 ps
CPU time 40.93 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:00:54 PM PDT 24
Peak memory 214352 kb
Host smart-34268b18-3cd6-46dd-8287-77a30cf8d0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265915774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.265915774
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.987419129
Short name T415
Test name
Test status
Simulation time 72475917 ps
CPU time 3.23 seconds
Started Mar 23 04:00:11 PM PDT 24
Finished Mar 23 04:00:14 PM PDT 24
Peak memory 216288 kb
Host smart-da7bffdf-8e01-45fc-8c9a-0cb3917af389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987419129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.987419129
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1139892181
Short name T982
Test name
Test status
Simulation time 5311893275 ps
CPU time 52.13 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:01:05 PM PDT 24
Peak memory 218400 kb
Host smart-2963b009-4ed6-4f73-bd9b-9029a049e005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139892181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1139892181
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2468421228
Short name T992
Test name
Test status
Simulation time 1789915090 ps
CPU time 44.95 seconds
Started Mar 23 04:00:14 PM PDT 24
Finished Mar 23 04:00:59 PM PDT 24
Peak memory 208564 kb
Host smart-df483bda-848a-4929-95e7-89890ae8dda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468421228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2468421228
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1928441141
Short name T655
Test name
Test status
Simulation time 75402901 ps
CPU time 2.88 seconds
Started Mar 23 04:00:11 PM PDT 24
Finished Mar 23 04:00:14 PM PDT 24
Peak memory 208656 kb
Host smart-35e27f90-a815-473f-ae4e-4e4afb9021e4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928441141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1928441141
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1506355609
Short name T955
Test name
Test status
Simulation time 1435558010 ps
CPU time 11.06 seconds
Started Mar 23 04:00:11 PM PDT 24
Finished Mar 23 04:00:22 PM PDT 24
Peak memory 207996 kb
Host smart-a65da28d-ca7c-4a65-8408-2be6f4b2c7d4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506355609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1506355609
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.4271016777
Short name T590
Test name
Test status
Simulation time 126363766 ps
CPU time 2.34 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:00:15 PM PDT 24
Peak memory 206764 kb
Host smart-da9a0bf1-000b-4502-b463-89672172ebe7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271016777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.4271016777
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1531644605
Short name T601
Test name
Test status
Simulation time 33560373 ps
CPU time 2.45 seconds
Started Mar 23 04:00:14 PM PDT 24
Finished Mar 23 04:00:16 PM PDT 24
Peak memory 215968 kb
Host smart-1c19a91b-e5a7-4c5b-b8d1-c55740399d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531644605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1531644605
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3492224402
Short name T889
Test name
Test status
Simulation time 1604321167 ps
CPU time 9.07 seconds
Started Mar 23 04:00:14 PM PDT 24
Finished Mar 23 04:00:23 PM PDT 24
Peak memory 208612 kb
Host smart-4d879a15-04aa-4e92-bad6-e922e801dfe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492224402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3492224402
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1313462402
Short name T994
Test name
Test status
Simulation time 317263989 ps
CPU time 4.64 seconds
Started Mar 23 04:00:07 PM PDT 24
Finished Mar 23 04:00:12 PM PDT 24
Peak memory 215308 kb
Host smart-9d675277-a50e-4472-9edc-892abb4dc380
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313462402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1313462402
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3253831491
Short name T393
Test name
Test status
Simulation time 213314672 ps
CPU time 6.19 seconds
Started Mar 23 04:00:16 PM PDT 24
Finished Mar 23 04:00:23 PM PDT 24
Peak memory 220044 kb
Host smart-83e06eb7-9cac-4f52-b7c6-79d3313593b0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253831491 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3253831491
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3247134259
Short name T396
Test name
Test status
Simulation time 351304079 ps
CPU time 9.29 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:00:22 PM PDT 24
Peak memory 207372 kb
Host smart-c00957b6-cc3a-4fe2-b088-728420758823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247134259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3247134259
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1890577066
Short name T161
Test name
Test status
Simulation time 140610731 ps
CPU time 2.41 seconds
Started Mar 23 04:00:17 PM PDT 24
Finished Mar 23 04:00:19 PM PDT 24
Peak memory 210120 kb
Host smart-28872041-b1e9-47f7-a784-33d5238efa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890577066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1890577066
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.735803065
Short name T662
Test name
Test status
Simulation time 10794584 ps
CPU time 0.83 seconds
Started Mar 23 04:00:26 PM PDT 24
Finished Mar 23 04:00:27 PM PDT 24
Peak memory 205896 kb
Host smart-713ed1f2-3ecd-4329-8a20-71419f91bac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735803065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.735803065
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2184690505
Short name T424
Test name
Test status
Simulation time 34756604 ps
CPU time 2.88 seconds
Started Mar 23 04:00:12 PM PDT 24
Finished Mar 23 04:00:15 PM PDT 24
Peak memory 214272 kb
Host smart-6b19c7cf-bf9f-46a6-8c60-61a48f323426
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2184690505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2184690505
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.4007473522
Short name T997
Test name
Test status
Simulation time 63695232 ps
CPU time 1.37 seconds
Started Mar 23 04:00:14 PM PDT 24
Finished Mar 23 04:00:15 PM PDT 24
Peak memory 208024 kb
Host smart-8a900635-5158-44d5-975f-32c9c368f9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007473522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4007473522
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3549688891
Short name T672
Test name
Test status
Simulation time 221537109 ps
CPU time 3.62 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:00:17 PM PDT 24
Peak memory 208552 kb
Host smart-8204dec4-4ebb-42ff-95ef-174835b0ac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549688891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3549688891
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1110407683
Short name T771
Test name
Test status
Simulation time 168163363 ps
CPU time 4.59 seconds
Started Mar 23 04:00:21 PM PDT 24
Finished Mar 23 04:00:26 PM PDT 24
Peak memory 210200 kb
Host smart-4639f459-5957-4149-8ce9-2be7b26bc4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110407683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1110407683
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2519307251
Short name T342
Test name
Test status
Simulation time 137529013 ps
CPU time 5.77 seconds
Started Mar 23 04:00:13 PM PDT 24
Finished Mar 23 04:00:19 PM PDT 24
Peak memory 209708 kb
Host smart-6a7e5ed2-f3be-47e2-8532-87a8c99eb338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519307251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2519307251
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1719185109
Short name T247
Test name
Test status
Simulation time 7381001741 ps
CPU time 48.33 seconds
Started Mar 23 04:00:12 PM PDT 24
Finished Mar 23 04:01:00 PM PDT 24
Peak memory 208864 kb
Host smart-ed1988b3-c5d7-46ae-b9fa-f6f99348ea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719185109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1719185109
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.360153986
Short name T828
Test name
Test status
Simulation time 29623006 ps
CPU time 2.26 seconds
Started Mar 23 04:00:12 PM PDT 24
Finished Mar 23 04:00:15 PM PDT 24
Peak memory 206900 kb
Host smart-62d2fdd2-a151-4456-8ebc-f913d17ffd2b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360153986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.360153986
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.4116728427
Short name T635
Test name
Test status
Simulation time 51136560 ps
CPU time 2.79 seconds
Started Mar 23 04:00:11 PM PDT 24
Finished Mar 23 04:00:14 PM PDT 24
Peak memory 208416 kb
Host smart-8b7880b6-1bd7-4317-b0b7-fd46c683d943
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116728427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.4116728427
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1449548483
Short name T593
Test name
Test status
Simulation time 1044032230 ps
CPU time 7.67 seconds
Started Mar 23 04:00:12 PM PDT 24
Finished Mar 23 04:00:19 PM PDT 24
Peak memory 208412 kb
Host smart-acb27e79-57de-4c8c-aecc-95cb2a73ef65
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449548483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1449548483
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.4042321127
Short name T267
Test name
Test status
Simulation time 1051582806 ps
CPU time 4.91 seconds
Started Mar 23 04:00:25 PM PDT 24
Finished Mar 23 04:00:30 PM PDT 24
Peak memory 209148 kb
Host smart-4de1c5f7-f06a-4b83-b66e-f0c1014527b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042321127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.4042321127
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2079648516
Short name T752
Test name
Test status
Simulation time 191885377 ps
CPU time 2.69 seconds
Started Mar 23 04:00:14 PM PDT 24
Finished Mar 23 04:00:17 PM PDT 24
Peak memory 207352 kb
Host smart-d0baded4-7824-43f5-afe5-840c14f6b924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079648516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2079648516
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1682295084
Short name T270
Test name
Test status
Simulation time 1852908640 ps
CPU time 36.15 seconds
Started Mar 23 04:00:31 PM PDT 24
Finished Mar 23 04:01:08 PM PDT 24
Peak memory 222444 kb
Host smart-148c5cad-5224-45a1-ba3d-18758f6a2b2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682295084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1682295084
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.3051264250
Short name T901
Test name
Test status
Simulation time 87236613 ps
CPU time 3.14 seconds
Started Mar 23 04:00:26 PM PDT 24
Finished Mar 23 04:00:30 PM PDT 24
Peak memory 214432 kb
Host smart-6850a3c2-26a8-4ee2-8e22-58d10955de98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051264250 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.3051264250
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2573556030
Short name T249
Test name
Test status
Simulation time 2622770783 ps
CPU time 66.25 seconds
Started Mar 23 04:00:14 PM PDT 24
Finished Mar 23 04:01:20 PM PDT 24
Peak memory 208956 kb
Host smart-058c230c-c69a-45ec-8c3e-715cf0a54ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573556030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2573556030
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.821878055
Short name T806
Test name
Test status
Simulation time 2326804611 ps
CPU time 12.35 seconds
Started Mar 23 04:00:26 PM PDT 24
Finished Mar 23 04:00:38 PM PDT 24
Peak memory 219632 kb
Host smart-9d4ae285-0917-43b0-875a-28e658c47c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821878055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.821878055
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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