Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
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Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
71.43 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv


Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 14 1 13 92.86
Crosses 49 17 32 65.31


Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
op_cp 5 1 4 80.00 100 1 1 0
state_cp 7 0 7 100.00 100 1 1 0
wip_cp 2 0 2 100.00 100 1 1 2


Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
state_x_wip_cross 14 1 13 92.86 100 1 1 0
state_x_op_cross 35 16 19 54.29 100 1 1 0


Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 1 4 80.00


Automatically Generated Bins for op_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[OpDisable] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[OpAdvance] 103 1 T6 3 T48 1 T112 1
auto[OpGenId] 20 1 T103 2 T7 2 T112 1
auto[OpGenSwOut] 40 1 T36 1 T7 1 T112 2
auto[OpGenHwOut] 26 1 T6 2 T7 1 T37 1


Summary for Variable state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for state_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] 1876 1 T35 1 T103 3 T6 1
auto[StInit] 167 1 T103 2 T6 5 T50 2
auto[StCreatorRootKey] 67 1 T36 1 T40 1 T112 1
auto[StOwnerIntKey] 37 1 T42 1 T37 1 T61 1
auto[StOwnerKey] 33 1 T46 1 T67 1 T65 1
auto[StDisabled] 410 1 T6 13 T50 10 T60 14
auto[StInvalid] 47 1 T41 1 T27 1 T29 1


Summary for Variable wip_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wip_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3524 1 T1 1 T2 1 T3 1
auto[1] 189 1 T103 2 T6 5 T36 1


Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 14 1 13 92.86 1


Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins
state_cpwip_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] [auto[1]] 0 1 1


Covered bins
state_cp   wip_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[0] 1852 1 T35 1 T103 3 T6 1
auto[StReset] auto[1] 24 1 T122 1 T124 1 T51 1
auto[StInit] auto[0] 66 1 T50 2 T7 1 T113 2
auto[StInit] auto[1] 101 1 T103 2 T6 5 T7 4
auto[StCreatorRootKey] auto[0] 34 1 T40 1 T203 1 T22 1
auto[StCreatorRootKey] auto[1] 33 1 T36 1 T112 1 T57 1
auto[StOwnerIntKey] auto[0] 21 1 T42 1 T61 1 T199 1
auto[StOwnerIntKey] auto[1] 16 1 T37 1 T62 1 T63 1
auto[StOwnerKey] auto[0] 28 1 T46 1 T67 1 T65 1
auto[StOwnerKey] auto[1] 5 1 T68 1 T204 1 T205 1
auto[StDisabled] auto[0] 400 1 T6 13 T50 10 T60 14
auto[StDisabled] auto[1] 10 1 T122 1 T206 1 T84 1
auto[StInvalid] auto[0] 47 1 T41 1 T27 1 T29 1


Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 35 16 19 54.29 16


Automatically Generated Cross Bins for state_x_op_cross

Element holes
state_cpop_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] * -- -- 5


Uncovered bins
state_cp   op_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[StReset]] [auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]] -- -- 4
[auto[StInit] , auto[StCreatorRootKey]] [auto[OpDisable]] -- -- 2
[auto[StOwnerIntKey] , auto[StOwnerKey]] [auto[OpGenId]] -- -- 2
[auto[StOwnerIntKey] , auto[StOwnerKey]] [auto[OpDisable]] -- -- 2
[auto[StDisabled]] [auto[OpDisable]] 0 1 1


Covered bins
state_cp   op_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[OpAdvance] 24 1 T122 1 T124 1 T51 1
auto[StInit] auto[OpAdvance] 48 1 T6 3 T48 1 T112 1
auto[StInit] auto[OpGenId] 14 1 T103 2 T7 2 T112 1
auto[StInit] auto[OpGenSwOut] 21 1 T7 1 T112 1 T75 1
auto[StInit] auto[OpGenHwOut] 18 1 T6 2 T7 1 T123 2
auto[StCreatorRootKey] auto[OpAdvance] 17 1 T57 1 T122 1 T123 1
auto[StCreatorRootKey] auto[OpGenId] 5 1 T58 1 T20 1 T45 1
auto[StCreatorRootKey] auto[OpGenSwOut] 8 1 T36 1 T112 1 T207 1
auto[StCreatorRootKey] auto[OpGenHwOut] 3 1 T8 1 T208 1 T209 1
auto[StOwnerIntKey] auto[OpAdvance] 6 1 T62 1 T210 1 T211 1
auto[StOwnerIntKey] auto[OpGenSwOut] 7 1 T63 1 T211 1 T207 1
auto[StOwnerIntKey] auto[OpGenHwOut] 3 1 T37 1 T212 1 T213 1
auto[StOwnerKey] auto[OpAdvance] 3 1 T204 1 T214 1 T215 1
auto[StOwnerKey] auto[OpGenSwOut] 1 1 T68 1 - - - -
auto[StOwnerKey] auto[OpGenHwOut] 1 1 T205 1 - - - -
auto[StDisabled] auto[OpAdvance] 5 1 T122 1 T206 1 T204 1
auto[StDisabled] auto[OpGenId] 1 1 T216 1 - - - -
auto[StDisabled] auto[OpGenSwOut] 3 1 T84 1 T179 1 T217 1
auto[StDisabled] auto[OpGenHwOut] 1 1 T218 1 - - - -