Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11879

1

T1

4

T2

7

T3

10

auto[Attestation]

8412

1

T1

4

T2

6

T3

2

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	3004	1			T2	1		T4	6		T5	2
auto[Aes]	3584	1			T2	3		T3	12		T4	2
auto[Kmac]	3674	1			T4	4		T17	10		T18	6
auto[Otbn]	3735	1			T1	8		T2	4		T4	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7911	1			T1	8		T2	4		T3	8
auto[OpGenId]	6294	1			T2	5		T4	8		T5	5
auto[OpGenSwOut]	6380	1			T2	3		T4	6		T5	3
auto[OpGenHwOut]	7617	1			T1	8		T2	5		T3	12
auto[OpDisable]	137	1			T2	1		T6	2		T50	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10318

1

T1

8

T2

12

T3

8

auto[OpDoneFail]

18021

1

T1

8

T2

6

T3

12

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6886	1			T1	1		T2	1		T3	5
auto[StInit]	4537	1			T1	2		T2	5		T3	2
auto[StCreatorRootKey]	2984	1			T1	2		T2	3		T3	2
auto[StOwnerIntKey]	2810	1			T1	2		T2	5		T3	2
auto[StOwnerKey]	2343	1			T1	2		T2	2		T3	2
auto[StDisabled]	7707	1			T1	7		T2	2		T3	7
auto[StInvalid]	1072	1			T41	18		T27	15		T29	21

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	390	1			T4	1		T18	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	110	1			T2	1		T6	4		T50	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	63	1			T129	1		T6	2		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	71	1			T5	1		T119	1		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	50	1			T50	2		T60	2		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	219	1			T18	1		T19	1		T30	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	39	1			T41	1		T29	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	357	1			T41	3		T103	2		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	137	1			T5	1		T104	1		T50	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	70	1			T30	1		T6	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	71	1			T119	1		T6	2		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	41	1			T19	1		T6	1		T60	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	225	1			T30	1		T6	2		T50	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	39	1			T27	1		T29	1		T190	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	353	1			T18	1		T41	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	118	1			T104	1		T50	3		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	60	1			T131	1		T6	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T4	1		T19	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	62	1			T119	1		T50	2		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	204	1			T18	2		T30	1		T129	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	36	1			T41	2		T29	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	355	1			T4	1		T18	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	114	1			T6	1		T60	3		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	75	1			T2	1		T6	2		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	73	1			T6	2		T50	1		T60	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	56	1			T30	1		T60	2		T7	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	220	1			T19	1		T30	2		T6	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	36	1			T27	2		T190	1		T196	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	84	1			T6	3		T50	5		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	117	1			T19	1		T6	4		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T6	1		T60	2		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	70	1			T6	1		T60	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	60	1			T4	2		T119	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	198	1			T119	2		T6	5		T50	5
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	41	1			T41	2		T27	2		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	87	1			T41	1		T6	4		T50	5
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	134	1			T6	3		T50	1		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	93	1			T60	3		T7	1		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	78	1			T119	1		T50	1		T7	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	57	1			T18	1		T19	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	210	1			T5	1		T18	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	28	1			T27	1		T29	1		T190	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	89	1			T6	2		T50	6		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	144	1			T50	3		T60	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	68	1			T6	2		T60	3		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	57	1			T19	1		T6	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	62	1			T119	1		T6	1		T7	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	192	1			T18	1		T30	3		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	31	1			T29	1		T196	1		T197	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	81	1			T6	2		T50	2		T7	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	122	1			T6	1		T50	3		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	72	1			T129	1		T50	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	58	1			T2	1		T6	1		T60	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	64	1			T104	1		T50	1		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	228	1			T4	1		T119	2		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	43	1			T41	1		T27	1		T29	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	295	1			T18	1		T41	1		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	113	1			T129	1		T6	1		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	76	1			T6	1		T60	2		T7	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	70	1			T129	1		T6	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	39	1			T4	1		T6	1		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	178	1			T19	1		T119	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	29	1			T200	1		T99	1		T201	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	412	1			T3	4		T104	1		T103	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	145	1			T2	1		T30	1		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	99	1			T3	1		T15	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	98	1			T2	1		T3	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	94	1			T3	1		T15	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	259	1			T3	3		T4	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	29	1			T190	1		T196	2		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	519	1			T4	1		T17	2		T104	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	132	1			T17	1		T129	1		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T17	1		T129	1		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	105	1			T17	1		T6	1		T98	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	101	1			T18	1		T104	1		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	285	1			T17	3		T18	1		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	38	1			T41	1		T190	1		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	509	1			T4	1		T18	3		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	152	1			T1	1		T19	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	90	1			T16	1		T6	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	108	1			T16	1		T104	2		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	83	1			T1	1		T19	1		T119	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	293	1			T1	2		T16	3		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	34	1			T27	1		T200	2		T202	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	77	1			T6	2		T50	3		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	131	1			T4	1		T6	1		T50	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	93	1			T6	1		T60	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	64	1			T129	1		T6	1		T60	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	44	1			T6	1		T60	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	169	1			T4	1		T5	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	37	1			T41	1		T190	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	68	1			T41	1		T6	1		T50	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	158	1			T3	1		T15	1		T104	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	102	1			T4	1		T6	1		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	110	1			T15	1		T19	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	94	1			T2	1		T30	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	265	1			T3	1		T15	3		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	24	1			T27	1		T196	2		T197	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	66	1			T41	1		T6	3		T50	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	170	1			T133	1		T119	1		T60	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	114	1			T133	1		T119	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	117	1			T133	1		T130	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	76	1			T17	1		T130	1		T50	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	263	1			T4	2		T17	1		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	30	1			T29	1		T190	1		T196	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	71	1			T41	1		T6	3		T50	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	161	1			T16	1		T18	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	114	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	97	1			T1	1		T2	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	77	1			T16	1		T104	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	308	1			T1	2		T16	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	41	1			T41	1		T190	1		T196	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	166	1			T5	1		T129	1		T119	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	776	1			T2	1		T4	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	173	1			T19	1		T30	1		T119	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	767	1			T5	1		T30	1		T41	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	196	1			T4	1		T19	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	728	1			T18	3		T30	1		T41	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	188	1			T2	1		T30	1		T6	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	741	1			T4	1		T18	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	193	1			T4	2		T119	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	454	1			T19	1		T41	2		T119	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	207	1			T18	1		T19	1		T119	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	480	1			T5	1		T18	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	166	1			T19	1		T119	1		T6	4
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	477	1			T18	1		T30	3		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	181	1			T2	1		T104	1		T129	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	487	1			T4	1		T41	1		T119	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	165	1			T4	1		T129	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	635	1			T18	1		T19	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	274	1			T2	1		T3	3		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	862	1			T2	1		T3	7		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	284	1			T17	2		T18	1		T104	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	987	1			T4	1		T17	6		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	262	1			T1	1		T16	2		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	1007	1			T1	3		T4	1		T16	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	183	1			T129	1		T6	3		T60	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	432	1			T4	2		T5	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	290	1			T2	1		T4	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	531	1			T3	2		T15	4		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	292	1			T17	1		T133	2		T130	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	544	1			T4	2		T17	1		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	270	1			T1	2		T2	2		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	599	1			T1	2		T4	1		T16	2