Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32483

1

T1

22

T2

20

T3

25

auto[1]

312

1

T19

7

T119

8

T134

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32493	1			T1	22		T2	20		T3	25
auto[134217728:268435455]	12	1			T135	2		T292	1		T347	1
auto[268435456:402653183]	9	1			T188	1		T135	1		T109	1
auto[402653184:536870911]	8	1			T266	1		T267	1		T393	1
auto[536870912:671088639]	8	1			T188	2		T321	1		T267	1
auto[671088640:805306367]	12	1			T119	1		T135	2		T292	1
auto[805306368:939524095]	10	1			T19	1		T266	1		T267	1
auto[939524096:1073741823]	6	1			T109	1		T370	1		T394	1
auto[1073741824:1207959551]	7	1			T188	1		T135	1		T255	1
auto[1207959552:1342177279]	10	1			T119	1		T135	1		T292	1
auto[1342177280:1476395007]	16	1			T19	1		T119	1		T150	1
auto[1476395008:1610612735]	11	1			T134	1		T109	1		T294	1
auto[1610612736:1744830463]	14	1			T134	1		T188	1		T292	1
auto[1744830464:1879048191]	11	1			T19	1		T109	1		T294	2
auto[1879048192:2013265919]	16	1			T119	1		T109	1		T395	1
auto[2013265920:2147483647]	9	1			T292	1		T304	1		T393	2
auto[2147483648:2281701375]	6	1			T119	1		T347	2		T243	1
auto[2281701376:2415919103]	14	1			T19	1		T119	1		T188	1
auto[2415919104:2550136831]	5	1			T119	1		T188	1		T109	1
auto[2550136832:2684354559]	10	1			T109	1		T292	2		T396	2
auto[2684354560:2818572287]	7	1			T19	1		T135	1		T397	1
auto[2818572288:2952790015]	5	1			T267	1		T304	1		T398	3
auto[2952790016:3087007743]	9	1			T135	1		T397	1		T394	1
auto[3087007744:3221225471]	14	1			T119	1		T134	1		T188	1
auto[3221225472:3355443199]	5	1			T109	1		T292	1		T294	1
auto[3355443200:3489660927]	12	1			T134	1		T109	1		T270	1
auto[3489660928:3623878655]	10	1			T135	1		T347	2		T395	1
auto[3623878656:3758096383]	6	1			T19	1		T109	1		T347	1
auto[3758096384:3892314111]	13	1			T19	1		T150	1		T188	1
auto[3892314112:4026531839]	12	1			T188	1		T135	1		T347	1
auto[4026531840:4160749567]	6	1			T188	1		T292	1		T294	1
auto[4160749568:4294967295]	9	1			T134	1		T266	2		T243	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32483	1			T1	22		T2	20		T3	25
auto[0:134217727]	auto[1]	10	1			T188	1		T292	1		T294	2
auto[134217728:268435455]	auto[1]	12	1			T135	2		T292	1		T347	1
auto[268435456:402653183]	auto[1]	9	1			T188	1		T135	1		T109	1
auto[402653184:536870911]	auto[1]	8	1			T266	1		T267	1		T393	1
auto[536870912:671088639]	auto[1]	8	1			T188	2		T321	1		T267	1
auto[671088640:805306367]	auto[1]	12	1			T119	1		T135	2		T292	1
auto[805306368:939524095]	auto[1]	10	1			T19	1		T266	1		T267	1
auto[939524096:1073741823]	auto[1]	6	1			T109	1		T370	1		T394	1
auto[1073741824:1207959551]	auto[1]	7	1			T188	1		T135	1		T255	1
auto[1207959552:1342177279]	auto[1]	10	1			T119	1		T135	1		T292	1
auto[1342177280:1476395007]	auto[1]	16	1			T19	1		T119	1		T150	1
auto[1476395008:1610612735]	auto[1]	11	1			T134	1		T109	1		T294	1
auto[1610612736:1744830463]	auto[1]	14	1			T134	1		T188	1		T292	1
auto[1744830464:1879048191]	auto[1]	11	1			T19	1		T109	1		T294	2
auto[1879048192:2013265919]	auto[1]	16	1			T119	1		T109	1		T395	1
auto[2013265920:2147483647]	auto[1]	9	1			T292	1		T304	1		T393	2
auto[2147483648:2281701375]	auto[1]	6	1			T119	1		T347	2		T243	1
auto[2281701376:2415919103]	auto[1]	14	1			T19	1		T119	1		T188	1
auto[2415919104:2550136831]	auto[1]	5	1			T119	1		T188	1		T109	1
auto[2550136832:2684354559]	auto[1]	10	1			T109	1		T292	2		T396	2
auto[2684354560:2818572287]	auto[1]	7	1			T19	1		T135	1		T397	1
auto[2818572288:2952790015]	auto[1]	5	1			T267	1		T304	1		T398	3
auto[2952790016:3087007743]	auto[1]	9	1			T135	1		T397	1		T394	1
auto[3087007744:3221225471]	auto[1]	14	1			T119	1		T134	1		T188	1
auto[3221225472:3355443199]	auto[1]	5	1			T109	1		T292	1		T294	1
auto[3355443200:3489660927]	auto[1]	12	1			T134	1		T109	1		T270	1
auto[3489660928:3623878655]	auto[1]	10	1			T135	1		T347	2		T395	1
auto[3623878656:3758096383]	auto[1]	6	1			T19	1		T109	1		T347	1
auto[3758096384:3892314111]	auto[1]	13	1			T19	1		T150	1		T188	1
auto[3892314112:4026531839]	auto[1]	12	1			T188	1		T135	1		T347	1
auto[4026531840:4160749567]	auto[1]	6	1			T188	1		T292	1		T294	1
auto[4160749568:4294967295]	auto[1]	9	1			T134	1		T266	2		T243	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1617

1

T2

1

T4

1

T5

5

auto[1]

1837

1

T2

1

T4

4

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T6	1		T86	1		T60	1
auto[134217728:268435455]	84	1			T5	1		T30	1		T6	1
auto[268435456:402653183]	96	1			T19	1		T50	1		T60	3
auto[402653184:536870911]	118	1			T5	1		T30	2		T104	1
auto[536870912:671088639]	103	1			T35	1		T6	1		T50	3
auto[671088640:805306367]	101	1			T19	1		T6	1		T50	1
auto[805306368:939524095]	101	1			T129	1		T6	3		T7	1
auto[939524096:1073741823]	125	1			T18	1		T19	1		T30	1
auto[1073741824:1207959551]	95	1			T4	1		T5	2		T41	1
auto[1207959552:1342177279]	100	1			T18	1		T41	1		T6	2
auto[1342177280:1476395007]	113	1			T4	1		T104	1		T103	1
auto[1476395008:1610612735]	130	1			T129	1		T50	1		T60	1
auto[1610612736:1744830463]	97	1			T4	1		T41	1		T50	1
auto[1744830464:1879048191]	114	1			T5	1		T6	2		T50	3
auto[1879048192:2013265919]	118	1			T6	2		T50	1		T7	1
auto[2013265920:2147483647]	95	1			T41	2		T129	1		T6	2
auto[2147483648:2281701375]	117	1			T2	1		T30	1		T104	1
auto[2281701376:2415919103]	115	1			T4	1		T129	1		T6	3
auto[2415919104:2550136831]	99	1			T86	1		T36	1		T60	3
auto[2550136832:2684354559]	127	1			T18	1		T6	3		T50	4
auto[2684354560:2818572287]	101	1			T18	1		T119	1		T6	1
auto[2818572288:2952790015]	107	1			T2	1		T18	1		T6	2
auto[2952790016:3087007743]	120	1			T41	1		T104	1		T129	1
auto[3087007744:3221225471]	105	1			T5	1		T7	1		T25	1
auto[3221225472:3355443199]	110	1			T4	1		T6	2		T50	1
auto[3355443200:3489660927]	101	1			T119	1		T6	2		T50	1
auto[3489660928:3623878655]	121	1			T104	1		T6	2		T50	3
auto[3623878656:3758096383]	117	1			T41	1		T129	1		T6	2
auto[3758096384:3892314111]	91	1			T41	1		T35	1		T6	3
auto[3892314112:4026531839]	119	1			T5	1		T19	1		T6	2
auto[4026531840:4160749567]	115	1			T41	1		T119	1		T6	1
auto[4160749568:4294967295]	103	1			T6	1		T60	1		T7	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	40	1			T6	1		T60	1		T7	1
auto[0:134217727]	auto[1]	56	1			T86	1		T122	1		T239	1
auto[134217728:268435455]	auto[0]	33	1			T5	1		T6	1		T7	1
auto[134217728:268435455]	auto[1]	51	1			T30	1		T60	1		T112	1
auto[268435456:402653183]	auto[0]	45	1			T60	1		T7	1		T27	2
auto[268435456:402653183]	auto[1]	51	1			T19	1		T50	1		T60	2
auto[402653184:536870911]	auto[0]	63	1			T5	1		T30	1		T104	1
auto[402653184:536870911]	auto[1]	55	1			T30	1		T6	1		T36	1
auto[536870912:671088639]	auto[0]	50	1			T35	1		T6	1		T50	2
auto[536870912:671088639]	auto[1]	53	1			T50	1		T7	1		T28	1
auto[671088640:805306367]	auto[0]	38	1			T50	1		T89	1		T62	1
auto[671088640:805306367]	auto[1]	63	1			T19	1		T6	1		T36	1
auto[805306368:939524095]	auto[0]	53	1			T281	1		T49	1		T286	1
auto[805306368:939524095]	auto[1]	48	1			T129	1		T6	3		T7	1
auto[939524096:1073741823]	auto[0]	58	1			T30	1		T129	1		T6	2
auto[939524096:1073741823]	auto[1]	67	1			T18	1		T19	1		T103	1
auto[1073741824:1207959551]	auto[0]	43	1			T5	1		T41	1		T6	3
auto[1073741824:1207959551]	auto[1]	52	1			T4	1		T5	1		T50	2
auto[1207959552:1342177279]	auto[0]	42	1			T41	1		T6	1		T7	1
auto[1207959552:1342177279]	auto[1]	58	1			T18	1		T6	1		T86	1
auto[1342177280:1476395007]	auto[0]	58	1			T104	1		T50	1		T98	1
auto[1342177280:1476395007]	auto[1]	55	1			T4	1		T103	1		T60	2
auto[1476395008:1610612735]	auto[0]	63	1			T7	1		T49	1		T150	1
auto[1476395008:1610612735]	auto[1]	67	1			T129	1		T50	1		T60	1
auto[1610612736:1744830463]	auto[0]	45	1			T4	1		T41	1		T50	1
auto[1610612736:1744830463]	auto[1]	52	1			T48	1		T73	1		T362	1
auto[1744830464:1879048191]	auto[0]	49	1			T50	1		T49	1		T122	1
auto[1744830464:1879048191]	auto[1]	65	1			T5	1		T6	2		T50	2
auto[1879048192:2013265919]	auto[0]	47	1			T7	1		T399	1		T80	1
auto[1879048192:2013265919]	auto[1]	71	1			T6	2		T50	1		T48	1
auto[2013265920:2147483647]	auto[0]	48	1			T41	2		T6	2		T50	1
auto[2013265920:2147483647]	auto[1]	47	1			T129	1		T50	1		T60	1
auto[2147483648:2281701375]	auto[0]	53	1			T2	1		T30	1		T60	1
auto[2147483648:2281701375]	auto[1]	64	1			T104	1		T6	1		T50	1
auto[2281701376:2415919103]	auto[0]	59	1			T6	3		T7	2		T64	1
auto[2281701376:2415919103]	auto[1]	56	1			T4	1		T129	1		T60	1
auto[2415919104:2550136831]	auto[0]	44	1			T36	1		T60	1		T7	1
auto[2415919104:2550136831]	auto[1]	55	1			T86	1		T60	2		T7	3
auto[2550136832:2684354559]	auto[0]	51	1			T6	1		T50	1		T60	2
auto[2550136832:2684354559]	auto[1]	76	1			T18	1		T6	2		T50	3
auto[2684354560:2818572287]	auto[0]	47	1			T119	1		T60	1		T7	1
auto[2684354560:2818572287]	auto[1]	54	1			T18	1		T6	1		T60	1
auto[2818572288:2952790015]	auto[0]	52	1			T6	2		T50	1		T60	1
auto[2818572288:2952790015]	auto[1]	55	1			T2	1		T18	1		T60	1
auto[2952790016:3087007743]	auto[0]	60	1			T41	1		T104	1		T129	1
auto[2952790016:3087007743]	auto[1]	60	1			T50	2		T28	1		T93	1
auto[3087007744:3221225471]	auto[0]	57	1			T5	1		T7	1		T25	1
auto[3087007744:3221225471]	auto[1]	48	1			T188	1		T190	1		T334	1
auto[3221225472:3355443199]	auto[0]	44	1			T6	2		T60	1		T123	1
auto[3221225472:3355443199]	auto[1]	66	1			T4	1		T50	1		T60	1
auto[3355443200:3489660927]	auto[0]	50	1			T6	2		T26	1		T198	1
auto[3355443200:3489660927]	auto[1]	51	1			T119	1		T50	1		T7	3
auto[3489660928:3623878655]	auto[0]	53	1			T104	1		T6	2		T7	3
auto[3489660928:3623878655]	auto[1]	68	1			T50	3		T60	1		T7	3
auto[3623878656:3758096383]	auto[0]	65	1			T41	1		T129	1		T6	1
auto[3623878656:3758096383]	auto[1]	52	1			T6	1		T7	3		T150	1
auto[3758096384:3892314111]	auto[0]	50	1			T41	1		T6	3		T247	1
auto[3758096384:3892314111]	auto[1]	41	1			T35	1		T60	1		T7	1
auto[3892314112:4026531839]	auto[0]	57	1			T5	1		T6	1		T7	2
auto[3892314112:4026531839]	auto[1]	62	1			T19	1		T6	1		T50	2
auto[4026531840:4160749567]	auto[0]	56	1			T119	1		T6	1		T7	2
auto[4026531840:4160749567]	auto[1]	59	1			T41	1		T50	1		T60	1
auto[4160749568:4294967295]	auto[0]	44	1			T6	1		T7	1		T43	1
auto[4160749568:4294967295]	auto[1]	59	1			T60	1		T7	1		T198	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1653

1

T2

1

T4

1

T5

4

auto[1]

1800

1

T2

1

T4

4

T5

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T5	1		T129	1		T119	1
auto[134217728:268435455]	100	1			T41	1		T7	5		T132	1
auto[268435456:402653183]	110	1			T4	1		T129	1		T60	2
auto[402653184:536870911]	108	1			T5	1		T18	1		T19	1
auto[536870912:671088639]	107	1			T18	1		T35	1		T6	2
auto[671088640:805306367]	111	1			T6	1		T36	1		T60	3
auto[805306368:939524095]	106	1			T5	1		T41	1		T129	1
auto[939524096:1073741823]	97	1			T30	1		T104	1		T6	2
auto[1073741824:1207959551]	107	1			T30	1		T6	3		T50	2
auto[1207959552:1342177279]	118	1			T5	1		T6	2		T7	3
auto[1342177280:1476395007]	124	1			T30	1		T103	1		T6	1
auto[1476395008:1610612735]	98	1			T104	1		T6	1		T60	1
auto[1610612736:1744830463]	105	1			T129	1		T6	1		T50	1
auto[1744830464:1879048191]	111	1			T35	1		T6	1		T50	2
auto[1879048192:2013265919]	117	1			T50	1		T7	3		T232	1
auto[2013265920:2147483647]	119	1			T30	1		T41	1		T50	2
auto[2147483648:2281701375]	85	1			T5	1		T6	1		T60	1
auto[2281701376:2415919103]	102	1			T6	2		T50	1		T60	3
auto[2415919104:2550136831]	118	1			T4	2		T30	1		T41	1
auto[2550136832:2684354559]	119	1			T19	1		T41	1		T104	1
auto[2684354560:2818572287]	122	1			T5	2		T6	2		T50	2
auto[2818572288:2952790015]	97	1			T18	1		T19	1		T41	1
auto[2952790016:3087007743]	100	1			T19	1		T6	3		T7	3
auto[3087007744:3221225471]	102	1			T50	1		T7	3		T25	1
auto[3221225472:3355443199]	105	1			T2	1		T4	1		T18	1
auto[3355443200:3489660927]	107	1			T2	1		T103	1		T119	1
auto[3489660928:3623878655]	105	1			T129	1		T6	2		T50	2
auto[3623878656:3758096383]	99	1			T103	1		T6	1		T7	1
auto[3758096384:3892314111]	117	1			T18	1		T6	3		T60	3
auto[3892314112:4026531839]	114	1			T6	4		T50	2		T60	2
auto[4026531840:4160749567]	116	1			T41	1		T129	1		T50	1
auto[4160749568:4294967295]	103	1			T4	1		T6	1		T50	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	38	1			T129	1		T119	1		T6	1
auto[0:134217727]	auto[1]	66	1			T5	1		T7	1		T64	1
auto[134217728:268435455]	auto[0]	46	1			T41	1		T7	2		T122	1
auto[134217728:268435455]	auto[1]	54	1			T7	3		T132	1		T33	1
auto[268435456:402653183]	auto[0]	52	1			T60	1		T49	2		T190	1
auto[268435456:402653183]	auto[1]	58	1			T4	1		T129	1		T60	1
auto[402653184:536870911]	auto[0]	48	1			T5	1		T41	1		T104	1
auto[402653184:536870911]	auto[1]	60	1			T18	1		T19	1		T119	1
auto[536870912:671088639]	auto[0]	46	1			T35	1		T6	2		T50	1
auto[536870912:671088639]	auto[1]	61	1			T18	1		T50	1		T7	3
auto[671088640:805306367]	auto[0]	53	1			T6	1		T36	1		T60	1
auto[671088640:805306367]	auto[1]	58	1			T60	2		T198	1		T281	1
auto[805306368:939524095]	auto[0]	46	1			T5	1		T129	1		T6	1
auto[805306368:939524095]	auto[1]	60	1			T41	1		T50	2		T7	1
auto[939524096:1073741823]	auto[0]	43	1			T30	1		T6	1		T7	1
auto[939524096:1073741823]	auto[1]	54	1			T104	1		T6	1		T60	2
auto[1073741824:1207959551]	auto[0]	52	1			T30	1		T6	3		T25	1
auto[1073741824:1207959551]	auto[1]	55	1			T50	2		T26	1		T122	1
auto[1207959552:1342177279]	auto[0]	53	1			T5	1		T6	2		T7	1
auto[1207959552:1342177279]	auto[1]	65	1			T7	2		T134	1		T188	1
auto[1342177280:1476395007]	auto[0]	59	1			T30	1		T60	2		T7	2
auto[1342177280:1476395007]	auto[1]	65	1			T103	1		T6	1		T50	1
auto[1476395008:1610612735]	auto[0]	43	1			T104	1		T6	1		T60	1
auto[1476395008:1610612735]	auto[1]	55	1			T7	1		T198	1		T112	1
auto[1610612736:1744830463]	auto[0]	45	1			T6	1		T7	1		T190	1
auto[1610612736:1744830463]	auto[1]	60	1			T129	1		T50	1		T36	1
auto[1744830464:1879048191]	auto[0]	50	1			T35	1		T7	2		T150	1
auto[1744830464:1879048191]	auto[1]	61	1			T6	1		T50	2		T60	1
auto[1879048192:2013265919]	auto[0]	62	1			T7	1		T190	1		T31	1
auto[1879048192:2013265919]	auto[1]	55	1			T50	1		T7	2		T232	1
auto[2013265920:2147483647]	auto[0]	51	1			T41	1		T50	1		T60	1
auto[2013265920:2147483647]	auto[1]	68	1			T30	1		T50	1		T60	1
auto[2147483648:2281701375]	auto[0]	37	1			T6	1		T60	1		T7	1
auto[2147483648:2281701375]	auto[1]	48	1			T5	1		T198	1		T281	1
auto[2281701376:2415919103]	auto[0]	46	1			T6	2		T49	1		T123	1
auto[2281701376:2415919103]	auto[1]	56	1			T50	1		T60	3		T7	1
auto[2415919104:2550136831]	auto[0]	64	1			T41	1		T6	1		T7	2
auto[2415919104:2550136831]	auto[1]	54	1			T4	2		T30	1		T6	2
auto[2550136832:2684354559]	auto[0]	60	1			T41	1		T104	1		T50	3
auto[2550136832:2684354559]	auto[1]	59	1			T19	1		T50	1		T281	1
auto[2684354560:2818572287]	auto[0]	62	1			T5	1		T50	1		T60	1
auto[2684354560:2818572287]	auto[1]	60	1			T5	1		T6	2		T50	1
auto[2818572288:2952790015]	auto[0]	60	1			T41	1		T104	1		T6	2
auto[2818572288:2952790015]	auto[1]	37	1			T18	1		T19	1		T6	1
auto[2952790016:3087007743]	auto[0]	45	1			T6	2		T7	1		T247	1
auto[2952790016:3087007743]	auto[1]	55	1			T19	1		T6	1		T7	2
auto[3087007744:3221225471]	auto[0]	46	1			T7	1		T37	1		T232	1
auto[3087007744:3221225471]	auto[1]	56	1			T50	1		T7	2		T25	1
auto[3221225472:3355443199]	auto[0]	52	1			T4	1		T41	1		T6	1
auto[3221225472:3355443199]	auto[1]	53	1			T2	1		T18	1		T129	1
auto[3355443200:3489660927]	auto[0]	54	1			T2	1		T6	2		T50	1
auto[3355443200:3489660927]	auto[1]	53	1			T103	1		T119	1		T6	4
auto[3489660928:3623878655]	auto[0]	53	1			T129	1		T6	1		T50	2
auto[3489660928:3623878655]	auto[1]	52	1			T6	1		T60	2		T48	1
auto[3623878656:3758096383]	auto[0]	53	1			T7	1		T49	1		T124	1
auto[3623878656:3758096383]	auto[1]	46	1			T103	1		T6	1		T112	1
auto[3758096384:3892314111]	auto[0]	60	1			T6	2		T7	1		T198	1
auto[3758096384:3892314111]	auto[1]	57	1			T18	1		T6	1		T60	3
auto[3892314112:4026531839]	auto[0]	66	1			T6	3		T50	1		T60	1
auto[3892314112:4026531839]	auto[1]	48	1			T6	1		T50	1		T60	1
auto[4026531840:4160749567]	auto[0]	57	1			T41	1		T129	1		T60	1
auto[4026531840:4160749567]	auto[1]	59	1			T50	1		T134	1		T150	1
auto[4160749568:4294967295]	auto[0]	51	1			T6	1		T37	1		T54	1
auto[4160749568:4294967295]	auto[1]	52	1			T4	1		T50	1		T7	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1622

1

T2

2

T4

1

T5

3

auto[1]

1834

1

T4

4

T5

4

T18

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T119	1		T50	1		T60	1
auto[134217728:268435455]	124	1			T18	1		T129	1		T6	2
auto[268435456:402653183]	99	1			T50	1		T86	1		T7	3
auto[402653184:536870911]	119	1			T2	1		T4	1		T19	1
auto[536870912:671088639]	116	1			T60	1		T7	3		T64	1
auto[671088640:805306367]	108	1			T4	1		T6	2		T50	1
auto[805306368:939524095]	93	1			T19	1		T6	1		T134	1
auto[939524096:1073741823]	105	1			T18	1		T129	1		T6	3
auto[1073741824:1207959551]	108	1			T4	1		T6	1		T50	4
auto[1207959552:1342177279]	107	1			T5	1		T19	1		T41	1
auto[1342177280:1476395007]	101	1			T41	1		T6	1		T36	1
auto[1476395008:1610612735]	131	1			T5	1		T6	1		T50	3
auto[1610612736:1744830463]	116	1			T41	1		T104	1		T6	1
auto[1744830464:1879048191]	103	1			T30	2		T50	1		T60	2
auto[1879048192:2013265919]	91	1			T30	1		T129	2		T6	2
auto[2013265920:2147483647]	108	1			T2	1		T19	1		T41	1
auto[2147483648:2281701375]	104	1			T4	1		T5	1		T18	1
auto[2281701376:2415919103]	97	1			T129	2		T6	2		T60	1
auto[2415919104:2550136831]	112	1			T103	1		T50	2		T7	2
auto[2550136832:2684354559]	108	1			T5	1		T30	1		T104	1
auto[2684354560:2818572287]	120	1			T6	1		T60	1		T7	4
auto[2818572288:2952790015]	116	1			T41	1		T103	1		T6	2
auto[2952790016:3087007743]	106	1			T18	1		T41	1		T6	1
auto[3087007744:3221225471]	112	1			T5	1		T35	1		T7	1
auto[3221225472:3355443199]	108	1			T6	2		T7	4		T281	1
auto[3355443200:3489660927]	117	1			T4	1		T41	1		T6	5
auto[3489660928:3623878655]	112	1			T103	1		T119	1		T6	5
auto[3623878656:3758096383]	118	1			T5	1		T41	1		T104	1
auto[3758096384:3892314111]	106	1			T5	1		T104	2		T50	1
auto[3892314112:4026531839]	94	1			T86	1		T60	2		T221	1
auto[4026531840:4160749567]	109	1			T30	1		T6	2		T50	2
auto[4160749568:4294967295]	99	1			T18	1		T35	1		T129	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	40	1			T119	1		T50	1		T124	1
auto[0:134217727]	auto[1]	49	1			T60	1		T122	1		T188	1
auto[134217728:268435455]	auto[0]	70	1			T129	1		T6	1		T48	1
auto[134217728:268435455]	auto[1]	54	1			T18	1		T6	1		T86	1
auto[268435456:402653183]	auto[0]	37	1			T122	1		T58	1		T211	1
auto[268435456:402653183]	auto[1]	62	1			T50	1		T86	1		T7	3
auto[402653184:536870911]	auto[0]	42	1			T2	1		T41	1		T49	1
auto[402653184:536870911]	auto[1]	77	1			T4	1		T19	1		T6	3
auto[536870912:671088639]	auto[0]	57	1			T7	2		T27	1		T49	1
auto[536870912:671088639]	auto[1]	59	1			T60	1		T7	1		T64	1
auto[671088640:805306367]	auto[0]	51	1			T6	2		T60	2		T37	1
auto[671088640:805306367]	auto[1]	57	1			T4	1		T50	1		T7	1
auto[805306368:939524095]	auto[0]	43	1			T6	1		T134	1		T132	1
auto[805306368:939524095]	auto[1]	50	1			T19	1		T239	1		T58	1
auto[939524096:1073741823]	auto[0]	46	1			T129	1		T6	3		T32	1
auto[939524096:1073741823]	auto[1]	59	1			T18	1		T50	4		T60	1
auto[1073741824:1207959551]	auto[0]	50	1			T6	1		T50	3		T60	2
auto[1073741824:1207959551]	auto[1]	58	1			T4	1		T50	1		T60	2
auto[1207959552:1342177279]	auto[0]	47	1			T6	2		T7	1		T49	1
auto[1207959552:1342177279]	auto[1]	60	1			T5	1		T19	1		T41	1
auto[1342177280:1476395007]	auto[0]	39	1			T41	1		T6	1		T7	1
auto[1342177280:1476395007]	auto[1]	62	1			T36	1		T60	1		T7	1
auto[1476395008:1610612735]	auto[0]	57	1			T5	1		T6	1		T50	1
auto[1476395008:1610612735]	auto[1]	74	1			T50	2		T60	2		T7	1
auto[1610612736:1744830463]	auto[0]	56	1			T41	1		T104	1		T6	1
auto[1610612736:1744830463]	auto[1]	60	1			T48	1		T62	1		T362	1
auto[1744830464:1879048191]	auto[0]	49	1			T30	1		T49	1		T399	2
auto[1744830464:1879048191]	auto[1]	54	1			T30	1		T50	1		T60	2
auto[1879048192:2013265919]	auto[0]	37	1			T30	1		T129	1		T6	2
auto[1879048192:2013265919]	auto[1]	54	1			T129	1		T50	2		T60	1
auto[2013265920:2147483647]	auto[0]	50	1			T2	1		T41	1		T6	2
auto[2013265920:2147483647]	auto[1]	58	1			T19	1		T50	2		T221	1
auto[2147483648:2281701375]	auto[0]	46	1			T25	1		T252	1		T109	1
auto[2147483648:2281701375]	auto[1]	58	1			T4	1		T5	1		T18	1
auto[2281701376:2415919103]	auto[0]	52	1			T129	1		T6	2		T60	1
auto[2281701376:2415919103]	auto[1]	45	1			T129	1		T198	2		T28	1
auto[2415919104:2550136831]	auto[0]	55	1			T50	1		T232	1		T89	1
auto[2415919104:2550136831]	auto[1]	57	1			T103	1		T50	1		T7	2
auto[2550136832:2684354559]	auto[0]	43	1			T5	1		T6	2		T7	1
auto[2550136832:2684354559]	auto[1]	65	1			T30	1		T104	1		T6	1
auto[2684354560:2818572287]	auto[0]	62	1			T6	1		T7	3		T25	1
auto[2684354560:2818572287]	auto[1]	58	1			T60	1		T7	1		T58	1
auto[2818572288:2952790015]	auto[0]	58	1			T41	1		T6	1		T7	1
auto[2818572288:2952790015]	auto[1]	58	1			T103	1		T6	1		T50	2
auto[2952790016:3087007743]	auto[0]	49	1			T6	1		T60	1		T25	1
auto[2952790016:3087007743]	auto[1]	57	1			T18	1		T41	1		T50	1
auto[3087007744:3221225471]	auto[0]	54	1			T5	1		T35	1		T7	1
auto[3087007744:3221225471]	auto[1]	58	1			T132	1		T135	1		T55	1
auto[3221225472:3355443199]	auto[0]	54	1			T6	2		T7	4		T122	1
auto[3221225472:3355443199]	auto[1]	54	1			T281	1		T132	1		T79	1
auto[3355443200:3489660927]	auto[0]	57	1			T4	1		T41	1		T6	1
auto[3355443200:3489660927]	auto[1]	60	1			T6	4		T60	1		T7	2
auto[3489660928:3623878655]	auto[0]	52	1			T119	1		T6	2		T60	1
auto[3489660928:3623878655]	auto[1]	60	1			T103	1		T6	3		T7	1
auto[3623878656:3758096383]	auto[0]	55	1			T41	1		T104	1		T6	1
auto[3623878656:3758096383]	auto[1]	63	1			T5	1		T119	1		T50	1
auto[3758096384:3892314111]	auto[0]	55	1			T104	2		T60	2		T198	1
auto[3758096384:3892314111]	auto[1]	51	1			T5	1		T50	1		T36	1
auto[3892314112:4026531839]	auto[0]	49	1			T60	1		T190	1		T33	1
auto[3892314112:4026531839]	auto[1]	45	1			T86	1		T60	1		T221	1
auto[4026531840:4160749567]	auto[0]	61	1			T30	1		T6	2		T50	2
auto[4026531840:4160749567]	auto[1]	48	1			T112	1		T49	1		T399	1
auto[4160749568:4294967295]	auto[0]	49	1			T129	1		T6	1		T50	1
auto[4160749568:4294967295]	auto[1]	50	1			T18	1		T35	1		T6	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1620

1

T2

2

T5

4

T30

2

auto[1]

1833

1

T4

5

T5

3

T18

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	103	1			T18	1		T41	1		T6	1
auto[134217728:268435455]	114	1			T19	1		T41	1		T129	1
auto[268435456:402653183]	112	1			T2	1		T103	2		T50	2
auto[402653184:536870911]	113	1			T104	1		T6	2		T50	3
auto[536870912:671088639]	131	1			T129	1		T6	3		T60	1
auto[671088640:805306367]	100	1			T5	1		T119	1		T50	1
auto[805306368:939524095]	98	1			T104	1		T6	3		T50	1
auto[939524096:1073741823]	127	1			T4	2		T104	1		T6	5
auto[1073741824:1207959551]	108	1			T18	1		T6	2		T50	1
auto[1207959552:1342177279]	116	1			T30	1		T41	1		T6	1
auto[1342177280:1476395007]	121	1			T119	1		T86	1		T60	1
auto[1476395008:1610612735]	99	1			T19	1		T50	1		T60	1
auto[1610612736:1744830463]	109	1			T30	1		T41	2		T119	1
auto[1744830464:1879048191]	116	1			T4	1		T19	1		T129	1
auto[1879048192:2013265919]	90	1			T18	1		T60	1		T7	1
auto[2013265920:2147483647]	97	1			T5	1		T41	1		T6	1
auto[2147483648:2281701375]	109	1			T18	1		T6	1		T50	3
auto[2281701376:2415919103]	124	1			T5	1		T6	3		T50	1
auto[2415919104:2550136831]	107	1			T4	1		T18	1		T6	2
auto[2550136832:2684354559]	91	1			T6	2		T50	1		T7	1
auto[2684354560:2818572287]	107	1			T19	1		T6	2		T50	2
auto[2818572288:2952790015]	111	1			T35	1		T6	3		T50	1
auto[2952790016:3087007743]	100	1			T104	1		T129	1		T50	1
auto[3087007744:3221225471]	100	1			T6	3		T50	1		T7	2
auto[3221225472:3355443199]	97	1			T7	3		T48	1		T25	1
auto[3355443200:3489660927]	106	1			T30	2		T104	1		T6	1
auto[3489660928:3623878655]	114	1			T41	1		T129	1		T6	3
auto[3623878656:3758096383]	114	1			T41	1		T6	2		T50	1
auto[3758096384:3892314111]	111	1			T2	1		T41	1		T6	4
auto[3892314112:4026531839]	97	1			T5	2		T30	1		T6	2
auto[4026531840:4160749567]	97	1			T129	1		T50	1		T86	1
auto[4160749568:4294967295]	114	1			T4	1		T5	2		T129	1