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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1600 1 T2 1 T4 1 T5 4
auto[1] 1852 1 T2 1 T4 4 T5 3


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 105 1 T5 1 T50 1 T60 3
auto[134217728:268435455] 114 1 T4 1 T30 1 T50 1
auto[268435456:402653183] 126 1 T30 1 T6 4 T50 1
auto[402653184:536870911] 105 1 T30 1 T6 3 T50 1
auto[536870912:671088639] 105 1 T6 2 T50 2 T60 3
auto[671088640:805306367] 99 1 T50 1 T36 1 T7 3
auto[805306368:939524095] 105 1 T4 1 T129 1 T6 2
auto[939524096:1073741823] 107 1 T5 1 T19 1 T30 1
auto[1073741824:1207959551] 95 1 T18 1 T6 1 T7 3
auto[1207959552:1342177279] 118 1 T2 1 T4 1 T129 1
auto[1342177280:1476395007] 102 1 T2 1 T129 1 T6 2
auto[1476395008:1610612735] 116 1 T4 1 T41 2 T6 1
auto[1610612736:1744830463] 96 1 T129 2 T6 1 T50 1
auto[1744830464:1879048191] 105 1 T5 1 T104 2 T6 3
auto[1879048192:2013265919] 110 1 T5 1 T30 1 T6 1
auto[2013265920:2147483647] 101 1 T6 1 T50 2 T60 4
auto[2147483648:2281701375] 101 1 T41 1 T6 1 T60 1
auto[2281701376:2415919103] 121 1 T18 1 T41 1 T104 1
auto[2415919104:2550136831] 117 1 T19 1 T50 2 T36 1
auto[2550136832:2684354559] 117 1 T18 1 T103 1 T6 1
auto[2684354560:2818572287] 102 1 T4 1 T35 1 T6 1
auto[2818572288:2952790015] 107 1 T6 2 T50 1 T7 2
auto[2952790016:3087007743] 112 1 T6 4 T50 3 T60 3
auto[3087007744:3221225471] 108 1 T6 2 T7 1 T25 1
auto[3221225472:3355443199] 104 1 T18 1 T41 1 T6 1
auto[3355443200:3489660927] 105 1 T129 1 T6 1 T50 1
auto[3489660928:3623878655] 104 1 T19 1 T41 1 T50 1
auto[3623878656:3758096383] 110 1 T5 1 T18 1 T103 1
auto[3758096384:3892314111] 117 1 T5 2 T6 1 T60 1
auto[3892314112:4026531839] 101 1 T103 1 T119 1 T6 1
auto[4026531840:4160749567] 105 1 T19 1 T41 1 T104 1
auto[4160749568:4294967295] 112 1 T104 1 T6 3 T50 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 50 1 T5 1 T60 2 T281 1
auto[0:134217727] auto[1] 55 1 T50 1 T60 1 T7 1
auto[134217728:268435455] auto[0] 56 1 T4 1 T30 1 T50 1
auto[134217728:268435455] auto[1] 58 1 T60 1 T7 1 T198 1
auto[268435456:402653183] auto[0] 63 1 T6 4 T60 1 T190 2
auto[268435456:402653183] auto[1] 63 1 T30 1 T50 1 T60 1
auto[402653184:536870911] auto[0] 53 1 T30 1 T6 2 T37 1
auto[402653184:536870911] auto[1] 52 1 T6 1 T50 1 T7 1
auto[536870912:671088639] auto[0] 55 1 T6 1 T60 1 T43 1
auto[536870912:671088639] auto[1] 50 1 T6 1 T50 2 T60 2
auto[671088640:805306367] auto[0] 54 1 T50 1 T7 3 T198 1
auto[671088640:805306367] auto[1] 45 1 T36 1 T64 1 T113 2
auto[805306368:939524095] auto[0] 33 1 T6 1 T50 1 T60 2
auto[805306368:939524095] auto[1] 72 1 T4 1 T129 1 T6 1
auto[939524096:1073741823] auto[0] 44 1 T5 1 T30 1 T41 1
auto[939524096:1073741823] auto[1] 63 1 T19 1 T41 1 T129 1
auto[1073741824:1207959551] auto[0] 43 1 T7 2 T58 2 T211 1
auto[1073741824:1207959551] auto[1] 52 1 T18 1 T6 1 T7 1
auto[1207959552:1342177279] auto[0] 55 1 T129 1 T6 2 T7 1
auto[1207959552:1342177279] auto[1] 63 1 T2 1 T4 1 T50 1
auto[1342177280:1476395007] auto[0] 49 1 T2 1 T129 1 T6 2
auto[1342177280:1476395007] auto[1] 53 1 T86 1 T7 3 T134 1
auto[1476395008:1610612735] auto[0] 61 1 T41 2 T6 1 T7 2
auto[1476395008:1610612735] auto[1] 55 1 T4 1 T198 1 T93 1
auto[1610612736:1744830463] auto[0] 37 1 T129 1 T50 1 T7 2
auto[1610612736:1744830463] auto[1] 59 1 T129 1 T6 1 T112 1
auto[1744830464:1879048191] auto[0] 51 1 T104 2 T6 1 T247 1
auto[1744830464:1879048191] auto[1] 54 1 T5 1 T6 2 T7 1
auto[1879048192:2013265919] auto[0] 47 1 T6 1 T7 1 T27 1
auto[1879048192:2013265919] auto[1] 63 1 T5 1 T30 1 T50 2
auto[2013265920:2147483647] auto[0] 47 1 T6 1 T60 2 T7 1
auto[2013265920:2147483647] auto[1] 54 1 T50 2 T60 2 T57 1
auto[2147483648:2281701375] auto[0] 51 1 T41 1 T6 1 T210 1
auto[2147483648:2281701375] auto[1] 50 1 T60 1 T29 1 T58 3
auto[2281701376:2415919103] auto[0] 50 1 T41 1 T104 1 T6 1
auto[2281701376:2415919103] auto[1] 71 1 T18 1 T6 1 T60 1
auto[2415919104:2550136831] auto[0] 45 1 T27 1 T150 1 T125 1
auto[2415919104:2550136831] auto[1] 72 1 T19 1 T50 2 T36 1
auto[2550136832:2684354559] auto[0] 57 1 T50 1 T7 2 T49 1
auto[2550136832:2684354559] auto[1] 60 1 T18 1 T103 1 T6 1
auto[2684354560:2818572287] auto[0] 42 1 T7 1 T399 1 T245 1
auto[2684354560:2818572287] auto[1] 60 1 T4 1 T35 1 T6 1
auto[2818572288:2952790015] auto[0] 43 1 T27 1 T29 1 T226 2
auto[2818572288:2952790015] auto[1] 64 1 T6 2 T50 1 T7 2
auto[2952790016:3087007743] auto[0] 52 1 T6 3 T50 2 T60 1
auto[2952790016:3087007743] auto[1] 60 1 T6 1 T50 1 T60 2
auto[3087007744:3221225471] auto[0] 51 1 T6 2 T7 1 T67 1
auto[3087007744:3221225471] auto[1] 57 1 T25 1 T26 1 T198 1
auto[3221225472:3355443199] auto[0] 51 1 T6 1 T50 1 T134 1
auto[3221225472:3355443199] auto[1] 53 1 T18 1 T41 1 T60 1
auto[3355443200:3489660927] auto[0] 48 1 T60 1 T43 1 T62 1
auto[3355443200:3489660927] auto[1] 57 1 T129 1 T6 1 T50 1
auto[3489660928:3623878655] auto[0] 52 1 T41 1 T50 1 T61 2
auto[3489660928:3623878655] auto[1] 52 1 T19 1 T132 1 T122 1
auto[3623878656:3758096383] auto[0] 49 1 T119 1 T7 1 T25 1
auto[3623878656:3758096383] auto[1] 61 1 T5 1 T18 1 T103 1
auto[3758096384:3892314111] auto[0] 58 1 T5 2 T6 1 T7 2
auto[3758096384:3892314111] auto[1] 59 1 T60 1 T48 2 T28 1
auto[3892314112:4026531839] auto[0] 53 1 T6 1 T7 1 T67 1
auto[3892314112:4026531839] auto[1] 48 1 T103 1 T119 1 T60 2
auto[4026531840:4160749567] auto[0] 52 1 T41 1 T6 4 T50 1
auto[4026531840:4160749567] auto[1] 53 1 T19 1 T104 1 T50 1
auto[4160749568:4294967295] auto[0] 48 1 T104 1 T60 1 T247 1
auto[4160749568:4294967295] auto[1] 64 1 T6 3 T50 1 T86 1

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