Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.83 99.10 97.79 98.64 100.00 99.20 98.41 91.63


Total test records in report: 1076
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T330 /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3722989976 Apr 27 04:09:33 PM PDT 24 Apr 27 04:09:38 PM PDT 24 55694430 ps
T1012 /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3101853 Apr 27 04:09:14 PM PDT 24 Apr 27 04:09:19 PM PDT 24 240585409 ps
T276 /workspace/coverage/default/27.keymgr_kmac_rsp_err.2948947029 Apr 27 04:11:30 PM PDT 24 Apr 27 04:11:33 PM PDT 24 177336287 ps
T1013 /workspace/coverage/default/44.keymgr_sideload_otbn.2310376211 Apr 27 04:12:47 PM PDT 24 Apr 27 04:13:08 PM PDT 24 1555836227 ps
T1014 /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3399296818 Apr 27 04:09:56 PM PDT 24 Apr 27 04:10:00 PM PDT 24 202050941 ps
T1015 /workspace/coverage/default/32.keymgr_sideload_protect.2105949004 Apr 27 04:11:53 PM PDT 24 Apr 27 04:11:56 PM PDT 24 41895231 ps
T97 /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3156015770 Apr 27 04:12:49 PM PDT 24 Apr 27 04:12:55 PM PDT 24 189144604 ps
T1016 /workspace/coverage/default/48.keymgr_random.776352389 Apr 27 04:13:03 PM PDT 24 Apr 27 04:13:12 PM PDT 24 1057794849 ps
T1017 /workspace/coverage/default/6.keymgr_stress_all.1401461279 Apr 27 04:09:34 PM PDT 24 Apr 27 04:10:09 PM PDT 24 1784948564 ps
T1018 /workspace/coverage/default/1.keymgr_lc_disable.2595659844 Apr 27 04:08:46 PM PDT 24 Apr 27 04:08:50 PM PDT 24 153871000 ps
T1019 /workspace/coverage/default/17.keymgr_sideload_protect.1501578583 Apr 27 04:10:35 PM PDT 24 Apr 27 04:10:38 PM PDT 24 82675792 ps
T1020 /workspace/coverage/default/45.keymgr_sw_invalid_input.236060078 Apr 27 04:12:53 PM PDT 24 Apr 27 04:13:02 PM PDT 24 853880481 ps
T1021 /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2274617278 Apr 27 04:11:04 PM PDT 24 Apr 27 04:11:11 PM PDT 24 452342685 ps
T1022 /workspace/coverage/default/28.keymgr_smoke.1106936382 Apr 27 04:11:30 PM PDT 24 Apr 27 04:11:33 PM PDT 24 60135061 ps
T1023 /workspace/coverage/default/19.keymgr_kmac_rsp_err.1499844926 Apr 27 04:10:49 PM PDT 24 Apr 27 04:12:16 PM PDT 24 12616829925 ps
T1024 /workspace/coverage/default/34.keymgr_stress_all.2453851746 Apr 27 04:12:06 PM PDT 24 Apr 27 04:23:51 PM PDT 24 24041878356 ps
T1025 /workspace/coverage/default/36.keymgr_stress_all.3504506288 Apr 27 04:12:10 PM PDT 24 Apr 27 04:12:52 PM PDT 24 1507225659 ps
T1026 /workspace/coverage/default/40.keymgr_sideload_otbn.4138434570 Apr 27 04:12:26 PM PDT 24 Apr 27 04:12:29 PM PDT 24 55183149 ps
T1027 /workspace/coverage/default/32.keymgr_sideload_otbn.815486579 Apr 27 04:11:46 PM PDT 24 Apr 27 04:12:22 PM PDT 24 5131123239 ps
T1028 /workspace/coverage/default/49.keymgr_smoke.4144169659 Apr 27 04:13:04 PM PDT 24 Apr 27 04:13:08 PM PDT 24 136101132 ps
T407 /workspace/coverage/default/22.keymgr_cfg_regwen.1643847248 Apr 27 04:11:05 PM PDT 24 Apr 27 04:11:13 PM PDT 24 1047191875 ps
T1029 /workspace/coverage/default/12.keymgr_random.3563826489 Apr 27 04:10:10 PM PDT 24 Apr 27 04:10:16 PM PDT 24 196440470 ps
T1030 /workspace/coverage/default/30.keymgr_direct_to_disabled.4292639715 Apr 27 04:11:42 PM PDT 24 Apr 27 04:11:47 PM PDT 24 116142259 ps
T1031 /workspace/coverage/default/27.keymgr_sideload_aes.2819645674 Apr 27 04:11:24 PM PDT 24 Apr 27 04:11:28 PM PDT 24 262540498 ps
T1032 /workspace/coverage/default/33.keymgr_sw_invalid_input.2069505566 Apr 27 04:11:55 PM PDT 24 Apr 27 04:12:03 PM PDT 24 277696507 ps
T1033 /workspace/coverage/default/33.keymgr_random.2682133979 Apr 27 04:11:54 PM PDT 24 Apr 27 04:12:00 PM PDT 24 417973548 ps
T1034 /workspace/coverage/default/6.keymgr_kmac_rsp_err.4051147490 Apr 27 04:09:40 PM PDT 24 Apr 27 04:09:46 PM PDT 24 298234777 ps
T1035 /workspace/coverage/default/47.keymgr_cfg_regwen.312915431 Apr 27 04:13:03 PM PDT 24 Apr 27 04:13:08 PM PDT 24 56390219 ps
T1036 /workspace/coverage/default/46.keymgr_stress_all.767529639 Apr 27 04:12:56 PM PDT 24 Apr 27 04:13:39 PM PDT 24 3266417289 ps
T1037 /workspace/coverage/default/41.keymgr_direct_to_disabled.3626487834 Apr 27 04:12:30 PM PDT 24 Apr 27 04:12:50 PM PDT 24 9253944937 ps
T318 /workspace/coverage/default/30.keymgr_cfg_regwen.1624288023 Apr 27 04:11:49 PM PDT 24 Apr 27 04:11:59 PM PDT 24 155302888 ps
T1038 /workspace/coverage/default/3.keymgr_sideload_kmac.1177097168 Apr 27 04:09:04 PM PDT 24 Apr 27 04:09:44 PM PDT 24 2381805884 ps
T1039 /workspace/coverage/default/42.keymgr_kmac_rsp_err.1653444597 Apr 27 04:12:35 PM PDT 24 Apr 27 04:12:43 PM PDT 24 271340399 ps
T1040 /workspace/coverage/default/16.keymgr_lc_disable.2508247685 Apr 27 04:10:30 PM PDT 24 Apr 27 04:10:35 PM PDT 24 388973368 ps
T1041 /workspace/coverage/default/16.keymgr_stress_all.4029480592 Apr 27 04:10:40 PM PDT 24 Apr 27 04:11:46 PM PDT 24 9013675525 ps
T1042 /workspace/coverage/default/0.keymgr_lc_disable.2674680832 Apr 27 04:08:36 PM PDT 24 Apr 27 04:08:41 PM PDT 24 457673850 ps
T1043 /workspace/coverage/default/41.keymgr_sideload_otbn.512520102 Apr 27 04:12:30 PM PDT 24 Apr 27 04:12:32 PM PDT 24 93079460 ps
T1044 /workspace/coverage/default/9.keymgr_sw_invalid_input.2499713853 Apr 27 04:09:51 PM PDT 24 Apr 27 04:09:57 PM PDT 24 119905339 ps
T378 /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1770598945 Apr 27 04:11:19 PM PDT 24 Apr 27 04:11:24 PM PDT 24 326054675 ps
T1045 /workspace/coverage/default/32.keymgr_smoke.4037027543 Apr 27 04:11:49 PM PDT 24 Apr 27 04:11:54 PM PDT 24 625060426 ps
T1046 /workspace/coverage/default/21.keymgr_kmac_rsp_err.164186360 Apr 27 04:11:01 PM PDT 24 Apr 27 04:11:14 PM PDT 24 587696595 ps
T1047 /workspace/coverage/default/18.keymgr_sync_async_fault_cross.980483934 Apr 27 04:10:44 PM PDT 24 Apr 27 04:10:47 PM PDT 24 193744595 ps
T1048 /workspace/coverage/default/38.keymgr_alert_test.1573043110 Apr 27 04:12:21 PM PDT 24 Apr 27 04:12:22 PM PDT 24 12664750 ps
T1049 /workspace/coverage/default/15.keymgr_direct_to_disabled.2651158175 Apr 27 04:10:24 PM PDT 24 Apr 27 04:10:27 PM PDT 24 36092378 ps
T1050 /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3785470411 Apr 27 04:11:41 PM PDT 24 Apr 27 04:11:44 PM PDT 24 157107947 ps
T1051 /workspace/coverage/default/22.keymgr_sw_invalid_input.3777366771 Apr 27 04:11:05 PM PDT 24 Apr 27 04:11:09 PM PDT 24 50689380 ps
T1052 /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1369324109 Apr 27 04:13:08 PM PDT 24 Apr 27 04:13:12 PM PDT 24 433690114 ps
T1053 /workspace/coverage/default/23.keymgr_sideload.1572418745 Apr 27 04:11:04 PM PDT 24 Apr 27 04:11:41 PM PDT 24 1984692806 ps
T1054 /workspace/coverage/default/3.keymgr_sideload_otbn.1147634698 Apr 27 04:09:06 PM PDT 24 Apr 27 04:09:08 PM PDT 24 24921316 ps
T1055 /workspace/coverage/default/42.keymgr_sideload_otbn.78098595 Apr 27 04:12:36 PM PDT 24 Apr 27 04:12:41 PM PDT 24 2876184675 ps
T1056 /workspace/coverage/default/32.keymgr_cfg_regwen.3531527289 Apr 27 04:11:53 PM PDT 24 Apr 27 04:11:57 PM PDT 24 103146727 ps
T105 /workspace/coverage/default/2.keymgr_sec_cm.2490346176 Apr 27 04:09:05 PM PDT 24 Apr 27 04:09:23 PM PDT 24 2414548090 ps
T1057 /workspace/coverage/default/22.keymgr_sideload_kmac.612784367 Apr 27 04:11:01 PM PDT 24 Apr 27 04:11:04 PM PDT 24 40074082 ps
T246 /workspace/coverage/default/38.keymgr_cfg_regwen.2528205513 Apr 27 04:12:20 PM PDT 24 Apr 27 04:12:24 PM PDT 24 86354675 ps
T1058 /workspace/coverage/default/2.keymgr_direct_to_disabled.163304942 Apr 27 04:08:59 PM PDT 24 Apr 27 04:09:03 PM PDT 24 383395456 ps
T367 /workspace/coverage/default/33.keymgr_kmac_rsp_err.3585752569 Apr 27 04:11:54 PM PDT 24 Apr 27 04:12:05 PM PDT 24 1055947344 ps
T1059 /workspace/coverage/default/24.keymgr_sideload_otbn.1352702179 Apr 27 04:11:10 PM PDT 24 Apr 27 04:11:17 PM PDT 24 2435559477 ps
T1060 /workspace/coverage/default/44.keymgr_sideload.3013666647 Apr 27 04:12:46 PM PDT 24 Apr 27 04:12:53 PM PDT 24 1060436115 ps
T1061 /workspace/coverage/default/14.keymgr_stress_all.3214594797 Apr 27 04:10:24 PM PDT 24 Apr 27 04:12:54 PM PDT 24 11128131663 ps
T1062 /workspace/coverage/default/5.keymgr_sideload_protect.2635783010 Apr 27 04:09:28 PM PDT 24 Apr 27 04:09:32 PM PDT 24 137276940 ps
T377 /workspace/coverage/default/13.keymgr_kmac_rsp_err.2522594158 Apr 27 04:10:14 PM PDT 24 Apr 27 04:10:19 PM PDT 24 282153423 ps
T1063 /workspace/coverage/default/20.keymgr_stress_all.1308718348 Apr 27 04:10:54 PM PDT 24 Apr 27 04:11:29 PM PDT 24 926493920 ps
T1064 /workspace/coverage/default/6.keymgr_sideload_aes.2698964073 Apr 27 04:09:28 PM PDT 24 Apr 27 04:09:33 PM PDT 24 364041821 ps
T1065 /workspace/coverage/default/25.keymgr_stress_all.2903257911 Apr 27 04:11:24 PM PDT 24 Apr 27 04:12:26 PM PDT 24 2390787745 ps
T1066 /workspace/coverage/default/18.keymgr_random.4290328709 Apr 27 04:10:44 PM PDT 24 Apr 27 04:10:50 PM PDT 24 273623368 ps
T1067 /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.4234109100 Apr 27 04:12:08 PM PDT 24 Apr 27 04:12:12 PM PDT 24 199825706 ps
T1068 /workspace/coverage/default/9.keymgr_sideload.3885232707 Apr 27 04:09:55 PM PDT 24 Apr 27 04:09:58 PM PDT 24 104702553 ps
T1069 /workspace/coverage/default/15.keymgr_sideload_otbn.1097772620 Apr 27 04:10:25 PM PDT 24 Apr 27 04:10:27 PM PDT 24 108781818 ps
T1070 /workspace/coverage/default/35.keymgr_sideload_protect.3957971478 Apr 27 04:12:10 PM PDT 24 Apr 27 04:12:15 PM PDT 24 88075736 ps
T1071 /workspace/coverage/default/34.keymgr_sideload_otbn.2717029920 Apr 27 04:12:01 PM PDT 24 Apr 27 04:12:14 PM PDT 24 1675405111 ps
T209 /workspace/coverage/default/31.keymgr_lc_disable.94732768 Apr 27 04:11:48 PM PDT 24 Apr 27 04:11:51 PM PDT 24 167876971 ps
T1072 /workspace/coverage/default/43.keymgr_sideload.3772150165 Apr 27 04:12:43 PM PDT 24 Apr 27 04:13:02 PM PDT 24 2750993464 ps
T1073 /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2092746916 Apr 27 04:10:55 PM PDT 24 Apr 27 04:10:59 PM PDT 24 315730804 ps
T1074 /workspace/coverage/default/29.keymgr_sideload_aes.2206744638 Apr 27 04:11:36 PM PDT 24 Apr 27 04:12:32 PM PDT 24 1781228796 ps
T1075 /workspace/coverage/default/42.keymgr_smoke.2933889177 Apr 27 04:12:35 PM PDT 24 Apr 27 04:12:40 PM PDT 24 129911725 ps
T1076 /workspace/coverage/default/43.keymgr_custom_cm.2668739108 Apr 27 04:12:47 PM PDT 24 Apr 27 04:12:49 PM PDT 24 294520091 ps

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1412978980
Short name T4
Test name
Test status
Simulation time 261378665 ps
CPU time 7.9 seconds
Started Apr 27 04:13:04 PM PDT 24
Finished Apr 27 04:13:13 PM PDT 24
Peak memory 218420 kb
Host smart-d2628c3c-c27c-4883-a5ea-7ace6366c343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412978980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1412978980
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3281398528
Short name T6
Test name
Test status
Simulation time 7251911725 ps
CPU time 137.04 seconds
Started Apr 27 04:12:20 PM PDT 24
Finished Apr 27 04:14:38 PM PDT 24
Peak memory 222540 kb
Host smart-ba5e7823-ec2b-402d-a3cf-081a1f723443
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281398528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3281398528
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1100350274
Short name T7
Test name
Test status
Simulation time 34330543788 ps
CPU time 1004.16 seconds
Started Apr 27 04:09:04 PM PDT 24
Finished Apr 27 04:25:49 PM PDT 24
Peak memory 230412 kb
Host smart-39ba84ad-206e-474a-8d96-3fd9b34be00f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100350274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1100350274
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.382797035
Short name T12
Test name
Test status
Simulation time 1303525089 ps
CPU time 32.41 seconds
Started Apr 27 04:08:57 PM PDT 24
Finished Apr 27 04:09:29 PM PDT 24
Peak memory 235096 kb
Host smart-16216791-c893-4d27-b9f4-6771637e4ba8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382797035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.382797035
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3420618772
Short name T113
Test name
Test status
Simulation time 362725304 ps
CPU time 5.82 seconds
Started Apr 27 04:12:10 PM PDT 24
Finished Apr 27 04:12:17 PM PDT 24
Peak memory 222604 kb
Host smart-ae339f18-dcf7-4458-ba08-15e4838c12dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420618772 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3420618772
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2750226276
Short name T212
Test name
Test status
Simulation time 999720546 ps
CPU time 23.97 seconds
Started Apr 27 04:09:18 PM PDT 24
Finished Apr 27 04:09:42 PM PDT 24
Peak memory 221092 kb
Host smart-086ae94e-853f-421c-b9b7-261324539e72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750226276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2750226276
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3070067165
Short name T19
Test name
Test status
Simulation time 100561263 ps
CPU time 5.36 seconds
Started Apr 27 04:08:34 PM PDT 24
Finished Apr 27 04:08:40 PM PDT 24
Peak memory 214304 kb
Host smart-36756f84-b0d1-458f-9d27-deb90218f087
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3070067165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3070067165
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.4178752211
Short name T58
Test name
Test status
Simulation time 800399214 ps
CPU time 29.53 seconds
Started Apr 27 04:13:05 PM PDT 24
Finished Apr 27 04:13:35 PM PDT 24
Peak memory 222488 kb
Host smart-942bdac8-6898-4c8f-8c48-b3dfc49621f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178752211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.4178752211
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1915538222
Short name T46
Test name
Test status
Simulation time 1527573143 ps
CPU time 6.27 seconds
Started Apr 27 04:11:18 PM PDT 24
Finished Apr 27 04:11:25 PM PDT 24
Peak memory 210668 kb
Host smart-d3c40ada-6af7-4e29-8344-e405a4851c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915538222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1915538222
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2754037034
Short name T33
Test name
Test status
Simulation time 119863771 ps
CPU time 5.37 seconds
Started Apr 27 04:11:42 PM PDT 24
Finished Apr 27 04:11:48 PM PDT 24
Peak memory 209864 kb
Host smart-a7a99d4f-0995-4634-bf6d-05f4318313ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754037034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2754037034
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.266028209
Short name T119
Test name
Test status
Simulation time 841267239 ps
CPU time 20.85 seconds
Started Apr 27 04:11:38 PM PDT 24
Finished Apr 27 04:11:59 PM PDT 24
Peak memory 222376 kb
Host smart-0ac4f568-fc07-4d95-b5f7-5ce772db4730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=266028209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.266028209
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1014458648
Short name T51
Test name
Test status
Simulation time 1454421790 ps
CPU time 34.28 seconds
Started Apr 27 04:10:28 PM PDT 24
Finished Apr 27 04:11:02 PM PDT 24
Peak memory 219832 kb
Host smart-c9df1639-cbd9-4a0b-9dba-d133a0cb7f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014458648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1014458648
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.725139348
Short name T149
Test name
Test status
Simulation time 263032989 ps
CPU time 6.88 seconds
Started Apr 27 01:49:00 PM PDT 24
Finished Apr 27 01:49:07 PM PDT 24
Peak memory 220016 kb
Host smart-b760600b-a356-40cf-92e4-38bbfe26d8d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725139348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.725139348
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.417842929
Short name T9
Test name
Test status
Simulation time 121971012 ps
CPU time 3.57 seconds
Started Apr 27 04:09:49 PM PDT 24
Finished Apr 27 04:09:53 PM PDT 24
Peak memory 222780 kb
Host smart-1018d40c-29c9-4397-ac22-461e42bcc3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417842929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.417842929
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.134766567
Short name T112
Test name
Test status
Simulation time 286983758 ps
CPU time 12.27 seconds
Started Apr 27 04:12:51 PM PDT 24
Finished Apr 27 04:13:04 PM PDT 24
Peak memory 223532 kb
Host smart-8a6f6a53-7175-4060-ba03-a74d8aa2819d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134766567 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.134766567
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2968168990
Short name T135
Test name
Test status
Simulation time 1121611616 ps
CPU time 7.03 seconds
Started Apr 27 04:12:10 PM PDT 24
Finished Apr 27 04:12:18 PM PDT 24
Peak memory 214308 kb
Host smart-9706937d-0b90-4ad8-9a11-73fc9c2afc4c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2968168990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2968168990
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.600195569
Short name T93
Test name
Test status
Simulation time 1128606292 ps
CPU time 4.87 seconds
Started Apr 27 04:12:52 PM PDT 24
Finished Apr 27 04:12:58 PM PDT 24
Peak memory 208268 kb
Host smart-d0c35c9f-838e-48a8-bcbd-14c27c423e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600195569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.600195569
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2734007483
Short name T400
Test name
Test status
Simulation time 435631981 ps
CPU time 20.58 seconds
Started Apr 27 04:12:36 PM PDT 24
Finished Apr 27 04:12:58 PM PDT 24
Peak memory 214872 kb
Host smart-2d9392b6-7062-40c5-829d-fe62fec69586
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2734007483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2734007483
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2371543140
Short name T137
Test name
Test status
Simulation time 20769705 ps
CPU time 0.95 seconds
Started Apr 27 01:49:13 PM PDT 24
Finished Apr 27 01:49:15 PM PDT 24
Peak memory 205428 kb
Host smart-f00557ad-b84d-4b34-8701-ef5e8aa5d0dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371543140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2371543140
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.799339983
Short name T41
Test name
Test status
Simulation time 200612451 ps
CPU time 3.83 seconds
Started Apr 27 04:11:03 PM PDT 24
Finished Apr 27 04:11:07 PM PDT 24
Peak memory 222364 kb
Host smart-fb5bc39f-48d5-42d7-a77d-f979a854747c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799339983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.799339983
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2214229855
Short name T60
Test name
Test status
Simulation time 4988891954 ps
CPU time 51.01 seconds
Started Apr 27 04:11:30 PM PDT 24
Finished Apr 27 04:12:22 PM PDT 24
Peak memory 219940 kb
Host smart-cd22a1de-7cd5-4464-807d-09f8bacf1e25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214229855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2214229855
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.4182192499
Short name T292
Test name
Test status
Simulation time 1745558253 ps
CPU time 47.43 seconds
Started Apr 27 04:12:20 PM PDT 24
Finished Apr 27 04:13:08 PM PDT 24
Peak memory 214864 kb
Host smart-f8370722-a539-40b6-98e8-453514898113
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182192499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.4182192499
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3280747344
Short name T350
Test name
Test status
Simulation time 692816385 ps
CPU time 16.54 seconds
Started Apr 27 04:12:36 PM PDT 24
Finished Apr 27 04:12:54 PM PDT 24
Peak memory 215476 kb
Host smart-1888e24e-d598-4ffa-836c-23b62953560b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3280747344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3280747344
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1485692556
Short name T50
Test name
Test status
Simulation time 3576101340 ps
CPU time 40.76 seconds
Started Apr 27 04:11:43 PM PDT 24
Finished Apr 27 04:12:24 PM PDT 24
Peak memory 222652 kb
Host smart-489c075e-bc1d-4b57-a614-863f84ebb407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485692556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1485692556
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2845850299
Short name T45
Test name
Test status
Simulation time 259486671 ps
CPU time 3 seconds
Started Apr 27 04:11:54 PM PDT 24
Finished Apr 27 04:11:58 PM PDT 24
Peak memory 210016 kb
Host smart-1fbb05ac-ed41-4e73-bbd0-8faab1baded1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845850299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2845850299
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.507734075
Short name T211
Test name
Test status
Simulation time 2313076353 ps
CPU time 72.58 seconds
Started Apr 27 04:12:29 PM PDT 24
Finished Apr 27 04:13:42 PM PDT 24
Peak memory 216004 kb
Host smart-38c08588-b5ae-476c-aff1-e47296f50cf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507734075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.507734075
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.71282571
Short name T23
Test name
Test status
Simulation time 1188194248 ps
CPU time 5.22 seconds
Started Apr 27 04:11:42 PM PDT 24
Finished Apr 27 04:11:48 PM PDT 24
Peak memory 220912 kb
Host smart-7fbf7b9d-e57c-44e9-ae90-69519a310a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71282571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.71282571
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.808294225
Short name T114
Test name
Test status
Simulation time 710079777 ps
CPU time 6.31 seconds
Started Apr 27 01:49:07 PM PDT 24
Finished Apr 27 01:49:15 PM PDT 24
Peak memory 218856 kb
Host smart-955a004b-2e7f-4531-9cde-20a24f4dd0aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808294225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.808294225
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.4061212302
Short name T188
Test name
Test status
Simulation time 2610818081 ps
CPU time 137.86 seconds
Started Apr 27 04:11:49 PM PDT 24
Finished Apr 27 04:14:07 PM PDT 24
Peak memory 219480 kb
Host smart-0b0553b7-8f3c-43b7-8e18-3b2688847bb3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4061212302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.4061212302
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.724802340
Short name T35
Test name
Test status
Simulation time 139123777 ps
CPU time 4.08 seconds
Started Apr 27 04:10:15 PM PDT 24
Finished Apr 27 04:10:19 PM PDT 24
Peak memory 210536 kb
Host smart-958e4bc7-9899-45e7-a203-8dfd0b55cd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724802340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.724802340
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1071702529
Short name T179
Test name
Test status
Simulation time 777316971 ps
CPU time 35.88 seconds
Started Apr 27 04:09:53 PM PDT 24
Finished Apr 27 04:10:30 PM PDT 24
Peak memory 216432 kb
Host smart-e6d78b3e-718a-4c9f-8e4d-6f6c27627f07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071702529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1071702529
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1225485598
Short name T242
Test name
Test status
Simulation time 790262938 ps
CPU time 12.32 seconds
Started Apr 27 04:10:19 PM PDT 24
Finished Apr 27 04:10:32 PM PDT 24
Peak memory 214280 kb
Host smart-451b8fa1-a287-44da-994e-840269e5f710
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1225485598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1225485598
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.714053963
Short name T153
Test name
Test status
Simulation time 474550112 ps
CPU time 11.83 seconds
Started Apr 27 04:08:33 PM PDT 24
Finished Apr 27 04:08:45 PM PDT 24
Peak memory 222612 kb
Host smart-1fa3ab55-caef-4025-810f-f70867a8f1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714053963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.714053963
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.4220718612
Short name T201
Test name
Test status
Simulation time 392447966 ps
CPU time 6.7 seconds
Started Apr 27 04:10:03 PM PDT 24
Finished Apr 27 04:10:10 PM PDT 24
Peak memory 222392 kb
Host smart-450192d9-fe3d-411f-a6f5-316d231f5f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220718612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.4220718612
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2216586079
Short name T160
Test name
Test status
Simulation time 123754025 ps
CPU time 6.27 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:18 PM PDT 24
Peak memory 213832 kb
Host smart-a7e2f473-e586-417a-880c-6e499a39e66b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216586079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2216586079
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3001459271
Short name T359
Test name
Test status
Simulation time 35059107135 ps
CPU time 160.61 seconds
Started Apr 27 04:10:29 PM PDT 24
Finished Apr 27 04:13:10 PM PDT 24
Peak memory 215676 kb
Host smart-9dfee982-9530-41cc-8773-70923fc07269
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3001459271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3001459271
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1999533415
Short name T229
Test name
Test status
Simulation time 275672459 ps
CPU time 9.13 seconds
Started Apr 27 04:10:26 PM PDT 24
Finished Apr 27 04:10:36 PM PDT 24
Peak memory 214232 kb
Host smart-64d2218c-7c28-4221-bbf7-a6bbbb138294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999533415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1999533415
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2902582219
Short name T134
Test name
Test status
Simulation time 68659285 ps
CPU time 4.79 seconds
Started Apr 27 04:10:13 PM PDT 24
Finished Apr 27 04:10:18 PM PDT 24
Peak memory 215384 kb
Host smart-3b149619-bf0b-4be8-827f-e4a756eb851a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902582219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2902582219
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1176023441
Short name T290
Test name
Test status
Simulation time 5306888201 ps
CPU time 70.69 seconds
Started Apr 27 04:12:49 PM PDT 24
Finished Apr 27 04:14:00 PM PDT 24
Peak memory 221920 kb
Host smart-17c0cb67-0071-4341-9302-721e15c38a87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176023441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1176023441
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2363751851
Short name T101
Test name
Test status
Simulation time 15520035 ps
CPU time 0.96 seconds
Started Apr 27 04:10:10 PM PDT 24
Finished Apr 27 04:10:12 PM PDT 24
Peak memory 206024 kb
Host smart-896439dc-83d0-47ba-b7ea-ac740dc06152
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363751851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2363751851
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.823726612
Short name T243
Test name
Test status
Simulation time 162775428 ps
CPU time 5.52 seconds
Started Apr 27 04:08:44 PM PDT 24
Finished Apr 27 04:08:50 PM PDT 24
Peak memory 222440 kb
Host smart-47bc13fe-c145-4cb6-92da-faafdf8eb090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=823726612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.823726612
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.4273624524
Short name T214
Test name
Test status
Simulation time 7088565369 ps
CPU time 39.98 seconds
Started Apr 27 04:09:57 PM PDT 24
Finished Apr 27 04:10:38 PM PDT 24
Peak memory 215996 kb
Host smart-07d6941b-3683-41d2-b533-ebf224ba255e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273624524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.4273624524
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.348344481
Short name T196
Test name
Test status
Simulation time 129217399 ps
CPU time 2.87 seconds
Started Apr 27 04:11:11 PM PDT 24
Finished Apr 27 04:11:14 PM PDT 24
Peak memory 214220 kb
Host smart-b37109bc-0c23-49f1-9127-351f9864d740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348344481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.348344481
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.103413668
Short name T371
Test name
Test status
Simulation time 310342582 ps
CPU time 3.89 seconds
Started Apr 27 04:10:08 PM PDT 24
Finished Apr 27 04:10:12 PM PDT 24
Peak memory 221276 kb
Host smart-921d7d84-12c1-4df1-955f-2f7785827c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103413668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.103413668
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2948947029
Short name T276
Test name
Test status
Simulation time 177336287 ps
CPU time 3.02 seconds
Started Apr 27 04:11:30 PM PDT 24
Finished Apr 27 04:11:33 PM PDT 24
Peak memory 210724 kb
Host smart-fa81a971-6af3-4b29-a032-6b4f1e852842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948947029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2948947029
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2517762287
Short name T151
Test name
Test status
Simulation time 1931423663 ps
CPU time 21.09 seconds
Started Apr 27 04:12:20 PM PDT 24
Finished Apr 27 04:12:42 PM PDT 24
Peak memory 218392 kb
Host smart-5057c99b-7a71-4719-919e-b489636fe840
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517762287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2517762287
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.187507306
Short name T155
Test name
Test status
Simulation time 126885496 ps
CPU time 5.29 seconds
Started Apr 27 04:10:48 PM PDT 24
Finished Apr 27 04:10:55 PM PDT 24
Peak memory 222648 kb
Host smart-11631bb0-a919-46cf-92c8-eb56f5bb7a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187507306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.187507306
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.525847578
Short name T69
Test name
Test status
Simulation time 14866613766 ps
CPU time 54.31 seconds
Started Apr 27 04:09:27 PM PDT 24
Finished Apr 27 04:10:22 PM PDT 24
Peak memory 222588 kb
Host smart-924bb67f-b256-44c8-8eb1-e1366836c620
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525847578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.525847578
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1213043068
Short name T376
Test name
Test status
Simulation time 671000827 ps
CPU time 5.55 seconds
Started Apr 27 04:10:19 PM PDT 24
Finished Apr 27 04:10:25 PM PDT 24
Peak memory 219180 kb
Host smart-0f678341-5e47-47b1-8b6a-f288dc1d2011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213043068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1213043068
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.979500814
Short name T168
Test name
Test status
Simulation time 4748319228 ps
CPU time 48.84 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:50:01 PM PDT 24
Peak memory 213860 kb
Host smart-0191e3f0-228d-4fd5-a2c5-03d643720b26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979500814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.979500814
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3408521730
Short name T257
Test name
Test status
Simulation time 69334743979 ps
CPU time 516.52 seconds
Started Apr 27 04:12:05 PM PDT 24
Finished Apr 27 04:20:42 PM PDT 24
Peak memory 222544 kb
Host smart-34adeeb1-d412-42a6-9897-7c7b5f5256aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408521730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3408521730
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3482550202
Short name T261
Test name
Test status
Simulation time 792357489 ps
CPU time 10.18 seconds
Started Apr 27 04:12:12 PM PDT 24
Finished Apr 27 04:12:23 PM PDT 24
Peak memory 208716 kb
Host smart-c116e94b-d067-46ce-bf76-1944b1e41bd3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482550202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3482550202
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2080230000
Short name T255
Test name
Test status
Simulation time 2383219470 ps
CPU time 69.66 seconds
Started Apr 27 04:12:56 PM PDT 24
Finished Apr 27 04:14:06 PM PDT 24
Peak memory 217324 kb
Host smart-9af41c1a-80b3-4528-922a-6560beec94c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2080230000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2080230000
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1003232203
Short name T21
Test name
Test status
Simulation time 189463252 ps
CPU time 1.68 seconds
Started Apr 27 04:09:40 PM PDT 24
Finished Apr 27 04:09:42 PM PDT 24
Peak memory 209060 kb
Host smart-2669435f-a3f3-4bcf-9089-0e2ad33fa78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003232203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1003232203
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3721239630
Short name T40
Test name
Test status
Simulation time 56230777 ps
CPU time 2.42 seconds
Started Apr 27 04:12:28 PM PDT 24
Finished Apr 27 04:12:31 PM PDT 24
Peak memory 209980 kb
Host smart-dcfe83b2-a3d8-4e8a-8d86-615b0d08b8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721239630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3721239630
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1310313050
Short name T70
Test name
Test status
Simulation time 152647297 ps
CPU time 6.38 seconds
Started Apr 27 04:13:00 PM PDT 24
Finished Apr 27 04:13:08 PM PDT 24
Peak memory 222676 kb
Host smart-2fbd3f1a-107d-49a5-b275-afa6ccd3c6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310313050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1310313050
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3034301092
Short name T158
Test name
Test status
Simulation time 3423783282 ps
CPU time 12.36 seconds
Started Apr 27 04:09:02 PM PDT 24
Finished Apr 27 04:09:15 PM PDT 24
Peak memory 218208 kb
Host smart-9c22dfbf-758b-43f5-a7cf-8aa0fbe3bc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034301092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3034301092
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3423281226
Short name T25
Test name
Test status
Simulation time 97082509 ps
CPU time 4.23 seconds
Started Apr 27 04:10:24 PM PDT 24
Finished Apr 27 04:10:29 PM PDT 24
Peak memory 214260 kb
Host smart-f5b46834-86c0-49e9-bc38-a2c4960ffe77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423281226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3423281226
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2379688317
Short name T710
Test name
Test status
Simulation time 114582595 ps
CPU time 3.99 seconds
Started Apr 27 04:10:38 PM PDT 24
Finished Apr 27 04:10:42 PM PDT 24
Peak memory 208624 kb
Host smart-c230fe77-0257-4b4b-bb0b-8565560dba66
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379688317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2379688317
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.114968530
Short name T202
Test name
Test status
Simulation time 1091467806 ps
CPU time 10.92 seconds
Started Apr 27 04:11:21 PM PDT 24
Finished Apr 27 04:11:32 PM PDT 24
Peak memory 214256 kb
Host smart-4bb30665-4b3a-49bd-8dd8-7164b953f96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114968530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.114968530
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2673117304
Short name T838
Test name
Test status
Simulation time 657793613 ps
CPU time 29.03 seconds
Started Apr 27 04:11:39 PM PDT 24
Finished Apr 27 04:12:08 PM PDT 24
Peak memory 216744 kb
Host smart-7b481962-f209-4652-893d-4e06578a7ce2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673117304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2673117304
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1607589487
Short name T304
Test name
Test status
Simulation time 62851291 ps
CPU time 4.11 seconds
Started Apr 27 04:09:17 PM PDT 24
Finished Apr 27 04:09:22 PM PDT 24
Peak memory 215624 kb
Host smart-7c7083d8-ceda-4bb4-8231-a79ebc446638
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1607589487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1607589487
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2475634483
Short name T926
Test name
Test status
Simulation time 616405764 ps
CPU time 16.8 seconds
Started Apr 27 04:12:43 PM PDT 24
Finished Apr 27 04:13:00 PM PDT 24
Peak memory 222480 kb
Host smart-3da75ccf-ca39-4bfb-bccc-60147829fcd3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475634483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2475634483
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2419256831
Short name T169
Test name
Test status
Simulation time 245211398 ps
CPU time 3.37 seconds
Started Apr 27 01:49:08 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 209060 kb
Host smart-4f767b57-3edf-4454-a724-d945d5ebbe3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419256831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2419256831
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4259236851
Short name T159
Test name
Test status
Simulation time 495649271 ps
CPU time 4.92 seconds
Started Apr 27 04:09:34 PM PDT 24
Finished Apr 27 04:09:40 PM PDT 24
Peak memory 209924 kb
Host smart-0c36ac4c-062f-469f-adf7-bef0c4b3e59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259236851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4259236851
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3100710496
Short name T152
Test name
Test status
Simulation time 410043635 ps
CPU time 5.51 seconds
Started Apr 27 04:10:20 PM PDT 24
Finished Apr 27 04:10:26 PM PDT 24
Peak memory 217828 kb
Host smart-01a34c39-72a4-4c80-853d-d669b45647a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100710496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3100710496
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2248530241
Short name T154
Test name
Test status
Simulation time 86276651 ps
CPU time 4.48 seconds
Started Apr 27 04:09:08 PM PDT 24
Finished Apr 27 04:09:13 PM PDT 24
Peak memory 218460 kb
Host smart-f956d596-fb6e-4e35-887a-332cb73f4459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248530241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2248530241
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2628655879
Short name T157
Test name
Test status
Simulation time 177903663 ps
CPU time 6.83 seconds
Started Apr 27 04:09:34 PM PDT 24
Finished Apr 27 04:09:41 PM PDT 24
Peak memory 222636 kb
Host smart-a58d80c8-1ad9-4f72-8796-765e46883daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628655879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2628655879
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.551136888
Short name T200
Test name
Test status
Simulation time 1797169291 ps
CPU time 8.83 seconds
Started Apr 27 04:11:09 PM PDT 24
Finished Apr 27 04:11:18 PM PDT 24
Peak memory 214400 kb
Host smart-ffe00538-ddf4-424d-907e-c13ab8532a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551136888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.551136888
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2879378309
Short name T283
Test name
Test status
Simulation time 636727505 ps
CPU time 7.31 seconds
Started Apr 27 04:11:27 PM PDT 24
Finished Apr 27 04:11:34 PM PDT 24
Peak memory 214296 kb
Host smart-a147179c-5fed-4f61-b884-cae0a7c1514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879378309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2879378309
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.574591162
Short name T328
Test name
Test status
Simulation time 596313963 ps
CPU time 21.94 seconds
Started Apr 27 04:11:54 PM PDT 24
Finished Apr 27 04:12:16 PM PDT 24
Peak memory 208564 kb
Host smart-67a7847e-5f19-45e9-b3ec-1c4ed144b4de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574591162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.574591162
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3227763439
Short name T231
Test name
Test status
Simulation time 1196343504 ps
CPU time 43.29 seconds
Started Apr 27 04:12:05 PM PDT 24
Finished Apr 27 04:12:49 PM PDT 24
Peak memory 222428 kb
Host smart-82aadd1e-b939-4fb7-984d-6fff1577dae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227763439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3227763439
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.639094402
Short name T279
Test name
Test status
Simulation time 858667120 ps
CPU time 11.25 seconds
Started Apr 27 04:12:20 PM PDT 24
Finished Apr 27 04:12:32 PM PDT 24
Peak memory 222436 kb
Host smart-f3113efc-3a3c-44fc-a8ad-9de7b893b13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639094402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.639094402
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3525971501
Short name T325
Test name
Test status
Simulation time 252908513 ps
CPU time 3.03 seconds
Started Apr 27 04:12:54 PM PDT 24
Finished Apr 27 04:12:58 PM PDT 24
Peak memory 208900 kb
Host smart-ce0dd2d9-5da3-4d98-85e4-de7bfb026583
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525971501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3525971501
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3040830786
Short name T92
Test name
Test status
Simulation time 116770520 ps
CPU time 3.48 seconds
Started Apr 27 04:12:58 PM PDT 24
Finished Apr 27 04:13:02 PM PDT 24
Peak memory 214280 kb
Host smart-89194b5c-0be7-48ff-bbf0-cac9762bb620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040830786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3040830786
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2936755828
Short name T275
Test name
Test status
Simulation time 330276387 ps
CPU time 4.86 seconds
Started Apr 27 04:09:29 PM PDT 24
Finished Apr 27 04:09:34 PM PDT 24
Peak memory 211688 kb
Host smart-956b0c45-e37b-4da2-ae51-49fe3592e37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936755828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2936755828
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.1591964053
Short name T204
Test name
Test status
Simulation time 326063955 ps
CPU time 21.21 seconds
Started Apr 27 04:09:33 PM PDT 24
Finished Apr 27 04:09:55 PM PDT 24
Peak memory 222584 kb
Host smart-819a5a5b-9669-4a97-970d-5d6753e87538
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591964053 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.1591964053
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3437754040
Short name T163
Test name
Test status
Simulation time 505373450 ps
CPU time 4.87 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:17 PM PDT 24
Peak memory 213812 kb
Host smart-200cb9b2-a1cf-4c51-bcd0-df6d50e3a652
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437754040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3437754040
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3804561061
Short name T171
Test name
Test status
Simulation time 122027861 ps
CPU time 6.19 seconds
Started Apr 27 01:48:50 PM PDT 24
Finished Apr 27 01:48:57 PM PDT 24
Peak memory 213828 kb
Host smart-95371790-4456-4644-9ac3-a7e0536485d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804561061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3804561061
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.53866913
Short name T166
Test name
Test status
Simulation time 568726245 ps
CPU time 5.36 seconds
Started Apr 27 01:48:56 PM PDT 24
Finished Apr 27 01:49:03 PM PDT 24
Peak memory 209172 kb
Host smart-30e919dc-d9c2-410e-997a-6953089f5253
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53866913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.53866913
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1727472687
Short name T173
Test name
Test status
Simulation time 1365385782 ps
CPU time 9.84 seconds
Started Apr 27 01:48:54 PM PDT 24
Finished Apr 27 01:49:05 PM PDT 24
Peak memory 209064 kb
Host smart-a449f3d2-a9e1-4d20-9375-a3859deec7f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727472687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1727472687
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2726567877
Short name T156
Test name
Test status
Simulation time 467039607 ps
CPU time 4.9 seconds
Started Apr 27 04:12:53 PM PDT 24
Finished Apr 27 04:12:58 PM PDT 24
Peak memory 218020 kb
Host smart-dff6f470-a4b5-474e-87a2-c5cbd9c5fb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726567877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2726567877
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3934901828
Short name T244
Test name
Test status
Simulation time 231481200 ps
CPU time 3.36 seconds
Started Apr 27 04:09:56 PM PDT 24
Finished Apr 27 04:10:00 PM PDT 24
Peak memory 214380 kb
Host smart-51f7cc92-099a-4c0b-8941-959ab443557e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934901828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3934901828
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3783918285
Short name T402
Test name
Test status
Simulation time 227275324 ps
CPU time 13.09 seconds
Started Apr 27 04:10:04 PM PDT 24
Finished Apr 27 04:10:17 PM PDT 24
Peak memory 214796 kb
Host smart-b88495ca-667c-4c58-b58e-2907b4228ef7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3783918285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3783918285
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.198607955
Short name T329
Test name
Test status
Simulation time 3011377912 ps
CPU time 101.99 seconds
Started Apr 27 04:10:38 PM PDT 24
Finished Apr 27 04:12:21 PM PDT 24
Peak memory 221392 kb
Host smart-025fb7d4-f295-435e-9bb2-793a0c80497c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198607955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.198607955
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.212330992
Short name T394
Test name
Test status
Simulation time 313104029 ps
CPU time 4.93 seconds
Started Apr 27 04:10:45 PM PDT 24
Finished Apr 27 04:10:51 PM PDT 24
Peak memory 215348 kb
Host smart-f47b9ebc-0919-4b8d-ae9d-26fd8f19892b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212330992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.212330992
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1309391225
Short name T68
Test name
Test status
Simulation time 509606713 ps
CPU time 15.2 seconds
Started Apr 27 04:10:49 PM PDT 24
Finished Apr 27 04:11:05 PM PDT 24
Peak memory 218584 kb
Host smart-79046583-743b-4c0d-980c-266dc1dfe01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309391225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1309391225
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.954323249
Short name T316
Test name
Test status
Simulation time 54614544 ps
CPU time 2.29 seconds
Started Apr 27 04:10:53 PM PDT 24
Finished Apr 27 04:10:56 PM PDT 24
Peak memory 211180 kb
Host smart-a0c2d031-80ab-4bfe-a054-d973a91e8b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954323249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.954323249
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3882840992
Short name T361
Test name
Test status
Simulation time 233710017 ps
CPU time 7.04 seconds
Started Apr 27 04:10:54 PM PDT 24
Finished Apr 27 04:11:01 PM PDT 24
Peak memory 214352 kb
Host smart-a88a4b8c-c2aa-45ca-9faf-efde4ab9470d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882840992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3882840992
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1770598945
Short name T378
Test name
Test status
Simulation time 326054675 ps
CPU time 4.29 seconds
Started Apr 27 04:11:19 PM PDT 24
Finished Apr 27 04:11:24 PM PDT 24
Peak memory 214280 kb
Host smart-dc8fed5f-2f0b-40e3-b1ba-e757200da7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770598945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1770598945
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3249670590
Short name T218
Test name
Test status
Simulation time 60975722 ps
CPU time 4.09 seconds
Started Apr 27 04:11:29 PM PDT 24
Finished Apr 27 04:11:34 PM PDT 24
Peak memory 214360 kb
Host smart-764b350f-53a4-4c62-ba6d-e07479d84571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249670590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3249670590
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1624288023
Short name T318
Test name
Test status
Simulation time 155302888 ps
CPU time 9.22 seconds
Started Apr 27 04:11:49 PM PDT 24
Finished Apr 27 04:11:59 PM PDT 24
Peak memory 215424 kb
Host smart-d087a11f-c142-4907-abfa-281e790146f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624288023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1624288023
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.94732768
Short name T209
Test name
Test status
Simulation time 167876971 ps
CPU time 2.95 seconds
Started Apr 27 04:11:48 PM PDT 24
Finished Apr 27 04:11:51 PM PDT 24
Peak memory 216448 kb
Host smart-5e852303-0ec1-4457-a280-3f0ea394ee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94732768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.94732768
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.506792686
Short name T254
Test name
Test status
Simulation time 213385883 ps
CPU time 7.52 seconds
Started Apr 27 04:12:03 PM PDT 24
Finished Apr 27 04:12:11 PM PDT 24
Peak memory 214268 kb
Host smart-04dafa0c-be29-40b9-8958-83584e739b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506792686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.506792686
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3932956304
Short name T300
Test name
Test status
Simulation time 11645369602 ps
CPU time 60.44 seconds
Started Apr 27 04:12:37 PM PDT 24
Finished Apr 27 04:13:38 PM PDT 24
Peak memory 214276 kb
Host smart-36eaca49-a29f-4e28-a636-e1d35a306762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932956304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3932956304
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.4223550367
Short name T205
Test name
Test status
Simulation time 169410244 ps
CPU time 5.66 seconds
Started Apr 27 04:13:10 PM PDT 24
Finished Apr 27 04:13:16 PM PDT 24
Peak memory 219732 kb
Host smart-51ca8b68-feb1-4e0b-b5fe-aefd49e907b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223550367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.4223550367
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.48874166
Short name T216
Test name
Test status
Simulation time 612439105 ps
CPU time 11.66 seconds
Started Apr 27 04:13:09 PM PDT 24
Finished Apr 27 04:13:21 PM PDT 24
Peak memory 222512 kb
Host smart-2b9a16d8-6e7f-47b3-b330-139dce92a204
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48874166 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.48874166
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3177515564
Short name T375
Test name
Test status
Simulation time 194458622 ps
CPU time 6.6 seconds
Started Apr 27 01:48:53 PM PDT 24
Finished Apr 27 01:49:01 PM PDT 24
Peak memory 205596 kb
Host smart-a20da4e6-8c6e-4479-ba3e-54407c9e553c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177515564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
177515564
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.420628707
Short name T441
Test name
Test status
Simulation time 867359069 ps
CPU time 14.96 seconds
Started Apr 27 01:48:54 PM PDT 24
Finished Apr 27 01:49:11 PM PDT 24
Peak memory 205496 kb
Host smart-74095b10-753c-4a46-8b35-a853cb390519
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420628707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.420628707
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2361942430
Short name T481
Test name
Test status
Simulation time 18396053 ps
CPU time 1.22 seconds
Started Apr 27 01:48:51 PM PDT 24
Finished Apr 27 01:48:53 PM PDT 24
Peak memory 205528 kb
Host smart-c98a4658-6b8f-4a48-a0b5-6097ef6ec13f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361942430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
361942430
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.748109323
Short name T430
Test name
Test status
Simulation time 75381474 ps
CPU time 1.51 seconds
Started Apr 27 01:49:08 PM PDT 24
Finished Apr 27 01:49:11 PM PDT 24
Peak memory 213872 kb
Host smart-a51a0249-0837-40ff-bbf1-60afe27b3036
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748109323 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.748109323
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2109224820
Short name T139
Test name
Test status
Simulation time 33138939 ps
CPU time 1.32 seconds
Started Apr 27 01:48:48 PM PDT 24
Finished Apr 27 01:48:50 PM PDT 24
Peak memory 205436 kb
Host smart-fdd0c3a1-e77e-4f57-9327-2980ded137e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109224820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2109224820
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.748767008
Short name T503
Test name
Test status
Simulation time 13553410 ps
CPU time 0.88 seconds
Started Apr 27 01:49:02 PM PDT 24
Finished Apr 27 01:49:03 PM PDT 24
Peak memory 205496 kb
Host smart-117db4ca-1a13-413a-8282-2507c79becdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748767008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.748767008
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1535847811
Short name T146
Test name
Test status
Simulation time 921434578 ps
CPU time 2.06 seconds
Started Apr 27 01:49:05 PM PDT 24
Finished Apr 27 01:49:07 PM PDT 24
Peak memory 205472 kb
Host smart-d6bbad60-f8b9-4b11-905a-da346decd5a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535847811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1535847811
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1490632370
Short name T539
Test name
Test status
Simulation time 688296519 ps
CPU time 3.69 seconds
Started Apr 27 01:49:05 PM PDT 24
Finished Apr 27 01:49:09 PM PDT 24
Peak memory 214008 kb
Host smart-4446945b-3126-4215-9ff1-3711c50f641d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490632370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1490632370
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2615828521
Short name T442
Test name
Test status
Simulation time 305493502 ps
CPU time 12.07 seconds
Started Apr 27 01:48:55 PM PDT 24
Finished Apr 27 01:49:09 PM PDT 24
Peak memory 213944 kb
Host smart-062f1ee4-e07d-407d-9b3c-fcd6420c9bb8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615828521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2615828521
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3544669616
Short name T540
Test name
Test status
Simulation time 557954725 ps
CPU time 3.49 seconds
Started Apr 27 01:49:10 PM PDT 24
Finished Apr 27 01:49:16 PM PDT 24
Peak memory 216412 kb
Host smart-64c5f73f-567c-4989-bf6f-6c12f1a5fca8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544669616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3544669616
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.4254131958
Short name T438
Test name
Test status
Simulation time 139597268 ps
CPU time 5 seconds
Started Apr 27 01:48:48 PM PDT 24
Finished Apr 27 01:48:54 PM PDT 24
Peak memory 208892 kb
Host smart-bc93ea83-9bb7-40a9-9ce5-0a4ca72dfdd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254131958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.4254131958
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3995663610
Short name T488
Test name
Test status
Simulation time 385040839 ps
CPU time 4.86 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:17 PM PDT 24
Peak memory 205432 kb
Host smart-c09841fb-3b00-4919-b56d-19404f78095e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995663610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
995663610
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3653733239
Short name T374
Test name
Test status
Simulation time 1177724292 ps
CPU time 9.93 seconds
Started Apr 27 01:48:54 PM PDT 24
Finished Apr 27 01:49:05 PM PDT 24
Peak memory 205512 kb
Host smart-36da2469-aa0b-4865-a4d0-1cfeb22228c4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653733239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
653733239
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.344307321
Short name T426
Test name
Test status
Simulation time 74757666 ps
CPU time 1.19 seconds
Started Apr 27 01:48:49 PM PDT 24
Finished Apr 27 01:48:52 PM PDT 24
Peak memory 205496 kb
Host smart-5857907b-ea7a-468e-a5a1-161ecfd5e68d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344307321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.344307321
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2665353920
Short name T516
Test name
Test status
Simulation time 71223674 ps
CPU time 1.31 seconds
Started Apr 27 01:48:56 PM PDT 24
Finished Apr 27 01:48:59 PM PDT 24
Peak memory 205600 kb
Host smart-d000d715-ab42-4776-9630-2e827418a5b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665353920 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2665353920
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.85019129
Short name T477
Test name
Test status
Simulation time 53356161 ps
CPU time 1.69 seconds
Started Apr 27 01:48:46 PM PDT 24
Finished Apr 27 01:48:48 PM PDT 24
Peak memory 205540 kb
Host smart-ec8c9577-50bf-4609-af63-df591d12908a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85019129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.85019129
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.458086430
Short name T509
Test name
Test status
Simulation time 20443452 ps
CPU time 0.71 seconds
Started Apr 27 01:49:02 PM PDT 24
Finished Apr 27 01:49:03 PM PDT 24
Peak memory 205360 kb
Host smart-a9f478fc-2c3f-4dce-a886-a42361c2b400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458086430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.458086430
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2772937283
Short name T143
Test name
Test status
Simulation time 120891470 ps
CPU time 2.12 seconds
Started Apr 27 01:49:02 PM PDT 24
Finished Apr 27 01:49:04 PM PDT 24
Peak memory 213696 kb
Host smart-2965bfa9-ae69-49ab-b8ff-ff72e4043e38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772937283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2772937283
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.921003387
Short name T435
Test name
Test status
Simulation time 1346624019 ps
CPU time 11.24 seconds
Started Apr 27 01:48:48 PM PDT 24
Finished Apr 27 01:49:01 PM PDT 24
Peak memory 214116 kb
Host smart-b6dc976e-e937-42e9-aa43-9d2876c0f896
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921003387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.921003387
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2901965770
Short name T535
Test name
Test status
Simulation time 41796894 ps
CPU time 2.86 seconds
Started Apr 27 01:49:11 PM PDT 24
Finished Apr 27 01:49:19 PM PDT 24
Peak memory 213768 kb
Host smart-83b988aa-cb48-4f86-8753-5e638856d46b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901965770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2901965770
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1937697298
Short name T178
Test name
Test status
Simulation time 58330473 ps
CPU time 3.26 seconds
Started Apr 27 01:48:53 PM PDT 24
Finished Apr 27 01:48:57 PM PDT 24
Peak memory 213992 kb
Host smart-37ce6186-5012-4b39-8666-911340d3570d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937697298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1937697298
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.92021201
Short name T531
Test name
Test status
Simulation time 11461435 ps
CPU time 1.01 seconds
Started Apr 27 01:49:00 PM PDT 24
Finished Apr 27 01:49:02 PM PDT 24
Peak memory 205528 kb
Host smart-9c2328ae-51a3-4375-b75e-50a40419e76f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92021201 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.92021201
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2533726941
Short name T144
Test name
Test status
Simulation time 16785976 ps
CPU time 0.88 seconds
Started Apr 27 01:48:57 PM PDT 24
Finished Apr 27 01:48:59 PM PDT 24
Peak memory 205312 kb
Host smart-63681eab-d464-4b4b-80b5-1210125fdd9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533726941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2533726941
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2620401833
Short name T505
Test name
Test status
Simulation time 242856799 ps
CPU time 0.74 seconds
Started Apr 27 01:49:06 PM PDT 24
Finished Apr 27 01:49:07 PM PDT 24
Peak memory 205460 kb
Host smart-7db9e151-599a-48c9-bb0e-9c9bf9d809e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620401833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2620401833
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3967178166
Short name T147
Test name
Test status
Simulation time 333788831 ps
CPU time 2.33 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 205500 kb
Host smart-8afcc29a-2938-43a8-94b2-6904e0d83d8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967178166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3967178166
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3557195110
Short name T537
Test name
Test status
Simulation time 130283002 ps
CPU time 4.62 seconds
Started Apr 27 01:49:07 PM PDT 24
Finished Apr 27 01:49:13 PM PDT 24
Peak memory 214080 kb
Host smart-24ca3276-a1cc-42ea-b94e-5b40e885d870
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557195110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3557195110
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1847737517
Short name T127
Test name
Test status
Simulation time 217127642 ps
CPU time 1.58 seconds
Started Apr 27 01:49:05 PM PDT 24
Finished Apr 27 01:49:07 PM PDT 24
Peak memory 213904 kb
Host smart-b9b58672-ab98-443d-b0aa-2317282a6bef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847737517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1847737517
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1102300024
Short name T454
Test name
Test status
Simulation time 27368047 ps
CPU time 1.56 seconds
Started Apr 27 01:49:15 PM PDT 24
Finished Apr 27 01:49:18 PM PDT 24
Peak memory 213896 kb
Host smart-9dc3f632-140a-4b54-ac6f-1a378548b8f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102300024 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1102300024
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3404491619
Short name T530
Test name
Test status
Simulation time 29911856 ps
CPU time 1.2 seconds
Started Apr 27 01:49:06 PM PDT 24
Finished Apr 27 01:49:08 PM PDT 24
Peak memory 205432 kb
Host smart-b8b83d64-a796-4f4b-8538-f8086472a670
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404491619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3404491619
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2232521110
Short name T422
Test name
Test status
Simulation time 34180332 ps
CPU time 0.82 seconds
Started Apr 27 01:48:59 PM PDT 24
Finished Apr 27 01:49:00 PM PDT 24
Peak memory 205464 kb
Host smart-80553680-7e33-44cb-817a-93c634b75c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232521110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2232521110
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1168889022
Short name T483
Test name
Test status
Simulation time 316658110 ps
CPU time 2.28 seconds
Started Apr 27 01:49:11 PM PDT 24
Finished Apr 27 01:49:16 PM PDT 24
Peak memory 205536 kb
Host smart-2f768b17-787a-4967-828d-1e1e1b553120
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168889022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1168889022
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1085643059
Short name T116
Test name
Test status
Simulation time 80592327 ps
CPU time 2.53 seconds
Started Apr 27 01:49:13 PM PDT 24
Finished Apr 27 01:49:17 PM PDT 24
Peak memory 213988 kb
Host smart-1dd715a6-2dcf-446c-9f38-37bd32c2a785
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085643059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1085643059
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3794638860
Short name T538
Test name
Test status
Simulation time 418035356 ps
CPU time 10.45 seconds
Started Apr 27 01:49:20 PM PDT 24
Finished Apr 27 01:49:30 PM PDT 24
Peak memory 213888 kb
Host smart-cfb7268c-3fe0-41d8-9f3d-f4ea3993d584
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794638860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3794638860
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3245100589
Short name T494
Test name
Test status
Simulation time 118982407 ps
CPU time 2.23 seconds
Started Apr 27 01:49:07 PM PDT 24
Finished Apr 27 01:49:11 PM PDT 24
Peak memory 213828 kb
Host smart-c01df8e3-475d-4357-a6cb-57d5e24dd620
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245100589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3245100589
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2103935799
Short name T460
Test name
Test status
Simulation time 234296283 ps
CPU time 1.73 seconds
Started Apr 27 01:49:11 PM PDT 24
Finished Apr 27 01:49:15 PM PDT 24
Peak memory 213896 kb
Host smart-70f222e8-452f-4beb-b3df-cc130539f2e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103935799 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2103935799
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1038414524
Short name T444
Test name
Test status
Simulation time 16370565 ps
CPU time 0.87 seconds
Started Apr 27 01:49:07 PM PDT 24
Finished Apr 27 01:49:09 PM PDT 24
Peak memory 205456 kb
Host smart-9863e24e-8461-4152-858c-9e69dec01077
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038414524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1038414524
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1664126713
Short name T520
Test name
Test status
Simulation time 41519973 ps
CPU time 0.77 seconds
Started Apr 27 01:49:10 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 205372 kb
Host smart-fef0554a-f3bc-461b-8454-a91c9d12069f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664126713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1664126713
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.706779613
Short name T490
Test name
Test status
Simulation time 192052057 ps
CPU time 3.95 seconds
Started Apr 27 01:49:04 PM PDT 24
Finished Apr 27 01:49:09 PM PDT 24
Peak memory 213972 kb
Host smart-97a3e602-3400-4734-ad2d-87ec5d72b9dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706779613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.706779613
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2310431520
Short name T434
Test name
Test status
Simulation time 42055237 ps
CPU time 2.61 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:15 PM PDT 24
Peak memory 213788 kb
Host smart-58c8e32e-60d2-467f-8703-d34b45d302a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310431520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2310431520
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3475071877
Short name T492
Test name
Test status
Simulation time 15609060 ps
CPU time 1.38 seconds
Started Apr 27 01:49:08 PM PDT 24
Finished Apr 27 01:49:11 PM PDT 24
Peak memory 213912 kb
Host smart-427051a3-0cf0-44ad-9970-6ad9b2494d78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475071877 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3475071877
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3125407474
Short name T148
Test name
Test status
Simulation time 37334785 ps
CPU time 0.96 seconds
Started Apr 27 01:48:55 PM PDT 24
Finished Apr 27 01:48:57 PM PDT 24
Peak memory 205396 kb
Host smart-aca44155-826d-450e-b420-69ba5282e6bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125407474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3125407474
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3194342630
Short name T526
Test name
Test status
Simulation time 7621984 ps
CPU time 0.74 seconds
Started Apr 27 01:48:57 PM PDT 24
Finished Apr 27 01:48:59 PM PDT 24
Peak memory 205380 kb
Host smart-874801b5-8dc9-4030-a018-22170b262053
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194342630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3194342630
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2639188032
Short name T497
Test name
Test status
Simulation time 39440203 ps
CPU time 2.62 seconds
Started Apr 27 01:49:49 PM PDT 24
Finished Apr 27 01:49:53 PM PDT 24
Peak memory 205504 kb
Host smart-18abb76a-8555-4c36-8051-c27913429fe8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639188032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2639188032
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4253175677
Short name T457
Test name
Test status
Simulation time 1891320844 ps
CPU time 20.59 seconds
Started Apr 27 01:49:00 PM PDT 24
Finished Apr 27 01:49:22 PM PDT 24
Peak memory 218080 kb
Host smart-c3d8da29-4b40-418e-b956-6515e52f1c98
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253175677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.4253175677
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3722335779
Short name T501
Test name
Test status
Simulation time 874952590 ps
CPU time 5.77 seconds
Started Apr 27 01:48:54 PM PDT 24
Finished Apr 27 01:49:02 PM PDT 24
Peak memory 213944 kb
Host smart-37b20de8-8f3f-4823-baaa-559fe5b81014
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722335779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3722335779
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1514461629
Short name T464
Test name
Test status
Simulation time 478866994 ps
CPU time 4.95 seconds
Started Apr 27 01:49:07 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 213832 kb
Host smart-e3ba3103-b875-431b-b02c-dca73ca25d98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514461629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1514461629
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1955145475
Short name T431
Test name
Test status
Simulation time 30269468 ps
CPU time 1.3 seconds
Started Apr 27 01:49:07 PM PDT 24
Finished Apr 27 01:49:09 PM PDT 24
Peak memory 213816 kb
Host smart-cebf3ba9-f335-495f-840b-b9823f4cb2ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955145475 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1955145475
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.457675784
Short name T533
Test name
Test status
Simulation time 155793894 ps
CPU time 1.16 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:12 PM PDT 24
Peak memory 205616 kb
Host smart-912f71e0-2486-4238-a6c0-81f2d2d862e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457675784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.457675784
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1143159690
Short name T425
Test name
Test status
Simulation time 7654159 ps
CPU time 0.78 seconds
Started Apr 27 01:49:08 PM PDT 24
Finished Apr 27 01:49:12 PM PDT 24
Peak memory 205512 kb
Host smart-34a9fd37-3163-4330-9d5e-ad0348a8e0a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143159690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1143159690
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4198110208
Short name T448
Test name
Test status
Simulation time 94228554 ps
CPU time 1.64 seconds
Started Apr 27 01:49:07 PM PDT 24
Finished Apr 27 01:49:10 PM PDT 24
Peak memory 205448 kb
Host smart-cdc5d320-20ff-41e3-857e-0de0a7e39306
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198110208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.4198110208
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3389098661
Short name T176
Test name
Test status
Simulation time 118621434 ps
CPU time 2.44 seconds
Started Apr 27 01:49:15 PM PDT 24
Finished Apr 27 01:49:18 PM PDT 24
Peak memory 218652 kb
Host smart-e399f9b2-1604-4b61-9ae4-09f776ba7691
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389098661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3389098661
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3435511598
Short name T510
Test name
Test status
Simulation time 210191946 ps
CPU time 8.33 seconds
Started Apr 27 01:49:00 PM PDT 24
Finished Apr 27 01:49:10 PM PDT 24
Peak memory 213980 kb
Host smart-5745dc2c-50bf-491e-b6cd-cdee620b09bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435511598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3435511598
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1579455051
Short name T140
Test name
Test status
Simulation time 411350233 ps
CPU time 2.83 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 213756 kb
Host smart-0a51a854-3464-44be-a4d7-a13485b441bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579455051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1579455051
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3036056000
Short name T373
Test name
Test status
Simulation time 804062850 ps
CPU time 5.88 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:18 PM PDT 24
Peak memory 213724 kb
Host smart-8c3715c6-651e-4673-8027-87267b9d6f2f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036056000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3036056000
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3363582523
Short name T527
Test name
Test status
Simulation time 23408587 ps
CPU time 1.18 seconds
Started Apr 27 01:49:11 PM PDT 24
Finished Apr 27 01:49:19 PM PDT 24
Peak memory 213740 kb
Host smart-c50673fc-5a34-4f28-b235-6674da2613ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363582523 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3363582523
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2458986799
Short name T529
Test name
Test status
Simulation time 19828322 ps
CPU time 1.09 seconds
Started Apr 27 01:49:17 PM PDT 24
Finished Apr 27 01:49:18 PM PDT 24
Peak memory 205556 kb
Host smart-c358bf6e-53bb-43da-80bb-76b8302ab02c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458986799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2458986799
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1124920030
Short name T522
Test name
Test status
Simulation time 26696911 ps
CPU time 0.8 seconds
Started Apr 27 01:49:24 PM PDT 24
Finished Apr 27 01:49:25 PM PDT 24
Peak memory 205412 kb
Host smart-ec30d9a3-e4f3-48bf-81e5-110eee94db86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124920030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1124920030
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1674106334
Short name T455
Test name
Test status
Simulation time 465692030 ps
CPU time 3.33 seconds
Started Apr 27 01:49:10 PM PDT 24
Finished Apr 27 01:49:16 PM PDT 24
Peak memory 214056 kb
Host smart-1ce086dd-99d2-4d30-b6eb-48420885c32f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674106334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1674106334
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.272873356
Short name T191
Test name
Test status
Simulation time 409402009 ps
CPU time 5.54 seconds
Started Apr 27 01:49:22 PM PDT 24
Finished Apr 27 01:49:28 PM PDT 24
Peak memory 216892 kb
Host smart-c3decebb-a966-47f6-b1f0-50456e9c8997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272873356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.272873356
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.6530393
Short name T459
Test name
Test status
Simulation time 58740912 ps
CPU time 1 seconds
Started Apr 27 01:49:00 PM PDT 24
Finished Apr 27 01:49:02 PM PDT 24
Peak memory 205596 kb
Host smart-acdf37ac-521c-4422-875f-b9404274dcb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6530393 -assert nopostproc +UVM_TESTNAME=ke
ymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.6530393
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1867209869
Short name T482
Test name
Test status
Simulation time 11121081 ps
CPU time 0.89 seconds
Started Apr 27 01:49:13 PM PDT 24
Finished Apr 27 01:49:15 PM PDT 24
Peak memory 205440 kb
Host smart-b912c11d-e87c-4032-b6f7-612bb505973b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867209869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1867209869
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3479780274
Short name T479
Test name
Test status
Simulation time 28623178 ps
CPU time 0.69 seconds
Started Apr 27 01:49:02 PM PDT 24
Finished Apr 27 01:49:03 PM PDT 24
Peak memory 205440 kb
Host smart-70752690-cc84-431e-b7f6-a109cd8565e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479780274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3479780274
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2879468373
Short name T450
Test name
Test status
Simulation time 95540794 ps
CPU time 2.88 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:15 PM PDT 24
Peak memory 216160 kb
Host smart-0cd41895-1896-45d5-95ef-50eae1b2830d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879468373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2879468373
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1633429522
Short name T420
Test name
Test status
Simulation time 26710108 ps
CPU time 1.17 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:13 PM PDT 24
Peak memory 205752 kb
Host smart-a95bf708-4da9-42ff-96c6-d877f1e0996c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633429522 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1633429522
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2291864868
Short name T145
Test name
Test status
Simulation time 22836334 ps
CPU time 1.18 seconds
Started Apr 27 01:49:13 PM PDT 24
Finished Apr 27 01:49:15 PM PDT 24
Peak memory 205488 kb
Host smart-1fe62149-1532-4588-bd20-c725f60aaffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291864868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2291864868
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3889836697
Short name T437
Test name
Test status
Simulation time 9370039 ps
CPU time 0.69 seconds
Started Apr 27 01:49:11 PM PDT 24
Finished Apr 27 01:49:22 PM PDT 24
Peak memory 205304 kb
Host smart-3c50531f-4ac7-4865-b508-fc527c3beb69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889836697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3889836697
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3991498190
Short name T465
Test name
Test status
Simulation time 872428778 ps
CPU time 3.18 seconds
Started Apr 27 01:49:07 PM PDT 24
Finished Apr 27 01:49:12 PM PDT 24
Peak memory 214056 kb
Host smart-ba944cbc-3297-4c87-87f8-cfaced388bef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991498190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3991498190
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3773726209
Short name T182
Test name
Test status
Simulation time 60000007 ps
CPU time 1.66 seconds
Started Apr 27 01:49:23 PM PDT 24
Finished Apr 27 01:49:25 PM PDT 24
Peak memory 213820 kb
Host smart-2f335e93-363c-43e6-bfa0-f9d4f7574c51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773726209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3773726209
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3837584496
Short name T543
Test name
Test status
Simulation time 2496992836 ps
CPU time 20.37 seconds
Started Apr 27 01:49:17 PM PDT 24
Finished Apr 27 01:49:38 PM PDT 24
Peak memory 213900 kb
Host smart-5fa8d5c1-9f97-41db-b88b-eb7a07743b65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837584496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3837584496
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2243218126
Short name T532
Test name
Test status
Simulation time 37043704 ps
CPU time 1.59 seconds
Started Apr 27 01:49:10 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 217892 kb
Host smart-5cc7ea45-157c-4022-ac5f-c80658cca3c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243218126 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2243218126
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3536678298
Short name T423
Test name
Test status
Simulation time 29600721 ps
CPU time 0.81 seconds
Started Apr 27 01:49:11 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 205324 kb
Host smart-823704cf-8b6e-4157-82ee-c05cc107bf09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536678298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3536678298
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2442003852
Short name T458
Test name
Test status
Simulation time 27876984 ps
CPU time 1.7 seconds
Started Apr 27 01:49:07 PM PDT 24
Finished Apr 27 01:49:10 PM PDT 24
Peak memory 205616 kb
Host smart-ddc9f23f-3cfd-47b4-b792-564688e1b7da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442003852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2442003852
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1123409556
Short name T181
Test name
Test status
Simulation time 178512378 ps
CPU time 5.55 seconds
Started Apr 27 01:49:23 PM PDT 24
Finished Apr 27 01:49:29 PM PDT 24
Peak memory 213916 kb
Host smart-3955fc20-b727-4bf8-af56-eaea4367f748
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123409556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1123409556
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4170902394
Short name T508
Test name
Test status
Simulation time 385807792 ps
CPU time 4.45 seconds
Started Apr 27 01:49:30 PM PDT 24
Finished Apr 27 01:49:35 PM PDT 24
Peak memory 214016 kb
Host smart-04007bd5-53e4-4179-b015-40cb48c40af8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170902394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.4170902394
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2630892338
Short name T126
Test name
Test status
Simulation time 156084435 ps
CPU time 2.65 seconds
Started Apr 27 01:49:00 PM PDT 24
Finished Apr 27 01:49:04 PM PDT 24
Peak memory 213940 kb
Host smart-421c2ad4-23a5-4f3b-a9da-230596201e02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630892338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2630892338
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1947211889
Short name T428
Test name
Test status
Simulation time 14493320 ps
CPU time 0.9 seconds
Started Apr 27 01:49:15 PM PDT 24
Finished Apr 27 01:49:17 PM PDT 24
Peak memory 205560 kb
Host smart-19da83d6-e621-4adf-9f20-05c6ee2550fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947211889 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1947211889
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.259849887
Short name T486
Test name
Test status
Simulation time 49856146 ps
CPU time 1.2 seconds
Started Apr 27 01:49:28 PM PDT 24
Finished Apr 27 01:49:29 PM PDT 24
Peak memory 205460 kb
Host smart-ba7bda18-a86e-4aea-b601-711cb1fda964
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259849887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.259849887
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2329722150
Short name T440
Test name
Test status
Simulation time 22217632 ps
CPU time 0.83 seconds
Started Apr 27 01:49:07 PM PDT 24
Finished Apr 27 01:49:09 PM PDT 24
Peak memory 205364 kb
Host smart-218f34e6-6cd0-48e3-9dbf-ddbb1ea0f72f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329722150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2329722150
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.337656594
Short name T506
Test name
Test status
Simulation time 2874456202 ps
CPU time 17.54 seconds
Started Apr 27 01:49:13 PM PDT 24
Finished Apr 27 01:49:32 PM PDT 24
Peak memory 217340 kb
Host smart-dc514f4c-bf8f-4973-957a-4541eaf7a42f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337656594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.337656594
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3755518966
Short name T480
Test name
Test status
Simulation time 330269998 ps
CPU time 4.33 seconds
Started Apr 27 01:49:11 PM PDT 24
Finished Apr 27 01:49:18 PM PDT 24
Peak memory 213984 kb
Host smart-bdfb40f5-90a7-492e-b95f-6d888a184698
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755518966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3755518966
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2444177593
Short name T470
Test name
Test status
Simulation time 372531473 ps
CPU time 3.98 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:16 PM PDT 24
Peak memory 213936 kb
Host smart-2a214c19-d9e6-4653-a2d9-7a19c242f218
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444177593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2444177593
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3132124882
Short name T164
Test name
Test status
Simulation time 113245003 ps
CPU time 3.42 seconds
Started Apr 27 01:49:08 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 209144 kb
Host smart-a6d57c4c-acdf-45b4-9efe-c9aee5624aad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132124882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3132124882
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.1567310596
Short name T432
Test name
Test status
Simulation time 770991003 ps
CPU time 7.43 seconds
Started Apr 27 01:50:03 PM PDT 24
Finished Apr 27 01:50:13 PM PDT 24
Peak memory 205416 kb
Host smart-c1601f37-6a2c-4791-9f61-d00b75129644
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567310596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.1
567310596
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.4154281149
Short name T495
Test name
Test status
Simulation time 257856364 ps
CPU time 1.35 seconds
Started Apr 27 01:48:58 PM PDT 24
Finished Apr 27 01:49:00 PM PDT 24
Peak memory 205412 kb
Host smart-cee1e3a6-b9bc-4f7b-91b0-5806964aadba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154281149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.4
154281149
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2863721478
Short name T185
Test name
Test status
Simulation time 14607654 ps
CPU time 0.92 seconds
Started Apr 27 01:48:49 PM PDT 24
Finished Apr 27 01:48:51 PM PDT 24
Peak memory 205464 kb
Host smart-60838332-26bd-4851-943b-2aa50c3c6aa4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863721478 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2863721478
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3246446396
Short name T541
Test name
Test status
Simulation time 23900986 ps
CPU time 1.49 seconds
Started Apr 27 01:48:49 PM PDT 24
Finished Apr 27 01:48:52 PM PDT 24
Peak memory 205540 kb
Host smart-c536d1f4-1c4a-4353-ac11-69e27432f111
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246446396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3246446396
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.72808859
Short name T511
Test name
Test status
Simulation time 13121155 ps
CPU time 0.86 seconds
Started Apr 27 01:49:05 PM PDT 24
Finished Apr 27 01:49:07 PM PDT 24
Peak memory 205452 kb
Host smart-30055241-b09e-4e5c-88c0-1c4963b21563
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72808859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.72808859
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1685143313
Short name T118
Test name
Test status
Simulation time 6241001800 ps
CPU time 12.88 seconds
Started Apr 27 01:49:05 PM PDT 24
Finished Apr 27 01:49:18 PM PDT 24
Peak memory 213948 kb
Host smart-836972cd-7bfe-4a6c-be5c-fbab317eed36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685143313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1685143313
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1904476518
Short name T536
Test name
Test status
Simulation time 845051937 ps
CPU time 8.99 seconds
Started Apr 27 01:49:54 PM PDT 24
Finished Apr 27 01:50:03 PM PDT 24
Peak memory 213768 kb
Host smart-7e761fd6-b9fc-42d7-973b-c999cfe40c0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904476518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1904476518
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1947337396
Short name T487
Test name
Test status
Simulation time 458371011 ps
CPU time 4.44 seconds
Started Apr 27 01:48:55 PM PDT 24
Finished Apr 27 01:49:01 PM PDT 24
Peak memory 213928 kb
Host smart-a5911148-a997-402b-a925-7893d6f34769
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947337396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1947337396
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3554072486
Short name T447
Test name
Test status
Simulation time 38122975 ps
CPU time 0.83 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:13 PM PDT 24
Peak memory 205424 kb
Host smart-f32dcb0b-128d-4bba-b0a3-38b8aae83be4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554072486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3554072486
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1521669866
Short name T471
Test name
Test status
Simulation time 87860805 ps
CPU time 0.7 seconds
Started Apr 27 01:49:05 PM PDT 24
Finished Apr 27 01:49:06 PM PDT 24
Peak memory 205428 kb
Host smart-fb6e3830-61dc-49c4-8290-adb2361c3ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521669866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1521669866
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3292631191
Short name T496
Test name
Test status
Simulation time 28932439 ps
CPU time 0.82 seconds
Started Apr 27 01:49:26 PM PDT 24
Finished Apr 27 01:49:27 PM PDT 24
Peak memory 205472 kb
Host smart-ec5997a2-7f94-4bb6-94fb-003f1ff57aff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292631191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3292631191
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2080650377
Short name T491
Test name
Test status
Simulation time 13425233 ps
CPU time 0.71 seconds
Started Apr 27 01:49:06 PM PDT 24
Finished Apr 27 01:49:08 PM PDT 24
Peak memory 205440 kb
Host smart-0773f213-d54c-4c69-8580-45c5792ab68f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080650377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2080650377
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1685335446
Short name T528
Test name
Test status
Simulation time 73596572 ps
CPU time 0.72 seconds
Started Apr 27 01:49:14 PM PDT 24
Finished Apr 27 01:49:15 PM PDT 24
Peak memory 205324 kb
Host smart-79f75bda-0a64-4e9b-b901-18f7518d2e07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685335446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1685335446
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2060008205
Short name T517
Test name
Test status
Simulation time 17598905 ps
CPU time 0.71 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:12 PM PDT 24
Peak memory 205468 kb
Host smart-2b979546-f724-4c9f-971e-18840c767c21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060008205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2060008205
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.4117206077
Short name T453
Test name
Test status
Simulation time 29499059 ps
CPU time 0.73 seconds
Started Apr 27 01:49:21 PM PDT 24
Finished Apr 27 01:49:22 PM PDT 24
Peak memory 205400 kb
Host smart-a31faac2-5b15-41a7-a639-c2ac1df583b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117206077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.4117206077
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1802872966
Short name T445
Test name
Test status
Simulation time 39022704 ps
CPU time 0.87 seconds
Started Apr 27 01:49:16 PM PDT 24
Finished Apr 27 01:49:18 PM PDT 24
Peak memory 205456 kb
Host smart-1b11a13c-6385-4883-bd7c-0a71c2f2c1dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802872966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1802872966
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.3281081615
Short name T418
Test name
Test status
Simulation time 7181705 ps
CPU time 0.83 seconds
Started Apr 27 01:49:25 PM PDT 24
Finished Apr 27 01:49:26 PM PDT 24
Peak memory 205456 kb
Host smart-044c53bf-4761-4008-aaf4-66e2b3d1692f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281081615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3281081615
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.386415616
Short name T513
Test name
Test status
Simulation time 8807581 ps
CPU time 0.66 seconds
Started Apr 27 01:49:16 PM PDT 24
Finished Apr 27 01:49:18 PM PDT 24
Peak memory 205460 kb
Host smart-fd09daa5-4ac3-4790-9f47-69fef9238244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386415616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.386415616
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2823909677
Short name T544
Test name
Test status
Simulation time 26089608 ps
CPU time 1.43 seconds
Started Apr 27 01:49:10 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 205520 kb
Host smart-1af8723d-8928-4c48-9828-2f2826c2f3f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823909677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
823909677
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3327915068
Short name T499
Test name
Test status
Simulation time 22655446 ps
CPU time 1.06 seconds
Started Apr 27 01:48:53 PM PDT 24
Finished Apr 27 01:48:55 PM PDT 24
Peak memory 205692 kb
Host smart-519e5619-b23c-42d3-9e04-c35f28027ceb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327915068 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3327915068
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.344655001
Short name T192
Test name
Test status
Simulation time 29573246 ps
CPU time 0.87 seconds
Started Apr 27 01:48:54 PM PDT 24
Finished Apr 27 01:48:56 PM PDT 24
Peak memory 205324 kb
Host smart-2d4eb298-4af6-43b3-9b30-ecfd8d0b5a96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344655001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.344655001
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2821868893
Short name T525
Test name
Test status
Simulation time 37104425 ps
CPU time 0.71 seconds
Started Apr 27 01:49:10 PM PDT 24
Finished Apr 27 01:49:13 PM PDT 24
Peak memory 205412 kb
Host smart-9b63617d-4bc7-404b-a1a1-331077597526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821868893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2821868893
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3888355434
Short name T446
Test name
Test status
Simulation time 140480720 ps
CPU time 2.43 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 213760 kb
Host smart-75014e99-a2af-4f9b-8585-9728c219fd13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888355434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3888355434
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3204429299
Short name T180
Test name
Test status
Simulation time 236068144 ps
CPU time 6.5 seconds
Started Apr 27 01:48:48 PM PDT 24
Finished Apr 27 01:48:56 PM PDT 24
Peak memory 214016 kb
Host smart-7c6856fc-6838-4f5a-8244-9d38606ec011
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204429299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3204429299
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2507977810
Short name T518
Test name
Test status
Simulation time 352123734 ps
CPU time 9.58 seconds
Started Apr 27 01:48:48 PM PDT 24
Finished Apr 27 01:48:59 PM PDT 24
Peak memory 220132 kb
Host smart-48785e5d-6711-4fbf-b0ac-2d4b03a7865b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507977810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2507977810
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2884769175
Short name T476
Test name
Test status
Simulation time 104236344 ps
CPU time 2.64 seconds
Started Apr 27 01:48:52 PM PDT 24
Finished Apr 27 01:48:55 PM PDT 24
Peak memory 216088 kb
Host smart-a59ad18d-c466-4778-ab0f-f69824ac5381
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884769175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2884769175
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.594661903
Short name T175
Test name
Test status
Simulation time 266434597 ps
CPU time 6.11 seconds
Started Apr 27 01:48:55 PM PDT 24
Finished Apr 27 01:49:03 PM PDT 24
Peak memory 208716 kb
Host smart-57e7aff2-60b3-464a-a8b0-bab1caa8341c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594661903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
594661903
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.4074461833
Short name T524
Test name
Test status
Simulation time 8094591 ps
CPU time 0.78 seconds
Started Apr 27 01:49:20 PM PDT 24
Finished Apr 27 01:49:21 PM PDT 24
Peak memory 205436 kb
Host smart-a116a30f-9728-48f7-9e4a-4a53f568d078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074461833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.4074461833
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3942889368
Short name T468
Test name
Test status
Simulation time 20557363 ps
CPU time 0.82 seconds
Started Apr 27 01:49:13 PM PDT 24
Finished Apr 27 01:49:15 PM PDT 24
Peak memory 205368 kb
Host smart-49efdcac-8a6a-4924-80c3-b498497ad02c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942889368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3942889368
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2669024354
Short name T141
Test name
Test status
Simulation time 15217190 ps
CPU time 0.67 seconds
Started Apr 27 01:49:11 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 205344 kb
Host smart-2d7c83fd-3472-4b26-9f72-898647f7b8bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669024354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2669024354
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3740182143
Short name T194
Test name
Test status
Simulation time 19811258 ps
CPU time 0.89 seconds
Started Apr 27 01:49:17 PM PDT 24
Finished Apr 27 01:49:18 PM PDT 24
Peak memory 205412 kb
Host smart-77b82d19-d62f-4090-a6db-1b40d71360a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740182143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3740182143
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.533004200
Short name T443
Test name
Test status
Simulation time 17052157 ps
CPU time 0.73 seconds
Started Apr 27 01:49:11 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 205432 kb
Host smart-e691e3c5-5189-4be2-8127-7a22e61d4429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533004200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.533004200
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.396135093
Short name T534
Test name
Test status
Simulation time 33099701 ps
CPU time 0.7 seconds
Started Apr 27 01:49:11 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 205328 kb
Host smart-7881dca6-8d80-4ace-beb3-0235a04cd8fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396135093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.396135093
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.597146307
Short name T523
Test name
Test status
Simulation time 16662872 ps
CPU time 0.83 seconds
Started Apr 27 01:49:10 PM PDT 24
Finished Apr 27 01:49:13 PM PDT 24
Peak memory 205396 kb
Host smart-d18da79d-6f9b-4acf-9d52-950ac8142bac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597146307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.597146307
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.763826283
Short name T485
Test name
Test status
Simulation time 42983050 ps
CPU time 0.82 seconds
Started Apr 27 01:49:49 PM PDT 24
Finished Apr 27 01:49:52 PM PDT 24
Peak memory 205424 kb
Host smart-581ce4fe-ad3a-4d98-b492-1578f0f6de76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763826283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.763826283
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1625432468
Short name T512
Test name
Test status
Simulation time 34740288 ps
CPU time 0.71 seconds
Started Apr 27 01:49:08 PM PDT 24
Finished Apr 27 01:49:11 PM PDT 24
Peak memory 205448 kb
Host smart-9593918c-eb22-4322-a299-f66310873c55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625432468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1625432468
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.349874374
Short name T484
Test name
Test status
Simulation time 11792276 ps
CPU time 0.85 seconds
Started Apr 27 01:49:10 PM PDT 24
Finished Apr 27 01:49:13 PM PDT 24
Peak memory 205412 kb
Host smart-200ba73b-1c92-4ddc-9aaa-c96c6a3251b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349874374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.349874374
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1186491935
Short name T183
Test name
Test status
Simulation time 8683730816 ps
CPU time 17.2 seconds
Started Apr 27 01:48:57 PM PDT 24
Finished Apr 27 01:49:15 PM PDT 24
Peak memory 205468 kb
Host smart-7d07614c-ffd3-43df-9576-d165fb6e19ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186491935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
186491935
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3797662699
Short name T433
Test name
Test status
Simulation time 94502352 ps
CPU time 1.31 seconds
Started Apr 27 01:49:02 PM PDT 24
Finished Apr 27 01:49:04 PM PDT 24
Peak memory 205356 kb
Host smart-c8a7e931-13ba-4844-bcb6-e1619e9dfe3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797662699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
797662699
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1385692229
Short name T469
Test name
Test status
Simulation time 22203512 ps
CPU time 1.66 seconds
Started Apr 27 01:48:50 PM PDT 24
Finished Apr 27 01:48:53 PM PDT 24
Peak memory 213868 kb
Host smart-0cc8d72d-b131-4de4-8fbb-2286e5c64b7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385692229 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1385692229
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.4064337786
Short name T474
Test name
Test status
Simulation time 28520032 ps
CPU time 1.06 seconds
Started Apr 27 01:49:05 PM PDT 24
Finished Apr 27 01:49:07 PM PDT 24
Peak memory 205508 kb
Host smart-299b66c0-dc2e-4a8f-a82e-ab8a67150b94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064337786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.4064337786
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3659084804
Short name T461
Test name
Test status
Simulation time 41455241 ps
CPU time 0.76 seconds
Started Apr 27 01:48:55 PM PDT 24
Finished Apr 27 01:48:58 PM PDT 24
Peak memory 205452 kb
Host smart-2e64b53c-6ec1-4e35-a83f-5a241635cbaa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659084804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3659084804
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4194346886
Short name T467
Test name
Test status
Simulation time 350680429 ps
CPU time 1.63 seconds
Started Apr 27 01:49:27 PM PDT 24
Finished Apr 27 01:49:29 PM PDT 24
Peak memory 205436 kb
Host smart-04aa189b-a524-4767-9605-b8090d291fa6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194346886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.4194346886
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1062305716
Short name T120
Test name
Test status
Simulation time 382529024 ps
CPU time 3.25 seconds
Started Apr 27 01:49:21 PM PDT 24
Finished Apr 27 01:49:30 PM PDT 24
Peak memory 222240 kb
Host smart-b0e01b6d-8dd0-4aaf-8f18-4ffceaeecb5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062305716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1062305716
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2280357270
Short name T473
Test name
Test status
Simulation time 199962979 ps
CPU time 4.9 seconds
Started Apr 27 01:48:56 PM PDT 24
Finished Apr 27 01:49:02 PM PDT 24
Peak memory 214048 kb
Host smart-6c31d6ab-1ed5-4523-8034-f9c09b8efb0c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280357270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2280357270
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3991841467
Short name T542
Test name
Test status
Simulation time 302691562 ps
CPU time 2.2 seconds
Started Apr 27 01:48:57 PM PDT 24
Finished Apr 27 01:49:00 PM PDT 24
Peak memory 213780 kb
Host smart-eccef30a-d37a-4b11-a430-4f9b485c547d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991841467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3991841467
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.20048074
Short name T372
Test name
Test status
Simulation time 1086151531 ps
CPU time 8.24 seconds
Started Apr 27 01:48:54 PM PDT 24
Finished Apr 27 01:49:04 PM PDT 24
Peak memory 213848 kb
Host smart-0ad8d889-8d8a-4955-a155-9b36b22fe9ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20048074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.20048074
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1241216667
Short name T456
Test name
Test status
Simulation time 20593085 ps
CPU time 0.77 seconds
Started Apr 27 01:49:22 PM PDT 24
Finished Apr 27 01:49:23 PM PDT 24
Peak memory 205472 kb
Host smart-53ae168b-90aa-43af-adfc-c41417d9999e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241216667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1241216667
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.631968420
Short name T419
Test name
Test status
Simulation time 38697632 ps
CPU time 0.67 seconds
Started Apr 27 01:49:15 PM PDT 24
Finished Apr 27 01:49:17 PM PDT 24
Peak memory 205472 kb
Host smart-2584476a-def1-450f-90c2-6f3a5c3be31e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631968420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.631968420
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.306091823
Short name T489
Test name
Test status
Simulation time 17386424 ps
CPU time 0.83 seconds
Started Apr 27 01:49:18 PM PDT 24
Finished Apr 27 01:49:20 PM PDT 24
Peak memory 205416 kb
Host smart-4e001c6a-80a4-41de-a88b-6eee338b9703
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306091823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.306091823
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.906338943
Short name T507
Test name
Test status
Simulation time 55865807 ps
CPU time 0.85 seconds
Started Apr 27 01:49:08 PM PDT 24
Finished Apr 27 01:49:12 PM PDT 24
Peak memory 205336 kb
Host smart-36899b4d-bb0c-437a-a17c-903da9301cce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906338943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.906338943
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.4017050883
Short name T439
Test name
Test status
Simulation time 21024361 ps
CPU time 0.81 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:12 PM PDT 24
Peak memory 205332 kb
Host smart-7222debb-efa3-4216-addd-6d7c2dc452ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017050883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.4017050883
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1113688472
Short name T502
Test name
Test status
Simulation time 12342043 ps
CPU time 0.72 seconds
Started Apr 27 01:49:40 PM PDT 24
Finished Apr 27 01:49:41 PM PDT 24
Peak memory 205396 kb
Host smart-9fb08d91-424e-4f2a-a8ed-8c2d818db427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113688472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1113688472
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1402039266
Short name T514
Test name
Test status
Simulation time 34757727 ps
CPU time 0.68 seconds
Started Apr 27 01:49:15 PM PDT 24
Finished Apr 27 01:49:17 PM PDT 24
Peak memory 205292 kb
Host smart-bf1ad32f-25c3-42cb-8093-f99fce381584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402039266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1402039266
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3372900014
Short name T424
Test name
Test status
Simulation time 131420934 ps
CPU time 0.68 seconds
Started Apr 27 01:49:08 PM PDT 24
Finished Apr 27 01:49:12 PM PDT 24
Peak memory 205404 kb
Host smart-6fe80570-aa6a-4e02-a0cf-e19cf5fb7438
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372900014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3372900014
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2354517124
Short name T493
Test name
Test status
Simulation time 16408054 ps
CPU time 0.81 seconds
Started Apr 27 01:49:08 PM PDT 24
Finished Apr 27 01:49:12 PM PDT 24
Peak memory 205460 kb
Host smart-92f2db10-2ef9-4e63-9845-7c38cbd5b291
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354517124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2354517124
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2971850466
Short name T193
Test name
Test status
Simulation time 30418975 ps
CPU time 0.92 seconds
Started Apr 27 01:49:27 PM PDT 24
Finished Apr 27 01:49:28 PM PDT 24
Peak memory 205460 kb
Host smart-c893c84a-d258-49b4-a95a-1fcd63d76259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971850466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2971850466
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3916606165
Short name T449
Test name
Test status
Simulation time 115186675 ps
CPU time 1.32 seconds
Started Apr 27 01:49:06 PM PDT 24
Finished Apr 27 01:49:08 PM PDT 24
Peak memory 213788 kb
Host smart-304dc5ee-9077-4ec9-a9fc-6bb0d18ce9c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916606165 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3916606165
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3139314292
Short name T463
Test name
Test status
Simulation time 11173920 ps
CPU time 0.86 seconds
Started Apr 27 01:48:56 PM PDT 24
Finished Apr 27 01:48:58 PM PDT 24
Peak memory 205452 kb
Host smart-09b87c20-0e6e-490f-8986-5be53f5e40e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139314292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3139314292
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1533261848
Short name T504
Test name
Test status
Simulation time 148614254 ps
CPU time 2.19 seconds
Started Apr 27 01:48:58 PM PDT 24
Finished Apr 27 01:49:01 PM PDT 24
Peak memory 205620 kb
Host smart-f2b67be1-f028-4bbe-9bfd-dce6cb514728
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533261848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1533261848
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.753997364
Short name T117
Test name
Test status
Simulation time 411043119 ps
CPU time 3.21 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:16 PM PDT 24
Peak memory 214036 kb
Host smart-b64573ae-bc89-4df5-a56d-fcde8f78b19b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753997364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.753997364
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3579073988
Short name T427
Test name
Test status
Simulation time 540754716 ps
CPU time 3.82 seconds
Started Apr 27 01:48:59 PM PDT 24
Finished Apr 27 01:49:03 PM PDT 24
Peak memory 213824 kb
Host smart-a147cf0f-7c28-48d5-b5bd-15c3101e86ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579073988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3579073988
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.219622782
Short name T161
Test name
Test status
Simulation time 489631335 ps
CPU time 11.57 seconds
Started Apr 27 01:49:04 PM PDT 24
Finished Apr 27 01:49:16 PM PDT 24
Peak memory 208780 kb
Host smart-0e2caf4b-f0b0-4aa3-8bd3-c207cb957b7f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219622782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
219622782
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3942178552
Short name T498
Test name
Test status
Simulation time 70792482 ps
CPU time 2.05 seconds
Started Apr 27 01:49:12 PM PDT 24
Finished Apr 27 01:49:16 PM PDT 24
Peak memory 213796 kb
Host smart-8ed65b8f-827f-468f-9aa2-00fc1f4abe1e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942178552 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3942178552
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4116800267
Short name T515
Test name
Test status
Simulation time 32029148 ps
CPU time 0.85 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:13 PM PDT 24
Peak memory 205416 kb
Host smart-e7db03f3-b4a6-46c7-9ad6-e1e9f2c84adb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116800267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.4116800267
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3218572623
Short name T429
Test name
Test status
Simulation time 14408239 ps
CPU time 0.9 seconds
Started Apr 27 01:49:06 PM PDT 24
Finished Apr 27 01:49:08 PM PDT 24
Peak memory 205444 kb
Host smart-38803e1f-217b-4650-8071-21470384ecb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218572623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3218572623
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3947397380
Short name T462
Test name
Test status
Simulation time 104166718 ps
CPU time 1.99 seconds
Started Apr 27 01:49:10 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 205548 kb
Host smart-5a2cc856-3df3-4d31-8de3-897cbda83112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947397380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3947397380
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2789736748
Short name T478
Test name
Test status
Simulation time 697308684 ps
CPU time 5.09 seconds
Started Apr 27 01:49:08 PM PDT 24
Finished Apr 27 01:49:16 PM PDT 24
Peak memory 214016 kb
Host smart-6254670c-0263-4f9b-a312-071487c0c9b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789736748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2789736748
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3219424929
Short name T451
Test name
Test status
Simulation time 252346091 ps
CPU time 8.09 seconds
Started Apr 27 01:49:09 PM PDT 24
Finished Apr 27 01:49:20 PM PDT 24
Peak memory 214000 kb
Host smart-e7ac0635-64cb-4db1-b1b9-a8ae125e6951
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219424929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3219424929
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2487855049
Short name T436
Test name
Test status
Simulation time 280321290 ps
CPU time 1.65 seconds
Started Apr 27 01:49:08 PM PDT 24
Finished Apr 27 01:49:11 PM PDT 24
Peak memory 213972 kb
Host smart-70830e16-6768-493f-a612-b0693e9ba04e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487855049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2487855049
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2640761645
Short name T177
Test name
Test status
Simulation time 153193789 ps
CPU time 3.49 seconds
Started Apr 27 01:48:54 PM PDT 24
Finished Apr 27 01:48:59 PM PDT 24
Peak memory 209172 kb
Host smart-e6af9046-407c-4265-8b08-131dfa84c313
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640761645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2640761645
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.728003392
Short name T128
Test name
Test status
Simulation time 61990758 ps
CPU time 2.27 seconds
Started Apr 27 01:48:56 PM PDT 24
Finished Apr 27 01:48:59 PM PDT 24
Peak memory 219560 kb
Host smart-564dba56-3182-463b-b7de-fd318286d99c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728003392 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.728003392
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1160892158
Short name T421
Test name
Test status
Simulation time 89193591 ps
CPU time 1.1 seconds
Started Apr 27 01:49:20 PM PDT 24
Finished Apr 27 01:49:22 PM PDT 24
Peak memory 205456 kb
Host smart-4205a807-4a6e-4554-ae8f-f87b3231323e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160892158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1160892158
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3809284002
Short name T472
Test name
Test status
Simulation time 13338325 ps
CPU time 0.89 seconds
Started Apr 27 01:49:06 PM PDT 24
Finished Apr 27 01:49:07 PM PDT 24
Peak memory 205448 kb
Host smart-f5547df5-708b-4a5a-80fe-e877620457af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809284002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3809284002
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.319118198
Short name T466
Test name
Test status
Simulation time 126436616 ps
CPU time 2.28 seconds
Started Apr 27 01:49:10 PM PDT 24
Finished Apr 27 01:49:15 PM PDT 24
Peak memory 213808 kb
Host smart-800fba54-88b2-4f70-bf56-edaa114fb1aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319118198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.319118198
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1251263331
Short name T195
Test name
Test status
Simulation time 1343636914 ps
CPU time 7.21 seconds
Started Apr 27 01:48:55 PM PDT 24
Finished Apr 27 01:49:04 PM PDT 24
Peak memory 222124 kb
Host smart-97c89926-b975-43fb-b159-03bf12785849
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251263331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1251263331
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2077555513
Short name T138
Test name
Test status
Simulation time 155345402 ps
CPU time 2.54 seconds
Started Apr 27 01:48:50 PM PDT 24
Finished Apr 27 01:48:54 PM PDT 24
Peak memory 222008 kb
Host smart-3c6d4bb3-bd98-414d-8006-69edb3153fd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077555513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2077555513
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2295490598
Short name T521
Test name
Test status
Simulation time 17468718 ps
CPU time 0.94 seconds
Started Apr 27 01:49:16 PM PDT 24
Finished Apr 27 01:49:18 PM PDT 24
Peak memory 205540 kb
Host smart-e0b05d7d-b897-4670-bcbd-8b0ba186b4d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295490598 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2295490598
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2807925550
Short name T136
Test name
Test status
Simulation time 53264491 ps
CPU time 1.11 seconds
Started Apr 27 01:49:15 PM PDT 24
Finished Apr 27 01:49:17 PM PDT 24
Peak memory 205520 kb
Host smart-9efde499-0441-40bb-9994-56f19924bd45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807925550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2807925550
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1234498377
Short name T142
Test name
Test status
Simulation time 25171501 ps
CPU time 0.7 seconds
Started Apr 27 01:49:04 PM PDT 24
Finished Apr 27 01:49:05 PM PDT 24
Peak memory 205376 kb
Host smart-fdc92b28-b7d8-4c27-83f7-18e2ba6a27e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234498377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1234498377
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3381704526
Short name T115
Test name
Test status
Simulation time 457300898 ps
CPU time 3.3 seconds
Started Apr 27 01:49:07 PM PDT 24
Finished Apr 27 01:49:12 PM PDT 24
Peak memory 214012 kb
Host smart-6f3daae5-04c9-4d6f-a05c-65d9fb7c09c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381704526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3381704526
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2625539774
Short name T174
Test name
Test status
Simulation time 250186822 ps
CPU time 3.61 seconds
Started Apr 27 01:48:56 PM PDT 24
Finished Apr 27 01:49:01 PM PDT 24
Peak memory 213868 kb
Host smart-ba563846-634c-4f83-b83a-2b3d49858f2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625539774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2625539774
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.973726628
Short name T184
Test name
Test status
Simulation time 56677994 ps
CPU time 1.63 seconds
Started Apr 27 01:48:58 PM PDT 24
Finished Apr 27 01:49:00 PM PDT 24
Peak memory 213884 kb
Host smart-d8b9a34a-df54-4ae0-8b3c-4779e0b1f20e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973726628 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.973726628
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3389931607
Short name T452
Test name
Test status
Simulation time 28941036 ps
CPU time 1.27 seconds
Started Apr 27 01:49:39 PM PDT 24
Finished Apr 27 01:49:41 PM PDT 24
Peak memory 205392 kb
Host smart-bb8522a5-3511-4f07-a9ca-344acb1149c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389931607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3389931607
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1500027605
Short name T475
Test name
Test status
Simulation time 11100078 ps
CPU time 0.84 seconds
Started Apr 27 01:49:10 PM PDT 24
Finished Apr 27 01:49:14 PM PDT 24
Peak memory 205404 kb
Host smart-46379397-2888-46d8-acda-b09a19964978
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500027605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1500027605
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3152774723
Short name T121
Test name
Test status
Simulation time 2046199177 ps
CPU time 31.42 seconds
Started Apr 27 01:49:17 PM PDT 24
Finished Apr 27 01:49:49 PM PDT 24
Peak memory 218152 kb
Host smart-6913f35a-e8df-49b3-961b-ff2739bbada9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152774723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3152774723
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1826090455
Short name T500
Test name
Test status
Simulation time 98134107 ps
CPU time 5.22 seconds
Started Apr 27 01:48:57 PM PDT 24
Finished Apr 27 01:49:03 PM PDT 24
Peak memory 213996 kb
Host smart-53884cf3-82d4-4e8f-9bc8-2d69892f7407
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826090455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1826090455
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3097647073
Short name T519
Test name
Test status
Simulation time 88186999 ps
CPU time 2.56 seconds
Started Apr 27 01:49:07 PM PDT 24
Finished Apr 27 01:49:11 PM PDT 24
Peak memory 213804 kb
Host smart-c1a76266-7239-4357-b171-b9949f17960f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097647073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3097647073
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2066249765
Short name T167
Test name
Test status
Simulation time 484287973 ps
CPU time 3.37 seconds
Started Apr 27 01:49:10 PM PDT 24
Finished Apr 27 01:49:16 PM PDT 24
Peak memory 209144 kb
Host smart-b1ad47a2-4617-4511-bb25-34ce8443c9f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066249765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2066249765
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.101876823
Short name T891
Test name
Test status
Simulation time 10551535 ps
CPU time 0.7 seconds
Started Apr 27 04:08:38 PM PDT 24
Finished Apr 27 04:08:39 PM PDT 24
Peak memory 205808 kb
Host smart-73d95218-dee8-4406-8fa5-dbfa050806df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101876823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.101876823
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3297094709
Short name T931
Test name
Test status
Simulation time 208434914 ps
CPU time 4.2 seconds
Started Apr 27 04:08:29 PM PDT 24
Finished Apr 27 04:08:33 PM PDT 24
Peak memory 210152 kb
Host smart-d98a0eca-d900-49c5-8a2a-b146d59b02d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297094709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3297094709
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.575817726
Short name T772
Test name
Test status
Simulation time 1360082385 ps
CPU time 4.83 seconds
Started Apr 27 04:08:33 PM PDT 24
Finished Apr 27 04:08:38 PM PDT 24
Peak memory 214360 kb
Host smart-2069a446-16df-4292-81d3-2e78c4c3b4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575817726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.575817726
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.931509137
Short name T190
Test name
Test status
Simulation time 235665863 ps
CPU time 9.56 seconds
Started Apr 27 04:08:33 PM PDT 24
Finished Apr 27 04:08:43 PM PDT 24
Peak memory 214324 kb
Host smart-a6925846-9755-401a-90b8-689aecba33ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931509137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.931509137
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2674680832
Short name T1042
Test name
Test status
Simulation time 457673850 ps
CPU time 4.53 seconds
Started Apr 27 04:08:36 PM PDT 24
Finished Apr 27 04:08:41 PM PDT 24
Peak memory 209996 kb
Host smart-14dd0a0e-5733-4d75-980b-06e71a95e2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674680832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2674680832
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2193655400
Short name T132
Test name
Test status
Simulation time 90835545 ps
CPU time 4.06 seconds
Started Apr 27 04:08:28 PM PDT 24
Finished Apr 27 04:08:33 PM PDT 24
Peak memory 209976 kb
Host smart-a2532198-e0f8-4793-9d16-262d16095560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193655400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2193655400
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.3942007836
Short name T14
Test name
Test status
Simulation time 10070700070 ps
CPU time 58.22 seconds
Started Apr 27 04:08:38 PM PDT 24
Finished Apr 27 04:09:37 PM PDT 24
Peak memory 237744 kb
Host smart-9f87e42f-a2a6-4b01-a383-6b33e06f2d71
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942007836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.3942007836
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1071650167
Short name T307
Test name
Test status
Simulation time 3529883217 ps
CPU time 43.65 seconds
Started Apr 27 04:08:27 PM PDT 24
Finished Apr 27 04:09:11 PM PDT 24
Peak memory 208868 kb
Host smart-b184045d-2fd1-4353-8f47-d7f396ece7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071650167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1071650167
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3007936946
Short name T834
Test name
Test status
Simulation time 429151070 ps
CPU time 3.65 seconds
Started Apr 27 04:08:35 PM PDT 24
Finished Apr 27 04:08:39 PM PDT 24
Peak memory 206716 kb
Host smart-7ebc700e-ef01-4717-91fd-70be04fcb445
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007936946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3007936946
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3914043623
Short name T130
Test name
Test status
Simulation time 80120925 ps
CPU time 3.61 seconds
Started Apr 27 04:08:27 PM PDT 24
Finished Apr 27 04:08:31 PM PDT 24
Peak memory 208980 kb
Host smart-02d53a67-d87d-4dcf-be52-1f7cf4691b4c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914043623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3914043623
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2248779119
Short name T731
Test name
Test status
Simulation time 333538580 ps
CPU time 4.54 seconds
Started Apr 27 04:08:26 PM PDT 24
Finished Apr 27 04:08:31 PM PDT 24
Peak memory 208600 kb
Host smart-c77d2cb2-a077-46c3-a338-3bbb9e01f526
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248779119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2248779119
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3458267743
Short name T716
Test name
Test status
Simulation time 1280748570 ps
CPU time 3.01 seconds
Started Apr 27 04:08:36 PM PDT 24
Finished Apr 27 04:08:40 PM PDT 24
Peak memory 214180 kb
Host smart-6dc2e03e-1f2f-4434-bc9e-7d7d1ea0c671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458267743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3458267743
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.825336459
Short name T547
Test name
Test status
Simulation time 870512959 ps
CPU time 4.46 seconds
Started Apr 27 04:08:27 PM PDT 24
Finished Apr 27 04:08:32 PM PDT 24
Peak memory 208552 kb
Host smart-cc501ded-22a6-4524-bed7-cb5d694c44eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825336459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.825336459
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3370349401
Short name T74
Test name
Test status
Simulation time 1031363477 ps
CPU time 16.47 seconds
Started Apr 27 04:08:39 PM PDT 24
Finished Apr 27 04:08:55 PM PDT 24
Peak memory 222520 kb
Host smart-8aa43a26-e5fa-480d-9bbb-c0d5d949539c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370349401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3370349401
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2325769166
Short name T729
Test name
Test status
Simulation time 579740318 ps
CPU time 4.11 seconds
Started Apr 27 04:08:39 PM PDT 24
Finished Apr 27 04:08:43 PM PDT 24
Peak memory 219824 kb
Host smart-5250c4b6-84d0-43df-9bbb-da318c65e701
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325769166 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2325769166
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1370667171
Short name T1007
Test name
Test status
Simulation time 346484735 ps
CPU time 9.65 seconds
Started Apr 27 04:08:34 PM PDT 24
Finished Apr 27 04:08:44 PM PDT 24
Peak memory 222404 kb
Host smart-ad16a329-97b4-4cac-be7d-f2de7fe9b9fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370667171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1370667171
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.159673247
Short name T66
Test name
Test status
Simulation time 60438518 ps
CPU time 3.6 seconds
Started Apr 27 04:08:34 PM PDT 24
Finished Apr 27 04:08:38 PM PDT 24
Peak memory 210300 kb
Host smart-1a1c099d-099f-458a-a0c6-9c8d877189e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159673247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.159673247
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1127986981
Short name T717
Test name
Test status
Simulation time 42847495 ps
CPU time 0.84 seconds
Started Apr 27 04:08:59 PM PDT 24
Finished Apr 27 04:09:00 PM PDT 24
Peak memory 205876 kb
Host smart-ee1ae43d-3b8b-43f2-86a8-6f255e70655f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127986981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1127986981
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.3266272601
Short name T837
Test name
Test status
Simulation time 2356213823 ps
CPU time 22.72 seconds
Started Apr 27 04:08:53 PM PDT 24
Finished Apr 27 04:09:16 PM PDT 24
Peak memory 221924 kb
Host smart-121c599f-6099-47d8-a58a-d6d69edfe480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266272601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3266272601
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3305510287
Short name T108
Test name
Test status
Simulation time 211302602 ps
CPU time 4.52 seconds
Started Apr 27 04:08:44 PM PDT 24
Finished Apr 27 04:08:49 PM PDT 24
Peak memory 209508 kb
Host smart-9c6fa442-27d9-458a-944c-04d6aeca6ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305510287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3305510287
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1528429775
Short name T237
Test name
Test status
Simulation time 572253799 ps
CPU time 6.35 seconds
Started Apr 27 04:08:46 PM PDT 24
Finished Apr 27 04:08:52 PM PDT 24
Peak memory 208928 kb
Host smart-4fb05973-0abd-40bf-9d45-b3c755474af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528429775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1528429775
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1927459460
Short name T743
Test name
Test status
Simulation time 351934785 ps
CPU time 11.32 seconds
Started Apr 27 04:08:44 PM PDT 24
Finished Apr 27 04:08:56 PM PDT 24
Peak memory 222456 kb
Host smart-f83d3829-76ba-4aeb-acf9-df72c2e03228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927459460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1927459460
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2595659844
Short name T1018
Test name
Test status
Simulation time 153871000 ps
CPU time 4.16 seconds
Started Apr 27 04:08:46 PM PDT 24
Finished Apr 27 04:08:50 PM PDT 24
Peak memory 218288 kb
Host smart-4b4f52ef-4165-4169-9442-32b660581eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595659844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2595659844
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1420983219
Short name T961
Test name
Test status
Simulation time 103083599 ps
CPU time 5.28 seconds
Started Apr 27 04:08:44 PM PDT 24
Finished Apr 27 04:08:50 PM PDT 24
Peak memory 209072 kb
Host smart-dd476d4b-6f91-462f-9a8f-c149474fcf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420983219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1420983219
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2428816809
Short name T978
Test name
Test status
Simulation time 106966542 ps
CPU time 2.88 seconds
Started Apr 27 04:08:37 PM PDT 24
Finished Apr 27 04:08:40 PM PDT 24
Peak memory 208488 kb
Host smart-e65a81a0-3e2a-4ed9-a658-b54e0e57fa7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428816809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2428816809
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3808578522
Short name T920
Test name
Test status
Simulation time 739919346 ps
CPU time 3.82 seconds
Started Apr 27 04:08:37 PM PDT 24
Finished Apr 27 04:08:41 PM PDT 24
Peak memory 208424 kb
Host smart-ef7b2475-396d-4535-b4ef-69e78b39ee14
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808578522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3808578522
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.4255576231
Short name T234
Test name
Test status
Simulation time 3355682260 ps
CPU time 34.31 seconds
Started Apr 27 04:08:39 PM PDT 24
Finished Apr 27 04:09:14 PM PDT 24
Peak memory 209000 kb
Host smart-14b3a67c-ced2-4a33-8cd3-d02148dc81ad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255576231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.4255576231
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1688821590
Short name T684
Test name
Test status
Simulation time 70972921 ps
CPU time 3.15 seconds
Started Apr 27 04:08:48 PM PDT 24
Finished Apr 27 04:08:51 PM PDT 24
Peak memory 206880 kb
Host smart-b8db8512-06e8-4f69-9924-67f6078a4d68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688821590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1688821590
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1759102837
Short name T289
Test name
Test status
Simulation time 104718843 ps
CPU time 2.17 seconds
Started Apr 27 04:08:52 PM PDT 24
Finished Apr 27 04:08:54 PM PDT 24
Peak memory 215348 kb
Host smart-e6836aa9-ac46-4cbb-abf7-9812c5f3a744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759102837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1759102837
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2374513288
Short name T412
Test name
Test status
Simulation time 385612114 ps
CPU time 3.89 seconds
Started Apr 27 04:08:38 PM PDT 24
Finished Apr 27 04:08:42 PM PDT 24
Peak memory 207012 kb
Host smart-65f2d55f-3c76-4b10-8476-f707b5651029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374513288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2374513288
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3300524179
Short name T737
Test name
Test status
Simulation time 3879191954 ps
CPU time 38.54 seconds
Started Apr 27 04:08:51 PM PDT 24
Finished Apr 27 04:09:30 PM PDT 24
Peak memory 215724 kb
Host smart-98ca1685-fb64-4424-a146-e22fabb005ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300524179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3300524179
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2648792521
Short name T935
Test name
Test status
Simulation time 754119272 ps
CPU time 15.92 seconds
Started Apr 27 04:08:51 PM PDT 24
Finished Apr 27 04:09:08 PM PDT 24
Peak memory 222680 kb
Host smart-5386ce80-b164-462d-b8a4-79dd3ddccd5e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648792521 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2648792521
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2654582128
Short name T745
Test name
Test status
Simulation time 179832010 ps
CPU time 5.95 seconds
Started Apr 27 04:08:45 PM PDT 24
Finished Apr 27 04:08:51 PM PDT 24
Peak memory 210496 kb
Host smart-74390f1c-9cbd-45e7-acd4-fcd9319364b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654582128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2654582128
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3523400814
Short name T818
Test name
Test status
Simulation time 79182180 ps
CPU time 1.44 seconds
Started Apr 27 04:08:52 PM PDT 24
Finished Apr 27 04:08:54 PM PDT 24
Peak memory 209872 kb
Host smart-62f242c0-816f-4302-9d1d-b0d17651cff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523400814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3523400814
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1641789034
Short name T551
Test name
Test status
Simulation time 16631509 ps
CPU time 0.8 seconds
Started Apr 27 04:10:03 PM PDT 24
Finished Apr 27 04:10:04 PM PDT 24
Peak memory 205868 kb
Host smart-f406c743-6c27-4647-a56a-1eac1a6ef70e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641789034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1641789034
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.257869309
Short name T321
Test name
Test status
Simulation time 997935430 ps
CPU time 8.08 seconds
Started Apr 27 04:09:56 PM PDT 24
Finished Apr 27 04:10:04 PM PDT 24
Peak memory 215184 kb
Host smart-3387a95a-25e6-4a9a-bcc1-87970e48ca49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=257869309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.257869309
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.385353990
Short name T852
Test name
Test status
Simulation time 115282164 ps
CPU time 2.38 seconds
Started Apr 27 04:09:58 PM PDT 24
Finished Apr 27 04:10:01 PM PDT 24
Peak memory 209820 kb
Host smart-c8e9b8be-84a5-439f-8542-4d0adcd13dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385353990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.385353990
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2625830424
Short name T2
Test name
Test status
Simulation time 44539834 ps
CPU time 2.4 seconds
Started Apr 27 04:09:55 PM PDT 24
Finished Apr 27 04:09:57 PM PDT 24
Peak memory 209220 kb
Host smart-af98724c-1f49-43be-8771-1fcb42c2747e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625830424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2625830424
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.984280664
Short name T824
Test name
Test status
Simulation time 201104494 ps
CPU time 4.59 seconds
Started Apr 27 04:09:59 PM PDT 24
Finished Apr 27 04:10:04 PM PDT 24
Peak memory 208480 kb
Host smart-5eea6184-7804-45e5-a421-93f394483ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984280664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.984280664
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1624791890
Short name T353
Test name
Test status
Simulation time 1426267352 ps
CPU time 13.98 seconds
Started Apr 27 04:09:56 PM PDT 24
Finished Apr 27 04:10:10 PM PDT 24
Peak memory 211936 kb
Host smart-56d45f5b-9d81-49ce-8dea-a085fbf32d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624791890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1624791890
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_random.3501942511
Short name T273
Test name
Test status
Simulation time 1888277898 ps
CPU time 24.81 seconds
Started Apr 27 04:09:57 PM PDT 24
Finished Apr 27 04:10:23 PM PDT 24
Peak memory 208400 kb
Host smart-c1931499-1ed9-49bd-8e97-84c7542c5f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501942511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3501942511
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.786746540
Short name T742
Test name
Test status
Simulation time 1112093506 ps
CPU time 11.82 seconds
Started Apr 27 04:09:50 PM PDT 24
Finished Apr 27 04:10:02 PM PDT 24
Peak memory 207080 kb
Host smart-3e785af8-ff06-4c9e-83f1-36cac1c0356f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786746540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.786746540
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.148522868
Short name T952
Test name
Test status
Simulation time 211643468 ps
CPU time 4.77 seconds
Started Apr 27 04:09:57 PM PDT 24
Finished Apr 27 04:10:02 PM PDT 24
Peak memory 208596 kb
Host smart-3c295101-4356-4c49-a91d-0e149b179153
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148522868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.148522868
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.4110048784
Short name T609
Test name
Test status
Simulation time 533708611 ps
CPU time 3.82 seconds
Started Apr 27 04:09:57 PM PDT 24
Finished Apr 27 04:10:02 PM PDT 24
Peak memory 208656 kb
Host smart-468d1486-5427-4d7a-ba72-de9ea1e3256e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110048784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.4110048784
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.858062886
Short name T635
Test name
Test status
Simulation time 61379353 ps
CPU time 2.42 seconds
Started Apr 27 04:10:01 PM PDT 24
Finished Apr 27 04:10:04 PM PDT 24
Peak memory 206832 kb
Host smart-62968945-2372-4284-a2c7-421a4c4d327b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858062886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.858062886
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1441780887
Short name T1002
Test name
Test status
Simulation time 24731338 ps
CPU time 1.87 seconds
Started Apr 27 04:09:51 PM PDT 24
Finished Apr 27 04:09:54 PM PDT 24
Peak memory 206856 kb
Host smart-cbe560c8-b80c-420f-a9f4-63b320cea053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441780887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1441780887
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2963215896
Short name T122
Test name
Test status
Simulation time 636013544 ps
CPU time 11.38 seconds
Started Apr 27 04:09:58 PM PDT 24
Finished Apr 27 04:10:09 PM PDT 24
Peak memory 222640 kb
Host smart-f0143b37-6133-4112-b634-d2e05ad93b8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963215896 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2963215896
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.1243881272
Short name T726
Test name
Test status
Simulation time 178351103 ps
CPU time 6.08 seconds
Started Apr 27 04:09:59 PM PDT 24
Finished Apr 27 04:10:05 PM PDT 24
Peak memory 207976 kb
Host smart-c413eb80-1c71-4b51-a838-b5e3a9556f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243881272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.1243881272
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3399296818
Short name T1014
Test name
Test status
Simulation time 202050941 ps
CPU time 3.76 seconds
Started Apr 27 04:09:56 PM PDT 24
Finished Apr 27 04:10:00 PM PDT 24
Peak memory 210496 kb
Host smart-5a1049d3-46e2-4ffa-8b37-ce08895bcc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399296818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3399296818
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2630868098
Short name T568
Test name
Test status
Simulation time 26252277 ps
CPU time 0.79 seconds
Started Apr 27 04:10:08 PM PDT 24
Finished Apr 27 04:10:09 PM PDT 24
Peak memory 205776 kb
Host smart-f7644cff-aae3-4d4d-9b0c-9398abc5736d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630868098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2630868098
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3251398224
Short name T994
Test name
Test status
Simulation time 64342839 ps
CPU time 3.31 seconds
Started Apr 27 04:10:05 PM PDT 24
Finished Apr 27 04:10:09 PM PDT 24
Peak memory 214648 kb
Host smart-29417e7b-f465-4006-9d12-90b42c2c3da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251398224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3251398224
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2231643370
Short name T79
Test name
Test status
Simulation time 152839773 ps
CPU time 2.13 seconds
Started Apr 27 04:10:07 PM PDT 24
Finished Apr 27 04:10:09 PM PDT 24
Peak memory 207504 kb
Host smart-354fa978-ebca-40fd-b1cc-0bd926cab00f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231643370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2231643370
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1112825349
Short name T654
Test name
Test status
Simulation time 267283781 ps
CPU time 3.62 seconds
Started Apr 27 04:10:03 PM PDT 24
Finished Apr 27 04:10:07 PM PDT 24
Peak memory 208856 kb
Host smart-2c8de4c3-b4ab-4ec8-8277-a174f185b810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112825349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1112825349
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1210314393
Short name T210
Test name
Test status
Simulation time 127481817 ps
CPU time 3.98 seconds
Started Apr 27 04:10:02 PM PDT 24
Finished Apr 27 04:10:07 PM PDT 24
Peak memory 220176 kb
Host smart-107c605e-66df-4c32-8d58-aef51e4ebb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210314393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1210314393
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.278613242
Short name T104
Test name
Test status
Simulation time 378245956 ps
CPU time 4.71 seconds
Started Apr 27 04:10:07 PM PDT 24
Finished Apr 27 04:10:12 PM PDT 24
Peak memory 209416 kb
Host smart-98084474-7db2-4685-99a6-034734535be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278613242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.278613242
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.4199194737
Short name T930
Test name
Test status
Simulation time 3002674763 ps
CPU time 21.03 seconds
Started Apr 27 04:10:05 PM PDT 24
Finished Apr 27 04:10:26 PM PDT 24
Peak memory 208220 kb
Host smart-f7d89de2-0776-4b03-a0a6-384e1e1636ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199194737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.4199194737
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3476145039
Short name T958
Test name
Test status
Simulation time 151803437 ps
CPU time 2.51 seconds
Started Apr 27 04:10:02 PM PDT 24
Finished Apr 27 04:10:05 PM PDT 24
Peak memory 206896 kb
Host smart-ca49dd92-9a20-4d86-94c7-1247cd992841
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476145039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3476145039
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.2177318193
Short name T17
Test name
Test status
Simulation time 38136592 ps
CPU time 2.6 seconds
Started Apr 27 04:10:03 PM PDT 24
Finished Apr 27 04:10:06 PM PDT 24
Peak memory 207508 kb
Host smart-77a3a3fd-1d25-455f-bec6-9a2ed938e429
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177318193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.2177318193
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2735988048
Short name T1
Test name
Test status
Simulation time 94796147 ps
CPU time 2.89 seconds
Started Apr 27 04:10:05 PM PDT 24
Finished Apr 27 04:10:08 PM PDT 24
Peak memory 206844 kb
Host smart-2449e9bd-8938-4925-a43f-8abcabcdd3a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735988048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2735988048
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.517837904
Short name T303
Test name
Test status
Simulation time 530059070 ps
CPU time 4.48 seconds
Started Apr 27 04:10:04 PM PDT 24
Finished Apr 27 04:10:09 PM PDT 24
Peak memory 207692 kb
Host smart-e9a59427-0163-46e3-ba55-6f3b55686474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517837904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.517837904
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3842018990
Short name T796
Test name
Test status
Simulation time 70959882 ps
CPU time 3.23 seconds
Started Apr 27 04:10:04 PM PDT 24
Finished Apr 27 04:10:08 PM PDT 24
Peak memory 208832 kb
Host smart-74a40093-44af-4cc1-8ca6-d52e71ea983b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842018990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3842018990
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3547184773
Short name T236
Test name
Test status
Simulation time 1414277075 ps
CPU time 30.64 seconds
Started Apr 27 04:10:02 PM PDT 24
Finished Apr 27 04:10:33 PM PDT 24
Peak memory 222464 kb
Host smart-8a558ae2-79d1-409f-ad51-c6d89ed6a05f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547184773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3547184773
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2787750166
Short name T616
Test name
Test status
Simulation time 256639359 ps
CPU time 3.59 seconds
Started Apr 27 04:10:03 PM PDT 24
Finished Apr 27 04:10:07 PM PDT 24
Peak memory 222080 kb
Host smart-3da8b162-5769-4233-91a8-c20e5e892325
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787750166 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2787750166
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.955742121
Short name T280
Test name
Test status
Simulation time 192960134 ps
CPU time 5.63 seconds
Started Apr 27 04:10:05 PM PDT 24
Finished Apr 27 04:10:11 PM PDT 24
Peak memory 208868 kb
Host smart-360e4e6e-918b-4191-9997-7bae0a359ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955742121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.955742121
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2891456228
Short name T555
Test name
Test status
Simulation time 206899887 ps
CPU time 2.7 seconds
Started Apr 27 04:10:02 PM PDT 24
Finished Apr 27 04:10:05 PM PDT 24
Peak memory 210248 kb
Host smart-f3a5520a-1507-44e6-9da3-1e0b543a7c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891456228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2891456228
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2295615726
Short name T235
Test name
Test status
Simulation time 1211100811 ps
CPU time 67.85 seconds
Started Apr 27 04:10:09 PM PDT 24
Finished Apr 27 04:11:17 PM PDT 24
Peak memory 214464 kb
Host smart-16dddad2-174b-4a61-ac5f-fbafc65444aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2295615726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2295615726
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.4175345968
Short name T876
Test name
Test status
Simulation time 42192052 ps
CPU time 1.46 seconds
Started Apr 27 04:10:10 PM PDT 24
Finished Apr 27 04:10:11 PM PDT 24
Peak memory 207812 kb
Host smart-d6f52550-8d1c-4b67-8c14-64c00754b8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175345968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.4175345968
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1456737056
Short name T296
Test name
Test status
Simulation time 533071259 ps
CPU time 6.42 seconds
Started Apr 27 04:10:09 PM PDT 24
Finished Apr 27 04:10:16 PM PDT 24
Peak memory 208948 kb
Host smart-f73b1fab-a732-4e4e-8f70-8e7d4a8f7c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456737056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1456737056
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1168348658
Short name T967
Test name
Test status
Simulation time 245037912 ps
CPU time 5.35 seconds
Started Apr 27 04:10:09 PM PDT 24
Finished Apr 27 04:10:15 PM PDT 24
Peak memory 214228 kb
Host smart-fe25bb1a-6453-4aaa-ae89-ba98d7ec3728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168348658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1168348658
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.429180154
Short name T49
Test name
Test status
Simulation time 236985964 ps
CPU time 5.26 seconds
Started Apr 27 04:10:09 PM PDT 24
Finished Apr 27 04:10:15 PM PDT 24
Peak memory 219988 kb
Host smart-6ab9beb9-5132-4bab-91c2-0fe65c6054eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429180154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.429180154
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3563826489
Short name T1029
Test name
Test status
Simulation time 196440470 ps
CPU time 5.5 seconds
Started Apr 27 04:10:10 PM PDT 24
Finished Apr 27 04:10:16 PM PDT 24
Peak memory 209644 kb
Host smart-c6e184a4-809e-437d-bfa0-fdb5e9b181a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563826489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3563826489
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3177019776
Short name T639
Test name
Test status
Simulation time 214887141 ps
CPU time 6.84 seconds
Started Apr 27 04:10:07 PM PDT 24
Finished Apr 27 04:10:14 PM PDT 24
Peak memory 208028 kb
Host smart-5eafbe05-c7a4-4c44-9177-f99aa84b8cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177019776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3177019776
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1611802782
Short name T803
Test name
Test status
Simulation time 38263663 ps
CPU time 2.6 seconds
Started Apr 27 04:10:08 PM PDT 24
Finished Apr 27 04:10:11 PM PDT 24
Peak memory 208732 kb
Host smart-aec4dcd1-13af-4434-a7ed-8dc2712f92be
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611802782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1611802782
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1046508123
Short name T924
Test name
Test status
Simulation time 254714583 ps
CPU time 3.44 seconds
Started Apr 27 04:10:10 PM PDT 24
Finished Apr 27 04:10:14 PM PDT 24
Peak memory 208512 kb
Host smart-52979580-847c-4839-8e0e-d3dbd35df734
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046508123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1046508123
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1234701262
Short name T387
Test name
Test status
Simulation time 1995452522 ps
CPU time 48.26 seconds
Started Apr 27 04:10:09 PM PDT 24
Finished Apr 27 04:10:57 PM PDT 24
Peak memory 208180 kb
Host smart-d73e1813-ac6f-42c2-8db8-3d74c335006b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234701262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1234701262
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.749794468
Short name T902
Test name
Test status
Simulation time 47865170 ps
CPU time 2.64 seconds
Started Apr 27 04:10:08 PM PDT 24
Finished Apr 27 04:10:11 PM PDT 24
Peak memory 214388 kb
Host smart-98860988-0ee0-4d78-ae6a-896c0fef0cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749794468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.749794468
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.4019509757
Short name T695
Test name
Test status
Simulation time 288023669 ps
CPU time 6.53 seconds
Started Apr 27 04:10:08 PM PDT 24
Finished Apr 27 04:10:15 PM PDT 24
Peak memory 207832 kb
Host smart-4d1b4154-662e-476c-bc66-21b17038bcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019509757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.4019509757
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3327439336
Short name T951
Test name
Test status
Simulation time 550001260 ps
CPU time 19.53 seconds
Started Apr 27 04:10:12 PM PDT 24
Finished Apr 27 04:10:32 PM PDT 24
Peak memory 218608 kb
Host smart-eddb93b3-538a-4791-acc4-a02538ac2ba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327439336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3327439336
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3431109359
Short name T667
Test name
Test status
Simulation time 58667671 ps
CPU time 3.46 seconds
Started Apr 27 04:10:10 PM PDT 24
Finished Apr 27 04:10:14 PM PDT 24
Peak memory 222644 kb
Host smart-4c0f9f93-c604-42c4-9bcc-860eda08c435
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431109359 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3431109359
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1248389126
Short name T722
Test name
Test status
Simulation time 66015907 ps
CPU time 4.18 seconds
Started Apr 27 04:10:09 PM PDT 24
Finished Apr 27 04:10:14 PM PDT 24
Peak memory 218496 kb
Host smart-a3e6a5bc-f728-448a-aec9-787f0739599b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248389126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1248389126
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2152122446
Short name T379
Test name
Test status
Simulation time 92608640 ps
CPU time 2.15 seconds
Started Apr 27 04:10:10 PM PDT 24
Finished Apr 27 04:10:13 PM PDT 24
Peak memory 209692 kb
Host smart-7c7da376-f5d4-44fa-8992-a784ff2dec49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152122446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2152122446
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.3853388336
Short name T606
Test name
Test status
Simulation time 15855174 ps
CPU time 0.75 seconds
Started Apr 27 04:10:23 PM PDT 24
Finished Apr 27 04:10:24 PM PDT 24
Peak memory 205876 kb
Host smart-d4e1a144-e053-4f71-b0cb-f4ce403f23a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853388336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.3853388336
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3700228825
Short name T774
Test name
Test status
Simulation time 1010998680 ps
CPU time 6.54 seconds
Started Apr 27 04:10:15 PM PDT 24
Finished Apr 27 04:10:22 PM PDT 24
Peak memory 207976 kb
Host smart-65688896-9bd5-4f57-a514-7744810a869a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700228825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3700228825
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3390192829
Short name T96
Test name
Test status
Simulation time 2506635244 ps
CPU time 26.3 seconds
Started Apr 27 04:10:17 PM PDT 24
Finished Apr 27 04:10:44 PM PDT 24
Peak memory 214376 kb
Host smart-cce2ffad-e770-4433-8740-e4fcb5fff341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390192829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3390192829
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2522594158
Short name T377
Test name
Test status
Simulation time 282153423 ps
CPU time 4.08 seconds
Started Apr 27 04:10:14 PM PDT 24
Finished Apr 27 04:10:19 PM PDT 24
Peak memory 211196 kb
Host smart-47239048-1c17-46d5-a3cd-a03341be467b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522594158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2522594158
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.46832373
Short name T640
Test name
Test status
Simulation time 426559265 ps
CPU time 4.05 seconds
Started Apr 27 04:10:16 PM PDT 24
Finished Apr 27 04:10:20 PM PDT 24
Peak memory 214332 kb
Host smart-82e8cb12-2fc0-42de-8e5f-ca3dcb60a874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46832373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.46832373
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1677320346
Short name T977
Test name
Test status
Simulation time 503911334 ps
CPU time 6.57 seconds
Started Apr 27 04:10:18 PM PDT 24
Finished Apr 27 04:10:25 PM PDT 24
Peak memory 209688 kb
Host smart-83467718-a44e-4768-8be0-01f345a07945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677320346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1677320346
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3719923303
Short name T274
Test name
Test status
Simulation time 27817904 ps
CPU time 2.12 seconds
Started Apr 27 04:10:14 PM PDT 24
Finished Apr 27 04:10:16 PM PDT 24
Peak memory 208588 kb
Host smart-bee52a60-c935-4a28-a396-b040b7d7649f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719923303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3719923303
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3083590168
Short name T320
Test name
Test status
Simulation time 3220358574 ps
CPU time 31.47 seconds
Started Apr 27 04:10:14 PM PDT 24
Finished Apr 27 04:10:46 PM PDT 24
Peak memory 208568 kb
Host smart-e29ff4ec-43f0-46e6-ab5b-db0fe2f1683e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083590168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3083590168
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2891776453
Short name T596
Test name
Test status
Simulation time 200757791 ps
CPU time 2.8 seconds
Started Apr 27 04:10:17 PM PDT 24
Finished Apr 27 04:10:20 PM PDT 24
Peak memory 208588 kb
Host smart-07d6b2e5-ca71-44e2-9bf6-3fbd05415ef9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891776453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2891776453
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1000188221
Short name T831
Test name
Test status
Simulation time 108581067 ps
CPU time 3.03 seconds
Started Apr 27 04:10:14 PM PDT 24
Finished Apr 27 04:10:17 PM PDT 24
Peak memory 206908 kb
Host smart-6091727a-f686-4566-a18c-df13bba301e9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000188221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1000188221
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3183956492
Short name T622
Test name
Test status
Simulation time 79012939 ps
CPU time 2.86 seconds
Started Apr 27 04:10:14 PM PDT 24
Finished Apr 27 04:10:17 PM PDT 24
Peak memory 220396 kb
Host smart-985f0cff-f840-45b7-b318-32a43339c96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183956492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3183956492
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.991336443
Short name T685
Test name
Test status
Simulation time 138593117 ps
CPU time 2.45 seconds
Started Apr 27 04:10:16 PM PDT 24
Finished Apr 27 04:10:19 PM PDT 24
Peak memory 207472 kb
Host smart-e3a7a735-6e1f-48ff-b068-9d05727eccab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991336443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.991336443
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.150788991
Short name T850
Test name
Test status
Simulation time 3780320800 ps
CPU time 12.15 seconds
Started Apr 27 04:10:21 PM PDT 24
Finished Apr 27 04:10:33 PM PDT 24
Peak memory 215964 kb
Host smart-2860ad75-7e3e-4cc8-9a65-651b350c02d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150788991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.150788991
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.1001575585
Short name T664
Test name
Test status
Simulation time 86123518 ps
CPU time 3.72 seconds
Started Apr 27 04:10:18 PM PDT 24
Finished Apr 27 04:10:23 PM PDT 24
Peak memory 219528 kb
Host smart-0fbbe7b1-7b35-4fde-bf2a-1d68bfa98a1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001575585 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.1001575585
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.210349687
Short name T573
Test name
Test status
Simulation time 2465071831 ps
CPU time 8.45 seconds
Started Apr 27 04:10:14 PM PDT 24
Finished Apr 27 04:10:22 PM PDT 24
Peak memory 208488 kb
Host smart-3733e053-2b3c-452b-a035-3b92a2985d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210349687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.210349687
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.547500560
Short name T944
Test name
Test status
Simulation time 219820634 ps
CPU time 2.44 seconds
Started Apr 27 04:10:17 PM PDT 24
Finished Apr 27 04:10:20 PM PDT 24
Peak memory 210048 kb
Host smart-90b4fb03-7130-45f2-86ed-f319f4c426e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547500560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.547500560
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1521975123
Short name T746
Test name
Test status
Simulation time 68313817 ps
CPU time 0.87 seconds
Started Apr 27 04:10:27 PM PDT 24
Finished Apr 27 04:10:28 PM PDT 24
Peak memory 205868 kb
Host smart-4d163e64-9aed-46e9-accc-1f9d730ec983
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521975123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1521975123
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2300742658
Short name T611
Test name
Test status
Simulation time 268289062 ps
CPU time 3.09 seconds
Started Apr 27 04:10:23 PM PDT 24
Finished Apr 27 04:10:27 PM PDT 24
Peak memory 209208 kb
Host smart-7ff3e947-daa0-4e4c-ac9f-f985e5c68dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300742658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2300742658
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3987433949
Short name T230
Test name
Test status
Simulation time 130287983 ps
CPU time 2.96 seconds
Started Apr 27 04:10:19 PM PDT 24
Finished Apr 27 04:10:22 PM PDT 24
Peak memory 214328 kb
Host smart-04d69f0e-7fe6-4a8c-8da4-0468b2171c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987433949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3987433949
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1792306559
Short name T946
Test name
Test status
Simulation time 448050643 ps
CPU time 3.58 seconds
Started Apr 27 04:10:23 PM PDT 24
Finished Apr 27 04:10:27 PM PDT 24
Peak memory 209384 kb
Host smart-a534dde1-b48f-43ff-b162-11cdbe6a4f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792306559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1792306559
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3744035226
Short name T793
Test name
Test status
Simulation time 293535079 ps
CPU time 6.16 seconds
Started Apr 27 04:10:19 PM PDT 24
Finished Apr 27 04:10:26 PM PDT 24
Peak memory 209772 kb
Host smart-d4f08916-0a1c-4370-940f-3dd1e62c031f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744035226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3744035226
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3670436645
Short name T225
Test name
Test status
Simulation time 71751508 ps
CPU time 3.09 seconds
Started Apr 27 04:10:20 PM PDT 24
Finished Apr 27 04:10:24 PM PDT 24
Peak memory 206676 kb
Host smart-9911c080-f3ab-4846-88bb-5a5566d75b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670436645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3670436645
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3254969036
Short name T962
Test name
Test status
Simulation time 116338038 ps
CPU time 3.27 seconds
Started Apr 27 04:10:21 PM PDT 24
Finished Apr 27 04:10:25 PM PDT 24
Peak memory 206856 kb
Host smart-664b75db-995c-4898-a814-70e1e2a945b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254969036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3254969036
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1713017757
Short name T567
Test name
Test status
Simulation time 245789828 ps
CPU time 3.35 seconds
Started Apr 27 04:10:20 PM PDT 24
Finished Apr 27 04:10:24 PM PDT 24
Peak memory 206988 kb
Host smart-3542dc42-bc7c-4a2a-827c-62de4a5a9f86
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713017757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1713017757
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3419808248
Short name T980
Test name
Test status
Simulation time 312846601 ps
CPU time 3.65 seconds
Started Apr 27 04:10:20 PM PDT 24
Finished Apr 27 04:10:24 PM PDT 24
Peak memory 208648 kb
Host smart-6b8ad9d1-f8b1-4b4f-a06c-600ba2dbaafe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419808248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3419808248
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3274419116
Short name T672
Test name
Test status
Simulation time 310796416 ps
CPU time 2.58 seconds
Started Apr 27 04:10:22 PM PDT 24
Finished Apr 27 04:10:25 PM PDT 24
Peak memory 207892 kb
Host smart-bb6c034a-899b-4514-936f-68b23f3fd450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274419116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3274419116
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1347639955
Short name T941
Test name
Test status
Simulation time 62570667 ps
CPU time 2.72 seconds
Started Apr 27 04:10:20 PM PDT 24
Finished Apr 27 04:10:23 PM PDT 24
Peak memory 206872 kb
Host smart-82ba654e-c030-4f6b-b23f-878a47445fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347639955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1347639955
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3214594797
Short name T1061
Test name
Test status
Simulation time 11128131663 ps
CPU time 148.97 seconds
Started Apr 27 04:10:24 PM PDT 24
Finished Apr 27 04:12:54 PM PDT 24
Peak memory 217328 kb
Host smart-2b262c87-cc9f-4a41-842f-ea7e856b5d1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214594797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3214594797
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3827499307
Short name T103
Test name
Test status
Simulation time 144570072 ps
CPU time 4.55 seconds
Started Apr 27 04:10:24 PM PDT 24
Finished Apr 27 04:10:29 PM PDT 24
Peak memory 222616 kb
Host smart-63936925-590c-4d00-8ad7-ab0c34127f3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827499307 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.3827499307
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.156880669
Short name T784
Test name
Test status
Simulation time 223093479 ps
CPU time 3.68 seconds
Started Apr 27 04:10:18 PM PDT 24
Finished Apr 27 04:10:22 PM PDT 24
Peak memory 207540 kb
Host smart-93b5a33d-9db1-438f-885b-55028e1cc4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156880669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.156880669
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2031726675
Short name T770
Test name
Test status
Simulation time 42843207 ps
CPU time 2.13 seconds
Started Apr 27 04:10:25 PM PDT 24
Finished Apr 27 04:10:27 PM PDT 24
Peak memory 209896 kb
Host smart-61fe4f73-0978-4776-a6b0-f8d8fa64d399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031726675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2031726675
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1846378422
Short name T632
Test name
Test status
Simulation time 47310929 ps
CPU time 0.76 seconds
Started Apr 27 04:10:29 PM PDT 24
Finished Apr 27 04:10:30 PM PDT 24
Peak memory 205656 kb
Host smart-f44050ed-c44f-4ae3-b155-50b03807132e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846378422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1846378422
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.35260035
Short name T408
Test name
Test status
Simulation time 838654735 ps
CPU time 8.23 seconds
Started Apr 27 04:10:24 PM PDT 24
Finished Apr 27 04:10:33 PM PDT 24
Peak memory 214816 kb
Host smart-63518e7e-686a-4193-b48c-7f4561e8e327
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=35260035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.35260035
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.787934642
Short name T38
Test name
Test status
Simulation time 569001290 ps
CPU time 4.73 seconds
Started Apr 27 04:10:27 PM PDT 24
Finished Apr 27 04:10:32 PM PDT 24
Peak memory 216168 kb
Host smart-2e4e9ee9-48f8-4dae-9a98-0a5f4699840e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787934642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.787934642
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2651158175
Short name T1049
Test name
Test status
Simulation time 36092378 ps
CPU time 1.64 seconds
Started Apr 27 04:10:24 PM PDT 24
Finished Apr 27 04:10:27 PM PDT 24
Peak memory 207740 kb
Host smart-b50c281c-ca03-49b1-bdbb-76ce02bf47ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651158175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2651158175
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.372351942
Short name T757
Test name
Test status
Simulation time 62596294 ps
CPU time 3.15 seconds
Started Apr 27 04:10:28 PM PDT 24
Finished Apr 27 04:10:31 PM PDT 24
Peak memory 209248 kb
Host smart-8f969bce-18e8-423b-961e-f60c3cfdf872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372351942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.372351942
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2650968692
Short name T556
Test name
Test status
Simulation time 86272468 ps
CPU time 4.23 seconds
Started Apr 27 04:10:27 PM PDT 24
Finished Apr 27 04:10:32 PM PDT 24
Peak memory 209088 kb
Host smart-050b7c61-f68c-42bc-a16c-baf98cb2ee60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650968692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2650968692
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2696923022
Short name T311
Test name
Test status
Simulation time 425758926 ps
CPU time 8.44 seconds
Started Apr 27 04:10:25 PM PDT 24
Finished Apr 27 04:10:34 PM PDT 24
Peak memory 206816 kb
Host smart-77becb52-47b7-48be-bf4a-11263f2b33b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696923022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2696923022
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.824027391
Short name T830
Test name
Test status
Simulation time 286573671 ps
CPU time 3.44 seconds
Started Apr 27 04:10:28 PM PDT 24
Finished Apr 27 04:10:32 PM PDT 24
Peak memory 208488 kb
Host smart-e599d35f-43c2-4c0f-a584-3cdc068bbf77
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824027391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.824027391
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2087918155
Short name T582
Test name
Test status
Simulation time 27988139 ps
CPU time 2.36 seconds
Started Apr 27 04:10:25 PM PDT 24
Finished Apr 27 04:10:28 PM PDT 24
Peak memory 208880 kb
Host smart-5b9d75e0-dcaf-43c7-b31d-537320a176dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087918155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2087918155
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.1097772620
Short name T1069
Test name
Test status
Simulation time 108781818 ps
CPU time 2.14 seconds
Started Apr 27 04:10:25 PM PDT 24
Finished Apr 27 04:10:27 PM PDT 24
Peak memory 206744 kb
Host smart-d8f79182-3192-4f0a-814e-ace30a295011
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097772620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.1097772620
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3497258539
Short name T106
Test name
Test status
Simulation time 49093801 ps
CPU time 2.14 seconds
Started Apr 27 04:10:31 PM PDT 24
Finished Apr 27 04:10:33 PM PDT 24
Peak memory 209596 kb
Host smart-9ffdd978-270e-40dc-a26d-82450dd6a8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497258539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3497258539
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3896341499
Short name T947
Test name
Test status
Simulation time 1623420148 ps
CPU time 17.56 seconds
Started Apr 27 04:10:25 PM PDT 24
Finished Apr 27 04:10:43 PM PDT 24
Peak memory 206952 kb
Host smart-0d88629e-416e-4b11-89e5-10d5fa264395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896341499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3896341499
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1255467293
Short name T724
Test name
Test status
Simulation time 91456097 ps
CPU time 4.19 seconds
Started Apr 27 04:10:31 PM PDT 24
Finished Apr 27 04:10:35 PM PDT 24
Peak memory 222624 kb
Host smart-411d78fb-b1e2-4525-b9e0-1973f05661f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255467293 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1255467293
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.625789552
Short name T312
Test name
Test status
Simulation time 97375845 ps
CPU time 4.99 seconds
Started Apr 27 04:10:26 PM PDT 24
Finished Apr 27 04:10:32 PM PDT 24
Peak memory 207880 kb
Host smart-102e149f-edec-4a1e-9da7-bb0edee61f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625789552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.625789552
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1662092261
Short name T564
Test name
Test status
Simulation time 33477346 ps
CPU time 1.96 seconds
Started Apr 27 04:10:29 PM PDT 24
Finished Apr 27 04:10:31 PM PDT 24
Peak memory 209496 kb
Host smart-b1bd65aa-53be-44cf-8acf-40875c2c3e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662092261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1662092261
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3602714308
Short name T100
Test name
Test status
Simulation time 36718666 ps
CPU time 0.75 seconds
Started Apr 27 04:10:36 PM PDT 24
Finished Apr 27 04:10:37 PM PDT 24
Peak memory 205840 kb
Host smart-cac6c43e-1c5b-4473-88b0-6d15f2bba96c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602714308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3602714308
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3098907448
Short name T896
Test name
Test status
Simulation time 1489532181 ps
CPU time 7.86 seconds
Started Apr 27 04:10:29 PM PDT 24
Finished Apr 27 04:10:37 PM PDT 24
Peak memory 221868 kb
Host smart-7c296613-5351-40bf-9c75-e4a3144fa523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098907448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3098907448
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2628926016
Short name T691
Test name
Test status
Simulation time 81685806 ps
CPU time 2.11 seconds
Started Apr 27 04:10:29 PM PDT 24
Finished Apr 27 04:10:32 PM PDT 24
Peak memory 214368 kb
Host smart-a0e3f729-334e-4374-96e1-7a5ca6b72d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628926016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2628926016
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1440430510
Short name T928
Test name
Test status
Simulation time 42456647 ps
CPU time 2.99 seconds
Started Apr 27 04:10:28 PM PDT 24
Finished Apr 27 04:10:31 PM PDT 24
Peak memory 214348 kb
Host smart-299f17fd-daa0-49b6-ad68-69cb0ef0c4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440430510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1440430510
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2508247685
Short name T1040
Test name
Test status
Simulation time 388973368 ps
CPU time 5 seconds
Started Apr 27 04:10:30 PM PDT 24
Finished Apr 27 04:10:35 PM PDT 24
Peak memory 210028 kb
Host smart-f82ed0e2-e01b-4d76-b9ce-0728261a1a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508247685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2508247685
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.2115562408
Short name T306
Test name
Test status
Simulation time 1128035623 ps
CPU time 7.03 seconds
Started Apr 27 04:10:32 PM PDT 24
Finished Apr 27 04:10:40 PM PDT 24
Peak memory 214324 kb
Host smart-c6b04b87-736f-4c27-a743-2b4207083f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115562408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.2115562408
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.380681814
Short name T723
Test name
Test status
Simulation time 77490937 ps
CPU time 2.49 seconds
Started Apr 27 04:10:32 PM PDT 24
Finished Apr 27 04:10:35 PM PDT 24
Peak memory 206708 kb
Host smart-7490556b-31da-4090-af64-483e5fc0bab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380681814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.380681814
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2471856881
Short name T272
Test name
Test status
Simulation time 133089292 ps
CPU time 3.96 seconds
Started Apr 27 04:10:31 PM PDT 24
Finished Apr 27 04:10:35 PM PDT 24
Peak memory 208852 kb
Host smart-228096b5-7435-4123-adb9-7daddd0b0245
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471856881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2471856881
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1303163817
Short name T826
Test name
Test status
Simulation time 24054701996 ps
CPU time 76.46 seconds
Started Apr 27 04:10:30 PM PDT 24
Finished Apr 27 04:11:47 PM PDT 24
Peak memory 208740 kb
Host smart-13d89a0e-2d64-49e3-b841-c9b86915e13b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303163817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1303163817
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.158935540
Short name T550
Test name
Test status
Simulation time 2275488735 ps
CPU time 17.42 seconds
Started Apr 27 04:10:31 PM PDT 24
Finished Apr 27 04:10:49 PM PDT 24
Peak memory 208084 kb
Host smart-a68ac3d4-08b7-48ba-ab16-65e3cf6543a5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158935540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.158935540
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2686888778
Short name T718
Test name
Test status
Simulation time 234211746 ps
CPU time 2.12 seconds
Started Apr 27 04:10:32 PM PDT 24
Finished Apr 27 04:10:34 PM PDT 24
Peak memory 206864 kb
Host smart-aaf70597-dfce-4d8c-a2bf-c9fb1ab0aa37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686888778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2686888778
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1736149324
Short name T744
Test name
Test status
Simulation time 40470731 ps
CPU time 1.85 seconds
Started Apr 27 04:10:29 PM PDT 24
Finished Apr 27 04:10:31 PM PDT 24
Peak memory 207196 kb
Host smart-c6206732-52b1-48ab-8311-5d7313e2b753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736149324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1736149324
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.4029480592
Short name T1041
Test name
Test status
Simulation time 9013675525 ps
CPU time 65.79 seconds
Started Apr 27 04:10:40 PM PDT 24
Finished Apr 27 04:11:46 PM PDT 24
Peak memory 215544 kb
Host smart-8c729799-1df0-4937-91b3-603a48aa063d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029480592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.4029480592
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.99272126
Short name T1003
Test name
Test status
Simulation time 187273187 ps
CPU time 8.66 seconds
Started Apr 27 04:10:38 PM PDT 24
Finished Apr 27 04:10:48 PM PDT 24
Peak memory 220540 kb
Host smart-830970b7-0e43-42de-9edf-c2d4b49c5688
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99272126 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.99272126
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.88511826
Short name T692
Test name
Test status
Simulation time 1040163883 ps
CPU time 24.45 seconds
Started Apr 27 04:10:29 PM PDT 24
Finished Apr 27 04:10:54 PM PDT 24
Peak memory 208640 kb
Host smart-2161c0a0-f51e-433e-91fd-cdaeaa3d02bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88511826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.88511826
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1531409526
Short name T170
Test name
Test status
Simulation time 681282735 ps
CPU time 3.96 seconds
Started Apr 27 04:10:28 PM PDT 24
Finished Apr 27 04:10:32 PM PDT 24
Peak memory 209712 kb
Host smart-d456c82d-efab-430f-80b1-ec19580eb47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531409526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1531409526
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.453509892
Short name T976
Test name
Test status
Simulation time 14563754 ps
CPU time 0.78 seconds
Started Apr 27 04:10:41 PM PDT 24
Finished Apr 27 04:10:42 PM PDT 24
Peak memory 205872 kb
Host smart-f9177fe3-3eb1-4a73-a1ce-868d260ae5ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453509892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.453509892
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1896752834
Short name T992
Test name
Test status
Simulation time 650705202 ps
CPU time 8.77 seconds
Started Apr 27 04:10:37 PM PDT 24
Finished Apr 27 04:10:46 PM PDT 24
Peak memory 214340 kb
Host smart-6df7fee5-5f5c-44fc-bcd8-12edc507e55d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1896752834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1896752834
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2492289926
Short name T43
Test name
Test status
Simulation time 601534994 ps
CPU time 13.37 seconds
Started Apr 27 04:10:43 PM PDT 24
Finished Apr 27 04:10:58 PM PDT 24
Peak memory 214252 kb
Host smart-ea4654fc-6744-446b-a18d-f345336460b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492289926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2492289926
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1587850461
Short name T576
Test name
Test status
Simulation time 180903359 ps
CPU time 2.41 seconds
Started Apr 27 04:10:43 PM PDT 24
Finished Apr 27 04:10:47 PM PDT 24
Peak memory 208108 kb
Host smart-2fb4d109-a6e5-44ea-9713-346bd8ac3e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587850461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1587850461
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2393656164
Short name T785
Test name
Test status
Simulation time 56303557 ps
CPU time 2.2 seconds
Started Apr 27 04:10:38 PM PDT 24
Finished Apr 27 04:10:40 PM PDT 24
Peak memory 218472 kb
Host smart-47d3a7ab-5bf3-4387-a008-30b0caec0215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393656164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2393656164
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.430148745
Short name T29
Test name
Test status
Simulation time 537926627 ps
CPU time 3.94 seconds
Started Apr 27 04:10:38 PM PDT 24
Finished Apr 27 04:10:42 PM PDT 24
Peak memory 222456 kb
Host smart-611e34df-4e0c-45d7-994d-47e5a34d4eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430148745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.430148745
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3611320685
Short name T206
Test name
Test status
Simulation time 102229606 ps
CPU time 3.94 seconds
Started Apr 27 04:10:36 PM PDT 24
Finished Apr 27 04:10:41 PM PDT 24
Peak memory 209696 kb
Host smart-bca3b9d5-5246-4378-9b70-48a46b9b4136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611320685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3611320685
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1705249374
Short name T348
Test name
Test status
Simulation time 1503430765 ps
CPU time 5.37 seconds
Started Apr 27 04:10:39 PM PDT 24
Finished Apr 27 04:10:45 PM PDT 24
Peak memory 209772 kb
Host smart-e1a638df-6928-4e8b-87f6-5645f371598f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705249374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1705249374
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3895821967
Short name T706
Test name
Test status
Simulation time 144074744 ps
CPU time 3.43 seconds
Started Apr 27 04:10:43 PM PDT 24
Finished Apr 27 04:10:48 PM PDT 24
Peak memory 208696 kb
Host smart-a18e3a19-cb6f-40d3-bf3a-faf4f96b02bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895821967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3895821967
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3412353132
Short name T698
Test name
Test status
Simulation time 173630928 ps
CPU time 4.25 seconds
Started Apr 27 04:10:37 PM PDT 24
Finished Apr 27 04:10:41 PM PDT 24
Peak memory 207872 kb
Host smart-f77b37d4-5592-4ec4-ba05-514f5cdfe8b1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412353132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3412353132
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.49819696
Short name T687
Test name
Test status
Simulation time 4957552183 ps
CPU time 19.29 seconds
Started Apr 27 04:10:43 PM PDT 24
Finished Apr 27 04:11:04 PM PDT 24
Peak memory 207972 kb
Host smart-9cd78940-2029-4bec-a4f8-731c8bd47ef5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49819696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.49819696
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1501578583
Short name T1019
Test name
Test status
Simulation time 82675792 ps
CPU time 2.52 seconds
Started Apr 27 04:10:35 PM PDT 24
Finished Apr 27 04:10:38 PM PDT 24
Peak memory 207812 kb
Host smart-ef6c79dd-a567-4b6b-9871-18469d60853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501578583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1501578583
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2106906029
Short name T741
Test name
Test status
Simulation time 9174472242 ps
CPU time 62.1 seconds
Started Apr 27 04:10:39 PM PDT 24
Finished Apr 27 04:11:41 PM PDT 24
Peak memory 208844 kb
Host smart-d2f7fb65-70ef-4109-b26d-f21f6a46b5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106906029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2106906029
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3253653245
Short name T697
Test name
Test status
Simulation time 205474042 ps
CPU time 14.47 seconds
Started Apr 27 04:10:39 PM PDT 24
Finished Apr 27 04:10:54 PM PDT 24
Peak memory 222596 kb
Host smart-530ceade-cd35-43f0-958f-e10e8734d194
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253653245 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3253653245
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.4254612605
Short name T391
Test name
Test status
Simulation time 47367342 ps
CPU time 2.8 seconds
Started Apr 27 04:10:40 PM PDT 24
Finished Apr 27 04:10:44 PM PDT 24
Peak memory 208768 kb
Host smart-b1febfc2-1ee1-4bba-b143-f47134ca1045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254612605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.4254612605
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.4245262707
Short name T910
Test name
Test status
Simulation time 749655401 ps
CPU time 3.48 seconds
Started Apr 27 04:10:37 PM PDT 24
Finished Apr 27 04:10:41 PM PDT 24
Peak memory 210668 kb
Host smart-11792fa9-d745-4e0f-8598-eaf0a7e5a67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245262707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.4245262707
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2844915755
Short name T863
Test name
Test status
Simulation time 18929099 ps
CPU time 0.84 seconds
Started Apr 27 04:10:43 PM PDT 24
Finished Apr 27 04:10:45 PM PDT 24
Peak memory 205872 kb
Host smart-57494684-fc89-4919-8a95-59c4d325244a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844915755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2844915755
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.157864931
Short name T36
Test name
Test status
Simulation time 47817061 ps
CPU time 2.97 seconds
Started Apr 27 04:10:44 PM PDT 24
Finished Apr 27 04:10:48 PM PDT 24
Peak memory 209492 kb
Host smart-a44f6830-4d1b-4f97-8113-d8900ffaf46b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157864931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.157864931
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.894341937
Short name T650
Test name
Test status
Simulation time 492557272 ps
CPU time 2.44 seconds
Started Apr 27 04:10:47 PM PDT 24
Finished Apr 27 04:10:51 PM PDT 24
Peak memory 209200 kb
Host smart-8eacc9e0-8326-4f32-8da5-1544aabb5192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894341937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.894341937
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2239749755
Short name T89
Test name
Test status
Simulation time 324804152 ps
CPU time 5.27 seconds
Started Apr 27 04:10:43 PM PDT 24
Finished Apr 27 04:10:49 PM PDT 24
Peak memory 214260 kb
Host smart-7cc2318c-f1e8-42e3-82ab-8ffe613bfd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239749755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2239749755
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1615970441
Short name T895
Test name
Test status
Simulation time 284429141 ps
CPU time 3.78 seconds
Started Apr 27 04:10:45 PM PDT 24
Finished Apr 27 04:10:49 PM PDT 24
Peak memory 210580 kb
Host smart-8343e473-a2c9-4d6d-b264-4ef75562e650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615970441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1615970441
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.323649518
Short name T827
Test name
Test status
Simulation time 81964327 ps
CPU time 3.79 seconds
Started Apr 27 04:10:44 PM PDT 24
Finished Apr 27 04:10:49 PM PDT 24
Peak memory 219264 kb
Host smart-db1915b5-83fa-4189-9c56-759a02bb734e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323649518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.323649518
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.4290328709
Short name T1066
Test name
Test status
Simulation time 273623368 ps
CPU time 5.25 seconds
Started Apr 27 04:10:44 PM PDT 24
Finished Apr 27 04:10:50 PM PDT 24
Peak memory 209796 kb
Host smart-1ad174b8-1218-4670-b84c-fb719e5b8a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290328709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.4290328709
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.166387260
Short name T342
Test name
Test status
Simulation time 567274321 ps
CPU time 8.68 seconds
Started Apr 27 04:10:44 PM PDT 24
Finished Apr 27 04:10:54 PM PDT 24
Peak memory 208396 kb
Host smart-57ab3cb0-06bf-4b1d-b44c-ac23d7a21942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166387260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.166387260
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2530763173
Short name T762
Test name
Test status
Simulation time 44071915 ps
CPU time 2.48 seconds
Started Apr 27 04:10:47 PM PDT 24
Finished Apr 27 04:10:51 PM PDT 24
Peak memory 208280 kb
Host smart-68716783-7610-4f82-87d0-4a4c9678ed6c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530763173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2530763173
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2980894172
Short name T808
Test name
Test status
Simulation time 158024454 ps
CPU time 5.13 seconds
Started Apr 27 04:10:43 PM PDT 24
Finished Apr 27 04:10:49 PM PDT 24
Peak memory 207896 kb
Host smart-03db8065-8a58-4712-9bde-e034712c79b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980894172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2980894172
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2585420370
Short name T982
Test name
Test status
Simulation time 110245050 ps
CPU time 2.27 seconds
Started Apr 27 04:10:43 PM PDT 24
Finished Apr 27 04:10:47 PM PDT 24
Peak memory 206824 kb
Host smart-7b947613-a5b7-4825-8d12-d37f5d16bc97
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585420370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2585420370
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1298547923
Short name T884
Test name
Test status
Simulation time 470275383 ps
CPU time 5.68 seconds
Started Apr 27 04:10:43 PM PDT 24
Finished Apr 27 04:10:50 PM PDT 24
Peak memory 214296 kb
Host smart-65ffce02-bb82-4a9a-9621-3a063317940a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298547923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1298547923
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1951406140
Short name T410
Test name
Test status
Simulation time 56373080 ps
CPU time 2.29 seconds
Started Apr 27 04:10:43 PM PDT 24
Finished Apr 27 04:10:47 PM PDT 24
Peak memory 208544 kb
Host smart-c7a7bacb-b5c0-4045-9ccf-5bcf08796d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951406140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1951406140
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2314785441
Short name T881
Test name
Test status
Simulation time 1337542412 ps
CPU time 30.42 seconds
Started Apr 27 04:10:43 PM PDT 24
Finished Apr 27 04:11:15 PM PDT 24
Peak memory 216800 kb
Host smart-6452668c-5301-47ab-8c13-4a68ef185ae9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314785441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2314785441
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.2107794766
Short name T207
Test name
Test status
Simulation time 538028763 ps
CPU time 18.69 seconds
Started Apr 27 04:10:43 PM PDT 24
Finished Apr 27 04:11:03 PM PDT 24
Peak memory 222600 kb
Host smart-9ab6afc6-c9c6-4ccc-acc8-732e3aa7d3b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107794766 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.2107794766
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3134635066
Short name T287
Test name
Test status
Simulation time 108258233 ps
CPU time 5.11 seconds
Started Apr 27 04:10:44 PM PDT 24
Finished Apr 27 04:10:50 PM PDT 24
Peak memory 210164 kb
Host smart-24fd7d9c-f8f7-4428-b9bd-989d003a9907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134635066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3134635066
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.980483934
Short name T1047
Test name
Test status
Simulation time 193744595 ps
CPU time 1.84 seconds
Started Apr 27 04:10:44 PM PDT 24
Finished Apr 27 04:10:47 PM PDT 24
Peak memory 210084 kb
Host smart-77b0f5d0-9b16-4fb1-8afb-e191da07bdef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980483934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.980483934
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3265491116
Short name T971
Test name
Test status
Simulation time 121986814 ps
CPU time 0.83 seconds
Started Apr 27 04:10:48 PM PDT 24
Finished Apr 27 04:10:49 PM PDT 24
Peak memory 205816 kb
Host smart-f9accb8d-b242-47de-ac39-a6dcc2cb5ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265491116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3265491116
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.885659016
Short name T305
Test name
Test status
Simulation time 215055819 ps
CPU time 4.26 seconds
Started Apr 27 04:10:49 PM PDT 24
Finished Apr 27 04:10:54 PM PDT 24
Peak memory 214356 kb
Host smart-c4d9d979-2216-4da2-b8a7-d7242c57917f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=885659016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.885659016
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2263147377
Short name T783
Test name
Test status
Simulation time 219338037 ps
CPU time 2.63 seconds
Started Apr 27 04:10:47 PM PDT 24
Finished Apr 27 04:10:50 PM PDT 24
Peak memory 207464 kb
Host smart-6273b71d-8681-4bfc-aac5-7d5a7ddf80b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263147377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2263147377
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.15794570
Short name T322
Test name
Test status
Simulation time 805591727 ps
CPU time 9 seconds
Started Apr 27 04:10:50 PM PDT 24
Finished Apr 27 04:10:59 PM PDT 24
Peak memory 214420 kb
Host smart-aa5c6fb8-40b4-4b6c-b4cb-419c2fd477a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15794570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.15794570
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1499844926
Short name T1023
Test name
Test status
Simulation time 12616829925 ps
CPU time 86.41 seconds
Started Apr 27 04:10:49 PM PDT 24
Finished Apr 27 04:12:16 PM PDT 24
Peak memory 226092 kb
Host smart-241cd002-2869-4f26-aa91-7090afd6c584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499844926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1499844926
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_random.1436859865
Short name T807
Test name
Test status
Simulation time 2465743505 ps
CPU time 13.65 seconds
Started Apr 27 04:10:48 PM PDT 24
Finished Apr 27 04:11:02 PM PDT 24
Peak memory 208640 kb
Host smart-1f5e3067-035b-445b-9bd1-3b8aed00cc6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436859865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1436859865
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.1304207161
Short name T779
Test name
Test status
Simulation time 829473059 ps
CPU time 4.95 seconds
Started Apr 27 04:10:46 PM PDT 24
Finished Apr 27 04:10:52 PM PDT 24
Peak memory 206940 kb
Host smart-4420378f-b5e7-48f9-be7d-184db352911f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304207161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.1304207161
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3258879734
Short name T988
Test name
Test status
Simulation time 209197955 ps
CPU time 2.77 seconds
Started Apr 27 04:10:47 PM PDT 24
Finished Apr 27 04:10:51 PM PDT 24
Peak memory 208200 kb
Host smart-2cb41e6c-85e0-46e8-9463-133886cbb752
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258879734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3258879734
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.4085224667
Short name T817
Test name
Test status
Simulation time 25225895 ps
CPU time 2.17 seconds
Started Apr 27 04:10:41 PM PDT 24
Finished Apr 27 04:10:44 PM PDT 24
Peak memory 208812 kb
Host smart-6b195430-81f9-406a-adc7-2e22b8ad5628
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085224667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.4085224667
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2258521427
Short name T88
Test name
Test status
Simulation time 635548111 ps
CPU time 7.44 seconds
Started Apr 27 04:10:48 PM PDT 24
Finished Apr 27 04:10:57 PM PDT 24
Peak memory 208472 kb
Host smart-35315478-6762-42a4-bbfb-1de358d7f3d9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258521427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2258521427
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1425159894
Short name T598
Test name
Test status
Simulation time 37323549 ps
CPU time 2.15 seconds
Started Apr 27 04:10:48 PM PDT 24
Finished Apr 27 04:10:51 PM PDT 24
Peak memory 210144 kb
Host smart-09af3f1d-b7d5-4107-b70b-106cae5c2dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425159894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1425159894
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1835305361
Short name T781
Test name
Test status
Simulation time 96608795 ps
CPU time 3.15 seconds
Started Apr 27 04:10:42 PM PDT 24
Finished Apr 27 04:10:46 PM PDT 24
Peak memory 206688 kb
Host smart-766af117-6326-4f87-b0a9-6f04eaa44aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835305361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1835305361
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.690274345
Short name T862
Test name
Test status
Simulation time 4925879799 ps
CPU time 15.41 seconds
Started Apr 27 04:10:50 PM PDT 24
Finished Apr 27 04:11:06 PM PDT 24
Peak memory 220768 kb
Host smart-b49c4b4d-0a20-4257-93ae-a19c142eb9e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690274345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.690274345
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1201504799
Short name T125
Test name
Test status
Simulation time 641839463 ps
CPU time 3.63 seconds
Started Apr 27 04:10:50 PM PDT 24
Finished Apr 27 04:10:54 PM PDT 24
Peak memory 214580 kb
Host smart-1107447a-ef07-4fbc-8622-f130e1aaa855
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201504799 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1201504799
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.4149349084
Short name T888
Test name
Test status
Simulation time 8665506409 ps
CPU time 57.15 seconds
Started Apr 27 04:10:49 PM PDT 24
Finished Apr 27 04:11:47 PM PDT 24
Peak memory 214500 kb
Host smart-5218e29b-bdaa-4420-9ffa-7cc2d2b58e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149349084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.4149349084
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3720529507
Short name T953
Test name
Test status
Simulation time 338716203 ps
CPU time 2.03 seconds
Started Apr 27 04:10:50 PM PDT 24
Finished Apr 27 04:10:52 PM PDT 24
Peak memory 209920 kb
Host smart-6abc6c5a-83ce-4320-8b1c-fc551c5e728a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720529507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3720529507
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2718958326
Short name T411
Test name
Test status
Simulation time 11214684 ps
CPU time 0.74 seconds
Started Apr 27 04:09:03 PM PDT 24
Finished Apr 27 04:09:04 PM PDT 24
Peak memory 205808 kb
Host smart-4e2e0770-7d1f-4345-ad01-36abe14ec0ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718958326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2718958326
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3166721332
Short name T393
Test name
Test status
Simulation time 111753341 ps
CPU time 6.24 seconds
Started Apr 27 04:08:57 PM PDT 24
Finished Apr 27 04:09:04 PM PDT 24
Peak memory 214932 kb
Host smart-fa5fc336-9881-4e8f-bb0c-48072db97abc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3166721332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3166721332
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.163304942
Short name T1058
Test name
Test status
Simulation time 383395456 ps
CPU time 3.67 seconds
Started Apr 27 04:08:59 PM PDT 24
Finished Apr 27 04:09:03 PM PDT 24
Peak memory 218124 kb
Host smart-53c71c63-f543-4758-85f3-2fcf3cffdd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163304942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.163304942
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.401963262
Short name T571
Test name
Test status
Simulation time 271870949 ps
CPU time 9.19 seconds
Started Apr 27 04:09:03 PM PDT 24
Finished Apr 27 04:09:13 PM PDT 24
Peak memory 214276 kb
Host smart-698f13f5-f66b-4b3e-ad16-8472511c3d08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401963262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.401963262
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1710341016
Short name T59
Test name
Test status
Simulation time 1771120027 ps
CPU time 6.64 seconds
Started Apr 27 04:09:05 PM PDT 24
Finished Apr 27 04:09:12 PM PDT 24
Peak memory 219768 kb
Host smart-18f3116c-49ac-49ed-8975-44fbc9a2d87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710341016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1710341016
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3857906988
Short name T18
Test name
Test status
Simulation time 5849276484 ps
CPU time 40.91 seconds
Started Apr 27 04:08:58 PM PDT 24
Finished Apr 27 04:09:40 PM PDT 24
Peak memory 209612 kb
Host smart-614d0669-81fd-407a-9e10-b237d21dee5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857906988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3857906988
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2490346176
Short name T105
Test name
Test status
Simulation time 2414548090 ps
CPU time 17.63 seconds
Started Apr 27 04:09:05 PM PDT 24
Finished Apr 27 04:09:23 PM PDT 24
Peak memory 237476 kb
Host smart-198c519a-b1ec-4bf6-9faa-0407d38e6028
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490346176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2490346176
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.533292019
Short name T657
Test name
Test status
Simulation time 139091097 ps
CPU time 4.22 seconds
Started Apr 27 04:08:58 PM PDT 24
Finished Apr 27 04:09:03 PM PDT 24
Peak memory 208616 kb
Host smart-2ca3b273-8f4b-4040-ac0d-35b27653c193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533292019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.533292019
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1474767206
Short name T943
Test name
Test status
Simulation time 668542593 ps
CPU time 5.65 seconds
Started Apr 27 04:09:00 PM PDT 24
Finished Apr 27 04:09:06 PM PDT 24
Peak memory 208524 kb
Host smart-316b89dd-b863-4a29-a930-71b2af9eb10e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474767206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1474767206
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.275019650
Short name T683
Test name
Test status
Simulation time 47403473 ps
CPU time 2.61 seconds
Started Apr 27 04:08:59 PM PDT 24
Finished Apr 27 04:09:02 PM PDT 24
Peak memory 208616 kb
Host smart-0dd7f9c4-0667-4746-b0e9-a24c30d99009
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275019650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.275019650
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1194992303
Short name T889
Test name
Test status
Simulation time 372755791 ps
CPU time 10.58 seconds
Started Apr 27 04:09:02 PM PDT 24
Finished Apr 27 04:09:13 PM PDT 24
Peak memory 218264 kb
Host smart-505510eb-bd53-4e44-a59b-06380f33707a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194992303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1194992303
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2808052572
Short name T960
Test name
Test status
Simulation time 1433279528 ps
CPU time 4.95 seconds
Started Apr 27 04:08:58 PM PDT 24
Finished Apr 27 04:09:04 PM PDT 24
Peak memory 206676 kb
Host smart-a46ed190-5c74-47d2-98a8-30f49f0d2363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808052572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2808052572
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.3097802858
Short name T794
Test name
Test status
Simulation time 320404568 ps
CPU time 3.18 seconds
Started Apr 27 04:09:04 PM PDT 24
Finished Apr 27 04:09:07 PM PDT 24
Peak memory 222620 kb
Host smart-c1e348e8-ca55-4b56-9b19-4e25bd978766
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097802858 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.3097802858
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3490119496
Short name T802
Test name
Test status
Simulation time 1441265781 ps
CPU time 35.55 seconds
Started Apr 27 04:09:03 PM PDT 24
Finished Apr 27 04:09:39 PM PDT 24
Peak memory 208548 kb
Host smart-09a12ce6-4ced-4ebb-bf34-4acabb799a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490119496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3490119496
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.577059223
Short name T111
Test name
Test status
Simulation time 211263696 ps
CPU time 4.97 seconds
Started Apr 27 04:09:06 PM PDT 24
Finished Apr 27 04:09:12 PM PDT 24
Peak memory 210688 kb
Host smart-c02db1c9-031e-4b6d-b3fe-f53e77b9614f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577059223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.577059223
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3910095760
Short name T714
Test name
Test status
Simulation time 13760884 ps
CPU time 0.77 seconds
Started Apr 27 04:10:56 PM PDT 24
Finished Apr 27 04:10:57 PM PDT 24
Peak memory 205792 kb
Host smart-c388bdcc-91aa-4a53-893a-4887577a9af8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910095760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3910095760
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2281950049
Short name T405
Test name
Test status
Simulation time 129140268 ps
CPU time 2.48 seconds
Started Apr 27 04:10:56 PM PDT 24
Finished Apr 27 04:10:58 PM PDT 24
Peak memory 214304 kb
Host smart-192a24b5-26f0-4075-97a2-1d43fc98da89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2281950049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2281950049
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.1548954696
Short name T31
Test name
Test status
Simulation time 1122739232 ps
CPU time 8.01 seconds
Started Apr 27 04:10:55 PM PDT 24
Finished Apr 27 04:11:03 PM PDT 24
Peak memory 222828 kb
Host smart-d9df0d23-bddd-4bd2-ba75-1b25329421dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548954696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1548954696
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4036118731
Short name T771
Test name
Test status
Simulation time 90969304 ps
CPU time 3.91 seconds
Started Apr 27 04:10:54 PM PDT 24
Finished Apr 27 04:10:58 PM PDT 24
Peak memory 209816 kb
Host smart-80a2161d-f95f-4134-8a3e-1ddff9783767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036118731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4036118731
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.442371826
Short name T297
Test name
Test status
Simulation time 52163316 ps
CPU time 2.78 seconds
Started Apr 27 04:10:55 PM PDT 24
Finished Apr 27 04:10:58 PM PDT 24
Peak memory 220044 kb
Host smart-f25c5d03-602c-4aba-9bfe-8447f300e033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442371826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.442371826
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3942525139
Short name T110
Test name
Test status
Simulation time 817667806 ps
CPU time 4.03 seconds
Started Apr 27 04:10:52 PM PDT 24
Finished Apr 27 04:10:57 PM PDT 24
Peak memory 208608 kb
Host smart-3f34f33b-2508-4942-a20a-1b79a87cf3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942525139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3942525139
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1319248919
Short name T221
Test name
Test status
Simulation time 222261280 ps
CPU time 5.57 seconds
Started Apr 27 04:10:55 PM PDT 24
Finished Apr 27 04:11:01 PM PDT 24
Peak memory 209708 kb
Host smart-55a0235a-a494-43fe-a91b-b325498e0712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319248919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1319248919
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.648633401
Short name T763
Test name
Test status
Simulation time 123099462 ps
CPU time 3.32 seconds
Started Apr 27 04:10:47 PM PDT 24
Finished Apr 27 04:10:51 PM PDT 24
Peak memory 208772 kb
Host smart-1842c7b1-22d6-405c-a414-0b0c42bd89a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648633401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.648633401
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.402922656
Short name T570
Test name
Test status
Simulation time 149069774 ps
CPU time 4.84 seconds
Started Apr 27 04:10:49 PM PDT 24
Finished Apr 27 04:10:54 PM PDT 24
Peak memory 208664 kb
Host smart-c13316d1-4cc0-4b20-ac39-646d8319c205
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402922656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.402922656
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.4415955
Short name T788
Test name
Test status
Simulation time 291512281 ps
CPU time 5.19 seconds
Started Apr 27 04:10:48 PM PDT 24
Finished Apr 27 04:10:54 PM PDT 24
Peak memory 208868 kb
Host smart-01110325-2a33-485a-a1a3-8d3423ce606a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4415955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4415955
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2483994493
Short name T187
Test name
Test status
Simulation time 83428110 ps
CPU time 3.07 seconds
Started Apr 27 04:10:53 PM PDT 24
Finished Apr 27 04:10:56 PM PDT 24
Peak memory 208988 kb
Host smart-0c49d052-b167-448f-af77-d5876bc91856
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483994493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2483994493
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3919862296
Short name T801
Test name
Test status
Simulation time 29814563 ps
CPU time 1.41 seconds
Started Apr 27 04:10:53 PM PDT 24
Finished Apr 27 04:10:55 PM PDT 24
Peak memory 207948 kb
Host smart-2140ae1e-42bb-4082-9802-e8dc54e777ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919862296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3919862296
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.4028959248
Short name T561
Test name
Test status
Simulation time 59439123 ps
CPU time 2.54 seconds
Started Apr 27 04:10:47 PM PDT 24
Finished Apr 27 04:10:51 PM PDT 24
Peak memory 208372 kb
Host smart-81321599-d762-4272-893d-34ef53435566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028959248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.4028959248
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1308718348
Short name T1063
Test name
Test status
Simulation time 926493920 ps
CPU time 34.57 seconds
Started Apr 27 04:10:54 PM PDT 24
Finished Apr 27 04:11:29 PM PDT 24
Peak memory 222496 kb
Host smart-5d1c1eb3-b7f1-4e9b-a6fa-dd195854caf2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308718348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1308718348
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.669791836
Short name T546
Test name
Test status
Simulation time 233629382 ps
CPU time 4.55 seconds
Started Apr 27 04:10:54 PM PDT 24
Finished Apr 27 04:10:59 PM PDT 24
Peak memory 220520 kb
Host smart-a0523f45-b622-47d0-a3d0-36049eeb2536
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669791836 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.669791836
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2092746916
Short name T1073
Test name
Test status
Simulation time 315730804 ps
CPU time 3.72 seconds
Started Apr 27 04:10:55 PM PDT 24
Finished Apr 27 04:10:59 PM PDT 24
Peak memory 210476 kb
Host smart-50ffda94-0bce-4b8c-861b-e8c7c7ba005c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092746916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2092746916
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2810421407
Short name T416
Test name
Test status
Simulation time 41036345 ps
CPU time 0.74 seconds
Started Apr 27 04:11:00 PM PDT 24
Finished Apr 27 04:11:01 PM PDT 24
Peak memory 205860 kb
Host smart-e5bfa669-6c55-4b57-b37e-c076df9bb980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810421407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2810421407
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3772828003
Short name T349
Test name
Test status
Simulation time 108002095 ps
CPU time 4.18 seconds
Started Apr 27 04:11:00 PM PDT 24
Finished Apr 27 04:11:04 PM PDT 24
Peak memory 214288 kb
Host smart-165cfbc1-9cdd-41c5-8bf1-ea6960320a9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3772828003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3772828003
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2799396756
Short name T898
Test name
Test status
Simulation time 948148715 ps
CPU time 4.23 seconds
Started Apr 27 04:11:02 PM PDT 24
Finished Apr 27 04:11:06 PM PDT 24
Peak memory 210112 kb
Host smart-e2451402-8b34-4d49-9b6d-934f3629c49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799396756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2799396756
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1742775339
Short name T302
Test name
Test status
Simulation time 236348801 ps
CPU time 3.37 seconds
Started Apr 27 04:10:59 PM PDT 24
Finished Apr 27 04:11:03 PM PDT 24
Peak memory 218376 kb
Host smart-90e254eb-0162-4b3f-b788-93d1f7433837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742775339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1742775339
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.223133014
Short name T1006
Test name
Test status
Simulation time 404688797 ps
CPU time 4.34 seconds
Started Apr 27 04:10:59 PM PDT 24
Finished Apr 27 04:11:03 PM PDT 24
Peak memory 208536 kb
Host smart-1aa28292-16b1-4d8d-a5d3-f4078402d29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223133014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.223133014
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.164186360
Short name T1046
Test name
Test status
Simulation time 587696595 ps
CPU time 12.42 seconds
Started Apr 27 04:11:01 PM PDT 24
Finished Apr 27 04:11:14 PM PDT 24
Peak memory 211120 kb
Host smart-a1901ecb-0d05-4167-8886-1d854dfef55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164186360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.164186360
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.4259515954
Short name T61
Test name
Test status
Simulation time 50822238 ps
CPU time 3.58 seconds
Started Apr 27 04:10:58 PM PDT 24
Finished Apr 27 04:11:02 PM PDT 24
Peak memory 222488 kb
Host smart-66b941ec-f62b-481f-88fa-a8147fa93e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4259515954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.4259515954
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3250617996
Short name T1011
Test name
Test status
Simulation time 123734520 ps
CPU time 5.48 seconds
Started Apr 27 04:11:11 PM PDT 24
Finished Apr 27 04:11:17 PM PDT 24
Peak memory 218308 kb
Host smart-da96e45a-68da-4a60-b519-cdc7973e1148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250617996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3250617996
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.279337841
Short name T727
Test name
Test status
Simulation time 332782599 ps
CPU time 3.96 seconds
Started Apr 27 04:10:53 PM PDT 24
Finished Apr 27 04:10:58 PM PDT 24
Peak memory 208556 kb
Host smart-e70a1361-edb6-47ca-a6ec-93960db6d73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279337841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.279337841
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1910757511
Short name T324
Test name
Test status
Simulation time 43726364 ps
CPU time 2.1 seconds
Started Apr 27 04:10:58 PM PDT 24
Finished Apr 27 04:11:00 PM PDT 24
Peak memory 208736 kb
Host smart-f17cc510-c6af-4f0b-adfa-6a5164fa86c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910757511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1910757511
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2754661891
Short name T816
Test name
Test status
Simulation time 78223346 ps
CPU time 3.12 seconds
Started Apr 27 04:11:00 PM PDT 24
Finished Apr 27 04:11:03 PM PDT 24
Peak memory 208552 kb
Host smart-b24aec47-eec2-4255-9566-2e32e1f797c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754661891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2754661891
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3000850724
Short name T732
Test name
Test status
Simulation time 276670704 ps
CPU time 3.79 seconds
Started Apr 27 04:10:59 PM PDT 24
Finished Apr 27 04:11:03 PM PDT 24
Peak memory 208752 kb
Host smart-c8b1cd88-91d5-462d-b082-b64acd56d5e6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000850724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3000850724
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.206110093
Short name T627
Test name
Test status
Simulation time 339001733 ps
CPU time 3.03 seconds
Started Apr 27 04:11:00 PM PDT 24
Finished Apr 27 04:11:04 PM PDT 24
Peak memory 218176 kb
Host smart-0814ba1b-6f2f-4d20-a4d6-8f2cb46c26d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206110093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.206110093
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.4002451679
Short name T628
Test name
Test status
Simulation time 4067197146 ps
CPU time 41.49 seconds
Started Apr 27 04:10:55 PM PDT 24
Finished Apr 27 04:11:37 PM PDT 24
Peak memory 208412 kb
Host smart-ac186409-d695-408e-abd7-f10cfe1760ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002451679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.4002451679
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.262390031
Short name T53
Test name
Test status
Simulation time 11376653866 ps
CPU time 132.95 seconds
Started Apr 27 04:11:01 PM PDT 24
Finished Apr 27 04:13:15 PM PDT 24
Peak memory 220360 kb
Host smart-8be2de01-3f11-4d0b-81de-c7c617c6474d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262390031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.262390031
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.1336365392
Short name T388
Test name
Test status
Simulation time 166140746 ps
CPU time 5.09 seconds
Started Apr 27 04:10:58 PM PDT 24
Finished Apr 27 04:11:04 PM PDT 24
Peak memory 220776 kb
Host smart-75f2fb64-c789-4a9a-97e3-0c6b375729e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336365392 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.1336365392
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3364811849
Short name T666
Test name
Test status
Simulation time 417630798 ps
CPU time 11.05 seconds
Started Apr 27 04:10:59 PM PDT 24
Finished Apr 27 04:11:10 PM PDT 24
Peak memory 208028 kb
Host smart-00d98a8b-350e-4b92-9b3f-5ff6ac1d92fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364811849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3364811849
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.4030137083
Short name T845
Test name
Test status
Simulation time 82071593 ps
CPU time 1.63 seconds
Started Apr 27 04:11:11 PM PDT 24
Finished Apr 27 04:11:13 PM PDT 24
Peak memory 209796 kb
Host smart-daef8148-934e-4696-9d37-f742dd944d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030137083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.4030137083
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.440550929
Short name T849
Test name
Test status
Simulation time 17653275 ps
CPU time 0.76 seconds
Started Apr 27 04:11:04 PM PDT 24
Finished Apr 27 04:11:05 PM PDT 24
Peak memory 205896 kb
Host smart-c02f928d-d63f-49e4-9c1d-6ab10ff7b903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440550929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.440550929
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1643847248
Short name T407
Test name
Test status
Simulation time 1047191875 ps
CPU time 6.93 seconds
Started Apr 27 04:11:05 PM PDT 24
Finished Apr 27 04:11:13 PM PDT 24
Peak memory 214236 kb
Host smart-62888cf1-af0d-43a2-aae7-487bca0b1917
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1643847248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1643847248
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.64264993
Short name T22
Test name
Test status
Simulation time 102766714 ps
CPU time 2.82 seconds
Started Apr 27 04:11:05 PM PDT 24
Finished Apr 27 04:11:08 PM PDT 24
Peak memory 221652 kb
Host smart-79a701c5-824d-4416-869e-ec544960d448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64264993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.64264993
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2666243023
Short name T873
Test name
Test status
Simulation time 858517803 ps
CPU time 27.09 seconds
Started Apr 27 04:11:05 PM PDT 24
Finished Apr 27 04:11:33 PM PDT 24
Peak memory 209572 kb
Host smart-4fd289f9-7af8-4cbe-a10c-7ffa3702f081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666243023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2666243023
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2274617278
Short name T1021
Test name
Test status
Simulation time 452342685 ps
CPU time 5.66 seconds
Started Apr 27 04:11:04 PM PDT 24
Finished Apr 27 04:11:11 PM PDT 24
Peak memory 219132 kb
Host smart-4aaaa613-4f21-4914-9129-d972a2ee8f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274617278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2274617278
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.396409202
Short name T704
Test name
Test status
Simulation time 90729488 ps
CPU time 4.3 seconds
Started Apr 27 04:11:06 PM PDT 24
Finished Apr 27 04:11:11 PM PDT 24
Peak memory 209292 kb
Host smart-b92b3ec5-98a8-41a4-8c10-44bc545966ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396409202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.396409202
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.172980183
Short name T867
Test name
Test status
Simulation time 225405272 ps
CPU time 3.76 seconds
Started Apr 27 04:11:03 PM PDT 24
Finished Apr 27 04:11:07 PM PDT 24
Peak memory 207560 kb
Host smart-8de75073-104d-4f1d-a70f-58361463159d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172980183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.172980183
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2581818056
Short name T309
Test name
Test status
Simulation time 34016715 ps
CPU time 2.47 seconds
Started Apr 27 04:10:58 PM PDT 24
Finished Apr 27 04:11:01 PM PDT 24
Peak memory 206832 kb
Host smart-ab828293-622e-4a33-872f-e639edf35131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581818056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2581818056
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1943421410
Short name T630
Test name
Test status
Simulation time 153170259 ps
CPU time 2.43 seconds
Started Apr 27 04:10:58 PM PDT 24
Finished Apr 27 04:11:01 PM PDT 24
Peak memory 206712 kb
Host smart-da9f2d04-7f5c-4729-8705-8cfb7f8b41cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943421410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1943421410
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.612784367
Short name T1057
Test name
Test status
Simulation time 40074082 ps
CPU time 2.11 seconds
Started Apr 27 04:11:01 PM PDT 24
Finished Apr 27 04:11:04 PM PDT 24
Peak memory 207624 kb
Host smart-37233d09-f3e5-44c8-b233-960b73dfadf2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612784367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.612784367
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1860788292
Short name T652
Test name
Test status
Simulation time 39706860 ps
CPU time 2.33 seconds
Started Apr 27 04:11:02 PM PDT 24
Finished Apr 27 04:11:05 PM PDT 24
Peak memory 206940 kb
Host smart-457e758a-3cc3-42c1-a128-f96ba2a294dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860788292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1860788292
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3879240374
Short name T357
Test name
Test status
Simulation time 77955946 ps
CPU time 3.59 seconds
Started Apr 27 04:11:04 PM PDT 24
Finished Apr 27 04:11:08 PM PDT 24
Peak memory 209852 kb
Host smart-c3c9512a-0f18-4069-aebe-2f1c670cf5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879240374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3879240374
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1667480570
Short name T705
Test name
Test status
Simulation time 115370887 ps
CPU time 2.67 seconds
Started Apr 27 04:10:57 PM PDT 24
Finished Apr 27 04:11:00 PM PDT 24
Peak memory 206600 kb
Host smart-c212d661-18b0-4646-aa61-90ebeafc5c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667480570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1667480570
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.4136839946
Short name T238
Test name
Test status
Simulation time 9528977501 ps
CPU time 59.63 seconds
Started Apr 27 04:11:08 PM PDT 24
Finished Apr 27 04:12:08 PM PDT 24
Peak memory 222380 kb
Host smart-6fed1106-cb7d-43c5-b171-549586fdcdf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136839946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.4136839946
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.326173048
Short name T748
Test name
Test status
Simulation time 367092003 ps
CPU time 7.61 seconds
Started Apr 27 04:11:05 PM PDT 24
Finished Apr 27 04:11:13 PM PDT 24
Peak memory 222588 kb
Host smart-b805a61c-8e27-4a4d-9253-65993f6810ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326173048 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.326173048
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3777366771
Short name T1051
Test name
Test status
Simulation time 50689380 ps
CPU time 3.47 seconds
Started Apr 27 04:11:05 PM PDT 24
Finished Apr 27 04:11:09 PM PDT 24
Peak memory 207604 kb
Host smart-00203207-5cb4-4620-aaff-58ecc09dc802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777366771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3777366771
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3156616782
Short name T172
Test name
Test status
Simulation time 91549582 ps
CPU time 1.61 seconds
Started Apr 27 04:11:09 PM PDT 24
Finished Apr 27 04:11:11 PM PDT 24
Peak memory 209760 kb
Host smart-250fe795-ea95-480d-a22b-d8ea3f72a4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156616782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3156616782
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1930844518
Short name T655
Test name
Test status
Simulation time 24782723 ps
CPU time 0.76 seconds
Started Apr 27 04:11:13 PM PDT 24
Finished Apr 27 04:11:14 PM PDT 24
Peak memory 205792 kb
Host smart-bfd1af43-8fc4-4162-a88c-32d982cc6d3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930844518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1930844518
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1757400825
Short name T347
Test name
Test status
Simulation time 255067197 ps
CPU time 12.84 seconds
Started Apr 27 04:11:06 PM PDT 24
Finished Apr 27 04:11:19 PM PDT 24
Peak memory 215212 kb
Host smart-4bfa317b-781f-46a4-ba4d-a2b66d476dd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1757400825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1757400825
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3024081143
Short name T75
Test name
Test status
Simulation time 210347126 ps
CPU time 2.37 seconds
Started Apr 27 04:11:12 PM PDT 24
Finished Apr 27 04:11:14 PM PDT 24
Peak memory 208440 kb
Host smart-ee77f799-20f3-4990-99d6-096b2812b952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3024081143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3024081143
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.45032541
Short name T78
Test name
Test status
Simulation time 39789751 ps
CPU time 1.75 seconds
Started Apr 27 04:11:05 PM PDT 24
Finished Apr 27 04:11:07 PM PDT 24
Peak memory 209156 kb
Host smart-b543732e-7342-4b49-872c-1b467b58a632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45032541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.45032541
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3404495518
Short name T887
Test name
Test status
Simulation time 152091731 ps
CPU time 4.46 seconds
Started Apr 27 04:11:09 PM PDT 24
Finished Apr 27 04:11:14 PM PDT 24
Peak memory 214340 kb
Host smart-bf026c99-93f5-4b3d-bf19-1b446c1a93f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404495518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3404495518
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1719978724
Short name T679
Test name
Test status
Simulation time 230453403 ps
CPU time 2.95 seconds
Started Apr 27 04:11:11 PM PDT 24
Finished Apr 27 04:11:15 PM PDT 24
Peak memory 220164 kb
Host smart-1fe944db-07d0-4392-9e87-7d5f3dc59d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719978724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1719978724
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3782919266
Short name T559
Test name
Test status
Simulation time 29547802 ps
CPU time 2.33 seconds
Started Apr 27 04:11:04 PM PDT 24
Finished Apr 27 04:11:07 PM PDT 24
Peak memory 207152 kb
Host smart-e410eca8-0cd5-48fa-af40-d30ef5e536bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782919266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3782919266
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1572418745
Short name T1053
Test name
Test status
Simulation time 1984692806 ps
CPU time 36.82 seconds
Started Apr 27 04:11:04 PM PDT 24
Finished Apr 27 04:11:41 PM PDT 24
Peak memory 209064 kb
Host smart-26bd865e-9532-411c-88ef-5920f8f5f6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572418745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1572418745
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3599351918
Short name T879
Test name
Test status
Simulation time 54994310 ps
CPU time 2.88 seconds
Started Apr 27 04:11:04 PM PDT 24
Finished Apr 27 04:11:07 PM PDT 24
Peak memory 206984 kb
Host smart-1b6f5de3-d26e-4adf-8e25-4512b4fe9a3c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599351918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3599351918
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1394724879
Short name T621
Test name
Test status
Simulation time 1292827423 ps
CPU time 9.31 seconds
Started Apr 27 04:11:04 PM PDT 24
Finished Apr 27 04:11:14 PM PDT 24
Peak memory 208788 kb
Host smart-7b722665-edc0-4e54-aaaf-600facb74acb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394724879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1394724879
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1340147392
Short name T663
Test name
Test status
Simulation time 33977329 ps
CPU time 2.23 seconds
Started Apr 27 04:11:04 PM PDT 24
Finished Apr 27 04:11:07 PM PDT 24
Peak memory 208788 kb
Host smart-aa29b946-f1f0-4309-b871-e35879e3da06
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340147392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1340147392
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.4074689976
Short name T689
Test name
Test status
Simulation time 69475920 ps
CPU time 1.99 seconds
Started Apr 27 04:11:11 PM PDT 24
Finished Apr 27 04:11:13 PM PDT 24
Peak memory 209324 kb
Host smart-c5ed8542-e5d3-4ff8-a77e-3fe01c482009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074689976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.4074689976
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1996342224
Short name T594
Test name
Test status
Simulation time 273907187 ps
CPU time 8.52 seconds
Started Apr 27 04:11:05 PM PDT 24
Finished Apr 27 04:11:14 PM PDT 24
Peak memory 207828 kb
Host smart-4dacdb30-6821-4612-83da-ad034a1cc034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996342224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1996342224
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2934785346
Short name T241
Test name
Test status
Simulation time 1124538845 ps
CPU time 22.14 seconds
Started Apr 27 04:11:08 PM PDT 24
Finished Apr 27 04:11:31 PM PDT 24
Peak memory 222476 kb
Host smart-ce0fff51-8b41-4bda-a619-aa3a3c70fbd5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934785346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2934785346
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2034076301
Short name T880
Test name
Test status
Simulation time 159382113 ps
CPU time 3.18 seconds
Started Apr 27 04:11:11 PM PDT 24
Finished Apr 27 04:11:15 PM PDT 24
Peak memory 222604 kb
Host smart-c771db82-3f86-4ffc-b38a-e231fdec2128
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034076301 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2034076301
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.528695093
Short name T30
Test name
Test status
Simulation time 17102895940 ps
CPU time 41.84 seconds
Started Apr 27 04:11:09 PM PDT 24
Finished Apr 27 04:11:51 PM PDT 24
Peak memory 209508 kb
Host smart-758368be-65d9-440e-bb8b-c4e18c48f85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528695093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.528695093
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1418410185
Short name T629
Test name
Test status
Simulation time 209277120 ps
CPU time 3.07 seconds
Started Apr 27 04:11:13 PM PDT 24
Finished Apr 27 04:11:17 PM PDT 24
Peak memory 209996 kb
Host smart-237669e9-f58e-4565-a72b-fa0d3f760f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418410185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1418410185
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1411386658
Short name T700
Test name
Test status
Simulation time 19179904 ps
CPU time 0.77 seconds
Started Apr 27 04:11:16 PM PDT 24
Finished Apr 27 04:11:17 PM PDT 24
Peak memory 205884 kb
Host smart-c34a52f4-b9a5-45b1-a3dd-885619800e5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411386658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1411386658
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1767207927
Short name T395
Test name
Test status
Simulation time 277320650 ps
CPU time 14.16 seconds
Started Apr 27 04:11:11 PM PDT 24
Finished Apr 27 04:11:26 PM PDT 24
Peak memory 214308 kb
Host smart-fc104f80-bb48-4833-9675-c45886b5e050
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1767207927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1767207927
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2016210640
Short name T858
Test name
Test status
Simulation time 186423376 ps
CPU time 3.19 seconds
Started Apr 27 04:11:14 PM PDT 24
Finished Apr 27 04:11:17 PM PDT 24
Peak memory 221828 kb
Host smart-9e3029d2-6302-4e89-b849-5343881bf749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016210640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2016210640
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3957318148
Short name T80
Test name
Test status
Simulation time 149065566 ps
CPU time 2.63 seconds
Started Apr 27 04:11:11 PM PDT 24
Finished Apr 27 04:11:14 PM PDT 24
Peak memory 218164 kb
Host smart-4248193d-d336-483c-8396-77e9f932b153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957318148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3957318148
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.436622717
Short name T633
Test name
Test status
Simulation time 2203944692 ps
CPU time 58.22 seconds
Started Apr 27 04:11:10 PM PDT 24
Finished Apr 27 04:12:09 PM PDT 24
Peak memory 214292 kb
Host smart-ed5a3195-cbaa-4783-9679-b77f515c1ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436622717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.436622717
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.706436012
Short name T885
Test name
Test status
Simulation time 151500129 ps
CPU time 1.69 seconds
Started Apr 27 04:11:09 PM PDT 24
Finished Apr 27 04:11:11 PM PDT 24
Peak memory 206116 kb
Host smart-01fbdf28-9936-459b-997d-b608d9e8c74d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706436012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.706436012
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2710083169
Short name T894
Test name
Test status
Simulation time 543214204 ps
CPU time 5.75 seconds
Started Apr 27 04:11:13 PM PDT 24
Finished Apr 27 04:11:19 PM PDT 24
Peak memory 214316 kb
Host smart-994e75e9-de19-4b40-a940-2a06b581bfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710083169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2710083169
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3370378562
Short name T383
Test name
Test status
Simulation time 785166580 ps
CPU time 3.23 seconds
Started Apr 27 04:11:11 PM PDT 24
Finished Apr 27 04:11:15 PM PDT 24
Peak memory 206824 kb
Host smart-6fd224b6-c210-4b35-b402-e396f411c956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370378562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3370378562
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3683340139
Short name T761
Test name
Test status
Simulation time 136256318 ps
CPU time 2.69 seconds
Started Apr 27 04:11:10 PM PDT 24
Finished Apr 27 04:11:13 PM PDT 24
Peak memory 208756 kb
Host smart-f020dccc-0808-4047-bfcf-37c7bc238032
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683340139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3683340139
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1500667372
Short name T638
Test name
Test status
Simulation time 206936100 ps
CPU time 3.08 seconds
Started Apr 27 04:11:11 PM PDT 24
Finished Apr 27 04:11:15 PM PDT 24
Peak memory 207972 kb
Host smart-15819662-056c-4a46-b59c-f3f82a799a32
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500667372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1500667372
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1352702179
Short name T1059
Test name
Test status
Simulation time 2435559477 ps
CPU time 7.06 seconds
Started Apr 27 04:11:10 PM PDT 24
Finished Apr 27 04:11:17 PM PDT 24
Peak memory 208692 kb
Host smart-aaaf7a06-8b96-4809-ba9f-856f49eab941
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352702179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1352702179
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3514528862
Short name T263
Test name
Test status
Simulation time 549847030 ps
CPU time 3.9 seconds
Started Apr 27 04:11:10 PM PDT 24
Finished Apr 27 04:11:15 PM PDT 24
Peak memory 214428 kb
Host smart-aaa23ab6-6421-421b-9cf6-efc3236cd019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514528862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3514528862
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2861501762
Short name T874
Test name
Test status
Simulation time 107171365 ps
CPU time 3.03 seconds
Started Apr 27 04:11:10 PM PDT 24
Finished Apr 27 04:11:13 PM PDT 24
Peak memory 208256 kb
Host smart-06f4714f-ab4d-4e80-8112-c1a2316413c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861501762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2861501762
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3854002245
Short name T264
Test name
Test status
Simulation time 4204375652 ps
CPU time 46.46 seconds
Started Apr 27 04:11:14 PM PDT 24
Finished Apr 27 04:12:01 PM PDT 24
Peak memory 217060 kb
Host smart-6137d088-731f-489b-84fa-83933203d9ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854002245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3854002245
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.466302787
Short name T215
Test name
Test status
Simulation time 117540838 ps
CPU time 6.17 seconds
Started Apr 27 04:11:12 PM PDT 24
Finished Apr 27 04:11:19 PM PDT 24
Peak memory 222588 kb
Host smart-0832fd25-4168-4ed6-aa7d-1e053759b1eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466302787 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.466302787
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.224016431
Short name T668
Test name
Test status
Simulation time 66385056 ps
CPU time 2.67 seconds
Started Apr 27 04:11:13 PM PDT 24
Finished Apr 27 04:11:16 PM PDT 24
Peak memory 208328 kb
Host smart-a6201b2a-600d-4264-bb87-9044ed024071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224016431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.224016431
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.964069232
Short name T733
Test name
Test status
Simulation time 50974902 ps
CPU time 2.18 seconds
Started Apr 27 04:11:14 PM PDT 24
Finished Apr 27 04:11:16 PM PDT 24
Peak memory 210220 kb
Host smart-50f8f397-ebc2-49a8-8032-ec0db5f0136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964069232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.964069232
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2150191426
Short name T707
Test name
Test status
Simulation time 56763269 ps
CPU time 0.87 seconds
Started Apr 27 04:11:24 PM PDT 24
Finished Apr 27 04:11:25 PM PDT 24
Peak memory 205904 kb
Host smart-cdf4bf29-568f-4e5b-b929-c868d4310271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150191426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2150191426
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.772627146
Short name T109
Test name
Test status
Simulation time 4967093903 ps
CPU time 63.48 seconds
Started Apr 27 04:11:18 PM PDT 24
Finished Apr 27 04:12:22 PM PDT 24
Peak memory 214420 kb
Host smart-f231081b-f7e1-4b92-84e9-307e26817fb2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=772627146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.772627146
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.89057404
Short name T819
Test name
Test status
Simulation time 181841955 ps
CPU time 1.95 seconds
Started Apr 27 04:11:19 PM PDT 24
Finished Apr 27 04:11:21 PM PDT 24
Peak memory 216480 kb
Host smart-9433ac95-1fe2-4b58-8de7-8d183928c27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89057404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.89057404
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2807534070
Short name T314
Test name
Test status
Simulation time 116761632 ps
CPU time 4.53 seconds
Started Apr 27 04:11:20 PM PDT 24
Finished Apr 27 04:11:25 PM PDT 24
Peak memory 209060 kb
Host smart-65277075-0529-486d-9caa-d002fb9cff42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807534070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2807534070
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3687167601
Short name T258
Test name
Test status
Simulation time 174105694 ps
CPU time 3.74 seconds
Started Apr 27 04:11:19 PM PDT 24
Finished Apr 27 04:11:23 PM PDT 24
Peak memory 220356 kb
Host smart-8e35c8e6-8d01-4915-8942-f7be2264bfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687167601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3687167601
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2406830260
Short name T557
Test name
Test status
Simulation time 1436615941 ps
CPU time 40.68 seconds
Started Apr 27 04:11:25 PM PDT 24
Finished Apr 27 04:12:06 PM PDT 24
Peak memory 219796 kb
Host smart-5c7b6a2a-e4a9-46b4-8dd9-90edd0cfdfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406830260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2406830260
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.209766086
Short name T969
Test name
Test status
Simulation time 242441927 ps
CPU time 3.73 seconds
Started Apr 27 04:11:14 PM PDT 24
Finished Apr 27 04:11:18 PM PDT 24
Peak memory 207952 kb
Host smart-0fed4603-5c4e-4d67-9776-2bc4c0de6a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209766086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.209766086
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.714636431
Short name T855
Test name
Test status
Simulation time 363804839 ps
CPU time 7.19 seconds
Started Apr 27 04:11:15 PM PDT 24
Finished Apr 27 04:11:22 PM PDT 24
Peak memory 209064 kb
Host smart-15840abd-f3c0-4d76-8f91-00d1023d3da3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714636431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.714636431
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1228351079
Short name T918
Test name
Test status
Simulation time 2169273205 ps
CPU time 6.52 seconds
Started Apr 27 04:11:14 PM PDT 24
Finished Apr 27 04:11:21 PM PDT 24
Peak memory 208560 kb
Host smart-40c03ab9-838f-4500-8033-5c94feb9586e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228351079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1228351079
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1112930457
Short name T16
Test name
Test status
Simulation time 1223805991 ps
CPU time 3.51 seconds
Started Apr 27 04:11:14 PM PDT 24
Finished Apr 27 04:11:18 PM PDT 24
Peak memory 206740 kb
Host smart-8caf17b1-c4f8-48c4-8bce-61ddb0b9c5ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112930457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1112930457
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1140673617
Short name T693
Test name
Test status
Simulation time 312144243 ps
CPU time 2.34 seconds
Started Apr 27 04:11:22 PM PDT 24
Finished Apr 27 04:11:25 PM PDT 24
Peak memory 209520 kb
Host smart-ca76f44e-b7dd-4afc-a3ad-000afa9d4500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140673617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1140673617
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.944258289
Short name T189
Test name
Test status
Simulation time 416682956 ps
CPU time 5.61 seconds
Started Apr 27 04:11:25 PM PDT 24
Finished Apr 27 04:11:31 PM PDT 24
Peak memory 207708 kb
Host smart-abe09935-5d3a-4c52-877d-89ef37db2a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944258289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.944258289
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2903257911
Short name T1065
Test name
Test status
Simulation time 2390787745 ps
CPU time 60.81 seconds
Started Apr 27 04:11:24 PM PDT 24
Finished Apr 27 04:12:26 PM PDT 24
Peak memory 222488 kb
Host smart-14f0ebe2-2dfe-4f2e-ad28-c99de1cdcfd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903257911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2903257911
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.1201912620
Short name T381
Test name
Test status
Simulation time 228110514 ps
CPU time 6.6 seconds
Started Apr 27 04:11:19 PM PDT 24
Finished Apr 27 04:11:26 PM PDT 24
Peak memory 219820 kb
Host smart-915c4bfe-169d-4ad4-82da-96bae217792d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201912620 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.1201912620
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1141151747
Short name T345
Test name
Test status
Simulation time 426661575 ps
CPU time 6.02 seconds
Started Apr 27 04:11:22 PM PDT 24
Finished Apr 27 04:11:29 PM PDT 24
Peak memory 209680 kb
Host smart-ffda1aa4-14ce-419e-b13a-b3944e00abc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141151747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1141151747
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3260371304
Short name T776
Test name
Test status
Simulation time 9419431 ps
CPU time 0.75 seconds
Started Apr 27 04:11:26 PM PDT 24
Finished Apr 27 04:11:27 PM PDT 24
Peak memory 205852 kb
Host smart-cc8647ab-4af6-4ab9-ac83-30ea3ccc6f62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260371304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3260371304
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3436104513
Short name T957
Test name
Test status
Simulation time 137597804 ps
CPU time 3.12 seconds
Started Apr 27 04:11:26 PM PDT 24
Finished Apr 27 04:11:30 PM PDT 24
Peak memory 215024 kb
Host smart-fee4253d-f6a2-4f1e-8cbf-d0087d77404c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3436104513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3436104513
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.243786406
Short name T795
Test name
Test status
Simulation time 754572963 ps
CPU time 3.8 seconds
Started Apr 27 04:11:26 PM PDT 24
Finished Apr 27 04:11:30 PM PDT 24
Peak memory 214332 kb
Host smart-9d52a03a-e03d-41ce-8ae6-a4d39aafff15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243786406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.243786406
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.4077415451
Short name T380
Test name
Test status
Simulation time 95393059 ps
CPU time 1.71 seconds
Started Apr 27 04:11:26 PM PDT 24
Finished Apr 27 04:11:28 PM PDT 24
Peak memory 207068 kb
Host smart-6019b500-5b6c-45ce-97b9-59ee90460aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077415451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.4077415451
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1955549559
Short name T90
Test name
Test status
Simulation time 991167535 ps
CPU time 7.4 seconds
Started Apr 27 04:11:25 PM PDT 24
Finished Apr 27 04:11:33 PM PDT 24
Peak memory 214336 kb
Host smart-06ff6bb1-7035-4470-9bb7-de7603667094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955549559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1955549559
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3577902849
Short name T366
Test name
Test status
Simulation time 641512699 ps
CPU time 8.8 seconds
Started Apr 27 04:11:26 PM PDT 24
Finished Apr 27 04:11:35 PM PDT 24
Peak memory 222348 kb
Host smart-2db5a6d2-81ae-40ec-93e7-558aeae7fe9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577902849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3577902849
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_random.1472264320
Short name T351
Test name
Test status
Simulation time 142582665 ps
CPU time 4.49 seconds
Started Apr 27 04:11:24 PM PDT 24
Finished Apr 27 04:11:29 PM PDT 24
Peak memory 218464 kb
Host smart-5334bb2b-6c3b-455c-8c06-576f3881f2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472264320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1472264320
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.972459868
Short name T851
Test name
Test status
Simulation time 262871377 ps
CPU time 4.34 seconds
Started Apr 27 04:11:20 PM PDT 24
Finished Apr 27 04:11:24 PM PDT 24
Peak memory 208944 kb
Host smart-80d138fb-3cd7-48be-aed6-53532fb2c67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972459868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.972459868
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1534384032
Short name T678
Test name
Test status
Simulation time 364023162 ps
CPU time 6.9 seconds
Started Apr 27 04:11:21 PM PDT 24
Finished Apr 27 04:11:28 PM PDT 24
Peak memory 206972 kb
Host smart-9f6381d4-674c-49cb-a691-7423c752b6c8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534384032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1534384032
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3453932073
Short name T964
Test name
Test status
Simulation time 19177183810 ps
CPU time 59.46 seconds
Started Apr 27 04:11:18 PM PDT 24
Finished Apr 27 04:12:18 PM PDT 24
Peak memory 209208 kb
Host smart-61e32950-fecf-4efa-bf5c-927a7acd6abf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453932073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3453932073
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3676724601
Short name T233
Test name
Test status
Simulation time 53204364 ps
CPU time 2.21 seconds
Started Apr 27 04:11:20 PM PDT 24
Finished Apr 27 04:11:23 PM PDT 24
Peak memory 208452 kb
Host smart-14da0b05-db8f-4d27-8c77-b535befa2c6a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676724601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3676724601
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3316777167
Short name T552
Test name
Test status
Simulation time 63947906 ps
CPU time 2.62 seconds
Started Apr 27 04:11:27 PM PDT 24
Finished Apr 27 04:11:30 PM PDT 24
Peak memory 209348 kb
Host smart-da2f24fa-ca9d-435f-ab6e-88cdfe243507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316777167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3316777167
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.297700248
Short name T554
Test name
Test status
Simulation time 922026124 ps
CPU time 9.25 seconds
Started Apr 27 04:11:19 PM PDT 24
Finished Apr 27 04:11:28 PM PDT 24
Peak memory 206708 kb
Host smart-21b8155b-a058-47de-a7f2-20c95a1e5794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297700248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.297700248
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.3533807554
Short name T828
Test name
Test status
Simulation time 2631787785 ps
CPU time 82.77 seconds
Started Apr 27 04:11:23 PM PDT 24
Finished Apr 27 04:12:46 PM PDT 24
Peak memory 222564 kb
Host smart-c722ad9e-80b2-496b-bddd-de211c7c17be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533807554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.3533807554
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1476694070
Short name T245
Test name
Test status
Simulation time 44815685 ps
CPU time 2.78 seconds
Started Apr 27 04:11:26 PM PDT 24
Finished Apr 27 04:11:30 PM PDT 24
Peak memory 209452 kb
Host smart-8e4a60dd-8a84-48d2-8d74-429a4dde4a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476694070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1476694070
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3850492542
Short name T740
Test name
Test status
Simulation time 34462301 ps
CPU time 2 seconds
Started Apr 27 04:11:30 PM PDT 24
Finished Apr 27 04:11:33 PM PDT 24
Peak memory 209688 kb
Host smart-fcd61013-59c8-485d-93f6-42e42337b8c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850492542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3850492542
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2905987493
Short name T619
Test name
Test status
Simulation time 10876112 ps
CPU time 0.76 seconds
Started Apr 27 04:11:30 PM PDT 24
Finished Apr 27 04:11:32 PM PDT 24
Peak memory 205804 kb
Host smart-9850b2c6-61bc-40c8-93ec-7e9c909adbbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905987493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2905987493
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.469913149
Short name T955
Test name
Test status
Simulation time 766951878 ps
CPU time 3.45 seconds
Started Apr 27 04:11:26 PM PDT 24
Finished Apr 27 04:11:30 PM PDT 24
Peak memory 214308 kb
Host smart-516ae7a7-551d-457c-b979-cc6594082792
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=469913149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.469913149
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1657622312
Short name T949
Test name
Test status
Simulation time 306367623 ps
CPU time 5.99 seconds
Started Apr 27 04:11:32 PM PDT 24
Finished Apr 27 04:11:38 PM PDT 24
Peak memory 218476 kb
Host smart-8a5dcdd7-3af4-4af2-8fda-0d064862565d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657622312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1657622312
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.679986024
Short name T343
Test name
Test status
Simulation time 180581457 ps
CPU time 6.98 seconds
Started Apr 27 04:11:23 PM PDT 24
Finished Apr 27 04:11:30 PM PDT 24
Peak memory 209420 kb
Host smart-f5e23435-f12a-4de9-abbe-0495ac6ad453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679986024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.679986024
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2578040900
Short name T72
Test name
Test status
Simulation time 82588199 ps
CPU time 4.39 seconds
Started Apr 27 04:11:25 PM PDT 24
Finished Apr 27 04:11:29 PM PDT 24
Peak memory 209828 kb
Host smart-21f51e74-c225-4e54-9013-f76c58fdea71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578040900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2578040900
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.553443856
Short name T709
Test name
Test status
Simulation time 59438359 ps
CPU time 3.75 seconds
Started Apr 27 04:11:24 PM PDT 24
Finished Apr 27 04:11:28 PM PDT 24
Peak memory 207940 kb
Host smart-e8a5e0b3-2579-4b61-b8ce-91d134f4658b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=553443856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.553443856
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.4206901095
Short name T344
Test name
Test status
Simulation time 239761594 ps
CPU time 3.32 seconds
Started Apr 27 04:11:25 PM PDT 24
Finished Apr 27 04:11:28 PM PDT 24
Peak memory 208588 kb
Host smart-19cf5b25-1c3f-446f-acb3-222977d7e2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206901095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4206901095
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2819645674
Short name T1031
Test name
Test status
Simulation time 262540498 ps
CPU time 3.79 seconds
Started Apr 27 04:11:24 PM PDT 24
Finished Apr 27 04:11:28 PM PDT 24
Peak memory 208736 kb
Host smart-61c360ce-4bde-46fd-9269-5d4d313c3aa6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819645674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2819645674
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2818119781
Short name T959
Test name
Test status
Simulation time 811764822 ps
CPU time 8.99 seconds
Started Apr 27 04:11:27 PM PDT 24
Finished Apr 27 04:11:37 PM PDT 24
Peak memory 208380 kb
Host smart-d24f8c4d-f8f2-4859-8ff4-72be1ecc4d76
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818119781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2818119781
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4095730357
Short name T950
Test name
Test status
Simulation time 227464294 ps
CPU time 9.05 seconds
Started Apr 27 04:11:26 PM PDT 24
Finished Apr 27 04:11:35 PM PDT 24
Peak memory 208460 kb
Host smart-1671f19c-daf8-47a4-88d5-cdf583d74f5d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095730357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4095730357
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.680272649
Short name T919
Test name
Test status
Simulation time 1205208861 ps
CPU time 2.54 seconds
Started Apr 27 04:11:31 PM PDT 24
Finished Apr 27 04:11:34 PM PDT 24
Peak memory 208004 kb
Host smart-e884bded-084f-405b-831f-160de42815b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680272649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.680272649
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2283439394
Short name T839
Test name
Test status
Simulation time 729824862 ps
CPU time 17.5 seconds
Started Apr 27 04:11:24 PM PDT 24
Finished Apr 27 04:11:42 PM PDT 24
Peak memory 207936 kb
Host smart-605a7598-5afb-443a-b4f5-a8aa2389d90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283439394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2283439394
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1234518200
Short name T966
Test name
Test status
Simulation time 74028983 ps
CPU time 2.43 seconds
Started Apr 27 04:11:32 PM PDT 24
Finished Apr 27 04:11:35 PM PDT 24
Peak memory 222604 kb
Host smart-1f75222a-3904-4f80-8237-3f6a5c19c68b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234518200 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1234518200
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.166067255
Short name T777
Test name
Test status
Simulation time 458708174 ps
CPU time 5.56 seconds
Started Apr 27 04:11:24 PM PDT 24
Finished Apr 27 04:11:30 PM PDT 24
Peak memory 218432 kb
Host smart-06e43f7e-0c93-4395-b5a8-c88c77dec3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166067255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.166067255
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2028722107
Short name T610
Test name
Test status
Simulation time 43844677 ps
CPU time 1.97 seconds
Started Apr 27 04:11:31 PM PDT 24
Finished Apr 27 04:11:33 PM PDT 24
Peak memory 209932 kb
Host smart-0d02b95c-d8ba-4351-9b08-2b317aacc727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028722107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2028722107
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2012071233
Short name T865
Test name
Test status
Simulation time 42703126 ps
CPU time 0.77 seconds
Started Apr 27 04:11:37 PM PDT 24
Finished Apr 27 04:11:38 PM PDT 24
Peak memory 205816 kb
Host smart-fdc81c2e-6edb-47ba-a6d8-89df2d53b6f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012071233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2012071233
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1340421493
Short name T406
Test name
Test status
Simulation time 310938009 ps
CPU time 15.56 seconds
Started Apr 27 04:11:29 PM PDT 24
Finished Apr 27 04:11:45 PM PDT 24
Peak memory 214304 kb
Host smart-238ae20a-dc36-43cd-880e-c7909fdec4d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1340421493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1340421493
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1595647784
Short name T24
Test name
Test status
Simulation time 157913863 ps
CPU time 1.88 seconds
Started Apr 27 04:11:37 PM PDT 24
Finished Apr 27 04:11:40 PM PDT 24
Peak memory 209924 kb
Host smart-f3871a6c-796e-4bfb-9aa0-bfb46a19b08c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595647784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1595647784
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1162575936
Short name T77
Test name
Test status
Simulation time 695613308 ps
CPU time 14.78 seconds
Started Apr 27 04:11:31 PM PDT 24
Finished Apr 27 04:11:46 PM PDT 24
Peak memory 208564 kb
Host smart-2fa39ed6-dcfb-4025-953d-f5ef381554b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162575936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1162575936
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1653243282
Short name T870
Test name
Test status
Simulation time 123714910 ps
CPU time 2.53 seconds
Started Apr 27 04:11:46 PM PDT 24
Finished Apr 27 04:11:49 PM PDT 24
Peak memory 209572 kb
Host smart-8d7ced50-85cf-4898-9f78-b6f9fe081327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653243282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1653243282
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2370932585
Short name T338
Test name
Test status
Simulation time 8659248804 ps
CPU time 52.65 seconds
Started Apr 27 04:11:36 PM PDT 24
Finished Apr 27 04:12:29 PM PDT 24
Peak memory 218536 kb
Host smart-5535f74c-c48a-4341-9d4c-da0aed534842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370932585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2370932585
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_random.2735511015
Short name T313
Test name
Test status
Simulation time 135881879 ps
CPU time 5.92 seconds
Started Apr 27 04:11:30 PM PDT 24
Finished Apr 27 04:11:37 PM PDT 24
Peak memory 214236 kb
Host smart-5ca7460b-d7e4-4052-abfe-33732bc47820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735511015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2735511015
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.19113191
Short name T295
Test name
Test status
Simulation time 108418242 ps
CPU time 3.12 seconds
Started Apr 27 04:11:32 PM PDT 24
Finished Apr 27 04:11:35 PM PDT 24
Peak memory 208964 kb
Host smart-0c9b3258-d75c-4c1b-849f-6301c8297f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19113191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.19113191
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3477901886
Short name T686
Test name
Test status
Simulation time 190617231 ps
CPU time 6.07 seconds
Started Apr 27 04:11:53 PM PDT 24
Finished Apr 27 04:12:00 PM PDT 24
Peak memory 208644 kb
Host smart-29487a08-2576-49ee-8478-ef0f30b09216
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477901886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3477901886
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3519558001
Short name T659
Test name
Test status
Simulation time 58751304 ps
CPU time 3.05 seconds
Started Apr 27 04:11:30 PM PDT 24
Finished Apr 27 04:11:33 PM PDT 24
Peak memory 206924 kb
Host smart-1ba0b5ac-3122-429e-8b1b-473a27bbb5c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519558001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3519558001
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2324381995
Short name T829
Test name
Test status
Simulation time 92208121 ps
CPU time 1.92 seconds
Started Apr 27 04:11:31 PM PDT 24
Finished Apr 27 04:11:33 PM PDT 24
Peak memory 206836 kb
Host smart-6f156fa2-5402-418c-81d1-59c6d67daae3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324381995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2324381995
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3158781711
Short name T833
Test name
Test status
Simulation time 67103759 ps
CPU time 2.58 seconds
Started Apr 27 04:11:36 PM PDT 24
Finished Apr 27 04:11:39 PM PDT 24
Peak memory 208684 kb
Host smart-bb5b13ab-0e2a-4e9e-b9c4-6e70c36c3cdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158781711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3158781711
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1106936382
Short name T1022
Test name
Test status
Simulation time 60135061 ps
CPU time 2.26 seconds
Started Apr 27 04:11:30 PM PDT 24
Finished Apr 27 04:11:33 PM PDT 24
Peak memory 206644 kb
Host smart-24a17e1a-6d93-4f8e-9bdd-d6731b0323ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106936382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1106936382
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.168711966
Short name T758
Test name
Test status
Simulation time 577103725 ps
CPU time 5.56 seconds
Started Apr 27 04:11:47 PM PDT 24
Finished Apr 27 04:11:54 PM PDT 24
Peak memory 222608 kb
Host smart-65b55f7e-fef0-4d33-b815-3d75393a36cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168711966 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.168711966
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2936929118
Short name T248
Test name
Test status
Simulation time 1347695319 ps
CPU time 9.57 seconds
Started Apr 27 04:11:32 PM PDT 24
Finished Apr 27 04:11:42 PM PDT 24
Peak memory 208888 kb
Host smart-7d5274e9-25da-4221-b5bc-27f6bff0f329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936929118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2936929118
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.368649566
Short name T165
Test name
Test status
Simulation time 504490116 ps
CPU time 6.25 seconds
Started Apr 27 04:11:37 PM PDT 24
Finished Apr 27 04:11:44 PM PDT 24
Peak memory 210236 kb
Host smart-8832681a-d04f-4f7d-9e7a-4ee9030eba53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368649566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.368649566
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1684931700
Short name T954
Test name
Test status
Simulation time 48718431 ps
CPU time 0.77 seconds
Started Apr 27 04:11:48 PM PDT 24
Finished Apr 27 04:11:50 PM PDT 24
Peak memory 205864 kb
Host smart-6ec58021-6fe4-4f3d-b3f0-7b247e645c34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684931700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1684931700
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3880104009
Short name T756
Test name
Test status
Simulation time 201328215 ps
CPU time 1.78 seconds
Started Apr 27 04:11:36 PM PDT 24
Finished Apr 27 04:11:38 PM PDT 24
Peak memory 207136 kb
Host smart-bee5bbc4-4bbd-4f34-b596-f9b572c64eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880104009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3880104009
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3933374378
Short name T355
Test name
Test status
Simulation time 240214375 ps
CPU time 2.88 seconds
Started Apr 27 04:11:36 PM PDT 24
Finished Apr 27 04:11:39 PM PDT 24
Peak memory 218464 kb
Host smart-ad3bfe1c-81a4-418c-bac5-ca99e69c8454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933374378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3933374378
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.2858944631
Short name T963
Test name
Test status
Simulation time 91510019 ps
CPU time 2.02 seconds
Started Apr 27 04:11:47 PM PDT 24
Finished Apr 27 04:11:49 PM PDT 24
Peak memory 209596 kb
Host smart-18b8f18b-2a2d-48ab-8ea8-0aeea52e75b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858944631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.2858944631
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.169049632
Short name T228
Test name
Test status
Simulation time 201640740 ps
CPU time 4.87 seconds
Started Apr 27 04:11:36 PM PDT 24
Finished Apr 27 04:11:41 PM PDT 24
Peak memory 210368 kb
Host smart-66756bfc-771c-4510-8071-05c7f97e233e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169049632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.169049632
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2850907883
Short name T840
Test name
Test status
Simulation time 414934053 ps
CPU time 4.48 seconds
Started Apr 27 04:11:35 PM PDT 24
Finished Apr 27 04:11:40 PM PDT 24
Peak memory 210672 kb
Host smart-0447e1b7-b6c9-4292-aa78-7c05fe639470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850907883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2850907883
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3335930595
Short name T268
Test name
Test status
Simulation time 115217479 ps
CPU time 5.06 seconds
Started Apr 27 04:11:35 PM PDT 24
Finished Apr 27 04:11:40 PM PDT 24
Peak memory 210216 kb
Host smart-34675d62-6b9e-4f71-8f0f-1d2b3cb6d762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335930595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3335930595
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3690942183
Short name T682
Test name
Test status
Simulation time 39230395467 ps
CPU time 61.93 seconds
Started Apr 27 04:11:34 PM PDT 24
Finished Apr 27 04:12:36 PM PDT 24
Peak memory 208760 kb
Host smart-008bf9b9-bf4e-41a0-896b-8a94c08c1706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690942183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3690942183
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2206744638
Short name T1074
Test name
Test status
Simulation time 1781228796 ps
CPU time 55.58 seconds
Started Apr 27 04:11:36 PM PDT 24
Finished Apr 27 04:12:32 PM PDT 24
Peak memory 208120 kb
Host smart-c1a795f8-8e44-4754-ba9e-488cad4dc19d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206744638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2206744638
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3244172959
Short name T284
Test name
Test status
Simulation time 46772735 ps
CPU time 2.78 seconds
Started Apr 27 04:11:48 PM PDT 24
Finished Apr 27 04:11:52 PM PDT 24
Peak memory 208712 kb
Host smart-08b4156a-f936-42fc-b412-e416359c31ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244172959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3244172959
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1267813407
Short name T620
Test name
Test status
Simulation time 2257972091 ps
CPU time 69.12 seconds
Started Apr 27 04:11:36 PM PDT 24
Finished Apr 27 04:12:45 PM PDT 24
Peak memory 207972 kb
Host smart-1bdd0ae3-0359-4a27-8185-dd206b6e6e80
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267813407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1267813407
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1426095904
Short name T649
Test name
Test status
Simulation time 396551881 ps
CPU time 4.13 seconds
Started Apr 27 04:11:37 PM PDT 24
Finished Apr 27 04:11:42 PM PDT 24
Peak memory 215784 kb
Host smart-48cb8395-8fc5-4df7-a838-575511cb2279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426095904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1426095904
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2253334480
Short name T417
Test name
Test status
Simulation time 172236509 ps
CPU time 3.27 seconds
Started Apr 27 04:11:38 PM PDT 24
Finished Apr 27 04:11:41 PM PDT 24
Peak memory 207136 kb
Host smart-712f339b-df83-44f7-b588-494f2b7bb14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253334480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2253334480
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.532620345
Short name T580
Test name
Test status
Simulation time 363238550 ps
CPU time 5.83 seconds
Started Apr 27 04:11:34 PM PDT 24
Finished Apr 27 04:11:40 PM PDT 24
Peak memory 220516 kb
Host smart-d13cea34-7d1a-4ad5-be45-dc65706ef5b4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532620345 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.532620345
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1993839055
Short name T836
Test name
Test status
Simulation time 197254611 ps
CPU time 3.82 seconds
Started Apr 27 04:11:48 PM PDT 24
Finished Apr 27 04:11:52 PM PDT 24
Peak memory 207656 kb
Host smart-bcd58588-cc14-4eb3-baae-c7eec448ca37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993839055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1993839055
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2638367127
Short name T864
Test name
Test status
Simulation time 186176833 ps
CPU time 2.58 seconds
Started Apr 27 04:11:38 PM PDT 24
Finished Apr 27 04:11:41 PM PDT 24
Peak memory 210092 kb
Host smart-5ee4f442-624a-4209-8edd-2a1c19f254af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638367127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2638367127
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.290703021
Short name T592
Test name
Test status
Simulation time 14816125 ps
CPU time 0.96 seconds
Started Apr 27 04:09:16 PM PDT 24
Finished Apr 27 04:09:18 PM PDT 24
Peak memory 206060 kb
Host smart-9e5a66db-7514-42a2-bc1e-09e1ad748d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290703021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.290703021
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2721384436
Short name T396
Test name
Test status
Simulation time 190627900 ps
CPU time 4.05 seconds
Started Apr 27 04:09:08 PM PDT 24
Finished Apr 27 04:09:13 PM PDT 24
Peak memory 214320 kb
Host smart-077166ca-faa7-4bee-9c90-83bb0dc38b40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721384436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2721384436
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2343312109
Short name T933
Test name
Test status
Simulation time 36570642 ps
CPU time 2.45 seconds
Started Apr 27 04:09:10 PM PDT 24
Finished Apr 27 04:09:13 PM PDT 24
Peak memory 207988 kb
Host smart-a9fdf4b5-4e14-4b0b-9f55-863ead595616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343312109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2343312109
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2681564230
Short name T690
Test name
Test status
Simulation time 304401181 ps
CPU time 6.35 seconds
Started Apr 27 04:09:10 PM PDT 24
Finished Apr 27 04:09:17 PM PDT 24
Peak memory 219712 kb
Host smart-a7a204b6-cb20-4fd4-a4de-878689c4bc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681564230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2681564230
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.475459619
Short name T337
Test name
Test status
Simulation time 217111954 ps
CPU time 4.27 seconds
Started Apr 27 04:09:09 PM PDT 24
Finished Apr 27 04:09:13 PM PDT 24
Peak memory 209444 kb
Host smart-b53b78c3-13ec-46bf-b435-42bf35fad0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475459619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.475459619
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2282995881
Short name T708
Test name
Test status
Simulation time 127644067 ps
CPU time 5.72 seconds
Started Apr 27 04:09:10 PM PDT 24
Finished Apr 27 04:09:17 PM PDT 24
Peak memory 222544 kb
Host smart-c135570f-7b54-4d4c-9beb-408f4bdc11e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282995881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2282995881
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1395055152
Short name T904
Test name
Test status
Simulation time 184927736 ps
CPU time 2.76 seconds
Started Apr 27 04:09:13 PM PDT 24
Finished Apr 27 04:09:16 PM PDT 24
Peak memory 207612 kb
Host smart-1029ea15-4524-4208-996b-4676ad62d243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395055152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1395055152
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3128192188
Short name T47
Test name
Test status
Simulation time 808054076 ps
CPU time 22.29 seconds
Started Apr 27 04:09:11 PM PDT 24
Finished Apr 27 04:09:34 PM PDT 24
Peak memory 232236 kb
Host smart-f77321b8-daaf-449b-a00e-04b1472fbca6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128192188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3128192188
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1973344193
Short name T945
Test name
Test status
Simulation time 632541164 ps
CPU time 4.96 seconds
Started Apr 27 04:09:04 PM PDT 24
Finished Apr 27 04:09:09 PM PDT 24
Peak memory 206852 kb
Host smart-fb850a18-f704-46c4-8911-1abdb3815982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973344193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1973344193
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2168154830
Short name T972
Test name
Test status
Simulation time 190435666 ps
CPU time 5.77 seconds
Started Apr 27 04:09:03 PM PDT 24
Finished Apr 27 04:09:10 PM PDT 24
Peak memory 208480 kb
Host smart-facc11e5-09de-4d3c-a9d3-759eab559a09
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168154830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2168154830
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1177097168
Short name T1038
Test name
Test status
Simulation time 2381805884 ps
CPU time 39.58 seconds
Started Apr 27 04:09:04 PM PDT 24
Finished Apr 27 04:09:44 PM PDT 24
Peak memory 208872 kb
Host smart-c6cea011-b045-455b-a10d-35c675d646b9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177097168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1177097168
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1147634698
Short name T1054
Test name
Test status
Simulation time 24921316 ps
CPU time 1.95 seconds
Started Apr 27 04:09:06 PM PDT 24
Finished Apr 27 04:09:08 PM PDT 24
Peak memory 208544 kb
Host smart-9779052c-b4ec-4f30-9b73-cb48261bd328
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147634698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1147634698
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1309240034
Short name T553
Test name
Test status
Simulation time 621199783 ps
CPU time 3.44 seconds
Started Apr 27 04:09:11 PM PDT 24
Finished Apr 27 04:09:14 PM PDT 24
Peak memory 215892 kb
Host smart-88cb2eb2-dc8f-4e9b-a894-425ac0c753af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309240034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1309240034
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.97847320
Short name T738
Test name
Test status
Simulation time 1938540090 ps
CPU time 21.24 seconds
Started Apr 27 04:09:04 PM PDT 24
Finished Apr 27 04:09:25 PM PDT 24
Peak memory 208300 kb
Host smart-5c4d6f8d-1228-4bcb-8c24-c28f89c0986f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97847320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.97847320
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.492405446
Short name T84
Test name
Test status
Simulation time 382040279 ps
CPU time 18.39 seconds
Started Apr 27 04:09:10 PM PDT 24
Finished Apr 27 04:09:29 PM PDT 24
Peak memory 217144 kb
Host smart-4f64160b-10a0-485f-a641-cdf79bc6ae5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492405446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.492405446
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.755852412
Short name T974
Test name
Test status
Simulation time 502408724 ps
CPU time 6.37 seconds
Started Apr 27 04:09:10 PM PDT 24
Finished Apr 27 04:09:17 PM PDT 24
Peak memory 222584 kb
Host smart-3dd139e5-78b2-4b22-b4b2-3de25c20d113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755852412 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.755852412
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.629883845
Short name T319
Test name
Test status
Simulation time 69596075 ps
CPU time 4.17 seconds
Started Apr 27 04:09:09 PM PDT 24
Finished Apr 27 04:09:13 PM PDT 24
Peak memory 210208 kb
Host smart-f4293612-eee2-4d2d-86de-827818dc53f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629883845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.629883845
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.623400594
Short name T599
Test name
Test status
Simulation time 1298455377 ps
CPU time 6.52 seconds
Started Apr 27 04:09:13 PM PDT 24
Finished Apr 27 04:09:20 PM PDT 24
Peak memory 210384 kb
Host smart-fe3fb678-19c6-4a5d-9208-4775cff66579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623400594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.623400594
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.61439634
Short name T725
Test name
Test status
Simulation time 34923766 ps
CPU time 0.81 seconds
Started Apr 27 04:11:43 PM PDT 24
Finished Apr 27 04:11:44 PM PDT 24
Peak memory 205804 kb
Host smart-0e7a9d58-1abf-4e38-833e-19d7c6a7c1ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61439634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.61439634
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.4292639715
Short name T1030
Test name
Test status
Simulation time 116142259 ps
CPU time 5.11 seconds
Started Apr 27 04:11:42 PM PDT 24
Finished Apr 27 04:11:47 PM PDT 24
Peak memory 210116 kb
Host smart-79010c7b-38d1-4c85-9d77-c195d2f32531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292639715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.4292639715
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3949694622
Short name T354
Test name
Test status
Simulation time 572916718 ps
CPU time 7.34 seconds
Started Apr 27 04:11:42 PM PDT 24
Finished Apr 27 04:11:50 PM PDT 24
Peak memory 214232 kb
Host smart-71408b73-6b00-42a5-b85c-a27bba884dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949694622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3949694622
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3708697010
Short name T1004
Test name
Test status
Simulation time 32585422 ps
CPU time 1.95 seconds
Started Apr 27 04:11:43 PM PDT 24
Finished Apr 27 04:11:45 PM PDT 24
Peak memory 208960 kb
Host smart-034574e2-d757-4e8e-9c29-e53cc52653db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708697010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3708697010
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2822535960
Short name T835
Test name
Test status
Simulation time 264302888 ps
CPU time 4.05 seconds
Started Apr 27 04:11:42 PM PDT 24
Finished Apr 27 04:11:47 PM PDT 24
Peak memory 207348 kb
Host smart-c354ee76-5390-4b59-a8a7-6a9c5073aedc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822535960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2822535960
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3246909502
Short name T750
Test name
Test status
Simulation time 56231896 ps
CPU time 2.71 seconds
Started Apr 27 04:11:42 PM PDT 24
Finished Apr 27 04:11:45 PM PDT 24
Peak memory 206788 kb
Host smart-432aaccc-56b5-4008-aed7-618841d7eb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246909502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3246909502
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1894001893
Short name T331
Test name
Test status
Simulation time 68061527 ps
CPU time 3.32 seconds
Started Apr 27 04:11:42 PM PDT 24
Finished Apr 27 04:11:46 PM PDT 24
Peak memory 206892 kb
Host smart-8826b3df-9af4-41d8-b8c0-26bd895e2354
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894001893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1894001893
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2974424265
Short name T780
Test name
Test status
Simulation time 101660273 ps
CPU time 4.26 seconds
Started Apr 27 04:11:42 PM PDT 24
Finished Apr 27 04:11:47 PM PDT 24
Peak memory 208988 kb
Host smart-549a8592-e16d-489e-bb6b-d4705f91fe92
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974424265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2974424265
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3810672406
Short name T844
Test name
Test status
Simulation time 3694772431 ps
CPU time 29.53 seconds
Started Apr 27 04:11:43 PM PDT 24
Finished Apr 27 04:12:13 PM PDT 24
Peak memory 209060 kb
Host smart-4c0a521f-09a8-4b0d-a4da-93f13266d67f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810672406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3810672406
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2004687827
Short name T548
Test name
Test status
Simulation time 38670939 ps
CPU time 2.49 seconds
Started Apr 27 04:11:44 PM PDT 24
Finished Apr 27 04:11:47 PM PDT 24
Peak memory 215484 kb
Host smart-86f04905-9b7f-4947-8915-d9d45b66ae9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004687827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2004687827
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.4283377143
Short name T382
Test name
Test status
Simulation time 209993499 ps
CPU time 4.57 seconds
Started Apr 27 04:11:48 PM PDT 24
Finished Apr 27 04:11:53 PM PDT 24
Peak memory 206724 kb
Host smart-91bb9893-20fd-4936-9bb8-652b11716cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283377143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.4283377143
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2284152848
Short name T871
Test name
Test status
Simulation time 125778813 ps
CPU time 10.66 seconds
Started Apr 27 04:11:42 PM PDT 24
Finished Apr 27 04:11:54 PM PDT 24
Peak memory 220396 kb
Host smart-9d3a51ed-87dd-4a71-ac71-24e24a2ed255
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284152848 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2284152848
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1603977045
Short name T651
Test name
Test status
Simulation time 533899181 ps
CPU time 9.99 seconds
Started Apr 27 04:11:41 PM PDT 24
Finished Apr 27 04:11:52 PM PDT 24
Peak memory 208128 kb
Host smart-0596cc22-09f4-4831-a137-df461caf2d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603977045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1603977045
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3785470411
Short name T1050
Test name
Test status
Simulation time 157107947 ps
CPU time 2.97 seconds
Started Apr 27 04:11:41 PM PDT 24
Finished Apr 27 04:11:44 PM PDT 24
Peak memory 210352 kb
Host smart-eae899e8-610f-44a0-a8c9-2952ab5238eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785470411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3785470411
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1754741740
Short name T735
Test name
Test status
Simulation time 15119068 ps
CPU time 0.81 seconds
Started Apr 27 04:11:47 PM PDT 24
Finished Apr 27 04:11:49 PM PDT 24
Peak memory 205848 kb
Host smart-af0407b5-8f62-4483-9512-8d8c5fdef251
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754741740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1754741740
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1933624638
Short name T820
Test name
Test status
Simulation time 242421743 ps
CPU time 5.92 seconds
Started Apr 27 04:11:48 PM PDT 24
Finished Apr 27 04:11:55 PM PDT 24
Peak memory 209980 kb
Host smart-6734527f-36d1-4c12-b2de-e4ede6f0f7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933624638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1933624638
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.404596327
Short name T872
Test name
Test status
Simulation time 612993245 ps
CPU time 14.63 seconds
Started Apr 27 04:11:50 PM PDT 24
Finished Apr 27 04:12:05 PM PDT 24
Peak memory 208752 kb
Host smart-318fb0af-2e2f-4992-9a38-0649b12acfbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404596327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.404596327
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.948487126
Short name T842
Test name
Test status
Simulation time 19330977302 ps
CPU time 105.71 seconds
Started Apr 27 04:11:47 PM PDT 24
Finished Apr 27 04:13:34 PM PDT 24
Peak memory 214428 kb
Host smart-8e03fdeb-ae3f-49f7-9a7c-9654714daef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948487126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.948487126
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1133272131
Short name T336
Test name
Test status
Simulation time 1117219914 ps
CPU time 31.34 seconds
Started Apr 27 04:11:51 PM PDT 24
Finished Apr 27 04:12:22 PM PDT 24
Peak memory 222440 kb
Host smart-fb6de077-570e-4d45-b8a8-9af7a981de35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133272131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1133272131
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_random.2681136437
Short name T269
Test name
Test status
Simulation time 431838932 ps
CPU time 11.44 seconds
Started Apr 27 04:11:49 PM PDT 24
Finished Apr 27 04:12:01 PM PDT 24
Peak memory 208004 kb
Host smart-14061dd2-0699-41ad-84ac-9060cbc1514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681136437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2681136437
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.841179835
Short name T739
Test name
Test status
Simulation time 151554225 ps
CPU time 6 seconds
Started Apr 27 04:11:42 PM PDT 24
Finished Apr 27 04:11:49 PM PDT 24
Peak memory 209048 kb
Host smart-771b83ad-2e4a-430d-83f4-ae12728fb44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841179835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.841179835
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2370467094
Short name T703
Test name
Test status
Simulation time 222058506 ps
CPU time 3.04 seconds
Started Apr 27 04:11:44 PM PDT 24
Finished Apr 27 04:11:47 PM PDT 24
Peak memory 206904 kb
Host smart-206b4e74-2393-4d8e-a11d-44495917b998
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370467094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2370467094
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1054509151
Short name T634
Test name
Test status
Simulation time 61562885 ps
CPU time 2.5 seconds
Started Apr 27 04:11:43 PM PDT 24
Finished Apr 27 04:11:46 PM PDT 24
Peak memory 206904 kb
Host smart-37140142-fbe9-4963-a631-d5216b773aa8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054509151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1054509151
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2745584888
Short name T358
Test name
Test status
Simulation time 196120141 ps
CPU time 2.97 seconds
Started Apr 27 04:11:44 PM PDT 24
Finished Apr 27 04:11:47 PM PDT 24
Peak memory 206796 kb
Host smart-76a75616-adf5-4422-89a3-09d05726ca0c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745584888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2745584888
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3581432135
Short name T937
Test name
Test status
Simulation time 115257404 ps
CPU time 2.25 seconds
Started Apr 27 04:11:48 PM PDT 24
Finished Apr 27 04:11:51 PM PDT 24
Peak memory 208664 kb
Host smart-c72ed26d-6abb-469d-9a52-c3b523932b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581432135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3581432135
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2053161101
Short name T612
Test name
Test status
Simulation time 61459823 ps
CPU time 2.99 seconds
Started Apr 27 04:11:42 PM PDT 24
Finished Apr 27 04:11:45 PM PDT 24
Peak memory 208508 kb
Host smart-3ba69d89-42c4-4fe1-b8df-5e7790ca10da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053161101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2053161101
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.868513077
Short name T356
Test name
Test status
Simulation time 1159735289 ps
CPU time 39.08 seconds
Started Apr 27 04:11:47 PM PDT 24
Finished Apr 27 04:12:27 PM PDT 24
Peak memory 220732 kb
Host smart-90cd2833-3deb-4154-a32e-008f60ca1ec1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868513077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.868513077
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.799918935
Short name T940
Test name
Test status
Simulation time 197286959 ps
CPU time 6.58 seconds
Started Apr 27 04:11:52 PM PDT 24
Finished Apr 27 04:11:58 PM PDT 24
Peak memory 219156 kb
Host smart-42a5fddc-9814-4af1-9ef5-2b73f287fd63
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799918935 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.799918935
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2892777430
Short name T589
Test name
Test status
Simulation time 178899183 ps
CPU time 6.53 seconds
Started Apr 27 04:11:53 PM PDT 24
Finished Apr 27 04:12:00 PM PDT 24
Peak memory 218396 kb
Host smart-cf2a930b-9f6a-4ba8-9b9d-bf5d51bef145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892777430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2892777430
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.571734958
Short name T199
Test name
Test status
Simulation time 135522984 ps
CPU time 2.94 seconds
Started Apr 27 04:11:48 PM PDT 24
Finished Apr 27 04:11:52 PM PDT 24
Peak memory 210284 kb
Host smart-1ab65e50-df57-43ba-b0bf-4a1317bae9be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571734958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.571734958
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.921365577
Short name T642
Test name
Test status
Simulation time 28411248 ps
CPU time 0.81 seconds
Started Apr 27 04:11:55 PM PDT 24
Finished Apr 27 04:11:56 PM PDT 24
Peak memory 205900 kb
Host smart-120475e3-07e7-40c8-8bda-bfe1488cbed1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921365577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.921365577
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3531527289
Short name T1056
Test name
Test status
Simulation time 103146727 ps
CPU time 4.05 seconds
Started Apr 27 04:11:53 PM PDT 24
Finished Apr 27 04:11:57 PM PDT 24
Peak memory 214308 kb
Host smart-bbecaed2-f2e1-4e1a-8b50-faf5f12084a5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3531527289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3531527289
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2096907569
Short name T39
Test name
Test status
Simulation time 99367536 ps
CPU time 5.17 seconds
Started Apr 27 04:11:53 PM PDT 24
Finished Apr 27 04:11:59 PM PDT 24
Peak memory 209840 kb
Host smart-0d348e31-8a0c-467d-aa30-fb12851d6d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096907569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2096907569
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2484860165
Short name T999
Test name
Test status
Simulation time 24087111593 ps
CPU time 35.33 seconds
Started Apr 27 04:11:48 PM PDT 24
Finished Apr 27 04:12:24 PM PDT 24
Peak memory 218288 kb
Host smart-1341919c-4625-4765-ba46-1e5fa8141d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484860165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2484860165
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.4234785797
Short name T913
Test name
Test status
Simulation time 2287850981 ps
CPU time 45.75 seconds
Started Apr 27 04:11:47 PM PDT 24
Finished Apr 27 04:12:33 PM PDT 24
Peak memory 214316 kb
Host smart-d1af7111-0616-4f0d-8877-61468eca750a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234785797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.4234785797
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2909650412
Short name T293
Test name
Test status
Simulation time 277992169 ps
CPU time 7.44 seconds
Started Apr 27 04:11:54 PM PDT 24
Finished Apr 27 04:12:02 PM PDT 24
Peak memory 222480 kb
Host smart-7aefc874-bb9a-4b5f-8c8c-abae2167521c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909650412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2909650412
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.20751074
Short name T790
Test name
Test status
Simulation time 386071614 ps
CPU time 4.71 seconds
Started Apr 27 04:11:51 PM PDT 24
Finished Apr 27 04:11:56 PM PDT 24
Peak memory 222564 kb
Host smart-c80506b1-e592-4e42-b788-7d7b48ca04d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20751074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.20751074
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1251443904
Short name T226
Test name
Test status
Simulation time 79149430 ps
CPU time 3.02 seconds
Started Apr 27 04:11:49 PM PDT 24
Finished Apr 27 04:11:52 PM PDT 24
Peak memory 218028 kb
Host smart-6754c0fd-68c9-4fb7-8008-332d170baaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251443904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1251443904
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.707141930
Short name T995
Test name
Test status
Simulation time 75750276 ps
CPU time 3.33 seconds
Started Apr 27 04:11:49 PM PDT 24
Finished Apr 27 04:11:53 PM PDT 24
Peak memory 208544 kb
Host smart-a5478e0d-abb3-4110-861a-81e59c8490ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707141930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.707141930
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2396722233
Short name T660
Test name
Test status
Simulation time 371796097 ps
CPU time 2.7 seconds
Started Apr 27 04:11:53 PM PDT 24
Finished Apr 27 04:11:56 PM PDT 24
Peak memory 206912 kb
Host smart-983df2af-7495-4c0f-b783-bb66028a4ed4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396722233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2396722233
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1900100270
Short name T927
Test name
Test status
Simulation time 214832148 ps
CPU time 5.75 seconds
Started Apr 27 04:11:48 PM PDT 24
Finished Apr 27 04:11:54 PM PDT 24
Peak memory 207892 kb
Host smart-34e1868d-4845-4ebd-9c39-45478a4aa829
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900100270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1900100270
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.815486579
Short name T1027
Test name
Test status
Simulation time 5131123239 ps
CPU time 35.12 seconds
Started Apr 27 04:11:46 PM PDT 24
Finished Apr 27 04:12:22 PM PDT 24
Peak memory 208344 kb
Host smart-4265c82b-1d66-48b4-9940-c86edcf433d4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815486579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.815486579
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2105949004
Short name T1015
Test name
Test status
Simulation time 41895231 ps
CPU time 1.93 seconds
Started Apr 27 04:11:53 PM PDT 24
Finished Apr 27 04:11:56 PM PDT 24
Peak memory 208216 kb
Host smart-d07cc677-68de-4164-85dc-d60a54cf1f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105949004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2105949004
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.4037027543
Short name T1045
Test name
Test status
Simulation time 625060426 ps
CPU time 4.11 seconds
Started Apr 27 04:11:49 PM PDT 24
Finished Apr 27 04:11:54 PM PDT 24
Peak memory 208156 kb
Host smart-ccc40c60-0db7-4e6b-a0e7-faee6cc0e846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037027543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.4037027543
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3429195635
Short name T55
Test name
Test status
Simulation time 2189939860 ps
CPU time 15.96 seconds
Started Apr 27 04:11:54 PM PDT 24
Finished Apr 27 04:12:11 PM PDT 24
Peak memory 214376 kb
Host smart-b5672c09-633a-4bb2-abab-5f54d309e568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429195635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3429195635
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2971515220
Short name T825
Test name
Test status
Simulation time 80363468 ps
CPU time 3.91 seconds
Started Apr 27 04:11:54 PM PDT 24
Finished Apr 27 04:11:59 PM PDT 24
Peak memory 217820 kb
Host smart-47b1698a-a06f-4f0e-922b-bc29fc9f60b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971515220 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2971515220
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1214970459
Short name T990
Test name
Test status
Simulation time 71305122 ps
CPU time 3.33 seconds
Started Apr 27 04:11:47 PM PDT 24
Finished Apr 27 04:11:52 PM PDT 24
Peak memory 207572 kb
Host smart-dd42aeb9-b998-4fb4-8a5c-ff88f9e91180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214970459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1214970459
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.644058857
Short name T869
Test name
Test status
Simulation time 28916346 ps
CPU time 2.03 seconds
Started Apr 27 04:11:54 PM PDT 24
Finished Apr 27 04:11:57 PM PDT 24
Peak memory 210152 kb
Host smart-895b8931-406a-49cc-bc8e-4efdae4de961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644058857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.644058857
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.527022949
Short name T832
Test name
Test status
Simulation time 19077425 ps
CPU time 0.89 seconds
Started Apr 27 04:12:00 PM PDT 24
Finished Apr 27 04:12:01 PM PDT 24
Peak memory 205848 kb
Host smart-48ae2735-ea2c-419d-9371-2c73c35df24a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527022949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.527022949
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2494255706
Short name T270
Test name
Test status
Simulation time 155863119 ps
CPU time 3.02 seconds
Started Apr 27 04:11:53 PM PDT 24
Finished Apr 27 04:11:57 PM PDT 24
Peak memory 215256 kb
Host smart-3644927f-30b0-4bb0-acea-35190d4e2cd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2494255706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2494255706
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.6730959
Short name T252
Test name
Test status
Simulation time 1219227893 ps
CPU time 20.37 seconds
Started Apr 27 04:11:53 PM PDT 24
Finished Apr 27 04:12:14 PM PDT 24
Peak memory 217760 kb
Host smart-210de8c0-5ed6-4840-8b07-b96d0b155829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6730959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.6730959
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.812348720
Short name T28
Test name
Test status
Simulation time 103689427 ps
CPU time 3.59 seconds
Started Apr 27 04:11:52 PM PDT 24
Finished Apr 27 04:11:57 PM PDT 24
Peak memory 219348 kb
Host smart-4ea5c9fd-1513-4b06-8baf-f90ca92498aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812348720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.812348720
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3585752569
Short name T367
Test name
Test status
Simulation time 1055947344 ps
CPU time 10.11 seconds
Started Apr 27 04:11:54 PM PDT 24
Finished Apr 27 04:12:05 PM PDT 24
Peak memory 222456 kb
Host smart-fa9bd56a-555b-4b8c-9c13-277d932b8720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585752569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3585752569
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3440440150
Short name T62
Test name
Test status
Simulation time 44211362 ps
CPU time 3.05 seconds
Started Apr 27 04:11:54 PM PDT 24
Finished Apr 27 04:11:58 PM PDT 24
Peak memory 209432 kb
Host smart-317696a9-086e-4537-a8e2-39e96e02ad4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440440150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3440440150
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2682133979
Short name T1033
Test name
Test status
Simulation time 417973548 ps
CPU time 5.53 seconds
Started Apr 27 04:11:54 PM PDT 24
Finished Apr 27 04:12:00 PM PDT 24
Peak memory 207528 kb
Host smart-f5918413-8340-4f16-a0ba-25f8f97e5c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682133979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2682133979
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3224124278
Short name T636
Test name
Test status
Simulation time 90417617 ps
CPU time 4 seconds
Started Apr 27 04:11:54 PM PDT 24
Finished Apr 27 04:11:58 PM PDT 24
Peak memory 208672 kb
Host smart-fccf553f-588d-4fba-8268-c07a6d890803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224124278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3224124278
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2546694899
Short name T900
Test name
Test status
Simulation time 258480405 ps
CPU time 7.63 seconds
Started Apr 27 04:11:54 PM PDT 24
Finished Apr 27 04:12:02 PM PDT 24
Peak memory 208712 kb
Host smart-221ed69d-0eb0-4be1-93a1-3ddd3cf89a9b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546694899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2546694899
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2145736665
Short name T648
Test name
Test status
Simulation time 130633385 ps
CPU time 2.56 seconds
Started Apr 27 04:11:55 PM PDT 24
Finished Apr 27 04:11:58 PM PDT 24
Peak memory 206732 kb
Host smart-7c8b0b2d-f3ac-413f-b97c-fffb06fd54e1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145736665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2145736665
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2153431378
Short name T222
Test name
Test status
Simulation time 97851306 ps
CPU time 2.74 seconds
Started Apr 27 04:11:54 PM PDT 24
Finished Apr 27 04:11:57 PM PDT 24
Peak memory 209216 kb
Host smart-74f69b2c-e67b-44f3-ae6a-54d6d4375b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153431378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2153431378
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.422642627
Short name T565
Test name
Test status
Simulation time 171735663 ps
CPU time 2.77 seconds
Started Apr 27 04:11:52 PM PDT 24
Finished Apr 27 04:11:55 PM PDT 24
Peak memory 206888 kb
Host smart-15b93340-d87b-4218-ab2f-05b14460bf0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422642627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.422642627
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1633491328
Short name T753
Test name
Test status
Simulation time 4369121013 ps
CPU time 130.16 seconds
Started Apr 27 04:12:05 PM PDT 24
Finished Apr 27 04:14:16 PM PDT 24
Peak memory 220704 kb
Host smart-2d64f0ba-e516-4732-b8c1-df5d776dc1ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633491328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1633491328
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2696961762
Short name T747
Test name
Test status
Simulation time 1135877309 ps
CPU time 5.67 seconds
Started Apr 27 04:11:57 PM PDT 24
Finished Apr 27 04:12:04 PM PDT 24
Peak memory 223152 kb
Host smart-092958b1-2b05-4a26-a881-c6eb7a4cf44f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696961762 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2696961762
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2069505566
Short name T1032
Test name
Test status
Simulation time 277696507 ps
CPU time 7.9 seconds
Started Apr 27 04:11:55 PM PDT 24
Finished Apr 27 04:12:03 PM PDT 24
Peak memory 208244 kb
Host smart-17fb28fb-ad1c-413a-9a12-11cac1a0b8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069505566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2069505566
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1892931464
Short name T934
Test name
Test status
Simulation time 2462657718 ps
CPU time 19.19 seconds
Started Apr 27 04:11:54 PM PDT 24
Finished Apr 27 04:12:14 PM PDT 24
Peak memory 210780 kb
Host smart-389ebab8-b406-439d-b5f1-9c6e511e9a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892931464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1892931464
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1009252237
Short name T674
Test name
Test status
Simulation time 21966055 ps
CPU time 0.82 seconds
Started Apr 27 04:12:04 PM PDT 24
Finished Apr 27 04:12:05 PM PDT 24
Peak memory 205800 kb
Host smart-f258a203-0bcf-4532-b243-30aa45602895
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009252237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1009252237
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.4053109793
Short name T404
Test name
Test status
Simulation time 2048881424 ps
CPU time 104.42 seconds
Started Apr 27 04:11:58 PM PDT 24
Finished Apr 27 04:13:43 PM PDT 24
Peak memory 222212 kb
Host smart-353ddd8e-11e2-407a-afbd-ad45c1b4b437
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4053109793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.4053109793
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.4073389920
Short name T32
Test name
Test status
Simulation time 2189540777 ps
CPU time 70.64 seconds
Started Apr 27 04:12:04 PM PDT 24
Finished Apr 27 04:13:15 PM PDT 24
Peak memory 233340 kb
Host smart-ca365b6d-a00c-4bf7-b6a9-ab7df8c82d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073389920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.4073389920
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.994285459
Short name T56
Test name
Test status
Simulation time 73889909 ps
CPU time 2.73 seconds
Started Apr 27 04:12:06 PM PDT 24
Finished Apr 27 04:12:09 PM PDT 24
Peak memory 207440 kb
Host smart-c0272d40-d58c-44d9-ae1f-a0f9c8e319f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994285459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.994285459
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3070613775
Short name T734
Test name
Test status
Simulation time 780196831 ps
CPU time 6.12 seconds
Started Apr 27 04:12:05 PM PDT 24
Finished Apr 27 04:12:11 PM PDT 24
Peak memory 208396 kb
Host smart-c160ec3b-68ae-405b-a806-e60155210725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070613775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3070613775
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3492886184
Short name T677
Test name
Test status
Simulation time 310234616 ps
CPU time 4.17 seconds
Started Apr 27 04:11:58 PM PDT 24
Finished Apr 27 04:12:02 PM PDT 24
Peak memory 222448 kb
Host smart-10223b1a-340a-42a3-b980-b1b3ed39b24d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492886184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3492886184
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2652006535
Short name T223
Test name
Test status
Simulation time 1665036852 ps
CPU time 38.47 seconds
Started Apr 27 04:12:05 PM PDT 24
Finished Apr 27 04:12:44 PM PDT 24
Peak memory 218476 kb
Host smart-457e2e4f-a7b8-48e2-941f-aca681f203de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652006535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2652006535
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2804124540
Short name T938
Test name
Test status
Simulation time 453439350 ps
CPU time 5.31 seconds
Started Apr 27 04:12:05 PM PDT 24
Finished Apr 27 04:12:11 PM PDT 24
Peak memory 206776 kb
Host smart-5cef96f4-b29b-41b3-8970-363c8a675e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804124540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2804124540
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.274525257
Short name T360
Test name
Test status
Simulation time 200848098 ps
CPU time 6.34 seconds
Started Apr 27 04:11:57 PM PDT 24
Finished Apr 27 04:12:04 PM PDT 24
Peak memory 207824 kb
Host smart-5067269e-cd46-4054-abef-6deeecab23d3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274525257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.274525257
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2905200218
Short name T890
Test name
Test status
Simulation time 38186576 ps
CPU time 1.92 seconds
Started Apr 27 04:12:00 PM PDT 24
Finished Apr 27 04:12:02 PM PDT 24
Peak memory 206696 kb
Host smart-72f71fdc-b136-420c-9670-afa67652ce94
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905200218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2905200218
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2717029920
Short name T1071
Test name
Test status
Simulation time 1675405111 ps
CPU time 12.36 seconds
Started Apr 27 04:12:01 PM PDT 24
Finished Apr 27 04:12:14 PM PDT 24
Peak memory 207676 kb
Host smart-69aeb05f-d657-4785-9d94-223474b15fe7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717029920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2717029920
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1600581870
Short name T614
Test name
Test status
Simulation time 318256518 ps
CPU time 3.8 seconds
Started Apr 27 04:12:07 PM PDT 24
Finished Apr 27 04:12:11 PM PDT 24
Peak memory 214324 kb
Host smart-5789bf18-9132-4704-8529-fe4134a085c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600581870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1600581870
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.86854050
Short name T131
Test name
Test status
Simulation time 25582066 ps
CPU time 1.95 seconds
Started Apr 27 04:12:00 PM PDT 24
Finished Apr 27 04:12:02 PM PDT 24
Peak memory 207316 kb
Host smart-a3eaa117-0964-4ecc-87a8-73390dc679b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86854050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.86854050
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2453851746
Short name T1024
Test name
Test status
Simulation time 24041878356 ps
CPU time 704.55 seconds
Started Apr 27 04:12:06 PM PDT 24
Finished Apr 27 04:23:51 PM PDT 24
Peak memory 233280 kb
Host smart-bf248f7a-c10b-47bd-b7c2-252b96f478f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453851746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2453851746
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.4234109100
Short name T1067
Test name
Test status
Simulation time 199825706 ps
CPU time 3.9 seconds
Started Apr 27 04:12:08 PM PDT 24
Finished Apr 27 04:12:12 PM PDT 24
Peak memory 219012 kb
Host smart-c76cedad-64a2-4871-8439-714fb206e6cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234109100 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.4234109100
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.630256359
Short name T866
Test name
Test status
Simulation time 267554387 ps
CPU time 3.68 seconds
Started Apr 27 04:11:58 PM PDT 24
Finished Apr 27 04:12:02 PM PDT 24
Peak memory 208764 kb
Host smart-d332ec42-071d-4b36-9ad6-2ff64c85229f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630256359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.630256359
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2014230796
Short name T661
Test name
Test status
Simulation time 1357350915 ps
CPU time 13.9 seconds
Started Apr 27 04:12:04 PM PDT 24
Finished Apr 27 04:12:18 PM PDT 24
Peak memory 211012 kb
Host smart-2e37f825-cc57-4460-9288-80ae63af3050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014230796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2014230796
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.4029623452
Short name T859
Test name
Test status
Simulation time 13806017 ps
CPU time 0.76 seconds
Started Apr 27 04:12:07 PM PDT 24
Finished Apr 27 04:12:08 PM PDT 24
Peak memory 205556 kb
Host smart-e503ed8e-8bbd-4fd3-ae4d-58f117cce14c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029623452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.4029623452
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.486801472
Short name T288
Test name
Test status
Simulation time 140278638 ps
CPU time 2.88 seconds
Started Apr 27 04:12:10 PM PDT 24
Finished Apr 27 04:12:14 PM PDT 24
Peak memory 214304 kb
Host smart-78ead752-05f2-4a2b-9088-787b12088429
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=486801472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.486801472
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3215580276
Short name T585
Test name
Test status
Simulation time 65426234 ps
CPU time 3.42 seconds
Started Apr 27 04:12:06 PM PDT 24
Finished Apr 27 04:12:10 PM PDT 24
Peak memory 209828 kb
Host smart-717e74a5-8fa5-4c47-9d70-4c12864733d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215580276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3215580276
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.255560773
Short name T83
Test name
Test status
Simulation time 32394762 ps
CPU time 1.94 seconds
Started Apr 27 04:12:07 PM PDT 24
Finished Apr 27 04:12:09 PM PDT 24
Peak memory 208744 kb
Host smart-099560ff-40e5-46f6-8d66-eb0040fe84e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255560773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.255560773
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1382366867
Short name T98
Test name
Test status
Simulation time 210931894 ps
CPU time 4.38 seconds
Started Apr 27 04:12:08 PM PDT 24
Finished Apr 27 04:12:12 PM PDT 24
Peak memory 208540 kb
Host smart-a24fdc46-6020-4a71-a309-674a0b429114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382366867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1382366867
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2337786971
Short name T608
Test name
Test status
Simulation time 478066693 ps
CPU time 5.35 seconds
Started Apr 27 04:12:07 PM PDT 24
Finished Apr 27 04:12:12 PM PDT 24
Peak memory 209460 kb
Host smart-c1fa6a8f-9b35-4518-8b5b-116feb2ee962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337786971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2337786971
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.4102675016
Short name T942
Test name
Test status
Simulation time 116081441 ps
CPU time 3.12 seconds
Started Apr 27 04:12:07 PM PDT 24
Finished Apr 27 04:12:10 PM PDT 24
Peak memory 207092 kb
Host smart-28530b7e-b6f5-49a0-9822-d4ac50b0a7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102675016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.4102675016
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2007024797
Short name T250
Test name
Test status
Simulation time 265123109 ps
CPU time 7.2 seconds
Started Apr 27 04:12:14 PM PDT 24
Finished Apr 27 04:12:21 PM PDT 24
Peak memory 208544 kb
Host smart-890a85fe-3448-4b24-ac5d-d3fa2fb1d212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007024797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2007024797
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.218420678
Short name T15
Test name
Test status
Simulation time 148312657 ps
CPU time 3.14 seconds
Started Apr 27 04:12:07 PM PDT 24
Finished Apr 27 04:12:10 PM PDT 24
Peak memory 206840 kb
Host smart-b1f2ec7c-953c-4cf8-b132-dcc3a596acd0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218420678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.218420678
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1003582090
Short name T615
Test name
Test status
Simulation time 95353256 ps
CPU time 2.61 seconds
Started Apr 27 04:12:04 PM PDT 24
Finished Apr 27 04:12:07 PM PDT 24
Peak memory 206864 kb
Host smart-3b2ea343-c694-4fd7-b7a7-50ebc7649641
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003582090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1003582090
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2006670128
Short name T624
Test name
Test status
Simulation time 159678771 ps
CPU time 2.4 seconds
Started Apr 27 04:12:09 PM PDT 24
Finished Apr 27 04:12:12 PM PDT 24
Peak memory 206832 kb
Host smart-add69de0-1d6e-4bba-9fa5-7f87081ec736
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006670128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2006670128
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3957971478
Short name T1070
Test name
Test status
Simulation time 88075736 ps
CPU time 3.86 seconds
Started Apr 27 04:12:10 PM PDT 24
Finished Apr 27 04:12:15 PM PDT 24
Peak memory 210344 kb
Host smart-248daff7-cd69-4582-848e-3cff20d1d783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957971478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3957971478
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3313117336
Short name T875
Test name
Test status
Simulation time 540942485 ps
CPU time 2.57 seconds
Started Apr 27 04:12:03 PM PDT 24
Finished Apr 27 04:12:06 PM PDT 24
Peak memory 208180 kb
Host smart-5f4b322a-109a-43e5-98da-af84e2fe4458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313117336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3313117336
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2780343770
Short name T786
Test name
Test status
Simulation time 357489651 ps
CPU time 11.69 seconds
Started Apr 27 04:12:08 PM PDT 24
Finished Apr 27 04:12:20 PM PDT 24
Peak memory 222876 kb
Host smart-c1871ce2-8f7b-4c67-bcef-b3abeb82a895
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780343770 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2780343770
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2140766723
Short name T993
Test name
Test status
Simulation time 2620644632 ps
CPU time 57.06 seconds
Started Apr 27 04:12:10 PM PDT 24
Finished Apr 27 04:13:08 PM PDT 24
Peak memory 209472 kb
Host smart-6d1208d9-e152-427c-a28e-b5bc08f2b965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140766723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2140766723
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3814458670
Short name T203
Test name
Test status
Simulation time 506633314 ps
CPU time 5.9 seconds
Started Apr 27 04:12:08 PM PDT 24
Finished Apr 27 04:12:14 PM PDT 24
Peak memory 210564 kb
Host smart-6ea15a10-6565-4c7f-8344-f2eac5042c8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814458670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3814458670
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.305614839
Short name T656
Test name
Test status
Simulation time 17915727 ps
CPU time 0.74 seconds
Started Apr 27 04:12:11 PM PDT 24
Finished Apr 27 04:12:12 PM PDT 24
Peak memory 205872 kb
Host smart-2e206b7e-6f84-4336-ba6c-196a2184524f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305614839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.305614839
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.156709295
Short name T57
Test name
Test status
Simulation time 547876400 ps
CPU time 4.66 seconds
Started Apr 27 04:12:11 PM PDT 24
Finished Apr 27 04:12:16 PM PDT 24
Peak memory 218480 kb
Host smart-f3116b34-04ff-46b2-8c95-a36b3ae54b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156709295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.156709295
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1172488507
Short name T916
Test name
Test status
Simulation time 527957077 ps
CPU time 2.88 seconds
Started Apr 27 04:12:10 PM PDT 24
Finished Apr 27 04:12:14 PM PDT 24
Peak memory 208136 kb
Host smart-8bc3b815-ce36-404e-b795-427d8d974380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172488507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1172488507
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.791325780
Short name T909
Test name
Test status
Simulation time 341311323 ps
CPU time 4.61 seconds
Started Apr 27 04:12:13 PM PDT 24
Finished Apr 27 04:12:18 PM PDT 24
Peak memory 209316 kb
Host smart-2a0ef928-972a-431e-9233-d3bb3f70eecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791325780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.791325780
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.4176797465
Short name T352
Test name
Test status
Simulation time 145962367 ps
CPU time 6.72 seconds
Started Apr 27 04:12:11 PM PDT 24
Finished Apr 27 04:12:18 PM PDT 24
Peak memory 210676 kb
Host smart-cd480cd3-427c-46d4-a4cf-ce3977e037f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176797465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4176797465
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.274728767
Short name T217
Test name
Test status
Simulation time 29570128 ps
CPU time 2.33 seconds
Started Apr 27 04:12:12 PM PDT 24
Finished Apr 27 04:12:15 PM PDT 24
Peak memory 208148 kb
Host smart-2bf7919a-85fb-4136-ada9-adee9d518b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274728767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.274728767
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1679577802
Short name T362
Test name
Test status
Simulation time 101855237 ps
CPU time 4.93 seconds
Started Apr 27 04:12:09 PM PDT 24
Finished Apr 27 04:12:15 PM PDT 24
Peak memory 210028 kb
Host smart-2fa1dd80-4e40-4cc3-8972-564d62463e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679577802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1679577802
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2099151243
Short name T755
Test name
Test status
Simulation time 3209068139 ps
CPU time 33.41 seconds
Started Apr 27 04:12:09 PM PDT 24
Finished Apr 27 04:12:43 PM PDT 24
Peak memory 208164 kb
Host smart-881f2cd2-fbe3-4dd7-b5aa-6746ee8377c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099151243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2099151243
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3625447182
Short name T645
Test name
Test status
Simulation time 100903000 ps
CPU time 2.85 seconds
Started Apr 27 04:12:10 PM PDT 24
Finished Apr 27 04:12:13 PM PDT 24
Peak memory 208732 kb
Host smart-27c87f11-ad08-4190-b228-64f8ecc75ee6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625447182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3625447182
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2905871761
Short name T984
Test name
Test status
Simulation time 1147208068 ps
CPU time 29.35 seconds
Started Apr 27 04:12:12 PM PDT 24
Finished Apr 27 04:12:42 PM PDT 24
Peak memory 208768 kb
Host smart-354a7f4a-9040-42df-bc7f-89b8ffa72295
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905871761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2905871761
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1838008556
Short name T861
Test name
Test status
Simulation time 29081813 ps
CPU time 2.26 seconds
Started Apr 27 04:12:13 PM PDT 24
Finished Apr 27 04:12:16 PM PDT 24
Peak memory 216004 kb
Host smart-96365d25-2fe1-4a1d-8a77-c182f16c0104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838008556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1838008556
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2777022416
Short name T597
Test name
Test status
Simulation time 105523297 ps
CPU time 4.32 seconds
Started Apr 27 04:12:04 PM PDT 24
Finished Apr 27 04:12:09 PM PDT 24
Peak memory 208288 kb
Host smart-da154437-a360-43bd-b764-5bb2c71f4fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777022416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2777022416
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3504506288
Short name T1025
Test name
Test status
Simulation time 1507225659 ps
CPU time 40.98 seconds
Started Apr 27 04:12:10 PM PDT 24
Finished Apr 27 04:12:52 PM PDT 24
Peak memory 214312 kb
Host smart-1a7c1e38-0e12-4264-904f-fd828b2b9015
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504506288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3504506288
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.4199151269
Short name T198
Test name
Test status
Simulation time 1478489345 ps
CPU time 9.19 seconds
Started Apr 27 04:12:09 PM PDT 24
Finished Apr 27 04:12:19 PM PDT 24
Peak memory 218260 kb
Host smart-5c9fe273-9324-4d78-b583-d33b5a0dd132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199151269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.4199151269
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3056909542
Short name T162
Test name
Test status
Simulation time 224247036 ps
CPU time 8.11 seconds
Started Apr 27 04:12:15 PM PDT 24
Finished Apr 27 04:12:24 PM PDT 24
Peak memory 210844 kb
Host smart-6372790a-e8ae-4d0b-a38e-ab0c3536c696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056909542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3056909542
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1081954680
Short name T563
Test name
Test status
Simulation time 36753129 ps
CPU time 0.74 seconds
Started Apr 27 04:12:17 PM PDT 24
Finished Apr 27 04:12:19 PM PDT 24
Peak memory 205852 kb
Host smart-aef532e2-66b2-4c38-a298-5a45dba6e119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081954680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1081954680
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3049629849
Short name T267
Test name
Test status
Simulation time 128556721 ps
CPU time 7.22 seconds
Started Apr 27 04:12:16 PM PDT 24
Finished Apr 27 04:12:24 PM PDT 24
Peak memory 222500 kb
Host smart-14868b8f-e86f-443e-a263-d4ae689dd223
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3049629849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3049629849
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.4003890770
Short name T44
Test name
Test status
Simulation time 63455808 ps
CPU time 1.91 seconds
Started Apr 27 04:12:15 PM PDT 24
Finished Apr 27 04:12:18 PM PDT 24
Peak memory 220888 kb
Host smart-4b4ac1cc-a85d-4e00-8ed6-5bbf8cb3b2a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003890770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.4003890770
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2985783230
Short name T340
Test name
Test status
Simulation time 163480670 ps
CPU time 4.74 seconds
Started Apr 27 04:12:15 PM PDT 24
Finished Apr 27 04:12:20 PM PDT 24
Peak memory 210112 kb
Host smart-3155bfcd-c458-40ff-adcb-2f18b9a8730e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985783230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2985783230
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.481638328
Short name T310
Test name
Test status
Simulation time 1495597554 ps
CPU time 21.39 seconds
Started Apr 27 04:12:15 PM PDT 24
Finished Apr 27 04:12:37 PM PDT 24
Peak memory 222004 kb
Host smart-0f3c02b2-a389-4ae8-9cef-4bc05d012df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481638328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.481638328
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3822081979
Short name T277
Test name
Test status
Simulation time 140678252 ps
CPU time 3.72 seconds
Started Apr 27 04:12:13 PM PDT 24
Finished Apr 27 04:12:17 PM PDT 24
Peak memory 222364 kb
Host smart-bfd9831b-6d44-4cf7-9eca-50be846d5ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822081979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3822081979
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.122978494
Short name T48
Test name
Test status
Simulation time 1669917315 ps
CPU time 3.84 seconds
Started Apr 27 04:12:16 PM PDT 24
Finished Apr 27 04:12:20 PM PDT 24
Peak memory 210052 kb
Host smart-78963d4a-a0b5-4893-ac31-05c4ef0e4b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122978494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.122978494
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3550030532
Short name T385
Test name
Test status
Simulation time 558939863 ps
CPU time 7.03 seconds
Started Apr 27 04:12:17 PM PDT 24
Finished Apr 27 04:12:24 PM PDT 24
Peak memory 208916 kb
Host smart-da23d059-c6b5-40ae-823b-f0d5a09b1a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550030532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3550030532
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.146924056
Short name T782
Test name
Test status
Simulation time 58405868 ps
CPU time 2.98 seconds
Started Apr 27 04:12:10 PM PDT 24
Finished Apr 27 04:12:13 PM PDT 24
Peak memory 208164 kb
Host smart-41bfb4a1-3aed-4e05-b730-c63076bd4aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146924056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.146924056
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.902931382
Short name T787
Test name
Test status
Simulation time 93410174 ps
CPU time 2.41 seconds
Started Apr 27 04:12:16 PM PDT 24
Finished Apr 27 04:12:19 PM PDT 24
Peak memory 206848 kb
Host smart-67d42b66-1091-4dde-a72d-cdacab6532db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902931382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.902931382
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.638125184
Short name T877
Test name
Test status
Simulation time 224562778 ps
CPU time 3.16 seconds
Started Apr 27 04:12:11 PM PDT 24
Finished Apr 27 04:12:14 PM PDT 24
Peak memory 208660 kb
Host smart-67927654-c1e6-4767-9cb8-7fc7f371ae6c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638125184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.638125184
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.752822418
Short name T752
Test name
Test status
Simulation time 125893783 ps
CPU time 3.12 seconds
Started Apr 27 04:12:15 PM PDT 24
Finished Apr 27 04:12:19 PM PDT 24
Peak memory 208300 kb
Host smart-66ba0a97-ba1f-4fdb-94e6-185412cbbc5d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752822418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.752822418
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3916933487
Short name T232
Test name
Test status
Simulation time 95273536 ps
CPU time 4.38 seconds
Started Apr 27 04:12:15 PM PDT 24
Finished Apr 27 04:12:19 PM PDT 24
Peak memory 209956 kb
Host smart-4e198641-cbeb-4d41-a795-6ba99d0acd94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916933487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3916933487
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.716292183
Short name T821
Test name
Test status
Simulation time 40156109 ps
CPU time 2.25 seconds
Started Apr 27 04:12:10 PM PDT 24
Finished Apr 27 04:12:12 PM PDT 24
Peak memory 206848 kb
Host smart-4c4296b1-ddc1-4981-9823-be39722f2c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716292183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.716292183
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2657098970
Short name T929
Test name
Test status
Simulation time 1264702568 ps
CPU time 31.67 seconds
Started Apr 27 04:12:17 PM PDT 24
Finished Apr 27 04:12:49 PM PDT 24
Peak memory 222500 kb
Host smart-890e462b-ae8c-414b-b05b-af5196a0c032
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657098970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2657098970
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3246543902
Short name T886
Test name
Test status
Simulation time 76077239 ps
CPU time 3.01 seconds
Started Apr 27 04:12:13 PM PDT 24
Finished Apr 27 04:12:17 PM PDT 24
Peak memory 214304 kb
Host smart-4439060e-6b06-49ae-b9e7-c4cda43a30b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246543902 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3246543902
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1335961502
Short name T626
Test name
Test status
Simulation time 143549288 ps
CPU time 4.72 seconds
Started Apr 27 04:12:17 PM PDT 24
Finished Apr 27 04:12:22 PM PDT 24
Peak memory 208116 kb
Host smart-0df972bb-b733-4001-9cfc-42ae9265861b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335961502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1335961502
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1297715817
Short name T384
Test name
Test status
Simulation time 361325704 ps
CPU time 1.7 seconds
Started Apr 27 04:12:19 PM PDT 24
Finished Apr 27 04:12:21 PM PDT 24
Peak memory 209716 kb
Host smart-ea0a02e6-adf1-449e-aaf3-935f25591331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297715817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1297715817
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1573043110
Short name T1048
Test name
Test status
Simulation time 12664750 ps
CPU time 0.86 seconds
Started Apr 27 04:12:21 PM PDT 24
Finished Apr 27 04:12:22 PM PDT 24
Peak memory 205884 kb
Host smart-d28527f1-d57a-4e98-96e4-99ef7b48e998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573043110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1573043110
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2528205513
Short name T246
Test name
Test status
Simulation time 86354675 ps
CPU time 4.3 seconds
Started Apr 27 04:12:20 PM PDT 24
Finished Apr 27 04:12:24 PM PDT 24
Peak memory 215512 kb
Host smart-0bb63ad4-4224-4c05-93db-248b1b7306c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528205513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2528205513
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2820161451
Short name T335
Test name
Test status
Simulation time 76296975 ps
CPU time 2.21 seconds
Started Apr 27 04:12:21 PM PDT 24
Finished Apr 27 04:12:24 PM PDT 24
Peak memory 214288 kb
Host smart-653ecfd2-0e2b-4b5d-895d-531ec81f9f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820161451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2820161451
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2615164552
Short name T323
Test name
Test status
Simulation time 85377261 ps
CPU time 3.86 seconds
Started Apr 27 04:12:20 PM PDT 24
Finished Apr 27 04:12:24 PM PDT 24
Peak memory 214268 kb
Host smart-101f6269-caa4-4543-aa42-0021ab039122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615164552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2615164552
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3278548915
Short name T694
Test name
Test status
Simulation time 675099978 ps
CPU time 3.95 seconds
Started Apr 27 04:12:19 PM PDT 24
Finished Apr 27 04:12:23 PM PDT 24
Peak memory 209692 kb
Host smart-240dcaf3-5637-4c81-bdab-5a334c2ee5fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278548915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3278548915
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2477085693
Short name T970
Test name
Test status
Simulation time 7596377831 ps
CPU time 57.18 seconds
Started Apr 27 04:12:16 PM PDT 24
Finished Apr 27 04:13:14 PM PDT 24
Peak memory 209612 kb
Host smart-2cd1df95-7d59-47f9-9e67-2839f59fac06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477085693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2477085693
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1974604572
Short name T392
Test name
Test status
Simulation time 244600765 ps
CPU time 6.57 seconds
Started Apr 27 04:12:16 PM PDT 24
Finished Apr 27 04:12:23 PM PDT 24
Peak memory 208436 kb
Host smart-df10eed5-24d6-4058-9f7b-3e26d64da413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974604572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1974604572
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.54149017
Short name T3
Test name
Test status
Simulation time 384847882 ps
CPU time 7.86 seconds
Started Apr 27 04:12:15 PM PDT 24
Finished Apr 27 04:12:23 PM PDT 24
Peak memory 208464 kb
Host smart-b1900b8a-0626-4f30-b3cf-13aae86014e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54149017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.54149017
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.508758439
Short name T332
Test name
Test status
Simulation time 536276759 ps
CPU time 5.55 seconds
Started Apr 27 04:12:15 PM PDT 24
Finished Apr 27 04:12:21 PM PDT 24
Peak memory 208600 kb
Host smart-24b54cbf-f5d4-45b1-9fa1-0e3aeba6d385
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508758439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.508758439
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2409561644
Short name T749
Test name
Test status
Simulation time 261848635 ps
CPU time 3.55 seconds
Started Apr 27 04:12:16 PM PDT 24
Finished Apr 27 04:12:20 PM PDT 24
Peak memory 206912 kb
Host smart-99e56d1b-f459-41e4-a3ba-c4f264ff4a76
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409561644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2409561644
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.4272762086
Short name T939
Test name
Test status
Simulation time 54334023 ps
CPU time 2.74 seconds
Started Apr 27 04:12:21 PM PDT 24
Finished Apr 27 04:12:24 PM PDT 24
Peak memory 216156 kb
Host smart-e00c6c64-473a-4a15-bce7-3caf70c245b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272762086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.4272762086
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1660721706
Short name T575
Test name
Test status
Simulation time 297296305 ps
CPU time 2.99 seconds
Started Apr 27 04:12:18 PM PDT 24
Finished Apr 27 04:12:22 PM PDT 24
Peak memory 208448 kb
Host smart-03feaab3-060f-49b7-ac98-46b0399706eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660721706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1660721706
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.3239823847
Short name T720
Test name
Test status
Simulation time 76383443 ps
CPU time 3.76 seconds
Started Apr 27 04:12:21 PM PDT 24
Finished Apr 27 04:12:25 PM PDT 24
Peak memory 214500 kb
Host smart-65b204b1-7a35-4db7-8e82-c90535404189
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239823847 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.3239823847
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.4145600414
Short name T676
Test name
Test status
Simulation time 610446914 ps
CPU time 19.68 seconds
Started Apr 27 04:12:22 PM PDT 24
Finished Apr 27 04:12:42 PM PDT 24
Peak memory 209144 kb
Host smart-e01b72fa-82ab-4876-9201-3e6c3bed8820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145600414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.4145600414
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2192611671
Short name T751
Test name
Test status
Simulation time 27087682 ps
CPU time 1.88 seconds
Started Apr 27 04:12:23 PM PDT 24
Finished Apr 27 04:12:26 PM PDT 24
Peak memory 210016 kb
Host smart-70ab5eed-cc0f-4d44-8df7-63c78b91ac55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192611671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2192611671
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.892563222
Short name T841
Test name
Test status
Simulation time 47820947 ps
CPU time 0.81 seconds
Started Apr 27 04:12:26 PM PDT 24
Finished Apr 27 04:12:27 PM PDT 24
Peak memory 205896 kb
Host smart-a2caa48e-1030-4fe2-a2a2-9f4b2e72c41a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892563222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.892563222
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.687678569
Short name T34
Test name
Test status
Simulation time 82561089 ps
CPU time 2.45 seconds
Started Apr 27 04:12:26 PM PDT 24
Finished Apr 27 04:12:29 PM PDT 24
Peak memory 215996 kb
Host smart-8ec246ec-ae4a-404a-a5f9-c86018a2a528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687678569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.687678569
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3238721253
Short name T64
Test name
Test status
Simulation time 30576117 ps
CPU time 2.33 seconds
Started Apr 27 04:12:23 PM PDT 24
Finished Apr 27 04:12:26 PM PDT 24
Peak memory 207636 kb
Host smart-82464897-7b29-4de6-bc95-94afc29967ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238721253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3238721253
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.204015060
Short name T94
Test name
Test status
Simulation time 380468457 ps
CPU time 4.34 seconds
Started Apr 27 04:12:26 PM PDT 24
Finished Apr 27 04:12:31 PM PDT 24
Peak memory 219792 kb
Host smart-caf56a1c-7e86-4cd4-805d-d252b57fb159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204015060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.204015060
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.271464837
Short name T315
Test name
Test status
Simulation time 1059246024 ps
CPU time 30.15 seconds
Started Apr 27 04:12:27 PM PDT 24
Finished Apr 27 04:12:58 PM PDT 24
Peak memory 220644 kb
Host smart-2b776852-85cd-4f03-ae38-ffa9a1fbdcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271464837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.271464837
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.749214089
Short name T282
Test name
Test status
Simulation time 60905618 ps
CPU time 3.86 seconds
Started Apr 27 04:12:24 PM PDT 24
Finished Apr 27 04:12:28 PM PDT 24
Peak memory 209620 kb
Host smart-01a1db23-396a-4f7b-bc5b-e57409538b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749214089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.749214089
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2022630044
Short name T675
Test name
Test status
Simulation time 174160724 ps
CPU time 3.63 seconds
Started Apr 27 04:12:21 PM PDT 24
Finished Apr 27 04:12:25 PM PDT 24
Peak memory 209104 kb
Host smart-b1d4c032-35b1-411c-ac54-938b25cadd9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022630044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2022630044
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.159666965
Short name T291
Test name
Test status
Simulation time 324049725 ps
CPU time 5.31 seconds
Started Apr 27 04:12:20 PM PDT 24
Finished Apr 27 04:12:26 PM PDT 24
Peak memory 206748 kb
Host smart-b6cf6914-a0a2-417a-a2a1-a230628fcc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159666965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.159666965
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3423060569
Short name T87
Test name
Test status
Simulation time 18532644505 ps
CPU time 49.12 seconds
Started Apr 27 04:12:23 PM PDT 24
Finished Apr 27 04:13:12 PM PDT 24
Peak memory 209228 kb
Host smart-50d7acdc-b2cd-4e87-919e-e0f3a55ccbdf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423060569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3423060569
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.4005665886
Short name T792
Test name
Test status
Simulation time 1379849656 ps
CPU time 33.87 seconds
Started Apr 27 04:12:22 PM PDT 24
Finished Apr 27 04:12:56 PM PDT 24
Peak memory 207988 kb
Host smart-5a068c87-f18b-418c-8ef6-4e5a0c8ae6de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005665886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.4005665886
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1325797233
Short name T813
Test name
Test status
Simulation time 205553034 ps
CPU time 4.24 seconds
Started Apr 27 04:12:22 PM PDT 24
Finished Apr 27 04:12:26 PM PDT 24
Peak memory 208828 kb
Host smart-cd821fe5-5d8c-4f9b-8900-d358962f55f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325797233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1325797233
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.4083607352
Short name T286
Test name
Test status
Simulation time 160996802 ps
CPU time 4.54 seconds
Started Apr 27 04:12:27 PM PDT 24
Finished Apr 27 04:12:32 PM PDT 24
Peak memory 210124 kb
Host smart-d7b8f085-d9e0-453a-b5ef-fd453b1641b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083607352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.4083607352
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.4046159828
Short name T986
Test name
Test status
Simulation time 57353672 ps
CPU time 3.18 seconds
Started Apr 27 04:12:19 PM PDT 24
Finished Apr 27 04:12:23 PM PDT 24
Peak memory 206848 kb
Host smart-2706a2ac-6484-4b3d-b95d-01cb9df7e7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046159828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.4046159828
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2519367426
Short name T893
Test name
Test status
Simulation time 643627583 ps
CPU time 23.73 seconds
Started Apr 27 04:12:25 PM PDT 24
Finished Apr 27 04:12:50 PM PDT 24
Peak memory 222528 kb
Host smart-6e4d6792-119d-46fb-8506-25c728eef0d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519367426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2519367426
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2490432302
Short name T124
Test name
Test status
Simulation time 303038268 ps
CPU time 5.29 seconds
Started Apr 27 04:12:25 PM PDT 24
Finished Apr 27 04:12:31 PM PDT 24
Peak memory 222668 kb
Host smart-5b830a10-f330-474e-8c2b-1a42aaa095a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490432302 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2490432302
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1729225466
Short name T989
Test name
Test status
Simulation time 368677065 ps
CPU time 4.57 seconds
Started Apr 27 04:12:24 PM PDT 24
Finished Apr 27 04:12:29 PM PDT 24
Peak memory 208264 kb
Host smart-4c740f12-375c-4e4b-a3f2-4a7a98f2b3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729225466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1729225466
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.779963510
Short name T186
Test name
Test status
Simulation time 24180793 ps
CPU time 0.94 seconds
Started Apr 27 04:09:16 PM PDT 24
Finished Apr 27 04:09:17 PM PDT 24
Peak memory 205992 kb
Host smart-7950b4e1-41f9-4083-89bf-7044c94b1cfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779963510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.779963510
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.548286285
Short name T37
Test name
Test status
Simulation time 882810930 ps
CPU time 2.56 seconds
Started Apr 27 04:09:18 PM PDT 24
Finished Apr 27 04:09:21 PM PDT 24
Peak memory 209556 kb
Host smart-a9bc3a3b-bbf2-4bbd-9deb-9851d1ffe035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548286285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.548286285
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2950718127
Short name T860
Test name
Test status
Simulation time 44959935 ps
CPU time 2.86 seconds
Started Apr 27 04:09:16 PM PDT 24
Finished Apr 27 04:09:20 PM PDT 24
Peak memory 219692 kb
Host smart-d7fbc9f3-b690-47ba-a3f8-a6fffcdc77f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950718127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2950718127
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3101853
Short name T1012
Test name
Test status
Simulation time 240585409 ps
CPU time 4.69 seconds
Started Apr 27 04:09:14 PM PDT 24
Finished Apr 27 04:09:19 PM PDT 24
Peak memory 209100 kb
Host smart-d4f16b7e-986e-4cc2-9500-bedc236085df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3101853
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3022367242
Short name T369
Test name
Test status
Simulation time 10408330595 ps
CPU time 37.13 seconds
Started Apr 27 04:09:14 PM PDT 24
Finished Apr 27 04:09:51 PM PDT 24
Peak memory 222480 kb
Host smart-c139fb0b-b157-47a8-ab07-ecadef8e7c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022367242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3022367242
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3228518295
Short name T67
Test name
Test status
Simulation time 208063208 ps
CPU time 6.25 seconds
Started Apr 27 04:09:14 PM PDT 24
Finished Apr 27 04:09:21 PM PDT 24
Peak memory 209924 kb
Host smart-28d3dcf9-de7c-47f5-a25a-84c6e3ccadae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228518295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3228518295
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2736607591
Short name T662
Test name
Test status
Simulation time 703729888 ps
CPU time 4.88 seconds
Started Apr 27 04:09:18 PM PDT 24
Finished Apr 27 04:09:23 PM PDT 24
Peak memory 209236 kb
Host smart-9b001747-dc08-42b2-a9db-0b725652bf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736607591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2736607591
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1443201307
Short name T13
Test name
Test status
Simulation time 3820998003 ps
CPU time 16.2 seconds
Started Apr 27 04:09:16 PM PDT 24
Finished Apr 27 04:09:33 PM PDT 24
Peak memory 231928 kb
Host smart-1fe05757-b710-45cf-9404-c6040116f90d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443201307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1443201307
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1947079898
Short name T923
Test name
Test status
Simulation time 351318065 ps
CPU time 3.41 seconds
Started Apr 27 04:09:16 PM PDT 24
Finished Apr 27 04:09:19 PM PDT 24
Peak memory 208404 kb
Host smart-ceb09ff0-2ef3-4d9c-9534-a690dc690b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947079898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1947079898
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1776876491
Short name T936
Test name
Test status
Simulation time 43333323 ps
CPU time 2.46 seconds
Started Apr 27 04:09:15 PM PDT 24
Finished Apr 27 04:09:18 PM PDT 24
Peak memory 206764 kb
Host smart-db42506d-f6ef-49a1-a642-3d90f03e39b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776876491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1776876491
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.904489773
Short name T804
Test name
Test status
Simulation time 211123244 ps
CPU time 5.98 seconds
Started Apr 27 04:09:15 PM PDT 24
Finished Apr 27 04:09:21 PM PDT 24
Peak memory 207896 kb
Host smart-ef6e84c0-2f88-4796-acda-327af3c130cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904489773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.904489773
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.201479033
Short name T251
Test name
Test status
Simulation time 42258361 ps
CPU time 2.48 seconds
Started Apr 27 04:09:17 PM PDT 24
Finished Apr 27 04:09:20 PM PDT 24
Peak memory 208804 kb
Host smart-2b15e52e-c0cb-4869-806a-c9f681fac537
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201479033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.201479033
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3676915687
Short name T673
Test name
Test status
Simulation time 53944137 ps
CPU time 3.07 seconds
Started Apr 27 04:09:14 PM PDT 24
Finished Apr 27 04:09:17 PM PDT 24
Peak memory 207896 kb
Host smart-f20e8571-4187-41ee-a7c2-fe176d80e1d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676915687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3676915687
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3768660923
Short name T665
Test name
Test status
Simulation time 1820886489 ps
CPU time 23.56 seconds
Started Apr 27 04:09:16 PM PDT 24
Finished Apr 27 04:09:40 PM PDT 24
Peak memory 207876 kb
Host smart-38746750-896f-4f38-b82b-fd0feaaf06ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768660923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3768660923
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.4179824118
Short name T285
Test name
Test status
Simulation time 363532133 ps
CPU time 11.32 seconds
Started Apr 27 04:09:18 PM PDT 24
Finished Apr 27 04:09:30 PM PDT 24
Peak memory 208600 kb
Host smart-408800ae-9d64-4136-aa5b-dc347072a404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179824118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.4179824118
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2369406681
Short name T646
Test name
Test status
Simulation time 251513455 ps
CPU time 5.19 seconds
Started Apr 27 04:09:15 PM PDT 24
Finished Apr 27 04:09:20 PM PDT 24
Peak memory 211020 kb
Host smart-7ecd456d-fe3c-4cbf-9e2a-85cdf5ae664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369406681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2369406681
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3218431468
Short name T932
Test name
Test status
Simulation time 120381020 ps
CPU time 1.17 seconds
Started Apr 27 04:12:29 PM PDT 24
Finished Apr 27 04:12:31 PM PDT 24
Peak memory 206004 kb
Host smart-7ca20c66-9e0a-4f4e-a62b-b5318c569ce6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218431468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3218431468
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.80060417
Short name T370
Test name
Test status
Simulation time 76033305 ps
CPU time 4.8 seconds
Started Apr 27 04:12:26 PM PDT 24
Finished Apr 27 04:12:32 PM PDT 24
Peak memory 222480 kb
Host smart-2e5f534d-77e0-4c4c-a6ce-e01e5f2e23bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=80060417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.80060417
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1896534881
Short name T71
Test name
Test status
Simulation time 4958043973 ps
CPU time 7.1 seconds
Started Apr 27 04:12:36 PM PDT 24
Finished Apr 27 04:12:45 PM PDT 24
Peak memory 210416 kb
Host smart-a3b23829-58cf-4c8f-b88e-58ffcaec9f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896534881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1896534881
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1988506996
Short name T948
Test name
Test status
Simulation time 233617474 ps
CPU time 3.7 seconds
Started Apr 27 04:12:27 PM PDT 24
Finished Apr 27 04:12:31 PM PDT 24
Peak memory 218280 kb
Host smart-9ef37267-fbbd-459a-a56e-446ce54fd112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988506996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1988506996
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.147699474
Short name T86
Test name
Test status
Simulation time 136093915 ps
CPU time 5.47 seconds
Started Apr 27 04:12:29 PM PDT 24
Finished Apr 27 04:12:35 PM PDT 24
Peak memory 209156 kb
Host smart-618eab9c-2e41-4ed2-b735-6f6dc77f79dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147699474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.147699474
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3448704063
Short name T253
Test name
Test status
Simulation time 305637523 ps
CPU time 9.49 seconds
Started Apr 27 04:12:31 PM PDT 24
Finished Apr 27 04:12:41 PM PDT 24
Peak memory 209448 kb
Host smart-1f8d1aae-3498-4511-ac3e-5902556f4fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448704063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3448704063
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1347979874
Short name T208
Test name
Test status
Simulation time 174902835 ps
CPU time 4.87 seconds
Started Apr 27 04:12:30 PM PDT 24
Finished Apr 27 04:12:36 PM PDT 24
Peak memory 218736 kb
Host smart-8dad06d3-f666-4462-9262-5d827d5c30bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347979874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1347979874
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1127450207
Short name T699
Test name
Test status
Simulation time 6145069255 ps
CPU time 105.35 seconds
Started Apr 27 04:12:27 PM PDT 24
Finished Apr 27 04:14:13 PM PDT 24
Peak memory 209820 kb
Host smart-2f651368-b8e6-4f18-8a7d-340cc63f72cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127450207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1127450207
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1741559294
Short name T333
Test name
Test status
Simulation time 957509003 ps
CPU time 24.34 seconds
Started Apr 27 04:12:26 PM PDT 24
Finished Apr 27 04:12:51 PM PDT 24
Peak memory 207960 kb
Host smart-c9b32b9a-ef1f-464d-8d55-3b8279b8cf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741559294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1741559294
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.4231045342
Short name T815
Test name
Test status
Simulation time 2266545744 ps
CPU time 7.19 seconds
Started Apr 27 04:12:26 PM PDT 24
Finished Apr 27 04:12:34 PM PDT 24
Peak memory 208024 kb
Host smart-32b39ed6-9e9b-488c-bd3c-70baa4ed49e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231045342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.4231045342
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.516300813
Short name T905
Test name
Test status
Simulation time 466901458 ps
CPU time 4.47 seconds
Started Apr 27 04:12:26 PM PDT 24
Finished Apr 27 04:12:31 PM PDT 24
Peak memory 207912 kb
Host smart-8cb71459-f622-4e35-b201-b30ba8d9665e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516300813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.516300813
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.4138434570
Short name T1026
Test name
Test status
Simulation time 55183149 ps
CPU time 1.85 seconds
Started Apr 27 04:12:26 PM PDT 24
Finished Apr 27 04:12:29 PM PDT 24
Peak memory 206896 kb
Host smart-6b282e95-fe7a-4bd4-b6dc-0d91ef7e5f8f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138434570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.4138434570
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2797697572
Short name T822
Test name
Test status
Simulation time 809090182 ps
CPU time 3.39 seconds
Started Apr 27 04:12:35 PM PDT 24
Finished Apr 27 04:12:40 PM PDT 24
Peak memory 209328 kb
Host smart-e040f1eb-69a9-44ca-9419-ba0a51fb7a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797697572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2797697572
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3285448019
Short name T921
Test name
Test status
Simulation time 40844955 ps
CPU time 2.33 seconds
Started Apr 27 04:12:25 PM PDT 24
Finished Apr 27 04:12:29 PM PDT 24
Peak memory 206816 kb
Host smart-7ad72e70-e6cd-4484-8b4e-032d8f68903e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285448019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3285448019
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1664528610
Short name T719
Test name
Test status
Simulation time 645838554 ps
CPU time 4.78 seconds
Started Apr 27 04:12:29 PM PDT 24
Finished Apr 27 04:12:34 PM PDT 24
Peak memory 222608 kb
Host smart-da898fb1-0bf4-4fa7-adbb-f05cb299a568
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664528610 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1664528610
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1041849569
Short name T308
Test name
Test status
Simulation time 154888612 ps
CPU time 4.16 seconds
Started Apr 27 04:12:31 PM PDT 24
Finished Apr 27 04:12:36 PM PDT 24
Peak memory 208216 kb
Host smart-4e0eef74-d8c2-47ff-87cc-7450bc74dc29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041849569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1041849569
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1568382051
Short name T912
Test name
Test status
Simulation time 2288861173 ps
CPU time 3.13 seconds
Started Apr 27 04:12:31 PM PDT 24
Finished Apr 27 04:12:34 PM PDT 24
Peak memory 210012 kb
Host smart-e7c5027a-ac37-4dce-a4ae-e141356319c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568382051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1568382051
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3424439793
Short name T991
Test name
Test status
Simulation time 40036085 ps
CPU time 0.77 seconds
Started Apr 27 04:12:37 PM PDT 24
Finished Apr 27 04:12:39 PM PDT 24
Peak memory 205856 kb
Host smart-3b8f89bd-5e38-40a5-a984-580b239d8a82
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424439793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3424439793
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.426503757
Short name T765
Test name
Test status
Simulation time 1215759671 ps
CPU time 9.13 seconds
Started Apr 27 04:12:36 PM PDT 24
Finished Apr 27 04:12:46 PM PDT 24
Peak memory 209340 kb
Host smart-82b268dd-be46-4f04-b564-3337c6b9d92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=426503757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.426503757
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3626487834
Short name T1037
Test name
Test status
Simulation time 9253944937 ps
CPU time 18.5 seconds
Started Apr 27 04:12:30 PM PDT 24
Finished Apr 27 04:12:50 PM PDT 24
Peak memory 209584 kb
Host smart-2b9ad4b0-c038-4ed1-98f7-09eb4192f07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626487834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3626487834
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2848287487
Short name T95
Test name
Test status
Simulation time 156225632 ps
CPU time 5.13 seconds
Started Apr 27 04:12:32 PM PDT 24
Finished Apr 27 04:12:37 PM PDT 24
Peak memory 208664 kb
Host smart-d8bc1b17-c7e4-40c4-80c1-1c0f4f5f1899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848287487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2848287487
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3330828359
Short name T278
Test name
Test status
Simulation time 1081082103 ps
CPU time 9.24 seconds
Started Apr 27 04:12:31 PM PDT 24
Finished Apr 27 04:12:40 PM PDT 24
Peak memory 222396 kb
Host smart-5b9ab98e-b54a-40d1-9c51-9208a5553e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330828359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3330828359
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2203578574
Short name T262
Test name
Test status
Simulation time 293015527 ps
CPU time 3.03 seconds
Started Apr 27 04:12:31 PM PDT 24
Finished Apr 27 04:12:35 PM PDT 24
Peak memory 210216 kb
Host smart-1d77e334-13dd-4730-acf3-a5c5be86a72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203578574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2203578574
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3003293715
Short name T600
Test name
Test status
Simulation time 2988731740 ps
CPU time 37.46 seconds
Started Apr 27 04:12:32 PM PDT 24
Finished Apr 27 04:13:10 PM PDT 24
Peak memory 218292 kb
Host smart-f86c24f2-a018-4962-b22c-33a630bbaa44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003293715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3003293715
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2589233728
Short name T809
Test name
Test status
Simulation time 30703914999 ps
CPU time 48.93 seconds
Started Apr 27 04:12:36 PM PDT 24
Finished Apr 27 04:13:26 PM PDT 24
Peak memory 207816 kb
Host smart-79b94fa0-f0a8-49fc-bb43-d6d6667b8051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589233728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2589233728
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1011460825
Short name T604
Test name
Test status
Simulation time 1277970411 ps
CPU time 7.6 seconds
Started Apr 27 04:12:31 PM PDT 24
Finished Apr 27 04:12:39 PM PDT 24
Peak memory 207968 kb
Host smart-4bd2df2c-ad2a-464b-b21a-c99b3ef59e55
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011460825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1011460825
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2897365378
Short name T1009
Test name
Test status
Simulation time 246209685 ps
CPU time 7.11 seconds
Started Apr 27 04:12:36 PM PDT 24
Finished Apr 27 04:12:44 PM PDT 24
Peak memory 207768 kb
Host smart-d5887e52-9c82-4b4c-a1b7-6c6dca315ebd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897365378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2897365378
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.512520102
Short name T1043
Test name
Test status
Simulation time 93079460 ps
CPU time 2.21 seconds
Started Apr 27 04:12:30 PM PDT 24
Finished Apr 27 04:12:32 PM PDT 24
Peak memory 208496 kb
Host smart-c9a7bec2-594f-468e-a8e7-4dbac7aa495f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512520102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.512520102
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2153222909
Short name T848
Test name
Test status
Simulation time 628312861 ps
CPU time 13.51 seconds
Started Apr 27 04:12:32 PM PDT 24
Finished Apr 27 04:12:46 PM PDT 24
Peak memory 214336 kb
Host smart-01bc4cbd-80c1-4489-b111-609816e1b4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153222909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2153222909
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3687180409
Short name T558
Test name
Test status
Simulation time 35022625 ps
CPU time 2.32 seconds
Started Apr 27 04:12:31 PM PDT 24
Finished Apr 27 04:12:34 PM PDT 24
Peak memory 206792 kb
Host smart-9a6be957-31f9-47cf-b6a0-575cbace5c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687180409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3687180409
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3800788188
Short name T224
Test name
Test status
Simulation time 142523340673 ps
CPU time 491.15 seconds
Started Apr 27 04:12:37 PM PDT 24
Finished Apr 27 04:20:49 PM PDT 24
Peak memory 230744 kb
Host smart-9074fe4e-c9f4-41c8-b87e-9eca7ba40d1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800788188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3800788188
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2045512275
Short name T669
Test name
Test status
Simulation time 565126696 ps
CPU time 4.59 seconds
Started Apr 27 04:12:32 PM PDT 24
Finished Apr 27 04:12:37 PM PDT 24
Peak memory 209236 kb
Host smart-1af5305f-96ee-4ab5-8b7c-3c2d00bf2329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045512275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2045512275
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1112766377
Short name T386
Test name
Test status
Simulation time 55888873 ps
CPU time 1.36 seconds
Started Apr 27 04:12:35 PM PDT 24
Finished Apr 27 04:12:37 PM PDT 24
Peak memory 209752 kb
Host smart-ce0f9b28-1824-42e8-afd0-0d57bfb1ade8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112766377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1112766377
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1254348787
Short name T588
Test name
Test status
Simulation time 29787228 ps
CPU time 1.11 seconds
Started Apr 27 04:12:41 PM PDT 24
Finished Apr 27 04:12:42 PM PDT 24
Peak memory 206052 kb
Host smart-343e5f63-7cdb-4be1-8402-2b5778b98486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254348787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1254348787
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.714331530
Short name T670
Test name
Test status
Simulation time 184954853 ps
CPU time 2.83 seconds
Started Apr 27 04:12:37 PM PDT 24
Finished Apr 27 04:12:41 PM PDT 24
Peak memory 214632 kb
Host smart-080fad70-dff4-4591-95ee-800be59df908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714331530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.714331530
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3135246092
Short name T914
Test name
Test status
Simulation time 565640302 ps
CPU time 8.13 seconds
Started Apr 27 04:12:35 PM PDT 24
Finished Apr 27 04:12:44 PM PDT 24
Peak memory 214376 kb
Host smart-b688ff08-e6fb-4a92-afc9-4e297933a546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135246092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3135246092
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1653444597
Short name T1039
Test name
Test status
Simulation time 271340399 ps
CPU time 7.14 seconds
Started Apr 27 04:12:35 PM PDT 24
Finished Apr 27 04:12:43 PM PDT 24
Peak memory 222436 kb
Host smart-baff155e-7021-4ca3-b1cc-7be11df2df16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653444597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1653444597
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.683238278
Short name T854
Test name
Test status
Simulation time 300602474 ps
CPU time 2.95 seconds
Started Apr 27 04:12:37 PM PDT 24
Finished Apr 27 04:12:41 PM PDT 24
Peak memory 220204 kb
Host smart-6095a970-6f70-4a01-80d3-948ac826e236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683238278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.683238278
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2762336022
Short name T653
Test name
Test status
Simulation time 1422082729 ps
CPU time 46.38 seconds
Started Apr 27 04:12:37 PM PDT 24
Finished Apr 27 04:13:25 PM PDT 24
Peak memory 218628 kb
Host smart-66b9bffe-7a45-44fe-b1c8-a16e7af6f691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762336022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2762336022
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2041447704
Short name T906
Test name
Test status
Simulation time 980605304 ps
CPU time 5.36 seconds
Started Apr 27 04:12:39 PM PDT 24
Finished Apr 27 04:12:45 PM PDT 24
Peak memory 208648 kb
Host smart-ce6fcfb9-5963-40b8-99f4-f0154150f92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041447704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2041447704
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3885697195
Short name T846
Test name
Test status
Simulation time 240579864 ps
CPU time 3.43 seconds
Started Apr 27 04:12:37 PM PDT 24
Finished Apr 27 04:12:41 PM PDT 24
Peak memory 206828 kb
Host smart-c47fd1cc-d5d0-496b-987b-71b791ab6b49
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885697195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3885697195
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2525636809
Short name T607
Test name
Test status
Simulation time 258359067 ps
CPU time 5.91 seconds
Started Apr 27 04:12:36 PM PDT 24
Finished Apr 27 04:12:43 PM PDT 24
Peak memory 208700 kb
Host smart-82d0937d-3d9e-4f7e-8000-a90e55debfdf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525636809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2525636809
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.78098595
Short name T1055
Test name
Test status
Simulation time 2876184675 ps
CPU time 5.34 seconds
Started Apr 27 04:12:36 PM PDT 24
Finished Apr 27 04:12:41 PM PDT 24
Peak memory 208084 kb
Host smart-887577bf-5bce-4f7c-a9ea-3d0722ae9891
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78098595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.78098595
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2976541083
Short name T658
Test name
Test status
Simulation time 256404019 ps
CPU time 2.68 seconds
Started Apr 27 04:12:40 PM PDT 24
Finished Apr 27 04:12:43 PM PDT 24
Peak memory 209116 kb
Host smart-6cd022c6-cdd8-4dc9-875b-e002bdc9067f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976541083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2976541083
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2933889177
Short name T1075
Test name
Test status
Simulation time 129911725 ps
CPU time 4.12 seconds
Started Apr 27 04:12:35 PM PDT 24
Finished Apr 27 04:12:40 PM PDT 24
Peak memory 206692 kb
Host smart-7653ae90-6d96-4bf0-90e3-c216902be677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933889177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2933889177
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1796667312
Short name T998
Test name
Test status
Simulation time 54824275 ps
CPU time 3.48 seconds
Started Apr 27 04:12:44 PM PDT 24
Finished Apr 27 04:12:48 PM PDT 24
Peak memory 222676 kb
Host smart-d2c8b090-f80b-461d-b182-42a29c9ac441
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796667312 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1796667312
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.29627296
Short name T641
Test name
Test status
Simulation time 33295264 ps
CPU time 2.62 seconds
Started Apr 27 04:12:36 PM PDT 24
Finished Apr 27 04:12:40 PM PDT 24
Peak memory 208740 kb
Host smart-8a83aa22-a009-43d9-882d-8ea97e91a3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29627296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.29627296
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1864359309
Short name T713
Test name
Test status
Simulation time 1787375753 ps
CPU time 22.72 seconds
Started Apr 27 04:12:35 PM PDT 24
Finished Apr 27 04:12:58 PM PDT 24
Peak memory 220868 kb
Host smart-1f1e0ca7-061b-424b-abba-210474778b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864359309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1864359309
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.841760534
Short name T584
Test name
Test status
Simulation time 22093220 ps
CPU time 1.01 seconds
Started Apr 27 04:12:53 PM PDT 24
Finished Apr 27 04:12:54 PM PDT 24
Peak memory 206076 kb
Host smart-6d4d3f0d-82cc-4bf0-a456-1f04fa24b5f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841760534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.841760534
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2891099502
Short name T219
Test name
Test status
Simulation time 46468310 ps
CPU time 2.77 seconds
Started Apr 27 04:12:41 PM PDT 24
Finished Apr 27 04:12:44 PM PDT 24
Peak memory 214896 kb
Host smart-e3a20d59-da26-445f-9407-bede1dcfb3cb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2891099502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2891099502
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2668739108
Short name T1076
Test name
Test status
Simulation time 294520091 ps
CPU time 1.96 seconds
Started Apr 27 04:12:47 PM PDT 24
Finished Apr 27 04:12:49 PM PDT 24
Peak memory 222748 kb
Host smart-52bb842f-2b81-4452-92a3-dc8fc433edcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668739108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2668739108
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2846897887
Short name T81
Test name
Test status
Simulation time 550898941 ps
CPU time 3.19 seconds
Started Apr 27 04:12:42 PM PDT 24
Finished Apr 27 04:12:46 PM PDT 24
Peak memory 218212 kb
Host smart-da517db8-f9b9-44aa-be21-35a3d69c54ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846897887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2846897887
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.2339947751
Short name T341
Test name
Test status
Simulation time 2805263685 ps
CPU time 14.68 seconds
Started Apr 27 04:12:43 PM PDT 24
Finished Apr 27 04:12:58 PM PDT 24
Peak memory 214344 kb
Host smart-65ff6c08-5886-48f1-83e8-300ae2c525ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339947751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.2339947751
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1105355004
Short name T8
Test name
Test status
Simulation time 100494043 ps
CPU time 3.69 seconds
Started Apr 27 04:12:42 PM PDT 24
Finished Apr 27 04:12:47 PM PDT 24
Peak memory 214328 kb
Host smart-35abc331-ac07-41a6-9a54-430fd03a8421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105355004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1105355004
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2785565658
Short name T566
Test name
Test status
Simulation time 10178028349 ps
CPU time 105 seconds
Started Apr 27 04:12:44 PM PDT 24
Finished Apr 27 04:14:30 PM PDT 24
Peak memory 222352 kb
Host smart-fa7e439b-6cca-40a7-99f0-a0a767135bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785565658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2785565658
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.3772150165
Short name T1072
Test name
Test status
Simulation time 2750993464 ps
CPU time 19.24 seconds
Started Apr 27 04:12:43 PM PDT 24
Finished Apr 27 04:13:02 PM PDT 24
Peak memory 208508 kb
Host smart-f1a69279-f1b1-4e56-822f-f790be53a602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772150165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.3772150165
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2415984519
Short name T778
Test name
Test status
Simulation time 1743587606 ps
CPU time 63.6 seconds
Started Apr 27 04:12:42 PM PDT 24
Finished Apr 27 04:13:46 PM PDT 24
Peak memory 208252 kb
Host smart-b6f55348-e00e-4f14-a66a-2efc2122fc14
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415984519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2415984519
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.356003670
Short name T901
Test name
Test status
Simulation time 858583054 ps
CPU time 21.11 seconds
Started Apr 27 04:12:44 PM PDT 24
Finished Apr 27 04:13:05 PM PDT 24
Peak memory 208116 kb
Host smart-af2da454-a037-4c2f-8f9f-d89e12851a30
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356003670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.356003670
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1381921044
Short name T760
Test name
Test status
Simulation time 69221900 ps
CPU time 3.27 seconds
Started Apr 27 04:12:44 PM PDT 24
Finished Apr 27 04:12:48 PM PDT 24
Peak memory 208160 kb
Host smart-b28d9092-6c48-4c66-a299-7a5c3db61bff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381921044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1381921044
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1886283281
Short name T583
Test name
Test status
Simulation time 251841725 ps
CPU time 4.53 seconds
Started Apr 27 04:12:50 PM PDT 24
Finished Apr 27 04:12:55 PM PDT 24
Peak memory 215784 kb
Host smart-95a3c7de-6a6a-4e54-8898-42bb3f65c4c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886283281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1886283281
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1331548310
Short name T409
Test name
Test status
Simulation time 170017379 ps
CPU time 4.34 seconds
Started Apr 27 04:12:41 PM PDT 24
Finished Apr 27 04:12:46 PM PDT 24
Peak memory 206916 kb
Host smart-6cfc2155-8f1e-456b-a3a4-e238ccc8e3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331548310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1331548310
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1675781273
Short name T915
Test name
Test status
Simulation time 2376378294 ps
CPU time 21.11 seconds
Started Apr 27 04:12:54 PM PDT 24
Finished Apr 27 04:13:16 PM PDT 24
Peak memory 216568 kb
Host smart-06655b9a-aef2-4f86-90c7-457f8dcbe96c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675781273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1675781273
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.97139089
Short name T52
Test name
Test status
Simulation time 572145693 ps
CPU time 6.76 seconds
Started Apr 27 04:12:47 PM PDT 24
Finished Apr 27 04:12:54 PM PDT 24
Peak memory 222524 kb
Host smart-ecd1cb71-7867-41c6-9b69-c7c1055a5be9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97139089 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.97139089
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.320199617
Short name T5
Test name
Test status
Simulation time 38245464 ps
CPU time 2.56 seconds
Started Apr 27 04:12:50 PM PDT 24
Finished Apr 27 04:12:53 PM PDT 24
Peak memory 207524 kb
Host smart-1a897a88-a8ca-4f5b-928b-434786a0b21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320199617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.320199617
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.530390615
Short name T390
Test name
Test status
Simulation time 32704582 ps
CPU time 1.93 seconds
Started Apr 27 04:12:54 PM PDT 24
Finished Apr 27 04:12:56 PM PDT 24
Peak memory 209920 kb
Host smart-fbf2bda5-9720-4166-afa6-9dc1a33fee5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530390615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.530390615
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.1493021894
Short name T759
Test name
Test status
Simulation time 83006922 ps
CPU time 1 seconds
Started Apr 27 04:12:48 PM PDT 24
Finished Apr 27 04:12:49 PM PDT 24
Peak memory 205956 kb
Host smart-97877f5e-fb4c-43b3-b92a-b2f46a59f401
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493021894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.1493021894
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2568763738
Short name T220
Test name
Test status
Simulation time 507280483 ps
CPU time 7.77 seconds
Started Apr 27 04:12:46 PM PDT 24
Finished Apr 27 04:12:54 PM PDT 24
Peak memory 214296 kb
Host smart-dd0ffddd-f095-4ded-9ce9-72532f4b369d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2568763738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2568763738
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.8289759
Short name T11
Test name
Test status
Simulation time 362955107 ps
CPU time 4.51 seconds
Started Apr 27 04:12:47 PM PDT 24
Finished Apr 27 04:12:53 PM PDT 24
Peak memory 214584 kb
Host smart-2208f51a-6e4f-4ece-b404-03b3287c92d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8289759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.8289759
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3114442481
Short name T239
Test name
Test status
Simulation time 332202416 ps
CPU time 4.23 seconds
Started Apr 27 04:12:48 PM PDT 24
Finished Apr 27 04:12:52 PM PDT 24
Peak memory 209596 kb
Host smart-e331e267-0ba1-4ca3-9f7b-27036982b43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114442481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3114442481
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3156015770
Short name T97
Test name
Test status
Simulation time 189144604 ps
CPU time 5.85 seconds
Started Apr 27 04:12:49 PM PDT 24
Finished Apr 27 04:12:55 PM PDT 24
Peak memory 208312 kb
Host smart-09c3fb8f-d322-4e3e-a900-d60a21e1b8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156015770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3156015770
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.4084190096
Short name T368
Test name
Test status
Simulation time 78977529 ps
CPU time 5.06 seconds
Started Apr 27 04:12:51 PM PDT 24
Finished Apr 27 04:12:56 PM PDT 24
Peak memory 222396 kb
Host smart-3b67b282-f92f-4d3f-adc9-685bf401b40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084190096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.4084190096
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2947039642
Short name T213
Test name
Test status
Simulation time 258355656 ps
CPU time 3.31 seconds
Started Apr 27 04:12:48 PM PDT 24
Finished Apr 27 04:12:52 PM PDT 24
Peak memory 214292 kb
Host smart-6990b53f-73d1-425f-8d89-5597a05b53cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947039642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2947039642
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.4159239657
Short name T569
Test name
Test status
Simulation time 88504601 ps
CPU time 2.54 seconds
Started Apr 27 04:12:46 PM PDT 24
Finished Apr 27 04:12:49 PM PDT 24
Peak memory 216244 kb
Host smart-e386c8d7-e9de-449a-9e4b-6b172f8a2aeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159239657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.4159239657
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3013666647
Short name T1060
Test name
Test status
Simulation time 1060436115 ps
CPU time 6.98 seconds
Started Apr 27 04:12:46 PM PDT 24
Finished Apr 27 04:12:53 PM PDT 24
Peak memory 208636 kb
Host smart-a81cec45-8b34-4cac-b2a2-bd4d82b56b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013666647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3013666647
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3022203413
Short name T549
Test name
Test status
Simulation time 1032615090 ps
CPU time 32.63 seconds
Started Apr 27 04:12:46 PM PDT 24
Finished Apr 27 04:13:19 PM PDT 24
Peak memory 208424 kb
Host smart-cd6ced6f-5b9a-4fc6-94ef-5978b4cc61c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022203413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3022203413
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2310376211
Short name T1013
Test name
Test status
Simulation time 1555836227 ps
CPU time 20.48 seconds
Started Apr 27 04:12:47 PM PDT 24
Finished Apr 27 04:13:08 PM PDT 24
Peak memory 208192 kb
Host smart-cc51e849-911e-4338-b1d7-dccc8ba61e1a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310376211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2310376211
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1992470606
Short name T812
Test name
Test status
Simulation time 51746166 ps
CPU time 2.5 seconds
Started Apr 27 04:12:48 PM PDT 24
Finished Apr 27 04:12:51 PM PDT 24
Peak memory 222388 kb
Host smart-1a367b53-8281-4ed2-b97b-98e694ead5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992470606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1992470606
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1955604272
Short name T415
Test name
Test status
Simulation time 1479871642 ps
CPU time 9.74 seconds
Started Apr 27 04:12:48 PM PDT 24
Finished Apr 27 04:12:59 PM PDT 24
Peak memory 206688 kb
Host smart-195760fc-2af8-4e7e-ab88-7c1eb6aa08fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955604272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1955604272
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1926778856
Short name T265
Test name
Test status
Simulation time 3279998965 ps
CPU time 18.47 seconds
Started Apr 27 04:12:47 PM PDT 24
Finished Apr 27 04:13:06 PM PDT 24
Peak memory 208060 kb
Host smart-56b166bb-74c3-41ae-8a93-6d0686d31bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926778856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1926778856
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1598208017
Short name T631
Test name
Test status
Simulation time 71782143 ps
CPU time 2.64 seconds
Started Apr 27 04:12:48 PM PDT 24
Finished Apr 27 04:12:51 PM PDT 24
Peak memory 210636 kb
Host smart-ef0f7698-b0e5-4b46-8d33-76420cd87023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598208017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1598208017
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2311037842
Short name T102
Test name
Test status
Simulation time 42404861 ps
CPU time 0.92 seconds
Started Apr 27 04:12:54 PM PDT 24
Finished Apr 27 04:12:56 PM PDT 24
Peak memory 205844 kb
Host smart-1b9524cc-604a-4725-a7aa-ea7bd326240a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311037842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2311037842
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1333806454
Short name T266
Test name
Test status
Simulation time 2257966724 ps
CPU time 30.68 seconds
Started Apr 27 04:12:46 PM PDT 24
Finished Apr 27 04:13:18 PM PDT 24
Peak memory 215236 kb
Host smart-4704a1ac-515d-446e-9e2b-d542de7065a9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1333806454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1333806454
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.505828719
Short name T54
Test name
Test status
Simulation time 255326522 ps
CPU time 3.47 seconds
Started Apr 27 04:12:55 PM PDT 24
Finished Apr 27 04:12:59 PM PDT 24
Peak memory 208316 kb
Host smart-2fe43f88-cd08-46e9-859a-64cad2d39f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505828719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.505828719
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.658226453
Short name T26
Test name
Test status
Simulation time 45810402 ps
CPU time 2.38 seconds
Started Apr 27 04:12:55 PM PDT 24
Finished Apr 27 04:12:58 PM PDT 24
Peak memory 209296 kb
Host smart-c0cb8950-9b82-413e-8a38-132f6f7e4b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658226453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.658226453
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3824628942
Short name T339
Test name
Test status
Simulation time 81674578 ps
CPU time 4.38 seconds
Started Apr 27 04:12:54 PM PDT 24
Finished Apr 27 04:13:00 PM PDT 24
Peak memory 211004 kb
Host smart-4b531c39-7474-49bb-ba77-131403b6b8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824628942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3824628942
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2053588636
Short name T73
Test name
Test status
Simulation time 79825979 ps
CPU time 4.14 seconds
Started Apr 27 04:12:54 PM PDT 24
Finished Apr 27 04:12:59 PM PDT 24
Peak memory 209036 kb
Host smart-bedb4a54-27e7-418e-a687-e9a4e59a2d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053588636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2053588636
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.257231792
Short name T983
Test name
Test status
Simulation time 2653533814 ps
CPU time 38.33 seconds
Started Apr 27 04:12:47 PM PDT 24
Finished Apr 27 04:13:26 PM PDT 24
Peak memory 208552 kb
Host smart-ec032cda-13da-4207-a805-8e66070fa4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257231792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.257231792
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1223971066
Short name T857
Test name
Test status
Simulation time 121330378 ps
CPU time 3.3 seconds
Started Apr 27 04:12:54 PM PDT 24
Finished Apr 27 04:12:57 PM PDT 24
Peak memory 208844 kb
Host smart-4a33fbff-3a68-45ca-a624-9600dae8e702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223971066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1223971066
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3589681530
Short name T644
Test name
Test status
Simulation time 465115511 ps
CPU time 13.92 seconds
Started Apr 27 04:12:49 PM PDT 24
Finished Apr 27 04:13:03 PM PDT 24
Peak memory 206884 kb
Host smart-2fdcd79c-8d83-4d34-a4dc-54f36c3630d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589681530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3589681530
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.527226218
Short name T798
Test name
Test status
Simulation time 5200086229 ps
CPU time 9.48 seconds
Started Apr 27 04:12:54 PM PDT 24
Finished Apr 27 04:13:04 PM PDT 24
Peak memory 207944 kb
Host smart-b1ce7f77-6e30-4486-91d6-124865fe00b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527226218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.527226218
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.4124903267
Short name T1008
Test name
Test status
Simulation time 1692640226 ps
CPU time 8.5 seconds
Started Apr 27 04:12:47 PM PDT 24
Finished Apr 27 04:12:56 PM PDT 24
Peak memory 208492 kb
Host smart-869e931b-6dd3-4022-a510-993174797aed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124903267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.4124903267
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.488032987
Short name T775
Test name
Test status
Simulation time 97129746 ps
CPU time 3.59 seconds
Started Apr 27 04:12:55 PM PDT 24
Finished Apr 27 04:12:59 PM PDT 24
Peak memory 218540 kb
Host smart-a2d6866d-06e1-41a0-9a39-08fb9eae1099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488032987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.488032987
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.926970081
Short name T413
Test name
Test status
Simulation time 162373776 ps
CPU time 4.58 seconds
Started Apr 27 04:12:53 PM PDT 24
Finished Apr 27 04:12:58 PM PDT 24
Peak memory 208228 kb
Host smart-37660397-7d4f-4f83-bce2-925310619af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926970081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.926970081
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2212652647
Short name T789
Test name
Test status
Simulation time 3213741144 ps
CPU time 47.1 seconds
Started Apr 27 04:12:54 PM PDT 24
Finished Apr 27 04:13:42 PM PDT 24
Peak memory 222528 kb
Host smart-5c4c2a3a-1a86-408f-a474-345a2e1df3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212652647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2212652647
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2968316084
Short name T728
Test name
Test status
Simulation time 346873968 ps
CPU time 6.84 seconds
Started Apr 27 04:12:54 PM PDT 24
Finished Apr 27 04:13:02 PM PDT 24
Peak memory 222620 kb
Host smart-979fb9de-c273-4a9d-9114-ce7701bd73a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968316084 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2968316084
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.236060078
Short name T1020
Test name
Test status
Simulation time 853880481 ps
CPU time 8.06 seconds
Started Apr 27 04:12:53 PM PDT 24
Finished Apr 27 04:13:02 PM PDT 24
Peak memory 208916 kb
Host smart-f053e273-88e7-4ee0-9571-df776387c694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236060078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.236060078
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.121795290
Short name T847
Test name
Test status
Simulation time 271362633 ps
CPU time 2.34 seconds
Started Apr 27 04:12:59 PM PDT 24
Finished Apr 27 04:13:02 PM PDT 24
Peak memory 210144 kb
Host smart-f1ca1b5d-b52d-4f16-a689-0932047f9b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121795290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.121795290
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1705443101
Short name T572
Test name
Test status
Simulation time 15910512 ps
CPU time 0.72 seconds
Started Apr 27 04:13:04 PM PDT 24
Finished Apr 27 04:13:05 PM PDT 24
Peak memory 205844 kb
Host smart-18fd4841-7dab-400d-97e2-462376bfe22a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705443101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1705443101
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1082767719
Short name T20
Test name
Test status
Simulation time 193387126 ps
CPU time 4.18 seconds
Started Apr 27 04:12:55 PM PDT 24
Finished Apr 27 04:12:59 PM PDT 24
Peak memory 214528 kb
Host smart-fd1b7a2b-3cf4-40f2-87ca-0c906238c3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082767719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1082767719
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.58453708
Short name T240
Test name
Test status
Simulation time 84194543 ps
CPU time 1.87 seconds
Started Apr 27 04:12:54 PM PDT 24
Finished Apr 27 04:12:57 PM PDT 24
Peak memory 208532 kb
Host smart-92560a98-73f7-4019-aed2-b2c32d4c1f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58453708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.58453708
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3879237178
Short name T365
Test name
Test status
Simulation time 1531397036 ps
CPU time 15.55 seconds
Started Apr 27 04:12:56 PM PDT 24
Finished Apr 27 04:13:12 PM PDT 24
Peak memory 214188 kb
Host smart-be716f61-795f-4433-9eff-bd52ebfef496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879237178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3879237178
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2941111899
Short name T613
Test name
Test status
Simulation time 223337755 ps
CPU time 3.29 seconds
Started Apr 27 04:12:56 PM PDT 24
Finished Apr 27 04:13:00 PM PDT 24
Peak memory 209232 kb
Host smart-adcbd01b-f4fd-4a7a-8abf-711a6cc7d4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941111899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2941111899
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2215753866
Short name T623
Test name
Test status
Simulation time 12556766107 ps
CPU time 50.25 seconds
Started Apr 27 04:12:55 PM PDT 24
Finished Apr 27 04:13:46 PM PDT 24
Peak memory 209272 kb
Host smart-d828d852-2555-4eed-87c3-af4a11c71c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215753866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2215753866
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.4257766373
Short name T414
Test name
Test status
Simulation time 574329629 ps
CPU time 3.37 seconds
Started Apr 27 04:13:00 PM PDT 24
Finished Apr 27 04:13:05 PM PDT 24
Peak memory 208480 kb
Host smart-b38710bb-499d-408a-8fe3-7fd96331c06f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257766373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.4257766373
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.691710355
Short name T811
Test name
Test status
Simulation time 206722278 ps
CPU time 3.28 seconds
Started Apr 27 04:12:56 PM PDT 24
Finished Apr 27 04:12:59 PM PDT 24
Peak memory 206748 kb
Host smart-e9e06452-1d82-4c77-98ec-133f88a6430e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691710355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.691710355
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2112633790
Short name T897
Test name
Test status
Simulation time 502833937 ps
CPU time 4.01 seconds
Started Apr 27 04:12:54 PM PDT 24
Finished Apr 27 04:12:58 PM PDT 24
Peak memory 207872 kb
Host smart-e3fae465-4635-4554-99f2-e8c9c7bb752f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112633790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2112633790
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.674835467
Short name T643
Test name
Test status
Simulation time 477121266 ps
CPU time 7.11 seconds
Started Apr 27 04:12:55 PM PDT 24
Finished Apr 27 04:13:03 PM PDT 24
Peak memory 208036 kb
Host smart-a0bd66ce-180a-4ade-a230-d2731238a543
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674835467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.674835467
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.702806363
Short name T389
Test name
Test status
Simulation time 64968935 ps
CPU time 2.74 seconds
Started Apr 27 04:13:01 PM PDT 24
Finished Apr 27 04:13:05 PM PDT 24
Peak memory 214304 kb
Host smart-14620ada-19c7-4150-9c2b-15640d9b0de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702806363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.702806363
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.4235430410
Short name T981
Test name
Test status
Simulation time 95482973 ps
CPU time 2.63 seconds
Started Apr 27 04:12:55 PM PDT 24
Finished Apr 27 04:12:59 PM PDT 24
Peak memory 206652 kb
Host smart-c11624b5-15d1-4a69-aacd-02bf55a494e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235430410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.4235430410
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.767529639
Short name T1036
Test name
Test status
Simulation time 3266417289 ps
CPU time 42.52 seconds
Started Apr 27 04:12:56 PM PDT 24
Finished Apr 27 04:13:39 PM PDT 24
Peak memory 222600 kb
Host smart-85375c7a-a93d-4418-bea0-600232132c25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767529639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.767529639
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.3779463973
Short name T605
Test name
Test status
Simulation time 87001458 ps
CPU time 5.38 seconds
Started Apr 27 04:12:57 PM PDT 24
Finished Apr 27 04:13:03 PM PDT 24
Peak memory 222584 kb
Host smart-1cfd253e-1669-487b-9361-fb0b776d2e78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779463973 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.3779463973
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1806298907
Short name T247
Test name
Test status
Simulation time 4717231564 ps
CPU time 51.55 seconds
Started Apr 27 04:12:55 PM PDT 24
Finished Apr 27 04:13:47 PM PDT 24
Peak memory 209604 kb
Host smart-607731b0-839b-4b93-a0ba-7ae91463717b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806298907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1806298907
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3845704539
Short name T65
Test name
Test status
Simulation time 94733306 ps
CPU time 3.04 seconds
Started Apr 27 04:13:00 PM PDT 24
Finished Apr 27 04:13:04 PM PDT 24
Peak memory 210380 kb
Host smart-40b91f46-34ff-4fb8-93ab-059b786f91e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845704539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3845704539
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.353920298
Short name T715
Test name
Test status
Simulation time 52578643 ps
CPU time 0.7 seconds
Started Apr 27 04:12:59 PM PDT 24
Finished Apr 27 04:13:01 PM PDT 24
Peak memory 205912 kb
Host smart-90d56b43-d81a-43f3-8649-753c8c862fc0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353920298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.353920298
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.312915431
Short name T1035
Test name
Test status
Simulation time 56390219 ps
CPU time 3.8 seconds
Started Apr 27 04:13:03 PM PDT 24
Finished Apr 27 04:13:08 PM PDT 24
Peak memory 215332 kb
Host smart-b9cd32ff-7a35-4c0c-8d37-7f135a041dfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=312915431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.312915431
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.3205462564
Short name T736
Test name
Test status
Simulation time 26318011 ps
CPU time 1.64 seconds
Started Apr 27 04:13:00 PM PDT 24
Finished Apr 27 04:13:03 PM PDT 24
Peak memory 207892 kb
Host smart-4c17e6b4-ca7b-4fb1-8ec5-00c1a56065bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205462564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.3205462564
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2850162269
Short name T91
Test name
Test status
Simulation time 1357664863 ps
CPU time 4.27 seconds
Started Apr 27 04:12:57 PM PDT 24
Finished Apr 27 04:13:02 PM PDT 24
Peak memory 218360 kb
Host smart-02610efb-31ef-4692-9114-c65c4bfd7bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850162269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2850162269
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.915046957
Short name T317
Test name
Test status
Simulation time 331767513 ps
CPU time 10.41 seconds
Started Apr 27 04:13:02 PM PDT 24
Finished Apr 27 04:13:13 PM PDT 24
Peak memory 222452 kb
Host smart-345e2046-cd03-4c2d-95d3-1572468fff76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915046957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.915046957
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1551930021
Short name T63
Test name
Test status
Simulation time 143754105 ps
CPU time 3.44 seconds
Started Apr 27 04:13:00 PM PDT 24
Finished Apr 27 04:13:05 PM PDT 24
Peak memory 216016 kb
Host smart-e65911d1-567e-4533-a541-11d65dc7d0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551930021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1551930021
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2205563327
Short name T271
Test name
Test status
Simulation time 1036432993 ps
CPU time 33.53 seconds
Started Apr 27 04:13:07 PM PDT 24
Finished Apr 27 04:13:41 PM PDT 24
Peak memory 208412 kb
Host smart-4167de67-8780-49fa-8233-826c8eca6fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205563327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2205563327
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2071685075
Short name T249
Test name
Test status
Simulation time 162344561 ps
CPU time 2.51 seconds
Started Apr 27 04:13:00 PM PDT 24
Finished Apr 27 04:13:04 PM PDT 24
Peak memory 207136 kb
Host smart-488bbb5a-d520-4ddf-9572-bc69baa3d92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071685075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2071685075
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2800074539
Short name T754
Test name
Test status
Simulation time 1252940036 ps
CPU time 4.45 seconds
Started Apr 27 04:12:59 PM PDT 24
Finished Apr 27 04:13:05 PM PDT 24
Peak memory 206760 kb
Host smart-788334db-5bfc-4217-90a1-76fa56a33931
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800074539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2800074539
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2703431843
Short name T882
Test name
Test status
Simulation time 133632391 ps
CPU time 4.51 seconds
Started Apr 27 04:12:59 PM PDT 24
Finished Apr 27 04:13:04 PM PDT 24
Peak memory 208716 kb
Host smart-68fcead1-781f-46b2-b78f-185c2d0da2a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703431843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2703431843
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2149132812
Short name T637
Test name
Test status
Simulation time 294359234 ps
CPU time 3.74 seconds
Started Apr 27 04:12:59 PM PDT 24
Finished Apr 27 04:13:04 PM PDT 24
Peak memory 208472 kb
Host smart-689053f2-8323-4192-a5e4-8ba4ce9317bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149132812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2149132812
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1383939216
Short name T907
Test name
Test status
Simulation time 408709057 ps
CPU time 3.75 seconds
Started Apr 27 04:13:08 PM PDT 24
Finished Apr 27 04:13:12 PM PDT 24
Peak memory 215812 kb
Host smart-3ded121d-9529-4c24-aa6e-68ed1815f123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383939216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1383939216
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1860905027
Short name T985
Test name
Test status
Simulation time 560957274 ps
CPU time 10.52 seconds
Started Apr 27 04:12:59 PM PDT 24
Finished Apr 27 04:13:11 PM PDT 24
Peak memory 207732 kb
Host smart-6697e98f-71b3-4f62-baae-01e1ca1c7993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860905027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1860905027
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3338782468
Short name T997
Test name
Test status
Simulation time 173776814 ps
CPU time 8.24 seconds
Started Apr 27 04:13:00 PM PDT 24
Finished Apr 27 04:13:10 PM PDT 24
Peak memory 209360 kb
Host smart-d007986a-4b38-4942-a164-4a8db3668cf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338782468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3338782468
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.316062725
Short name T123
Test name
Test status
Simulation time 523038416 ps
CPU time 7.49 seconds
Started Apr 27 04:12:58 PM PDT 24
Finished Apr 27 04:13:06 PM PDT 24
Peak memory 223096 kb
Host smart-45782247-900a-4cdf-b806-dffa642f5dbf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316062725 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.316062725
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2859382225
Short name T577
Test name
Test status
Simulation time 77237470 ps
CPU time 5.01 seconds
Started Apr 27 04:13:04 PM PDT 24
Finished Apr 27 04:13:10 PM PDT 24
Peak memory 214324 kb
Host smart-bad300dc-ffc0-4001-b961-29add513e61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859382225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2859382225
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1037474689
Short name T805
Test name
Test status
Simulation time 37791250 ps
CPU time 2.49 seconds
Started Apr 27 04:13:02 PM PDT 24
Finished Apr 27 04:13:05 PM PDT 24
Peak memory 210260 kb
Host smart-3426c4f5-9555-4ec2-ad30-bb3ba795913f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037474689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1037474689
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.367558226
Short name T587
Test name
Test status
Simulation time 14923938 ps
CPU time 0.8 seconds
Started Apr 27 04:13:07 PM PDT 24
Finished Apr 27 04:13:09 PM PDT 24
Peak memory 205832 kb
Host smart-63f9ed96-ad5c-480e-889a-e233b2de0405
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367558226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.367558226
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1040317942
Short name T294
Test name
Test status
Simulation time 702234746 ps
CPU time 12.15 seconds
Started Apr 27 04:13:01 PM PDT 24
Finished Apr 27 04:13:14 PM PDT 24
Peak memory 222476 kb
Host smart-976c7c46-bdef-4caf-8311-a9c849a9301a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1040317942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1040317942
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.489743102
Short name T10
Test name
Test status
Simulation time 147452887 ps
CPU time 3.9 seconds
Started Apr 27 04:13:09 PM PDT 24
Finished Apr 27 04:13:13 PM PDT 24
Peak memory 222792 kb
Host smart-655e5e9b-0a20-48b6-99ff-f2fe5cc89162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489743102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.489743102
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3163470528
Short name T76
Test name
Test status
Simulation time 288435851 ps
CPU time 2.94 seconds
Started Apr 27 04:13:09 PM PDT 24
Finished Apr 27 04:13:12 PM PDT 24
Peak memory 209240 kb
Host smart-3134f0cf-30cc-443a-8d76-0e478f914b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163470528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3163470528
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3380228318
Short name T711
Test name
Test status
Simulation time 98360530 ps
CPU time 2.45 seconds
Started Apr 27 04:13:00 PM PDT 24
Finished Apr 27 04:13:04 PM PDT 24
Peak memory 209004 kb
Host smart-e2d9ee37-e6a6-4273-b290-65bfb84fa712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380228318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3380228318
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1108991592
Short name T581
Test name
Test status
Simulation time 129232948 ps
CPU time 5.2 seconds
Started Apr 27 04:12:59 PM PDT 24
Finished Apr 27 04:13:06 PM PDT 24
Peak memory 210284 kb
Host smart-80de598e-a9e5-4420-a067-b67f112c377a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108991592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1108991592
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.776352389
Short name T1016
Test name
Test status
Simulation time 1057794849 ps
CPU time 8.07 seconds
Started Apr 27 04:13:03 PM PDT 24
Finished Apr 27 04:13:12 PM PDT 24
Peak memory 209504 kb
Host smart-b2fbe4c8-058c-4975-9fdc-e213c5088aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776352389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.776352389
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1140916674
Short name T256
Test name
Test status
Simulation time 271572738 ps
CPU time 3.04 seconds
Started Apr 27 04:12:59 PM PDT 24
Finished Apr 27 04:13:04 PM PDT 24
Peak memory 208980 kb
Host smart-63ee0f12-a5bf-403f-87be-f7cd5b46d068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140916674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1140916674
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2315311223
Short name T767
Test name
Test status
Simulation time 475996067 ps
CPU time 5.69 seconds
Started Apr 27 04:12:58 PM PDT 24
Finished Apr 27 04:13:05 PM PDT 24
Peak memory 206816 kb
Host smart-854ec398-1af3-4918-8b65-ab391461d534
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315311223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2315311223
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.4089645974
Short name T696
Test name
Test status
Simulation time 47949369 ps
CPU time 2.12 seconds
Started Apr 27 04:13:00 PM PDT 24
Finished Apr 27 04:13:03 PM PDT 24
Peak memory 207304 kb
Host smart-cd0f61d1-afe3-412c-800f-52c4aa241255
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089645974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.4089645974
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2151289897
Short name T602
Test name
Test status
Simulation time 709580545 ps
CPU time 6.02 seconds
Started Apr 27 04:13:01 PM PDT 24
Finished Apr 27 04:13:08 PM PDT 24
Peak memory 208064 kb
Host smart-04b2f679-bea8-40bd-a925-946dec61af6f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151289897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2151289897
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.437259988
Short name T979
Test name
Test status
Simulation time 175527128 ps
CPU time 3.38 seconds
Started Apr 27 04:13:00 PM PDT 24
Finished Apr 27 04:13:04 PM PDT 24
Peak memory 218128 kb
Host smart-ad7a3aa1-f081-4929-a2f9-32c8b9c7b9d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437259988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.437259988
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1593587443
Short name T806
Test name
Test status
Simulation time 292197596 ps
CPU time 4.16 seconds
Started Apr 27 04:13:01 PM PDT 24
Finished Apr 27 04:13:06 PM PDT 24
Peak memory 208328 kb
Host smart-38a9f1f0-943f-41f1-8076-bd774dbf9fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593587443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1593587443
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3469379734
Short name T853
Test name
Test status
Simulation time 275498091 ps
CPU time 6.64 seconds
Started Apr 27 04:13:06 PM PDT 24
Finished Apr 27 04:13:13 PM PDT 24
Peak memory 222592 kb
Host smart-eab5eb34-5f2d-43c1-b51d-0b7cd5fbb6e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469379734 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3469379734
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.622798295
Short name T603
Test name
Test status
Simulation time 234862376 ps
CPU time 3.04 seconds
Started Apr 27 04:13:03 PM PDT 24
Finished Apr 27 04:13:07 PM PDT 24
Peak memory 210336 kb
Host smart-7f5b6c31-614e-480c-a450-4be81ab6a47e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622798295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.622798295
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1484606470
Short name T601
Test name
Test status
Simulation time 29996775 ps
CPU time 0.79 seconds
Started Apr 27 04:13:13 PM PDT 24
Finished Apr 27 04:13:14 PM PDT 24
Peak memory 205840 kb
Host smart-320bd04b-43a5-432d-b9d4-339ac0b6effb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484606470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1484606470
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3644184581
Short name T150
Test name
Test status
Simulation time 525586010 ps
CPU time 2.38 seconds
Started Apr 27 04:13:03 PM PDT 24
Finished Apr 27 04:13:06 PM PDT 24
Peak memory 214332 kb
Host smart-45f3dcf9-1e1d-4bed-a13d-12f7e98dae77
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3644184581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3644184581
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.455570721
Short name T908
Test name
Test status
Simulation time 63040085 ps
CPU time 2.83 seconds
Started Apr 27 04:13:10 PM PDT 24
Finished Apr 27 04:13:14 PM PDT 24
Peak memory 217692 kb
Host smart-e29db662-ef6a-429f-82dc-ead8d4f5bde4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455570721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.455570721
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1307171522
Short name T82
Test name
Test status
Simulation time 285480761 ps
CPU time 2.35 seconds
Started Apr 27 04:13:04 PM PDT 24
Finished Apr 27 04:13:07 PM PDT 24
Peak memory 208576 kb
Host smart-a8bc5aa2-77cc-4385-9c35-2bfe0e0209ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307171522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1307171522
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1369324109
Short name T1052
Test name
Test status
Simulation time 433690114 ps
CPU time 3.62 seconds
Started Apr 27 04:13:08 PM PDT 24
Finished Apr 27 04:13:12 PM PDT 24
Peak memory 219144 kb
Host smart-eb9a6914-5e33-4761-97a6-a173f885d996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369324109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1369324109
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.658024854
Short name T197
Test name
Test status
Simulation time 243805271 ps
CPU time 4.83 seconds
Started Apr 27 04:13:05 PM PDT 24
Finished Apr 27 04:13:10 PM PDT 24
Peak memory 214228 kb
Host smart-0d9459dc-53fc-44bf-86bc-d54adcd97913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658024854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.658024854
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_random.1646302189
Short name T281
Test name
Test status
Simulation time 221695744 ps
CPU time 8.34 seconds
Started Apr 27 04:13:03 PM PDT 24
Finished Apr 27 04:13:12 PM PDT 24
Peak memory 209892 kb
Host smart-63643af4-b9c6-4ab8-acee-f80f760f57b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646302189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1646302189
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.460350100
Short name T1001
Test name
Test status
Simulation time 366524376 ps
CPU time 4.22 seconds
Started Apr 27 04:13:06 PM PDT 24
Finished Apr 27 04:13:11 PM PDT 24
Peak memory 208512 kb
Host smart-bd3ddb11-b1c2-49be-8608-eb3736f62c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460350100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.460350100
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1647934387
Short name T721
Test name
Test status
Simulation time 71668065 ps
CPU time 3.21 seconds
Started Apr 27 04:13:07 PM PDT 24
Finished Apr 27 04:13:10 PM PDT 24
Peak memory 206748 kb
Host smart-e696f9a3-8f3c-4392-a23b-363a09f8d5e1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647934387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1647934387
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1776398226
Short name T133
Test name
Test status
Simulation time 51340277 ps
CPU time 2.9 seconds
Started Apr 27 04:13:05 PM PDT 24
Finished Apr 27 04:13:08 PM PDT 24
Peak memory 207020 kb
Host smart-2caa3c51-f8c5-4b8b-a120-7c90e4f8424e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776398226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1776398226
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.4226428379
Short name T625
Test name
Test status
Simulation time 1640224321 ps
CPU time 7.76 seconds
Started Apr 27 04:13:03 PM PDT 24
Finished Apr 27 04:13:12 PM PDT 24
Peak memory 208080 kb
Host smart-c767e3bd-d735-4b5f-b476-673cb0b033a5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226428379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.4226428379
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.241506803
Short name T911
Test name
Test status
Simulation time 257606228 ps
CPU time 2.17 seconds
Started Apr 27 04:13:10 PM PDT 24
Finished Apr 27 04:13:13 PM PDT 24
Peak memory 215324 kb
Host smart-1feab2f9-b3e1-4151-88b3-46cda3b522b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241506803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.241506803
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.4144169659
Short name T1028
Test name
Test status
Simulation time 136101132 ps
CPU time 3.56 seconds
Started Apr 27 04:13:04 PM PDT 24
Finished Apr 27 04:13:08 PM PDT 24
Peak memory 208408 kb
Host smart-9682bf3b-6456-47e1-9d1c-8bc11120b91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144169659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.4144169659
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1781791060
Short name T590
Test name
Test status
Simulation time 143862786 ps
CPU time 6.45 seconds
Started Apr 27 04:13:10 PM PDT 24
Finished Apr 27 04:13:17 PM PDT 24
Peak memory 216480 kb
Host smart-a51bcbac-f1fd-45e6-a4de-6453b2bf3899
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781791060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1781791060
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.265385287
Short name T327
Test name
Test status
Simulation time 147037862 ps
CPU time 5.08 seconds
Started Apr 27 04:13:06 PM PDT 24
Finished Apr 27 04:13:11 PM PDT 24
Peak memory 218188 kb
Host smart-ba14cad3-fad6-4c5e-a10a-4be5eb62b0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265385287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.265385287
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.991836411
Short name T823
Test name
Test status
Simulation time 81321769 ps
CPU time 3.16 seconds
Started Apr 27 04:13:09 PM PDT 24
Finished Apr 27 04:13:12 PM PDT 24
Peak memory 210084 kb
Host smart-012f82e7-4057-4cec-aa79-80839fc243e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991836411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.991836411
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2047929589
Short name T647
Test name
Test status
Simulation time 35261992 ps
CPU time 0.83 seconds
Started Apr 27 04:09:28 PM PDT 24
Finished Apr 27 04:09:29 PM PDT 24
Peak memory 205904 kb
Host smart-e2564bf4-866d-400f-9c3a-fd15280bac94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047929589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2047929589
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2810515512
Short name T398
Test name
Test status
Simulation time 293906781 ps
CPU time 14.47 seconds
Started Apr 27 04:09:22 PM PDT 24
Finished Apr 27 04:09:37 PM PDT 24
Peak memory 215092 kb
Host smart-b26d48d6-f2c5-4fa8-bb35-a8cf7fad901b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2810515512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2810515512
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2933996874
Short name T814
Test name
Test status
Simulation time 76746621 ps
CPU time 2.43 seconds
Started Apr 27 04:09:28 PM PDT 24
Finished Apr 27 04:09:31 PM PDT 24
Peak memory 219132 kb
Host smart-99b2c9f3-9357-4b2f-b245-181c2702de5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933996874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2933996874
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3784015665
Short name T617
Test name
Test status
Simulation time 276962076 ps
CPU time 2.82 seconds
Started Apr 27 04:09:22 PM PDT 24
Finished Apr 27 04:09:26 PM PDT 24
Peak memory 208536 kb
Host smart-e76ab909-689e-49c5-adf9-813ab70514bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784015665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3784015665
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3109320305
Short name T1010
Test name
Test status
Simulation time 129072099 ps
CPU time 2.67 seconds
Started Apr 27 04:09:30 PM PDT 24
Finished Apr 27 04:09:33 PM PDT 24
Peak memory 209012 kb
Host smart-ca07e058-5cd0-457b-bfb7-e3b70db1a802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109320305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3109320305
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.49545905
Short name T764
Test name
Test status
Simulation time 97520882 ps
CPU time 3.29 seconds
Started Apr 27 04:09:23 PM PDT 24
Finished Apr 27 04:09:27 PM PDT 24
Peak memory 219796 kb
Host smart-910e6be5-190a-4799-bd88-3a49d90d812d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49545905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.49545905
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1497416908
Short name T903
Test name
Test status
Simulation time 57289984 ps
CPU time 3.12 seconds
Started Apr 27 04:09:24 PM PDT 24
Finished Apr 27 04:09:27 PM PDT 24
Peak memory 208840 kb
Host smart-0bc57f49-8f9f-427f-8680-e45cddf3dd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497416908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1497416908
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.855492991
Short name T702
Test name
Test status
Simulation time 1041881017 ps
CPU time 2.78 seconds
Started Apr 27 04:09:23 PM PDT 24
Finished Apr 27 04:09:26 PM PDT 24
Peak memory 206908 kb
Host smart-866fc8a9-a40e-4222-912c-6811658c825b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855492991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.855492991
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.391038876
Short name T298
Test name
Test status
Simulation time 154567847 ps
CPU time 3.98 seconds
Started Apr 27 04:09:23 PM PDT 24
Finished Apr 27 04:09:28 PM PDT 24
Peak memory 208568 kb
Host smart-d976d119-a39e-42e0-93fe-9f680c14ab0f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391038876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.391038876
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.4092224187
Short name T227
Test name
Test status
Simulation time 763631454 ps
CPU time 6.6 seconds
Started Apr 27 04:09:24 PM PDT 24
Finished Apr 27 04:09:31 PM PDT 24
Peak memory 207784 kb
Host smart-0484ddaf-0094-4a01-93c2-3be1f3bfce5b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092224187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.4092224187
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3441150730
Short name T800
Test name
Test status
Simulation time 454789306 ps
CPU time 4.36 seconds
Started Apr 27 04:09:22 PM PDT 24
Finished Apr 27 04:09:26 PM PDT 24
Peak memory 206700 kb
Host smart-1b78ba7e-99e3-46fe-94ae-55f39d534008
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441150730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3441150730
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2635783010
Short name T1062
Test name
Test status
Simulation time 137276940 ps
CPU time 3.55 seconds
Started Apr 27 04:09:28 PM PDT 24
Finished Apr 27 04:09:32 PM PDT 24
Peak memory 215900 kb
Host smart-15bb70f5-ea4b-4806-ad55-57d2412d2fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635783010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2635783010
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2135659342
Short name T799
Test name
Test status
Simulation time 5399630531 ps
CPU time 30.49 seconds
Started Apr 27 04:09:24 PM PDT 24
Finished Apr 27 04:09:55 PM PDT 24
Peak memory 208832 kb
Host smart-8507d0f7-1c7c-4798-a848-916cd8f65ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135659342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2135659342
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.1564652579
Short name T595
Test name
Test status
Simulation time 58206970 ps
CPU time 4.17 seconds
Started Apr 27 04:09:28 PM PDT 24
Finished Apr 27 04:09:32 PM PDT 24
Peak memory 222544 kb
Host smart-6a613cec-cf46-4b6f-a18d-d013eb667bf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564652579 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.1564652579
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1460357301
Short name T326
Test name
Test status
Simulation time 3496786616 ps
CPU time 10.36 seconds
Started Apr 27 04:09:24 PM PDT 24
Finished Apr 27 04:09:35 PM PDT 24
Peak memory 208156 kb
Host smart-7b19d278-882a-49ea-8068-6eb50fb8e792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460357301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1460357301
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1047222111
Short name T878
Test name
Test status
Simulation time 140107074 ps
CPU time 3.51 seconds
Started Apr 27 04:09:27 PM PDT 24
Finished Apr 27 04:09:31 PM PDT 24
Peak memory 210324 kb
Host smart-549e5e58-263b-4fe1-bb9e-cbece0036119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047222111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1047222111
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.37984992
Short name T797
Test name
Test status
Simulation time 79212891 ps
CPU time 0.74 seconds
Started Apr 27 04:09:34 PM PDT 24
Finished Apr 27 04:09:35 PM PDT 24
Peak memory 205864 kb
Host smart-92239bdc-a0a5-424b-992e-9361851998a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37984992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.37984992
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.352730677
Short name T403
Test name
Test status
Simulation time 106555511 ps
CPU time 4.06 seconds
Started Apr 27 04:09:27 PM PDT 24
Finished Apr 27 04:09:32 PM PDT 24
Peak memory 214320 kb
Host smart-da4aedeb-de0f-4708-979b-05faf84f742d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352730677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.352730677
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1656332691
Short name T769
Test name
Test status
Simulation time 94987112 ps
CPU time 1.56 seconds
Started Apr 27 04:09:28 PM PDT 24
Finished Apr 27 04:09:30 PM PDT 24
Peak memory 207752 kb
Host smart-231a90c9-858e-4c3a-8946-01a382354af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656332691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1656332691
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3722989976
Short name T330
Test name
Test status
Simulation time 55694430 ps
CPU time 3.86 seconds
Started Apr 27 04:09:33 PM PDT 24
Finished Apr 27 04:09:38 PM PDT 24
Peak memory 208972 kb
Host smart-1cf9a052-66aa-4869-91a9-9e60f6b6fa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722989976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3722989976
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.4051147490
Short name T1034
Test name
Test status
Simulation time 298234777 ps
CPU time 5.54 seconds
Started Apr 27 04:09:40 PM PDT 24
Finished Apr 27 04:09:46 PM PDT 24
Peak memory 214196 kb
Host smart-f97de713-f8b9-4a33-94ad-985a5075ebfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051147490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.4051147490
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3151931346
Short name T586
Test name
Test status
Simulation time 290831522 ps
CPU time 5.41 seconds
Started Apr 27 04:09:28 PM PDT 24
Finished Apr 27 04:09:34 PM PDT 24
Peak memory 220576 kb
Host smart-76e236fc-fb15-4505-8849-87dfaf571cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151931346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3151931346
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1847217308
Short name T1000
Test name
Test status
Simulation time 225016023 ps
CPU time 5.06 seconds
Started Apr 27 04:09:30 PM PDT 24
Finished Apr 27 04:09:36 PM PDT 24
Peak memory 217036 kb
Host smart-415969bb-95ab-42c0-8eb3-c70f93b9becf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847217308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1847217308
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1179032016
Short name T346
Test name
Test status
Simulation time 92027616 ps
CPU time 1.82 seconds
Started Apr 27 04:09:28 PM PDT 24
Finished Apr 27 04:09:30 PM PDT 24
Peak memory 206724 kb
Host smart-d81c55db-3d64-4988-8948-353e81f6617d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179032016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1179032016
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.2698964073
Short name T1064
Test name
Test status
Simulation time 364041821 ps
CPU time 4.8 seconds
Started Apr 27 04:09:28 PM PDT 24
Finished Apr 27 04:09:33 PM PDT 24
Peak memory 206880 kb
Host smart-6d48ce4a-f3fa-4a66-9d94-9c2eccf2cbc1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698964073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2698964073
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3939089961
Short name T363
Test name
Test status
Simulation time 67596660 ps
CPU time 3.55 seconds
Started Apr 27 04:09:28 PM PDT 24
Finished Apr 27 04:09:32 PM PDT 24
Peak memory 206776 kb
Host smart-d0b2e31a-7992-43a5-b497-913518997e85
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939089961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3939089961
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.4265247892
Short name T579
Test name
Test status
Simulation time 2845179625 ps
CPU time 51.92 seconds
Started Apr 27 04:09:28 PM PDT 24
Finished Apr 27 04:10:21 PM PDT 24
Peak memory 209180 kb
Host smart-0c85b753-57ac-419c-9e5f-b3eb72735611
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265247892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.4265247892
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2484382354
Short name T260
Test name
Test status
Simulation time 329447509 ps
CPU time 2.37 seconds
Started Apr 27 04:09:33 PM PDT 24
Finished Apr 27 04:09:36 PM PDT 24
Peak memory 214284 kb
Host smart-5ef8ef39-9be3-4c0f-b3cd-4b78d501a0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484382354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2484382354
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.766723719
Short name T973
Test name
Test status
Simulation time 223574927 ps
CPU time 3.07 seconds
Started Apr 27 04:09:28 PM PDT 24
Finished Apr 27 04:09:32 PM PDT 24
Peak memory 207268 kb
Host smart-66a2c0f2-f0e2-4a76-b7db-29dbe2988e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766723719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.766723719
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1401461279
Short name T1017
Test name
Test status
Simulation time 1784948564 ps
CPU time 34.22 seconds
Started Apr 27 04:09:34 PM PDT 24
Finished Apr 27 04:10:09 PM PDT 24
Peak memory 222496 kb
Host smart-a19495fe-788e-4c80-a65a-cdd17b30139d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401461279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1401461279
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.873327245
Short name T401
Test name
Test status
Simulation time 225758644 ps
CPU time 4.33 seconds
Started Apr 27 04:09:27 PM PDT 24
Finished Apr 27 04:09:32 PM PDT 24
Peak memory 209516 kb
Host smart-f228e20e-fa3b-4028-a9c3-268a1c36d083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873327245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.873327245
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1125482096
Short name T968
Test name
Test status
Simulation time 35636397 ps
CPU time 0.9 seconds
Started Apr 27 04:09:44 PM PDT 24
Finished Apr 27 04:09:46 PM PDT 24
Peak memory 205896 kb
Host smart-76761b35-764b-4c1c-a0ac-3663ffaf0e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125482096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1125482096
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2192879116
Short name T259
Test name
Test status
Simulation time 164043313 ps
CPU time 3.53 seconds
Started Apr 27 04:09:39 PM PDT 24
Finished Apr 27 04:09:42 PM PDT 24
Peak memory 214352 kb
Host smart-b4e7b1f3-36ef-46da-997e-bdb8de05c8fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2192879116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2192879116
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1206096689
Short name T773
Test name
Test status
Simulation time 62841937 ps
CPU time 2.23 seconds
Started Apr 27 04:09:40 PM PDT 24
Finished Apr 27 04:09:43 PM PDT 24
Peak memory 207164 kb
Host smart-903960fc-da43-454b-a83d-fa8981a88b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206096689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1206096689
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.40859956
Short name T618
Test name
Test status
Simulation time 189478041 ps
CPU time 6.62 seconds
Started Apr 27 04:09:40 PM PDT 24
Finished Apr 27 04:09:47 PM PDT 24
Peak memory 209132 kb
Host smart-05f4441d-c115-4127-b1fc-7bac673738b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40859956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.40859956
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3643130131
Short name T99
Test name
Test status
Simulation time 184775128 ps
CPU time 3.36 seconds
Started Apr 27 04:09:41 PM PDT 24
Finished Apr 27 04:09:44 PM PDT 24
Peak memory 222432 kb
Host smart-cdc6f119-2146-452f-a70c-bf10ab63383f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643130131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3643130131
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.193213965
Short name T987
Test name
Test status
Simulation time 32722007 ps
CPU time 2.52 seconds
Started Apr 27 04:09:40 PM PDT 24
Finished Apr 27 04:09:43 PM PDT 24
Peak memory 214412 kb
Host smart-c436b86f-8e9b-4670-820b-8b475ccf8985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193213965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.193213965
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.840804189
Short name T1005
Test name
Test status
Simulation time 96746721 ps
CPU time 4.92 seconds
Started Apr 27 04:09:38 PM PDT 24
Finished Apr 27 04:09:44 PM PDT 24
Peak memory 208368 kb
Host smart-ebd3d8a3-6894-484e-b8f4-0fa21ffec827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840804189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.840804189
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.613537889
Short name T578
Test name
Test status
Simulation time 705702010 ps
CPU time 19.6 seconds
Started Apr 27 04:09:40 PM PDT 24
Finished Apr 27 04:10:00 PM PDT 24
Peak memory 207904 kb
Host smart-9df9aad6-f435-436b-853d-846ba9be4005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613537889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.613537889
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1018759695
Short name T701
Test name
Test status
Simulation time 36215807 ps
CPU time 2.53 seconds
Started Apr 27 04:09:42 PM PDT 24
Finished Apr 27 04:09:44 PM PDT 24
Peak memory 207620 kb
Host smart-a54a7fc0-feb5-434a-ad92-a355704fe2f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018759695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1018759695
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.4061055920
Short name T917
Test name
Test status
Simulation time 118345452 ps
CPU time 2.28 seconds
Started Apr 27 04:09:41 PM PDT 24
Finished Apr 27 04:09:44 PM PDT 24
Peak memory 208824 kb
Host smart-752383f0-4dc9-4b93-b1e5-68eb88479787
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061055920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.4061055920
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2919920675
Short name T688
Test name
Test status
Simulation time 96223258 ps
CPU time 3.25 seconds
Started Apr 27 04:09:40 PM PDT 24
Finished Apr 27 04:09:43 PM PDT 24
Peak memory 206872 kb
Host smart-5846321f-a26a-42ed-9a94-2b54b0815e94
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919920675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2919920675
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.674590081
Short name T574
Test name
Test status
Simulation time 510602387 ps
CPU time 6.7 seconds
Started Apr 27 04:09:41 PM PDT 24
Finished Apr 27 04:09:48 PM PDT 24
Peak memory 214248 kb
Host smart-50641b34-67c9-49e1-a178-35eeb7663855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674590081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.674590081
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.455315924
Short name T730
Test name
Test status
Simulation time 251152007 ps
CPU time 3.15 seconds
Started Apr 27 04:09:33 PM PDT 24
Finished Apr 27 04:09:37 PM PDT 24
Peak memory 208648 kb
Host smart-76dc0728-5c88-4dae-af1c-d96668a4ecd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455315924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.455315924
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.319473031
Short name T299
Test name
Test status
Simulation time 435253447 ps
CPU time 18.43 seconds
Started Apr 27 04:09:40 PM PDT 24
Finished Apr 27 04:09:59 PM PDT 24
Peak memory 216560 kb
Host smart-96649101-d510-42c3-93a2-7c44c3c01563
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319473031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.319473031
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.574283109
Short name T591
Test name
Test status
Simulation time 483565125 ps
CPU time 6.9 seconds
Started Apr 27 04:09:47 PM PDT 24
Finished Apr 27 04:09:54 PM PDT 24
Peak memory 223728 kb
Host smart-8cef17cf-e19f-46a9-af13-c0b8b959f3d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574283109 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.574283109
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3918105316
Short name T810
Test name
Test status
Simulation time 629924985 ps
CPU time 6.91 seconds
Started Apr 27 04:09:40 PM PDT 24
Finished Apr 27 04:09:48 PM PDT 24
Peak memory 208748 kb
Host smart-7a93b157-b54d-4cc4-b21d-a9c11f7f6f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918105316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3918105316
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.705268514
Short name T560
Test name
Test status
Simulation time 212000859 ps
CPU time 2.11 seconds
Started Apr 27 04:09:40 PM PDT 24
Finished Apr 27 04:09:42 PM PDT 24
Peak memory 210096 kb
Host smart-c1d88916-6aab-41fd-a963-da29df98a257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705268514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.705268514
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3907834988
Short name T681
Test name
Test status
Simulation time 37719241 ps
CPU time 0.73 seconds
Started Apr 27 04:09:55 PM PDT 24
Finished Apr 27 04:09:56 PM PDT 24
Peak memory 205796 kb
Host smart-f030bf9d-c41c-4c5b-a9fe-012eaa71beaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907834988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3907834988
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3425818882
Short name T397
Test name
Test status
Simulation time 814607880 ps
CPU time 16.21 seconds
Started Apr 27 04:09:45 PM PDT 24
Finished Apr 27 04:10:01 PM PDT 24
Peak memory 214312 kb
Host smart-fd99611c-d91f-40a9-9e7e-35b98bad6403
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3425818882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3425818882
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.4148616625
Short name T791
Test name
Test status
Simulation time 233268382 ps
CPU time 3.73 seconds
Started Apr 27 04:09:53 PM PDT 24
Finished Apr 27 04:09:57 PM PDT 24
Peak memory 209568 kb
Host smart-85560084-1c91-4874-bf2b-6b18969ab60c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148616625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.4148616625
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.482258154
Short name T766
Test name
Test status
Simulation time 424883562 ps
CPU time 5.24 seconds
Started Apr 27 04:09:45 PM PDT 24
Finished Apr 27 04:09:51 PM PDT 24
Peak memory 214376 kb
Host smart-33d00234-21d6-47f4-bcca-8118d07fcaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482258154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.482258154
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.3474350109
Short name T680
Test name
Test status
Simulation time 193064726 ps
CPU time 3.72 seconds
Started Apr 27 04:09:47 PM PDT 24
Finished Apr 27 04:09:51 PM PDT 24
Peak memory 208688 kb
Host smart-554d27b3-6d6f-4fe4-acd9-ead2c341d5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474350109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.3474350109
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3695904350
Short name T364
Test name
Test status
Simulation time 256156978 ps
CPU time 2.9 seconds
Started Apr 27 04:09:44 PM PDT 24
Finished Apr 27 04:09:47 PM PDT 24
Peak memory 214496 kb
Host smart-cbb3b61b-61e6-4294-bfa3-dbfb73d351c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695904350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3695904350
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.374833927
Short name T768
Test name
Test status
Simulation time 165618831 ps
CPU time 2.6 seconds
Started Apr 27 04:09:47 PM PDT 24
Finished Apr 27 04:09:50 PM PDT 24
Peak memory 214280 kb
Host smart-2f10f9a4-5568-41d4-90d7-632117bc60ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374833927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.374833927
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3125505912
Short name T129
Test name
Test status
Simulation time 8448076725 ps
CPU time 17.49 seconds
Started Apr 27 04:09:46 PM PDT 24
Finished Apr 27 04:10:03 PM PDT 24
Peak memory 218532 kb
Host smart-181d2b2c-1f5e-4520-9a0f-be19d5392552
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125505912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3125505912
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3899700818
Short name T956
Test name
Test status
Simulation time 162722243 ps
CPU time 5.13 seconds
Started Apr 27 04:09:47 PM PDT 24
Finished Apr 27 04:09:52 PM PDT 24
Peak memory 207804 kb
Host smart-464121fd-24a7-48cf-9a6f-73f28c9c00d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899700818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3899700818
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.327342588
Short name T545
Test name
Test status
Simulation time 155899859 ps
CPU time 2.87 seconds
Started Apr 27 04:09:48 PM PDT 24
Finished Apr 27 04:09:51 PM PDT 24
Peak memory 208800 kb
Host smart-8ae6cb84-9818-4a7d-9866-ce5cca0492da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327342588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.327342588
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2852249080
Short name T107
Test name
Test status
Simulation time 88557314 ps
CPU time 2.05 seconds
Started Apr 27 04:09:48 PM PDT 24
Finished Apr 27 04:09:51 PM PDT 24
Peak memory 208768 kb
Host smart-40476d77-f09e-4e7f-898d-41740b1bb929
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852249080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2852249080
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3563921583
Short name T593
Test name
Test status
Simulation time 90420154 ps
CPU time 3.68 seconds
Started Apr 27 04:09:46 PM PDT 24
Finished Apr 27 04:09:50 PM PDT 24
Peak memory 208628 kb
Host smart-05ddb6fe-1983-494c-bfb1-bc2049de1d4d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563921583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3563921583
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.4034663612
Short name T843
Test name
Test status
Simulation time 241349242 ps
CPU time 3.07 seconds
Started Apr 27 04:09:46 PM PDT 24
Finished Apr 27 04:09:49 PM PDT 24
Peak memory 215688 kb
Host smart-bbb77c15-db49-44f7-8417-3210cdc68ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034663612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.4034663612
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3466489456
Short name T856
Test name
Test status
Simulation time 1519444926 ps
CPU time 44 seconds
Started Apr 27 04:09:46 PM PDT 24
Finished Apr 27 04:10:31 PM PDT 24
Peak memory 208336 kb
Host smart-3b1efdad-6818-4b92-a1cf-389b240e0b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466489456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3466489456
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2738833028
Short name T301
Test name
Test status
Simulation time 3939287420 ps
CPU time 32.6 seconds
Started Apr 27 04:09:48 PM PDT 24
Finished Apr 27 04:10:21 PM PDT 24
Peak memory 222540 kb
Host smart-3cb961d2-fc05-44bb-8d57-3ec083d55861
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738833028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2738833028
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.106899380
Short name T892
Test name
Test status
Simulation time 291297692 ps
CPU time 6.61 seconds
Started Apr 27 04:09:46 PM PDT 24
Finished Apr 27 04:09:53 PM PDT 24
Peak memory 222560 kb
Host smart-f7915d8b-f442-47eb-84a7-9c3cbadbb2d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106899380 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.106899380
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.279285543
Short name T334
Test name
Test status
Simulation time 157939349 ps
CPU time 3.72 seconds
Started Apr 27 04:09:45 PM PDT 24
Finished Apr 27 04:09:49 PM PDT 24
Peak memory 208456 kb
Host smart-084da7cd-57c7-40ce-868c-8c7657f29323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279285543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.279285543
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2828752657
Short name T42
Test name
Test status
Simulation time 184424451 ps
CPU time 4.45 seconds
Started Apr 27 04:09:47 PM PDT 24
Finished Apr 27 04:09:52 PM PDT 24
Peak memory 210464 kb
Host smart-76ad0c29-8c9b-4de5-8e46-779b2301f748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828752657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2828752657
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2887092569
Short name T925
Test name
Test status
Simulation time 48432288 ps
CPU time 0.88 seconds
Started Apr 27 04:09:53 PM PDT 24
Finished Apr 27 04:09:54 PM PDT 24
Peak memory 205796 kb
Host smart-2f7c77ce-9f4b-4793-a552-76f94a1032be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887092569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2887092569
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1360193250
Short name T922
Test name
Test status
Simulation time 44026587 ps
CPU time 2.89 seconds
Started Apr 27 04:09:50 PM PDT 24
Finished Apr 27 04:09:54 PM PDT 24
Peak memory 214348 kb
Host smart-7bfaf2b7-3141-4f06-923d-43967c916588
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1360193250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1360193250
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3028957815
Short name T85
Test name
Test status
Simulation time 54198421 ps
CPU time 2.57 seconds
Started Apr 27 04:09:51 PM PDT 24
Finished Apr 27 04:09:54 PM PDT 24
Peak memory 208716 kb
Host smart-7974dce5-3534-405d-93df-940467b652f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028957815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3028957815
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.452715381
Short name T975
Test name
Test status
Simulation time 218711957 ps
CPU time 4.62 seconds
Started Apr 27 04:09:52 PM PDT 24
Finished Apr 27 04:09:57 PM PDT 24
Peak memory 208604 kb
Host smart-0c09c3d6-6100-4971-b4fa-9259989b46d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452715381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.452715381
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2093952462
Short name T27
Test name
Test status
Simulation time 59117383 ps
CPU time 3.17 seconds
Started Apr 27 04:09:53 PM PDT 24
Finished Apr 27 04:09:57 PM PDT 24
Peak memory 222496 kb
Host smart-aab56e0b-0a77-4975-b343-2897af902fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093952462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2093952462
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.229434567
Short name T399
Test name
Test status
Simulation time 157505638 ps
CPU time 2.73 seconds
Started Apr 27 04:09:55 PM PDT 24
Finished Apr 27 04:09:58 PM PDT 24
Peak memory 222376 kb
Host smart-d604f1b3-d3d8-413e-86f1-6a5f56f0b348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229434567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.229434567
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2082183040
Short name T899
Test name
Test status
Simulation time 224830178 ps
CPU time 4.16 seconds
Started Apr 27 04:09:54 PM PDT 24
Finished Apr 27 04:09:58 PM PDT 24
Peak memory 208464 kb
Host smart-53e507dd-b882-4657-85ed-fa5245e72178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082183040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2082183040
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3885232707
Short name T1068
Test name
Test status
Simulation time 104702553 ps
CPU time 2.25 seconds
Started Apr 27 04:09:55 PM PDT 24
Finished Apr 27 04:09:58 PM PDT 24
Peak memory 208552 kb
Host smart-058db5a4-57d1-492a-8a64-aedd140aa9f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885232707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3885232707
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2956440615
Short name T562
Test name
Test status
Simulation time 578777579 ps
CPU time 4.37 seconds
Started Apr 27 04:09:54 PM PDT 24
Finished Apr 27 04:09:58 PM PDT 24
Peak memory 206660 kb
Host smart-c4dfc515-a19d-47ac-b6a9-9167335a6390
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956440615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2956440615
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3887814212
Short name T883
Test name
Test status
Simulation time 751068366 ps
CPU time 6.47 seconds
Started Apr 27 04:09:50 PM PDT 24
Finished Apr 27 04:09:57 PM PDT 24
Peak memory 208856 kb
Host smart-7d72ba1e-3e73-477f-93cb-77d9a89866c4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887814212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3887814212
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3011070621
Short name T868
Test name
Test status
Simulation time 440073201 ps
CPU time 5.46 seconds
Started Apr 27 04:09:52 PM PDT 24
Finished Apr 27 04:09:58 PM PDT 24
Peak memory 208952 kb
Host smart-297990da-888c-43af-848c-f89ea75f21ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011070621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3011070621
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3572134031
Short name T996
Test name
Test status
Simulation time 37314797 ps
CPU time 2.26 seconds
Started Apr 27 04:09:53 PM PDT 24
Finished Apr 27 04:09:56 PM PDT 24
Peak memory 214400 kb
Host smart-5cde4899-d14b-47cc-860e-be1c278d11a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572134031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3572134031
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3372384453
Short name T965
Test name
Test status
Simulation time 631216678 ps
CPU time 5.09 seconds
Started Apr 27 04:09:49 PM PDT 24
Finished Apr 27 04:09:55 PM PDT 24
Peak memory 208468 kb
Host smart-d320fe7c-1096-401a-bb2f-474ca608f0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372384453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3372384453
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.847517267
Short name T712
Test name
Test status
Simulation time 168304687 ps
CPU time 8.22 seconds
Started Apr 27 04:09:53 PM PDT 24
Finished Apr 27 04:10:01 PM PDT 24
Peak memory 219888 kb
Host smart-871d506a-0353-49e9-a82d-6dc0f07d87c7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847517267 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.847517267
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2499713853
Short name T1044
Test name
Test status
Simulation time 119905339 ps
CPU time 5.55 seconds
Started Apr 27 04:09:51 PM PDT 24
Finished Apr 27 04:09:57 PM PDT 24
Peak memory 214300 kb
Host smart-f89fbbf3-09f1-4831-9bc2-d4bdb38281aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499713853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2499713853
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.4017532410
Short name T671
Test name
Test status
Simulation time 153794605 ps
CPU time 2.12 seconds
Started Apr 27 04:09:53 PM PDT 24
Finished Apr 27 04:09:56 PM PDT 24
Peak memory 210120 kb
Host smart-e86a18a4-9e9a-4f2f-89ef-5e32c6a7e8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017532410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.4017532410
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%