Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
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Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
68.25 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv


Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 14 1 13 92.86
Crosses 49 19 30 61.22


Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
op_cp 5 1 4 80.00 100 1 1 0
state_cp 7 0 7 100.00 100 1 1 0
wip_cp 2 0 2 100.00 100 1 1 2


Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
state_x_wip_cross 14 1 13 92.86 100 1 1 0
state_x_op_cross 35 18 17 48.57 100 1 1 0


Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 1 4 80.00


Automatically Generated Bins for op_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
auto[OpDisable] 0 1 1


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[OpAdvance] 66 1 T3 1 T42 1 T43 1
auto[OpGenId] 15 1 T7 1 T8 1 T76 1
auto[OpGenSwOut] 35 1 T3 1 T102 1 T7 1
auto[OpGenHwOut] 21 1 T6 1 T7 1 T45 1


Summary for Variable state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for state_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] 1805 1 T3 3 T42 1 T102 3
auto[StInit] 151 1 T3 2 T43 1 T35 1
auto[StCreatorRootKey] 60 1 T30 1 T102 1 T124 2
auto[StOwnerIntKey] 40 1 T7 1 T26 1 T124 1
auto[StOwnerKey] 34 1 T60 1 T64 1 T61 1
auto[StDisabled] 369 1 T7 4 T48 13 T67 1
auto[StInvalid] 42 1 T16 1 T20 1 T39 1


Summary for Variable wip_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wip_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3437 1 T1 1 T2 1 T3 4
auto[1] 137 1 T3 2 T42 1 T43 1


Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 14 1 13 92.86 1


Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins
state_cpwip_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] [auto[1]] 0 1 1


Covered bins
state_cp   wip_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[0] 1791 1 T3 2 T102 3 T7 2
auto[StReset] auto[1] 14 1 T3 1 T42 1 T115 2
auto[StInit] auto[0] 73 1 T3 1 T35 1 T87 1
auto[StInit] auto[1] 78 1 T3 1 T43 1 T102 1
auto[StCreatorRootKey] auto[0] 41 1 T30 1 T124 2 T51 1
auto[StCreatorRootKey] auto[1] 19 1 T102 1 T203 1 T31 1
auto[StOwnerIntKey] auto[0] 28 1 T124 1 T56 1 T58 1
auto[StOwnerIntKey] auto[1] 12 1 T7 1 T26 1 T57 1
auto[StOwnerKey] auto[0] 21 1 T60 1 T61 1 T65 2
auto[StOwnerKey] auto[1] 13 1 T64 1 T204 1 T205 1
auto[StDisabled] auto[0] 368 1 T7 4 T48 13 T67 1
auto[StDisabled] auto[1] 1 1 T206 1 - - - -
auto[StInvalid] auto[0] 42 1 T16 1 T20 1 T39 1


Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 35 18 17 48.57 18


Automatically Generated Cross Bins for state_x_op_cross

Element holes
state_cpop_cpCOUNTAT LEASTNUMBERSTATUS
[auto[StInvalid]] * -- -- 5


Uncovered bins
state_cp   op_cp   COUNT   AT LEAST   NUMBER   STATUS   
[auto[StReset]] [auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]] -- -- 4
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]] [auto[OpDisable]] -- -- 3
[auto[StOwnerKey]] [auto[OpGenHwOut] , auto[OpDisable]] -- -- 2
[auto[StDisabled]] [auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]] -- -- 4


Covered bins
state_cp   op_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] auto[OpAdvance] 14 1 T3 1 T42 1 T115 2
auto[StInit] auto[OpAdvance] 30 1 T43 1 T114 3 T115 1
auto[StInit] auto[OpGenId] 9 1 T7 1 T8 1 T76 1
auto[StInit] auto[OpGenSwOut] 24 1 T3 1 T102 1 T114 2
auto[StInit] auto[OpGenHwOut] 15 1 T6 1 T7 1 T45 1
auto[StCreatorRootKey] auto[OpAdvance] 10 1 T102 1 T203 1 T207 1
auto[StCreatorRootKey] auto[OpGenId] 2 1 T208 1 T209 1 - -
auto[StCreatorRootKey] auto[OpGenSwOut] 3 1 T66 1 T55 1 T210 1
auto[StCreatorRootKey] auto[OpGenHwOut] 4 1 T31 1 T211 1 T212 1
auto[StOwnerIntKey] auto[OpAdvance] 5 1 T26 1 T44 1 T150 1
auto[StOwnerIntKey] auto[OpGenId] 2 1 T213 1 T214 1 - -
auto[StOwnerIntKey] auto[OpGenSwOut] 3 1 T7 1 T57 1 T215 1
auto[StOwnerIntKey] auto[OpGenHwOut] 2 1 T70 1 T216 1 - -
auto[StOwnerKey] auto[OpAdvance] 6 1 T204 1 T205 1 T217 1
auto[StOwnerKey] auto[OpGenId] 2 1 T218 1 T219 1 - -
auto[StOwnerKey] auto[OpGenSwOut] 5 1 T64 1 T220 1 T221 1
auto[StDisabled] auto[OpAdvance] 1 1 T206 1 - - - -