Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11371

1

T1

5

T2

3

T3

1

auto[Attestation]

7700

1

T1

3

T2

8

T4

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2751	1			T2	2		T5	2		T12	1
auto[Aes]	3362	1			T2	3		T5	11		T12	1
auto[Kmac]	3474	1			T2	1		T4	8		T5	5
auto[Otbn]	3508	1			T1	8		T3	1		T5	5

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7575	1			T1	8		T2	8		T3	2
auto[OpGenId]	5976	1			T2	5		T5	4		T12	4
auto[OpGenSwOut]	5974	1			T2	6		T3	1		T5	14
auto[OpGenHwOut]	7121	1			T1	8		T4	8		T5	9
auto[OpDisable]	131	1			T46	1		T47	1		T48	4

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9827

1

T1

8

T2

8

T3

2

auto[OpDoneFail]

16950

1

T1

8

T2

11

T3

1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6441	1			T1	1		T2	4		T3	3
auto[StInit]	4327	1			T1	2		T2	2		T4	2
auto[StCreatorRootKey]	2868	1			T1	2		T2	2		T4	2
auto[StOwnerIntKey]	2519	1			T1	2		T2	2		T4	2
auto[StOwnerKey]	2296	1			T1	2		T2	2		T4	2
auto[StDisabled]	7367	1			T1	7		T2	7		T4	7
auto[StInvalid]	959	1			T16	32		T20	28		T39	28

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	320	1			T2	1		T18	1		T89	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	114	1			T25	1		T21	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	86	1			T5	1		T12	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	58	1			T25	1		T120	1		T135	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	55	1			T48	4		T59	2		T60	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	181	1			T21	1		T120	3		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	37	1			T16	2		T39	1		T96	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	334	1			T5	4		T16	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	106	1			T5	1		T20	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	80	1			T5	1		T194	1		T135	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	67	1			T133	1		T48	1		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	53	1			T5	1		T194	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	221	1			T12	1		T133	1		T7	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	32	1			T20	1		T39	1		T96	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	354	1			T2	1		T5	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	117	1			T5	1		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	76	1			T124	1		T48	3		T59	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	62	1			T17	1		T18	1		T86	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	61	1			T7	2		T196	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	229	1			T5	1		T17	1		T18	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	30	1			T16	4		T20	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	347	1			T3	1		T18	1		T89	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	117	1			T21	1		T22	1		T102	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	66	1			T5	1		T195	1		T180	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	66	1			T48	1		T60	2		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	71	1			T18	1		T21	1		T183	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	177	1			T5	1		T18	3		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	27	1			T20	1		T97	4		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	50	1			T7	2		T124	4		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	116	1			T22	1		T23	1		T7	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T25	1		T46	1		T182	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T120	1		T48	1		T56	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	55	1			T48	1		T60	2		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	214	1			T2	1		T18	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	29	1			T16	1		T20	2		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	57	1			T16	1		T7	1		T124	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	113	1			T2	1		T120	1		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	72	1			T180	1		T184	2		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	55	1			T18	2		T133	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	35	1			T195	1		T182	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	196	1			T2	2		T120	1		T7	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	28	1			T39	1		T91	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	82	1			T16	1		T7	1		T124	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	130	1			T43	1		T120	1		T131	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	77	1			T102	1		T46	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T25	1		T48	2		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	66	1			T7	1		T48	2		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	174	1			T12	1		T18	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	35	1			T16	3		T20	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	64	1			T7	2		T124	2		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	121	1			T22	1		T24	2		T184	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T181	1		T59	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T12	1		T21	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	63	1			T5	1		T40	1		T89	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	192	1			T120	1		T7	4		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	36	1			T16	1		T39	1		T96	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	293	1			T18	1		T89	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	104	1			T7	1		T24	3		T124	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	76	1			T133	1		T46	1		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	50	1			T120	1		T48	2		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	45	1			T120	1		T48	1		T60	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	166	1			T5	1		T18	1		T48	5
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	27	1			T20	1		T39	2		T91	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	468	1			T16	1		T18	1		T89	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	140	1			T30	1		T21	1		T22	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	98	1			T41	1		T21	1		T103	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	83	1			T103	1		T135	2		T7	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	89	1			T84	1		T184	1		T48	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	267	1			T5	2		T40	1		T25	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	31	1			T96	1		T199	1		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	439	1			T5	1		T18	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	136	1			T4	1		T20	1		T21	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T17	1		T21	1		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	95	1			T21	1		T83	1		T182	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	96	1			T4	1		T201	1		T182	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	263	1			T4	1		T17	1		T89	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	21	1			T16	2		T199	1		T202	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	531	1			T5	2		T16	1		T89	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	156	1			T21	1		T35	1		T138	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	106	1			T1	1		T133	1		T180	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T138	1		T135	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	102	1			T7	1		T184	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	256	1			T1	4		T25	3		T138	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	21	1			T16	2		T20	1		T91	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	69	1			T16	3		T7	3		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	115	1			T43	1		T30	1		T22	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	48	1			T181	1		T183	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	68	1			T18	1		T25	2		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	41	1			T182	1		T184	2		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	161	1			T18	1		T25	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	35	1			T20	2		T39	2		T96	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	51	1			T7	1		T124	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	140	1			T5	1		T134	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	90	1			T41	1		T25	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	84	1			T25	1		T134	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	91	1			T103	1		T134	1		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	251	1			T5	1		T103	1		T134	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	30	1			T16	1		T20	3		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	62	1			T16	2		T124	3		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	130	1			T40	1		T131	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	99	1			T4	1		T131	2		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T4	1		T89	1		T135	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	85	1			T83	1		T182	1		T183	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	263	1			T4	3		T5	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	31	1			T16	2		T20	1		T39	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	62	1			T7	2		T124	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	126	1			T1	1		T89	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	96	1			T18	1		T41	2		T138	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	87	1			T1	1		T132	1		T133	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	69	1			T1	1		T138	1		T132	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	275	1			T18	2		T40	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	25	1			T16	1		T20	1		T199	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	189	1			T5	1		T12	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	662	1			T2	1		T16	2		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	189	1			T5	2		T194	2		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	704	1			T5	5		T12	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	189	1			T17	1		T18	1		T7	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	740	1			T2	1		T5	3		T16	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	193	1			T5	1		T18	1		T21	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	678	1			T3	1		T5	1		T18	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	182	1			T120	1		T46	1		T182	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	420	1			T2	1		T16	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	153	1			T18	2		T133	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	403	1			T2	3		T16	1		T120	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	204	1			T25	1		T102	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	434	1			T12	1		T16	4		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	197	1			T5	1		T12	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	437	1			T16	1		T120	1		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	152	1			T120	2		T133	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	609	1			T5	1		T18	2		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	257	1			T41	1		T21	1		T103	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	919	1			T5	2		T16	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	279	1			T4	1		T17	1		T21	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	871	1			T4	2		T5	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	294	1			T1	1		T138	1		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	969	1			T1	4		T5	2		T16	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	145	1			T18	1		T25	2		T7	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	392	1			T16	3		T18	1		T20	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	249	1			T41	1		T25	2		T103	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	488	1			T5	2		T16	1		T20	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	256	1			T4	2		T89	1		T131	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	501	1			T4	3		T5	1		T16	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	238	1			T1	2		T18	1		T41	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	502	1			T1	1		T16	1		T18	2