Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30675

1

T1

22

T2

21

T3

6

auto[1]

284

1

T18

5

T120

6

T148

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30680	1			T1	22		T2	21		T3	6
auto[134217728:268435455]	10	1			T222	1		T229	1		T408	2
auto[268435456:402653183]	12	1			T229	1		T277	1		T252	1
auto[402653184:536870911]	6	1			T237	1		T277	1		T357	1
auto[536870912:671088639]	12	1			T18	2		T355	1		T245	1
auto[671088640:805306367]	7	1			T245	1		T222	1		T409	1
auto[805306368:939524095]	10	1			T148	1		T197	1		T237	1
auto[939524096:1073741823]	12	1			T18	1		T109	1		T252	1
auto[1073741824:1207959551]	8	1			T18	1		T148	2		T222	1
auto[1207959552:1342177279]	10	1			T120	1		T197	1		T245	1
auto[1342177280:1476395007]	6	1			T222	2		T301	1		T410	1
auto[1476395008:1610612735]	7	1			T197	1		T277	2		T408	1
auto[1610612736:1744830463]	10	1			T18	1		T148	1		T299	1
auto[1744830464:1879048191]	7	1			T120	1		T285	1		T409	1
auto[1879048192:2013265919]	9	1			T277	1		T410	2		T408	1
auto[2013265920:2147483647]	7	1			T245	1		T301	1		T277	1
auto[2147483648:2281701375]	6	1			T237	1		T408	1		T311	1
auto[2281701376:2415919103]	13	1			T222	1		T252	1		T267	1
auto[2415919104:2550136831]	9	1			T197	1		T111	1		T229	1
auto[2550136832:2684354559]	10	1			T197	1		T109	1		T408	1
auto[2684354560:2818572287]	7	1			T120	1		T277	1		T252	1
auto[2818572288:2952790015]	10	1			T148	1		T245	1		T301	1
auto[2952790016:3087007743]	7	1			T120	1		T409	1		T411	1
auto[3087007744:3221225471]	9	1			T299	1		T245	1		T109	1
auto[3221225472:3355443199]	5	1			T408	1		T359	1		T411	1
auto[3355443200:3489660927]	12	1			T222	2		T229	1		T277	1
auto[3489660928:3623878655]	4	1			T311	2		T412	2		-	-
auto[3623878656:3758096383]	9	1			T148	1		T222	1		T109	1
auto[3758096384:3892314111]	12	1			T222	2		T109	1		T229	1
auto[3892314112:4026531839]	8	1			T120	2		T222	1		T277	1
auto[4026531840:4160749567]	11	1			T245	1		T410	1		T359	1
auto[4160749568:4294967295]	14	1			T148	1		T222	1		T237	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30675	1			T1	22		T2	21		T3	6
auto[0:134217727]	auto[1]	5	1			T148	1		T311	1		T268	1
auto[134217728:268435455]	auto[1]	10	1			T222	1		T229	1		T408	2
auto[268435456:402653183]	auto[1]	12	1			T229	1		T277	1		T252	1
auto[402653184:536870911]	auto[1]	6	1			T237	1		T277	1		T357	1
auto[536870912:671088639]	auto[1]	12	1			T18	2		T355	1		T245	1
auto[671088640:805306367]	auto[1]	7	1			T245	1		T222	1		T409	1
auto[805306368:939524095]	auto[1]	10	1			T148	1		T197	1		T237	1
auto[939524096:1073741823]	auto[1]	12	1			T18	1		T109	1		T252	1
auto[1073741824:1207959551]	auto[1]	8	1			T18	1		T148	2		T222	1
auto[1207959552:1342177279]	auto[1]	10	1			T120	1		T197	1		T245	1
auto[1342177280:1476395007]	auto[1]	6	1			T222	2		T301	1		T410	1
auto[1476395008:1610612735]	auto[1]	7	1			T197	1		T277	2		T408	1
auto[1610612736:1744830463]	auto[1]	10	1			T18	1		T148	1		T299	1
auto[1744830464:1879048191]	auto[1]	7	1			T120	1		T285	1		T409	1
auto[1879048192:2013265919]	auto[1]	9	1			T277	1		T410	2		T408	1
auto[2013265920:2147483647]	auto[1]	7	1			T245	1		T301	1		T277	1
auto[2147483648:2281701375]	auto[1]	6	1			T237	1		T408	1		T311	1
auto[2281701376:2415919103]	auto[1]	13	1			T222	1		T252	1		T267	1
auto[2415919104:2550136831]	auto[1]	9	1			T197	1		T111	1		T229	1
auto[2550136832:2684354559]	auto[1]	10	1			T197	1		T109	1		T408	1
auto[2684354560:2818572287]	auto[1]	7	1			T120	1		T277	1		T252	1
auto[2818572288:2952790015]	auto[1]	10	1			T148	1		T245	1		T301	1
auto[2952790016:3087007743]	auto[1]	7	1			T120	1		T409	1		T411	1
auto[3087007744:3221225471]	auto[1]	9	1			T299	1		T245	1		T109	1
auto[3221225472:3355443199]	auto[1]	5	1			T408	1		T359	1		T411	1
auto[3355443200:3489660927]	auto[1]	12	1			T222	2		T229	1		T277	1
auto[3489660928:3623878655]	auto[1]	4	1			T311	2		T412	2		-	-
auto[3623878656:3758096383]	auto[1]	9	1			T148	1		T222	1		T109	1
auto[3758096384:3892314111]	auto[1]	12	1			T222	2		T109	1		T229	1
auto[3892314112:4026531839]	auto[1]	8	1			T120	2		T222	1		T277	1
auto[4026531840:4160749567]	auto[1]	11	1			T245	1		T410	1		T359	1
auto[4160749568:4294967295]	auto[1]	14	1			T148	1		T222	1		T237	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1491

1

T5

1

T16

9

T18

4

auto[1]

1651

1

T3

1

T5

5

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T16	1		T41	1		T21	1
auto[134217728:268435455]	106	1			T120	1		T86	1		T182	1
auto[268435456:402653183]	108	1			T16	1		T20	1		T7	2
auto[402653184:536870911]	102	1			T42	2		T22	3		T7	1
auto[536870912:671088639]	98	1			T120	1		T133	1		T47	1
auto[671088640:805306367]	101	1			T7	1		T8	2		T24	1
auto[805306368:939524095]	124	1			T16	1		T42	1		T20	1
auto[939524096:1073741823]	102	1			T18	1		T6	1		T7	2
auto[1073741824:1207959551]	87	1			T43	1		T21	1		T22	1
auto[1207959552:1342177279]	111	1			T16	1		T133	1		T6	1
auto[1342177280:1476395007]	107	1			T195	1		T114	2		T181	1
auto[1476395008:1610612735]	84	1			T43	1		T41	1		T7	1
auto[1610612736:1744830463]	84	1			T5	1		T25	1		T7	1
auto[1744830464:1879048191]	91	1			T46	1		T7	1		T24	1
auto[1879048192:2013265919]	92	1			T3	1		T43	1		T114	1
auto[2013265920:2147483647]	92	1			T7	1		T182	1		T48	2
auto[2147483648:2281701375]	88	1			T16	1		T21	1		T135	1
auto[2281701376:2415919103]	111	1			T5	1		T7	1		T87	1
auto[2415919104:2550136831]	83	1			T20	1		T30	1		T195	1
auto[2550136832:2684354559]	104	1			T5	2		T7	2		T124	1
auto[2684354560:2818572287]	103	1			T16	1		T23	1		T135	1
auto[2818572288:2952790015]	99	1			T18	1		T43	1		T87	1
auto[2952790016:3087007743]	93	1			T16	3		T18	2		T43	1
auto[3087007744:3221225471]	77	1			T16	1		T18	1		T7	2
auto[3221225472:3355443199]	81	1			T43	2		T39	1		T45	1
auto[3355443200:3489660927]	99	1			T7	2		T47	1		T39	1
auto[3489660928:3623878655]	105	1			T16	1		T42	1		T20	1
auto[3623878656:3758096383]	119	1			T20	1		T21	1		T22	1
auto[3758096384:3892314111]	104	1			T5	1		T42	1		T30	1
auto[3892314112:4026531839]	96	1			T22	1		T131	1		T7	1
auto[4026531840:4160749567]	93	1			T5	1		T102	1		T87	1
auto[4160749568:4294967295]	109	1			T20	1		T25	2		T6	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T16	1		T41	1		T22	1
auto[0:134217727]	auto[1]	47	1			T21	1		T120	1		T23	1
auto[134217728:268435455]	auto[0]	53	1			T86	1		T182	1		T197	1
auto[134217728:268435455]	auto[1]	53	1			T120	1		T124	1		T44	1
auto[268435456:402653183]	auto[0]	50	1			T16	1		T7	2		T90	1
auto[268435456:402653183]	auto[1]	58	1			T20	1		T196	1		T232	1
auto[402653184:536870911]	auto[0]	54	1			T42	1		T22	3		T7	1
auto[402653184:536870911]	auto[1]	48	1			T42	1		T86	1		T236	1
auto[536870912:671088639]	auto[0]	51	1			T120	1		T47	1		T124	1
auto[536870912:671088639]	auto[1]	47	1			T133	1		T60	1		T300	1
auto[671088640:805306367]	auto[0]	47	1			T7	1		T8	2		T24	1
auto[671088640:805306367]	auto[1]	54	1			T60	2		T96	1		T56	1
auto[805306368:939524095]	auto[0]	61	1			T42	1		T43	1		T114	1
auto[805306368:939524095]	auto[1]	63	1			T16	1		T20	1		T131	1
auto[939524096:1073741823]	auto[0]	51	1			T18	1		T6	1		T7	1
auto[939524096:1073741823]	auto[1]	51	1			T7	1		T26	1		T184	1
auto[1073741824:1207959551]	auto[0]	43	1			T43	1		T59	1		T60	1
auto[1073741824:1207959551]	auto[1]	44	1			T21	1		T22	1		T133	1
auto[1207959552:1342177279]	auto[0]	38	1			T16	1		T6	1		T39	1
auto[1207959552:1342177279]	auto[1]	73	1			T133	1		T185	1		T48	4
auto[1342177280:1476395007]	auto[0]	49	1			T114	1		T90	1		T57	1
auto[1342177280:1476395007]	auto[1]	58	1			T195	1		T114	1		T181	1
auto[1476395008:1610612735]	auto[0]	34	1			T43	1		T7	1		T45	1
auto[1476395008:1610612735]	auto[1]	50	1			T41	1		T60	1		T70	2
auto[1610612736:1744830463]	auto[0]	36	1			T24	1		T182	1		T96	1
auto[1610612736:1744830463]	auto[1]	48	1			T5	1		T25	1		T7	1
auto[1744830464:1879048191]	auto[0]	46	1			T46	1		T24	1		T195	1
auto[1744830464:1879048191]	auto[1]	45	1			T7	1		T48	1		T60	2
auto[1879048192:2013265919]	auto[0]	52	1			T43	1		T114	1		T183	1
auto[1879048192:2013265919]	auto[1]	40	1			T3	1		T115	1		T60	3
auto[2013265920:2147483647]	auto[0]	46	1			T182	1		T48	1		T96	1
auto[2013265920:2147483647]	auto[1]	46	1			T7	1		T48	1		T60	1
auto[2147483648:2281701375]	auto[0]	35	1			T16	1		T21	1		T195	1
auto[2147483648:2281701375]	auto[1]	53	1			T135	1		T60	1		T96	1
auto[2281701376:2415919103]	auto[0]	53	1			T7	1		T87	1		T91	1
auto[2281701376:2415919103]	auto[1]	58	1			T5	1		T48	1		T148	1
auto[2415919104:2550136831]	auto[0]	32	1			T48	1		T91	1		T148	1
auto[2415919104:2550136831]	auto[1]	51	1			T20	1		T30	1		T195	1
auto[2550136832:2684354559]	auto[0]	47	1			T124	1		T257	1		T200	1
auto[2550136832:2684354559]	auto[1]	57	1			T5	2		T7	2		T56	3
auto[2684354560:2818572287]	auto[0]	47	1			T16	1		T23	1		T7	1
auto[2684354560:2818572287]	auto[1]	56	1			T135	1		T87	1		T48	1
auto[2818572288:2952790015]	auto[0]	53	1			T18	1		T43	1		T87	1
auto[2818572288:2952790015]	auto[1]	46	1			T47	1		T48	1		T56	1
auto[2952790016:3087007743]	auto[0]	41	1			T16	3		T18	1		T43	1
auto[2952790016:3087007743]	auto[1]	52	1			T18	1		T30	1		T59	1
auto[3087007744:3221225471]	auto[0]	36	1			T16	1		T18	1		T7	2
auto[3087007744:3221225471]	auto[1]	41	1			T182	1		T185	1		T48	1
auto[3221225472:3355443199]	auto[0]	40	1			T43	2		T39	1		T45	1
auto[3221225472:3355443199]	auto[1]	41	1			T181	1		T183	1		T60	3
auto[3355443200:3489660927]	auto[0]	42	1			T7	1		T39	1		T24	1
auto[3355443200:3489660927]	auto[1]	57	1			T7	1		T47	1		T57	1
auto[3489660928:3623878655]	auto[0]	54	1			T42	1		T20	1		T6	1
auto[3489660928:3623878655]	auto[1]	51	1			T16	1		T120	1		T180	1
auto[3623878656:3758096383]	auto[0]	59	1			T20	1		T22	1		T6	1
auto[3623878656:3758096383]	auto[1]	60	1			T21	1		T7	1		T48	3
auto[3758096384:3892314111]	auto[0]	54	1			T133	1		T56	2		T98	1
auto[3758096384:3892314111]	auto[1]	50	1			T5	1		T42	1		T30	1
auto[3892314112:4026531839]	auto[0]	53	1			T22	1		T7	1		T48	1
auto[3892314112:4026531839]	auto[1]	43	1			T131	1		T48	1		T196	1
auto[4026531840:4160749567]	auto[0]	38	1			T5	1		T87	1		T48	1
auto[4026531840:4160749567]	auto[1]	55	1			T102	1		T183	1		T48	1
auto[4160749568:4294967295]	auto[0]	54	1			T20	1		T6	1		T23	1
auto[4160749568:4294967295]	auto[1]	55	1			T25	2		T46	1		T7	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1514

1

T5

2

T16

10

T18

4

auto[1]

1633

1

T3

1

T5

4

T16

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T3	1		T20	1		T43	1
auto[134217728:268435455]	91	1			T5	1		T30	1		T6	1
auto[268435456:402653183]	99	1			T5	1		T45	1		T185	1
auto[402653184:536870911]	102	1			T16	1		T22	1		T7	1
auto[536870912:671088639]	108	1			T20	2		T8	2		T24	1
auto[671088640:805306367]	94	1			T25	1		T124	1		T48	2
auto[805306368:939524095]	112	1			T42	1		T7	2		T86	1
auto[939524096:1073741823]	112	1			T16	2		T39	1		T24	1
auto[1073741824:1207959551]	111	1			T5	1		T16	1		T18	1
auto[1207959552:1342177279]	88	1			T21	1		T7	1		T181	1
auto[1342177280:1476395007]	120	1			T16	2		T43	1		T41	1
auto[1476395008:1610612735]	92	1			T5	1		T43	1		T25	1
auto[1610612736:1744830463]	72	1			T135	1		T114	1		T180	1
auto[1744830464:1879048191]	94	1			T16	1		T7	1		T47	1
auto[1879048192:2013265919]	97	1			T43	1		T133	1		T6	2
auto[2013265920:2147483647]	108	1			T7	4		T87	1		T24	1
auto[2147483648:2281701375]	109	1			T131	1		T23	1		T7	1
auto[2281701376:2415919103]	88	1			T18	1		T133	1		T183	1
auto[2415919104:2550136831]	97	1			T42	1		T43	1		T22	1
auto[2550136832:2684354559]	98	1			T21	1		T7	3		T181	1
auto[2684354560:2818572287]	97	1			T18	1		T43	1		T7	1
auto[2818572288:2952790015]	95	1			T20	1		T30	1		T22	1
auto[2952790016:3087007743]	87	1			T5	1		T22	2		T131	1
auto[3087007744:3221225471]	90	1			T133	1		T7	1		T47	1
auto[3221225472:3355443199]	84	1			T43	1		T120	2		T6	1
auto[3355443200:3489660927]	99	1			T16	2		T20	1		T41	1
auto[3489660928:3623878655]	103	1			T16	1		T42	1		T7	1
auto[3623878656:3758096383]	116	1			T5	1		T24	1		T183	1
auto[3758096384:3892314111]	107	1			T18	1		T42	1		T20	1
auto[3892314112:4026531839]	99	1			T43	1		T25	1		T30	1
auto[4026531840:4160749567]	90	1			T18	1		T23	1		T7	2
auto[4160749568:4294967295]	89	1			T16	1		T42	1		T21	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T43	1		T46	1		T87	1
auto[0:134217727]	auto[1]	46	1			T3	1		T20	1		T296	1
auto[134217728:268435455]	auto[0]	45	1			T5	1		T6	1		T7	1
auto[134217728:268435455]	auto[1]	46	1			T30	1		T60	2		T230	1
auto[268435456:402653183]	auto[0]	50	1			T5	1		T45	1		T90	1
auto[268435456:402653183]	auto[1]	49	1			T185	1		T60	2		T247	1
auto[402653184:536870911]	auto[0]	51	1			T16	1		T22	1		T39	1
auto[402653184:536870911]	auto[1]	51	1			T7	1		T124	1		T184	1
auto[536870912:671088639]	auto[0]	49	1			T20	1		T8	2		T24	1
auto[536870912:671088639]	auto[1]	59	1			T20	1		T115	1		T184	1
auto[671088640:805306367]	auto[0]	53	1			T25	1		T91	1		T67	1
auto[671088640:805306367]	auto[1]	41	1			T124	1		T48	2		T306	1
auto[805306368:939524095]	auto[0]	51	1			T42	1		T7	1		T86	1
auto[805306368:939524095]	auto[1]	61	1			T7	1		T124	1		T148	1
auto[939524096:1073741823]	auto[0]	63	1			T16	2		T39	1		T24	1
auto[939524096:1073741823]	auto[1]	49	1			T183	1		T48	1		T56	1
auto[1073741824:1207959551]	auto[0]	45	1			T16	1		T18	1		T48	2
auto[1073741824:1207959551]	auto[1]	66	1			T5	1		T7	1		T124	2
auto[1207959552:1342177279]	auto[0]	40	1			T183	1		T60	1		T230	1
auto[1207959552:1342177279]	auto[1]	48	1			T21	1		T7	1		T181	1
auto[1342177280:1476395007]	auto[0]	58	1			T16	2		T43	1		T41	1
auto[1342177280:1476395007]	auto[1]	62	1			T7	1		T124	1		T59	1
auto[1476395008:1610612735]	auto[0]	46	1			T43	1		T25	1		T7	1
auto[1476395008:1610612735]	auto[1]	46	1			T5	1		T7	1		T124	1
auto[1610612736:1744830463]	auto[0]	24	1			T269	1		T71	2		T413	1
auto[1610612736:1744830463]	auto[1]	48	1			T135	1		T114	1		T180	1
auto[1744830464:1879048191]	auto[0]	46	1			T16	1		T7	1		T39	1
auto[1744830464:1879048191]	auto[1]	48	1			T47	1		T195	1		T57	1
auto[1879048192:2013265919]	auto[0]	49	1			T43	1		T133	1		T6	2
auto[1879048192:2013265919]	auto[1]	48	1			T135	1		T60	2		T236	1
auto[2013265920:2147483647]	auto[0]	54	1			T7	2		T87	1		T24	1
auto[2013265920:2147483647]	auto[1]	54	1			T7	2		T300	1		T98	1
auto[2147483648:2281701375]	auto[0]	54	1			T7	1		T87	1		T48	1
auto[2147483648:2281701375]	auto[1]	55	1			T131	1		T23	1		T91	1
auto[2281701376:2415919103]	auto[0]	48	1			T18	1		T183	1		T91	1
auto[2281701376:2415919103]	auto[1]	40	1			T133	1		T48	1		T60	1
auto[2415919104:2550136831]	auto[0]	54	1			T43	1		T22	1		T7	2
auto[2415919104:2550136831]	auto[1]	43	1			T42	1		T7	1		T48	1
auto[2550136832:2684354559]	auto[0]	50	1			T21	1		T7	3		T90	1
auto[2550136832:2684354559]	auto[1]	48	1			T181	1		T48	2		T60	1
auto[2684354560:2818572287]	auto[0]	34	1			T7	1		T182	1		T124	1
auto[2684354560:2818572287]	auto[1]	63	1			T18	1		T43	1		T180	1
auto[2818572288:2952790015]	auto[0]	46	1			T20	1		T22	1		T8	1
auto[2818572288:2952790015]	auto[1]	49	1			T30	1		T6	1		T7	1
auto[2952790016:3087007743]	auto[0]	39	1			T22	2		T131	1		T87	1
auto[2952790016:3087007743]	auto[1]	48	1			T5	1		T60	1		T56	2
auto[3087007744:3221225471]	auto[0]	40	1			T133	1		T124	1		T306	1
auto[3087007744:3221225471]	auto[1]	50	1			T7	1		T47	1		T48	1
auto[3221225472:3355443199]	auto[0]	42	1			T43	1		T6	1		T124	1
auto[3221225472:3355443199]	auto[1]	42	1			T120	2		T46	1		T181	1
auto[3355443200:3489660927]	auto[0]	46	1			T16	1		T20	1		T22	1
auto[3355443200:3489660927]	auto[1]	53	1			T16	1		T41	1		T21	1
auto[3489660928:3623878655]	auto[0]	48	1			T16	1		T42	1		T7	1
auto[3489660928:3623878655]	auto[1]	55	1			T26	1		T185	1		T60	1
auto[3623878656:3758096383]	auto[0]	50	1			T24	1		T183	1		T48	2
auto[3623878656:3758096383]	auto[1]	66	1			T5	1		T48	2		T60	2
auto[3758096384:3892314111]	auto[0]	45	1			T18	1		T42	1		T20	1
auto[3758096384:3892314111]	auto[1]	62	1			T133	1		T86	1		T182	1
auto[3892314112:4026531839]	auto[0]	52	1			T43	1		T25	1		T120	1
auto[3892314112:4026531839]	auto[1]	47	1			T30	1		T102	1		T7	1
auto[4026531840:4160749567]	auto[0]	46	1			T18	1		T23	1		T7	2
auto[4026531840:4160749567]	auto[1]	44	1			T180	1		T196	1		T60	1
auto[4160749568:4294967295]	auto[0]	43	1			T16	1		T114	1		T48	1
auto[4160749568:4294967295]	auto[1]	46	1			T42	1		T21	1		T7	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1503

1

T5

1

T16

10

T18

4

auto[1]

1647

1

T3

1

T5

5

T16

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	88	1			T5	1		T22	1		T7	1
auto[134217728:268435455]	98	1			T16	1		T131	1		T7	1
auto[268435456:402653183]	106	1			T5	1		T120	1		T7	1
auto[402653184:536870911]	105	1			T16	2		T43	1		T7	1
auto[536870912:671088639]	124	1			T20	1		T25	1		T30	1
auto[671088640:805306367]	101	1			T5	1		T43	3		T41	1
auto[805306368:939524095]	97	1			T5	1		T18	1		T22	1
auto[939524096:1073741823]	102	1			T18	1		T7	1		T86	1
auto[1073741824:1207959551]	87	1			T42	1		T133	1		T6	1
auto[1207959552:1342177279]	94	1			T18	1		T42	1		T25	1
auto[1342177280:1476395007]	107	1			T16	1		T20	1		T7	1
auto[1476395008:1610612735]	107	1			T182	1		T91	1		T257	1
auto[1610612736:1744830463]	105	1			T16	1		T7	1		T87	1
auto[1744830464:1879048191]	104	1			T25	1		T22	1		T133	1
auto[1879048192:2013265919]	101	1			T42	1		T7	2		T124	1
auto[2013265920:2147483647]	88	1			T5	1		T16	1		T20	1
auto[2147483648:2281701375]	82	1			T120	1		T6	1		T45	1
auto[2281701376:2415919103]	72	1			T16	1		T18	1		T20	1
auto[2415919104:2550136831]	91	1			T42	1		T24	1		T183	1
auto[2550136832:2684354559]	102	1			T18	1		T21	2		T135	2
auto[2684354560:2818572287]	97	1			T43	1		T86	1		T114	1
auto[2818572288:2952790015]	103	1			T16	1		T20	1		T23	1
auto[2952790016:3087007743]	92	1			T41	1		T22	1		T6	1
auto[3087007744:3221225471]	96	1			T16	1		T43	1		T7	1
auto[3221225472:3355443199]	106	1			T5	1		T42	1		T120	1
auto[3355443200:3489660927]	94	1			T6	1		T181	1		T48	1
auto[3489660928:3623878655]	84	1			T43	1		T7	1		T87	1
auto[3623878656:3758096383]	107	1			T16	1		T30	1		T21	1
auto[3758096384:3892314111]	94	1			T120	1		T45	1		T124	1
auto[3892314112:4026531839]	104	1			T16	1		T20	1		T43	1
auto[4026531840:4160749567]	97	1			T30	1		T7	1		T195	1
auto[4160749568:4294967295]	115	1			T3	1		T133	1		T23	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T5	1		T22	1		T7	1
auto[0:134217727]	auto[1]	43	1			T124	1		T148	1		T60	1
auto[134217728:268435455]	auto[0]	45	1			T16	1		T7	1		T124	1
auto[134217728:268435455]	auto[1]	53	1			T131	1		T26	1		T185	1
auto[268435456:402653183]	auto[0]	53	1			T114	1		T90	1		T67	1
auto[268435456:402653183]	auto[1]	53	1			T5	1		T120	1		T7	1
auto[402653184:536870911]	auto[0]	43	1			T16	2		T43	1		T87	1
auto[402653184:536870911]	auto[1]	62	1			T7	1		T47	1		T195	1
auto[536870912:671088639]	auto[0]	50	1			T20	1		T25	1		T7	1
auto[536870912:671088639]	auto[1]	74	1			T30	1		T133	1		T7	1
auto[671088640:805306367]	auto[0]	46	1			T43	3		T41	1		T39	1
auto[671088640:805306367]	auto[1]	55	1			T5	1		T48	1		T96	1
auto[805306368:939524095]	auto[0]	44	1			T22	1		T7	1		T182	1
auto[805306368:939524095]	auto[1]	53	1			T5	1		T18	1		T7	2
auto[939524096:1073741823]	auto[0]	55	1			T18	1		T86	1		T90	1
auto[939524096:1073741823]	auto[1]	47	1			T7	1		T114	1		T60	2
auto[1073741824:1207959551]	auto[0]	44	1			T42	1		T195	1		T114	1
auto[1073741824:1207959551]	auto[1]	43	1			T133	1		T6	1		T60	2
auto[1207959552:1342177279]	auto[0]	45	1			T18	1		T42	1		T6	1
auto[1207959552:1342177279]	auto[1]	49	1			T25	1		T21	1		T23	1
auto[1342177280:1476395007]	auto[0]	48	1			T16	1		T20	1		T90	1
auto[1342177280:1476395007]	auto[1]	59	1			T7	1		T115	1		T184	1
auto[1476395008:1610612735]	auto[0]	54	1			T182	1		T91	1		T257	1
auto[1476395008:1610612735]	auto[1]	53	1			T314	1		T70	1		T65	1
auto[1610612736:1744830463]	auto[0]	46	1			T16	1		T7	1		T87	1
auto[1610612736:1744830463]	auto[1]	59	1			T60	1		T96	1		T56	1
auto[1744830464:1879048191]	auto[0]	55	1			T25	1		T22	1		T133	1
auto[1744830464:1879048191]	auto[1]	49	1			T7	1		T86	1		T47	1
auto[1879048192:2013265919]	auto[0]	47	1			T42	1		T7	1		T124	1
auto[1879048192:2013265919]	auto[1]	54	1			T7	1		T48	3		T60	2
auto[2013265920:2147483647]	auto[0]	50	1			T16	1		T20	1		T22	3
auto[2013265920:2147483647]	auto[1]	38	1			T5	1		T7	1		T251	2
auto[2147483648:2281701375]	auto[0]	45	1			T6	1		T236	1		T70	1
auto[2147483648:2281701375]	auto[1]	37	1			T120	1		T45	1		T56	1
auto[2281701376:2415919103]	auto[0]	33	1			T16	1		T18	1		T64	1
auto[2281701376:2415919103]	auto[1]	39	1			T20	1		T131	1		T48	1
auto[2415919104:2550136831]	auto[0]	39	1			T24	1		T48	1		T196	1
auto[2415919104:2550136831]	auto[1]	52	1			T42	1		T183	1		T184	1
auto[2550136832:2684354559]	auto[0]	48	1			T18	1		T21	1		T7	1
auto[2550136832:2684354559]	auto[1]	54	1			T21	1		T135	2		T7	1
auto[2684354560:2818572287]	auto[0]	43	1			T43	1		T86	1		T182	1
auto[2684354560:2818572287]	auto[1]	54	1			T114	1		T181	1		T48	1
auto[2818572288:2952790015]	auto[0]	46	1			T16	1		T23	1		T124	1
auto[2818572288:2952790015]	auto[1]	57	1			T20	1		T46	1		T7	2
auto[2952790016:3087007743]	auto[0]	46	1			T41	1		T22	1		T6	1
auto[2952790016:3087007743]	auto[1]	46	1			T48	2		T148	1		T232	1
auto[3087007744:3221225471]	auto[0]	45	1			T16	1		T43	1		T8	1
auto[3087007744:3221225471]	auto[1]	51	1			T7	1		T47	1		T181	1
auto[3221225472:3355443199]	auto[0]	53	1			T42	1		T39	1		T90	1
auto[3221225472:3355443199]	auto[1]	53	1			T5	1		T120	1		T7	1
auto[3355443200:3489660927]	auto[0]	52	1			T6	1		T48	1		T67	1
auto[3355443200:3489660927]	auto[1]	42	1			T181	1		T75	1		T70	1
auto[3489660928:3623878655]	auto[0]	40	1			T43	1		T7	1		T87	1
auto[3489660928:3623878655]	auto[1]	44	1			T180	1		T124	1		T56	1
auto[3623878656:3758096383]	auto[0]	48	1			T183	1		T67	1		T44	1
auto[3623878656:3758096383]	auto[1]	59	1			T16	1		T30	1		T21	1
auto[3758096384:3892314111]	auto[0]	49	1			T120	1		T45	1		T48	1
auto[3758096384:3892314111]	auto[1]	45	1			T124	1		T48	2		T59	1
auto[3892314112:4026531839]	auto[0]	46	1			T16	1		T20	1		T43	1
auto[3892314112:4026531839]	auto[1]	58	1			T7	1		T48	3		T91	1
auto[4026531840:4160749567]	auto[0]	40	1			T7	1		T148	1		T44	1
auto[4026531840:4160749567]	auto[1]	57	1			T30	1		T195	1		T48	1
auto[4160749568:4294967295]	auto[0]	60	1			T23	1		T7	2		T39	1
auto[4160749568:4294967295]	auto[1]	55	1			T3	1		T133	1		T115	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1507

1

T5

1

T16

10

T18

5

auto[1]

1639

1

T3

1

T5

5

T16

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	82	1			T42	1		T120	1		T22	1
auto[134217728:268435455]	101	1			T5	1		T16	1		T43	1
auto[268435456:402653183]	122	1			T42	1		T20	1		T45	1
auto[402653184:536870911]	101	1			T21	2		T23	1		T7	1
auto[536870912:671088639]	91	1			T7	1		T24	1		T183	1
auto[671088640:805306367]	99	1			T23	1		T182	1		T183	1
auto[805306368:939524095]	102	1			T3	1		T42	1		T21	1
auto[939524096:1073741823]	90	1			T25	1		T47	1		T24	1
auto[1073741824:1207959551]	107	1			T5	1		T42	1		T20	1
auto[1207959552:1342177279]	105	1			T22	2		T133	1		T6	1
auto[1342177280:1476395007]	91	1			T16	1		T6	1		T7	1
auto[1476395008:1610612735]	99	1			T43	1		T22	1		T67	1
auto[1610612736:1744830463]	80	1			T5	1		T16	1		T46	1
auto[1744830464:1879048191]	96	1			T30	1		T133	1		T6	2
auto[1879048192:2013265919]	98	1			T16	1		T22	1		T7	1
auto[2013265920:2147483647]	95	1			T5	1		T22	1		T133	1
auto[2147483648:2281701375]	102	1			T20	1		T6	1		T8	1
auto[2281701376:2415919103]	113	1			T5	1		T120	1		T131	1
auto[2415919104:2550136831]	90	1			T7	1		T91	1		T300	1
auto[2550136832:2684354559]	92	1			T43	1		T7	1		T195	1
auto[2684354560:2818572287]	106	1			T16	1		T43	1		T86	1
auto[2818572288:2952790015]	102	1			T18	1		T20	1		T41	1
auto[2952790016:3087007743]	96	1			T20	1		T43	1		T30	1
auto[3087007744:3221225471]	112	1			T18	2		T25	1		T21	1
auto[3221225472:3355443199]	106	1			T7	3		T48	2		T148	1
auto[3355443200:3489660927]	117	1			T16	2		T18	1		T20	1
auto[3489660928:3623878655]	97	1			T7	2		T87	1		T114	1
auto[3623878656:3758096383]	88	1			T5	1		T16	1		T25	1
auto[3758096384:3892314111]	79	1			T16	1		T135	1		T87	1
auto[3892314112:4026531839]	95	1			T7	1		T90	1		T48	1
auto[4026531840:4160749567]	89	1			T16	1		T18	1		T7	3
auto[4160749568:4294967295]	103	1			T16	1		T42	1		T120	1