dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2818 1 T3 1 T5 6 T16 11
auto[1] 278 1 T18 7 T120 5 T148 6


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 104 1 T16 2 T20 1 T30 1
auto[134217728:268435455] 100 1 T16 2 T30 1 T22 1
auto[268435456:402653183] 102 1 T16 1 T180 1 T182 1
auto[402653184:536870911] 109 1 T18 1 T120 1 T124 1
auto[536870912:671088639] 101 1 T5 1 T18 1 T20 1
auto[671088640:805306367] 86 1 T5 1 T18 1 T7 1
auto[805306368:939524095] 94 1 T18 2 T43 2 T120 1
auto[939524096:1073741823] 105 1 T3 1 T45 1 T90 1
auto[1073741824:1207959551] 93 1 T16 1 T21 1 T22 1
auto[1207959552:1342177279] 82 1 T16 1 T131 1 T7 1
auto[1342177280:1476395007] 98 1 T18 1 T22 1 T7 1
auto[1476395008:1610612735] 112 1 T41 1 T120 1 T24 1
auto[1610612736:1744830463] 89 1 T120 1 T133 2 T6 1
auto[1744830464:1879048191] 87 1 T20 1 T43 1 T120 1
auto[1879048192:2013265919] 94 1 T5 1 T42 1 T46 1
auto[2013265920:2147483647] 82 1 T5 1 T102 1 T6 1
auto[2147483648:2281701375] 100 1 T22 1 T133 1 T87 1
auto[2281701376:2415919103] 90 1 T21 1 T135 1 T7 1
auto[2415919104:2550136831] 97 1 T43 1 T22 2 T23 1
auto[2550136832:2684354559] 102 1 T25 1 T7 2 T47 1
auto[2684354560:2818572287] 101 1 T18 1 T42 1 T21 1
auto[2818572288:2952790015] 85 1 T18 2 T25 1 T131 1
auto[2952790016:3087007743] 88 1 T16 1 T18 1 T91 1
auto[3087007744:3221225471] 107 1 T16 1 T25 1 T7 2
auto[3221225472:3355443199] 115 1 T195 1 T180 1 T182 1
auto[3355443200:3489660927] 88 1 T5 1 T86 1 T185 1
auto[3489660928:3623878655] 97 1 T20 1 T120 1 T133 1
auto[3623878656:3758096383] 98 1 T16 1 T18 1 T20 1
auto[3758096384:3892314111] 105 1 T18 1 T7 2 T47 1
auto[3892314112:4026531839] 86 1 T5 1 T16 1 T41 1
auto[4026531840:4160749567] 94 1 T20 1 T48 1 T60 2
auto[4160749568:4294967295] 105 1 T120 1 T22 1 T46 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 92 1 T16 2 T20 1 T30 1
auto[0:134217727] auto[1] 12 1 T120 1 T222 1 T410 1
auto[134217728:268435455] auto[0] 95 1 T16 2 T30 1 T22 1
auto[134217728:268435455] auto[1] 5 1 T109 1 T408 1 T359 2
auto[268435456:402653183] auto[0] 93 1 T16 1 T180 1 T182 1
auto[268435456:402653183] auto[1] 9 1 T109 1 T301 1 T252 1
auto[402653184:536870911] auto[0] 97 1 T18 1 T120 1 T124 1
auto[402653184:536870911] auto[1] 12 1 T222 1 T237 1 T277 1
auto[536870912:671088639] auto[0] 92 1 T5 1 T20 1 T120 1
auto[536870912:671088639] auto[1] 9 1 T18 1 T222 1 T361 1
auto[671088640:805306367] auto[0] 77 1 T5 1 T7 1 T48 3
auto[671088640:805306367] auto[1] 9 1 T18 1 T229 1 T359 1
auto[805306368:939524095] auto[0] 84 1 T43 2 T135 1 T39 1
auto[805306368:939524095] auto[1] 10 1 T18 2 T120 1 T148 1
auto[939524096:1073741823] auto[0] 91 1 T3 1 T45 1 T90 1
auto[939524096:1073741823] auto[1] 14 1 T299 1 T237 1 T359 1
auto[1073741824:1207959551] auto[0] 87 1 T16 1 T21 1 T22 1
auto[1073741824:1207959551] auto[1] 6 1 T197 1 T277 1 T252 1
auto[1207959552:1342177279] auto[0] 79 1 T16 1 T131 1 T7 1
auto[1207959552:1342177279] auto[1] 3 1 T277 1 T357 1 T423 1
auto[1342177280:1476395007] auto[0] 91 1 T18 1 T22 1 T7 1
auto[1342177280:1476395007] auto[1] 7 1 T409 1 T424 1 T419 1
auto[1476395008:1610612735] auto[0] 106 1 T41 1 T120 1 T24 1
auto[1476395008:1610612735] auto[1] 6 1 T237 1 T408 1 T412 1
auto[1610612736:1744830463] auto[0] 82 1 T133 2 T6 1 T7 1
auto[1610612736:1744830463] auto[1] 7 1 T120 1 T222 1 T359 1
auto[1744830464:1879048191] auto[0] 71 1 T20 1 T43 1 T115 1
auto[1744830464:1879048191] auto[1] 16 1 T120 1 T148 1 T237 1
auto[1879048192:2013265919] auto[0] 83 1 T5 1 T42 1 T46 1
auto[1879048192:2013265919] auto[1] 11 1 T148 2 T245 1 T109 1
auto[2013265920:2147483647] auto[0] 77 1 T5 1 T102 1 T6 1
auto[2013265920:2147483647] auto[1] 5 1 T267 1 T421 1 T268 1
auto[2147483648:2281701375] auto[0] 91 1 T22 1 T133 1 T87 1
auto[2147483648:2281701375] auto[1] 9 1 T229 1 T408 1 T361 1
auto[2281701376:2415919103] auto[0] 81 1 T21 1 T135 1 T7 1
auto[2281701376:2415919103] auto[1] 9 1 T197 1 T299 1 T222 1
auto[2415919104:2550136831] auto[0] 88 1 T43 1 T22 2 T23 1
auto[2415919104:2550136831] auto[1] 9 1 T222 1 T111 1 T277 1
auto[2550136832:2684354559] auto[0] 94 1 T25 1 T7 2 T47 1
auto[2550136832:2684354559] auto[1] 8 1 T277 1 T361 1 T285 1
auto[2684354560:2818572287] auto[0] 87 1 T42 1 T21 1 T182 1
auto[2684354560:2818572287] auto[1] 14 1 T18 1 T148 1 T245 1
auto[2818572288:2952790015] auto[0] 78 1 T18 1 T25 1 T131 1
auto[2818572288:2952790015] auto[1] 7 1 T18 1 T410 1 T267 1
auto[2952790016:3087007743] auto[0] 80 1 T16 1 T91 1 T56 1
auto[2952790016:3087007743] auto[1] 8 1 T18 1 T148 1 T222 1
auto[3087007744:3221225471] auto[0] 102 1 T16 1 T25 1 T7 2
auto[3087007744:3221225471] auto[1] 5 1 T245 2 T109 1 T277 1
auto[3221225472:3355443199] auto[0] 103 1 T195 1 T180 1 T182 1
auto[3221225472:3355443199] auto[1] 12 1 T197 1 T222 2 T237 1
auto[3355443200:3489660927] auto[0] 76 1 T5 1 T86 1 T185 1
auto[3355443200:3489660927] auto[1] 12 1 T237 1 T301 2 T252 1
auto[3489660928:3623878655] auto[0] 90 1 T20 1 T133 1 T45 1
auto[3489660928:3623878655] auto[1] 7 1 T120 1 T410 1 T412 1
auto[3623878656:3758096383] auto[0] 89 1 T16 1 T18 1 T20 1
auto[3623878656:3758096383] auto[1] 9 1 T245 1 T109 1 T229 1
auto[3758096384:3892314111] auto[0] 103 1 T18 1 T7 2 T47 1
auto[3758096384:3892314111] auto[1] 2 1 T410 1 T366 1 - -
auto[3892314112:4026531839] auto[0] 80 1 T5 1 T16 1 T41 1
auto[3892314112:4026531839] auto[1] 6 1 T245 1 T410 1 T223 1
auto[4026531840:4160749567] auto[0] 84 1 T20 1 T48 1 T60 2
auto[4026531840:4160749567] auto[1] 10 1 T197 1 T229 1 T410 1
auto[4160749568:4294967295] auto[0] 95 1 T120 1 T22 1 T46 1
auto[4160749568:4294967295] auto[1] 10 1 T197 1 T245 1 T229 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%