Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.85 99.10 97.99 98.74 100.00 99.11 98.41 91.58


Total test records in report: 1073
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T381 /workspace/coverage/default/13.keymgr_sw_invalid_input.3033093365 May 04 03:47:27 PM PDT 24 May 04 03:48:01 PM PDT 24 1311387683 ps
T1014 /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1763282676 May 04 03:48:58 PM PDT 24 May 04 03:49:00 PM PDT 24 41776497 ps
T1015 /workspace/coverage/default/42.keymgr_sync_async_fault_cross.4255577766 May 04 03:49:53 PM PDT 24 May 04 03:49:56 PM PDT 24 104879436 ps
T1016 /workspace/coverage/default/34.keymgr_sideload_otbn.822707874 May 04 03:49:17 PM PDT 24 May 04 03:49:22 PM PDT 24 502473902 ps
T1017 /workspace/coverage/default/25.keymgr_sideload_aes.2758206849 May 04 03:48:32 PM PDT 24 May 04 03:48:35 PM PDT 24 756307902 ps
T1018 /workspace/coverage/default/49.keymgr_sideload_protect.1083881759 May 04 03:50:21 PM PDT 24 May 04 03:50:24 PM PDT 24 56229758 ps
T1019 /workspace/coverage/default/20.keymgr_kmac_rsp_err.587515744 May 04 03:48:08 PM PDT 24 May 04 03:48:12 PM PDT 24 100141681 ps
T1020 /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2286108347 May 04 03:48:03 PM PDT 24 May 04 03:48:08 PM PDT 24 737809958 ps
T1021 /workspace/coverage/default/2.keymgr_smoke.2022192654 May 04 03:46:02 PM PDT 24 May 04 03:46:04 PM PDT 24 33998249 ps
T1022 /workspace/coverage/default/45.keymgr_alert_test.1050761996 May 04 03:50:03 PM PDT 24 May 04 03:50:04 PM PDT 24 13141673 ps
T369 /workspace/coverage/default/27.keymgr_kmac_rsp_err.825291770 May 04 03:48:40 PM PDT 24 May 04 03:48:45 PM PDT 24 54232401 ps
T334 /workspace/coverage/default/30.keymgr_kmac_rsp_err.1707097337 May 04 03:48:58 PM PDT 24 May 04 03:49:07 PM PDT 24 982354369 ps
T367 /workspace/coverage/default/8.keymgr_kmac_rsp_err.1900411737 May 04 03:46:58 PM PDT 24 May 04 03:47:04 PM PDT 24 329718899 ps
T1023 /workspace/coverage/default/14.keymgr_sw_invalid_input.3461142217 May 04 03:47:34 PM PDT 24 May 04 03:47:39 PM PDT 24 239467417 ps
T291 /workspace/coverage/default/5.keymgr_kmac_rsp_err.946165130 May 04 03:46:35 PM PDT 24 May 04 03:47:38 PM PDT 24 2910964035 ps
T1024 /workspace/coverage/default/9.keymgr_smoke.2413985892 May 04 03:47:00 PM PDT 24 May 04 03:47:03 PM PDT 24 350100598 ps
T350 /workspace/coverage/default/16.keymgr_kmac_rsp_err.1086785960 May 04 03:47:49 PM PDT 24 May 04 03:47:55 PM PDT 24 106288679 ps
T1025 /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2618531190 May 04 03:49:09 PM PDT 24 May 04 03:49:20 PM PDT 24 165698403 ps
T1026 /workspace/coverage/default/24.keymgr_sw_invalid_input.544325742 May 04 03:48:30 PM PDT 24 May 04 03:48:56 PM PDT 24 3693728730 ps
T1027 /workspace/coverage/default/10.keymgr_lc_disable.3748773873 May 04 03:47:05 PM PDT 24 May 04 03:47:09 PM PDT 24 184285869 ps
T1028 /workspace/coverage/default/26.keymgr_hwsw_invalid_input.4122965105 May 04 03:48:35 PM PDT 24 May 04 03:48:44 PM PDT 24 268351018 ps
T1029 /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1296486965 May 04 03:47:09 PM PDT 24 May 04 03:47:18 PM PDT 24 181162952 ps
T214 /workspace/coverage/default/46.keymgr_lc_disable.127712731 May 04 03:50:04 PM PDT 24 May 04 03:50:09 PM PDT 24 141293467 ps
T1030 /workspace/coverage/default/34.keymgr_lc_disable.3215338188 May 04 03:49:15 PM PDT 24 May 04 03:49:19 PM PDT 24 332400751 ps
T1031 /workspace/coverage/default/24.keymgr_sideload_protect.1544785155 May 04 03:48:30 PM PDT 24 May 04 03:48:44 PM PDT 24 422181720 ps
T1032 /workspace/coverage/default/20.keymgr_sideload_protect.3939908477 May 04 03:48:10 PM PDT 24 May 04 03:48:13 PM PDT 24 409277651 ps
T292 /workspace/coverage/default/3.keymgr_kmac_rsp_err.1846795920 May 04 03:46:19 PM PDT 24 May 04 03:46:22 PM PDT 24 813389238 ps
T1033 /workspace/coverage/default/40.keymgr_sideload_otbn.1641817535 May 04 03:49:40 PM PDT 24 May 04 03:49:44 PM PDT 24 359345584 ps
T274 /workspace/coverage/default/18.keymgr_stress_all.174571906 May 04 03:47:57 PM PDT 24 May 04 03:49:32 PM PDT 24 17537554169 ps
T1034 /workspace/coverage/default/41.keymgr_random.3888052711 May 04 03:49:47 PM PDT 24 May 04 03:49:54 PM PDT 24 1082263279 ps
T423 /workspace/coverage/default/35.keymgr_cfg_regwen.1484771554 May 04 03:49:23 PM PDT 24 May 04 03:49:31 PM PDT 24 1320363867 ps
T1035 /workspace/coverage/default/30.keymgr_random.4124663239 May 04 03:48:56 PM PDT 24 May 04 03:49:02 PM PDT 24 429835784 ps
T1036 /workspace/coverage/default/29.keymgr_random.3504542795 May 04 03:48:52 PM PDT 24 May 04 03:48:56 PM PDT 24 217252302 ps
T1037 /workspace/coverage/default/43.keymgr_alert_test.741081916 May 04 03:49:53 PM PDT 24 May 04 03:49:54 PM PDT 24 45537818 ps
T1038 /workspace/coverage/default/48.keymgr_stress_all.1482057759 May 04 03:50:17 PM PDT 24 May 04 03:50:22 PM PDT 24 173031319 ps
T1039 /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.3990925677 May 04 03:47:41 PM PDT 24 May 04 03:47:45 PM PDT 24 192771293 ps
T425 /workspace/coverage/default/44.keymgr_cfg_regwen.1241443067 May 04 03:50:04 PM PDT 24 May 04 03:50:09 PM PDT 24 197865574 ps
T1040 /workspace/coverage/default/7.keymgr_direct_to_disabled.2198591024 May 04 03:46:46 PM PDT 24 May 04 03:46:50 PM PDT 24 267577203 ps
T1041 /workspace/coverage/default/24.keymgr_sideload_otbn.2183669776 May 04 03:48:23 PM PDT 24 May 04 03:48:29 PM PDT 24 1088777437 ps
T1042 /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3844184964 May 04 03:46:41 PM PDT 24 May 04 03:46:48 PM PDT 24 510436958 ps
T1043 /workspace/coverage/default/46.keymgr_sideload_kmac.2438366734 May 04 03:50:11 PM PDT 24 May 04 03:50:15 PM PDT 24 228205082 ps
T1044 /workspace/coverage/default/23.keymgr_random.2921480682 May 04 03:48:21 PM PDT 24 May 04 03:48:24 PM PDT 24 45472309 ps
T1045 /workspace/coverage/default/3.keymgr_sideload_protect.317915173 May 04 03:46:21 PM PDT 24 May 04 03:46:47 PM PDT 24 2523300285 ps
T1046 /workspace/coverage/default/44.keymgr_sideload.4269330618 May 04 03:50:05 PM PDT 24 May 04 03:50:12 PM PDT 24 253722210 ps
T1047 /workspace/coverage/default/37.keymgr_sync_async_fault_cross.4001656769 May 04 03:49:35 PM PDT 24 May 04 03:49:38 PM PDT 24 33485332 ps
T1048 /workspace/coverage/default/19.keymgr_sw_invalid_input.1221756848 May 04 03:48:03 PM PDT 24 May 04 03:48:08 PM PDT 24 509772666 ps
T1049 /workspace/coverage/default/5.keymgr_sideload_aes.3179108053 May 04 03:46:30 PM PDT 24 May 04 03:46:35 PM PDT 24 160401753 ps
T1050 /workspace/coverage/default/40.keymgr_lc_disable.171280494 May 04 03:49:44 PM PDT 24 May 04 03:49:48 PM PDT 24 67657720 ps
T1051 /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1165069064 May 04 03:49:49 PM PDT 24 May 04 03:49:54 PM PDT 24 379959768 ps
T1052 /workspace/coverage/default/27.keymgr_sideload_otbn.3014808148 May 04 03:48:37 PM PDT 24 May 04 03:48:42 PM PDT 24 138764333 ps
T1053 /workspace/coverage/default/19.keymgr_random.265039453 May 04 03:48:02 PM PDT 24 May 04 03:48:06 PM PDT 24 383565566 ps
T1054 /workspace/coverage/default/41.keymgr_stress_all.1611534172 May 04 03:49:49 PM PDT 24 May 04 03:50:01 PM PDT 24 1739287025 ps
T1055 /workspace/coverage/default/24.keymgr_custom_cm.3201632222 May 04 03:48:29 PM PDT 24 May 04 03:48:50 PM PDT 24 3263986907 ps
T1056 /workspace/coverage/default/15.keymgr_random.501556006 May 04 03:47:39 PM PDT 24 May 04 03:48:06 PM PDT 24 848048404 ps
T1057 /workspace/coverage/default/46.keymgr_sideload.1875907975 May 04 03:50:10 PM PDT 24 May 04 03:50:15 PM PDT 24 146028051 ps
T1058 /workspace/coverage/default/15.keymgr_sync_async_fault_cross.756938128 May 04 03:47:40 PM PDT 24 May 04 03:47:43 PM PDT 24 267692492 ps
T1059 /workspace/coverage/default/1.keymgr_direct_to_disabled.4294029339 May 04 03:46:02 PM PDT 24 May 04 03:46:06 PM PDT 24 75848763 ps
T1060 /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3853307022 May 04 03:48:41 PM PDT 24 May 04 03:48:47 PM PDT 24 793689197 ps
T1061 /workspace/coverage/default/25.keymgr_sync_async_fault_cross.939489124 May 04 03:48:34 PM PDT 24 May 04 03:48:37 PM PDT 24 70478269 ps
T1062 /workspace/coverage/default/9.keymgr_stress_all.1932494404 May 04 03:47:08 PM PDT 24 May 04 03:49:00 PM PDT 24 16671079278 ps
T1063 /workspace/coverage/default/23.keymgr_sideload_aes.418947112 May 04 03:48:18 PM PDT 24 May 04 03:49:13 PM PDT 24 2174090773 ps
T250 /workspace/coverage/default/29.keymgr_cfg_regwen.1691902788 May 04 03:48:51 PM PDT 24 May 04 03:49:00 PM PDT 24 283071917 ps
T1064 /workspace/coverage/default/10.keymgr_sideload_kmac.4207542458 May 04 03:47:06 PM PDT 24 May 04 03:47:09 PM PDT 24 53828475 ps
T1065 /workspace/coverage/default/36.keymgr_cfg_regwen.3594549869 May 04 03:49:22 PM PDT 24 May 04 03:49:27 PM PDT 24 859850592 ps
T1066 /workspace/coverage/default/17.keymgr_sw_invalid_input.773121644 May 04 03:47:52 PM PDT 24 May 04 03:47:56 PM PDT 24 84232581 ps
T1067 /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3229604910 May 04 03:49:15 PM PDT 24 May 04 03:49:20 PM PDT 24 208055450 ps
T1068 /workspace/coverage/default/2.keymgr_sync_async_fault_cross.4071963950 May 04 03:46:13 PM PDT 24 May 04 03:46:16 PM PDT 24 55576425 ps
T166 /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2732207186 May 04 03:47:15 PM PDT 24 May 04 03:47:20 PM PDT 24 95701293 ps
T1069 /workspace/coverage/default/23.keymgr_lc_disable.2008808676 May 04 03:48:18 PM PDT 24 May 04 03:48:31 PM PDT 24 908560041 ps
T1070 /workspace/coverage/default/27.keymgr_random.3821429393 May 04 03:48:36 PM PDT 24 May 04 03:48:40 PM PDT 24 130986247 ps
T1071 /workspace/coverage/default/47.keymgr_sideload_otbn.1864677642 May 04 03:50:10 PM PDT 24 May 04 03:50:13 PM PDT 24 54918854 ps
T1072 /workspace/coverage/default/40.keymgr_sideload.1249614653 May 04 03:49:44 PM PDT 24 May 04 03:49:51 PM PDT 24 381772470 ps
T1073 /workspace/coverage/default/30.keymgr_sideload_kmac.3969527602 May 04 03:48:59 PM PDT 24 May 04 03:49:03 PM PDT 24 162661574 ps

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3394711428
Short name T16
Test name
Test status
Simulation time 625356587 ps
CPU time 9.42 seconds
Started May 04 03:48:57 PM PDT 24
Finished May 04 03:49:07 PM PDT 24
Peak memory 214504 kb
Host smart-55b79a5c-58ef-4c87-b6a9-0cae25095294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394711428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3394711428
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2230619569
Short name T48
Test name
Test status
Simulation time 1123157288 ps
CPU time 45.69 seconds
Started May 04 03:48:58 PM PDT 24
Finished May 04 03:49:44 PM PDT 24
Peak memory 221212 kb
Host smart-1734554c-2530-4294-8638-31be0bcc934f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230619569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2230619569
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.541170643
Short name T18
Test name
Test status
Simulation time 254682037 ps
CPU time 5.25 seconds
Started May 04 03:47:50 PM PDT 24
Finished May 04 03:47:56 PM PDT 24
Peak memory 215332 kb
Host smart-66b12ed7-099e-4369-9b29-312b6b9c2081
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541170643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.541170643
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2299761222
Short name T70
Test name
Test status
Simulation time 5431152214 ps
CPU time 53.41 seconds
Started May 04 03:46:59 PM PDT 24
Finished May 04 03:47:54 PM PDT 24
Peak memory 215512 kb
Host smart-521c5271-a6fe-48f5-8963-f6721b0bbc2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299761222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2299761222
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2469289631
Short name T13
Test name
Test status
Simulation time 948577239 ps
CPU time 13.11 seconds
Started May 04 03:46:23 PM PDT 24
Finished May 04 03:46:37 PM PDT 24
Peak memory 232012 kb
Host smart-8f72ec2b-dabc-4289-835a-e39223a794ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469289631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2469289631
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.537151722
Short name T115
Test name
Test status
Simulation time 186871168 ps
CPU time 6.05 seconds
Started May 04 03:47:08 PM PDT 24
Finished May 04 03:47:14 PM PDT 24
Peak memory 222524 kb
Host smart-41337629-9d82-49d9-a823-cf499a2e3c5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537151722 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.537151722
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1906582131
Short name T60
Test name
Test status
Simulation time 7838267885 ps
CPU time 41.08 seconds
Started May 04 03:47:16 PM PDT 24
Finished May 04 03:47:58 PM PDT 24
Peak memory 222472 kb
Host smart-9e4281a2-b9c5-49a8-bef9-e35fc1e58650
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906582131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1906582131
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2923916585
Short name T28
Test name
Test status
Simulation time 57656596 ps
CPU time 3.38 seconds
Started May 04 03:47:57 PM PDT 24
Finished May 04 03:48:01 PM PDT 24
Peak memory 221784 kb
Host smart-531751e3-ae7d-4a4d-9311-2252021f654d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923916585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2923916585
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.674155902
Short name T116
Test name
Test status
Simulation time 247926978 ps
CPU time 11.51 seconds
Started May 04 03:35:01 PM PDT 24
Finished May 04 03:35:13 PM PDT 24
Peak memory 213976 kb
Host smart-75aadc98-0ed2-400d-8ff5-8636d1b0afce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674155902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.674155902
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3755111569
Short name T51
Test name
Test status
Simulation time 648895318 ps
CPU time 2.44 seconds
Started May 04 03:50:14 PM PDT 24
Finished May 04 03:50:17 PM PDT 24
Peak memory 209824 kb
Host smart-3a8d48e1-090b-44b4-bfc3-9754f2d5e88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755111569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3755111569
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3130049987
Short name T42
Test name
Test status
Simulation time 40051463 ps
CPU time 2.52 seconds
Started May 04 03:50:21 PM PDT 24
Finished May 04 03:50:24 PM PDT 24
Peak memory 206176 kb
Host smart-27731396-493d-43b0-bf32-d10992966119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130049987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3130049987
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2089662707
Short name T222
Test name
Test status
Simulation time 273988016 ps
CPU time 7.72 seconds
Started May 04 03:50:09 PM PDT 24
Finished May 04 03:50:17 PM PDT 24
Peak memory 214244 kb
Host smart-a07b122c-3180-4ce0-a7ba-3eb8ac1d5d8c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2089662707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2089662707
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3723640963
Short name T7
Test name
Test status
Simulation time 20052258100 ps
CPU time 119.98 seconds
Started May 04 03:49:20 PM PDT 24
Finished May 04 03:51:21 PM PDT 24
Peak memory 216544 kb
Host smart-a582648b-0aa5-494c-83f3-23e610ce44c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723640963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3723640963
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.323978963
Short name T24
Test name
Test status
Simulation time 104161494 ps
CPU time 4.43 seconds
Started May 04 03:46:59 PM PDT 24
Finished May 04 03:47:04 PM PDT 24
Peak memory 219820 kb
Host smart-5a03c5a2-3f0b-418c-b12f-0d2eaf2b5526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323978963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.323978963
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1325452177
Short name T411
Test name
Test status
Simulation time 825270503 ps
CPU time 13.39 seconds
Started May 04 03:47:27 PM PDT 24
Finished May 04 03:47:41 PM PDT 24
Peak memory 215736 kb
Host smart-472294af-dc34-4874-bddd-478e72398025
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1325452177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1325452177
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.773039906
Short name T124
Test name
Test status
Simulation time 281291590 ps
CPU time 12.05 seconds
Started May 04 03:49:36 PM PDT 24
Finished May 04 03:49:49 PM PDT 24
Peak memory 220228 kb
Host smart-ce2c8c79-4415-474e-88ac-1e576fda6bf2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773039906 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.773039906
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1691902788
Short name T250
Test name
Test status
Simulation time 283071917 ps
CPU time 8.3 seconds
Started May 04 03:48:51 PM PDT 24
Finished May 04 03:49:00 PM PDT 24
Peak memory 215504 kb
Host smart-2135dbd3-e515-49c9-9f55-d74a7c36107b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1691902788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1691902788
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.957438759
Short name T276
Test name
Test status
Simulation time 1005353918 ps
CPU time 28.15 seconds
Started May 04 03:49:46 PM PDT 24
Finished May 04 03:50:15 PM PDT 24
Peak memory 215332 kb
Host smart-dd2e47a5-d19b-4a27-a2c5-86ff30ed2281
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957438759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.957438759
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2681288844
Short name T408
Test name
Test status
Simulation time 198757771 ps
CPU time 5.92 seconds
Started May 04 03:48:34 PM PDT 24
Finished May 04 03:48:41 PM PDT 24
Peak memory 214304 kb
Host smart-655a2e79-e494-4461-8d05-90d96621a908
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2681288844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2681288844
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1950786062
Short name T71
Test name
Test status
Simulation time 1762880496 ps
CPU time 38.78 seconds
Started May 04 03:49:36 PM PDT 24
Finished May 04 03:50:15 PM PDT 24
Peak memory 222408 kb
Host smart-69a32f8d-ec2a-46af-b769-3715c88e02f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950786062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1950786062
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.4182387681
Short name T268
Test name
Test status
Simulation time 397044957 ps
CPU time 11.54 seconds
Started May 04 03:49:47 PM PDT 24
Finished May 04 03:50:00 PM PDT 24
Peak memory 215540 kb
Host smart-bf8d8b26-a72b-4a2b-854e-e22ac6e03980
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4182387681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.4182387681
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2416461699
Short name T219
Test name
Test status
Simulation time 472656484 ps
CPU time 12.12 seconds
Started May 04 03:48:37 PM PDT 24
Finished May 04 03:48:50 PM PDT 24
Peak memory 218436 kb
Host smart-4d093192-65d5-4fdd-9e60-4face7db6833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416461699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2416461699
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.4054520365
Short name T159
Test name
Test status
Simulation time 437923037 ps
CPU time 5.16 seconds
Started May 04 03:35:15 PM PDT 24
Finished May 04 03:35:22 PM PDT 24
Peak memory 213852 kb
Host smart-2988d791-90a7-4ff8-b679-8ba9b18a3a43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054520365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.4054520365
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.4275331119
Short name T277
Test name
Test status
Simulation time 1730729736 ps
CPU time 14.34 seconds
Started May 04 03:48:58 PM PDT 24
Finished May 04 03:49:13 PM PDT 24
Peak memory 214260 kb
Host smart-ff5bac2c-b652-41c3-922c-11843841661c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4275331119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.4275331119
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.781161151
Short name T21
Test name
Test status
Simulation time 2998385025 ps
CPU time 8.7 seconds
Started May 04 03:47:34 PM PDT 24
Finished May 04 03:47:43 PM PDT 24
Peak memory 214348 kb
Host smart-7be684b1-6f79-402b-8084-e8f69f2c281b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781161151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.781161151
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2273028194
Short name T76
Test name
Test status
Simulation time 8270464943 ps
CPU time 80.03 seconds
Started May 04 03:47:34 PM PDT 24
Finished May 04 03:48:54 PM PDT 24
Peak memory 215296 kb
Host smart-9d66cb2b-e777-4529-b35e-96cde59ce62c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273028194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2273028194
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2127174734
Short name T93
Test name
Test status
Simulation time 1454747288 ps
CPU time 8.11 seconds
Started May 04 03:49:42 PM PDT 24
Finished May 04 03:49:51 PM PDT 24
Peak memory 214312 kb
Host smart-376e8be5-2f00-4739-aba0-ef772b4e8ada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127174734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2127174734
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2289565314
Short name T30
Test name
Test status
Simulation time 113603826 ps
CPU time 3.58 seconds
Started May 04 03:47:42 PM PDT 24
Finished May 04 03:47:46 PM PDT 24
Peak memory 209956 kb
Host smart-701a3a53-d153-4bc3-8dc8-765d3c12d188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289565314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2289565314
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.4125379845
Short name T205
Test name
Test status
Simulation time 1611381430 ps
CPU time 51.41 seconds
Started May 04 03:50:06 PM PDT 24
Finished May 04 03:50:58 PM PDT 24
Peak memory 222428 kb
Host smart-6fab774d-9d01-4f17-9a0a-0f65ea5d2cc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125379845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.4125379845
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3709122669
Short name T121
Test name
Test status
Simulation time 491445560 ps
CPU time 4.59 seconds
Started May 04 03:34:57 PM PDT 24
Finished May 04 03:35:03 PM PDT 24
Peak memory 222168 kb
Host smart-f839e57a-3fba-41fd-97ad-5b8689f1e928
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709122669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3709122669
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1149787920
Short name T150
Test name
Test status
Simulation time 1560870845 ps
CPU time 10.2 seconds
Started May 04 03:49:47 PM PDT 24
Finished May 04 03:49:58 PM PDT 24
Peak memory 222760 kb
Host smart-b655c605-8118-4734-8d68-4e4dafa6f735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149787920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1149787920
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2534776866
Short name T273
Test name
Test status
Simulation time 13585165585 ps
CPU time 38.16 seconds
Started May 04 03:45:45 PM PDT 24
Finished May 04 03:46:23 PM PDT 24
Peak memory 222540 kb
Host smart-665eee50-0999-4670-afc6-01a88bf0d266
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2534776866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2534776866
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.811201032
Short name T296
Test name
Test status
Simulation time 199282343 ps
CPU time 7.54 seconds
Started May 04 03:49:30 PM PDT 24
Finished May 04 03:49:38 PM PDT 24
Peak memory 222436 kb
Host smart-fde762bb-cef6-4d9b-8fe2-bb6f111e4058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811201032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.811201032
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.332051411
Short name T66
Test name
Test status
Simulation time 269167832 ps
CPU time 3.38 seconds
Started May 04 03:47:32 PM PDT 24
Finished May 04 03:47:36 PM PDT 24
Peak memory 214628 kb
Host smart-cbd0629a-61fc-4754-ac51-2bf4326d0207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332051411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.332051411
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3572148851
Short name T120
Test name
Test status
Simulation time 878853065 ps
CPU time 45.48 seconds
Started May 04 03:46:29 PM PDT 24
Finished May 04 03:47:15 PM PDT 24
Peak memory 214876 kb
Host smart-87aee762-6179-4a5b-a143-bcc6d96038df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572148851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3572148851
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3830628003
Short name T68
Test name
Test status
Simulation time 539611024 ps
CPU time 28.41 seconds
Started May 04 03:50:13 PM PDT 24
Finished May 04 03:50:42 PM PDT 24
Peak memory 222332 kb
Host smart-fb97107e-343b-4722-821e-704b135c48c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830628003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3830628003
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3529276911
Short name T259
Test name
Test status
Simulation time 775798411 ps
CPU time 6.91 seconds
Started May 04 03:48:36 PM PDT 24
Finished May 04 03:48:44 PM PDT 24
Peak memory 210784 kb
Host smart-7aadb07e-6ef3-45b7-b186-28466e75f5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529276911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3529276911
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2618018441
Short name T419
Test name
Test status
Simulation time 710642446 ps
CPU time 35.83 seconds
Started May 04 03:49:15 PM PDT 24
Finished May 04 03:49:51 PM PDT 24
Peak memory 214316 kb
Host smart-b78f6530-e1b1-41bb-9275-dd8f9f3416a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2618018441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2618018441
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.1076140869
Short name T114
Test name
Test status
Simulation time 233685325 ps
CPU time 8.47 seconds
Started May 04 03:46:17 PM PDT 24
Finished May 04 03:46:26 PM PDT 24
Peak memory 222620 kb
Host smart-dcfc8b55-6240-4398-b103-d5e569565372
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076140869 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.1076140869
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3029575291
Short name T212
Test name
Test status
Simulation time 15888626069 ps
CPU time 104.98 seconds
Started May 04 03:47:40 PM PDT 24
Finished May 04 03:49:26 PM PDT 24
Peak memory 222628 kb
Host smart-9d5a83ff-8767-44ca-956c-fadfae34a237
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029575291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3029575291
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3126685932
Short name T427
Test name
Test status
Simulation time 10183249 ps
CPU time 0.87 seconds
Started May 04 03:48:25 PM PDT 24
Finished May 04 03:48:27 PM PDT 24
Peak memory 205656 kb
Host smart-3977890f-a67c-4c6f-b763-dc10c82f3749
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126685932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3126685932
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1418258167
Short name T311
Test name
Test status
Simulation time 54817129 ps
CPU time 4.08 seconds
Started May 04 03:48:42 PM PDT 24
Finished May 04 03:48:46 PM PDT 24
Peak memory 215320 kb
Host smart-72263520-9787-4088-abf0-7ec18259fc68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1418258167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1418258167
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1860021421
Short name T168
Test name
Test status
Simulation time 1510558938 ps
CPU time 33.67 seconds
Started May 04 03:35:17 PM PDT 24
Finished May 04 03:35:52 PM PDT 24
Peak memory 213964 kb
Host smart-dc43e080-6cc9-459e-b1ce-46f89f112e20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860021421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1860021421
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.4063597905
Short name T160
Test name
Test status
Simulation time 371434041 ps
CPU time 10.08 seconds
Started May 04 03:35:24 PM PDT 24
Finished May 04 03:35:35 PM PDT 24
Peak memory 213908 kb
Host smart-48f8ee8e-179e-4bd9-b18b-9d3aae9eaf22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063597905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.4063597905
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1819744439
Short name T154
Test name
Test status
Simulation time 3380244264 ps
CPU time 28.11 seconds
Started May 04 03:47:16 PM PDT 24
Finished May 04 03:47:44 PM PDT 24
Peak memory 214836 kb
Host smart-2c37bf7d-5445-44b0-aea1-adbdbcc130cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819744439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1819744439
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.4240997331
Short name T340
Test name
Test status
Simulation time 1806297101 ps
CPU time 51.65 seconds
Started May 04 03:46:01 PM PDT 24
Finished May 04 03:46:53 PM PDT 24
Peak memory 215892 kb
Host smart-0eb68f2e-90d8-497c-b886-b1a58d9b5892
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240997331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.4240997331
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3881670051
Short name T271
Test name
Test status
Simulation time 488175337 ps
CPU time 5.82 seconds
Started May 04 03:48:58 PM PDT 24
Finished May 04 03:49:04 PM PDT 24
Peak memory 209076 kb
Host smart-877b915c-ed71-4d75-961b-229d9337853e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881670051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3881670051
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3062964761
Short name T174
Test name
Test status
Simulation time 645571501 ps
CPU time 10.4 seconds
Started May 04 03:35:25 PM PDT 24
Finished May 04 03:35:36 PM PDT 24
Peak memory 209288 kb
Host smart-857158cb-4371-424c-802b-148bb0c079df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062964761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3062964761
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.884386991
Short name T153
Test name
Test status
Simulation time 140553668 ps
CPU time 5.33 seconds
Started May 04 03:49:20 PM PDT 24
Finished May 04 03:49:26 PM PDT 24
Peak memory 222664 kb
Host smart-5e53edd7-2705-4236-bf50-23994f7f8dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884386991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.884386991
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1859991133
Short name T73
Test name
Test status
Simulation time 126342013 ps
CPU time 3.32 seconds
Started May 04 03:49:32 PM PDT 24
Finished May 04 03:49:36 PM PDT 24
Peak memory 214648 kb
Host smart-6d86a2bb-492c-4c32-8117-78fc06c85bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859991133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1859991133
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3748921825
Short name T206
Test name
Test status
Simulation time 1104873066 ps
CPU time 43.75 seconds
Started May 04 03:47:11 PM PDT 24
Finished May 04 03:47:55 PM PDT 24
Peak memory 222448 kb
Host smart-5e409d4b-47df-4a53-8d99-814a5a58af33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748921825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3748921825
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.908172968
Short name T97
Test name
Test status
Simulation time 1819035858 ps
CPU time 21.85 seconds
Started May 04 03:48:21 PM PDT 24
Finished May 04 03:48:43 PM PDT 24
Peak memory 222448 kb
Host smart-9dfee61c-5587-4e4d-b644-34481e94781c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908172968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.908172968
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1933672025
Short name T293
Test name
Test status
Simulation time 773648872 ps
CPU time 30.59 seconds
Started May 04 03:50:07 PM PDT 24
Finished May 04 03:50:38 PM PDT 24
Peak memory 222428 kb
Host smart-2f201011-7c4f-48b9-8da3-046f0eedf843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933672025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1933672025
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1472086847
Short name T162
Test name
Test status
Simulation time 1549211938 ps
CPU time 12.3 seconds
Started May 04 03:34:45 PM PDT 24
Finished May 04 03:34:58 PM PDT 24
Peak memory 209052 kb
Host smart-1a25ff47-ad88-461a-a40d-601905ae08b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472086847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1472086847
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.2900711093
Short name T167
Test name
Test status
Simulation time 1241168984 ps
CPU time 13.6 seconds
Started May 04 03:35:03 PM PDT 24
Finished May 04 03:35:17 PM PDT 24
Peak memory 209052 kb
Host smart-4ef3b4e5-f83b-4382-adc5-78374eec2659
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900711093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.2900711093
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1877940708
Short name T10
Test name
Test status
Simulation time 99429283 ps
CPU time 2.25 seconds
Started May 04 03:48:58 PM PDT 24
Finished May 04 03:49:01 PM PDT 24
Peak memory 209388 kb
Host smart-da8f1232-7155-4ecd-8935-02c7b597ae5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877940708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1877940708
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2373529279
Short name T149
Test name
Test status
Simulation time 705850849 ps
CPU time 22.82 seconds
Started May 04 03:48:24 PM PDT 24
Finished May 04 03:48:48 PM PDT 24
Peak memory 217844 kb
Host smart-5aec6714-5fdf-45db-94c2-8a8c28aa6ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373529279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2373529279
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3597901872
Short name T110
Test name
Test status
Simulation time 3471454316 ps
CPU time 50.03 seconds
Started May 04 03:50:09 PM PDT 24
Finished May 04 03:51:00 PM PDT 24
Peak memory 223796 kb
Host smart-7fe51747-83fd-4c13-a5c2-36db538865fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597901872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3597901872
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1797595338
Short name T152
Test name
Test status
Simulation time 233863098 ps
CPU time 7.33 seconds
Started May 04 03:46:54 PM PDT 24
Finished May 04 03:47:01 PM PDT 24
Peak memory 222792 kb
Host smart-22bd17d2-187c-40b6-8a84-e84b2e06dd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797595338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1797595338
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3412679515
Short name T57
Test name
Test status
Simulation time 118622494 ps
CPU time 5.13 seconds
Started May 04 03:49:42 PM PDT 24
Finished May 04 03:49:48 PM PDT 24
Peak memory 217624 kb
Host smart-70763f13-99b1-446b-b31d-e35578b890fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412679515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3412679515
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.855954382
Short name T151
Test name
Test status
Simulation time 187798838 ps
CPU time 5.48 seconds
Started May 04 03:50:05 PM PDT 24
Finished May 04 03:50:11 PM PDT 24
Peak memory 218296 kb
Host smart-c3c7248c-1643-45b5-aeaf-ea961f773bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855954382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.855954382
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2531683898
Short name T25
Test name
Test status
Simulation time 472820010 ps
CPU time 12.55 seconds
Started May 04 03:49:53 PM PDT 24
Finished May 04 03:50:06 PM PDT 24
Peak memory 208176 kb
Host smart-436a8c09-e896-45f8-9c88-e8cfc004ca8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531683898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2531683898
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2508322328
Short name T224
Test name
Test status
Simulation time 533688020 ps
CPU time 7.99 seconds
Started May 04 03:46:13 PM PDT 24
Finished May 04 03:46:21 PM PDT 24
Peak memory 222472 kb
Host smart-4d6fdb4b-1c7f-40e2-9d65-b9e5ba25dd2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2508322328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2508322328
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1222577157
Short name T384
Test name
Test status
Simulation time 42328492 ps
CPU time 2.94 seconds
Started May 04 03:50:02 PM PDT 24
Finished May 04 03:50:05 PM PDT 24
Peak memory 208976 kb
Host smart-cd80c677-ab87-451e-a9bd-4f2090fa566f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222577157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1222577157
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.946165130
Short name T291
Test name
Test status
Simulation time 2910964035 ps
CPU time 62.32 seconds
Started May 04 03:46:35 PM PDT 24
Finished May 04 03:47:38 PM PDT 24
Peak memory 225080 kb
Host smart-fec314ca-c474-4823-9e09-28f9b7cabf4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946165130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.946165130
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1117867287
Short name T64
Test name
Test status
Simulation time 173804057 ps
CPU time 5.78 seconds
Started May 04 03:46:01 PM PDT 24
Finished May 04 03:46:07 PM PDT 24
Peak memory 209468 kb
Host smart-df7a5f2f-1234-4308-bbcf-794277a04549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117867287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1117867287
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.4228910572
Short name T96
Test name
Test status
Simulation time 89211179 ps
CPU time 4.44 seconds
Started May 04 03:47:04 PM PDT 24
Finished May 04 03:47:09 PM PDT 24
Peak memory 210348 kb
Host smart-e2d88bdc-4a3d-4031-adbe-4f3c7229e7cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228910572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.4228910572
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3248190785
Short name T255
Test name
Test status
Simulation time 428618098 ps
CPU time 9.45 seconds
Started May 04 03:47:21 PM PDT 24
Finished May 04 03:47:31 PM PDT 24
Peak memory 208576 kb
Host smart-e79b015c-ebe5-48f1-9259-dfa81e5ada76
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248190785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3248190785
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2540993602
Short name T363
Test name
Test status
Simulation time 1229774972 ps
CPU time 46.32 seconds
Started May 04 03:47:51 PM PDT 24
Finished May 04 03:48:38 PM PDT 24
Peak memory 220560 kb
Host smart-61a5d965-96b6-4a30-a1e3-bb0687c745c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540993602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2540993602
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.4024622622
Short name T690
Test name
Test status
Simulation time 651862451 ps
CPU time 7.73 seconds
Started May 04 03:48:24 PM PDT 24
Finished May 04 03:48:33 PM PDT 24
Peak memory 207824 kb
Host smart-578615f4-42b5-4a2f-b90f-9b4448a9502c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024622622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.4024622622
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2689114606
Short name T335
Test name
Test status
Simulation time 11309767134 ps
CPU time 94.05 seconds
Started May 04 03:49:46 PM PDT 24
Finished May 04 03:51:20 PM PDT 24
Peak memory 229180 kb
Host smart-eebb7a2e-09cd-494c-836d-9ed53c39b4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689114606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2689114606
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3506958358
Short name T266
Test name
Test status
Simulation time 1028329854 ps
CPU time 6.27 seconds
Started May 04 03:49:53 PM PDT 24
Finished May 04 03:50:00 PM PDT 24
Peak memory 222408 kb
Host smart-88861d7a-096d-40a4-938f-51032ff7bf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506958358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3506958358
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3526533619
Short name T366
Test name
Test status
Simulation time 166225068 ps
CPU time 9.27 seconds
Started May 04 03:50:13 PM PDT 24
Finished May 04 03:50:23 PM PDT 24
Peak memory 214928 kb
Host smart-5fcdf950-7b54-4886-834d-4ecd418fce9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3526533619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3526533619
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2796749890
Short name T252
Test name
Test status
Simulation time 338959015 ps
CPU time 4.78 seconds
Started May 04 03:46:52 PM PDT 24
Finished May 04 03:46:57 PM PDT 24
Peak memory 214304 kb
Host smart-a842cda9-722d-4d89-86aa-b440c6e5379f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2796749890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2796749890
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.4089466903
Short name T193
Test name
Test status
Simulation time 129653310 ps
CPU time 3.11 seconds
Started May 04 03:34:40 PM PDT 24
Finished May 04 03:34:44 PM PDT 24
Peak memory 213832 kb
Host smart-7dea3667-a104-4e1c-85f8-33eeacb4f64d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089466903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.4089466903
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1902510300
Short name T169
Test name
Test status
Simulation time 1344760249 ps
CPU time 16.28 seconds
Started May 04 03:35:10 PM PDT 24
Finished May 04 03:35:27 PM PDT 24
Peak memory 209316 kb
Host smart-9f53d596-a6c4-4a69-b920-21dc4181df4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902510300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1902510300
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1628207022
Short name T128
Test name
Test status
Simulation time 1004279784 ps
CPU time 10.33 seconds
Started May 04 03:34:56 PM PDT 24
Finished May 04 03:35:07 PM PDT 24
Peak memory 213884 kb
Host smart-2e276ebc-72ca-4fc1-bfc9-0453146af27d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628207022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1628207022
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.4109528210
Short name T163
Test name
Test status
Simulation time 126824707 ps
CPU time 6.61 seconds
Started May 04 03:35:03 PM PDT 24
Finished May 04 03:35:10 PM PDT 24
Peak memory 213816 kb
Host smart-27f7aa63-bd59-4acf-8ff8-a710ad5ccaa4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109528210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.4109528210
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2597617154
Short name T165
Test name
Test status
Simulation time 2695045345 ps
CPU time 10.67 seconds
Started May 04 03:35:05 PM PDT 24
Finished May 04 03:35:17 PM PDT 24
Peak memory 213904 kb
Host smart-5c5a20c3-686c-4e6e-9ab0-767f3f740b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597617154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2597617154
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.997877066
Short name T875
Test name
Test status
Simulation time 57120565 ps
CPU time 2.31 seconds
Started May 04 03:47:34 PM PDT 24
Finished May 04 03:47:37 PM PDT 24
Peak memory 210176 kb
Host smart-1f5fecd0-3141-41d9-a309-70467ca70e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997877066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.997877066
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3253290942
Short name T157
Test name
Test status
Simulation time 535792646 ps
CPU time 5.91 seconds
Started May 04 03:50:05 PM PDT 24
Finished May 04 03:50:12 PM PDT 24
Peak memory 222624 kb
Host smart-8b93217e-e88f-4cc6-aff1-cfdb5c7970c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253290942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3253290942
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2973177853
Short name T346
Test name
Test status
Simulation time 65206080 ps
CPU time 3.31 seconds
Started May 04 03:47:17 PM PDT 24
Finished May 04 03:47:21 PM PDT 24
Peak memory 206816 kb
Host smart-c97cb369-4c39-4b51-85c3-6629c4c36d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973177853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2973177853
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2717647239
Short name T994
Test name
Test status
Simulation time 352402773 ps
CPU time 4.29 seconds
Started May 04 03:47:34 PM PDT 24
Finished May 04 03:47:38 PM PDT 24
Peak memory 210848 kb
Host smart-ca384135-8113-4a82-8fce-fbb4f659775a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717647239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2717647239
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.420977720
Short name T893
Test name
Test status
Simulation time 753525340 ps
CPU time 5.84 seconds
Started May 04 03:47:47 PM PDT 24
Finished May 04 03:47:53 PM PDT 24
Peak memory 214284 kb
Host smart-62939eac-8b70-4430-8fec-3444cbf19990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420977720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.420977720
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1086785960
Short name T350
Test name
Test status
Simulation time 106288679 ps
CPU time 5.45 seconds
Started May 04 03:47:49 PM PDT 24
Finished May 04 03:47:55 PM PDT 24
Peak memory 222432 kb
Host smart-7c4c03ab-332f-4025-9be9-9453f523f3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086785960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1086785960
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3708819023
Short name T379
Test name
Test status
Simulation time 362271461 ps
CPU time 8.92 seconds
Started May 04 03:47:49 PM PDT 24
Finished May 04 03:47:59 PM PDT 24
Peak memory 210468 kb
Host smart-b9fa3e7b-83d2-487c-b7a4-4c7213225ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708819023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3708819023
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.431038217
Short name T375
Test name
Test status
Simulation time 575474745 ps
CPU time 10.71 seconds
Started May 04 03:47:49 PM PDT 24
Finished May 04 03:48:01 PM PDT 24
Peak memory 219400 kb
Host smart-823c54f9-4235-45e2-803f-380a0fe28405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431038217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.431038217
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2476654607
Short name T44
Test name
Test status
Simulation time 363404120 ps
CPU time 4.81 seconds
Started May 04 03:46:07 PM PDT 24
Finished May 04 03:46:12 PM PDT 24
Peak memory 222512 kb
Host smart-dc5979c4-8f1d-4fa7-b485-4bee40126c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476654607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2476654607
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.551667449
Short name T229
Test name
Test status
Simulation time 121779347 ps
CPU time 4.53 seconds
Started May 04 03:48:13 PM PDT 24
Finished May 04 03:48:18 PM PDT 24
Peak memory 215284 kb
Host smart-5bcc4f67-8e57-4fd4-a9cf-7789b413c136
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=551667449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.551667449
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.683417378
Short name T368
Test name
Test status
Simulation time 542554926 ps
CPU time 16.92 seconds
Started May 04 03:48:25 PM PDT 24
Finished May 04 03:48:43 PM PDT 24
Peak memory 222160 kb
Host smart-ba95a5fe-44cc-454a-8c4c-7f059a71231e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683417378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.683417378
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3502038965
Short name T342
Test name
Test status
Simulation time 390418282 ps
CPU time 6.05 seconds
Started May 04 03:49:02 PM PDT 24
Finished May 04 03:49:09 PM PDT 24
Peak memory 215068 kb
Host smart-4631552c-32ce-4a09-9fee-451c859df811
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3502038965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3502038965
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2780313371
Short name T209
Test name
Test status
Simulation time 6616235271 ps
CPU time 43.03 seconds
Started May 04 03:49:36 PM PDT 24
Finished May 04 03:50:20 PM PDT 24
Peak memory 215092 kb
Host smart-6b5a331b-042d-4b71-bc42-ec134b0eedcf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780313371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2780313371
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2875487805
Short name T332
Test name
Test status
Simulation time 312852576 ps
CPU time 12.54 seconds
Started May 04 03:46:18 PM PDT 24
Finished May 04 03:46:31 PM PDT 24
Peak memory 211420 kb
Host smart-f7f41ae8-48dd-4c79-a214-24e0eab5a59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875487805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2875487805
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.3527574344
Short name T213
Test name
Test status
Simulation time 164477939 ps
CPU time 9.65 seconds
Started May 04 03:49:49 PM PDT 24
Finished May 04 03:49:59 PM PDT 24
Peak memory 222696 kb
Host smart-2b92a949-1ad6-4742-9412-e89299b2d6a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527574344 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.3527574344
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.4181594096
Short name T155
Test name
Test status
Simulation time 332402871 ps
CPU time 6.38 seconds
Started May 04 03:46:23 PM PDT 24
Finished May 04 03:46:30 PM PDT 24
Peak memory 216912 kb
Host smart-41502f38-b594-48f3-90bf-cd2698ea86b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181594096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.4181594096
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2259501254
Short name T141
Test name
Test status
Simulation time 734045249 ps
CPU time 5.91 seconds
Started May 04 03:34:47 PM PDT 24
Finished May 04 03:34:53 PM PDT 24
Peak memory 205540 kb
Host smart-28a4d679-e6b1-4c67-bf78-bd4f77cd5fa1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259501254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
259501254
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3428245279
Short name T430
Test name
Test status
Simulation time 3622027779 ps
CPU time 8.42 seconds
Started May 04 03:34:45 PM PDT 24
Finished May 04 03:34:54 PM PDT 24
Peak memory 205560 kb
Host smart-6dbc511a-80a1-44c0-aca7-16a1287355a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428245279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
428245279
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1973167474
Short name T517
Test name
Test status
Simulation time 86006411 ps
CPU time 0.97 seconds
Started May 04 03:34:44 PM PDT 24
Finished May 04 03:34:46 PM PDT 24
Peak memory 205436 kb
Host smart-3a86de68-6543-438a-bd36-940eb88788a7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973167474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
973167474
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2085935431
Short name T436
Test name
Test status
Simulation time 61633663 ps
CPU time 1.09 seconds
Started May 04 03:34:47 PM PDT 24
Finished May 04 03:34:49 PM PDT 24
Peak memory 205688 kb
Host smart-e7ca20bb-b866-47a6-a108-171e6ca966ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085935431 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2085935431
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3074626919
Short name T515
Test name
Test status
Simulation time 15630888 ps
CPU time 0.75 seconds
Started May 04 03:34:39 PM PDT 24
Finished May 04 03:34:40 PM PDT 24
Peak memory 205404 kb
Host smart-dc3bae30-4013-4bf2-8d1f-e7a96e4c2ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074626919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3074626919
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2206404841
Short name T142
Test name
Test status
Simulation time 84987141 ps
CPU time 2.39 seconds
Started May 04 03:34:50 PM PDT 24
Finished May 04 03:34:53 PM PDT 24
Peak memory 213728 kb
Host smart-47aced77-379c-4e3f-b0bb-4744e34bd00f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206404841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2206404841
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3673514953
Short name T179
Test name
Test status
Simulation time 346834651 ps
CPU time 7.25 seconds
Started May 04 03:34:40 PM PDT 24
Finished May 04 03:34:48 PM PDT 24
Peak memory 222216 kb
Host smart-e98ae23a-192f-477a-9421-f2475cf2b46c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673514953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3673514953
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1523840799
Short name T440
Test name
Test status
Simulation time 485428105 ps
CPU time 11.04 seconds
Started May 04 03:34:40 PM PDT 24
Finished May 04 03:34:52 PM PDT 24
Peak memory 213972 kb
Host smart-69f2f546-04fe-4970-9cae-7949e0dca8a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523840799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1523840799
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1474328629
Short name T173
Test name
Test status
Simulation time 757197260 ps
CPU time 8.87 seconds
Started May 04 03:34:40 PM PDT 24
Finished May 04 03:34:49 PM PDT 24
Peak memory 208992 kb
Host smart-10461da8-7804-40c5-8ef4-8411766f8d09
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474328629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1474328629
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.776555480
Short name T537
Test name
Test status
Simulation time 1449676952 ps
CPU time 9.4 seconds
Started May 04 03:34:45 PM PDT 24
Finished May 04 03:34:55 PM PDT 24
Peak memory 205612 kb
Host smart-c6ee394c-31af-4f77-9369-7dfbbef27c69
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776555480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.776555480
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.2732957320
Short name T178
Test name
Test status
Simulation time 61862430 ps
CPU time 1.13 seconds
Started May 04 03:34:47 PM PDT 24
Finished May 04 03:34:49 PM PDT 24
Peak memory 205612 kb
Host smart-5733c1b8-616a-4b4a-afbf-f6033d35c0be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732957320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.2
732957320
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1813958227
Short name T432
Test name
Test status
Simulation time 88758113 ps
CPU time 1.31 seconds
Started May 04 03:34:56 PM PDT 24
Finished May 04 03:34:58 PM PDT 24
Peak memory 205644 kb
Host smart-65d61d2a-10da-4cec-8045-ab58dda397d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813958227 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1813958227
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2459064471
Short name T488
Test name
Test status
Simulation time 13846001 ps
CPU time 1.13 seconds
Started May 04 03:34:46 PM PDT 24
Finished May 04 03:34:47 PM PDT 24
Peak memory 205528 kb
Host smart-e030d01f-4f44-47ff-ba3d-29e8c25edd62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459064471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2459064471
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2720466245
Short name T523
Test name
Test status
Simulation time 26126418 ps
CPU time 0.7 seconds
Started May 04 03:34:45 PM PDT 24
Finished May 04 03:34:46 PM PDT 24
Peak memory 205400 kb
Host smart-02abdaf8-23f9-4c47-9f4b-5f0a7548acd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720466245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2720466245
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1829540826
Short name T484
Test name
Test status
Simulation time 221732257 ps
CPU time 4.94 seconds
Started May 04 03:34:47 PM PDT 24
Finished May 04 03:34:52 PM PDT 24
Peak memory 218720 kb
Host smart-4f3d5dc2-426a-4356-9acf-bdc4fdfb10be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829540826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1829540826
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.482281826
Short name T463
Test name
Test status
Simulation time 264248750 ps
CPU time 8.95 seconds
Started May 04 03:34:45 PM PDT 24
Finished May 04 03:34:54 PM PDT 24
Peak memory 213980 kb
Host smart-6cd2dc88-c66a-48d9-b814-14744f33f8c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482281826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.482281826
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1686754024
Short name T494
Test name
Test status
Simulation time 268128184 ps
CPU time 3.04 seconds
Started May 04 03:34:47 PM PDT 24
Finished May 04 03:34:50 PM PDT 24
Peak memory 216132 kb
Host smart-8f060d70-7cdb-410c-9f50-4329a8031178
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686754024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1686754024
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3393362996
Short name T459
Test name
Test status
Simulation time 74622192 ps
CPU time 1.73 seconds
Started May 04 03:35:13 PM PDT 24
Finished May 04 03:35:16 PM PDT 24
Peak memory 213804 kb
Host smart-0489e91a-527a-4602-8161-f4e3cd337440
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393362996 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3393362996
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.3062636096
Short name T498
Test name
Test status
Simulation time 18355419 ps
CPU time 0.93 seconds
Started May 04 03:35:04 PM PDT 24
Finished May 04 03:35:06 PM PDT 24
Peak memory 205456 kb
Host smart-88a679e9-44f2-4185-a424-c57e523b5b19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062636096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3062636096
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2752982100
Short name T554
Test name
Test status
Simulation time 11266787 ps
CPU time 0.77 seconds
Started May 04 03:35:04 PM PDT 24
Finished May 04 03:35:06 PM PDT 24
Peak memory 205480 kb
Host smart-88f79563-b3c7-4bd4-a565-898e84554fbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752982100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2752982100
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.4061758759
Short name T478
Test name
Test status
Simulation time 76022113 ps
CPU time 2.17 seconds
Started May 04 03:35:05 PM PDT 24
Finished May 04 03:35:08 PM PDT 24
Peak memory 205596 kb
Host smart-72b5cd5e-d37e-4237-824e-7cbd334cfe29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061758759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.4061758759
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2360537344
Short name T188
Test name
Test status
Simulation time 284567936 ps
CPU time 5.17 seconds
Started May 04 03:35:04 PM PDT 24
Finished May 04 03:35:10 PM PDT 24
Peak memory 214036 kb
Host smart-1d867b99-e68b-4f04-a51e-117170d2f651
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360537344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2360537344
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2575753835
Short name T557
Test name
Test status
Simulation time 80158220 ps
CPU time 1.64 seconds
Started May 04 03:35:03 PM PDT 24
Finished May 04 03:35:06 PM PDT 24
Peak memory 213868 kb
Host smart-834b7289-de3d-404c-bcc3-c8ba10b757d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575753835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2575753835
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3407323470
Short name T482
Test name
Test status
Simulation time 222445735 ps
CPU time 1.4 seconds
Started May 04 03:35:10 PM PDT 24
Finished May 04 03:35:12 PM PDT 24
Peak memory 213848 kb
Host smart-9731edf4-2832-439d-b0fd-2d543faed801
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407323470 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3407323470
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1668841727
Short name T522
Test name
Test status
Simulation time 13415631 ps
CPU time 1.24 seconds
Started May 04 03:35:08 PM PDT 24
Finished May 04 03:35:10 PM PDT 24
Peak memory 205616 kb
Host smart-05124772-c14f-4416-8472-6e9aaffefa45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668841727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1668841727
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.745676919
Short name T437
Test name
Test status
Simulation time 11234180 ps
CPU time 0.82 seconds
Started May 04 03:35:08 PM PDT 24
Finished May 04 03:35:10 PM PDT 24
Peak memory 205380 kb
Host smart-40d3e75b-b5f3-4dfd-9d37-4071a0ec5535
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745676919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.745676919
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2315425451
Short name T139
Test name
Test status
Simulation time 658141090 ps
CPU time 2.49 seconds
Started May 04 03:35:08 PM PDT 24
Finished May 04 03:35:11 PM PDT 24
Peak memory 205572 kb
Host smart-38ef3d6f-f156-4f54-a87d-f4ee44d512df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315425451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2315425451
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.735961715
Short name T525
Test name
Test status
Simulation time 259630273 ps
CPU time 5.67 seconds
Started May 04 03:35:09 PM PDT 24
Finished May 04 03:35:15 PM PDT 24
Peak memory 214024 kb
Host smart-abab1839-6e65-4774-9ad1-3417a85ee1ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735961715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.735961715
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1440404145
Short name T441
Test name
Test status
Simulation time 100308764 ps
CPU time 4.22 seconds
Started May 04 03:35:08 PM PDT 24
Finished May 04 03:35:12 PM PDT 24
Peak memory 213816 kb
Host smart-b6e80375-0298-4850-bca1-24d0c80c6ac5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440404145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1440404145
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2282853633
Short name T562
Test name
Test status
Simulation time 330321514 ps
CPU time 3.62 seconds
Started May 04 03:35:07 PM PDT 24
Finished May 04 03:35:11 PM PDT 24
Peak memory 216252 kb
Host smart-e514fdb1-70a0-491e-85ad-ebc29972b61e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282853633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2282853633
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1475906327
Short name T540
Test name
Test status
Simulation time 79154311 ps
CPU time 1.87 seconds
Started May 04 03:35:10 PM PDT 24
Finished May 04 03:35:13 PM PDT 24
Peak memory 213848 kb
Host smart-5885d85c-bbdb-45e5-a62e-f4355406ba08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475906327 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1475906327
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.3991768846
Short name T499
Test name
Test status
Simulation time 145119249 ps
CPU time 1.17 seconds
Started May 04 03:35:15 PM PDT 24
Finished May 04 03:35:17 PM PDT 24
Peak memory 204808 kb
Host smart-e51e5235-9523-444d-93cc-c330c1373fae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991768846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.3991768846
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1780526544
Short name T511
Test name
Test status
Simulation time 147987794 ps
CPU time 0.78 seconds
Started May 04 03:35:08 PM PDT 24
Finished May 04 03:35:09 PM PDT 24
Peak memory 205460 kb
Host smart-a451d9ab-4f96-40c5-ae08-67a02be05244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780526544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1780526544
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.529251979
Short name T481
Test name
Test status
Simulation time 104020119 ps
CPU time 3.29 seconds
Started May 04 03:35:10 PM PDT 24
Finished May 04 03:35:14 PM PDT 24
Peak memory 205672 kb
Host smart-b12e387f-ce72-41bc-8ee9-988c4a1d8416
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529251979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.529251979
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4223718632
Short name T119
Test name
Test status
Simulation time 134808967 ps
CPU time 4.12 seconds
Started May 04 03:35:10 PM PDT 24
Finished May 04 03:35:15 PM PDT 24
Peak memory 222180 kb
Host smart-87ece32d-6739-4c6e-831f-915eadf4959d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223718632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.4223718632
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.4181335177
Short name T533
Test name
Test status
Simulation time 437619495 ps
CPU time 4.46 seconds
Started May 04 03:35:09 PM PDT 24
Finished May 04 03:35:14 PM PDT 24
Peak memory 213856 kb
Host smart-45138f56-b9ee-4182-82d1-b57dae59fd9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181335177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.4181335177
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.505553050
Short name T559
Test name
Test status
Simulation time 117993990 ps
CPU time 1.52 seconds
Started May 04 03:35:14 PM PDT 24
Finished May 04 03:35:16 PM PDT 24
Peak memory 213884 kb
Host smart-05aac38b-8805-4443-8ec1-43c2a79bab71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505553050 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.505553050
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3975944459
Short name T451
Test name
Test status
Simulation time 14182762 ps
CPU time 1.16 seconds
Started May 04 03:35:10 PM PDT 24
Finished May 04 03:35:12 PM PDT 24
Peak memory 205528 kb
Host smart-bef4c861-03b1-4bf9-abcf-6084153662c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975944459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3975944459
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.4271473761
Short name T473
Test name
Test status
Simulation time 10475459 ps
CPU time 0.72 seconds
Started May 04 03:35:14 PM PDT 24
Finished May 04 03:35:16 PM PDT 24
Peak memory 205468 kb
Host smart-de094dea-efa5-4912-890a-47686c24096a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271473761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.4271473761
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.775824063
Short name T147
Test name
Test status
Simulation time 83569948 ps
CPU time 1.9 seconds
Started May 04 03:35:11 PM PDT 24
Finished May 04 03:35:13 PM PDT 24
Peak memory 205596 kb
Host smart-edd49ef4-94e9-4300-a953-b9fa6a953549
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775824063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.775824063
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.576148086
Short name T123
Test name
Test status
Simulation time 268705217 ps
CPU time 1.8 seconds
Started May 04 03:35:08 PM PDT 24
Finished May 04 03:35:11 PM PDT 24
Peak memory 213960 kb
Host smart-142dc2cf-27a5-48de-a7f7-fb2b22b3507e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576148086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.576148086
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2847849293
Short name T453
Test name
Test status
Simulation time 357006700 ps
CPU time 9 seconds
Started May 04 03:35:15 PM PDT 24
Finished May 04 03:35:25 PM PDT 24
Peak memory 213020 kb
Host smart-978e217f-23a8-48ad-aac8-96e77cd0d225
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847849293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2847849293
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1822882604
Short name T521
Test name
Test status
Simulation time 363033431 ps
CPU time 2.66 seconds
Started May 04 03:35:10 PM PDT 24
Finished May 04 03:35:14 PM PDT 24
Peak memory 213892 kb
Host smart-027bc6f9-8afc-4e89-8adf-f0d664dde7e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822882604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1822882604
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2147890722
Short name T171
Test name
Test status
Simulation time 762798932 ps
CPU time 10.99 seconds
Started May 04 03:35:10 PM PDT 24
Finished May 04 03:35:22 PM PDT 24
Peak memory 213908 kb
Host smart-3efe7581-c3f8-4b90-86a2-543c4ce711da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147890722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2147890722
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1042969263
Short name T186
Test name
Test status
Simulation time 71820701 ps
CPU time 1.32 seconds
Started May 04 03:35:12 PM PDT 24
Finished May 04 03:35:14 PM PDT 24
Peak memory 213940 kb
Host smart-e395789e-5736-492a-8635-d1c0ab43c54a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042969263 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1042969263
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.762517288
Short name T545
Test name
Test status
Simulation time 46492178 ps
CPU time 1.15 seconds
Started May 04 03:35:14 PM PDT 24
Finished May 04 03:35:16 PM PDT 24
Peak memory 205544 kb
Host smart-e2a7a034-b9f3-4713-940e-5c2077846c3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762517288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.762517288
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.229459312
Short name T556
Test name
Test status
Simulation time 36741521 ps
CPU time 0.73 seconds
Started May 04 03:35:14 PM PDT 24
Finished May 04 03:35:15 PM PDT 24
Peak memory 205456 kb
Host smart-969cf11a-ea7e-4399-a49a-096114e7fb48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229459312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.229459312
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4240710228
Short name T146
Test name
Test status
Simulation time 99952402 ps
CPU time 3.23 seconds
Started May 04 03:35:14 PM PDT 24
Finished May 04 03:35:18 PM PDT 24
Peak memory 205572 kb
Host smart-57904496-f77f-4c08-a05b-8fb5501c5931
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240710228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.4240710228
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2479467876
Short name T495
Test name
Test status
Simulation time 4595886832 ps
CPU time 67.71 seconds
Started May 04 03:35:12 PM PDT 24
Finished May 04 03:36:21 PM PDT 24
Peak memory 215004 kb
Host smart-ca5d6684-f2f7-4f4a-aeb8-cf445a93450b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479467876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2479467876
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3652117351
Short name T496
Test name
Test status
Simulation time 587191219 ps
CPU time 5.64 seconds
Started May 04 03:35:16 PM PDT 24
Finished May 04 03:35:23 PM PDT 24
Peak memory 213984 kb
Host smart-4a6bdc50-92a4-4328-a844-5bf6ad7d9b80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652117351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3652117351
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3326068270
Short name T126
Test name
Test status
Simulation time 153867846 ps
CPU time 3.97 seconds
Started May 04 03:35:13 PM PDT 24
Finished May 04 03:35:18 PM PDT 24
Peak memory 217104 kb
Host smart-4786c4da-5e38-461e-a5a3-b45b605dfe51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326068270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3326068270
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3121212243
Short name T548
Test name
Test status
Simulation time 131249082 ps
CPU time 1.07 seconds
Started May 04 03:35:17 PM PDT 24
Finished May 04 03:35:19 PM PDT 24
Peak memory 205548 kb
Host smart-c23e0ab0-1938-4de3-bb2f-06c5fdefbb4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121212243 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3121212243
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3403581607
Short name T508
Test name
Test status
Simulation time 32642600 ps
CPU time 1.23 seconds
Started May 04 03:35:13 PM PDT 24
Finished May 04 03:35:15 PM PDT 24
Peak memory 205468 kb
Host smart-96b73ac8-a6d4-46e9-b45e-2ea4aee59956
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403581607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3403581607
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2551149072
Short name T501
Test name
Test status
Simulation time 18039043 ps
CPU time 1.02 seconds
Started May 04 03:35:13 PM PDT 24
Finished May 04 03:35:15 PM PDT 24
Peak memory 205628 kb
Host smart-291dcd2f-8b99-4087-b593-bd468bb3ddf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551149072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2551149072
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.153902036
Short name T558
Test name
Test status
Simulation time 370631125 ps
CPU time 5.39 seconds
Started May 04 03:35:13 PM PDT 24
Finished May 04 03:35:19 PM PDT 24
Peak memory 222172 kb
Host smart-9cfbafd3-582e-4362-aabb-10ed1e238d2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153902036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shado
w_reg_errors.153902036
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.414726008
Short name T117
Test name
Test status
Simulation time 989080765 ps
CPU time 4.38 seconds
Started May 04 03:35:17 PM PDT 24
Finished May 04 03:35:23 PM PDT 24
Peak memory 213964 kb
Host smart-17bbb27e-5473-4023-b591-550cc59b25a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414726008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.414726008
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3316718026
Short name T137
Test name
Test status
Simulation time 79281452 ps
CPU time 2.19 seconds
Started May 04 03:35:14 PM PDT 24
Finished May 04 03:35:17 PM PDT 24
Peak memory 214032 kb
Host smart-576fe934-216e-4d1e-a094-70b40c098f9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316718026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3316718026
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1551487221
Short name T136
Test name
Test status
Simulation time 37324152 ps
CPU time 1.78 seconds
Started May 04 03:35:13 PM PDT 24
Finished May 04 03:35:16 PM PDT 24
Peak memory 218184 kb
Host smart-0160bbf7-3d33-4986-b23e-e0a965bf306b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551487221 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1551487221
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3973093469
Short name T444
Test name
Test status
Simulation time 18715452 ps
CPU time 0.96 seconds
Started May 04 03:35:14 PM PDT 24
Finished May 04 03:35:15 PM PDT 24
Peak memory 205444 kb
Host smart-beb51e15-367e-4043-8546-aee52b95361a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973093469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3973093469
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1528205117
Short name T555
Test name
Test status
Simulation time 94130940 ps
CPU time 0.81 seconds
Started May 04 03:35:15 PM PDT 24
Finished May 04 03:35:17 PM PDT 24
Peak memory 205416 kb
Host smart-e7febeee-3219-42d5-a8f7-ee67f8c36771
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528205117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1528205117
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3320476046
Short name T513
Test name
Test status
Simulation time 50966705 ps
CPU time 1.68 seconds
Started May 04 03:35:17 PM PDT 24
Finished May 04 03:35:20 PM PDT 24
Peak memory 205580 kb
Host smart-ff333b89-c082-4989-9cde-f3c9fb08a130
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320476046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3320476046
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1348541529
Short name T434
Test name
Test status
Simulation time 365864925 ps
CPU time 8.92 seconds
Started May 04 03:35:23 PM PDT 24
Finished May 04 03:35:33 PM PDT 24
Peak memory 214036 kb
Host smart-51d243b5-3102-437e-b7fd-54b56ccda36a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348541529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1348541529
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4247207716
Short name T500
Test name
Test status
Simulation time 50787739 ps
CPU time 2.28 seconds
Started May 04 03:35:15 PM PDT 24
Finished May 04 03:35:19 PM PDT 24
Peak memory 213924 kb
Host smart-385d1500-30d4-47eb-9ecd-92059f41d6ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247207716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.4247207716
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3089970572
Short name T549
Test name
Test status
Simulation time 40091785 ps
CPU time 1.06 seconds
Started May 04 03:35:22 PM PDT 24
Finished May 04 03:35:24 PM PDT 24
Peak memory 205584 kb
Host smart-5cc78ff0-4e4e-42bf-a16a-4d5110516d7b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089970572 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3089970572
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1502347011
Short name T490
Test name
Test status
Simulation time 180311176 ps
CPU time 0.92 seconds
Started May 04 03:35:22 PM PDT 24
Finished May 04 03:35:23 PM PDT 24
Peak memory 205456 kb
Host smart-d3aa135d-50db-4578-8b33-6cefa8df8d4d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502347011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1502347011
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1179829244
Short name T144
Test name
Test status
Simulation time 39016928 ps
CPU time 0.73 seconds
Started May 04 03:35:23 PM PDT 24
Finished May 04 03:35:24 PM PDT 24
Peak memory 205400 kb
Host smart-6d6bd9e8-7168-4843-935f-7355ccc43b7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179829244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1179829244
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1691968890
Short name T449
Test name
Test status
Simulation time 24177842 ps
CPU time 1.48 seconds
Started May 04 03:35:25 PM PDT 24
Finished May 04 03:35:27 PM PDT 24
Peak memory 205604 kb
Host smart-cab495a5-c8f8-41b5-9780-8d51e586c903
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691968890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1691968890
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3647551153
Short name T454
Test name
Test status
Simulation time 606231964 ps
CPU time 12.53 seconds
Started May 04 03:35:15 PM PDT 24
Finished May 04 03:35:29 PM PDT 24
Peak memory 215160 kb
Host smart-61d71495-1893-49f4-a07d-cac62ee9296f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647551153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3647551153
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.511809023
Short name T534
Test name
Test status
Simulation time 778151416 ps
CPU time 11.03 seconds
Started May 04 03:35:14 PM PDT 24
Finished May 04 03:35:26 PM PDT 24
Peak memory 214032 kb
Host smart-f78b7969-c18e-4773-b9eb-b47c037a0b1c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511809023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.511809023
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3451957420
Short name T130
Test name
Test status
Simulation time 329411083 ps
CPU time 3.08 seconds
Started May 04 03:35:16 PM PDT 24
Finished May 04 03:35:20 PM PDT 24
Peak memory 213800 kb
Host smart-ee2ea957-f0cf-4b8f-bbf1-f26c441cec0a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451957420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3451957420
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2428255193
Short name T161
Test name
Test status
Simulation time 220760235 ps
CPU time 4.85 seconds
Started May 04 03:35:15 PM PDT 24
Finished May 04 03:35:21 PM PDT 24
Peak memory 213852 kb
Host smart-6fe0418f-c174-4c2e-88ff-7fe47c0530e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428255193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2428255193
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.582741691
Short name T539
Test name
Test status
Simulation time 181356440 ps
CPU time 1.35 seconds
Started May 04 03:35:25 PM PDT 24
Finished May 04 03:35:27 PM PDT 24
Peak memory 213820 kb
Host smart-47f05227-53d2-4d99-9131-63cb02e3702b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582741691 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.582741691
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.766527653
Short name T452
Test name
Test status
Simulation time 17770994 ps
CPU time 0.95 seconds
Started May 04 03:35:26 PM PDT 24
Finished May 04 03:35:28 PM PDT 24
Peak memory 205408 kb
Host smart-6456594e-193a-4b45-aae6-7402605e057e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766527653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.766527653
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.718540457
Short name T190
Test name
Test status
Simulation time 42470812 ps
CPU time 0.78 seconds
Started May 04 03:35:26 PM PDT 24
Finished May 04 03:35:28 PM PDT 24
Peak memory 205452 kb
Host smart-00779117-a16f-421c-89c1-caec09db68dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718540457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.718540457
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.488151141
Short name T546
Test name
Test status
Simulation time 22315843 ps
CPU time 1.74 seconds
Started May 04 03:35:24 PM PDT 24
Finished May 04 03:35:27 PM PDT 24
Peak memory 205680 kb
Host smart-f39c9b00-530b-46fb-b06e-8f953aed04b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488151141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.488151141
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2586875172
Short name T122
Test name
Test status
Simulation time 510163226 ps
CPU time 5.17 seconds
Started May 04 03:35:22 PM PDT 24
Finished May 04 03:35:28 PM PDT 24
Peak memory 214048 kb
Host smart-ce4a56a1-85bd-4b10-b7b9-a000e3fcce1b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586875172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2586875172
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3336470673
Short name T118
Test name
Test status
Simulation time 2271710981 ps
CPU time 14.94 seconds
Started May 04 03:35:23 PM PDT 24
Finished May 04 03:35:38 PM PDT 24
Peak memory 213980 kb
Host smart-156d0eb1-d309-4dee-bb0e-ddea5b374de2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336470673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3336470673
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1683293171
Short name T458
Test name
Test status
Simulation time 230424732 ps
CPU time 2.12 seconds
Started May 04 03:35:23 PM PDT 24
Finished May 04 03:35:26 PM PDT 24
Peak memory 213796 kb
Host smart-32b55265-b2bb-4f06-aca1-f35b36e0ba4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683293171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1683293171
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3878917609
Short name T187
Test name
Test status
Simulation time 30879347 ps
CPU time 1.51 seconds
Started May 04 03:35:24 PM PDT 24
Finished May 04 03:35:26 PM PDT 24
Peak memory 205716 kb
Host smart-0b34eb40-4c19-4022-9122-287528508176
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878917609 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3878917609
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3171495998
Short name T504
Test name
Test status
Simulation time 120146856 ps
CPU time 1.21 seconds
Started May 04 03:35:25 PM PDT 24
Finished May 04 03:35:27 PM PDT 24
Peak memory 205524 kb
Host smart-4f4e91a9-9061-4a59-8aee-2f7e0757f33e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171495998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3171495998
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.117169031
Short name T145
Test name
Test status
Simulation time 19270355 ps
CPU time 0.7 seconds
Started May 04 03:35:23 PM PDT 24
Finished May 04 03:35:24 PM PDT 24
Peak memory 205452 kb
Host smart-4932d8bc-16bd-4fcf-a3dd-970317553fc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117169031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.117169031
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1825917808
Short name T433
Test name
Test status
Simulation time 19360712 ps
CPU time 1.51 seconds
Started May 04 03:35:23 PM PDT 24
Finished May 04 03:35:25 PM PDT 24
Peak memory 205568 kb
Host smart-1e79c8f6-20c1-4fe1-807b-f55bd1012109
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825917808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1825917808
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3418899547
Short name T466
Test name
Test status
Simulation time 360304106 ps
CPU time 3.29 seconds
Started May 04 03:35:23 PM PDT 24
Finished May 04 03:35:27 PM PDT 24
Peak memory 214020 kb
Host smart-df80cc25-1daf-4415-9736-1f42065f0c19
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418899547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3418899547
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4017702688
Short name T502
Test name
Test status
Simulation time 47182135 ps
CPU time 1.86 seconds
Started May 04 03:35:25 PM PDT 24
Finished May 04 03:35:27 PM PDT 24
Peak memory 213888 kb
Host smart-e5bcd429-40ca-4cd6-878a-0497ebc91157
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017702688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.4017702688
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.4137239093
Short name T446
Test name
Test status
Simulation time 129222025 ps
CPU time 7.43 seconds
Started May 04 03:34:52 PM PDT 24
Finished May 04 03:35:01 PM PDT 24
Peak memory 205496 kb
Host smart-30920780-317c-4c1b-82ce-0042ea7a77e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137239093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.4
137239093
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.86569116
Short name T460
Test name
Test status
Simulation time 264833046 ps
CPU time 6.35 seconds
Started May 04 03:34:53 PM PDT 24
Finished May 04 03:35:00 PM PDT 24
Peak memory 205576 kb
Host smart-557112e2-6edc-415e-b98e-f8281af3967d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86569116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.86569116
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.499470107
Short name T477
Test name
Test status
Simulation time 53083624 ps
CPU time 1.01 seconds
Started May 04 03:34:46 PM PDT 24
Finished May 04 03:34:48 PM PDT 24
Peak memory 205440 kb
Host smart-bb27e8d2-4fd1-4a0e-b61a-d5712b655f4c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499470107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.499470107
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.172686204
Short name T518
Test name
Test status
Simulation time 35549946 ps
CPU time 1.31 seconds
Started May 04 03:34:52 PM PDT 24
Finished May 04 03:34:54 PM PDT 24
Peak memory 213844 kb
Host smart-fff136ec-5a8d-4446-860a-1abb8f603bc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172686204 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.172686204
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.202011432
Short name T447
Test name
Test status
Simulation time 64250538 ps
CPU time 1.11 seconds
Started May 04 03:34:56 PM PDT 24
Finished May 04 03:34:58 PM PDT 24
Peak memory 205512 kb
Host smart-288a801f-4a5d-41a8-acf7-bbcc6b89dd29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202011432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.202011432
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.479961356
Short name T429
Test name
Test status
Simulation time 22463720 ps
CPU time 0.92 seconds
Started May 04 03:34:44 PM PDT 24
Finished May 04 03:34:46 PM PDT 24
Peak memory 205416 kb
Host smart-0001d099-de2a-4a54-ad72-6cecffd4c98e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479961356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.479961356
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3368569264
Short name T483
Test name
Test status
Simulation time 257048793 ps
CPU time 2.15 seconds
Started May 04 03:34:52 PM PDT 24
Finished May 04 03:34:54 PM PDT 24
Peak memory 205596 kb
Host smart-00c35117-eedf-4d75-a27c-11450839da6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368569264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3368569264
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1448673698
Short name T512
Test name
Test status
Simulation time 185889723 ps
CPU time 2.54 seconds
Started May 04 03:34:45 PM PDT 24
Finished May 04 03:34:48 PM PDT 24
Peak memory 214040 kb
Host smart-fb9c5b39-31b6-44bb-83e7-0284f2187063
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448673698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1448673698
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2876142194
Short name T486
Test name
Test status
Simulation time 297556771 ps
CPU time 2.89 seconds
Started May 04 03:34:56 PM PDT 24
Finished May 04 03:35:00 PM PDT 24
Peak memory 216940 kb
Host smart-f19b7800-45cf-4ad7-9749-41c343bc5c27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876142194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2876142194
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.466325951
Short name T487
Test name
Test status
Simulation time 41807804 ps
CPU time 0.86 seconds
Started May 04 03:35:25 PM PDT 24
Finished May 04 03:35:27 PM PDT 24
Peak memory 205352 kb
Host smart-240092e7-a091-40dc-939b-ffcf838756f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466325951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.466325951
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.805788708
Short name T507
Test name
Test status
Simulation time 54961454 ps
CPU time 0.76 seconds
Started May 04 03:35:23 PM PDT 24
Finished May 04 03:35:25 PM PDT 24
Peak memory 205396 kb
Host smart-abe0d200-7e23-43e7-973f-9c3eddbca0ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805788708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.805788708
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.633722316
Short name T519
Test name
Test status
Simulation time 53246962 ps
CPU time 0.82 seconds
Started May 04 03:35:26 PM PDT 24
Finished May 04 03:35:28 PM PDT 24
Peak memory 205488 kb
Host smart-ed14ab3e-bb53-49f3-8ed1-47937273c545
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633722316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.633722316
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3883746864
Short name T470
Test name
Test status
Simulation time 11893694 ps
CPU time 0.73 seconds
Started May 04 03:35:22 PM PDT 24
Finished May 04 03:35:24 PM PDT 24
Peak memory 205468 kb
Host smart-a0b9977d-b854-4a2e-8513-4ff92bff6f1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883746864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3883746864
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3522857093
Short name T550
Test name
Test status
Simulation time 11128335 ps
CPU time 0.86 seconds
Started May 04 03:35:24 PM PDT 24
Finished May 04 03:35:25 PM PDT 24
Peak memory 205404 kb
Host smart-c118d70b-3e8d-4331-b101-9cd342aa0b54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522857093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3522857093
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2394437635
Short name T189
Test name
Test status
Simulation time 10828932 ps
CPU time 0.81 seconds
Started May 04 03:35:25 PM PDT 24
Finished May 04 03:35:26 PM PDT 24
Peak memory 205392 kb
Host smart-ac2733ac-fff9-49f9-9783-b7a10ca966c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394437635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2394437635
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.534990715
Short name T530
Test name
Test status
Simulation time 22238266 ps
CPU time 0.96 seconds
Started May 04 03:35:25 PM PDT 24
Finished May 04 03:35:26 PM PDT 24
Peak memory 205372 kb
Host smart-568793ac-ae1c-4820-b6fd-0da0d6846fe6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534990715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.534990715
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2278403289
Short name T524
Test name
Test status
Simulation time 17688220 ps
CPU time 0.76 seconds
Started May 04 03:35:23 PM PDT 24
Finished May 04 03:35:24 PM PDT 24
Peak memory 205476 kb
Host smart-76140acd-94ba-4e3f-8ccb-0289a30df4bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278403289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2278403289
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.679361115
Short name T471
Test name
Test status
Simulation time 46522129 ps
CPU time 0.84 seconds
Started May 04 03:35:25 PM PDT 24
Finished May 04 03:35:27 PM PDT 24
Peak memory 205428 kb
Host smart-7d6879df-8870-4a00-a19f-399b2d21a5d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679361115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.679361115
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.73802736
Short name T455
Test name
Test status
Simulation time 30729401 ps
CPU time 0.75 seconds
Started May 04 03:35:25 PM PDT 24
Finished May 04 03:35:27 PM PDT 24
Peak memory 205448 kb
Host smart-c6266d5b-b6bc-42e6-8ca5-cf72fbd78a37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73802736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.73802736
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.241777830
Short name T140
Test name
Test status
Simulation time 71401684 ps
CPU time 4.01 seconds
Started May 04 03:34:51 PM PDT 24
Finished May 04 03:34:56 PM PDT 24
Peak memory 205516 kb
Host smart-4a173626-785d-4f4e-9188-771f666e2108
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241777830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.241777830
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1049028223
Short name T491
Test name
Test status
Simulation time 511117752 ps
CPU time 14.26 seconds
Started May 04 03:34:51 PM PDT 24
Finished May 04 03:35:06 PM PDT 24
Peak memory 205540 kb
Host smart-f3b29248-e74e-4e92-ba2a-30fef58f9384
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049028223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
049028223
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.489471261
Short name T552
Test name
Test status
Simulation time 136324106 ps
CPU time 1.02 seconds
Started May 04 03:34:52 PM PDT 24
Finished May 04 03:34:54 PM PDT 24
Peak memory 205436 kb
Host smart-702718a6-a27b-4ab2-9d9f-90ba80e796a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489471261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.489471261
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3340457366
Short name T442
Test name
Test status
Simulation time 38095865 ps
CPU time 1.58 seconds
Started May 04 03:34:52 PM PDT 24
Finished May 04 03:34:54 PM PDT 24
Peak memory 213860 kb
Host smart-a7de0694-de78-497a-b502-b96a8b74bd54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340457366 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3340457366
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1654355508
Short name T489
Test name
Test status
Simulation time 19383146 ps
CPU time 0.68 seconds
Started May 04 03:34:53 PM PDT 24
Finished May 04 03:34:54 PM PDT 24
Peak memory 205488 kb
Host smart-7b89c4dd-5c35-43b8-9562-70dd48ef7922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654355508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1654355508
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3454562531
Short name T553
Test name
Test status
Simulation time 43955694 ps
CPU time 1.36 seconds
Started May 04 03:34:51 PM PDT 24
Finished May 04 03:34:53 PM PDT 24
Peak memory 205600 kb
Host smart-df687447-b7f7-4eb8-ae69-5338705fccbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454562531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3454562531
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.512461154
Short name T448
Test name
Test status
Simulation time 284903595 ps
CPU time 3.24 seconds
Started May 04 03:34:52 PM PDT 24
Finished May 04 03:34:56 PM PDT 24
Peak memory 214068 kb
Host smart-197c4fba-8506-4f54-af06-c483f16ac6b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512461154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow
_reg_errors.512461154
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.376606019
Short name T164
Test name
Test status
Simulation time 199347088 ps
CPU time 2.77 seconds
Started May 04 03:34:50 PM PDT 24
Finished May 04 03:34:53 PM PDT 24
Peak memory 213880 kb
Host smart-b5e93b89-7f1e-406d-a81f-eb42b8d8f786
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376606019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.376606019
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3479496846
Short name T551
Test name
Test status
Simulation time 13867744 ps
CPU time 0.9 seconds
Started May 04 03:35:24 PM PDT 24
Finished May 04 03:35:26 PM PDT 24
Peak memory 205412 kb
Host smart-78a2e41c-32fe-403f-a9d3-5d5262c37b0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479496846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3479496846
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2263732969
Short name T528
Test name
Test status
Simulation time 53020908 ps
CPU time 0.72 seconds
Started May 04 03:35:26 PM PDT 24
Finished May 04 03:35:28 PM PDT 24
Peak memory 205052 kb
Host smart-f5af9161-a46f-4943-91da-b47f338d3e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263732969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2263732969
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3420271178
Short name T438
Test name
Test status
Simulation time 39726316 ps
CPU time 0.75 seconds
Started May 04 03:35:26 PM PDT 24
Finished May 04 03:35:28 PM PDT 24
Peak memory 205440 kb
Host smart-2433bd3a-f514-490c-bfe5-116f93d04f53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420271178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3420271178
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3371411942
Short name T535
Test name
Test status
Simulation time 46009741 ps
CPU time 0.86 seconds
Started May 04 03:35:33 PM PDT 24
Finished May 04 03:35:35 PM PDT 24
Peak memory 205488 kb
Host smart-1c7a58c8-b6c0-472a-8e13-99149f557495
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371411942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3371411942
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.83558872
Short name T192
Test name
Test status
Simulation time 22538567 ps
CPU time 0.83 seconds
Started May 04 03:35:27 PM PDT 24
Finished May 04 03:35:29 PM PDT 24
Peak memory 205372 kb
Host smart-0f684533-8695-4431-a1f6-1f3a88947286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83558872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.83558872
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.902669819
Short name T520
Test name
Test status
Simulation time 17364225 ps
CPU time 0.82 seconds
Started May 04 03:35:31 PM PDT 24
Finished May 04 03:35:32 PM PDT 24
Peak memory 205396 kb
Host smart-153e2831-1853-4fda-bf5f-dcfa4c282dcb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902669819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.902669819
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1416813104
Short name T428
Test name
Test status
Simulation time 20552116 ps
CPU time 0.7 seconds
Started May 04 03:35:29 PM PDT 24
Finished May 04 03:35:31 PM PDT 24
Peak memory 205424 kb
Host smart-a51e4e73-143b-4d13-9f32-990ea972dee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416813104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1416813104
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.222787028
Short name T465
Test name
Test status
Simulation time 166447948 ps
CPU time 0.8 seconds
Started May 04 03:35:25 PM PDT 24
Finished May 04 03:35:27 PM PDT 24
Peak memory 205400 kb
Host smart-94cdba58-5582-4528-98e3-80134d764c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222787028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.222787028
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3895076202
Short name T445
Test name
Test status
Simulation time 19617638 ps
CPU time 0.76 seconds
Started May 04 03:35:28 PM PDT 24
Finished May 04 03:35:30 PM PDT 24
Peak memory 205476 kb
Host smart-98218425-ffcd-4655-a6ed-97adb3ee0b1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895076202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3895076202
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.462222439
Short name T475
Test name
Test status
Simulation time 46118144 ps
CPU time 0.72 seconds
Started May 04 03:35:26 PM PDT 24
Finished May 04 03:35:28 PM PDT 24
Peak memory 205456 kb
Host smart-30465203-90ce-4f35-b4fc-5f58553d3983
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462222439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.462222439
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2515961372
Short name T531
Test name
Test status
Simulation time 357394303 ps
CPU time 13.85 seconds
Started May 04 03:34:58 PM PDT 24
Finished May 04 03:35:13 PM PDT 24
Peak memory 205516 kb
Host smart-0091b2ad-aac0-4453-a513-8b09dfdb8b6c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515961372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
515961372
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.4192634223
Short name T560
Test name
Test status
Simulation time 100989998 ps
CPU time 1.01 seconds
Started May 04 03:34:58 PM PDT 24
Finished May 04 03:35:00 PM PDT 24
Peak memory 205456 kb
Host smart-2b89a574-e867-48d8-8c84-aee35974fcc6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192634223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.4
192634223
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1490987390
Short name T527
Test name
Test status
Simulation time 40039196 ps
CPU time 1.27 seconds
Started May 04 03:34:59 PM PDT 24
Finished May 04 03:35:01 PM PDT 24
Peak memory 213524 kb
Host smart-9aa0ebf5-a401-473f-96a5-f8b784d1728b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490987390 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1490987390
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.520945618
Short name T561
Test name
Test status
Simulation time 455626106 ps
CPU time 1.31 seconds
Started May 04 03:35:03 PM PDT 24
Finished May 04 03:35:05 PM PDT 24
Peak memory 205452 kb
Host smart-b199032d-a637-4918-b589-f223a3126513
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520945618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.520945618
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3678106626
Short name T509
Test name
Test status
Simulation time 19231060 ps
CPU time 0.71 seconds
Started May 04 03:35:00 PM PDT 24
Finished May 04 03:35:01 PM PDT 24
Peak memory 205416 kb
Host smart-2e634c11-1ed3-4146-8306-5cfb30e4160b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678106626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3678106626
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3262607010
Short name T462
Test name
Test status
Simulation time 103817766 ps
CPU time 1.51 seconds
Started May 04 03:34:57 PM PDT 24
Finished May 04 03:34:59 PM PDT 24
Peak memory 205576 kb
Host smart-bd41787c-7041-4f0a-bce3-a1db867002bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262607010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3262607010
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1861596778
Short name T544
Test name
Test status
Simulation time 386760953 ps
CPU time 2.61 seconds
Started May 04 03:34:57 PM PDT 24
Finished May 04 03:35:00 PM PDT 24
Peak memory 214004 kb
Host smart-c816218b-b947-4b1f-ad37-f2f5201c8a3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861596778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1861596778
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1770347559
Short name T467
Test name
Test status
Simulation time 203360079 ps
CPU time 8.48 seconds
Started May 04 03:34:50 PM PDT 24
Finished May 04 03:34:59 PM PDT 24
Peak memory 220204 kb
Host smart-011e60c4-60ff-44e7-994a-78b687e0064d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770347559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1770347559
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.4292752663
Short name T536
Test name
Test status
Simulation time 57487523 ps
CPU time 1.75 seconds
Started May 04 03:34:57 PM PDT 24
Finished May 04 03:35:00 PM PDT 24
Peak memory 216016 kb
Host smart-3d25eabb-a466-454f-9baa-b69fb9473214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292752663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.4292752663
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1205976860
Short name T129
Test name
Test status
Simulation time 346386806 ps
CPU time 8.92 seconds
Started May 04 03:34:57 PM PDT 24
Finished May 04 03:35:07 PM PDT 24
Peak memory 213728 kb
Host smart-9b457205-33dc-4e1e-84a4-58180ff72622
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205976860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1205976860
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.797895380
Short name T547
Test name
Test status
Simulation time 186735598 ps
CPU time 0.73 seconds
Started May 04 03:35:34 PM PDT 24
Finished May 04 03:35:35 PM PDT 24
Peak memory 205416 kb
Host smart-162193a8-dfac-40c5-8a8b-4c0cb50abcfd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797895380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.797895380
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2134925359
Short name T435
Test name
Test status
Simulation time 39738789 ps
CPU time 0.78 seconds
Started May 04 03:35:31 PM PDT 24
Finished May 04 03:35:32 PM PDT 24
Peak memory 205400 kb
Host smart-4a00eea1-957a-48ca-8ad7-9f37f47f2b30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134925359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2134925359
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3166033746
Short name T506
Test name
Test status
Simulation time 16676458 ps
CPU time 0.7 seconds
Started May 04 03:35:27 PM PDT 24
Finished May 04 03:35:29 PM PDT 24
Peak memory 205464 kb
Host smart-0b96b287-b2a4-498e-b712-d341e08fda3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166033746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3166033746
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.920764420
Short name T529
Test name
Test status
Simulation time 69140749 ps
CPU time 0.77 seconds
Started May 04 03:35:27 PM PDT 24
Finished May 04 03:35:29 PM PDT 24
Peak memory 205468 kb
Host smart-bb2f55fb-dec1-4d57-a44f-e292cb5b3897
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920764420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.920764420
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.186192311
Short name T505
Test name
Test status
Simulation time 25984386 ps
CPU time 0.87 seconds
Started May 04 03:35:28 PM PDT 24
Finished May 04 03:35:30 PM PDT 24
Peak memory 205468 kb
Host smart-dced61d5-0de4-4798-b3f1-d27c2b9c2938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186192311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.186192311
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1351342328
Short name T191
Test name
Test status
Simulation time 10744654 ps
CPU time 0.73 seconds
Started May 04 03:35:26 PM PDT 24
Finished May 04 03:35:28 PM PDT 24
Peak memory 205388 kb
Host smart-0159e269-a45b-4b1f-b09a-f703e5ffb24a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351342328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1351342328
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.4133810110
Short name T479
Test name
Test status
Simulation time 19682876 ps
CPU time 0.75 seconds
Started May 04 03:35:34 PM PDT 24
Finished May 04 03:35:35 PM PDT 24
Peak memory 205220 kb
Host smart-efce07f2-3cc1-4df8-8539-030efdf3ba41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133810110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.4133810110
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2549082698
Short name T457
Test name
Test status
Simulation time 14739774 ps
CPU time 0.86 seconds
Started May 04 03:35:34 PM PDT 24
Finished May 04 03:35:35 PM PDT 24
Peak memory 205144 kb
Host smart-7cf211f0-5943-41e2-95ad-dacb3d615b46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549082698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2549082698
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.524466870
Short name T476
Test name
Test status
Simulation time 15178700 ps
CPU time 0.68 seconds
Started May 04 03:35:29 PM PDT 24
Finished May 04 03:35:30 PM PDT 24
Peak memory 205396 kb
Host smart-e7107a92-54be-4388-bb97-35bd057d111a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524466870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.524466870
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.640298728
Short name T514
Test name
Test status
Simulation time 11491101 ps
CPU time 0.81 seconds
Started May 04 03:35:27 PM PDT 24
Finished May 04 03:35:29 PM PDT 24
Peak memory 205452 kb
Host smart-48fec50e-4195-461e-b391-932ae1e0eca6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640298728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.640298728
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3928499099
Short name T485
Test name
Test status
Simulation time 27566892 ps
CPU time 0.97 seconds
Started May 04 03:34:58 PM PDT 24
Finished May 04 03:35:00 PM PDT 24
Peak memory 205528 kb
Host smart-24aed84d-373a-4e50-b41a-3f6c2ccb8b63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928499099 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3928499099
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1892922935
Short name T538
Test name
Test status
Simulation time 11266751 ps
CPU time 0.87 seconds
Started May 04 03:34:58 PM PDT 24
Finished May 04 03:35:00 PM PDT 24
Peak memory 205388 kb
Host smart-ed7dce20-387b-489c-85bf-3e303969e7e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892922935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1892922935
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3020293804
Short name T510
Test name
Test status
Simulation time 23713823 ps
CPU time 0.84 seconds
Started May 04 03:34:59 PM PDT 24
Finished May 04 03:35:01 PM PDT 24
Peak memory 204960 kb
Host smart-4290de1e-e3c2-47c0-b35c-71e56644b67a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020293804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3020293804
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1863353541
Short name T474
Test name
Test status
Simulation time 43316883 ps
CPU time 2.66 seconds
Started May 04 03:35:03 PM PDT 24
Finished May 04 03:35:06 PM PDT 24
Peak memory 205556 kb
Host smart-3f04c117-6390-49c9-9ce3-46aabab4b429
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863353541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1863353541
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1368995215
Short name T469
Test name
Test status
Simulation time 338503710 ps
CPU time 5.18 seconds
Started May 04 03:35:01 PM PDT 24
Finished May 04 03:35:07 PM PDT 24
Peak memory 213956 kb
Host smart-02d0eb18-c13a-4028-acb9-c4fe9220179b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368995215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1368995215
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.336499961
Short name T497
Test name
Test status
Simulation time 292007607 ps
CPU time 3.31 seconds
Started May 04 03:34:58 PM PDT 24
Finished May 04 03:35:02 PM PDT 24
Peak memory 213792 kb
Host smart-565daf5e-6490-412d-bc69-8efc8ae25a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336499961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.336499961
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3038939731
Short name T532
Test name
Test status
Simulation time 31271499 ps
CPU time 1.27 seconds
Started May 04 03:34:56 PM PDT 24
Finished May 04 03:34:58 PM PDT 24
Peak memory 205740 kb
Host smart-043d259a-7808-49ec-84c2-edc581881dc0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038939731 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3038939731
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1470599952
Short name T464
Test name
Test status
Simulation time 26589696 ps
CPU time 0.71 seconds
Started May 04 03:34:59 PM PDT 24
Finished May 04 03:35:00 PM PDT 24
Peak memory 205464 kb
Host smart-e6d9308b-8477-481f-9c7b-72873567f934
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470599952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1470599952
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2796110716
Short name T176
Test name
Test status
Simulation time 268870262 ps
CPU time 2.82 seconds
Started May 04 03:35:03 PM PDT 24
Finished May 04 03:35:07 PM PDT 24
Peak memory 213996 kb
Host smart-e2d5d3fb-a1a7-4f3d-b1b2-b341e9b64f91
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796110716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2796110716
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.4269094665
Short name T543
Test name
Test status
Simulation time 359853905 ps
CPU time 8.11 seconds
Started May 04 03:34:56 PM PDT 24
Finished May 04 03:35:05 PM PDT 24
Peak memory 213960 kb
Host smart-a65c7d84-35ca-453e-bb85-b46afcfd9986
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269094665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.4269094665
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1727264195
Short name T480
Test name
Test status
Simulation time 99359393 ps
CPU time 4.09 seconds
Started May 04 03:34:57 PM PDT 24
Finished May 04 03:35:02 PM PDT 24
Peak memory 213848 kb
Host smart-945a8d2e-f97c-4d8f-abb7-256784411f76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727264195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1727264195
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.342008894
Short name T541
Test name
Test status
Simulation time 19142126 ps
CPU time 1.44 seconds
Started May 04 03:35:07 PM PDT 24
Finished May 04 03:35:09 PM PDT 24
Peak memory 213728 kb
Host smart-cb75199f-d20f-4fc9-88e5-9b9a1aaf9064
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342008894 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.342008894
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2078938258
Short name T439
Test name
Test status
Simulation time 22306997 ps
CPU time 1.3 seconds
Started May 04 03:35:02 PM PDT 24
Finished May 04 03:35:04 PM PDT 24
Peak memory 205516 kb
Host smart-51f24a06-a1e6-42c0-8756-02b9491520a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078938258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2078938258
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.4089641911
Short name T456
Test name
Test status
Simulation time 17079219 ps
CPU time 0.81 seconds
Started May 04 03:35:04 PM PDT 24
Finished May 04 03:35:06 PM PDT 24
Peak memory 205448 kb
Host smart-231d3457-0844-4413-ab0e-e70395588edf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089641911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.4089641911
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.4082876811
Short name T143
Test name
Test status
Simulation time 89482728 ps
CPU time 3.93 seconds
Started May 04 03:35:03 PM PDT 24
Finished May 04 03:35:08 PM PDT 24
Peak memory 205448 kb
Host smart-e295fcb1-abfd-4af9-86c5-f44d0a78a833
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082876811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.4082876811
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3516580143
Short name T443
Test name
Test status
Simulation time 121157688 ps
CPU time 1.7 seconds
Started May 04 03:35:12 PM PDT 24
Finished May 04 03:35:15 PM PDT 24
Peak memory 214076 kb
Host smart-7eb4874d-99f2-4017-bf59-20fb9bad8df3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516580143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3516580143
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3828490141
Short name T431
Test name
Test status
Simulation time 361313353 ps
CPU time 5.74 seconds
Started May 04 03:35:03 PM PDT 24
Finished May 04 03:35:10 PM PDT 24
Peak memory 213980 kb
Host smart-b32f67c7-ebf1-482f-9342-d4dbe2f3dda2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828490141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3828490141
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1463700985
Short name T493
Test name
Test status
Simulation time 71945771 ps
CPU time 2.48 seconds
Started May 04 03:35:02 PM PDT 24
Finished May 04 03:35:05 PM PDT 24
Peak memory 213956 kb
Host smart-95355ab7-c7c3-4641-9071-044dc65ad076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463700985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1463700985
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1406964671
Short name T542
Test name
Test status
Simulation time 49169179 ps
CPU time 1.58 seconds
Started May 04 03:35:02 PM PDT 24
Finished May 04 03:35:04 PM PDT 24
Peak memory 205684 kb
Host smart-483deba7-42ac-4d63-ab5d-d975618158a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406964671 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1406964671
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3033887511
Short name T472
Test name
Test status
Simulation time 22681639 ps
CPU time 0.78 seconds
Started May 04 03:35:12 PM PDT 24
Finished May 04 03:35:14 PM PDT 24
Peak memory 205468 kb
Host smart-213ac3d4-3ed3-4e51-8ffc-d290f9b48af6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033887511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3033887511
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3521302775
Short name T468
Test name
Test status
Simulation time 130752311 ps
CPU time 1.97 seconds
Started May 04 03:35:02 PM PDT 24
Finished May 04 03:35:05 PM PDT 24
Peak memory 205604 kb
Host smart-91270776-69b8-4cbd-a5ee-23171d690014
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521302775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3521302775
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3000176923
Short name T503
Test name
Test status
Simulation time 117325510 ps
CPU time 2.64 seconds
Started May 04 03:35:03 PM PDT 24
Finished May 04 03:35:06 PM PDT 24
Peak memory 222216 kb
Host smart-d4717832-3d97-404a-ba8c-f67907618b6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000176923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3000176923
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2224309425
Short name T492
Test name
Test status
Simulation time 441492624 ps
CPU time 8.12 seconds
Started May 04 03:35:04 PM PDT 24
Finished May 04 03:35:13 PM PDT 24
Peak memory 214016 kb
Host smart-4b3f966c-ac46-408d-abef-509d60600a54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224309425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2224309425
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2151323945
Short name T177
Test name
Test status
Simulation time 136524704 ps
CPU time 2.18 seconds
Started May 04 03:35:04 PM PDT 24
Finished May 04 03:35:07 PM PDT 24
Peak memory 213796 kb
Host smart-8323fd4d-2398-45c4-a367-09fab020265b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151323945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2151323945
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1324490796
Short name T172
Test name
Test status
Simulation time 221126596 ps
CPU time 9.26 seconds
Started May 04 03:35:01 PM PDT 24
Finished May 04 03:35:11 PM PDT 24
Peak memory 213956 kb
Host smart-3a29cb78-0b2d-4297-935f-8e172f33c2fd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324490796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1324490796
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2838885066
Short name T127
Test name
Test status
Simulation time 37542014 ps
CPU time 2.61 seconds
Started May 04 03:35:02 PM PDT 24
Finished May 04 03:35:05 PM PDT 24
Peak memory 213952 kb
Host smart-9d68d8a7-f311-405a-931c-65df9269e3c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838885066 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2838885066
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.4110491147
Short name T526
Test name
Test status
Simulation time 61941494 ps
CPU time 1.16 seconds
Started May 04 03:35:07 PM PDT 24
Finished May 04 03:35:08 PM PDT 24
Peak memory 205504 kb
Host smart-f91399a0-ca7b-4853-b5fd-b4a9e924f917
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110491147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.4110491147
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.953246187
Short name T386
Test name
Test status
Simulation time 51794104 ps
CPU time 0.84 seconds
Started May 04 03:35:02 PM PDT 24
Finished May 04 03:35:04 PM PDT 24
Peak memory 205468 kb
Host smart-6142ac2b-10d2-4a30-a746-a9c098f2a827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953246187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.953246187
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.995960982
Short name T450
Test name
Test status
Simulation time 49692432 ps
CPU time 1.43 seconds
Started May 04 03:35:07 PM PDT 24
Finished May 04 03:35:09 PM PDT 24
Peak memory 205572 kb
Host smart-224fe3e9-cd02-4e4d-89d7-3f80d8275aef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995960982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.995960982
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2221440866
Short name T175
Test name
Test status
Simulation time 775871629 ps
CPU time 6.76 seconds
Started May 04 03:35:13 PM PDT 24
Finished May 04 03:35:20 PM PDT 24
Peak memory 222208 kb
Host smart-24c606c5-90f8-4476-878c-2cecfc53cd6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221440866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2221440866
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2442126473
Short name T461
Test name
Test status
Simulation time 746547937 ps
CPU time 8.43 seconds
Started May 04 03:35:02 PM PDT 24
Finished May 04 03:35:11 PM PDT 24
Peak memory 213988 kb
Host smart-c8793f3d-9052-44db-a206-29cf7183de2a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442126473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2442126473
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1771288452
Short name T516
Test name
Test status
Simulation time 27017790 ps
CPU time 2.14 seconds
Started May 04 03:35:03 PM PDT 24
Finished May 04 03:35:06 PM PDT 24
Peak memory 213888 kb
Host smart-a8a017a1-7ea0-4918-8b5e-0c788e7bd00c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771288452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1771288452
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3154328206
Short name T970
Test name
Test status
Simulation time 8135766 ps
CPU time 0.72 seconds
Started May 04 03:45:49 PM PDT 24
Finished May 04 03:45:50 PM PDT 24
Peak memory 205868 kb
Host smart-2e2d48a8-5cc6-4c5e-829c-db8cb397258b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154328206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3154328206
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.340698474
Short name T38
Test name
Test status
Simulation time 573590479 ps
CPU time 2.71 seconds
Started May 04 03:45:51 PM PDT 24
Finished May 04 03:45:54 PM PDT 24
Peak memory 222380 kb
Host smart-74026cf8-d974-44b3-9174-9ca5ff8a10e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340698474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.340698474
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3760000747
Short name T788
Test name
Test status
Simulation time 53179891 ps
CPU time 2.83 seconds
Started May 04 03:45:46 PM PDT 24
Finished May 04 03:45:49 PM PDT 24
Peak memory 210276 kb
Host smart-9035edca-a6a0-409b-84ef-78ea520bd9a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760000747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3760000747
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.4065836057
Short name T922
Test name
Test status
Simulation time 222507194 ps
CPU time 6.51 seconds
Started May 04 03:45:45 PM PDT 24
Finished May 04 03:45:52 PM PDT 24
Peak memory 208408 kb
Host smart-6718d394-eb31-4ba0-a9d3-70bdc656c735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065836057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.4065836057
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3420615406
Short name T295
Test name
Test status
Simulation time 249369769 ps
CPU time 4.06 seconds
Started May 04 03:45:50 PM PDT 24
Finished May 04 03:45:55 PM PDT 24
Peak memory 222412 kb
Host smart-682d3b0e-39c0-4541-b792-319acad1dd77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420615406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3420615406
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.96731213
Short name T405
Test name
Test status
Simulation time 95067944 ps
CPU time 3.27 seconds
Started May 04 03:45:45 PM PDT 24
Finished May 04 03:45:48 PM PDT 24
Peak memory 220036 kb
Host smart-ab24449d-8ff1-402e-afbb-117d2ecf1df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96731213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.96731213
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1937343746
Short name T618
Test name
Test status
Simulation time 257661749 ps
CPU time 4.03 seconds
Started May 04 03:45:46 PM PDT 24
Finished May 04 03:45:50 PM PDT 24
Peak memory 207832 kb
Host smart-241c0f74-456b-48d1-ac6c-0be76d48eeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937343746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1937343746
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1577453884
Short name T15
Test name
Test status
Simulation time 896929811 ps
CPU time 11.98 seconds
Started May 04 03:45:50 PM PDT 24
Finished May 04 03:46:03 PM PDT 24
Peak memory 237936 kb
Host smart-aa697c55-e7d5-411e-b538-212fe45c4b7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577453884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1577453884
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2741209127
Short name T689
Test name
Test status
Simulation time 379914305 ps
CPU time 5.08 seconds
Started May 04 03:45:40 PM PDT 24
Finished May 04 03:45:45 PM PDT 24
Peak memory 206756 kb
Host smart-b6aacabc-e674-4f4e-be90-d84ca2b0fad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741209127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2741209127
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.4159665863
Short name T768
Test name
Test status
Simulation time 3962363393 ps
CPU time 28.29 seconds
Started May 04 03:45:40 PM PDT 24
Finished May 04 03:46:09 PM PDT 24
Peak memory 208636 kb
Host smart-16e3d244-ed50-4db9-b02d-2e6d94d2b28b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159665863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.4159665863
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3630343635
Short name T667
Test name
Test status
Simulation time 38167922 ps
CPU time 2.58 seconds
Started May 04 03:45:39 PM PDT 24
Finished May 04 03:45:42 PM PDT 24
Peak memory 206892 kb
Host smart-6eb328e6-e1ac-4cf8-ba52-9c4e1c9886f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630343635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3630343635
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2267059152
Short name T310
Test name
Test status
Simulation time 214535925 ps
CPU time 2.86 seconds
Started May 04 03:45:39 PM PDT 24
Finished May 04 03:45:43 PM PDT 24
Peak memory 208828 kb
Host smart-1bbe290b-4c1c-4161-9a5d-93cf93e40c40
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267059152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2267059152
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.871857463
Short name T973
Test name
Test status
Simulation time 55094362 ps
CPU time 2.78 seconds
Started May 04 03:45:50 PM PDT 24
Finished May 04 03:45:53 PM PDT 24
Peak memory 209920 kb
Host smart-07ff79d2-8ede-4234-91e4-b6aeca6fe71a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871857463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.871857463
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1506270478
Short name T891
Test name
Test status
Simulation time 23342895 ps
CPU time 1.88 seconds
Started May 04 03:45:39 PM PDT 24
Finished May 04 03:45:41 PM PDT 24
Peak memory 207160 kb
Host smart-7db1fffa-93f7-4c2d-b1e3-d51c02093020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506270478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1506270478
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2623090065
Short name T82
Test name
Test status
Simulation time 5488330447 ps
CPU time 40.4 seconds
Started May 04 03:45:50 PM PDT 24
Finished May 04 03:46:31 PM PDT 24
Peak memory 221816 kb
Host smart-740e51db-cf2d-40de-93df-dfcfdcfbb59d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623090065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2623090065
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2906340018
Short name T715
Test name
Test status
Simulation time 465769799 ps
CPU time 4.69 seconds
Started May 04 03:45:51 PM PDT 24
Finished May 04 03:45:56 PM PDT 24
Peak memory 222616 kb
Host smart-f5b56768-dd68-4a70-a004-30d3585d722f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906340018 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2906340018
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.54810387
Short name T227
Test name
Test status
Simulation time 245089364 ps
CPU time 3.33 seconds
Started May 04 03:45:44 PM PDT 24
Finished May 04 03:45:48 PM PDT 24
Peak memory 209672 kb
Host smart-6f69d804-bc80-4b17-97f1-c2fb9f866c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54810387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.54810387
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.4265624430
Short name T800
Test name
Test status
Simulation time 70794642 ps
CPU time 2.98 seconds
Started May 04 03:45:50 PM PDT 24
Finished May 04 03:45:53 PM PDT 24
Peak memory 210260 kb
Host smart-1f3bcc0b-6f18-4a25-bdb3-fb70b8667bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265624430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.4265624430
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1447839569
Short name T702
Test name
Test status
Simulation time 79263261 ps
CPU time 1.02 seconds
Started May 04 03:46:05 PM PDT 24
Finished May 04 03:46:06 PM PDT 24
Peak memory 206024 kb
Host smart-81cc9205-2169-42d9-b8f0-b463083011a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447839569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1447839569
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2979656894
Short name T285
Test name
Test status
Simulation time 136747293 ps
CPU time 2.94 seconds
Started May 04 03:46:04 PM PDT 24
Finished May 04 03:46:08 PM PDT 24
Peak memory 215268 kb
Host smart-5b7165ef-09d1-4708-8201-e25337318b83
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2979656894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2979656894
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.750978490
Short name T1010
Test name
Test status
Simulation time 1143285044 ps
CPU time 27.7 seconds
Started May 04 03:46:05 PM PDT 24
Finished May 04 03:46:33 PM PDT 24
Peak memory 210116 kb
Host smart-1aa0ddfe-e90b-49cb-a190-b88d5907cfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750978490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.750978490
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.4294029339
Short name T1059
Test name
Test status
Simulation time 75848763 ps
CPU time 3.48 seconds
Started May 04 03:46:02 PM PDT 24
Finished May 04 03:46:06 PM PDT 24
Peak memory 218392 kb
Host smart-40b7e9ca-e5ea-4a97-8169-be9eb6b6e007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294029339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.4294029339
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.3942337275
Short name T22
Test name
Test status
Simulation time 162881299 ps
CPU time 5.46 seconds
Started May 04 03:46:02 PM PDT 24
Finished May 04 03:46:08 PM PDT 24
Peak memory 219164 kb
Host smart-64d56d66-e222-4caa-9d65-0c92d31fb1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942337275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.3942337275
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.4024253097
Short name T264
Test name
Test status
Simulation time 526279530 ps
CPU time 8.74 seconds
Started May 04 03:46:02 PM PDT 24
Finished May 04 03:46:11 PM PDT 24
Peak memory 209932 kb
Host smart-337f595f-7ed3-419f-bd42-5053ae3bf96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024253097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.4024253097
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_random.2016426644
Short name T868
Test name
Test status
Simulation time 188792811 ps
CPU time 3.24 seconds
Started May 04 03:46:05 PM PDT 24
Finished May 04 03:46:09 PM PDT 24
Peak memory 207476 kb
Host smart-198828ec-c790-42c7-ac8e-1f60d1f7b998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016426644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2016426644
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3217711103
Short name T14
Test name
Test status
Simulation time 2626129161 ps
CPU time 37.57 seconds
Started May 04 03:46:05 PM PDT 24
Finished May 04 03:46:43 PM PDT 24
Peak memory 235536 kb
Host smart-7dbb4021-314c-438b-a120-4cbb7bf4ce83
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217711103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3217711103
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1426803479
Short name T389
Test name
Test status
Simulation time 127448341 ps
CPU time 2.91 seconds
Started May 04 03:45:55 PM PDT 24
Finished May 04 03:45:58 PM PDT 24
Peak memory 206784 kb
Host smart-a3188242-8d55-47a7-a7aa-5619bc4a17e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426803479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1426803479
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1679643902
Short name T712
Test name
Test status
Simulation time 519883528 ps
CPU time 14.83 seconds
Started May 04 03:46:01 PM PDT 24
Finished May 04 03:46:17 PM PDT 24
Peak memory 208552 kb
Host smart-56bff5fc-b35d-43c2-8aa2-c3a108ed857a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679643902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1679643902
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.99601979
Short name T654
Test name
Test status
Simulation time 136581342 ps
CPU time 3.19 seconds
Started May 04 03:45:55 PM PDT 24
Finished May 04 03:45:58 PM PDT 24
Peak memory 206820 kb
Host smart-3d7db91d-2ea5-4dd6-a16b-a6aea41e9dcf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99601979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.99601979
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3803602053
Short name T242
Test name
Test status
Simulation time 354740791 ps
CPU time 5.66 seconds
Started May 04 03:46:00 PM PDT 24
Finished May 04 03:46:06 PM PDT 24
Peak memory 208828 kb
Host smart-79212006-b434-412f-8e67-2446ee545fbe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803602053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3803602053
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2381518561
Short name T415
Test name
Test status
Simulation time 50867335 ps
CPU time 1.81 seconds
Started May 04 03:46:05 PM PDT 24
Finished May 04 03:46:07 PM PDT 24
Peak memory 222400 kb
Host smart-284b7c3d-c919-4c80-97d0-9e65f0392380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381518561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2381518561
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2611127242
Short name T861
Test name
Test status
Simulation time 10269599264 ps
CPU time 35.17 seconds
Started May 04 03:45:56 PM PDT 24
Finished May 04 03:46:32 PM PDT 24
Peak memory 208164 kb
Host smart-22149ecc-02e6-4966-8533-4bd2ee9267ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611127242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2611127242
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2596830477
Short name T207
Test name
Test status
Simulation time 331608433 ps
CPU time 7.58 seconds
Started May 04 03:46:02 PM PDT 24
Finished May 04 03:46:10 PM PDT 24
Peak memory 222624 kb
Host smart-b2d20f52-8c00-4b96-a1a4-71eb58e379e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596830477 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2596830477
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.4273809372
Short name T784
Test name
Test status
Simulation time 1348418613 ps
CPU time 31.96 seconds
Started May 04 03:46:05 PM PDT 24
Finished May 04 03:46:37 PM PDT 24
Peak memory 218240 kb
Host smart-6e45b052-2df8-4459-a76a-fee178e7b84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273809372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.4273809372
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.743896987
Short name T856
Test name
Test status
Simulation time 44402384 ps
CPU time 1.7 seconds
Started May 04 03:46:01 PM PDT 24
Finished May 04 03:46:03 PM PDT 24
Peak memory 209848 kb
Host smart-deb84c7e-652b-45e3-bd2c-deb2e54ada77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743896987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.743896987
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3195622920
Short name T563
Test name
Test status
Simulation time 8131694 ps
CPU time 0.79 seconds
Started May 04 03:47:10 PM PDT 24
Finished May 04 03:47:12 PM PDT 24
Peak memory 205856 kb
Host smart-2315156d-e1b5-46a0-bab7-c103ea851a5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195622920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3195622920
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1748963564
Short name T421
Test name
Test status
Simulation time 109456770 ps
CPU time 2.46 seconds
Started May 04 03:47:07 PM PDT 24
Finished May 04 03:47:10 PM PDT 24
Peak memory 214340 kb
Host smart-e27b7bd0-d3dd-4149-9dce-eba734dfbebe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748963564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1748963564
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1155062135
Short name T32
Test name
Test status
Simulation time 1688879301 ps
CPU time 4.07 seconds
Started May 04 03:47:05 PM PDT 24
Finished May 04 03:47:09 PM PDT 24
Peak memory 210156 kb
Host smart-e9c4076f-01c0-45b1-80a6-7650f44575a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155062135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1155062135
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.663158338
Short name T851
Test name
Test status
Simulation time 248049667 ps
CPU time 4.86 seconds
Started May 04 03:47:09 PM PDT 24
Finished May 04 03:47:15 PM PDT 24
Peak memory 209272 kb
Host smart-46358ca6-87ca-4826-b65c-194e993d7326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663158338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.663158338
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1298261095
Short name T612
Test name
Test status
Simulation time 87130610 ps
CPU time 3.99 seconds
Started May 04 03:47:04 PM PDT 24
Finished May 04 03:47:08 PM PDT 24
Peak memory 208188 kb
Host smart-001c03bc-b06a-4a2f-8015-5d1166487c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298261095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1298261095
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3748773873
Short name T1027
Test name
Test status
Simulation time 184285869 ps
CPU time 3.26 seconds
Started May 04 03:47:05 PM PDT 24
Finished May 04 03:47:09 PM PDT 24
Peak memory 214224 kb
Host smart-7dbf309d-814d-4c64-9cd7-313d69fc5dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748773873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3748773873
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3277558172
Short name T256
Test name
Test status
Simulation time 312402477 ps
CPU time 8.76 seconds
Started May 04 03:47:06 PM PDT 24
Finished May 04 03:47:16 PM PDT 24
Peak memory 218424 kb
Host smart-fc0afcea-557c-41a6-b8ef-8fa1691f92d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277558172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3277558172
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.192134969
Short name T279
Test name
Test status
Simulation time 123740410 ps
CPU time 3.97 seconds
Started May 04 03:47:04 PM PDT 24
Finished May 04 03:47:08 PM PDT 24
Peak memory 206788 kb
Host smart-4bcfcc12-d7a2-48bd-9f62-63e7d3b40539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192134969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.192134969
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3295859297
Short name T845
Test name
Test status
Simulation time 37461530 ps
CPU time 2.58 seconds
Started May 04 03:47:04 PM PDT 24
Finished May 04 03:47:07 PM PDT 24
Peak memory 207400 kb
Host smart-6f3b8064-dd18-4903-9168-f9cda804bb31
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295859297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3295859297
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.4207542458
Short name T1064
Test name
Test status
Simulation time 53828475 ps
CPU time 2.83 seconds
Started May 04 03:47:06 PM PDT 24
Finished May 04 03:47:09 PM PDT 24
Peak memory 206984 kb
Host smart-985fecee-62cd-4b79-be15-21e5c914e8ae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207542458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.4207542458
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2759539255
Short name T298
Test name
Test status
Simulation time 1559527641 ps
CPU time 38.4 seconds
Started May 04 03:47:04 PM PDT 24
Finished May 04 03:47:43 PM PDT 24
Peak memory 208640 kb
Host smart-e3434127-950f-4047-b29d-bdb66eb64055
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759539255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2759539255
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.4194492594
Short name T642
Test name
Test status
Simulation time 34735475 ps
CPU time 2.42 seconds
Started May 04 03:47:07 PM PDT 24
Finished May 04 03:47:10 PM PDT 24
Peak memory 207988 kb
Host smart-225902c6-a8ca-4092-9f28-be98ddde5ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194492594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.4194492594
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.369456502
Short name T946
Test name
Test status
Simulation time 535453747 ps
CPU time 16.8 seconds
Started May 04 03:47:05 PM PDT 24
Finished May 04 03:47:23 PM PDT 24
Peak memory 208372 kb
Host smart-4aefdbf4-9c85-4f95-90bf-9cbf03dcc4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369456502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.369456502
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1296486965
Short name T1029
Test name
Test status
Simulation time 181162952 ps
CPU time 8.84 seconds
Started May 04 03:47:09 PM PDT 24
Finished May 04 03:47:18 PM PDT 24
Peak memory 222616 kb
Host smart-9752195d-4d12-4e29-910c-cb783e440b46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296486965 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1296486965
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.81357668
Short name T302
Test name
Test status
Simulation time 122438338 ps
CPU time 5.5 seconds
Started May 04 03:47:05 PM PDT 24
Finished May 04 03:47:11 PM PDT 24
Peak memory 209676 kb
Host smart-02f3a44f-4c45-4f9b-b890-45c3c5bfe7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81357668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.81357668
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.533678092
Short name T806
Test name
Test status
Simulation time 299001067 ps
CPU time 2.55 seconds
Started May 04 03:47:10 PM PDT 24
Finished May 04 03:47:13 PM PDT 24
Peak memory 210320 kb
Host smart-04fd577a-cf5b-477f-b2a7-69b10d34f7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533678092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.533678092
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1475210336
Short name T639
Test name
Test status
Simulation time 39257699 ps
CPU time 0.83 seconds
Started May 04 03:47:16 PM PDT 24
Finished May 04 03:47:17 PM PDT 24
Peak memory 205856 kb
Host smart-5a58e9c7-0172-4764-88b2-fd86891c3a36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475210336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1475210336
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.528809783
Short name T422
Test name
Test status
Simulation time 105848426 ps
CPU time 2.9 seconds
Started May 04 03:47:10 PM PDT 24
Finished May 04 03:47:13 PM PDT 24
Peak memory 214304 kb
Host smart-b2c94081-9efa-434a-b46f-81cd6d7f8193
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=528809783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.528809783
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.942411630
Short name T744
Test name
Test status
Simulation time 241794636 ps
CPU time 3.43 seconds
Started May 04 03:47:10 PM PDT 24
Finished May 04 03:47:14 PM PDT 24
Peak memory 218216 kb
Host smart-6078f075-c1b1-4e64-850a-886f19dbd283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942411630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.942411630
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1308206496
Short name T986
Test name
Test status
Simulation time 56036934 ps
CPU time 3.55 seconds
Started May 04 03:47:16 PM PDT 24
Finished May 04 03:47:20 PM PDT 24
Peak memory 214296 kb
Host smart-ec423458-ebe0-4091-94dc-511bcdf03684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308206496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1308206496
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2243393601
Short name T39
Test name
Test status
Simulation time 3792254743 ps
CPU time 75.81 seconds
Started May 04 03:47:16 PM PDT 24
Finished May 04 03:48:33 PM PDT 24
Peak memory 219460 kb
Host smart-dbc7dec8-c121-48be-af9d-0f04f6218940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243393601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2243393601
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.4131636194
Short name T218
Test name
Test status
Simulation time 235291066 ps
CPU time 4.83 seconds
Started May 04 03:47:14 PM PDT 24
Finished May 04 03:47:19 PM PDT 24
Peak memory 214360 kb
Host smart-8f205772-ea3e-44d9-8659-76dda5980976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131636194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.4131636194
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.759558931
Short name T633
Test name
Test status
Simulation time 99861906 ps
CPU time 5.15 seconds
Started May 04 03:47:11 PM PDT 24
Finished May 04 03:47:16 PM PDT 24
Peak memory 209324 kb
Host smart-49a7defb-93bd-4764-aea4-5e3ed72527a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759558931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.759558931
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3892346771
Short name T309
Test name
Test status
Simulation time 231572406 ps
CPU time 5.13 seconds
Started May 04 03:47:11 PM PDT 24
Finished May 04 03:47:16 PM PDT 24
Peak memory 208492 kb
Host smart-899928f2-ecb5-4fa5-bee9-9541e4258498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892346771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3892346771
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3246013860
Short name T643
Test name
Test status
Simulation time 111253798 ps
CPU time 3.8 seconds
Started May 04 03:47:14 PM PDT 24
Finished May 04 03:47:18 PM PDT 24
Peak memory 206832 kb
Host smart-29b37698-9cef-4bb5-8b45-bf9c11eedd7c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246013860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3246013860
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.609876185
Short name T697
Test name
Test status
Simulation time 19635872 ps
CPU time 1.8 seconds
Started May 04 03:47:10 PM PDT 24
Finished May 04 03:47:12 PM PDT 24
Peak memory 206940 kb
Host smart-6020c473-2294-4921-8bcf-1c3db22d8c52
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609876185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.609876185
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3027049554
Short name T327
Test name
Test status
Simulation time 138730072 ps
CPU time 5.48 seconds
Started May 04 03:47:14 PM PDT 24
Finished May 04 03:47:20 PM PDT 24
Peak memory 206932 kb
Host smart-db897eca-8d5c-4152-bc67-f391e5b40a71
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027049554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3027049554
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3037797257
Short name T232
Test name
Test status
Simulation time 706078504 ps
CPU time 5.49 seconds
Started May 04 03:47:15 PM PDT 24
Finished May 04 03:47:21 PM PDT 24
Peak memory 209732 kb
Host smart-0f916ff9-e984-4396-9bff-026c842cbc98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037797257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3037797257
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.3454087801
Short name T980
Test name
Test status
Simulation time 54509041 ps
CPU time 2.53 seconds
Started May 04 03:47:10 PM PDT 24
Finished May 04 03:47:13 PM PDT 24
Peak memory 207792 kb
Host smart-990393e9-472d-4032-bb51-7f75e06fd8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454087801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.3454087801
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1485721648
Short name T72
Test name
Test status
Simulation time 286251225 ps
CPU time 11.75 seconds
Started May 04 03:47:15 PM PDT 24
Finished May 04 03:47:27 PM PDT 24
Peak memory 222644 kb
Host smart-dc93a10a-b572-4384-abbb-f440db0154ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485721648 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1485721648
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.684374289
Short name T1006
Test name
Test status
Simulation time 426476181 ps
CPU time 5.26 seconds
Started May 04 03:47:10 PM PDT 24
Finished May 04 03:47:16 PM PDT 24
Peak memory 218292 kb
Host smart-8598b25b-ad1f-478d-a809-d85752e7915c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684374289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.684374289
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2732207186
Short name T166
Test name
Test status
Simulation time 95701293 ps
CPU time 3.9 seconds
Started May 04 03:47:15 PM PDT 24
Finished May 04 03:47:20 PM PDT 24
Peak memory 210236 kb
Host smart-0a6b6d73-1f9c-4cd6-ae0f-3cfeb8d9f78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732207186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2732207186
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2741584542
Short name T996
Test name
Test status
Simulation time 72796963 ps
CPU time 0.75 seconds
Started May 04 03:47:29 PM PDT 24
Finished May 04 03:47:30 PM PDT 24
Peak memory 205856 kb
Host smart-53794618-76b2-40d5-b824-15495be0d020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741584542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2741584542
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1634362654
Short name T359
Test name
Test status
Simulation time 1818446574 ps
CPU time 61.11 seconds
Started May 04 03:47:26 PM PDT 24
Finished May 04 03:48:27 PM PDT 24
Peak memory 214312 kb
Host smart-a4176cd5-8a0c-4627-ab1d-1ac1ea33a5df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1634362654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1634362654
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3272445897
Short name T879
Test name
Test status
Simulation time 195523281 ps
CPU time 4.84 seconds
Started May 04 03:47:26 PM PDT 24
Finished May 04 03:47:32 PM PDT 24
Peak memory 222868 kb
Host smart-77212c16-42f6-4c75-9558-bc00c8fe5bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272445897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3272445897
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1888903004
Short name T646
Test name
Test status
Simulation time 119673771 ps
CPU time 3.48 seconds
Started May 04 03:47:21 PM PDT 24
Finished May 04 03:47:26 PM PDT 24
Peak memory 209676 kb
Host smart-1759e5c6-aa78-4dd8-a505-eaf487062198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888903004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1888903004
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.272742653
Short name T916
Test name
Test status
Simulation time 125255813 ps
CPU time 4.72 seconds
Started May 04 03:47:22 PM PDT 24
Finished May 04 03:47:27 PM PDT 24
Peak memory 208764 kb
Host smart-b211f2dc-f5a7-486c-9d7c-14cf13b0d042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272742653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.272742653
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.1480464148
Short name T734
Test name
Test status
Simulation time 163540945 ps
CPU time 4.28 seconds
Started May 04 03:47:23 PM PDT 24
Finished May 04 03:47:27 PM PDT 24
Peak memory 208628 kb
Host smart-4fbc6646-2adc-41d4-9f2a-4252fd7b5983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480464148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.1480464148
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2150177931
Short name T799
Test name
Test status
Simulation time 103925967 ps
CPU time 4.92 seconds
Started May 04 03:47:22 PM PDT 24
Finished May 04 03:47:27 PM PDT 24
Peak memory 209692 kb
Host smart-0a67f5df-ee22-43d1-9f2d-cef19872769e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150177931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2150177931
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1308442896
Short name T816
Test name
Test status
Simulation time 67015391 ps
CPU time 2.98 seconds
Started May 04 03:47:21 PM PDT 24
Finished May 04 03:47:24 PM PDT 24
Peak memory 206912 kb
Host smart-7a7b04c6-c03f-4abd-b5c2-2c65cb73f81b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308442896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1308442896
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1540970928
Short name T819
Test name
Test status
Simulation time 1408203589 ps
CPU time 4.83 seconds
Started May 04 03:47:21 PM PDT 24
Finished May 04 03:47:27 PM PDT 24
Peak memory 208688 kb
Host smart-4f6dd5f0-cf43-464b-a1a5-b7e8a0f33aca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540970928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1540970928
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.416601217
Short name T876
Test name
Test status
Simulation time 540940280 ps
CPU time 3.58 seconds
Started May 04 03:47:27 PM PDT 24
Finished May 04 03:47:31 PM PDT 24
Peak memory 208072 kb
Host smart-68601700-eb00-4d05-8240-16cab25f05df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416601217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.416601217
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1330286470
Short name T659
Test name
Test status
Simulation time 3192022794 ps
CPU time 68.65 seconds
Started May 04 03:47:15 PM PDT 24
Finished May 04 03:48:24 PM PDT 24
Peak memory 208668 kb
Host smart-9dcf1072-ae3c-436b-a78b-00510d2cf794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330286470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1330286470
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.4200917267
Short name T588
Test name
Test status
Simulation time 202749591 ps
CPU time 5.55 seconds
Started May 04 03:47:29 PM PDT 24
Finished May 04 03:47:35 PM PDT 24
Peak memory 207756 kb
Host smart-c90c1983-14ec-4385-9db2-82ae07783d37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200917267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.4200917267
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2136040430
Short name T619
Test name
Test status
Simulation time 274000607 ps
CPU time 6.22 seconds
Started May 04 03:47:28 PM PDT 24
Finished May 04 03:47:35 PM PDT 24
Peak memory 223328 kb
Host smart-5d4131b9-270d-485a-9f72-da8000a9ea3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136040430 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2136040430
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.774132881
Short name T352
Test name
Test status
Simulation time 771818428 ps
CPU time 8.71 seconds
Started May 04 03:47:21 PM PDT 24
Finished May 04 03:47:31 PM PDT 24
Peak memory 214400 kb
Host smart-a1b0142c-6107-4e8f-9806-e7607c59c7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774132881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.774132881
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.692678196
Short name T571
Test name
Test status
Simulation time 250009458 ps
CPU time 2.78 seconds
Started May 04 03:47:26 PM PDT 24
Finished May 04 03:47:30 PM PDT 24
Peak memory 210396 kb
Host smart-5b942b2a-e96e-4f2a-bc33-31dc1fc435e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692678196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.692678196
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.744307573
Short name T1008
Test name
Test status
Simulation time 15768082 ps
CPU time 0.97 seconds
Started May 04 03:47:33 PM PDT 24
Finished May 04 03:47:34 PM PDT 24
Peak memory 206032 kb
Host smart-6d35f390-8023-4876-afd8-e1f6b09c3d5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744307573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.744307573
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1477644283
Short name T26
Test name
Test status
Simulation time 73750157 ps
CPU time 3.25 seconds
Started May 04 03:47:29 PM PDT 24
Finished May 04 03:47:32 PM PDT 24
Peak memory 208784 kb
Host smart-d742f548-e933-4d0c-afed-a6ee9d0fa4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477644283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1477644283
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3641768145
Short name T47
Test name
Test status
Simulation time 454509272 ps
CPU time 3.53 seconds
Started May 04 03:47:26 PM PDT 24
Finished May 04 03:47:31 PM PDT 24
Peak memory 209312 kb
Host smart-36b9afca-81e3-4939-b3a8-1a44669b5ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641768145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3641768145
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.4187189756
Short name T967
Test name
Test status
Simulation time 1503428106 ps
CPU time 9.07 seconds
Started May 04 03:47:29 PM PDT 24
Finished May 04 03:47:38 PM PDT 24
Peak memory 208736 kb
Host smart-ddbb7ea5-c814-4ce1-b7b6-4a16951fd88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187189756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.4187189756
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.4080947153
Short name T818
Test name
Test status
Simulation time 228043182 ps
CPU time 4.35 seconds
Started May 04 03:47:26 PM PDT 24
Finished May 04 03:47:32 PM PDT 24
Peak memory 211036 kb
Host smart-cf972e78-f193-4b4e-9c43-5b2c49a99d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080947153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.4080947153
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.4284378097
Short name T900
Test name
Test status
Simulation time 134910501 ps
CPU time 3.5 seconds
Started May 04 03:47:26 PM PDT 24
Finished May 04 03:47:30 PM PDT 24
Peak memory 209672 kb
Host smart-2d03a0f5-d1aa-4ab1-987a-aa9115c1fbb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284378097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.4284378097
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2285931494
Short name T711
Test name
Test status
Simulation time 858994460 ps
CPU time 7.87 seconds
Started May 04 03:47:27 PM PDT 24
Finished May 04 03:47:35 PM PDT 24
Peak memory 208944 kb
Host smart-2cea85c5-38d2-4da7-bf01-9480b06b7ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285931494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2285931494
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2548624985
Short name T380
Test name
Test status
Simulation time 120960506 ps
CPU time 2.35 seconds
Started May 04 03:47:28 PM PDT 24
Finished May 04 03:47:31 PM PDT 24
Peak memory 208560 kb
Host smart-ced04656-d870-4f1d-9b35-5d57f059d450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548624985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2548624985
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3907001081
Short name T903
Test name
Test status
Simulation time 36821534 ps
CPU time 2.48 seconds
Started May 04 03:47:28 PM PDT 24
Finished May 04 03:47:31 PM PDT 24
Peak memory 207248 kb
Host smart-79832e76-f4f3-4830-8f9d-e5c7c3bc178d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907001081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3907001081
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1816759216
Short name T894
Test name
Test status
Simulation time 149476084 ps
CPU time 3.38 seconds
Started May 04 03:47:27 PM PDT 24
Finished May 04 03:47:31 PM PDT 24
Peak memory 208768 kb
Host smart-e2a54fa8-2f40-4548-9c67-06a047bd26e8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816759216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1816759216
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.422353410
Short name T966
Test name
Test status
Simulation time 380772764 ps
CPU time 4.14 seconds
Started May 04 03:47:26 PM PDT 24
Finished May 04 03:47:32 PM PDT 24
Peak memory 206924 kb
Host smart-68330b22-e3b0-45cb-931c-892efdf48862
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422353410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.422353410
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3222645072
Short name T972
Test name
Test status
Simulation time 1164217853 ps
CPU time 12.34 seconds
Started May 04 03:47:28 PM PDT 24
Finished May 04 03:47:41 PM PDT 24
Peak memory 208140 kb
Host smart-f6bba96e-9b5c-4058-8a3a-ad2392d360b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222645072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3222645072
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.768718980
Short name T589
Test name
Test status
Simulation time 59146493 ps
CPU time 2.95 seconds
Started May 04 03:47:26 PM PDT 24
Finished May 04 03:47:29 PM PDT 24
Peak memory 206780 kb
Host smart-6ba74c51-8496-4168-bd71-83e4fc988ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768718980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.768718980
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2072273211
Short name T243
Test name
Test status
Simulation time 6333351323 ps
CPU time 64.94 seconds
Started May 04 03:47:38 PM PDT 24
Finished May 04 03:48:44 PM PDT 24
Peak memory 216268 kb
Host smart-1061ac9e-2611-4e02-b80f-e40511a524c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072273211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2072273211
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.4071838550
Short name T770
Test name
Test status
Simulation time 187876777 ps
CPU time 7.05 seconds
Started May 04 03:47:31 PM PDT 24
Finished May 04 03:47:39 PM PDT 24
Peak memory 219676 kb
Host smart-cd5e0735-46d3-44ad-b430-104390591f13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071838550 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.4071838550
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3033093365
Short name T381
Test name
Test status
Simulation time 1311387683 ps
CPU time 33.36 seconds
Started May 04 03:47:27 PM PDT 24
Finished May 04 03:48:01 PM PDT 24
Peak memory 217844 kb
Host smart-9c961319-dee6-476a-8271-f4f0d4ead57e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033093365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3033093365
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2193769926
Short name T686
Test name
Test status
Simulation time 145272911 ps
CPU time 0.76 seconds
Started May 04 03:47:42 PM PDT 24
Finished May 04 03:47:43 PM PDT 24
Peak memory 205748 kb
Host smart-34c05680-9460-434c-9dc8-15037559e111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193769926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2193769926
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2745851344
Short name T109
Test name
Test status
Simulation time 227453779 ps
CPU time 10.93 seconds
Started May 04 03:47:32 PM PDT 24
Finished May 04 03:47:44 PM PDT 24
Peak memory 215516 kb
Host smart-aad4cfc4-6361-448b-a97f-70e8036e2028
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2745851344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2745851344
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2973400560
Short name T772
Test name
Test status
Simulation time 120589221 ps
CPU time 3.28 seconds
Started May 04 03:47:32 PM PDT 24
Finished May 04 03:47:36 PM PDT 24
Peak memory 207588 kb
Host smart-7fe0bf38-982d-488a-8550-d02d0f79dbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973400560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2973400560
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.4136709832
Short name T263
Test name
Test status
Simulation time 352229407 ps
CPU time 14.93 seconds
Started May 04 03:47:32 PM PDT 24
Finished May 04 03:47:48 PM PDT 24
Peak memory 222400 kb
Host smart-441f17fb-9105-467e-868e-87b4223913df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136709832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4136709832
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.805204081
Short name T220
Test name
Test status
Simulation time 232147767 ps
CPU time 4.51 seconds
Started May 04 03:47:38 PM PDT 24
Finished May 04 03:47:43 PM PDT 24
Peak memory 220396 kb
Host smart-913854de-7546-4eb9-a1bf-959a41504050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805204081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.805204081
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3497008341
Short name T714
Test name
Test status
Simulation time 764485308 ps
CPU time 5.57 seconds
Started May 04 03:47:33 PM PDT 24
Finished May 04 03:47:39 PM PDT 24
Peak memory 207980 kb
Host smart-eb1cb078-dd11-4834-b738-b076dabd3781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497008341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3497008341
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1789288441
Short name T873
Test name
Test status
Simulation time 65521923 ps
CPU time 2.27 seconds
Started May 04 03:47:40 PM PDT 24
Finished May 04 03:47:43 PM PDT 24
Peak memory 207596 kb
Host smart-f15e4a2a-706e-45bf-a8c4-d5a8eda040e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789288441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1789288441
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3047714257
Short name T955
Test name
Test status
Simulation time 432294656 ps
CPU time 3.38 seconds
Started May 04 03:47:33 PM PDT 24
Finished May 04 03:47:37 PM PDT 24
Peak memory 208700 kb
Host smart-396aed1d-731d-4d4f-b3f0-5dbb8a1d644c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047714257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3047714257
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.193133772
Short name T4
Test name
Test status
Simulation time 40444594 ps
CPU time 2.29 seconds
Started May 04 03:47:31 PM PDT 24
Finished May 04 03:47:34 PM PDT 24
Peak memory 206892 kb
Host smart-ee2a6e5f-efbe-4cee-b8ea-da4ab3b83281
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193133772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.193133772
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3004801860
Short name T871
Test name
Test status
Simulation time 220919987 ps
CPU time 4.16 seconds
Started May 04 03:47:37 PM PDT 24
Finished May 04 03:47:41 PM PDT 24
Peak memory 208332 kb
Host smart-b4f81e28-b2e0-49fa-bb37-558cc320cfc6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004801860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3004801860
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.415382713
Short name T951
Test name
Test status
Simulation time 42970151 ps
CPU time 2.84 seconds
Started May 04 03:47:33 PM PDT 24
Finished May 04 03:47:37 PM PDT 24
Peak memory 209964 kb
Host smart-c9bedeb0-ad61-4aad-bfc1-a98824fbc9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415382713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.415382713
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3456653343
Short name T402
Test name
Test status
Simulation time 90332892 ps
CPU time 3.23 seconds
Started May 04 03:47:32 PM PDT 24
Finished May 04 03:47:36 PM PDT 24
Peak memory 206608 kb
Host smart-39b2b37c-7338-430f-b954-dd94570c1797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456653343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3456653343
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.84057184
Short name T305
Test name
Test status
Simulation time 155331058 ps
CPU time 6.94 seconds
Started May 04 03:47:35 PM PDT 24
Finished May 04 03:47:42 PM PDT 24
Peak memory 222496 kb
Host smart-4c2ffca4-8e55-4e48-b24a-0a5d99f52dbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84057184 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.84057184
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3461142217
Short name T1023
Test name
Test status
Simulation time 239467417 ps
CPU time 4.25 seconds
Started May 04 03:47:34 PM PDT 24
Finished May 04 03:47:39 PM PDT 24
Peak memory 209204 kb
Host smart-d70c38f2-b4b4-47c8-a99a-b7a683d6b06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461142217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3461142217
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3688334682
Short name T929
Test name
Test status
Simulation time 40362781 ps
CPU time 0.89 seconds
Started May 04 03:47:39 PM PDT 24
Finished May 04 03:47:41 PM PDT 24
Peak memory 205836 kb
Host smart-4288192b-e62f-4ebc-aba3-101d47b4098b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688334682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3688334682
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1428831281
Short name T943
Test name
Test status
Simulation time 138452187 ps
CPU time 3.61 seconds
Started May 04 03:47:39 PM PDT 24
Finished May 04 03:47:44 PM PDT 24
Peak memory 214232 kb
Host smart-d5feaa21-d257-47cc-b6e2-be5c6d480e23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1428831281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1428831281
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1405443826
Short name T78
Test name
Test status
Simulation time 2446056820 ps
CPU time 15.68 seconds
Started May 04 03:47:40 PM PDT 24
Finished May 04 03:47:56 PM PDT 24
Peak memory 208788 kb
Host smart-cb43d34d-5492-485e-a917-472c42d707dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405443826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1405443826
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2309489497
Short name T92
Test name
Test status
Simulation time 1097658556 ps
CPU time 4.58 seconds
Started May 04 03:47:40 PM PDT 24
Finished May 04 03:47:45 PM PDT 24
Peak memory 219976 kb
Host smart-13bf44c7-528f-4b86-94db-97da03ef3bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309489497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2309489497
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2536181911
Short name T234
Test name
Test status
Simulation time 2540405926 ps
CPU time 8.78 seconds
Started May 04 03:47:41 PM PDT 24
Finished May 04 03:47:50 PM PDT 24
Peak memory 211028 kb
Host smart-ccdb5d2f-4aa3-45d4-84d8-a0aefa92d7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536181911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2536181911
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2098611676
Short name T790
Test name
Test status
Simulation time 332845519 ps
CPU time 3.2 seconds
Started May 04 03:47:38 PM PDT 24
Finished May 04 03:47:42 PM PDT 24
Peak memory 214304 kb
Host smart-adb2258f-962d-479c-bce8-e860794eef50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098611676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2098611676
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.501556006
Short name T1056
Test name
Test status
Simulation time 848048404 ps
CPU time 26.38 seconds
Started May 04 03:47:39 PM PDT 24
Finished May 04 03:48:06 PM PDT 24
Peak memory 208556 kb
Host smart-f2790421-a1b9-4721-9f25-5ecfe97b13b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501556006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.501556006
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1347320291
Short name T923
Test name
Test status
Simulation time 829194557 ps
CPU time 4.19 seconds
Started May 04 03:47:39 PM PDT 24
Finished May 04 03:47:44 PM PDT 24
Peak memory 207428 kb
Host smart-77471a91-ad59-44ec-945a-de9a8025abc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347320291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1347320291
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2739230647
Short name T709
Test name
Test status
Simulation time 213970956 ps
CPU time 4.03 seconds
Started May 04 03:47:40 PM PDT 24
Finished May 04 03:47:45 PM PDT 24
Peak memory 206896 kb
Host smart-0822592c-d3b2-4980-b2f4-7207b5552475
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739230647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2739230647
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3634888852
Short name T743
Test name
Test status
Simulation time 104059826 ps
CPU time 4.11 seconds
Started May 04 03:47:38 PM PDT 24
Finished May 04 03:47:43 PM PDT 24
Peak memory 206824 kb
Host smart-5c11fcf0-e572-4495-bf62-8a6c8575dc96
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634888852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3634888852
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.111236913
Short name T985
Test name
Test status
Simulation time 49884639 ps
CPU time 2.98 seconds
Started May 04 03:47:39 PM PDT 24
Finished May 04 03:47:43 PM PDT 24
Peak memory 207236 kb
Host smart-7a395a41-4490-4d8e-9041-6c8193f5be12
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111236913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.111236913
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1250634467
Short name T783
Test name
Test status
Simulation time 1308532441 ps
CPU time 12.3 seconds
Started May 04 03:47:39 PM PDT 24
Finished May 04 03:47:52 PM PDT 24
Peak memory 209040 kb
Host smart-26430d2f-8e74-401a-b2b9-17e88c65cbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250634467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1250634467
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3269859834
Short name T637
Test name
Test status
Simulation time 40244374 ps
CPU time 2.37 seconds
Started May 04 03:47:40 PM PDT 24
Finished May 04 03:47:43 PM PDT 24
Peak memory 207216 kb
Host smart-ecfca32b-fb83-4444-b262-d050754d27df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269859834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3269859834
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.3990925677
Short name T1039
Test name
Test status
Simulation time 192771293 ps
CPU time 4.25 seconds
Started May 04 03:47:41 PM PDT 24
Finished May 04 03:47:45 PM PDT 24
Peak memory 214376 kb
Host smart-37b9d880-45bf-4d7d-ac25-906e27195a4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990925677 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.3990925677
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1820819786
Short name T940
Test name
Test status
Simulation time 80927342 ps
CPU time 4.17 seconds
Started May 04 03:47:42 PM PDT 24
Finished May 04 03:47:46 PM PDT 24
Peak memory 209292 kb
Host smart-a87496b1-bd17-4580-90de-21c495699a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820819786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1820819786
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.756938128
Short name T1058
Test name
Test status
Simulation time 267692492 ps
CPU time 2.12 seconds
Started May 04 03:47:40 PM PDT 24
Finished May 04 03:47:43 PM PDT 24
Peak memory 209988 kb
Host smart-bb8293a8-8303-4c93-9c19-1741fdeda0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756938128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.756938128
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3912089839
Short name T842
Test name
Test status
Simulation time 11545133 ps
CPU time 0.74 seconds
Started May 04 03:47:48 PM PDT 24
Finished May 04 03:47:49 PM PDT 24
Peak memory 205868 kb
Host smart-728f7aeb-0a68-4c90-b41c-1074b57facbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912089839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3912089839
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3047161270
Short name T399
Test name
Test status
Simulation time 305012740 ps
CPU time 3.16 seconds
Started May 04 03:47:44 PM PDT 24
Finished May 04 03:47:48 PM PDT 24
Peak memory 214252 kb
Host smart-8f87f0d3-51d8-484e-b4a3-7087e0d6e610
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3047161270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3047161270
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3625234772
Short name T984
Test name
Test status
Simulation time 889764995 ps
CPU time 24.76 seconds
Started May 04 03:47:57 PM PDT 24
Finished May 04 03:48:23 PM PDT 24
Peak memory 222892 kb
Host smart-e3f08be9-eb5f-42a0-9578-38aaf46840de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625234772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3625234772
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.4138292647
Short name T390
Test name
Test status
Simulation time 45099031 ps
CPU time 2.41 seconds
Started May 04 03:47:57 PM PDT 24
Finished May 04 03:48:00 PM PDT 24
Peak memory 208680 kb
Host smart-5073563e-d0e6-4f50-b8dc-0b64268a1bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138292647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.4138292647
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2189485547
Short name T640
Test name
Test status
Simulation time 1242677663 ps
CPU time 13.29 seconds
Started May 04 03:47:46 PM PDT 24
Finished May 04 03:48:00 PM PDT 24
Peak memory 208924 kb
Host smart-7a3d4b63-19e5-4d55-aabb-7b99197cbe54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189485547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2189485547
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3233580895
Short name T803
Test name
Test status
Simulation time 71404952 ps
CPU time 3.85 seconds
Started May 04 03:47:45 PM PDT 24
Finished May 04 03:47:49 PM PDT 24
Peak memory 208952 kb
Host smart-da1ce9ce-c7f7-49df-b9e1-b6a583e8ddba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233580895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3233580895
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3316620295
Short name T964
Test name
Test status
Simulation time 35463872 ps
CPU time 1.69 seconds
Started May 04 03:47:47 PM PDT 24
Finished May 04 03:47:49 PM PDT 24
Peak memory 206900 kb
Host smart-a6dc28af-e013-4e7c-acaf-8d96d10c63a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316620295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3316620295
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3018997521
Short name T241
Test name
Test status
Simulation time 153682019 ps
CPU time 6.52 seconds
Started May 04 03:47:44 PM PDT 24
Finished May 04 03:47:51 PM PDT 24
Peak memory 208636 kb
Host smart-c5d1c2cb-b5a0-47f7-b095-a172ff95f7c5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018997521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3018997521
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.178878038
Short name T662
Test name
Test status
Simulation time 274757488 ps
CPU time 3.92 seconds
Started May 04 03:47:47 PM PDT 24
Finished May 04 03:47:51 PM PDT 24
Peak memory 208680 kb
Host smart-ebb389b2-325a-4af4-ad75-5aad88860fb9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178878038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.178878038
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3020018949
Short name T696
Test name
Test status
Simulation time 501506389 ps
CPU time 14.27 seconds
Started May 04 03:47:48 PM PDT 24
Finished May 04 03:48:02 PM PDT 24
Peak memory 208668 kb
Host smart-9e6cadaf-9c23-4e58-b3c9-3d704681a814
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020018949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3020018949
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3143985356
Short name T426
Test name
Test status
Simulation time 101323856 ps
CPU time 2.09 seconds
Started May 04 03:47:48 PM PDT 24
Finished May 04 03:47:50 PM PDT 24
Peak memory 207980 kb
Host smart-639d7793-91f6-454f-9945-9beb903b5245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143985356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3143985356
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3084870902
Short name T587
Test name
Test status
Simulation time 44912356 ps
CPU time 2.62 seconds
Started May 04 03:47:39 PM PDT 24
Finished May 04 03:47:43 PM PDT 24
Peak memory 208184 kb
Host smart-d650c333-f2d6-4358-8438-98eb7c417dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084870902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3084870902
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1313031419
Short name T280
Test name
Test status
Simulation time 435125332 ps
CPU time 12.15 seconds
Started May 04 03:47:46 PM PDT 24
Finished May 04 03:47:58 PM PDT 24
Peak memory 220348 kb
Host smart-5a5707e2-ab67-4690-8985-9b21655f3c13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313031419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1313031419
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.2611544651
Short name T807
Test name
Test status
Simulation time 1204745980 ps
CPU time 5.11 seconds
Started May 04 03:47:56 PM PDT 24
Finished May 04 03:48:02 PM PDT 24
Peak memory 222696 kb
Host smart-2f6d15c1-9a12-4eee-87f8-8b3096c796b7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611544651 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.2611544651
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2018856347
Short name T58
Test name
Test status
Simulation time 3745443473 ps
CPU time 32.74 seconds
Started May 04 03:47:46 PM PDT 24
Finished May 04 03:48:19 PM PDT 24
Peak memory 211732 kb
Host smart-09543700-b573-44fd-aa46-82934899a229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018856347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2018856347
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.80042515
Short name T836
Test name
Test status
Simulation time 57191221 ps
CPU time 0.75 seconds
Started May 04 03:47:52 PM PDT 24
Finished May 04 03:47:53 PM PDT 24
Peak memory 205884 kb
Host smart-4353c6a7-415d-4307-89f6-d833ee731e60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80042515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.80042515
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1719812815
Short name T595
Test name
Test status
Simulation time 3100550668 ps
CPU time 22.36 seconds
Started May 04 03:47:51 PM PDT 24
Finished May 04 03:48:14 PM PDT 24
Peak memory 214312 kb
Host smart-629a4737-8d07-4941-8a32-54c5d090d90f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719812815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1719812815
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2788477157
Short name T798
Test name
Test status
Simulation time 263255925 ps
CPU time 3.92 seconds
Started May 04 03:47:57 PM PDT 24
Finished May 04 03:48:02 PM PDT 24
Peak memory 211588 kb
Host smart-0d2126f6-ed49-4016-a4fe-8b46e6e9a3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788477157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2788477157
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.477556526
Short name T87
Test name
Test status
Simulation time 83189005 ps
CPU time 3 seconds
Started May 04 03:47:51 PM PDT 24
Finished May 04 03:47:54 PM PDT 24
Peak memory 214336 kb
Host smart-cb524df9-6daa-443b-a735-1755b6dc8199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477556526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.477556526
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3651790188
Short name T586
Test name
Test status
Simulation time 197192065 ps
CPU time 6.19 seconds
Started May 04 03:47:46 PM PDT 24
Finished May 04 03:47:53 PM PDT 24
Peak memory 207068 kb
Host smart-e5888b27-800c-48db-9cb1-3783009d5302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651790188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3651790188
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1333373327
Short name T726
Test name
Test status
Simulation time 359642522 ps
CPU time 2.56 seconds
Started May 04 03:47:47 PM PDT 24
Finished May 04 03:47:50 PM PDT 24
Peak memory 206784 kb
Host smart-0c1c699b-36d4-4c40-95fe-193b9f53771d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333373327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1333373327
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3678527545
Short name T108
Test name
Test status
Simulation time 118378136 ps
CPU time 5.29 seconds
Started May 04 03:47:47 PM PDT 24
Finished May 04 03:47:53 PM PDT 24
Peak memory 206904 kb
Host smart-71c3690d-d089-44f2-9388-463ab285a623
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678527545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3678527545
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.117852033
Short name T649
Test name
Test status
Simulation time 245902353 ps
CPU time 7.04 seconds
Started May 04 03:47:48 PM PDT 24
Finished May 04 03:47:55 PM PDT 24
Peak memory 208016 kb
Host smart-e2ec31b9-e1d8-44d0-8483-1ee0bb71fa5a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117852033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.117852033
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3662006751
Short name T611
Test name
Test status
Simulation time 95035610 ps
CPU time 3.19 seconds
Started May 04 03:47:45 PM PDT 24
Finished May 04 03:47:49 PM PDT 24
Peak memory 208276 kb
Host smart-a89c7f6c-2111-44a3-ab13-55918111bce8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662006751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3662006751
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.953999625
Short name T678
Test name
Test status
Simulation time 385858812 ps
CPU time 3.55 seconds
Started May 04 03:47:50 PM PDT 24
Finished May 04 03:47:54 PM PDT 24
Peak memory 209748 kb
Host smart-ed9e3fce-47da-474e-8900-94a0a14070ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953999625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.953999625
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.4201579974
Short name T999
Test name
Test status
Simulation time 79663016 ps
CPU time 1.8 seconds
Started May 04 03:47:45 PM PDT 24
Finished May 04 03:47:48 PM PDT 24
Peak memory 206644 kb
Host smart-8b9b901e-eb7f-4684-98e4-ebfe315aee78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201579974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.4201579974
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3815495374
Short name T401
Test name
Test status
Simulation time 561031914 ps
CPU time 6.6 seconds
Started May 04 03:47:53 PM PDT 24
Finished May 04 03:48:00 PM PDT 24
Peak memory 222592 kb
Host smart-ab5a49c1-4a65-4ae8-a69f-74e7b277c131
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815495374 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3815495374
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.773121644
Short name T1066
Test name
Test status
Simulation time 84232581 ps
CPU time 4.09 seconds
Started May 04 03:47:52 PM PDT 24
Finished May 04 03:47:56 PM PDT 24
Peak memory 207872 kb
Host smart-6da7b718-5aa1-4b67-9bf3-a4467c288b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773121644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.773121644
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2530567550
Short name T739
Test name
Test status
Simulation time 42243203 ps
CPU time 2.45 seconds
Started May 04 03:47:53 PM PDT 24
Finished May 04 03:47:56 PM PDT 24
Peak memory 210244 kb
Host smart-b89a68af-c831-4c85-96c7-ac1077d14a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530567550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2530567550
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1495990648
Short name T658
Test name
Test status
Simulation time 279203081 ps
CPU time 0.98 seconds
Started May 04 03:47:56 PM PDT 24
Finished May 04 03:47:57 PM PDT 24
Peak memory 205848 kb
Host smart-067cd667-1b78-4ad6-9dc4-ad6362264374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495990648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1495990648
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.4145756034
Short name T371
Test name
Test status
Simulation time 6311802789 ps
CPU time 81.43 seconds
Started May 04 03:47:50 PM PDT 24
Finished May 04 03:49:12 PM PDT 24
Peak memory 214388 kb
Host smart-a3cbc1a0-4fb9-4a2e-ba50-026a2f5b438e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145756034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.4145756034
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2565642700
Short name T863
Test name
Test status
Simulation time 45375022 ps
CPU time 1.96 seconds
Started May 04 03:47:57 PM PDT 24
Finished May 04 03:48:00 PM PDT 24
Peak memory 209616 kb
Host smart-85191750-51eb-4110-abb4-4b03b240e715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565642700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2565642700
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1770759931
Short name T620
Test name
Test status
Simulation time 2790464099 ps
CPU time 28.26 seconds
Started May 04 03:47:52 PM PDT 24
Finished May 04 03:48:21 PM PDT 24
Peak memory 208968 kb
Host smart-9e346610-ab36-477d-b380-3bb38990112f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770759931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1770759931
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1524410666
Short name T979
Test name
Test status
Simulation time 876458321 ps
CPU time 5.77 seconds
Started May 04 03:47:57 PM PDT 24
Finished May 04 03:48:03 PM PDT 24
Peak memory 222388 kb
Host smart-3138ec2e-0b77-48ec-919f-bd178b1c4fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524410666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1524410666
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3465765506
Short name T779
Test name
Test status
Simulation time 819806892 ps
CPU time 5.4 seconds
Started May 04 03:47:53 PM PDT 24
Finished May 04 03:47:59 PM PDT 24
Peak memory 222480 kb
Host smart-93ea01b0-715d-4e63-a7f0-f19ab8343b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465765506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3465765506
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1995174298
Short name T749
Test name
Test status
Simulation time 559526269 ps
CPU time 3.34 seconds
Started May 04 03:47:57 PM PDT 24
Finished May 04 03:48:01 PM PDT 24
Peak memory 210500 kb
Host smart-b3d5c1cf-ab54-4ec2-b7d6-d94602cdf51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995174298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1995174298
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2408592524
Short name T233
Test name
Test status
Simulation time 486771011 ps
CPU time 4.4 seconds
Started May 04 03:47:51 PM PDT 24
Finished May 04 03:47:56 PM PDT 24
Peak memory 208380 kb
Host smart-e4dd097a-c7c2-49fb-9644-129f07e86794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408592524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2408592524
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3243239462
Short name T683
Test name
Test status
Simulation time 706990677 ps
CPU time 5.56 seconds
Started May 04 03:47:53 PM PDT 24
Finished May 04 03:47:59 PM PDT 24
Peak memory 208444 kb
Host smart-31036a13-40ec-4e8c-809d-19d46756d4c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243239462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3243239462
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1368207284
Short name T855
Test name
Test status
Simulation time 119552556 ps
CPU time 2.59 seconds
Started May 04 03:47:51 PM PDT 24
Finished May 04 03:47:54 PM PDT 24
Peak memory 208972 kb
Host smart-087efbca-23c0-40df-86bd-7a8f6a49128b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368207284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1368207284
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3892736063
Short name T1
Test name
Test status
Simulation time 58472766 ps
CPU time 3.28 seconds
Started May 04 03:47:49 PM PDT 24
Finished May 04 03:47:53 PM PDT 24
Peak memory 206972 kb
Host smart-19315fa9-a0e9-4be8-8694-664255435675
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892736063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3892736063
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3642711262
Short name T1004
Test name
Test status
Simulation time 183475757 ps
CPU time 4.08 seconds
Started May 04 03:47:59 PM PDT 24
Finished May 04 03:48:03 PM PDT 24
Peak memory 214268 kb
Host smart-5cb99a74-9755-4c73-a22d-af0454824e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642711262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3642711262
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.673430115
Short name T617
Test name
Test status
Simulation time 7346433281 ps
CPU time 16.11 seconds
Started May 04 03:47:57 PM PDT 24
Finished May 04 03:48:14 PM PDT 24
Peak memory 207964 kb
Host smart-51bc1637-da39-4366-9ec2-a1dc2712a19d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673430115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.673430115
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.174571906
Short name T274
Test name
Test status
Simulation time 17537554169 ps
CPU time 95.21 seconds
Started May 04 03:47:57 PM PDT 24
Finished May 04 03:49:32 PM PDT 24
Peak memory 222580 kb
Host smart-93548672-99f2-4a2d-892e-2434cacf6ddf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174571906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.174571906
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3697126234
Short name T963
Test name
Test status
Simulation time 65847929 ps
CPU time 4.35 seconds
Started May 04 03:47:57 PM PDT 24
Finished May 04 03:48:01 PM PDT 24
Peak memory 222496 kb
Host smart-f98d109c-f61f-4b1c-9ea9-37a00cd59cbe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697126234 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3697126234
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1894851172
Short name T910
Test name
Test status
Simulation time 482545117 ps
CPU time 5.9 seconds
Started May 04 03:47:58 PM PDT 24
Finished May 04 03:48:05 PM PDT 24
Peak memory 209716 kb
Host smart-236a422e-9e8e-45d6-8503-838089a303fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894851172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1894851172
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2887871177
Short name T766
Test name
Test status
Simulation time 59822620 ps
CPU time 3.23 seconds
Started May 04 03:47:58 PM PDT 24
Finished May 04 03:48:02 PM PDT 24
Peak memory 210428 kb
Host smart-f13e0483-8791-42cb-ab75-ebea180e5af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887871177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2887871177
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1065815546
Short name T791
Test name
Test status
Simulation time 17778506 ps
CPU time 0.78 seconds
Started May 04 03:48:02 PM PDT 24
Finished May 04 03:48:03 PM PDT 24
Peak memory 205808 kb
Host smart-126e2f05-b3d9-42b8-bb37-879b19e88009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065815546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1065815546
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1443869034
Short name T223
Test name
Test status
Simulation time 170331623 ps
CPU time 3.58 seconds
Started May 04 03:48:00 PM PDT 24
Finished May 04 03:48:04 PM PDT 24
Peak memory 214244 kb
Host smart-58b4fba5-596e-48df-a24e-6579bb09bbe1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1443869034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1443869034
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2503643692
Short name T156
Test name
Test status
Simulation time 4118972634 ps
CPU time 69.98 seconds
Started May 04 03:48:01 PM PDT 24
Finished May 04 03:49:12 PM PDT 24
Peak memory 222760 kb
Host smart-24cc4a66-189d-4478-bfb8-e6f86855092e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503643692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2503643692
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2745870427
Short name T257
Test name
Test status
Simulation time 390779495 ps
CPU time 4.7 seconds
Started May 04 03:48:00 PM PDT 24
Finished May 04 03:48:05 PM PDT 24
Peak memory 209228 kb
Host smart-24adbde3-356e-4728-afc3-4aaf790bb6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745870427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2745870427
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.301101838
Short name T94
Test name
Test status
Simulation time 1029272999 ps
CPU time 8.41 seconds
Started May 04 03:48:01 PM PDT 24
Finished May 04 03:48:10 PM PDT 24
Peak memory 220808 kb
Host smart-576d6038-31df-4a00-891e-8aab7619eca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301101838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.301101838
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1255937730
Short name T978
Test name
Test status
Simulation time 1979915665 ps
CPU time 70.99 seconds
Started May 04 03:48:01 PM PDT 24
Finished May 04 03:49:12 PM PDT 24
Peak memory 230628 kb
Host smart-9012f4ba-7ce2-4b3c-958c-a227266bd91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255937730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1255937730
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.484191066
Short name T975
Test name
Test status
Simulation time 480890171 ps
CPU time 3.33 seconds
Started May 04 03:48:03 PM PDT 24
Finished May 04 03:48:07 PM PDT 24
Peak memory 208260 kb
Host smart-1ddebf95-6436-4375-8848-39d19c775aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484191066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.484191066
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.265039453
Short name T1053
Test name
Test status
Simulation time 383565566 ps
CPU time 3.77 seconds
Started May 04 03:48:02 PM PDT 24
Finished May 04 03:48:06 PM PDT 24
Peak memory 207788 kb
Host smart-43c75349-4340-401c-9036-c8a6ce5acf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265039453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.265039453
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3351122938
Short name T679
Test name
Test status
Simulation time 61456043 ps
CPU time 3.08 seconds
Started May 04 03:48:00 PM PDT 24
Finished May 04 03:48:03 PM PDT 24
Peak memory 206720 kb
Host smart-18ad7041-4f28-4ba6-9b5e-987a9f99834f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351122938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3351122938
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.686299803
Short name T713
Test name
Test status
Simulation time 80051543 ps
CPU time 3.33 seconds
Started May 04 03:48:03 PM PDT 24
Finished May 04 03:48:07 PM PDT 24
Peak memory 208156 kb
Host smart-6f816740-2169-4be0-a7e1-27cc308c960c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686299803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.686299803
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.2686517617
Short name T938
Test name
Test status
Simulation time 432277899 ps
CPU time 5.15 seconds
Started May 04 03:47:56 PM PDT 24
Finished May 04 03:48:02 PM PDT 24
Peak memory 206884 kb
Host smart-74f65ac3-b9a6-4ae7-b953-a197e7499a23
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686517617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.2686517617
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1660199293
Short name T721
Test name
Test status
Simulation time 1221106823 ps
CPU time 30.99 seconds
Started May 04 03:48:02 PM PDT 24
Finished May 04 03:48:33 PM PDT 24
Peak memory 208436 kb
Host smart-af38a497-9414-4fcd-849b-8dff0e794b8e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660199293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1660199293
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2665288837
Short name T705
Test name
Test status
Simulation time 128733710 ps
CPU time 2.7 seconds
Started May 04 03:48:02 PM PDT 24
Finished May 04 03:48:05 PM PDT 24
Peak memory 207456 kb
Host smart-476fbde4-171f-4dd4-b204-e72f96b1885a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665288837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2665288837
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3798018536
Short name T674
Test name
Test status
Simulation time 154044306 ps
CPU time 4.08 seconds
Started May 04 03:47:59 PM PDT 24
Finished May 04 03:48:04 PM PDT 24
Peak memory 208536 kb
Host smart-7224f9e7-bccd-41ae-9261-b356fd845411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798018536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3798018536
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2603538802
Short name T221
Test name
Test status
Simulation time 1930279196 ps
CPU time 54.79 seconds
Started May 04 03:48:03 PM PDT 24
Finished May 04 03:48:58 PM PDT 24
Peak memory 215076 kb
Host smart-263068af-7762-487d-b7c7-403a18da05b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603538802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2603538802
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.3444326237
Short name T125
Test name
Test status
Simulation time 606077596 ps
CPU time 7.4 seconds
Started May 04 03:48:04 PM PDT 24
Finished May 04 03:48:11 PM PDT 24
Peak memory 222532 kb
Host smart-aa96f676-67c1-4f0f-b73a-00206be45301
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444326237 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.3444326237
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1221756848
Short name T1048
Test name
Test status
Simulation time 509772666 ps
CPU time 4.14 seconds
Started May 04 03:48:03 PM PDT 24
Finished May 04 03:48:08 PM PDT 24
Peak memory 207784 kb
Host smart-6aa1caf3-8ca3-4fa8-9e77-ed4bffcc95ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221756848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1221756848
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2286108347
Short name T1020
Test name
Test status
Simulation time 737809958 ps
CPU time 4.45 seconds
Started May 04 03:48:03 PM PDT 24
Finished May 04 03:48:08 PM PDT 24
Peak memory 210944 kb
Host smart-9010d358-a7f7-4870-9b28-2f83f5feed14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286108347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2286108347
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.4089840915
Short name T896
Test name
Test status
Simulation time 14022903 ps
CPU time 0.9 seconds
Started May 04 03:46:13 PM PDT 24
Finished May 04 03:46:14 PM PDT 24
Peak memory 206052 kb
Host smart-3feff151-be74-4136-8708-15dfe94ea00d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089840915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.4089840915
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.839347556
Short name T197
Test name
Test status
Simulation time 295195972 ps
CPU time 4.65 seconds
Started May 04 03:46:07 PM PDT 24
Finished May 04 03:46:12 PM PDT 24
Peak memory 214292 kb
Host smart-86afc693-5cc1-49c4-ab0a-49461d3ba474
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=839347556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.839347556
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3354060002
Short name T738
Test name
Test status
Simulation time 86700158 ps
CPU time 3.06 seconds
Started May 04 03:46:07 PM PDT 24
Finished May 04 03:46:10 PM PDT 24
Peak memory 209568 kb
Host smart-31118cc7-e6a2-4382-a731-5be0210d1bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354060002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3354060002
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1261372603
Short name T336
Test name
Test status
Simulation time 253126128 ps
CPU time 6.67 seconds
Started May 04 03:46:07 PM PDT 24
Finished May 04 03:46:15 PM PDT 24
Peak memory 209720 kb
Host smart-62d8c82e-89ae-40ab-8f6b-e93ca32ad07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261372603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1261372603
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3559187230
Short name T356
Test name
Test status
Simulation time 283547809 ps
CPU time 7.53 seconds
Started May 04 03:46:09 PM PDT 24
Finished May 04 03:46:17 PM PDT 24
Peak memory 219108 kb
Host smart-e4adfdbd-83f3-4b1b-afde-ef6552c870ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559187230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3559187230
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_random.963962657
Short name T769
Test name
Test status
Simulation time 214883575 ps
CPU time 8.91 seconds
Started May 04 03:46:07 PM PDT 24
Finished May 04 03:46:16 PM PDT 24
Peak memory 214308 kb
Host smart-c51df0ea-cf40-427a-8d99-562f179cd700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963962657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.963962657
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3472021264
Short name T105
Test name
Test status
Simulation time 1979294790 ps
CPU time 11.63 seconds
Started May 04 03:46:14 PM PDT 24
Finished May 04 03:46:26 PM PDT 24
Peak memory 238164 kb
Host smart-c2fff795-2e05-44cf-8fd5-ef86f53c9338
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472021264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3472021264
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2427042222
Short name T89
Test name
Test status
Simulation time 94663015 ps
CPU time 4 seconds
Started May 04 03:46:06 PM PDT 24
Finished May 04 03:46:10 PM PDT 24
Peak memory 208368 kb
Host smart-6f00469f-5a74-4ed1-99b0-fa6124e29261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427042222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2427042222
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.137806149
Short name T1011
Test name
Test status
Simulation time 120064855 ps
CPU time 2.38 seconds
Started May 04 03:46:08 PM PDT 24
Finished May 04 03:46:11 PM PDT 24
Peak memory 206848 kb
Host smart-ce673c2c-e2b3-4d72-b6d8-c84d74fbbd34
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137806149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.137806149
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.926605188
Short name T652
Test name
Test status
Simulation time 589080908 ps
CPU time 5.17 seconds
Started May 04 03:46:06 PM PDT 24
Finished May 04 03:46:11 PM PDT 24
Peak memory 206864 kb
Host smart-d38e7b97-b9c3-4ee2-9809-a140f6af140c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926605188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.926605188
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2541494036
Short name T393
Test name
Test status
Simulation time 138175322 ps
CPU time 2.94 seconds
Started May 04 03:46:07 PM PDT 24
Finished May 04 03:46:11 PM PDT 24
Peak memory 206900 kb
Host smart-d350cab4-0941-47c4-baab-fb908d70ebd5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541494036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2541494036
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1425947586
Short name T135
Test name
Test status
Simulation time 43964152 ps
CPU time 2.56 seconds
Started May 04 03:46:07 PM PDT 24
Finished May 04 03:46:10 PM PDT 24
Peak memory 207480 kb
Host smart-30f8b36b-6f38-445b-a19e-f1b3e0a184ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425947586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1425947586
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2022192654
Short name T1021
Test name
Test status
Simulation time 33998249 ps
CPU time 2.35 seconds
Started May 04 03:46:02 PM PDT 24
Finished May 04 03:46:04 PM PDT 24
Peak memory 206900 kb
Host smart-f347a82a-2930-4304-a3d6-ad561c2adc7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022192654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2022192654
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1004726992
Short name T54
Test name
Test status
Simulation time 2245561712 ps
CPU time 42.45 seconds
Started May 04 03:46:12 PM PDT 24
Finished May 04 03:46:55 PM PDT 24
Peak memory 215488 kb
Host smart-38a59368-ccc6-4a24-b8c3-80f105ba1c22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004726992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1004726992
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.4168014365
Short name T730
Test name
Test status
Simulation time 457364378 ps
CPU time 6.93 seconds
Started May 04 03:46:12 PM PDT 24
Finished May 04 03:46:19 PM PDT 24
Peak memory 220196 kb
Host smart-052d8a39-5b3b-44c7-92c3-c5d0bfbfa1a2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168014365 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.4168014365
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2675881289
Short name T898
Test name
Test status
Simulation time 102409813 ps
CPU time 4.25 seconds
Started May 04 03:46:06 PM PDT 24
Finished May 04 03:46:11 PM PDT 24
Peak memory 209976 kb
Host smart-8887f68c-d509-4c49-ac29-c367112cce1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675881289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2675881289
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.4071963950
Short name T1068
Test name
Test status
Simulation time 55576425 ps
CPU time 1.99 seconds
Started May 04 03:46:13 PM PDT 24
Finished May 04 03:46:16 PM PDT 24
Peak memory 210152 kb
Host smart-adffa6e1-6504-4f2a-8029-b2c9021df483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071963950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.4071963950
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2769165448
Short name T969
Test name
Test status
Simulation time 24975737 ps
CPU time 0.73 seconds
Started May 04 03:48:11 PM PDT 24
Finished May 04 03:48:12 PM PDT 24
Peak memory 205856 kb
Host smart-01bade49-5e7e-4b63-9f49-88b1cc081d59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769165448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2769165448
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.112569193
Short name T412
Test name
Test status
Simulation time 770515825 ps
CPU time 9.92 seconds
Started May 04 03:48:07 PM PDT 24
Finished May 04 03:48:17 PM PDT 24
Peak memory 214252 kb
Host smart-2e9ee386-fe0a-4446-83a6-ec21b494b2b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=112569193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.112569193
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2752898830
Short name T36
Test name
Test status
Simulation time 1297528711 ps
CPU time 13.28 seconds
Started May 04 03:48:07 PM PDT 24
Finished May 04 03:48:21 PM PDT 24
Peak memory 217904 kb
Host smart-65d19b30-fb15-44b7-8461-81d2a119a484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752898830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2752898830
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1068553342
Short name T385
Test name
Test status
Simulation time 137095348 ps
CPU time 4.27 seconds
Started May 04 03:48:10 PM PDT 24
Finished May 04 03:48:15 PM PDT 24
Peak memory 222568 kb
Host smart-c5816985-c0a3-405f-9e1f-bb4aa3260c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068553342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1068553342
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3876451715
Short name T388
Test name
Test status
Simulation time 5217755997 ps
CPU time 30.92 seconds
Started May 04 03:48:08 PM PDT 24
Finished May 04 03:48:39 PM PDT 24
Peak memory 220564 kb
Host smart-abd6592c-68d0-4a01-bb79-980da68ec98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876451715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3876451715
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.587515744
Short name T1019
Test name
Test status
Simulation time 100141681 ps
CPU time 3.43 seconds
Started May 04 03:48:08 PM PDT 24
Finished May 04 03:48:12 PM PDT 24
Peak memory 211720 kb
Host smart-1c5a7f38-0bba-4a97-88fa-cb3e59f3b0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587515744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.587515744
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.633162422
Short name T50
Test name
Test status
Simulation time 57163119 ps
CPU time 2.77 seconds
Started May 04 03:48:07 PM PDT 24
Finished May 04 03:48:10 PM PDT 24
Peak memory 214288 kb
Host smart-23c3b9a9-dc9f-4741-a3c5-978eb9135080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633162422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.633162422
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2714858770
Short name T688
Test name
Test status
Simulation time 803530281 ps
CPU time 4.73 seconds
Started May 04 03:48:10 PM PDT 24
Finished May 04 03:48:15 PM PDT 24
Peak memory 218404 kb
Host smart-6621acb4-ab26-4b0e-83e9-286d04678d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714858770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2714858770
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.526000972
Short name T723
Test name
Test status
Simulation time 244916167 ps
CPU time 8.7 seconds
Started May 04 03:48:10 PM PDT 24
Finished May 04 03:48:19 PM PDT 24
Peak memory 207864 kb
Host smart-70564c17-7d31-4ddf-a562-deea5c19d074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526000972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.526000972
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3981568653
Short name T720
Test name
Test status
Simulation time 1738184798 ps
CPU time 49.32 seconds
Started May 04 03:48:07 PM PDT 24
Finished May 04 03:48:57 PM PDT 24
Peak memory 208308 kb
Host smart-4dd53082-07c9-4144-a42d-9e9cd95f51ca
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981568653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3981568653
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.4076731325
Short name T396
Test name
Test status
Simulation time 644969107 ps
CPU time 6.37 seconds
Started May 04 03:48:08 PM PDT 24
Finished May 04 03:48:15 PM PDT 24
Peak memory 208788 kb
Host smart-434600ca-e2dd-4887-9612-4b622c659f69
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076731325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4076731325
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3444966792
Short name T680
Test name
Test status
Simulation time 1318116176 ps
CPU time 5.91 seconds
Started May 04 03:48:07 PM PDT 24
Finished May 04 03:48:13 PM PDT 24
Peak memory 207920 kb
Host smart-8badff13-3b16-4c9b-8b87-6088dac1de07
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444966792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3444966792
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3939908477
Short name T1032
Test name
Test status
Simulation time 409277651 ps
CPU time 3.21 seconds
Started May 04 03:48:10 PM PDT 24
Finished May 04 03:48:13 PM PDT 24
Peak memory 209864 kb
Host smart-b9d07b5e-05e4-4392-bf08-d1c0f3054b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939908477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3939908477
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2156792026
Short name T869
Test name
Test status
Simulation time 74577246 ps
CPU time 2.32 seconds
Started May 04 03:48:03 PM PDT 24
Finished May 04 03:48:05 PM PDT 24
Peak memory 206872 kb
Host smart-3629f4ca-3b0e-4dc1-89ec-1e09908c84e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156792026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2156792026
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.4264424214
Short name T316
Test name
Test status
Simulation time 1681493632 ps
CPU time 17.25 seconds
Started May 04 03:48:07 PM PDT 24
Finished May 04 03:48:25 PM PDT 24
Peak memory 216640 kb
Host smart-bdc1d0d9-8e83-4d2d-8db8-92fbd455e664
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264424214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.4264424214
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2604567668
Short name T351
Test name
Test status
Simulation time 146190656 ps
CPU time 5.73 seconds
Started May 04 03:48:09 PM PDT 24
Finished May 04 03:48:15 PM PDT 24
Peak memory 219692 kb
Host smart-40236fbc-f804-4826-9874-928752f075ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604567668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2604567668
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1389813557
Short name T62
Test name
Test status
Simulation time 92673992 ps
CPU time 2.8 seconds
Started May 04 03:48:10 PM PDT 24
Finished May 04 03:48:13 PM PDT 24
Peak memory 210520 kb
Host smart-c8e5b7e6-d7fb-4d60-8376-427ef9462444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389813557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1389813557
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.111907636
Short name T602
Test name
Test status
Simulation time 12152733 ps
CPU time 0.87 seconds
Started May 04 03:48:16 PM PDT 24
Finished May 04 03:48:17 PM PDT 24
Peak memory 205892 kb
Host smart-71e3304a-245c-44de-8c96-a3e92830bd70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111907636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.111907636
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.787140888
Short name T248
Test name
Test status
Simulation time 208517370 ps
CPU time 4.74 seconds
Started May 04 03:48:13 PM PDT 24
Finished May 04 03:48:19 PM PDT 24
Peak memory 210652 kb
Host smart-1845f591-a7d8-424a-a79c-4f59beed4864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787140888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.787140888
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1647195147
Short name T1000
Test name
Test status
Simulation time 44019885 ps
CPU time 1.87 seconds
Started May 04 03:48:12 PM PDT 24
Finished May 04 03:48:15 PM PDT 24
Peak memory 218568 kb
Host smart-fb60334f-81b3-4aae-bf8b-5a8405daa4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647195147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1647195147
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2343610578
Short name T665
Test name
Test status
Simulation time 1617608836 ps
CPU time 20.92 seconds
Started May 04 03:48:14 PM PDT 24
Finished May 04 03:48:36 PM PDT 24
Peak memory 214328 kb
Host smart-4be3d19a-5828-4663-a117-0d790502ae9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343610578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2343610578
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2809446610
Short name T235
Test name
Test status
Simulation time 580896528 ps
CPU time 6.11 seconds
Started May 04 03:48:14 PM PDT 24
Finished May 04 03:48:20 PM PDT 24
Peak memory 214212 kb
Host smart-ac5f4979-072b-45f8-932f-4de4fe1ad6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809446610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2809446610
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2952652135
Short name T645
Test name
Test status
Simulation time 231984124 ps
CPU time 3.37 seconds
Started May 04 03:48:14 PM PDT 24
Finished May 04 03:48:18 PM PDT 24
Peak memory 208184 kb
Host smart-3d610c2c-f813-4e0b-b10a-d2a338663744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952652135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2952652135
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.653637358
Short name T323
Test name
Test status
Simulation time 322082129 ps
CPU time 2.96 seconds
Started May 04 03:48:07 PM PDT 24
Finished May 04 03:48:10 PM PDT 24
Peak memory 208804 kb
Host smart-ab0dd8d5-63e4-42c6-ab8d-d36942a906b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653637358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.653637358
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1563975475
Short name T17
Test name
Test status
Simulation time 403257195 ps
CPU time 2.37 seconds
Started May 04 03:48:07 PM PDT 24
Finished May 04 03:48:10 PM PDT 24
Peak memory 206916 kb
Host smart-3e5af7b8-2ee0-45f6-9533-7475e159c611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563975475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1563975475
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.4066937677
Short name T906
Test name
Test status
Simulation time 115373120 ps
CPU time 3.99 seconds
Started May 04 03:48:09 PM PDT 24
Finished May 04 03:48:13 PM PDT 24
Peak memory 206692 kb
Host smart-71a22bf8-2e7f-43b0-8443-5f512c49c9d8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066937677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.4066937677
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.216930699
Short name T965
Test name
Test status
Simulation time 744796337 ps
CPU time 7.79 seconds
Started May 04 03:48:07 PM PDT 24
Finished May 04 03:48:15 PM PDT 24
Peak memory 208732 kb
Host smart-4b44e957-a882-4169-8787-dadd5055c0c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216930699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.216930699
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.865474183
Short name T592
Test name
Test status
Simulation time 163653003 ps
CPU time 2.74 seconds
Started May 04 03:48:08 PM PDT 24
Finished May 04 03:48:12 PM PDT 24
Peak memory 207256 kb
Host smart-81e4c94e-bb2b-4a97-a61a-a80f5dc17804
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865474183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.865474183
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1444965972
Short name T416
Test name
Test status
Simulation time 828629919 ps
CPU time 4.83 seconds
Started May 04 03:48:14 PM PDT 24
Finished May 04 03:48:19 PM PDT 24
Peak memory 214380 kb
Host smart-e9a48dc1-2ec9-4998-914c-0207cb2c48e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444965972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1444965972
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.195645061
Short name T850
Test name
Test status
Simulation time 367639627 ps
CPU time 4.93 seconds
Started May 04 03:48:07 PM PDT 24
Finished May 04 03:48:13 PM PDT 24
Peak memory 206720 kb
Host smart-3ff418cf-a016-45ad-9a00-e8b02e55ca54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195645061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.195645061
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2964858686
Short name T56
Test name
Test status
Simulation time 417608120 ps
CPU time 18.02 seconds
Started May 04 03:48:12 PM PDT 24
Finished May 04 03:48:31 PM PDT 24
Peak memory 222556 kb
Host smart-98d5f9fa-26ce-47a0-9d2f-5bed002fe597
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964858686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2964858686
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.4207137968
Short name T737
Test name
Test status
Simulation time 53213976 ps
CPU time 4.21 seconds
Started May 04 03:48:12 PM PDT 24
Finished May 04 03:48:17 PM PDT 24
Peak memory 222636 kb
Host smart-af2367b6-0127-4a23-ada0-7505e7cc8348
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207137968 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.4207137968
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.3121559219
Short name T185
Test name
Test status
Simulation time 304762616 ps
CPU time 8.2 seconds
Started May 04 03:48:14 PM PDT 24
Finished May 04 03:48:23 PM PDT 24
Peak memory 208352 kb
Host smart-efb4ac8f-9e27-480f-8417-a6d2c2a666d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121559219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.3121559219
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1572074674
Short name T599
Test name
Test status
Simulation time 164093043 ps
CPU time 2.27 seconds
Started May 04 03:48:14 PM PDT 24
Finished May 04 03:48:16 PM PDT 24
Peak memory 210004 kb
Host smart-c5f9db0c-d92d-4324-85c6-4250ba69055a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572074674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1572074674
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3522556993
Short name T1012
Test name
Test status
Simulation time 212655694 ps
CPU time 4.22 seconds
Started May 04 03:48:21 PM PDT 24
Finished May 04 03:48:25 PM PDT 24
Peak memory 214320 kb
Host smart-1e5b875c-e2c6-46f5-be39-c269dd3c9f79
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3522556993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3522556993
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2954421378
Short name T837
Test name
Test status
Simulation time 120237579 ps
CPU time 2.95 seconds
Started May 04 03:48:19 PM PDT 24
Finished May 04 03:48:22 PM PDT 24
Peak memory 210024 kb
Host smart-b473279e-4342-4a49-b877-19fa591f7ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954421378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2954421378
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2112608750
Short name T835
Test name
Test status
Simulation time 57623119 ps
CPU time 1.54 seconds
Started May 04 03:48:18 PM PDT 24
Finished May 04 03:48:20 PM PDT 24
Peak memory 206920 kb
Host smart-30666f99-48f6-4a9d-871a-926a3da1d65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112608750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2112608750
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.945283247
Short name T821
Test name
Test status
Simulation time 2984549901 ps
CPU time 19.74 seconds
Started May 04 03:48:20 PM PDT 24
Finished May 04 03:48:40 PM PDT 24
Peak memory 214336 kb
Host smart-e1797534-4897-4a34-8e68-278a1c1d3758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945283247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.945283247
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1148598145
Short name T944
Test name
Test status
Simulation time 336048349 ps
CPU time 3.32 seconds
Started May 04 03:48:19 PM PDT 24
Finished May 04 03:48:23 PM PDT 24
Peak memory 214336 kb
Host smart-125a01e9-4d63-4855-8cf0-6d6ec7d91d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148598145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1148598145
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.4192487557
Short name T244
Test name
Test status
Simulation time 304164788 ps
CPU time 11.26 seconds
Started May 04 03:48:20 PM PDT 24
Finished May 04 03:48:31 PM PDT 24
Peak memory 207504 kb
Host smart-5b6f7a2f-0745-43c0-bdf7-a284d7228481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192487557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.4192487557
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.196834752
Short name T982
Test name
Test status
Simulation time 19389145 ps
CPU time 1.71 seconds
Started May 04 03:48:13 PM PDT 24
Finished May 04 03:48:16 PM PDT 24
Peak memory 206800 kb
Host smart-1dc37a03-340c-4e24-8eec-2a56c24d5629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196834752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.196834752
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3883699932
Short name T822
Test name
Test status
Simulation time 96603335 ps
CPU time 2.17 seconds
Started May 04 03:48:13 PM PDT 24
Finished May 04 03:48:16 PM PDT 24
Peak memory 208644 kb
Host smart-5831d059-55f4-47a6-bd83-afd3320de3cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883699932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3883699932
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2934771307
Short name T675
Test name
Test status
Simulation time 922727401 ps
CPU time 4.24 seconds
Started May 04 03:48:12 PM PDT 24
Finished May 04 03:48:17 PM PDT 24
Peak memory 206888 kb
Host smart-80a9981e-1f49-4c1b-b806-3b24e8114fe3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934771307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2934771307
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3736782384
Short name T804
Test name
Test status
Simulation time 345882558 ps
CPU time 7.05 seconds
Started May 04 03:48:20 PM PDT 24
Finished May 04 03:48:27 PM PDT 24
Peak memory 208120 kb
Host smart-d322de45-8643-4f00-9b96-0f0b2a3a04b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736782384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3736782384
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2347669067
Short name T180
Test name
Test status
Simulation time 99534382 ps
CPU time 4.31 seconds
Started May 04 03:48:19 PM PDT 24
Finished May 04 03:48:24 PM PDT 24
Peak memory 218356 kb
Host smart-97812c06-c6c3-494f-9b43-0fced7a1d106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347669067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2347669067
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1374737663
Short name T760
Test name
Test status
Simulation time 43734768 ps
CPU time 1.82 seconds
Started May 04 03:48:12 PM PDT 24
Finished May 04 03:48:14 PM PDT 24
Peak memory 206584 kb
Host smart-7d281e12-5b2c-4fbc-a666-26a96dd5d684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374737663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1374737663
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2741928594
Short name T230
Test name
Test status
Simulation time 1645841905 ps
CPU time 11.45 seconds
Started May 04 03:48:21 PM PDT 24
Finished May 04 03:48:33 PM PDT 24
Peak memory 215524 kb
Host smart-dd4f8c20-7914-4dc5-8466-a91d7fbcc33c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741928594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2741928594
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.840185027
Short name T698
Test name
Test status
Simulation time 465145470 ps
CPU time 8.02 seconds
Started May 04 03:48:19 PM PDT 24
Finished May 04 03:48:27 PM PDT 24
Peak memory 222600 kb
Host smart-ad949e29-ea0f-4eb3-bef9-77505212d55c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840185027 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.840185027
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3606855898
Short name T621
Test name
Test status
Simulation time 894314327 ps
CPU time 10.64 seconds
Started May 04 03:48:19 PM PDT 24
Finished May 04 03:48:30 PM PDT 24
Peak memory 218432 kb
Host smart-8feed94e-3dc9-48a7-99d8-6653cec2383c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606855898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3606855898
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3404956187
Short name T672
Test name
Test status
Simulation time 170361121 ps
CPU time 5.49 seconds
Started May 04 03:48:18 PM PDT 24
Finished May 04 03:48:24 PM PDT 24
Peak memory 211032 kb
Host smart-4dce89a4-97b3-4799-8b23-d9f48006521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404956187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3404956187
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1886732137
Short name T1009
Test name
Test status
Simulation time 37116178 ps
CPU time 0.85 seconds
Started May 04 03:48:22 PM PDT 24
Finished May 04 03:48:23 PM PDT 24
Peak memory 205812 kb
Host smart-18e4589a-5ea1-46c7-b218-5b03ad9c04e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886732137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1886732137
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2613009866
Short name T781
Test name
Test status
Simulation time 1610667284 ps
CPU time 14.52 seconds
Started May 04 03:48:20 PM PDT 24
Finished May 04 03:48:36 PM PDT 24
Peak memory 214312 kb
Host smart-461b2dea-3800-49cc-979d-818c4abbaed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613009866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2613009866
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2718818599
Short name T112
Test name
Test status
Simulation time 2243092069 ps
CPU time 13.64 seconds
Started May 04 03:48:20 PM PDT 24
Finished May 04 03:48:34 PM PDT 24
Peak memory 208392 kb
Host smart-e607c461-427c-47b8-bb17-b9924a15409b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718818599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2718818599
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2008808676
Short name T1069
Test name
Test status
Simulation time 908560041 ps
CPU time 12.54 seconds
Started May 04 03:48:18 PM PDT 24
Finished May 04 03:48:31 PM PDT 24
Peak memory 210164 kb
Host smart-1249ede6-6fa3-40a4-b383-b00eecb5b2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008808676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2008808676
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2921480682
Short name T1044
Test name
Test status
Simulation time 45472309 ps
CPU time 3.02 seconds
Started May 04 03:48:21 PM PDT 24
Finished May 04 03:48:24 PM PDT 24
Peak memory 217924 kb
Host smart-d2c5723c-7c5d-4608-a809-b5c8ea05123e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921480682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2921480682
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2440101267
Short name T747
Test name
Test status
Simulation time 62961811 ps
CPU time 3.12 seconds
Started May 04 03:48:25 PM PDT 24
Finished May 04 03:48:29 PM PDT 24
Peak memory 207808 kb
Host smart-827d8815-a896-4249-ba99-9de6e0a04e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440101267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2440101267
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.418947112
Short name T1063
Test name
Test status
Simulation time 2174090773 ps
CPU time 54.78 seconds
Started May 04 03:48:18 PM PDT 24
Finished May 04 03:49:13 PM PDT 24
Peak memory 208544 kb
Host smart-97e56b39-562f-4d25-888b-1cb889a28f68
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418947112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.418947112
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3838083619
Short name T83
Test name
Test status
Simulation time 1377223722 ps
CPU time 11.05 seconds
Started May 04 03:48:20 PM PDT 24
Finished May 04 03:48:32 PM PDT 24
Peak memory 208652 kb
Host smart-c3ea02ef-231a-438d-ab01-3e005c3a264e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838083619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3838083619
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2210170441
Short name T605
Test name
Test status
Simulation time 490303960 ps
CPU time 6.84 seconds
Started May 04 03:48:20 PM PDT 24
Finished May 04 03:48:28 PM PDT 24
Peak memory 208852 kb
Host smart-0ce5587b-1724-4353-853c-a4210049d0e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210170441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2210170441
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1836564375
Short name T907
Test name
Test status
Simulation time 345932421 ps
CPU time 2.19 seconds
Started May 04 03:48:24 PM PDT 24
Finished May 04 03:48:27 PM PDT 24
Peak memory 215560 kb
Host smart-557f13cf-5360-4b02-94ac-325c44c407c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836564375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1836564375
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3871587829
Short name T833
Test name
Test status
Simulation time 4061909223 ps
CPU time 47.41 seconds
Started May 04 03:48:23 PM PDT 24
Finished May 04 03:49:11 PM PDT 24
Peak memory 208344 kb
Host smart-cfff4ec4-4686-49ac-a942-7504ed04004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871587829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3871587829
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1191827525
Short name T77
Test name
Test status
Simulation time 1805500300 ps
CPU time 34.34 seconds
Started May 04 03:48:25 PM PDT 24
Finished May 04 03:49:00 PM PDT 24
Peak memory 221136 kb
Host smart-f306c812-a4bb-4cef-b04a-053e6b9ef4cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191827525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1191827525
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.420388983
Short name T418
Test name
Test status
Simulation time 149229281 ps
CPU time 5.87 seconds
Started May 04 03:48:25 PM PDT 24
Finished May 04 03:48:31 PM PDT 24
Peak memory 221744 kb
Host smart-e2c426d6-bcd7-4d5e-9c6b-ba3f6f715efa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420388983 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.420388983
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1076774032
Short name T328
Test name
Test status
Simulation time 181782041 ps
CPU time 3.62 seconds
Started May 04 03:48:21 PM PDT 24
Finished May 04 03:48:25 PM PDT 24
Peak memory 207508 kb
Host smart-6504cfd3-8273-4739-9e80-6c90c06f0ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076774032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1076774032
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.394697444
Short name T926
Test name
Test status
Simulation time 436571114 ps
CPU time 8.97 seconds
Started May 04 03:48:23 PM PDT 24
Finished May 04 03:48:33 PM PDT 24
Peak memory 210328 kb
Host smart-3a815ed0-7993-4d31-85d2-e7a617dd9745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394697444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.394697444
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2483258680
Short name T579
Test name
Test status
Simulation time 109139721 ps
CPU time 1.19 seconds
Started May 04 03:48:30 PM PDT 24
Finished May 04 03:48:32 PM PDT 24
Peak memory 206020 kb
Host smart-d8aac471-d03c-4030-a33d-2aae80254b2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483258680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2483258680
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.753462177
Short name T237
Test name
Test status
Simulation time 148530429 ps
CPU time 5.05 seconds
Started May 04 03:48:24 PM PDT 24
Finished May 04 03:48:30 PM PDT 24
Peak memory 214260 kb
Host smart-1d8fc8f6-d73b-41cf-8d83-8b79e783906d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=753462177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.753462177
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3201632222
Short name T1055
Test name
Test status
Simulation time 3263986907 ps
CPU time 20.17 seconds
Started May 04 03:48:29 PM PDT 24
Finished May 04 03:48:50 PM PDT 24
Peak memory 220284 kb
Host smart-b2cdc71b-9507-4bc7-ab51-d32ef37d186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201632222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3201632222
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2615841009
Short name T288
Test name
Test status
Simulation time 489899930 ps
CPU time 2.56 seconds
Started May 04 03:48:24 PM PDT 24
Finished May 04 03:48:27 PM PDT 24
Peak memory 214388 kb
Host smart-0eb44d07-e184-4df9-b3e4-fcf0a85afd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615841009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2615841009
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.707981742
Short name T924
Test name
Test status
Simulation time 237929068 ps
CPU time 3.65 seconds
Started May 04 03:48:29 PM PDT 24
Finished May 04 03:48:33 PM PDT 24
Peak memory 208300 kb
Host smart-fd2a17a4-2c74-4874-9aea-5400b9a22378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707981742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.707981742
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3309953423
Short name T349
Test name
Test status
Simulation time 86194518 ps
CPU time 4.36 seconds
Started May 04 03:48:29 PM PDT 24
Finished May 04 03:48:33 PM PDT 24
Peak memory 222392 kb
Host smart-e48d3319-18a6-4da3-813c-fc66bdb07bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309953423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3309953423
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_random.3579249925
Short name T636
Test name
Test status
Simulation time 48927373 ps
CPU time 3.37 seconds
Started May 04 03:48:23 PM PDT 24
Finished May 04 03:48:26 PM PDT 24
Peak memory 207776 kb
Host smart-1c289059-cd85-40a9-b1eb-4eeae89650b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579249925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3579249925
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2321553113
Short name T778
Test name
Test status
Simulation time 1739625858 ps
CPU time 50.7 seconds
Started May 04 03:48:24 PM PDT 24
Finished May 04 03:49:15 PM PDT 24
Peak memory 208600 kb
Host smart-491aafc5-3cf1-4469-af74-b43259b41d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321553113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2321553113
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.620958823
Short name T918
Test name
Test status
Simulation time 713353716 ps
CPU time 16.18 seconds
Started May 04 03:48:23 PM PDT 24
Finished May 04 03:48:40 PM PDT 24
Peak memory 208872 kb
Host smart-4303c58c-456c-4dc1-b569-4c2117f0bc91
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620958823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.620958823
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2183669776
Short name T1041
Test name
Test status
Simulation time 1088777437 ps
CPU time 5.45 seconds
Started May 04 03:48:23 PM PDT 24
Finished May 04 03:48:29 PM PDT 24
Peak memory 208028 kb
Host smart-d17769eb-4fde-44ba-8dfa-1627f2e4bb03
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183669776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2183669776
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1544785155
Short name T1031
Test name
Test status
Simulation time 422181720 ps
CPU time 13.18 seconds
Started May 04 03:48:30 PM PDT 24
Finished May 04 03:48:44 PM PDT 24
Peak memory 218124 kb
Host smart-c74191fc-90d0-49f0-adb1-2f100b23e86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544785155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1544785155
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.431896599
Short name T761
Test name
Test status
Simulation time 1111096380 ps
CPU time 27.24 seconds
Started May 04 03:48:23 PM PDT 24
Finished May 04 03:48:51 PM PDT 24
Peak memory 208772 kb
Host smart-b5ab365e-e591-4c76-ba6d-b84b2bcda313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431896599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.431896599
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1826592110
Short name T376
Test name
Test status
Simulation time 20485374003 ps
CPU time 84.95 seconds
Started May 04 03:48:32 PM PDT 24
Finished May 04 03:49:57 PM PDT 24
Peak memory 216276 kb
Host smart-b3e822c3-25fb-4b70-a7e0-24efaa45e975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826592110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1826592110
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.265487717
Short name T655
Test name
Test status
Simulation time 42752571 ps
CPU time 3.01 seconds
Started May 04 03:48:30 PM PDT 24
Finished May 04 03:48:34 PM PDT 24
Peak memory 222608 kb
Host smart-a9f9aec6-1823-4e73-b38a-664cc7412871
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265487717 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.265487717
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.544325742
Short name T1026
Test name
Test status
Simulation time 3693728730 ps
CPU time 26.29 seconds
Started May 04 03:48:30 PM PDT 24
Finished May 04 03:48:56 PM PDT 24
Peak memory 218292 kb
Host smart-16aa659f-cb5b-41a3-892b-c9fa73a1c1a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544325742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.544325742
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.925400013
Short name T897
Test name
Test status
Simulation time 153658959 ps
CPU time 2.17 seconds
Started May 04 03:48:31 PM PDT 24
Finished May 04 03:48:34 PM PDT 24
Peak memory 210060 kb
Host smart-6620278f-6e24-4a0f-9acc-f853c2ba5823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=925400013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.925400013
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.868036064
Short name T653
Test name
Test status
Simulation time 35342821 ps
CPU time 0.78 seconds
Started May 04 03:48:36 PM PDT 24
Finished May 04 03:48:38 PM PDT 24
Peak memory 205872 kb
Host smart-9cfa9420-652b-4a68-85a1-039c882221cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868036064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.868036064
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.786512279
Short name T307
Test name
Test status
Simulation time 402516860 ps
CPU time 3.15 seconds
Started May 04 03:48:30 PM PDT 24
Finished May 04 03:48:34 PM PDT 24
Peak memory 219568 kb
Host smart-88633ce6-45d1-436c-99b4-4b8b9b76c0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786512279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.786512279
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.121807718
Short name T262
Test name
Test status
Simulation time 337949155 ps
CPU time 4.67 seconds
Started May 04 03:48:35 PM PDT 24
Finished May 04 03:48:40 PM PDT 24
Peak memory 214272 kb
Host smart-8e2f3aac-1efc-4fbe-bfd6-6a44bb238125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121807718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.121807718
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.404120683
Short name T810
Test name
Test status
Simulation time 65471427 ps
CPU time 3.06 seconds
Started May 04 03:48:29 PM PDT 24
Finished May 04 03:48:33 PM PDT 24
Peak memory 222604 kb
Host smart-2a10f6be-d8bd-499e-be20-3ba625f61d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404120683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.404120683
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1930918339
Short name T5
Test name
Test status
Simulation time 152472278 ps
CPU time 2.9 seconds
Started May 04 03:48:30 PM PDT 24
Finished May 04 03:48:33 PM PDT 24
Peak memory 209716 kb
Host smart-09a6ffd9-883f-4b82-adf2-6e582de12e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930918339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1930918339
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1470826486
Short name T763
Test name
Test status
Simulation time 193723435 ps
CPU time 2.71 seconds
Started May 04 03:48:29 PM PDT 24
Finished May 04 03:48:32 PM PDT 24
Peak memory 206848 kb
Host smart-62da7fca-c2be-47e0-b2d3-e46dcb684bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470826486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1470826486
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2758206849
Short name T1017
Test name
Test status
Simulation time 756307902 ps
CPU time 2.69 seconds
Started May 04 03:48:32 PM PDT 24
Finished May 04 03:48:35 PM PDT 24
Peak memory 208784 kb
Host smart-9cd9bc81-59a4-4fd3-a65e-85fa2971a0f4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758206849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2758206849
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3988525514
Short name T827
Test name
Test status
Simulation time 135694006 ps
CPU time 4.18 seconds
Started May 04 03:48:30 PM PDT 24
Finished May 04 03:48:35 PM PDT 24
Peak memory 208500 kb
Host smart-49777540-9cde-4952-aa46-6c683d7b41a7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988525514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3988525514
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2534154130
Short name T884
Test name
Test status
Simulation time 138418706 ps
CPU time 3.53 seconds
Started May 04 03:48:30 PM PDT 24
Finished May 04 03:48:34 PM PDT 24
Peak memory 208552 kb
Host smart-715071e8-3dd4-4ab5-ae3c-2dc2252a52ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534154130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2534154130
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2946228009
Short name T932
Test name
Test status
Simulation time 40314421 ps
CPU time 2.32 seconds
Started May 04 03:48:35 PM PDT 24
Finished May 04 03:48:38 PM PDT 24
Peak memory 209064 kb
Host smart-f7ba5e20-e2fb-4b6a-a581-4e6a87177e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946228009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2946228009
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.949881532
Short name T669
Test name
Test status
Simulation time 98293901 ps
CPU time 3.32 seconds
Started May 04 03:48:30 PM PDT 24
Finished May 04 03:48:33 PM PDT 24
Peak memory 208316 kb
Host smart-175e7cbc-6a0a-4443-8a78-9c58a2604838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949881532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.949881532
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3411035261
Short name T322
Test name
Test status
Simulation time 3392248391 ps
CPU time 30.69 seconds
Started May 04 03:48:34 PM PDT 24
Finished May 04 03:49:05 PM PDT 24
Peak memory 222476 kb
Host smart-7871955e-6a4e-4006-8b02-4387d74617f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411035261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3411035261
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3816255545
Short name T677
Test name
Test status
Simulation time 981961606 ps
CPU time 6.5 seconds
Started May 04 03:48:43 PM PDT 24
Finished May 04 03:48:49 PM PDT 24
Peak memory 222552 kb
Host smart-22f2ad48-c115-4f01-bb14-af9ce866bd46
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816255545 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3816255545
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1142220036
Short name T86
Test name
Test status
Simulation time 71274823 ps
CPU time 3.49 seconds
Started May 04 03:48:31 PM PDT 24
Finished May 04 03:48:35 PM PDT 24
Peak memory 208604 kb
Host smart-b56ee57a-0d89-4061-a20f-f8fef439b29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142220036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1142220036
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.939489124
Short name T1061
Test name
Test status
Simulation time 70478269 ps
CPU time 3.06 seconds
Started May 04 03:48:34 PM PDT 24
Finished May 04 03:48:37 PM PDT 24
Peak memory 209880 kb
Host smart-84ab30ca-82c6-498f-963d-b9435e98df0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939489124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.939489124
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.664153941
Short name T882
Test name
Test status
Simulation time 24386231 ps
CPU time 0.81 seconds
Started May 04 03:48:35 PM PDT 24
Finished May 04 03:48:37 PM PDT 24
Peak memory 205820 kb
Host smart-77a95bb3-3277-44e5-9741-a83c3fcee898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664153941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.664153941
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.722506740
Short name T245
Test name
Test status
Simulation time 974100693 ps
CPU time 13.86 seconds
Started May 04 03:48:36 PM PDT 24
Finished May 04 03:48:51 PM PDT 24
Peak memory 215584 kb
Host smart-16d33b0d-ecb8-4caf-a8eb-ff1a885c0942
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=722506740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.722506740
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2689260981
Short name T34
Test name
Test status
Simulation time 403872140 ps
CPU time 11.57 seconds
Started May 04 03:48:41 PM PDT 24
Finished May 04 03:48:53 PM PDT 24
Peak memory 222792 kb
Host smart-8a1e8e90-4dd8-4381-b773-613c9b6913cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689260981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2689260981
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.4043757046
Short name T601
Test name
Test status
Simulation time 62039187 ps
CPU time 2.39 seconds
Started May 04 03:48:36 PM PDT 24
Finished May 04 03:48:39 PM PDT 24
Peak memory 218480 kb
Host smart-37e8ec99-a1b0-439e-899d-e8ea968e239f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043757046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.4043757046
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.4122965105
Short name T1028
Test name
Test status
Simulation time 268351018 ps
CPU time 7.81 seconds
Started May 04 03:48:35 PM PDT 24
Finished May 04 03:48:44 PM PDT 24
Peak memory 214280 kb
Host smart-7390a6ad-bdd3-481e-af37-8e50ce8ce067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122965105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.4122965105
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.4148290009
Short name T67
Test name
Test status
Simulation time 75775912 ps
CPU time 3.37 seconds
Started May 04 03:48:41 PM PDT 24
Finished May 04 03:48:45 PM PDT 24
Peak memory 222556 kb
Host smart-e51b77c7-8a22-4715-bb51-989295715ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148290009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.4148290009
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3602020895
Short name T870
Test name
Test status
Simulation time 2395227721 ps
CPU time 17.45 seconds
Started May 04 03:48:35 PM PDT 24
Finished May 04 03:48:53 PM PDT 24
Peak memory 218396 kb
Host smart-29cf9481-d613-4886-84e2-f045200251a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602020895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3602020895
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.376604215
Short name T40
Test name
Test status
Simulation time 202160025 ps
CPU time 2.8 seconds
Started May 04 03:48:36 PM PDT 24
Finished May 04 03:48:40 PM PDT 24
Peak memory 206820 kb
Host smart-5e4a2f57-0d8b-45d2-ae99-e527d79bd4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376604215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.376604215
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2300720848
Short name T767
Test name
Test status
Simulation time 130726842 ps
CPU time 4.28 seconds
Started May 04 03:48:38 PM PDT 24
Finished May 04 03:48:43 PM PDT 24
Peak memory 206912 kb
Host smart-341160f6-98b2-4c03-932e-a542370b09fe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300720848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2300720848
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.732061170
Short name T338
Test name
Test status
Simulation time 39304831 ps
CPU time 2.54 seconds
Started May 04 03:48:37 PM PDT 24
Finished May 04 03:48:41 PM PDT 24
Peak memory 207388 kb
Host smart-e30f985d-201d-47a5-bbaf-233b59bbded4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732061170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.732061170
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1909191228
Short name T857
Test name
Test status
Simulation time 127547252 ps
CPU time 4.49 seconds
Started May 04 03:48:37 PM PDT 24
Finished May 04 03:48:42 PM PDT 24
Peak memory 208620 kb
Host smart-9cfc00f7-7e71-431f-9eea-3e326c3a99f6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909191228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1909191228
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1518192361
Short name T246
Test name
Test status
Simulation time 100448281 ps
CPU time 3.55 seconds
Started May 04 03:48:37 PM PDT 24
Finished May 04 03:48:41 PM PDT 24
Peak memory 214288 kb
Host smart-70f9660e-1d33-48a0-9d12-b349dc80d253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518192361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1518192361
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.948954921
Short name T792
Test name
Test status
Simulation time 207673416 ps
CPU time 4.46 seconds
Started May 04 03:48:34 PM PDT 24
Finished May 04 03:48:40 PM PDT 24
Peak memory 207352 kb
Host smart-54358733-1206-4616-9e21-ce32ef1b1237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948954921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.948954921
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.4146768035
Short name T325
Test name
Test status
Simulation time 564685248 ps
CPU time 28.46 seconds
Started May 04 03:48:37 PM PDT 24
Finished May 04 03:49:06 PM PDT 24
Peak memory 215708 kb
Host smart-0aeb9d16-f098-4ab6-afcd-1c5299321af2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146768035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.4146768035
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1974940922
Short name T746
Test name
Test status
Simulation time 50199327 ps
CPU time 2.95 seconds
Started May 04 03:48:37 PM PDT 24
Finished May 04 03:48:40 PM PDT 24
Peak memory 217544 kb
Host smart-625e5975-2e5f-43c9-a3c3-419ccfbe9d98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974940922 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1974940922
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.4027746255
Short name T253
Test name
Test status
Simulation time 65350579 ps
CPU time 4 seconds
Started May 04 03:48:41 PM PDT 24
Finished May 04 03:48:46 PM PDT 24
Peak memory 210376 kb
Host smart-4bb9e2ba-99e7-479d-a546-171035f47841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027746255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.4027746255
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3988304472
Short name T582
Test name
Test status
Simulation time 92052685 ps
CPU time 2.8 seconds
Started May 04 03:48:36 PM PDT 24
Finished May 04 03:48:39 PM PDT 24
Peak memory 210048 kb
Host smart-74658fdb-c823-41a3-9821-ee86f85f4c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988304472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3988304472
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3942944584
Short name T754
Test name
Test status
Simulation time 53713213 ps
CPU time 0.77 seconds
Started May 04 03:48:43 PM PDT 24
Finished May 04 03:48:44 PM PDT 24
Peak memory 205872 kb
Host smart-eb07252e-2b3c-4341-b1cf-31feba4ecf72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942944584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3942944584
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1226417850
Short name T11
Test name
Test status
Simulation time 68865433 ps
CPU time 2.86 seconds
Started May 04 03:48:43 PM PDT 24
Finished May 04 03:48:46 PM PDT 24
Peak memory 207684 kb
Host smart-0a8dc21a-9491-433a-8930-a7008e51bf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226417850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1226417850
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.1180285630
Short name T75
Test name
Test status
Simulation time 376813748 ps
CPU time 11.58 seconds
Started May 04 03:48:41 PM PDT 24
Finished May 04 03:48:53 PM PDT 24
Peak memory 209400 kb
Host smart-bc7852da-d8ad-4fc1-a465-7a3fe62bd011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180285630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.1180285630
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3853307022
Short name T1060
Test name
Test status
Simulation time 793689197 ps
CPU time 5.31 seconds
Started May 04 03:48:41 PM PDT 24
Finished May 04 03:48:47 PM PDT 24
Peak memory 214296 kb
Host smart-991a4ed4-c4b0-48d2-821b-e6b79864d040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853307022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3853307022
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.825291770
Short name T369
Test name
Test status
Simulation time 54232401 ps
CPU time 3.32 seconds
Started May 04 03:48:40 PM PDT 24
Finished May 04 03:48:45 PM PDT 24
Peak memory 211484 kb
Host smart-29ee6667-fabd-416e-9ba3-c13196736063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825291770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.825291770
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.4001579919
Short name T6
Test name
Test status
Simulation time 113322340 ps
CPU time 5.08 seconds
Started May 04 03:48:43 PM PDT 24
Finished May 04 03:48:48 PM PDT 24
Peak memory 222472 kb
Host smart-020cce55-f7ff-44ac-8c0e-18843fdb103d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001579919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.4001579919
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3821429393
Short name T1070
Test name
Test status
Simulation time 130986247 ps
CPU time 3.61 seconds
Started May 04 03:48:36 PM PDT 24
Finished May 04 03:48:40 PM PDT 24
Peak memory 207644 kb
Host smart-cc85b728-dbb1-4ab4-a49e-c52e85aaf0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821429393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3821429393
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3067871087
Short name T329
Test name
Test status
Simulation time 170314735 ps
CPU time 5.05 seconds
Started May 04 03:48:35 PM PDT 24
Finished May 04 03:48:40 PM PDT 24
Peak memory 208336 kb
Host smart-4ade3057-5f47-453d-92e7-71b9f68273f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067871087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3067871087
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2090770828
Short name T853
Test name
Test status
Simulation time 498475081 ps
CPU time 4.33 seconds
Started May 04 03:48:37 PM PDT 24
Finished May 04 03:48:42 PM PDT 24
Peak memory 208644 kb
Host smart-59cfdf6a-ea66-4397-9a06-1b800d1b0075
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090770828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2090770828
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.3147589810
Short name T106
Test name
Test status
Simulation time 44329299 ps
CPU time 1.87 seconds
Started May 04 03:48:42 PM PDT 24
Finished May 04 03:48:44 PM PDT 24
Peak memory 207164 kb
Host smart-9d73eff9-14f2-4cf8-9036-842e2f4a0b4e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147589810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.3147589810
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.3014808148
Short name T1052
Test name
Test status
Simulation time 138764333 ps
CPU time 4.41 seconds
Started May 04 03:48:37 PM PDT 24
Finished May 04 03:48:42 PM PDT 24
Peak memory 206692 kb
Host smart-24a4821d-1c92-4d82-b2a4-845dc81ab6f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014808148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.3014808148
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1278697402
Short name T41
Test name
Test status
Simulation time 34754195 ps
CPU time 1.61 seconds
Started May 04 03:48:43 PM PDT 24
Finished May 04 03:48:46 PM PDT 24
Peak memory 207788 kb
Host smart-7d459e16-d8a7-4c8d-beae-fd38c9c9b230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278697402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1278697402
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3704215091
Short name T564
Test name
Test status
Simulation time 929557448 ps
CPU time 19.38 seconds
Started May 04 03:48:38 PM PDT 24
Finished May 04 03:48:58 PM PDT 24
Peak memory 208768 kb
Host smart-30feaa88-191b-40d8-91e4-272c11ff06b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704215091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3704215091
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.298773297
Short name T992
Test name
Test status
Simulation time 191706545 ps
CPU time 13.27 seconds
Started May 04 03:48:43 PM PDT 24
Finished May 04 03:48:57 PM PDT 24
Peak memory 220896 kb
Host smart-ca102be8-d0ec-4a58-8a14-087ed7d99c7c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298773297 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.298773297
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.347879350
Short name T949
Test name
Test status
Simulation time 67079471 ps
CPU time 2.57 seconds
Started May 04 03:48:42 PM PDT 24
Finished May 04 03:48:45 PM PDT 24
Peak memory 207612 kb
Host smart-860b4249-4c59-47a9-b76f-fe8c6e04a383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347879350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.347879350
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1050090739
Short name T885
Test name
Test status
Simulation time 77087407 ps
CPU time 2.71 seconds
Started May 04 03:48:41 PM PDT 24
Finished May 04 03:48:44 PM PDT 24
Peak memory 210300 kb
Host smart-140deb2c-61dd-45e5-b36c-52d55df4d052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050090739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1050090739
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3927982321
Short name T917
Test name
Test status
Simulation time 60137999 ps
CPU time 0.87 seconds
Started May 04 03:48:45 PM PDT 24
Finished May 04 03:48:46 PM PDT 24
Peak memory 205852 kb
Host smart-7ffd08c7-2546-4855-a2e5-aab890362f4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927982321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3927982321
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3168605680
Short name T420
Test name
Test status
Simulation time 132054217 ps
CPU time 7.07 seconds
Started May 04 03:48:47 PM PDT 24
Finished May 04 03:48:55 PM PDT 24
Peak memory 214308 kb
Host smart-f3754036-c1c2-41f4-81c9-d87e363cd614
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3168605680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3168605680
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.4156908569
Short name T215
Test name
Test status
Simulation time 193790190 ps
CPU time 2.34 seconds
Started May 04 03:48:44 PM PDT 24
Finished May 04 03:48:47 PM PDT 24
Peak memory 208768 kb
Host smart-eb95e448-6a52-4014-8e86-c4cf8530b682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156908569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.4156908569
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2096198380
Short name T847
Test name
Test status
Simulation time 667791904 ps
CPU time 16.37 seconds
Started May 04 03:48:46 PM PDT 24
Finished May 04 03:49:03 PM PDT 24
Peak memory 218136 kb
Host smart-1541181c-2573-4bf6-856d-6eb2494b14bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096198380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2096198380
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3290974018
Short name T651
Test name
Test status
Simulation time 1278698820 ps
CPU time 39.48 seconds
Started May 04 03:48:47 PM PDT 24
Finished May 04 03:49:27 PM PDT 24
Peak memory 214312 kb
Host smart-e78fc86a-029b-4696-816d-c33c277bc945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290974018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3290974018
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.839735148
Short name T261
Test name
Test status
Simulation time 1530070389 ps
CPU time 10.32 seconds
Started May 04 03:48:45 PM PDT 24
Finished May 04 03:48:56 PM PDT 24
Peak memory 211548 kb
Host smart-5910b408-cd06-47bb-be37-03d19f02f487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839735148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.839735148
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.83161039
Short name T661
Test name
Test status
Simulation time 111240018 ps
CPU time 4.23 seconds
Started May 04 03:48:47 PM PDT 24
Finished May 04 03:48:52 PM PDT 24
Peak memory 210460 kb
Host smart-a6cfd846-19e8-484e-914c-094334e8896d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83161039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.83161039
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1734340148
Short name T983
Test name
Test status
Simulation time 1999536874 ps
CPU time 37.47 seconds
Started May 04 03:48:46 PM PDT 24
Finished May 04 03:49:24 PM PDT 24
Peak memory 219748 kb
Host smart-2e603f7d-ba78-4071-97b2-f27b7bef45f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734340148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1734340148
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1203888923
Short name T989
Test name
Test status
Simulation time 56779965 ps
CPU time 2.96 seconds
Started May 04 03:48:42 PM PDT 24
Finished May 04 03:48:46 PM PDT 24
Peak memory 208540 kb
Host smart-eeb9c076-39c4-4ed1-bf5a-06c4f840e84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203888923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1203888923
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2583048618
Short name T85
Test name
Test status
Simulation time 130526436 ps
CPU time 3.3 seconds
Started May 04 03:48:43 PM PDT 24
Finished May 04 03:48:47 PM PDT 24
Peak memory 207552 kb
Host smart-587412b3-b513-41ea-b674-05f0f8156b6d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583048618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2583048618
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2560915900
Short name T382
Test name
Test status
Simulation time 1084050321 ps
CPU time 8.9 seconds
Started May 04 03:48:42 PM PDT 24
Finished May 04 03:48:51 PM PDT 24
Peak memory 207716 kb
Host smart-6c93b40f-07f3-4f88-abe5-386f02b2356a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560915900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2560915900
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.310171346
Short name T281
Test name
Test status
Simulation time 139561925 ps
CPU time 4.59 seconds
Started May 04 03:48:46 PM PDT 24
Finished May 04 03:48:51 PM PDT 24
Peak memory 208616 kb
Host smart-9613a892-e816-446e-b81e-134fb562041f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310171346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.310171346
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.121684169
Short name T297
Test name
Test status
Simulation time 573811964 ps
CPU time 7.54 seconds
Started May 04 03:48:46 PM PDT 24
Finished May 04 03:48:54 PM PDT 24
Peak memory 210032 kb
Host smart-86eba464-d4f6-4833-a394-e1a7d9525568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121684169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.121684169
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1794658137
Short name T630
Test name
Test status
Simulation time 1097486036 ps
CPU time 18.12 seconds
Started May 04 03:48:40 PM PDT 24
Finished May 04 03:48:59 PM PDT 24
Peak memory 208256 kb
Host smart-fece6168-f042-4186-bcc2-41d32c87286a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794658137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1794658137
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2974257674
Short name T284
Test name
Test status
Simulation time 145591689 ps
CPU time 10.37 seconds
Started May 04 03:48:46 PM PDT 24
Finished May 04 03:48:57 PM PDT 24
Peak memory 220112 kb
Host smart-0715996e-8ec4-4783-972d-96f894e45cc5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974257674 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2974257674
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.2413415346
Short name T889
Test name
Test status
Simulation time 434707639 ps
CPU time 5.47 seconds
Started May 04 03:48:45 PM PDT 24
Finished May 04 03:48:51 PM PDT 24
Peak memory 208240 kb
Host smart-8fd5e090-57a7-4d10-b680-67d49f2ce93d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413415346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.2413415346
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2076358658
Short name T52
Test name
Test status
Simulation time 156703194 ps
CPU time 1.9 seconds
Started May 04 03:48:46 PM PDT 24
Finished May 04 03:48:49 PM PDT 24
Peak memory 209796 kb
Host smart-dd59b740-58dc-44bc-b1b8-63d1dad5dbd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076358658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2076358658
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.207275046
Short name T622
Test name
Test status
Simulation time 40603063 ps
CPU time 0.84 seconds
Started May 04 03:48:57 PM PDT 24
Finished May 04 03:48:58 PM PDT 24
Peak memory 205844 kb
Host smart-a1c8ca9d-009c-4881-8af9-e4db6b3311d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207275046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.207275046
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.436628881
Short name T1005
Test name
Test status
Simulation time 46723445 ps
CPU time 2.5 seconds
Started May 04 03:48:56 PM PDT 24
Finished May 04 03:49:00 PM PDT 24
Peak memory 209528 kb
Host smart-0e9a7c60-9871-412f-9d48-ec2122ac8bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436628881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.436628881
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2170989416
Short name T1007
Test name
Test status
Simulation time 76362665 ps
CPU time 3.72 seconds
Started May 04 03:48:56 PM PDT 24
Finished May 04 03:49:01 PM PDT 24
Peak memory 219348 kb
Host smart-48c2aa48-724b-483e-9f7d-2ee748aae9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170989416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2170989416
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3504542795
Short name T1036
Test name
Test status
Simulation time 217252302 ps
CPU time 2.94 seconds
Started May 04 03:48:52 PM PDT 24
Finished May 04 03:48:56 PM PDT 24
Peak memory 222440 kb
Host smart-0eb4dba5-9da1-4b82-a9fc-ad2e17557d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504542795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3504542795
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3043312733
Short name T656
Test name
Test status
Simulation time 229777258 ps
CPU time 3.93 seconds
Started May 04 03:48:46 PM PDT 24
Finished May 04 03:48:51 PM PDT 24
Peak memory 208396 kb
Host smart-94943351-1290-43d3-b472-20246094064d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043312733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3043312733
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.419125325
Short name T583
Test name
Test status
Simulation time 43422356 ps
CPU time 2.66 seconds
Started May 04 03:48:57 PM PDT 24
Finished May 04 03:49:00 PM PDT 24
Peak memory 206968 kb
Host smart-6984686d-3712-4894-b963-5473d08cdede
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419125325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.419125325
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2895189399
Short name T313
Test name
Test status
Simulation time 678195407 ps
CPU time 3.02 seconds
Started May 04 03:48:58 PM PDT 24
Finished May 04 03:49:02 PM PDT 24
Peak memory 207328 kb
Host smart-1d23e6e7-8d94-4360-9613-29d6cbaa8955
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895189399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2895189399
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.4287298475
Short name T756
Test name
Test status
Simulation time 113246546 ps
CPU time 3.21 seconds
Started May 04 03:48:50 PM PDT 24
Finished May 04 03:48:53 PM PDT 24
Peak memory 208684 kb
Host smart-4912ac5f-cbd9-4b9b-9430-5f3710ca717f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287298475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.4287298475
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2324350801
Short name T225
Test name
Test status
Simulation time 195625170 ps
CPU time 3.05 seconds
Started May 04 03:48:56 PM PDT 24
Finished May 04 03:49:00 PM PDT 24
Peak memory 208688 kb
Host smart-e7463136-0395-4281-9b0d-2b60373529bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324350801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2324350801
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2621877686
Short name T883
Test name
Test status
Simulation time 5298221769 ps
CPU time 44.96 seconds
Started May 04 03:48:45 PM PDT 24
Finished May 04 03:49:31 PM PDT 24
Peak memory 208300 kb
Host smart-1f556d65-b0f0-43a2-b580-20b6d86a3c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621877686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2621877686
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.992337627
Short name T391
Test name
Test status
Simulation time 32936117096 ps
CPU time 96.6 seconds
Started May 04 03:48:52 PM PDT 24
Finished May 04 03:50:29 PM PDT 24
Peak memory 217104 kb
Host smart-d6ff5498-66f4-4174-8885-c75b88e640a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992337627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.992337627
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3192070319
Short name T604
Test name
Test status
Simulation time 128785905 ps
CPU time 4.42 seconds
Started May 04 03:48:55 PM PDT 24
Finished May 04 03:49:00 PM PDT 24
Peak memory 220784 kb
Host smart-2b1211da-05d1-45c0-bfc8-76f5220f0602
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192070319 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3192070319
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2350948109
Short name T811
Test name
Test status
Simulation time 106731129 ps
CPU time 5.63 seconds
Started May 04 03:49:04 PM PDT 24
Finished May 04 03:49:10 PM PDT 24
Peak memory 209092 kb
Host smart-ab14f3ea-07b6-4548-bc7c-63006d8e7a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350948109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2350948109
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1763282676
Short name T1014
Test name
Test status
Simulation time 41776497 ps
CPU time 2.41 seconds
Started May 04 03:48:58 PM PDT 24
Finished May 04 03:49:00 PM PDT 24
Peak memory 210012 kb
Host smart-cc8f8276-a28e-4022-86ce-b3cb1ce6172a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763282676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1763282676
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1788442175
Short name T817
Test name
Test status
Simulation time 17162992 ps
CPU time 0.79 seconds
Started May 04 03:46:17 PM PDT 24
Finished May 04 03:46:19 PM PDT 24
Peak memory 205888 kb
Host smart-3f0da6db-be76-44f1-826d-6b5ad01addbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788442175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1788442175
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3734401161
Short name T27
Test name
Test status
Simulation time 212982614 ps
CPU time 3.43 seconds
Started May 04 03:46:17 PM PDT 24
Finished May 04 03:46:21 PM PDT 24
Peak memory 209896 kb
Host smart-e8ce2b9b-6efc-4de5-94f9-503c27633387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734401161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3734401161
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.446524347
Short name T829
Test name
Test status
Simulation time 737126516 ps
CPU time 5.51 seconds
Started May 04 03:46:11 PM PDT 24
Finished May 04 03:46:17 PM PDT 24
Peak memory 209252 kb
Host smart-771062cb-2e18-49b7-a815-deee66ea780e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446524347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.446524347
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3789451457
Short name T881
Test name
Test status
Simulation time 798442913 ps
CPU time 5.08 seconds
Started May 04 03:46:17 PM PDT 24
Finished May 04 03:46:23 PM PDT 24
Peak memory 219680 kb
Host smart-ac2629b5-8edf-4937-8531-1408fcc6aeac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789451457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3789451457
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1846795920
Short name T292
Test name
Test status
Simulation time 813389238 ps
CPU time 2.99 seconds
Started May 04 03:46:19 PM PDT 24
Finished May 04 03:46:22 PM PDT 24
Peak memory 222308 kb
Host smart-1c849ce1-14f3-4bb5-a4fa-c2b4537caa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846795920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1846795920
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1207443971
Short name T55
Test name
Test status
Simulation time 432449240 ps
CPU time 12.18 seconds
Started May 04 03:46:14 PM PDT 24
Finished May 04 03:46:26 PM PDT 24
Peak memory 218388 kb
Host smart-247283bc-e03f-4da0-b938-22443496d5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207443971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1207443971
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.106597165
Short name T623
Test name
Test status
Simulation time 794815929 ps
CPU time 4.59 seconds
Started May 04 03:46:13 PM PDT 24
Finished May 04 03:46:18 PM PDT 24
Peak memory 209296 kb
Host smart-618bff1f-cc9f-44c1-be1e-ba7cc2cfd45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106597165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.106597165
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3033022226
Short name T104
Test name
Test status
Simulation time 10258871285 ps
CPU time 50.66 seconds
Started May 04 03:46:19 PM PDT 24
Finished May 04 03:47:10 PM PDT 24
Peak memory 239408 kb
Host smart-05e05629-14b7-4414-9c5d-b203b462b995
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033022226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3033022226
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.849184918
Short name T785
Test name
Test status
Simulation time 4868963587 ps
CPU time 53.87 seconds
Started May 04 03:46:12 PM PDT 24
Finished May 04 03:47:06 PM PDT 24
Peak memory 208560 kb
Host smart-711ee810-1312-45c6-8661-55be5827edd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849184918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.849184918
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.19769576
Short name T724
Test name
Test status
Simulation time 50427221 ps
CPU time 2.73 seconds
Started May 04 03:46:12 PM PDT 24
Finished May 04 03:46:15 PM PDT 24
Peak memory 206840 kb
Host smart-163202f4-e962-4822-bba1-f778f6908e73
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19769576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.19769576
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1262727466
Short name T962
Test name
Test status
Simulation time 1034330743 ps
CPU time 8.1 seconds
Started May 04 03:46:12 PM PDT 24
Finished May 04 03:46:20 PM PDT 24
Peak memory 208364 kb
Host smart-13c4f4d3-5de5-4668-99df-7cede25bbe64
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262727466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1262727466
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.777201204
Short name T852
Test name
Test status
Simulation time 22438828261 ps
CPU time 72.82 seconds
Started May 04 03:46:12 PM PDT 24
Finished May 04 03:47:25 PM PDT 24
Peak memory 208996 kb
Host smart-2b6cf8b5-adbd-4980-a82f-d3d3c2e8539b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777201204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.777201204
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.317915173
Short name T1045
Test name
Test status
Simulation time 2523300285 ps
CPU time 25.62 seconds
Started May 04 03:46:21 PM PDT 24
Finished May 04 03:46:47 PM PDT 24
Peak memory 220628 kb
Host smart-aa1ab629-ced2-4678-a4fd-ac08e84d33ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317915173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.317915173
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.909592169
Short name T568
Test name
Test status
Simulation time 76100737 ps
CPU time 2.3 seconds
Started May 04 03:46:12 PM PDT 24
Finished May 04 03:46:15 PM PDT 24
Peak memory 207132 kb
Host smart-0c76ee39-fee4-48a1-8ba2-a84d5016e885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909592169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.909592169
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.24593993
Short name T254
Test name
Test status
Simulation time 5524351769 ps
CPU time 42.09 seconds
Started May 04 03:46:19 PM PDT 24
Finished May 04 03:47:01 PM PDT 24
Peak memory 215744 kb
Host smart-5970376e-02c6-4675-a204-384946bf10cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24593993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.24593993
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2909627476
Short name T324
Test name
Test status
Simulation time 395790097 ps
CPU time 14.63 seconds
Started May 04 03:46:18 PM PDT 24
Finished May 04 03:46:33 PM PDT 24
Peak memory 210276 kb
Host smart-791dee0d-57df-4a01-b005-71106b4fa83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909627476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2909627476
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.177811189
Short name T406
Test name
Test status
Simulation time 79882331 ps
CPU time 2.01 seconds
Started May 04 03:46:20 PM PDT 24
Finished May 04 03:46:22 PM PDT 24
Peak memory 210320 kb
Host smart-9f5d0de6-2576-4092-adf5-7401aa48827e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177811189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.177811189
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.388489408
Short name T957
Test name
Test status
Simulation time 13195243 ps
CPU time 0.74 seconds
Started May 04 03:48:56 PM PDT 24
Finished May 04 03:48:57 PM PDT 24
Peak memory 205844 kb
Host smart-eb7048d9-fdb3-4430-8c8a-4e70c43297bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388489408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.388489408
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1406139831
Short name T1001
Test name
Test status
Simulation time 71612617 ps
CPU time 4.02 seconds
Started May 04 03:49:04 PM PDT 24
Finished May 04 03:49:08 PM PDT 24
Peak memory 209556 kb
Host smart-be087041-7503-41e3-a68d-29f41a3ada96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406139831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1406139831
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.3346915893
Short name T831
Test name
Test status
Simulation time 3456104731 ps
CPU time 9.68 seconds
Started May 04 03:49:04 PM PDT 24
Finished May 04 03:49:14 PM PDT 24
Peak memory 210372 kb
Host smart-048fccc1-7b90-4a3f-9f96-166247c6de04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346915893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.3346915893
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3999448817
Short name T813
Test name
Test status
Simulation time 94071512 ps
CPU time 3.32 seconds
Started May 04 03:48:56 PM PDT 24
Finished May 04 03:48:59 PM PDT 24
Peak memory 208996 kb
Host smart-056cf261-4358-4209-808b-a30b11186022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999448817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3999448817
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1707097337
Short name T334
Test name
Test status
Simulation time 982354369 ps
CPU time 8.37 seconds
Started May 04 03:48:58 PM PDT 24
Finished May 04 03:49:07 PM PDT 24
Peak memory 222508 kb
Host smart-ed7993e6-23b3-40d8-be44-add78b7b1271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707097337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1707097337
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3064167165
Short name T974
Test name
Test status
Simulation time 611532337 ps
CPU time 5.01 seconds
Started May 04 03:48:56 PM PDT 24
Finished May 04 03:49:01 PM PDT 24
Peak memory 220096 kb
Host smart-c9c402df-75d9-42ee-b8ea-96f8c0e6c294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064167165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3064167165
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.4124663239
Short name T1035
Test name
Test status
Simulation time 429835784 ps
CPU time 5.33 seconds
Started May 04 03:48:56 PM PDT 24
Finished May 04 03:49:02 PM PDT 24
Peak memory 208536 kb
Host smart-4f3fc8f1-6091-44b2-8107-f40ffab79303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124663239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.4124663239
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2383385650
Short name T775
Test name
Test status
Simulation time 2768055117 ps
CPU time 32.05 seconds
Started May 04 03:48:56 PM PDT 24
Finished May 04 03:49:29 PM PDT 24
Peak memory 208116 kb
Host smart-655b1491-7c6d-4658-8015-5ead8fbd37a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383385650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2383385650
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2752970366
Short name T710
Test name
Test status
Simulation time 3476758657 ps
CPU time 6.99 seconds
Started May 04 03:49:04 PM PDT 24
Finished May 04 03:49:12 PM PDT 24
Peak memory 208812 kb
Host smart-c27cc0c1-7b35-4961-9ac6-d76629774beb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752970366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2752970366
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3969527602
Short name T1073
Test name
Test status
Simulation time 162661574 ps
CPU time 3.16 seconds
Started May 04 03:48:59 PM PDT 24
Finished May 04 03:49:03 PM PDT 24
Peak memory 206928 kb
Host smart-22b38b09-63d4-4dd6-987f-6a88816cd03d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969527602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3969527602
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.709141900
Short name T753
Test name
Test status
Simulation time 434788393 ps
CPU time 5.76 seconds
Started May 04 03:48:58 PM PDT 24
Finished May 04 03:49:04 PM PDT 24
Peak memory 206844 kb
Host smart-a2cad42e-31fa-4656-9efb-ef993518c5be
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709141900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.709141900
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.36817968
Short name T226
Test name
Test status
Simulation time 142856998 ps
CPU time 2.21 seconds
Started May 04 03:48:58 PM PDT 24
Finished May 04 03:49:01 PM PDT 24
Peak memory 215636 kb
Host smart-82c23dc6-aad2-440b-9dee-304be5d3f1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36817968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.36817968
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3212995922
Short name T695
Test name
Test status
Simulation time 1608161157 ps
CPU time 4.21 seconds
Started May 04 03:49:03 PM PDT 24
Finished May 04 03:49:08 PM PDT 24
Peak memory 207116 kb
Host smart-b001706e-1917-4bae-8be0-45a72a17f476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212995922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3212995922
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2673766445
Short name T3
Test name
Test status
Simulation time 135066204 ps
CPU time 3.49 seconds
Started May 04 03:48:57 PM PDT 24
Finished May 04 03:49:01 PM PDT 24
Peak memory 222680 kb
Host smart-6233bcc8-a908-427a-8c0a-d7630de12ce9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673766445 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2673766445
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1872007771
Short name T272
Test name
Test status
Simulation time 512139783 ps
CPU time 8.33 seconds
Started May 04 03:49:04 PM PDT 24
Finished May 04 03:49:12 PM PDT 24
Peak memory 218256 kb
Host smart-fc5c5c24-183b-4639-8c28-43848666a2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872007771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1872007771
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1611998514
Short name T671
Test name
Test status
Simulation time 75139652 ps
CPU time 3.06 seconds
Started May 04 03:48:57 PM PDT 24
Finished May 04 03:49:01 PM PDT 24
Peak memory 210200 kb
Host smart-58f07a98-634d-4eec-a4e5-3585898b100c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611998514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1611998514
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2260074021
Short name T99
Test name
Test status
Simulation time 14891772 ps
CPU time 1 seconds
Started May 04 03:49:04 PM PDT 24
Finished May 04 03:49:06 PM PDT 24
Peak memory 205980 kb
Host smart-604b7516-5b94-4042-91d0-3b4556543839
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260074021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2260074021
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1224442298
Short name T33
Test name
Test status
Simulation time 169109402 ps
CPU time 2.74 seconds
Started May 04 03:49:04 PM PDT 24
Finished May 04 03:49:08 PM PDT 24
Peak memory 215304 kb
Host smart-4afdb791-e72d-493f-80f8-68df7046e8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224442298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1224442298
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2270754836
Short name T958
Test name
Test status
Simulation time 2288953175 ps
CPU time 13.53 seconds
Started May 04 03:49:07 PM PDT 24
Finished May 04 03:49:20 PM PDT 24
Peak memory 208416 kb
Host smart-6606e930-47b7-4bab-8121-bee95a144f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270754836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2270754836
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2157092944
Short name T347
Test name
Test status
Simulation time 124043865 ps
CPU time 5.81 seconds
Started May 04 03:49:06 PM PDT 24
Finished May 04 03:49:12 PM PDT 24
Peak memory 220472 kb
Host smart-a05d0ec4-df80-44e9-829f-8298d746a4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157092944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2157092944
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3450766356
Short name T43
Test name
Test status
Simulation time 44845507 ps
CPU time 2.65 seconds
Started May 04 03:49:06 PM PDT 24
Finished May 04 03:49:09 PM PDT 24
Peak memory 209420 kb
Host smart-97246d0a-aca0-4d42-8ce2-e0188249971c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450766356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3450766356
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2902145553
Short name T826
Test name
Test status
Simulation time 2399312539 ps
CPU time 54.52 seconds
Started May 04 03:49:07 PM PDT 24
Finished May 04 03:50:02 PM PDT 24
Peak memory 209200 kb
Host smart-e465d544-6f61-4942-a2e7-5135f57d37c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902145553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2902145553
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4031871727
Short name T270
Test name
Test status
Simulation time 274839219 ps
CPU time 1.99 seconds
Started May 04 03:48:59 PM PDT 24
Finished May 04 03:49:02 PM PDT 24
Peak memory 207632 kb
Host smart-7d47170a-af0d-46d8-aa8a-8db5ca740042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031871727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4031871727
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1861790645
Short name T240
Test name
Test status
Simulation time 101764663 ps
CPU time 4.12 seconds
Started May 04 03:48:57 PM PDT 24
Finished May 04 03:49:02 PM PDT 24
Peak memory 208636 kb
Host smart-f97dd9b9-1c3d-4942-b887-930b62741fbd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861790645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1861790645
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2028960711
Short name T727
Test name
Test status
Simulation time 105569985 ps
CPU time 2.4 seconds
Started May 04 03:48:58 PM PDT 24
Finished May 04 03:49:01 PM PDT 24
Peak memory 206848 kb
Host smart-f7ba7b1e-5a91-4abe-8e46-59f20e5722a5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028960711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2028960711
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3610705948
Short name T138
Test name
Test status
Simulation time 564497054 ps
CPU time 6.6 seconds
Started May 04 03:49:02 PM PDT 24
Finished May 04 03:49:10 PM PDT 24
Peak memory 209168 kb
Host smart-74ce6219-5f97-42dd-ba2e-a68a3a1261e6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610705948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3610705948
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3948940750
Short name T184
Test name
Test status
Simulation time 175335299 ps
CPU time 6.85 seconds
Started May 04 03:49:02 PM PDT 24
Finished May 04 03:49:09 PM PDT 24
Peak memory 208056 kb
Host smart-e115b912-1ad9-4b0b-91a9-6724d21f1ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948940750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3948940750
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2278020501
Short name T797
Test name
Test status
Simulation time 124561334 ps
CPU time 3 seconds
Started May 04 03:48:59 PM PDT 24
Finished May 04 03:49:02 PM PDT 24
Peak memory 208452 kb
Host smart-427855ef-17c5-47cd-bbc6-bc518780d38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278020501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2278020501
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.938639729
Short name T308
Test name
Test status
Simulation time 7283272324 ps
CPU time 75.74 seconds
Started May 04 03:49:03 PM PDT 24
Finished May 04 03:50:20 PM PDT 24
Peak memory 217432 kb
Host smart-9ba155df-0c06-42c7-bfd7-0c27e7fbb093
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938639729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.938639729
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.88884253
Short name T751
Test name
Test status
Simulation time 175469458 ps
CPU time 4.64 seconds
Started May 04 03:49:05 PM PDT 24
Finished May 04 03:49:10 PM PDT 24
Peak memory 218608 kb
Host smart-3ebd6a8e-2e38-4b96-aade-6e1a2048718e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88884253 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.88884253
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.16986454
Short name T183
Test name
Test status
Simulation time 467304818 ps
CPU time 5.85 seconds
Started May 04 03:49:03 PM PDT 24
Finished May 04 03:49:10 PM PDT 24
Peak memory 209764 kb
Host smart-648ca1ab-9588-41f0-8579-bb81568288ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16986454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.16986454
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.943719955
Short name T63
Test name
Test status
Simulation time 360409735 ps
CPU time 3.94 seconds
Started May 04 03:49:08 PM PDT 24
Finished May 04 03:49:12 PM PDT 24
Peak memory 210300 kb
Host smart-d6edfcff-212b-4100-a0b4-2ce7d48eff1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943719955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.943719955
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3849047529
Short name T960
Test name
Test status
Simulation time 45259257 ps
CPU time 0.88 seconds
Started May 04 03:49:11 PM PDT 24
Finished May 04 03:49:12 PM PDT 24
Peak memory 205880 kb
Host smart-ad8f35d2-83be-4f01-9d72-a381c36c11a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849047529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3849047529
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1229294883
Short name T299
Test name
Test status
Simulation time 55593916 ps
CPU time 3.5 seconds
Started May 04 03:49:10 PM PDT 24
Finished May 04 03:49:14 PM PDT 24
Peak memory 215052 kb
Host smart-cd8b9840-64f1-46b5-a569-bd420019d6a1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1229294883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1229294883
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2718355675
Short name T904
Test name
Test status
Simulation time 86620680 ps
CPU time 2.83 seconds
Started May 04 03:49:09 PM PDT 24
Finished May 04 03:49:13 PM PDT 24
Peak memory 214404 kb
Host smart-c328dca9-7bd8-43e2-bcde-73022a430126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718355675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2718355675
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2687602099
Short name T348
Test name
Test status
Simulation time 428698118 ps
CPU time 5.66 seconds
Started May 04 03:49:08 PM PDT 24
Finished May 04 03:49:15 PM PDT 24
Peak memory 207428 kb
Host smart-8a2d82e7-d272-4e82-b081-e95e78c92a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687602099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2687602099
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3937215647
Short name T990
Test name
Test status
Simulation time 424595857 ps
CPU time 4.28 seconds
Started May 04 03:49:11 PM PDT 24
Finished May 04 03:49:15 PM PDT 24
Peak memory 219200 kb
Host smart-d28db717-2cd6-47d9-84c6-32790027a662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937215647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3937215647
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2630197023
Short name T91
Test name
Test status
Simulation time 51715169 ps
CPU time 3.43 seconds
Started May 04 03:49:09 PM PDT 24
Finished May 04 03:49:13 PM PDT 24
Peak memory 222472 kb
Host smart-019c9329-6ccc-4cf5-b250-6ca3abcdf573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630197023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2630197023
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3219713261
Short name T53
Test name
Test status
Simulation time 86887126 ps
CPU time 3.06 seconds
Started May 04 03:49:14 PM PDT 24
Finished May 04 03:49:17 PM PDT 24
Peak memory 207572 kb
Host smart-23bdbdf5-24a1-43a9-9c4f-5ba2188c3a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219713261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3219713261
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1380617652
Short name T950
Test name
Test status
Simulation time 6527753563 ps
CPU time 45.95 seconds
Started May 04 03:49:09 PM PDT 24
Finished May 04 03:49:56 PM PDT 24
Peak memory 209696 kb
Host smart-55fcd302-edfb-4e2b-8cc8-e6d1279df93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380617652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1380617652
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3082780288
Short name T931
Test name
Test status
Simulation time 24039855 ps
CPU time 1.88 seconds
Started May 04 03:49:05 PM PDT 24
Finished May 04 03:49:07 PM PDT 24
Peak memory 206880 kb
Host smart-aad81bed-0314-45fc-bbb3-f55775f9e64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082780288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3082780288
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.4155206701
Short name T905
Test name
Test status
Simulation time 3593028088 ps
CPU time 35.83 seconds
Started May 04 03:49:11 PM PDT 24
Finished May 04 03:49:48 PM PDT 24
Peak memory 208536 kb
Host smart-c95f7288-79a4-4630-8059-d4c551891013
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155206701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.4155206701
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2624760745
Short name T201
Test name
Test status
Simulation time 74438587 ps
CPU time 3.03 seconds
Started May 04 03:49:09 PM PDT 24
Finished May 04 03:49:13 PM PDT 24
Peak memory 206968 kb
Host smart-0b806d4b-7fea-4c43-bf9f-e1c3f7a963ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624760745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2624760745
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2620958262
Short name T569
Test name
Test status
Simulation time 29062265 ps
CPU time 2.29 seconds
Started May 04 03:49:11 PM PDT 24
Finished May 04 03:49:14 PM PDT 24
Peak memory 209000 kb
Host smart-f49f58cf-6715-4055-8547-fa40c4388dec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620958262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2620958262
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1136869133
Short name T304
Test name
Test status
Simulation time 921034410 ps
CPU time 6.89 seconds
Started May 04 03:49:11 PM PDT 24
Finished May 04 03:49:18 PM PDT 24
Peak memory 214320 kb
Host smart-80d6a370-f4af-4b67-af01-e1a879598eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136869133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1136869133
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1753875384
Short name T609
Test name
Test status
Simulation time 3578226653 ps
CPU time 40.95 seconds
Started May 04 03:49:05 PM PDT 24
Finished May 04 03:49:46 PM PDT 24
Peak memory 208792 kb
Host smart-6354268c-854b-42bb-8730-6192518c64fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753875384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1753875384
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1216902475
Short name T854
Test name
Test status
Simulation time 3680566846 ps
CPU time 97.46 seconds
Started May 04 03:49:10 PM PDT 24
Finished May 04 03:50:48 PM PDT 24
Peak memory 216276 kb
Host smart-05afc6fe-ec4c-4470-9b94-25005c3546af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216902475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1216902475
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.2618531190
Short name T1025
Test name
Test status
Simulation time 165698403 ps
CPU time 10.73 seconds
Started May 04 03:49:09 PM PDT 24
Finished May 04 03:49:20 PM PDT 24
Peak memory 222592 kb
Host smart-e5028db6-e2b7-482a-8602-3103b1ba6695
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618531190 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.2618531190
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.829291575
Short name T794
Test name
Test status
Simulation time 150232831 ps
CPU time 4.25 seconds
Started May 04 03:49:12 PM PDT 24
Finished May 04 03:49:17 PM PDT 24
Peak memory 208100 kb
Host smart-430f277f-8a4a-4ca1-acee-efd3dc667aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829291575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.829291575
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.119331649
Short name T795
Test name
Test status
Simulation time 93565282 ps
CPU time 1.66 seconds
Started May 04 03:49:10 PM PDT 24
Finished May 04 03:49:12 PM PDT 24
Peak memory 209696 kb
Host smart-c00b69f8-b4f9-4747-9ba4-61f6331d14ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119331649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.119331649
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2480732337
Short name T648
Test name
Test status
Simulation time 34157363 ps
CPU time 0.74 seconds
Started May 04 03:49:23 PM PDT 24
Finished May 04 03:49:24 PM PDT 24
Peak memory 205852 kb
Host smart-1b98706d-6a9d-4640-a661-347660bb26db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480732337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2480732337
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2134653718
Short name T317
Test name
Test status
Simulation time 95226573 ps
CPU time 2.76 seconds
Started May 04 03:49:10 PM PDT 24
Finished May 04 03:49:13 PM PDT 24
Peak memory 215268 kb
Host smart-3a6225fc-6f7b-40c4-b4f0-6d62d832eb52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2134653718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2134653718
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.310295754
Short name T823
Test name
Test status
Simulation time 125072233 ps
CPU time 2.79 seconds
Started May 04 03:49:09 PM PDT 24
Finished May 04 03:49:13 PM PDT 24
Peak memory 216532 kb
Host smart-de8c0d69-7ae8-4595-86a3-7789bb67629d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310295754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.310295754
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1563477809
Short name T314
Test name
Test status
Simulation time 36751346 ps
CPU time 2.31 seconds
Started May 04 03:49:10 PM PDT 24
Finished May 04 03:49:13 PM PDT 24
Peak memory 208944 kb
Host smart-ce3f9f7e-c8af-4814-960c-7e872e70aed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563477809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1563477809
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.110480465
Short name T239
Test name
Test status
Simulation time 203068916 ps
CPU time 3.41 seconds
Started May 04 03:49:11 PM PDT 24
Finished May 04 03:49:15 PM PDT 24
Peak memory 219164 kb
Host smart-719ce110-4b6d-4b5c-8116-bcc52ca02a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110480465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.110480465
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.697658272
Short name T199
Test name
Test status
Simulation time 143623954 ps
CPU time 4.75 seconds
Started May 04 03:49:09 PM PDT 24
Finished May 04 03:49:14 PM PDT 24
Peak memory 211208 kb
Host smart-db628e39-9a6e-4643-950f-66277e12f6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697658272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.697658272
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2746630611
Short name T670
Test name
Test status
Simulation time 537164121 ps
CPU time 2.77 seconds
Started May 04 03:49:10 PM PDT 24
Finished May 04 03:49:13 PM PDT 24
Peak memory 214300 kb
Host smart-c31eb3f9-ba09-4c42-bcdc-4cbfc26ec268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746630611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2746630611
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.4252264625
Short name T682
Test name
Test status
Simulation time 79924032 ps
CPU time 2.92 seconds
Started May 04 03:49:09 PM PDT 24
Finished May 04 03:49:13 PM PDT 24
Peak memory 207344 kb
Host smart-7506c6b7-b086-4bb0-860a-001ed1de3b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252264625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.4252264625
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.728371608
Short name T732
Test name
Test status
Simulation time 43416341 ps
CPU time 2.58 seconds
Started May 04 03:49:08 PM PDT 24
Finished May 04 03:49:11 PM PDT 24
Peak memory 208168 kb
Host smart-8a52e504-1df7-47e2-a292-c2694f097d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728371608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.728371608
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2478317484
Short name T103
Test name
Test status
Simulation time 733742618 ps
CPU time 7.55 seconds
Started May 04 03:49:11 PM PDT 24
Finished May 04 03:49:19 PM PDT 24
Peak memory 208988 kb
Host smart-93817f60-6b2e-42f5-9ee2-92a41a467834
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478317484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2478317484
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.465192025
Short name T627
Test name
Test status
Simulation time 210689743 ps
CPU time 2.99 seconds
Started May 04 03:49:13 PM PDT 24
Finished May 04 03:49:17 PM PDT 24
Peak memory 206956 kb
Host smart-c9523d4a-0d32-45ed-94a5-dcfc3537124a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465192025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.465192025
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3246761837
Short name T132
Test name
Test status
Simulation time 352799352 ps
CPU time 4.73 seconds
Started May 04 03:49:11 PM PDT 24
Finished May 04 03:49:16 PM PDT 24
Peak memory 206912 kb
Host smart-2d0d2cc4-7a69-4aa6-ba78-ec011799cfe2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246761837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3246761837
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.783376453
Short name T181
Test name
Test status
Simulation time 48391002 ps
CPU time 2.62 seconds
Started May 04 03:49:17 PM PDT 24
Finished May 04 03:49:21 PM PDT 24
Peak memory 209756 kb
Host smart-6683da05-ae77-4f32-a54f-ccd86cba301e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783376453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.783376453
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1812612739
Short name T394
Test name
Test status
Simulation time 552390317 ps
CPU time 5.38 seconds
Started May 04 03:49:08 PM PDT 24
Finished May 04 03:49:14 PM PDT 24
Peak memory 208544 kb
Host smart-f282bf3f-29c3-4b93-95fe-fcc3ee4c5b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812612739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1812612739
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1762034640
Short name T888
Test name
Test status
Simulation time 620348325 ps
CPU time 13.16 seconds
Started May 04 03:49:14 PM PDT 24
Finished May 04 03:49:28 PM PDT 24
Peak memory 220692 kb
Host smart-3fcb44cd-2140-41ed-ab0e-3e12c5fe0855
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762034640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1762034640
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2191708020
Short name T844
Test name
Test status
Simulation time 255003730 ps
CPU time 7.29 seconds
Started May 04 03:49:15 PM PDT 24
Finished May 04 03:49:23 PM PDT 24
Peak memory 220160 kb
Host smart-49bd6af4-f34b-476a-8de1-d6fb70df80ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191708020 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2191708020
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1298479363
Short name T988
Test name
Test status
Simulation time 161535204 ps
CPU time 2.88 seconds
Started May 04 03:49:09 PM PDT 24
Finished May 04 03:49:13 PM PDT 24
Peak memory 208188 kb
Host smart-c9a92517-569c-42d5-b2a8-a51760ec8afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298479363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1298479363
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2931855300
Short name T395
Test name
Test status
Simulation time 120375828 ps
CPU time 1.84 seconds
Started May 04 03:49:17 PM PDT 24
Finished May 04 03:49:19 PM PDT 24
Peak memory 209676 kb
Host smart-c9bb4c2e-7359-428c-92d6-b2843c3fabe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931855300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2931855300
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1060469221
Short name T101
Test name
Test status
Simulation time 42766796 ps
CPU time 0.76 seconds
Started May 04 03:49:14 PM PDT 24
Finished May 04 03:49:16 PM PDT 24
Peak memory 205864 kb
Host smart-65940e12-64d3-45c3-be8d-322cae68c11c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060469221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1060469221
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.531692032
Short name T69
Test name
Test status
Simulation time 145200964 ps
CPU time 3.64 seconds
Started May 04 03:49:16 PM PDT 24
Finished May 04 03:49:20 PM PDT 24
Peak memory 214556 kb
Host smart-7824bbc8-bd9c-46ad-aa23-573c0921b1c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531692032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.531692032
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2436175549
Short name T362
Test name
Test status
Simulation time 188546317 ps
CPU time 6.03 seconds
Started May 04 03:49:16 PM PDT 24
Finished May 04 03:49:23 PM PDT 24
Peak memory 207812 kb
Host smart-d7773d0a-4f23-469f-8ffa-6f48986c1bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436175549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2436175549
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3775497017
Short name T878
Test name
Test status
Simulation time 1141637924 ps
CPU time 8.94 seconds
Started May 04 03:49:16 PM PDT 24
Finished May 04 03:49:25 PM PDT 24
Peak memory 208876 kb
Host smart-e7bc0920-cb78-4190-8131-6082369cb0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775497017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3775497017
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3215338188
Short name T1030
Test name
Test status
Simulation time 332400751 ps
CPU time 3.58 seconds
Started May 04 03:49:15 PM PDT 24
Finished May 04 03:49:19 PM PDT 24
Peak memory 209944 kb
Host smart-51bce1f3-229a-4d32-950d-4dad4f4cfe4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215338188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3215338188
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.3125439095
Short name T287
Test name
Test status
Simulation time 336656150 ps
CPU time 3.86 seconds
Started May 04 03:49:23 PM PDT 24
Finished May 04 03:49:27 PM PDT 24
Peak memory 218372 kb
Host smart-515a10ff-fcc9-438a-87da-dc4ad7738567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125439095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.3125439095
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3377022338
Short name T319
Test name
Test status
Simulation time 214029323 ps
CPU time 3.88 seconds
Started May 04 03:49:15 PM PDT 24
Finished May 04 03:49:19 PM PDT 24
Peak memory 206916 kb
Host smart-f2a02c2e-7a4e-4d0c-b551-21c0b35d7f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377022338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3377022338
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.4042182540
Short name T849
Test name
Test status
Simulation time 1190060846 ps
CPU time 27.57 seconds
Started May 04 03:49:17 PM PDT 24
Finished May 04 03:49:45 PM PDT 24
Peak memory 208704 kb
Host smart-9ff40100-f59f-42b2-ab03-48a561b5a411
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042182540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.4042182540
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.4280749557
Short name T634
Test name
Test status
Simulation time 46812000 ps
CPU time 2.62 seconds
Started May 04 03:49:19 PM PDT 24
Finished May 04 03:49:22 PM PDT 24
Peak memory 206716 kb
Host smart-a788bb71-373f-42a2-af77-63e3be73e7b0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280749557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4280749557
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.822707874
Short name T1016
Test name
Test status
Simulation time 502473902 ps
CPU time 4.6 seconds
Started May 04 03:49:17 PM PDT 24
Finished May 04 03:49:22 PM PDT 24
Peak memory 208352 kb
Host smart-64b6b231-4f70-48cc-a20b-403b63aaae07
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822707874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.822707874
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2993626256
Short name T247
Test name
Test status
Simulation time 2138900012 ps
CPU time 13.1 seconds
Started May 04 03:49:15 PM PDT 24
Finished May 04 03:49:29 PM PDT 24
Peak memory 218244 kb
Host smart-e9b066db-f57d-4fd5-9d3c-6e65c888a1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993626256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2993626256
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1449237046
Short name T694
Test name
Test status
Simulation time 133063019 ps
CPU time 2.56 seconds
Started May 04 03:49:15 PM PDT 24
Finished May 04 03:49:18 PM PDT 24
Peak memory 206008 kb
Host smart-d9167ad4-7c11-4634-ad16-d375ab81a3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449237046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1449237046
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3345764451
Short name T81
Test name
Test status
Simulation time 37997418208 ps
CPU time 240.94 seconds
Started May 04 03:49:23 PM PDT 24
Finished May 04 03:53:24 PM PDT 24
Peak memory 222460 kb
Host smart-4978ebeb-73f0-4cf8-91a4-66f6fe589c94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345764451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3345764451
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.17552037
Short name T741
Test name
Test status
Simulation time 101230643 ps
CPU time 3.51 seconds
Started May 04 03:49:15 PM PDT 24
Finished May 04 03:49:19 PM PDT 24
Peak memory 219408 kb
Host smart-46452542-0ea7-4f2c-b274-d89f3c2599de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17552037 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.17552037
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3893765337
Short name T914
Test name
Test status
Simulation time 568937944 ps
CPU time 3.9 seconds
Started May 04 03:49:16 PM PDT 24
Finished May 04 03:49:20 PM PDT 24
Peak memory 207140 kb
Host smart-ea35945a-d4da-44ad-8d1c-0a95e4dc5694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893765337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3893765337
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3229604910
Short name T1067
Test name
Test status
Simulation time 208055450 ps
CPU time 4.24 seconds
Started May 04 03:49:15 PM PDT 24
Finished May 04 03:49:20 PM PDT 24
Peak memory 210596 kb
Host smart-2ce9fc28-2b18-43ae-9332-482bba279d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229604910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3229604910
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2286664838
Short name T919
Test name
Test status
Simulation time 23815215 ps
CPU time 1.06 seconds
Started May 04 03:49:23 PM PDT 24
Finished May 04 03:49:25 PM PDT 24
Peak memory 206040 kb
Host smart-c84d8956-1ab8-43f9-9b4d-9e22b58d3902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286664838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2286664838
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1484771554
Short name T423
Test name
Test status
Simulation time 1320363867 ps
CPU time 7.76 seconds
Started May 04 03:49:23 PM PDT 24
Finished May 04 03:49:31 PM PDT 24
Peak memory 222492 kb
Host smart-931bcf46-e4d3-4a8a-9f2e-0b821e87c8c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1484771554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1484771554
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.527270814
Short name T899
Test name
Test status
Simulation time 78424679 ps
CPU time 1.63 seconds
Started May 04 03:49:22 PM PDT 24
Finished May 04 03:49:24 PM PDT 24
Peak memory 207704 kb
Host smart-2600a36e-e370-4273-9816-3ad91d1f433a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527270814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.527270814
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3669724263
Short name T337
Test name
Test status
Simulation time 2057538790 ps
CPU time 4.21 seconds
Started May 04 03:49:22 PM PDT 24
Finished May 04 03:49:27 PM PDT 24
Peak memory 208216 kb
Host smart-06aaa515-8d7e-4302-a0f2-98e14e63ea9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669724263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3669724263
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1662631676
Short name T260
Test name
Test status
Simulation time 58881361 ps
CPU time 3.65 seconds
Started May 04 03:49:22 PM PDT 24
Finished May 04 03:49:26 PM PDT 24
Peak memory 211828 kb
Host smart-8c5e4dd4-dcc7-4f02-ae6d-455aaeb484e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662631676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1662631676
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2121142677
Short name T607
Test name
Test status
Simulation time 426356618 ps
CPU time 3.2 seconds
Started May 04 03:49:22 PM PDT 24
Finished May 04 03:49:25 PM PDT 24
Peak memory 206100 kb
Host smart-95ca138c-01c4-45ce-a440-fafd6ff705a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121142677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2121142677
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1348151729
Short name T596
Test name
Test status
Simulation time 218775992 ps
CPU time 4.03 seconds
Started May 04 03:49:23 PM PDT 24
Finished May 04 03:49:28 PM PDT 24
Peak memory 218260 kb
Host smart-db625efc-a329-4476-8e6f-fac413118303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348151729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1348151729
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1396881445
Short name T995
Test name
Test status
Simulation time 292988444 ps
CPU time 4.62 seconds
Started May 04 03:49:17 PM PDT 24
Finished May 04 03:49:22 PM PDT 24
Peak memory 208372 kb
Host smart-fb2031f4-9b55-4113-a708-fc49305ec8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396881445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1396881445
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2645306795
Short name T591
Test name
Test status
Simulation time 599010417 ps
CPU time 7.3 seconds
Started May 04 03:49:20 PM PDT 24
Finished May 04 03:49:28 PM PDT 24
Peak memory 208264 kb
Host smart-cf87ec63-b811-4ff2-93cf-3e28c135f076
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645306795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2645306795
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2345095950
Short name T88
Test name
Test status
Simulation time 121481969 ps
CPU time 2.34 seconds
Started May 04 03:49:22 PM PDT 24
Finished May 04 03:49:24 PM PDT 24
Peak memory 206732 kb
Host smart-75f7bc4b-069d-40ae-9917-11cd81485879
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345095950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2345095950
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2953000347
Short name T717
Test name
Test status
Simulation time 740765133 ps
CPU time 19.9 seconds
Started May 04 03:49:24 PM PDT 24
Finished May 04 03:49:44 PM PDT 24
Peak memory 208140 kb
Host smart-ec8bb3e1-1eaf-4b77-8081-e3aa36310114
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953000347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2953000347
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3712074468
Short name T577
Test name
Test status
Simulation time 360615231 ps
CPU time 10.54 seconds
Started May 04 03:49:23 PM PDT 24
Finished May 04 03:49:34 PM PDT 24
Peak memory 209240 kb
Host smart-b4692abf-8d3e-48a7-a994-ba4c3b3cabf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712074468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3712074468
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3663192064
Short name T194
Test name
Test status
Simulation time 143564736 ps
CPU time 3.26 seconds
Started May 04 03:49:14 PM PDT 24
Finished May 04 03:49:18 PM PDT 24
Peak memory 207972 kb
Host smart-2fea67a9-823e-47f4-a32f-ed2726ea15c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663192064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3663192064
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1575240543
Short name T203
Test name
Test status
Simulation time 88068969 ps
CPU time 5.98 seconds
Started May 04 03:49:20 PM PDT 24
Finished May 04 03:49:26 PM PDT 24
Peak memory 222672 kb
Host smart-63f333ec-540f-427f-b096-ba8f9ce1ee85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575240543 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1575240543
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.970895718
Short name T701
Test name
Test status
Simulation time 141168465 ps
CPU time 4.83 seconds
Started May 04 03:49:23 PM PDT 24
Finished May 04 03:49:29 PM PDT 24
Peak memory 218096 kb
Host smart-3c506603-34d6-44b0-ac75-698af4c645d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970895718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.970895718
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2335438371
Short name T936
Test name
Test status
Simulation time 491035385 ps
CPU time 3.86 seconds
Started May 04 03:49:25 PM PDT 24
Finished May 04 03:49:30 PM PDT 24
Peak memory 209772 kb
Host smart-8d157307-de67-4d47-93ab-3377eed88bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335438371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2335438371
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3718002725
Short name T762
Test name
Test status
Simulation time 13078607 ps
CPU time 0.76 seconds
Started May 04 03:49:25 PM PDT 24
Finished May 04 03:49:27 PM PDT 24
Peak memory 205804 kb
Host smart-e60fb18c-b575-465e-b7dc-7aa81e112b8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718002725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3718002725
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3594549869
Short name T1065
Test name
Test status
Simulation time 859850592 ps
CPU time 4.75 seconds
Started May 04 03:49:22 PM PDT 24
Finished May 04 03:49:27 PM PDT 24
Peak memory 214844 kb
Host smart-0742fcec-59a8-48a1-b292-60baf6b8d6ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3594549869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3594549869
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2643501414
Short name T29
Test name
Test status
Simulation time 950359601 ps
CPU time 5.08 seconds
Started May 04 03:49:27 PM PDT 24
Finished May 04 03:49:32 PM PDT 24
Peak memory 209840 kb
Host smart-ffddd269-098a-4018-ad61-ebd862d31da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643501414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2643501414
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.1168585932
Short name T939
Test name
Test status
Simulation time 376048298 ps
CPU time 5.27 seconds
Started May 04 03:49:22 PM PDT 24
Finished May 04 03:49:28 PM PDT 24
Peak memory 209672 kb
Host smart-4eafb5d9-c9de-452d-973e-bca93d6c707c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168585932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.1168585932
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.750369153
Short name T372
Test name
Test status
Simulation time 95380453 ps
CPU time 4.45 seconds
Started May 04 03:49:27 PM PDT 24
Finished May 04 03:49:32 PM PDT 24
Peak memory 220700 kb
Host smart-e3f3eadf-c925-4ae1-a5e4-10ebc3996bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750369153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.750369153
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1772632421
Short name T590
Test name
Test status
Simulation time 146576347 ps
CPU time 2.24 seconds
Started May 04 03:49:21 PM PDT 24
Finished May 04 03:49:23 PM PDT 24
Peak memory 214320 kb
Host smart-6f49cf85-844d-482b-863a-8c885380674f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772632421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1772632421
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.991069678
Short name T133
Test name
Test status
Simulation time 117165129 ps
CPU time 5.38 seconds
Started May 04 03:49:25 PM PDT 24
Finished May 04 03:49:31 PM PDT 24
Peak memory 208868 kb
Host smart-3503cfc5-e237-46c0-802a-dcb78aab38b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991069678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.991069678
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3816623955
Short name T275
Test name
Test status
Simulation time 3259096561 ps
CPU time 34.12 seconds
Started May 04 03:49:21 PM PDT 24
Finished May 04 03:49:55 PM PDT 24
Peak memory 208412 kb
Host smart-a3d83a26-af2f-4e32-b56a-e5c86f3da5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816623955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3816623955
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3436503085
Short name T880
Test name
Test status
Simulation time 481254028 ps
CPU time 2.45 seconds
Started May 04 03:49:25 PM PDT 24
Finished May 04 03:49:28 PM PDT 24
Peak memory 206780 kb
Host smart-2725a6c8-f6f2-4d89-bd46-d183154c714b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436503085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3436503085
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3124264939
Short name T572
Test name
Test status
Simulation time 851253619 ps
CPU time 22.06 seconds
Started May 04 03:49:20 PM PDT 24
Finished May 04 03:49:42 PM PDT 24
Peak memory 208164 kb
Host smart-8e6506cc-bc9c-4140-a0ec-79d97557aa00
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124264939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3124264939
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2285797397
Short name T937
Test name
Test status
Simulation time 487122615 ps
CPU time 10.11 seconds
Started May 04 03:49:23 PM PDT 24
Finished May 04 03:49:34 PM PDT 24
Peak memory 208584 kb
Host smart-dd9083c6-710f-46ad-bb5c-279d7cf5b83a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285797397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2285797397
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1018389382
Short name T131
Test name
Test status
Simulation time 259975521 ps
CPU time 2.35 seconds
Started May 04 03:49:24 PM PDT 24
Finished May 04 03:49:27 PM PDT 24
Peak memory 209908 kb
Host smart-308c4e92-bcc3-4698-bde7-039f622d0edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018389382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1018389382
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3195035467
Short name T19
Test name
Test status
Simulation time 23027781 ps
CPU time 1.85 seconds
Started May 04 03:49:22 PM PDT 24
Finished May 04 03:49:25 PM PDT 24
Peak memory 206828 kb
Host smart-980cfdd9-7ddc-415e-906b-62f84df49ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195035467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3195035467
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2418039326
Short name T814
Test name
Test status
Simulation time 9381267722 ps
CPU time 48.93 seconds
Started May 04 03:49:27 PM PDT 24
Finished May 04 03:50:16 PM PDT 24
Peak memory 208532 kb
Host smart-4a132f72-51c9-47a2-84aa-6dd8c4560f3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418039326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2418039326
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.457828340
Short name T606
Test name
Test status
Simulation time 276679282 ps
CPU time 3.49 seconds
Started May 04 03:49:26 PM PDT 24
Finished May 04 03:49:30 PM PDT 24
Peak memory 218548 kb
Host smart-1ffa31c8-4494-4565-a023-5478cc260f74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457828340 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.457828340
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3775110569
Short name T731
Test name
Test status
Simulation time 65589010 ps
CPU time 2.28 seconds
Started May 04 03:49:23 PM PDT 24
Finished May 04 03:49:26 PM PDT 24
Peak memory 207352 kb
Host smart-1e818588-dd83-4381-88ed-419386e22dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775110569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3775110569
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2681528368
Short name T578
Test name
Test status
Simulation time 140534951 ps
CPU time 0.85 seconds
Started May 04 03:49:34 PM PDT 24
Finished May 04 03:49:35 PM PDT 24
Peak memory 205796 kb
Host smart-b9e4329a-ef76-411e-a329-61739bcaec06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681528368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2681528368
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3569788884
Short name T409
Test name
Test status
Simulation time 223966395 ps
CPU time 10.25 seconds
Started May 04 03:49:27 PM PDT 24
Finished May 04 03:49:38 PM PDT 24
Peak memory 215252 kb
Host smart-f63b29c1-69e3-48b7-90ed-615eb1f5648d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3569788884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3569788884
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1640384282
Short name T79
Test name
Test status
Simulation time 72534065 ps
CPU time 3.12 seconds
Started May 04 03:49:25 PM PDT 24
Finished May 04 03:49:29 PM PDT 24
Peak memory 208952 kb
Host smart-45fc6672-58fe-4e15-b550-0f701b530338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640384282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1640384282
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2503388793
Short name T374
Test name
Test status
Simulation time 648034254 ps
CPU time 18.24 seconds
Started May 04 03:49:25 PM PDT 24
Finished May 04 03:49:44 PM PDT 24
Peak memory 219700 kb
Host smart-c1b0a8fb-040e-4b82-9130-82406ce333b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503388793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2503388793
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2063256338
Short name T417
Test name
Test status
Simulation time 48769195 ps
CPU time 2.42 seconds
Started May 04 03:49:27 PM PDT 24
Finished May 04 03:49:30 PM PDT 24
Peak memory 206996 kb
Host smart-b48c4ea8-d224-4a28-b515-a0f6663c14d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063256338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2063256338
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.898515068
Short name T952
Test name
Test status
Simulation time 56947466 ps
CPU time 3.52 seconds
Started May 04 03:49:25 PM PDT 24
Finished May 04 03:49:29 PM PDT 24
Peak memory 209620 kb
Host smart-a85e584f-689e-40a7-8ce9-6426e86f2d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898515068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.898515068
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2246101939
Short name T874
Test name
Test status
Simulation time 97048212 ps
CPU time 1.77 seconds
Started May 04 03:49:25 PM PDT 24
Finished May 04 03:49:27 PM PDT 24
Peak memory 206884 kb
Host smart-d0137acc-87bb-48c4-a6ce-fac4416c5ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246101939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2246101939
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1779923655
Short name T282
Test name
Test status
Simulation time 206312726 ps
CPU time 4.01 seconds
Started May 04 03:49:26 PM PDT 24
Finished May 04 03:49:31 PM PDT 24
Peak memory 206860 kb
Host smart-1d49d2eb-15f2-4b66-914a-2ac595f690aa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779923655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1779923655
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1320102971
Short name T759
Test name
Test status
Simulation time 2694118468 ps
CPU time 20.7 seconds
Started May 04 03:49:26 PM PDT 24
Finished May 04 03:49:48 PM PDT 24
Peak memory 207964 kb
Host smart-fdc3ed51-ad2c-4816-9bc5-330b54fb8aff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320102971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1320102971
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3435907035
Short name T954
Test name
Test status
Simulation time 36542111 ps
CPU time 2.66 seconds
Started May 04 03:49:26 PM PDT 24
Finished May 04 03:49:30 PM PDT 24
Peak memory 208696 kb
Host smart-373c8a0b-8cb3-4554-a087-7ce82a25c3fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435907035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3435907035
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3390975613
Short name T632
Test name
Test status
Simulation time 55185256 ps
CPU time 3.14 seconds
Started May 04 03:49:33 PM PDT 24
Finished May 04 03:49:36 PM PDT 24
Peak memory 210004 kb
Host smart-93a9d541-736e-4c73-bcc7-56feb3953a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390975613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3390975613
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.799411811
Short name T625
Test name
Test status
Simulation time 214928557 ps
CPU time 2.98 seconds
Started May 04 03:49:26 PM PDT 24
Finished May 04 03:49:29 PM PDT 24
Peak memory 208472 kb
Host smart-4fdff430-88c6-4fd9-8129-7075892242c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799411811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.799411811
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.1779332483
Short name T787
Test name
Test status
Simulation time 118958805 ps
CPU time 2.71 seconds
Started May 04 03:49:36 PM PDT 24
Finished May 04 03:49:39 PM PDT 24
Peak memory 218292 kb
Host smart-8e9a0f6c-aa13-414c-87ca-3bdcbd7f37e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779332483 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.1779332483
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3884504091
Short name T251
Test name
Test status
Simulation time 5872014074 ps
CPU time 39.65 seconds
Started May 04 03:49:28 PM PDT 24
Finished May 04 03:50:08 PM PDT 24
Peak memory 209864 kb
Host smart-de9fb974-302e-4834-affe-c851d4a5bdb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884504091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3884504091
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.4001656769
Short name T1047
Test name
Test status
Simulation time 33485332 ps
CPU time 1.8 seconds
Started May 04 03:49:35 PM PDT 24
Finished May 04 03:49:38 PM PDT 24
Peak memory 209892 kb
Host smart-13949a4f-e727-4453-965f-62741b9bdb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001656769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.4001656769
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2203990419
Short name T1013
Test name
Test status
Simulation time 10933228 ps
CPU time 0.87 seconds
Started May 04 03:49:36 PM PDT 24
Finished May 04 03:49:37 PM PDT 24
Peak memory 205816 kb
Host smart-6679e8cd-74d7-4a64-b960-2e40bc8eddc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203990419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2203990419
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3255018626
Short name T378
Test name
Test status
Simulation time 528069476 ps
CPU time 4.25 seconds
Started May 04 03:49:35 PM PDT 24
Finished May 04 03:49:40 PM PDT 24
Peak memory 215428 kb
Host smart-5529c22c-f23e-469b-a11c-a2d000eb5880
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3255018626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3255018626
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1567971335
Short name T37
Test name
Test status
Simulation time 103105338 ps
CPU time 4.13 seconds
Started May 04 03:49:37 PM PDT 24
Finished May 04 03:49:41 PM PDT 24
Peak memory 220472 kb
Host smart-e2d42622-a912-4eae-b29e-f85b2ac9fec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567971335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1567971335
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.4182225972
Short name T915
Test name
Test status
Simulation time 163792049 ps
CPU time 4.15 seconds
Started May 04 03:49:30 PM PDT 24
Finished May 04 03:49:36 PM PDT 24
Peak memory 207176 kb
Host smart-d7ec2f45-fecf-41df-b4b3-dcfc4af5feaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182225972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.4182225972
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.704905564
Short name T387
Test name
Test status
Simulation time 39976491 ps
CPU time 2.81 seconds
Started May 04 03:49:36 PM PDT 24
Finished May 04 03:49:40 PM PDT 24
Peak memory 214368 kb
Host smart-021f437c-0dfc-48d8-af38-48a2a1c56bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704905564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.704905564
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3437864668
Short name T333
Test name
Test status
Simulation time 1572603794 ps
CPU time 13.26 seconds
Started May 04 03:49:35 PM PDT 24
Finished May 04 03:49:49 PM PDT 24
Peak memory 211188 kb
Host smart-92a47867-969d-44f4-a792-34fc3a92f91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437864668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3437864668
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2234082548
Short name T736
Test name
Test status
Simulation time 485389989 ps
CPU time 3.88 seconds
Started May 04 03:49:32 PM PDT 24
Finished May 04 03:49:36 PM PDT 24
Peak memory 219728 kb
Host smart-816c7f20-9880-436b-92f3-ec10bc8095f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234082548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2234082548
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.98698164
Short name T765
Test name
Test status
Simulation time 147780571 ps
CPU time 6.14 seconds
Started May 04 03:49:33 PM PDT 24
Finished May 04 03:49:39 PM PDT 24
Peak memory 219600 kb
Host smart-4621ff4b-231d-4ff0-af6d-4c9d341f9c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98698164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.98698164
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2271432250
Short name T397
Test name
Test status
Simulation time 53498945 ps
CPU time 2.72 seconds
Started May 04 03:49:31 PM PDT 24
Finished May 04 03:49:34 PM PDT 24
Peak memory 208544 kb
Host smart-cb7e1eb4-a082-4805-a491-2ec0261af1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271432250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2271432250
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3348499692
Short name T398
Test name
Test status
Simulation time 9157805426 ps
CPU time 55.74 seconds
Started May 04 03:49:36 PM PDT 24
Finished May 04 03:50:32 PM PDT 24
Peak memory 207952 kb
Host smart-84766fa2-e1e3-453e-96e8-352b17257edd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348499692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3348499692
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3433027684
Short name T360
Test name
Test status
Simulation time 95880711 ps
CPU time 2.84 seconds
Started May 04 03:49:31 PM PDT 24
Finished May 04 03:49:34 PM PDT 24
Peak memory 207312 kb
Host smart-caefa2d8-c5f4-4909-b096-8092f873edc8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433027684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3433027684
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3929616122
Short name T825
Test name
Test status
Simulation time 160040903 ps
CPU time 2.43 seconds
Started May 04 03:49:35 PM PDT 24
Finished May 04 03:49:37 PM PDT 24
Peak memory 206920 kb
Host smart-69da3600-a8a6-415b-9764-269d6f8826aa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929616122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3929616122
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2295598759
Short name T843
Test name
Test status
Simulation time 155889007 ps
CPU time 2.33 seconds
Started May 04 03:49:38 PM PDT 24
Finished May 04 03:49:41 PM PDT 24
Peak memory 215572 kb
Host smart-f122b0f3-5ef0-43ed-8629-b1e199a5d49c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295598759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2295598759
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3367362159
Short name T872
Test name
Test status
Simulation time 1116812327 ps
CPU time 9.72 seconds
Started May 04 03:49:34 PM PDT 24
Finished May 04 03:49:44 PM PDT 24
Peak memory 207768 kb
Host smart-558c6d9d-a9eb-4956-9cc5-36e1b0ae601d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367362159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3367362159
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3242318202
Short name T414
Test name
Test status
Simulation time 328902924 ps
CPU time 4.11 seconds
Started May 04 03:49:38 PM PDT 24
Finished May 04 03:49:43 PM PDT 24
Peak memory 210184 kb
Host smart-97df04d7-89e7-43b6-9d11-76159470dff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242318202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3242318202
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2253354203
Short name T628
Test name
Test status
Simulation time 806088419 ps
CPU time 8.76 seconds
Started May 04 03:49:37 PM PDT 24
Finished May 04 03:49:46 PM PDT 24
Peak memory 210972 kb
Host smart-8a27cc70-e3dd-47da-949f-53b95e691952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253354203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2253354203
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3303834651
Short name T626
Test name
Test status
Simulation time 14821274 ps
CPU time 0.93 seconds
Started May 04 03:49:36 PM PDT 24
Finished May 04 03:49:37 PM PDT 24
Peak memory 206064 kb
Host smart-5fddcf58-6c9c-46f4-8bbe-08bb042f6ab7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303834651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3303834651
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3471568997
Short name T301
Test name
Test status
Simulation time 333435986 ps
CPU time 4.34 seconds
Started May 04 03:49:38 PM PDT 24
Finished May 04 03:49:43 PM PDT 24
Peak memory 215120 kb
Host smart-a93e5b5f-b4ff-4a15-b3ac-dedb6b05969d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3471568997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3471568997
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3754174307
Short name T31
Test name
Test status
Simulation time 124842056 ps
CPU time 3.73 seconds
Started May 04 03:49:36 PM PDT 24
Finished May 04 03:49:40 PM PDT 24
Peak memory 215304 kb
Host smart-09dc787e-0ed8-4b73-a1c5-7d6b256abf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754174307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3754174307
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2916061145
Short name T413
Test name
Test status
Simulation time 82188239 ps
CPU time 2.17 seconds
Started May 04 03:49:36 PM PDT 24
Finished May 04 03:49:38 PM PDT 24
Peak memory 218208 kb
Host smart-b9303e20-c5c8-4f58-ac62-20f73afc1344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916061145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2916061145
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1511937941
Short name T953
Test name
Test status
Simulation time 136206590 ps
CPU time 2.6 seconds
Started May 04 03:49:38 PM PDT 24
Finished May 04 03:49:42 PM PDT 24
Peak memory 214280 kb
Host smart-2887741c-7087-440f-a0c0-265507e430ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511937941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1511937941
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2367152762
Short name T265
Test name
Test status
Simulation time 295182023 ps
CPU time 7.18 seconds
Started May 04 03:49:35 PM PDT 24
Finished May 04 03:49:42 PM PDT 24
Peak memory 214168 kb
Host smart-e4f24700-6704-4db1-9113-80228ba65085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367152762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2367152762
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3719138443
Short name T703
Test name
Test status
Simulation time 514200409 ps
CPU time 3.59 seconds
Started May 04 03:49:38 PM PDT 24
Finished May 04 03:49:42 PM PDT 24
Peak memory 222376 kb
Host smart-3a1005e2-c8d5-4118-b706-ddeaeec011a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719138443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3719138443
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.410681935
Short name T249
Test name
Test status
Simulation time 596528468 ps
CPU time 6.59 seconds
Started May 04 03:49:35 PM PDT 24
Finished May 04 03:49:42 PM PDT 24
Peak memory 208768 kb
Host smart-50fe6f55-63d3-4fd5-a9cc-1125e12f5889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410681935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.410681935
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3523047825
Short name T647
Test name
Test status
Simulation time 1073336828 ps
CPU time 38.39 seconds
Started May 04 03:49:35 PM PDT 24
Finished May 04 03:50:14 PM PDT 24
Peak memory 208292 kb
Host smart-4ca58f20-2422-4eee-bf5a-fca76774b658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523047825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3523047825
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.237425691
Short name T84
Test name
Test status
Simulation time 164402816 ps
CPU time 6.53 seconds
Started May 04 03:49:36 PM PDT 24
Finished May 04 03:49:43 PM PDT 24
Peak memory 208968 kb
Host smart-321c394b-02d1-40bf-890d-bc077e060283
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237425691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.237425691
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.51911105
Short name T839
Test name
Test status
Simulation time 60044864 ps
CPU time 3.06 seconds
Started May 04 03:49:36 PM PDT 24
Finished May 04 03:49:40 PM PDT 24
Peak memory 208616 kb
Host smart-39601026-bc0a-4ea1-b996-70c924c1cf08
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51911105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.51911105
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.4290960742
Short name T650
Test name
Test status
Simulation time 191001818 ps
CPU time 4.48 seconds
Started May 04 03:49:37 PM PDT 24
Finished May 04 03:49:42 PM PDT 24
Peak memory 206920 kb
Host smart-c13ebec1-800c-4b58-89f8-61225585bec6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290960742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.4290960742
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1473187860
Short name T820
Test name
Test status
Simulation time 62113500 ps
CPU time 3.2 seconds
Started May 04 03:49:37 PM PDT 24
Finished May 04 03:49:41 PM PDT 24
Peak memory 218212 kb
Host smart-c4362dcb-7e93-4d43-8d5f-916acdd36048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473187860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1473187860
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.815295680
Short name T392
Test name
Test status
Simulation time 35764449 ps
CPU time 2.23 seconds
Started May 04 03:49:37 PM PDT 24
Finished May 04 03:49:40 PM PDT 24
Peak memory 206636 kb
Host smart-fd9b7f09-6f61-4fde-b01b-b37e839b3cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815295680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.815295680
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.4234021583
Short name T808
Test name
Test status
Simulation time 3570302081 ps
CPU time 62.34 seconds
Started May 04 03:49:38 PM PDT 24
Finished May 04 03:50:41 PM PDT 24
Peak memory 218196 kb
Host smart-b4d896ab-2edc-489a-8910-4809de83bd43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234021583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.4234021583
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.103703491
Short name T581
Test name
Test status
Simulation time 446729416 ps
CPU time 3.94 seconds
Started May 04 03:49:38 PM PDT 24
Finished May 04 03:49:43 PM PDT 24
Peak memory 214328 kb
Host smart-d4e9f80c-a480-42dc-b8c3-f3ad52a0441a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103703491 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.103703491
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.546709485
Short name T339
Test name
Test status
Simulation time 486203773 ps
CPU time 5.34 seconds
Started May 04 03:49:38 PM PDT 24
Finished May 04 03:49:44 PM PDT 24
Peak memory 208220 kb
Host smart-284935fc-f1f5-419c-9a3b-64384ad7d086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546709485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.546709485
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.1789391987
Short name T681
Test name
Test status
Simulation time 566785529 ps
CPU time 3.42 seconds
Started May 04 03:49:38 PM PDT 24
Finished May 04 03:49:42 PM PDT 24
Peak memory 210180 kb
Host smart-6984eb90-854d-4e76-87f2-407cd8ca6381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789391987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.1789391987
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.4161971786
Short name T624
Test name
Test status
Simulation time 19360379 ps
CPU time 0.86 seconds
Started May 04 03:46:23 PM PDT 24
Finished May 04 03:46:24 PM PDT 24
Peak memory 205872 kb
Host smart-4ffba389-d156-422c-bf67-e909df6e2005
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161971786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.4161971786
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2253769447
Short name T361
Test name
Test status
Simulation time 527291646 ps
CPU time 4.26 seconds
Started May 04 03:46:18 PM PDT 24
Finished May 04 03:46:22 PM PDT 24
Peak memory 214336 kb
Host smart-c7d0fd7c-019d-4bd9-a52e-ac70a02f8cd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2253769447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2253769447
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.233697577
Short name T704
Test name
Test status
Simulation time 800893925 ps
CPU time 2.94 seconds
Started May 04 03:46:18 PM PDT 24
Finished May 04 03:46:22 PM PDT 24
Peak memory 217836 kb
Host smart-a070259d-8ad9-42c2-bf1c-9fdb990cece6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233697577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.233697577
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1130570937
Short name T740
Test name
Test status
Simulation time 173040287 ps
CPU time 3.17 seconds
Started May 04 03:46:20 PM PDT 24
Finished May 04 03:46:23 PM PDT 24
Peak memory 214264 kb
Host smart-1c195395-8d61-4e9b-a5a2-b5987d3a3621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130570937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1130570937
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_random.3133410922
Short name T947
Test name
Test status
Simulation time 1383760882 ps
CPU time 9.08 seconds
Started May 04 03:46:17 PM PDT 24
Finished May 04 03:46:26 PM PDT 24
Peak memory 209648 kb
Host smart-378a4ebf-d171-477f-be1b-382f5720ff22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133410922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3133410922
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1640086665
Short name T318
Test name
Test status
Simulation time 110256062 ps
CPU time 4.53 seconds
Started May 04 03:46:19 PM PDT 24
Finished May 04 03:46:24 PM PDT 24
Peak memory 208596 kb
Host smart-1b334895-d8f7-4f34-9c6c-9818ef926bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640086665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1640086665
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3776060875
Short name T755
Test name
Test status
Simulation time 80875688 ps
CPU time 3.77 seconds
Started May 04 03:46:20 PM PDT 24
Finished May 04 03:46:25 PM PDT 24
Peak memory 207848 kb
Host smart-f2432469-6f07-437e-9422-b4dd18e859f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776060875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3776060875
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1217392535
Short name T752
Test name
Test status
Simulation time 126434054 ps
CPU time 3.35 seconds
Started May 04 03:46:19 PM PDT 24
Finished May 04 03:46:23 PM PDT 24
Peak memory 206892 kb
Host smart-438e227a-5c76-4769-908e-9ff0360ce1d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217392535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1217392535
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3465156308
Short name T330
Test name
Test status
Simulation time 319699398 ps
CPU time 3.69 seconds
Started May 04 03:46:18 PM PDT 24
Finished May 04 03:46:22 PM PDT 24
Peak memory 206884 kb
Host smart-331d0993-beb7-4f06-ab04-5c6355b49d26
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465156308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3465156308
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1380342469
Short name T935
Test name
Test status
Simulation time 220849076 ps
CPU time 2.64 seconds
Started May 04 03:46:23 PM PDT 24
Finished May 04 03:46:26 PM PDT 24
Peak memory 209248 kb
Host smart-19b47918-42f0-404a-ac22-96413d3f5752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380342469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1380342469
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1714999581
Short name T993
Test name
Test status
Simulation time 448834224 ps
CPU time 6.28 seconds
Started May 04 03:46:20 PM PDT 24
Finished May 04 03:46:27 PM PDT 24
Peak memory 206816 kb
Host smart-ffd8ca4b-6cfa-46f7-b25c-003ec21cec31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714999581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1714999581
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1870012870
Short name T320
Test name
Test status
Simulation time 188305244 ps
CPU time 7.41 seconds
Started May 04 03:46:25 PM PDT 24
Finished May 04 03:46:33 PM PDT 24
Peak memory 208716 kb
Host smart-79bb1971-8480-4d72-8a5d-e5bd6e56be70
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870012870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1870012870
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3678187964
Short name T400
Test name
Test status
Simulation time 519997307 ps
CPU time 7.43 seconds
Started May 04 03:46:23 PM PDT 24
Finished May 04 03:46:31 PM PDT 24
Peak memory 222552 kb
Host smart-f3b2cf55-dc25-4365-810b-20e2d35c11d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678187964 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3678187964
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.400237110
Short name T757
Test name
Test status
Simulation time 37993882 ps
CPU time 2.69 seconds
Started May 04 03:46:20 PM PDT 24
Finished May 04 03:46:23 PM PDT 24
Peak memory 214216 kb
Host smart-98c63dba-ad58-485f-a972-288494dd8c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400237110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.400237110
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.192895666
Short name T901
Test name
Test status
Simulation time 66421687 ps
CPU time 2.22 seconds
Started May 04 03:46:23 PM PDT 24
Finished May 04 03:46:26 PM PDT 24
Peak memory 210184 kb
Host smart-11f67fd8-aa29-46e1-9829-e1b8eb2404b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192895666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.192895666
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1942603951
Short name T877
Test name
Test status
Simulation time 12446370 ps
CPU time 0.72 seconds
Started May 04 03:49:51 PM PDT 24
Finished May 04 03:49:53 PM PDT 24
Peak memory 205760 kb
Host smart-fc153720-e4fe-490b-a0bd-7d824c59e0c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942603951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1942603951
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1835696650
Short name T410
Test name
Test status
Simulation time 416387372 ps
CPU time 5.69 seconds
Started May 04 03:49:45 PM PDT 24
Finished May 04 03:49:52 PM PDT 24
Peak memory 214324 kb
Host smart-59d7729f-4ac9-4d1f-860b-bd5e2e2b76a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1835696650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1835696650
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.4044198388
Short name T832
Test name
Test status
Simulation time 453193749 ps
CPU time 2.26 seconds
Started May 04 03:49:40 PM PDT 24
Finished May 04 03:49:43 PM PDT 24
Peak memory 218364 kb
Host smart-12ad69db-0c85-49b4-8d3d-e2ee3455fb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044198388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.4044198388
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.171280494
Short name T1050
Test name
Test status
Simulation time 67657720 ps
CPU time 3.29 seconds
Started May 04 03:49:44 PM PDT 24
Finished May 04 03:49:48 PM PDT 24
Peak memory 219228 kb
Host smart-4a139bdc-1108-4c50-8b1a-b92ca6e1733c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171280494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.171280494
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.659803743
Short name T848
Test name
Test status
Simulation time 9353550945 ps
CPU time 95.66 seconds
Started May 04 03:49:45 PM PDT 24
Finished May 04 03:51:21 PM PDT 24
Peak memory 218040 kb
Host smart-3960f5f6-07f2-4601-ad69-e30e4a488df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659803743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.659803743
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1249614653
Short name T1072
Test name
Test status
Simulation time 381772470 ps
CPU time 6.34 seconds
Started May 04 03:49:44 PM PDT 24
Finished May 04 03:49:51 PM PDT 24
Peak memory 206652 kb
Host smart-935ce36c-2497-47e9-8571-e9428532e1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249614653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1249614653
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2753791223
Short name T867
Test name
Test status
Simulation time 151651393 ps
CPU time 4.67 seconds
Started May 04 03:49:42 PM PDT 24
Finished May 04 03:49:47 PM PDT 24
Peak memory 208820 kb
Host smart-a76261a0-c3ac-49f6-a0c2-0f689d77b577
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753791223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2753791223
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.4011340607
Short name T886
Test name
Test status
Simulation time 252278532 ps
CPU time 3.15 seconds
Started May 04 03:49:44 PM PDT 24
Finished May 04 03:49:48 PM PDT 24
Peak memory 206868 kb
Host smart-e6b0f103-65b2-4281-a275-f1a1ad95fa08
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011340607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.4011340607
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1641817535
Short name T1033
Test name
Test status
Simulation time 359345584 ps
CPU time 3.09 seconds
Started May 04 03:49:40 PM PDT 24
Finished May 04 03:49:44 PM PDT 24
Peak memory 208616 kb
Host smart-c789b6b3-732f-47f9-9671-cae3aaee9f6f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641817535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1641817535
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.4275862097
Short name T706
Test name
Test status
Simulation time 477096148 ps
CPU time 5.23 seconds
Started May 04 03:49:41 PM PDT 24
Finished May 04 03:49:47 PM PDT 24
Peak memory 209708 kb
Host smart-23059644-bdc5-4b7f-802a-67a5fbac1382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275862097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.4275862097
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1662334577
Short name T565
Test name
Test status
Simulation time 700433053 ps
CPU time 4.28 seconds
Started May 04 03:49:46 PM PDT 24
Finished May 04 03:49:51 PM PDT 24
Peak memory 207236 kb
Host smart-d81e6b22-3665-4752-a219-5e0f645cf092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662334577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1662334577
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.14319215
Short name T644
Test name
Test status
Simulation time 217407227 ps
CPU time 6.01 seconds
Started May 04 03:49:40 PM PDT 24
Finished May 04 03:49:47 PM PDT 24
Peak memory 222472 kb
Host smart-6e2e842b-22f3-46a8-b18a-e718938cebe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14319215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.14319215
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1736992090
Short name T777
Test name
Test status
Simulation time 1725114066 ps
CPU time 14.75 seconds
Started May 04 03:49:43 PM PDT 24
Finished May 04 03:49:58 PM PDT 24
Peak memory 211024 kb
Host smart-63c75004-aa32-42b1-9291-71faf7cd84b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736992090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1736992090
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2459730903
Short name T786
Test name
Test status
Simulation time 9961953 ps
CPU time 0.86 seconds
Started May 04 03:49:48 PM PDT 24
Finished May 04 03:49:50 PM PDT 24
Peak memory 205868 kb
Host smart-7df90d08-ed78-4e42-9217-8b0b2bc77973
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459730903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2459730903
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2609170264
Short name T258
Test name
Test status
Simulation time 60013674 ps
CPU time 3.29 seconds
Started May 04 03:49:49 PM PDT 24
Finished May 04 03:49:53 PM PDT 24
Peak memory 207512 kb
Host smart-1ddccf50-52dd-48bc-b929-5551158284af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609170264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2609170264
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3613199772
Short name T719
Test name
Test status
Simulation time 484872468 ps
CPU time 11.19 seconds
Started May 04 03:49:48 PM PDT 24
Finished May 04 03:50:00 PM PDT 24
Peak memory 209360 kb
Host smart-deb3fc39-bbfb-4b1f-b720-fea3e670048b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613199772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3613199772
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.607951695
Short name T200
Test name
Test status
Simulation time 198209143 ps
CPU time 5 seconds
Started May 04 03:49:47 PM PDT 24
Finished May 04 03:49:53 PM PDT 24
Peak memory 222440 kb
Host smart-f9d3be34-e478-4c61-92b2-03b02cfbe7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607951695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.607951695
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.870380364
Short name T45
Test name
Test status
Simulation time 95691272 ps
CPU time 3.5 seconds
Started May 04 03:49:49 PM PDT 24
Finished May 04 03:49:54 PM PDT 24
Peak memory 222484 kb
Host smart-0f20e207-b1ee-4b69-a035-1f933623faef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870380364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.870380364
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3888052711
Short name T1034
Test name
Test status
Simulation time 1082263279 ps
CPU time 5.7 seconds
Started May 04 03:49:47 PM PDT 24
Finished May 04 03:49:54 PM PDT 24
Peak memory 209548 kb
Host smart-3a4c86fb-0dcc-4a3e-a54f-30c5646e289a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888052711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3888052711
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3513635201
Short name T997
Test name
Test status
Simulation time 405180595 ps
CPU time 10.83 seconds
Started May 04 03:49:46 PM PDT 24
Finished May 04 03:49:57 PM PDT 24
Peak memory 208696 kb
Host smart-fe10f624-cffc-4344-97b6-5e97a432022b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513635201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3513635201
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1753187696
Short name T598
Test name
Test status
Simulation time 429100025 ps
CPU time 7.07 seconds
Started May 04 03:49:47 PM PDT 24
Finished May 04 03:49:55 PM PDT 24
Peak memory 208536 kb
Host smart-61eb3958-2f12-4e8f-b728-f03848bd399b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753187696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1753187696
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3385245537
Short name T828
Test name
Test status
Simulation time 229419889 ps
CPU time 6.7 seconds
Started May 04 03:49:47 PM PDT 24
Finished May 04 03:49:54 PM PDT 24
Peak memory 207928 kb
Host smart-07620319-48c8-49da-9c4f-d8e8e0d4ab19
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385245537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3385245537
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2344563801
Short name T862
Test name
Test status
Simulation time 395355507 ps
CPU time 3.87 seconds
Started May 04 03:49:46 PM PDT 24
Finished May 04 03:49:50 PM PDT 24
Peak memory 206792 kb
Host smart-0fb0c47e-2578-4807-aeec-5ad4f15ec5a9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344563801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2344563801
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2760155087
Short name T838
Test name
Test status
Simulation time 1049756889 ps
CPU time 13.74 seconds
Started May 04 03:49:47 PM PDT 24
Finished May 04 03:50:02 PM PDT 24
Peak memory 214312 kb
Host smart-ab6ad19d-366c-4730-9ff9-46c2636abf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760155087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2760155087
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2329239039
Short name T566
Test name
Test status
Simulation time 954075345 ps
CPU time 27.23 seconds
Started May 04 03:49:46 PM PDT 24
Finished May 04 03:50:13 PM PDT 24
Peak memory 207684 kb
Host smart-527a3e24-f82d-4f3f-9d31-8388f7cf2f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329239039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2329239039
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1611534172
Short name T1054
Test name
Test status
Simulation time 1739287025 ps
CPU time 11.3 seconds
Started May 04 03:49:49 PM PDT 24
Finished May 04 03:50:01 PM PDT 24
Peak memory 220104 kb
Host smart-d4d26cdd-98ec-43db-8d91-9805b9c0e7db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611534172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1611534172
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3431561685
Short name T805
Test name
Test status
Simulation time 151687961 ps
CPU time 3.97 seconds
Started May 04 03:49:48 PM PDT 24
Finished May 04 03:49:53 PM PDT 24
Peak memory 222592 kb
Host smart-06a79895-5ca2-46b4-a263-8fd12c550a8d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431561685 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3431561685
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2608173130
Short name T343
Test name
Test status
Simulation time 112179896 ps
CPU time 4.02 seconds
Started May 04 03:49:52 PM PDT 24
Finished May 04 03:49:56 PM PDT 24
Peak memory 209508 kb
Host smart-b1bf7826-0048-42bd-8ec9-78bb95360b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608173130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2608173130
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1320785872
Short name T113
Test name
Test status
Simulation time 183413526 ps
CPU time 2.71 seconds
Started May 04 03:49:49 PM PDT 24
Finished May 04 03:49:52 PM PDT 24
Peak memory 210376 kb
Host smart-3fe7d802-0e5a-4762-98ab-0032f1c9d1d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320785872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1320785872
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.592198324
Short name T865
Test name
Test status
Simulation time 10737848 ps
CPU time 0.83 seconds
Started May 04 03:49:52 PM PDT 24
Finished May 04 03:49:54 PM PDT 24
Peak memory 205856 kb
Host smart-56f13f22-216c-47b0-af82-d85fd1bd01bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592198324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.592198324
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1919008026
Short name T355
Test name
Test status
Simulation time 135541860 ps
CPU time 3.12 seconds
Started May 04 03:49:48 PM PDT 24
Finished May 04 03:49:52 PM PDT 24
Peak memory 215436 kb
Host smart-7fe51caa-86ee-4812-9fbc-db32125cb213
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919008026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1919008026
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1286948933
Short name T9
Test name
Test status
Simulation time 374955729 ps
CPU time 3.73 seconds
Started May 04 03:49:53 PM PDT 24
Finished May 04 03:49:57 PM PDT 24
Peak memory 214624 kb
Host smart-8afb27a9-b7ea-497b-867c-d34c6bd7afca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286948933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1286948933
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.4275821621
Short name T866
Test name
Test status
Simulation time 183431451 ps
CPU time 5.49 seconds
Started May 04 03:49:52 PM PDT 24
Finished May 04 03:49:58 PM PDT 24
Peak memory 209720 kb
Host smart-023c75d3-0b16-452b-9d8b-5b384f63e7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275821621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.4275821621
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1165069064
Short name T1051
Test name
Test status
Simulation time 379959768 ps
CPU time 4.1 seconds
Started May 04 03:49:49 PM PDT 24
Finished May 04 03:49:54 PM PDT 24
Peak memory 220436 kb
Host smart-64892789-6f8c-40e4-8261-6e5338719cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165069064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1165069064
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3311003485
Short name T941
Test name
Test status
Simulation time 1910259022 ps
CPU time 25.87 seconds
Started May 04 03:50:06 PM PDT 24
Finished May 04 03:50:32 PM PDT 24
Peak memory 222416 kb
Host smart-64318046-054c-4859-ba9a-19241a59e4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311003485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3311003485
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.4209503791
Short name T278
Test name
Test status
Simulation time 273252650 ps
CPU time 2.93 seconds
Started May 04 03:49:47 PM PDT 24
Finished May 04 03:49:51 PM PDT 24
Peak memory 210080 kb
Host smart-fab9039c-fbbc-46a2-a4a1-5f356c9b2315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209503791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.4209503791
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1929455213
Short name T269
Test name
Test status
Simulation time 585464461 ps
CPU time 5.96 seconds
Started May 04 03:49:48 PM PDT 24
Finished May 04 03:49:54 PM PDT 24
Peak memory 218228 kb
Host smart-e2ce305d-7ed9-4d0c-a828-c10865998c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929455213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1929455213
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3972468440
Short name T614
Test name
Test status
Simulation time 239531738 ps
CPU time 6.71 seconds
Started May 04 03:49:46 PM PDT 24
Finished May 04 03:49:53 PM PDT 24
Peak memory 207880 kb
Host smart-158b7d37-01df-4c7d-9b26-b196bc6f33dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972468440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3972468440
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.4231204984
Short name T728
Test name
Test status
Simulation time 594146735 ps
CPU time 3.88 seconds
Started May 04 03:49:47 PM PDT 24
Finished May 04 03:49:51 PM PDT 24
Peak memory 208816 kb
Host smart-6c751709-d040-4ce9-b92c-95ebb02409f8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231204984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.4231204984
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3649754868
Short name T629
Test name
Test status
Simulation time 858536111 ps
CPU time 3.73 seconds
Started May 04 03:49:47 PM PDT 24
Finished May 04 03:49:51 PM PDT 24
Peak memory 206856 kb
Host smart-74b26039-a4dd-46cf-b865-4dfa7b170550
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649754868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3649754868
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.289287985
Short name T663
Test name
Test status
Simulation time 54528272 ps
CPU time 2.26 seconds
Started May 04 03:49:48 PM PDT 24
Finished May 04 03:49:51 PM PDT 24
Peak memory 208628 kb
Host smart-48d312ba-851d-467e-9785-964155cc42a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289287985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.289287985
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2018665852
Short name T236
Test name
Test status
Simulation time 44117976 ps
CPU time 2.93 seconds
Started May 04 03:50:06 PM PDT 24
Finished May 04 03:50:09 PM PDT 24
Peak memory 214392 kb
Host smart-fb528b9f-2e24-47bb-81d6-765feb06c28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018665852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2018665852
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.184451649
Short name T895
Test name
Test status
Simulation time 120770941 ps
CPU time 3.02 seconds
Started May 04 03:49:51 PM PDT 24
Finished May 04 03:49:55 PM PDT 24
Peak memory 208324 kb
Host smart-135e712b-15a6-4587-9b72-c730fea3fab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184451649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.184451649
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1071706108
Short name T341
Test name
Test status
Simulation time 3393489917 ps
CPU time 33.97 seconds
Started May 04 03:49:53 PM PDT 24
Finished May 04 03:50:28 PM PDT 24
Peak memory 215248 kb
Host smart-ad250344-5c1b-486d-84de-b512c2da1053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071706108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1071706108
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3850378326
Short name T102
Test name
Test status
Simulation time 56374165 ps
CPU time 4.47 seconds
Started May 04 03:49:53 PM PDT 24
Finished May 04 03:49:58 PM PDT 24
Peak memory 222556 kb
Host smart-70d6b031-2b94-45b2-9568-13d7c42c0548
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850378326 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3850378326
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.409138179
Short name T196
Test name
Test status
Simulation time 2013090515 ps
CPU time 11.39 seconds
Started May 04 03:49:49 PM PDT 24
Finished May 04 03:50:01 PM PDT 24
Peak memory 207396 kb
Host smart-09f70c69-18c8-42a0-83dc-8571f890c27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409138179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.409138179
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.4255577766
Short name T1015
Test name
Test status
Simulation time 104879436 ps
CPU time 2.63 seconds
Started May 04 03:49:53 PM PDT 24
Finished May 04 03:49:56 PM PDT 24
Peak memory 210504 kb
Host smart-66aaee8d-37c1-4ca1-8ad4-648125941da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255577766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.4255577766
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.741081916
Short name T1037
Test name
Test status
Simulation time 45537818 ps
CPU time 0.87 seconds
Started May 04 03:49:53 PM PDT 24
Finished May 04 03:49:54 PM PDT 24
Peak memory 205808 kb
Host smart-05f72f16-8b90-41d5-8f56-75a89df60c98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741081916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.741081916
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1129717873
Short name T148
Test name
Test status
Simulation time 625315854 ps
CPU time 9.01 seconds
Started May 04 03:49:52 PM PDT 24
Finished May 04 03:50:02 PM PDT 24
Peak memory 214556 kb
Host smart-f04c6dc2-313d-4b7b-b3b9-c151fcb77acc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1129717873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1129717873
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3959300801
Short name T657
Test name
Test status
Simulation time 128481633 ps
CPU time 3.48 seconds
Started May 04 03:50:06 PM PDT 24
Finished May 04 03:50:10 PM PDT 24
Peak memory 218440 kb
Host smart-af5454fa-7e15-4da6-802a-476a7f1bb0e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959300801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3959300801
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.361390564
Short name T80
Test name
Test status
Simulation time 84193193 ps
CPU time 4 seconds
Started May 04 03:49:55 PM PDT 24
Finished May 04 03:50:00 PM PDT 24
Peak memory 218136 kb
Host smart-89a11596-ec9f-4f46-9d22-bfd573d55eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361390564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.361390564
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3085503316
Short name T95
Test name
Test status
Simulation time 345986752 ps
CPU time 4.94 seconds
Started May 04 03:49:54 PM PDT 24
Finished May 04 03:50:00 PM PDT 24
Peak memory 214392 kb
Host smart-160013a3-42a3-4f1d-b735-08f8e434e082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085503316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3085503316
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1410019476
Short name T638
Test name
Test status
Simulation time 303271174 ps
CPU time 3.02 seconds
Started May 04 03:49:53 PM PDT 24
Finished May 04 03:49:57 PM PDT 24
Peak memory 214304 kb
Host smart-13b378b7-265b-4226-ab2d-4ed9c718e143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410019476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1410019476
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1888971481
Short name T575
Test name
Test status
Simulation time 4469272235 ps
CPU time 30.88 seconds
Started May 04 03:49:53 PM PDT 24
Finished May 04 03:50:25 PM PDT 24
Peak memory 208396 kb
Host smart-0b18e983-9380-4877-803d-90385b94acf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888971481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1888971481
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.858236246
Short name T286
Test name
Test status
Simulation time 2765896395 ps
CPU time 19.22 seconds
Started May 04 03:49:53 PM PDT 24
Finished May 04 03:50:13 PM PDT 24
Peak memory 208672 kb
Host smart-c1720641-ab7c-4586-af00-e638bef36d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858236246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.858236246
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1612138936
Short name T729
Test name
Test status
Simulation time 15041274397 ps
CPU time 30.87 seconds
Started May 04 03:49:52 PM PDT 24
Finished May 04 03:50:23 PM PDT 24
Peak memory 208908 kb
Host smart-1cab0dec-cea6-4866-bb2b-e26a67d703e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612138936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1612138936
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4251118123
Short name T365
Test name
Test status
Simulation time 107124799 ps
CPU time 2.24 seconds
Started May 04 03:49:53 PM PDT 24
Finished May 04 03:49:56 PM PDT 24
Peak memory 206684 kb
Host smart-233c6f45-0e7c-47d4-9315-03d6d5d12d50
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251118123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4251118123
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.4104567959
Short name T1003
Test name
Test status
Simulation time 922274906 ps
CPU time 9.95 seconds
Started May 04 03:50:03 PM PDT 24
Finished May 04 03:50:14 PM PDT 24
Peak memory 208724 kb
Host smart-f2e654b0-9180-48bf-bb38-924eeaed9bc8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104567959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.4104567959
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.524881940
Short name T934
Test name
Test status
Simulation time 1342097513 ps
CPU time 16.55 seconds
Started May 04 03:49:54 PM PDT 24
Finished May 04 03:50:11 PM PDT 24
Peak memory 207812 kb
Host smart-a9e96cdb-d500-475b-a468-6d3087419d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524881940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.524881940
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2038626201
Short name T998
Test name
Test status
Simulation time 8721533525 ps
CPU time 46.43 seconds
Started May 04 03:50:03 PM PDT 24
Finished May 04 03:50:50 PM PDT 24
Peak memory 208516 kb
Host smart-a998dd1c-341b-408b-b3da-a58a2f8fc55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038626201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2038626201
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2223865109
Short name T928
Test name
Test status
Simulation time 89083112 ps
CPU time 3.89 seconds
Started May 04 03:49:53 PM PDT 24
Finished May 04 03:49:58 PM PDT 24
Peak memory 214388 kb
Host smart-28a6e40d-e48c-4fbb-a105-a3be5a0c1fe5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223865109 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2223865109
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3112616532
Short name T758
Test name
Test status
Simulation time 430755604 ps
CPU time 2.53 seconds
Started May 04 03:49:53 PM PDT 24
Finished May 04 03:49:56 PM PDT 24
Peak memory 209940 kb
Host smart-a560dd79-92e0-4a9d-9c65-2c2a65200083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112616532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3112616532
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2429162225
Short name T100
Test name
Test status
Simulation time 21106807 ps
CPU time 0.87 seconds
Started May 04 03:50:03 PM PDT 24
Finished May 04 03:50:05 PM PDT 24
Peak memory 205856 kb
Host smart-82671035-cae7-46d7-88e9-6df483af5e90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429162225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2429162225
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1241443067
Short name T425
Test name
Test status
Simulation time 197865574 ps
CPU time 3.93 seconds
Started May 04 03:50:04 PM PDT 24
Finished May 04 03:50:09 PM PDT 24
Peak memory 214292 kb
Host smart-cf19d30d-3cee-49ae-9207-0b16497a9792
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1241443067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1241443067
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2596427532
Short name T860
Test name
Test status
Simulation time 58467242 ps
CPU time 2.18 seconds
Started May 04 03:50:02 PM PDT 24
Finished May 04 03:50:05 PM PDT 24
Peak memory 207832 kb
Host smart-4db32978-0849-4a8d-b308-48c713359e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596427532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2596427532
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.4041766964
Short name T666
Test name
Test status
Simulation time 3812555573 ps
CPU time 33.66 seconds
Started May 04 03:50:02 PM PDT 24
Finished May 04 03:50:36 PM PDT 24
Peak memory 220588 kb
Host smart-e4d3ab45-47b3-4cfc-a30a-95ffb99d2b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041766964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.4041766964
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2939777241
Short name T344
Test name
Test status
Simulation time 289863174 ps
CPU time 4.62 seconds
Started May 04 03:50:07 PM PDT 24
Finished May 04 03:50:12 PM PDT 24
Peak memory 210272 kb
Host smart-ddb02a9a-6de7-4010-97c6-82d132fe17b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939777241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2939777241
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1668351448
Short name T377
Test name
Test status
Simulation time 108057651 ps
CPU time 4.5 seconds
Started May 04 03:50:02 PM PDT 24
Finished May 04 03:50:07 PM PDT 24
Peak memory 209936 kb
Host smart-d1884dbc-7f1b-43b7-ab99-734f7800a68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668351448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1668351448
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.4269330618
Short name T1046
Test name
Test status
Simulation time 253722210 ps
CPU time 5.66 seconds
Started May 04 03:50:05 PM PDT 24
Finished May 04 03:50:12 PM PDT 24
Peak memory 209084 kb
Host smart-7e548042-cdff-475a-9876-b836b3d5ca2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269330618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.4269330618
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1702772238
Short name T840
Test name
Test status
Simulation time 49401767 ps
CPU time 2.9 seconds
Started May 04 03:50:02 PM PDT 24
Finished May 04 03:50:06 PM PDT 24
Peak memory 206868 kb
Host smart-5b36443d-4635-410e-bc7b-6df43ad89664
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702772238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1702772238
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2297329020
Short name T354
Test name
Test status
Simulation time 88999449 ps
CPU time 3.67 seconds
Started May 04 03:50:04 PM PDT 24
Finished May 04 03:50:09 PM PDT 24
Peak memory 208832 kb
Host smart-2c221872-6772-4713-bc9f-60bc8aac016c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297329020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2297329020
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2660225844
Short name T228
Test name
Test status
Simulation time 122645610 ps
CPU time 3.13 seconds
Started May 04 03:50:02 PM PDT 24
Finished May 04 03:50:06 PM PDT 24
Peak memory 208240 kb
Host smart-328af9c1-ac17-4d87-9835-23825ce862ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660225844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2660225844
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1853524260
Short name T801
Test name
Test status
Simulation time 48011422 ps
CPU time 2.52 seconds
Started May 04 03:50:05 PM PDT 24
Finished May 04 03:50:08 PM PDT 24
Peak memory 206936 kb
Host smart-92501244-7579-4ee9-b4a5-ab21df2421e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853524260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1853524260
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2212109052
Short name T774
Test name
Test status
Simulation time 50146865 ps
CPU time 0.76 seconds
Started May 04 03:50:03 PM PDT 24
Finished May 04 03:50:05 PM PDT 24
Peak memory 205852 kb
Host smart-359a327a-2808-43f2-ab97-5c597c231962
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212109052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2212109052
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.98142006
Short name T593
Test name
Test status
Simulation time 120985805 ps
CPU time 6.79 seconds
Started May 04 03:50:02 PM PDT 24
Finished May 04 03:50:09 PM PDT 24
Peak memory 221776 kb
Host smart-32b3fa92-6e0e-472d-aac8-fd4e53ab8695
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98142006 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.98142006
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2947091644
Short name T793
Test name
Test status
Simulation time 276004790 ps
CPU time 3.26 seconds
Started May 04 03:50:02 PM PDT 24
Finished May 04 03:50:06 PM PDT 24
Peak memory 208020 kb
Host smart-5e029016-4879-4e1c-ab45-d6029a55f5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947091644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2947091644
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.569369871
Short name T170
Test name
Test status
Simulation time 263883242 ps
CPU time 2.92 seconds
Started May 04 03:50:07 PM PDT 24
Finished May 04 03:50:10 PM PDT 24
Peak memory 210460 kb
Host smart-a971945b-d45f-4d35-b14a-8bdd921ac0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569369871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.569369871
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1050761996
Short name T1022
Test name
Test status
Simulation time 13141673 ps
CPU time 0.75 seconds
Started May 04 03:50:03 PM PDT 24
Finished May 04 03:50:04 PM PDT 24
Peak memory 205804 kb
Host smart-575c77df-4b82-4122-8cde-a253727bf9c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050761996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1050761996
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2707538874
Short name T357
Test name
Test status
Simulation time 117182312 ps
CPU time 3.8 seconds
Started May 04 03:50:06 PM PDT 24
Finished May 04 03:50:10 PM PDT 24
Peak memory 214460 kb
Host smart-26a53597-506a-4304-a9f1-83970e52eeb4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2707538874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2707538874
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1219294917
Short name T8
Test name
Test status
Simulation time 341737914 ps
CPU time 7.92 seconds
Started May 04 03:50:06 PM PDT 24
Finished May 04 03:50:15 PM PDT 24
Peak memory 217172 kb
Host smart-1a265763-ec45-4ebc-9314-c1219b0e15cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219294917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1219294917
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2026399019
Short name T74
Test name
Test status
Simulation time 63329742 ps
CPU time 2.42 seconds
Started May 04 03:50:07 PM PDT 24
Finished May 04 03:50:10 PM PDT 24
Peak memory 214304 kb
Host smart-bebee2ba-81cb-4c85-b1b3-b80eae1b1409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026399019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2026399019
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2185663558
Short name T238
Test name
Test status
Simulation time 86881934 ps
CPU time 3.27 seconds
Started May 04 03:50:05 PM PDT 24
Finished May 04 03:50:09 PM PDT 24
Peak memory 208972 kb
Host smart-692a78f2-d38d-4c85-b3f5-cf1cd46a9d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185663558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2185663558
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2531124786
Short name T748
Test name
Test status
Simulation time 262778550 ps
CPU time 3.37 seconds
Started May 04 03:50:05 PM PDT 24
Finished May 04 03:50:09 PM PDT 24
Peak memory 220176 kb
Host smart-9abea993-205a-4c05-bc1c-e5f803ea8c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531124786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2531124786
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.493806204
Short name T773
Test name
Test status
Simulation time 161187658 ps
CPU time 5.68 seconds
Started May 04 03:50:06 PM PDT 24
Finished May 04 03:50:13 PM PDT 24
Peak memory 218148 kb
Host smart-3048c742-d974-4023-b4d2-c96fa13e4171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493806204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.493806204
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1529399669
Short name T231
Test name
Test status
Simulation time 5668742572 ps
CPU time 42.29 seconds
Started May 04 03:50:03 PM PDT 24
Finished May 04 03:50:46 PM PDT 24
Peak memory 207904 kb
Host smart-428e5c11-d329-44ca-8b45-7192e67964be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529399669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1529399669
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3070933208
Short name T567
Test name
Test status
Simulation time 629122427 ps
CPU time 5.18 seconds
Started May 04 03:50:06 PM PDT 24
Finished May 04 03:50:12 PM PDT 24
Peak memory 206740 kb
Host smart-03419c87-ecfc-40d8-b5b7-6f96b49e1ba6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070933208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3070933208
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2891287989
Short name T676
Test name
Test status
Simulation time 82311358 ps
CPU time 2.49 seconds
Started May 04 03:50:03 PM PDT 24
Finished May 04 03:50:06 PM PDT 24
Peak memory 206956 kb
Host smart-6f212d60-e266-4e49-989d-1872e71f9027
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891287989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2891287989
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.4198123181
Short name T892
Test name
Test status
Simulation time 93368424 ps
CPU time 3.45 seconds
Started May 04 03:50:04 PM PDT 24
Finished May 04 03:50:08 PM PDT 24
Peak memory 206988 kb
Host smart-c7d0caf2-a03f-4f9e-a22c-35c9de99beb9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198123181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.4198123181
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.251514864
Short name T908
Test name
Test status
Simulation time 3026867655 ps
CPU time 31.85 seconds
Started May 04 03:50:04 PM PDT 24
Finished May 04 03:50:37 PM PDT 24
Peak memory 218436 kb
Host smart-ba79222a-b7f4-4a1d-9630-1818abc5c239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251514864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.251514864
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2151129943
Short name T616
Test name
Test status
Simulation time 158157191 ps
CPU time 2.45 seconds
Started May 04 03:50:03 PM PDT 24
Finished May 04 03:50:06 PM PDT 24
Peak memory 206680 kb
Host smart-5b6d0192-2428-4db2-92f5-56a97921db7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151129943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2151129943
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2326978698
Short name T673
Test name
Test status
Simulation time 1155898824 ps
CPU time 4.5 seconds
Started May 04 03:50:06 PM PDT 24
Finished May 04 03:50:11 PM PDT 24
Peak memory 215748 kb
Host smart-b7b79d96-f384-463c-9fa2-d66f5d4110da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326978698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2326978698
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2733334347
Short name T404
Test name
Test status
Simulation time 75812451 ps
CPU time 5.15 seconds
Started May 04 03:50:04 PM PDT 24
Finished May 04 03:50:10 PM PDT 24
Peak memory 222572 kb
Host smart-8fb9a5a5-0d7f-4db2-966e-b21622b6a7a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733334347 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2733334347
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2716228952
Short name T971
Test name
Test status
Simulation time 279939027 ps
CPU time 7.58 seconds
Started May 04 03:50:04 PM PDT 24
Finished May 04 03:50:12 PM PDT 24
Peak memory 207620 kb
Host smart-b4d025c0-928f-43a7-959a-6024952462ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716228952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2716228952
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.748048976
Short name T976
Test name
Test status
Simulation time 4389822165 ps
CPU time 17.73 seconds
Started May 04 03:50:08 PM PDT 24
Finished May 04 03:50:27 PM PDT 24
Peak memory 210988 kb
Host smart-ba7abc27-1905-43a1-88e2-8be0985bf1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748048976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.748048976
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.1491709846
Short name T859
Test name
Test status
Simulation time 54157709 ps
CPU time 0.72 seconds
Started May 04 03:50:10 PM PDT 24
Finished May 04 03:50:11 PM PDT 24
Peak memory 205856 kb
Host smart-47a4fb1c-d937-4352-b882-a10f84d6458a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491709846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1491709846
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.456554897
Short name T864
Test name
Test status
Simulation time 34411539 ps
CPU time 2.48 seconds
Started May 04 03:50:11 PM PDT 24
Finished May 04 03:50:14 PM PDT 24
Peak memory 214304 kb
Host smart-53a9087d-5417-4708-ae93-6c5a7e7c6c02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=456554897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.456554897
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.920800623
Short name T345
Test name
Test status
Simulation time 2389309198 ps
CPU time 26.73 seconds
Started May 04 03:50:05 PM PDT 24
Finished May 04 03:50:33 PM PDT 24
Peak memory 218172 kb
Host smart-d0b7c75d-6ccd-4896-9df4-f69c1a5563ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920800623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.920800623
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3747681985
Short name T725
Test name
Test status
Simulation time 324131755 ps
CPU time 8.46 seconds
Started May 04 03:50:04 PM PDT 24
Finished May 04 03:50:13 PM PDT 24
Peak memory 214224 kb
Host smart-a385fc2e-ece6-442c-8100-4174dbe6740b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747681985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3747681985
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2545606358
Short name T290
Test name
Test status
Simulation time 372366491 ps
CPU time 11.42 seconds
Started May 04 03:50:04 PM PDT 24
Finished May 04 03:50:16 PM PDT 24
Peak memory 222476 kb
Host smart-0e1f355f-0043-4a90-a75b-981a3eb6343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545606358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2545606358
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.127712731
Short name T214
Test name
Test status
Simulation time 141293467 ps
CPU time 4.3 seconds
Started May 04 03:50:04 PM PDT 24
Finished May 04 03:50:09 PM PDT 24
Peak memory 214232 kb
Host smart-0d853e1b-0666-4ff5-a523-8d3e64b256a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127712731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.127712731
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.239018006
Short name T585
Test name
Test status
Simulation time 593524375 ps
CPU time 8.44 seconds
Started May 04 03:50:06 PM PDT 24
Finished May 04 03:50:15 PM PDT 24
Peak memory 209204 kb
Host smart-9c3bc409-494d-48c8-a2b1-9b5b56dfaab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239018006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.239018006
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1875907975
Short name T1057
Test name
Test status
Simulation time 146028051 ps
CPU time 4.66 seconds
Started May 04 03:50:10 PM PDT 24
Finished May 04 03:50:15 PM PDT 24
Peak memory 207796 kb
Host smart-3f34cfc1-eb2d-465f-9454-bb8e411aee9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875907975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1875907975
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1092372062
Short name T782
Test name
Test status
Simulation time 1640995525 ps
CPU time 12.69 seconds
Started May 04 03:50:07 PM PDT 24
Finished May 04 03:50:20 PM PDT 24
Peak memory 209032 kb
Host smart-2c4109b9-1b20-4fab-8e13-4ebd100e2904
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092372062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1092372062
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2438366734
Short name T1043
Test name
Test status
Simulation time 228205082 ps
CPU time 3.56 seconds
Started May 04 03:50:11 PM PDT 24
Finished May 04 03:50:15 PM PDT 24
Peak memory 208620 kb
Host smart-c0e73c8e-a7b6-4412-829f-8384b29d6553
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438366734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2438366734
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1772570005
Short name T764
Test name
Test status
Simulation time 1019998228 ps
CPU time 26.8 seconds
Started May 04 03:50:08 PM PDT 24
Finished May 04 03:50:35 PM PDT 24
Peak memory 208204 kb
Host smart-14d5228b-c8eb-4eb0-9b39-6eebbbb0885b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772570005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1772570005
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3124332077
Short name T959
Test name
Test status
Simulation time 153549461 ps
CPU time 2.77 seconds
Started May 04 03:50:04 PM PDT 24
Finished May 04 03:50:08 PM PDT 24
Peak memory 209572 kb
Host smart-afda8470-d4be-4436-aad2-a9f5bd16a991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124332077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3124332077
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2192712822
Short name T573
Test name
Test status
Simulation time 657869552 ps
CPU time 5.35 seconds
Started May 04 03:50:03 PM PDT 24
Finished May 04 03:50:09 PM PDT 24
Peak memory 206540 kb
Host smart-7f42a6cc-988a-4fdf-ae8c-5251ff06bdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192712822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2192712822
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1793608147
Short name T1002
Test name
Test status
Simulation time 370257982 ps
CPU time 3.86 seconds
Started May 04 03:50:07 PM PDT 24
Finished May 04 03:50:11 PM PDT 24
Peak memory 207956 kb
Host smart-4c704877-75ad-442d-b915-7d600b75a1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793608147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1793608147
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.469657732
Short name T407
Test name
Test status
Simulation time 581440440 ps
CPU time 5.61 seconds
Started May 04 03:50:05 PM PDT 24
Finished May 04 03:50:11 PM PDT 24
Peak memory 210940 kb
Host smart-b274895b-5676-4ce4-9c83-e22540e58d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469657732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.469657732
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1261873532
Short name T631
Test name
Test status
Simulation time 10904652 ps
CPU time 0.73 seconds
Started May 04 03:50:20 PM PDT 24
Finished May 04 03:50:22 PM PDT 24
Peak memory 205796 kb
Host smart-ae287bd8-d125-435d-9c8c-a6a673f40dc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261873532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1261873532
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1441019651
Short name T46
Test name
Test status
Simulation time 54162257 ps
CPU time 2.51 seconds
Started May 04 03:50:08 PM PDT 24
Finished May 04 03:50:11 PM PDT 24
Peak memory 208912 kb
Host smart-77ec7e6a-9532-4fd6-9747-6347c2e32dd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441019651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1441019651
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1266201458
Short name T23
Test name
Test status
Simulation time 406624240 ps
CPU time 5.06 seconds
Started May 04 03:50:10 PM PDT 24
Finished May 04 03:50:16 PM PDT 24
Peak memory 208792 kb
Host smart-3fa98d54-ee9e-461e-a604-e9e993a73758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266201458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1266201458
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3826779523
Short name T198
Test name
Test status
Simulation time 276139600 ps
CPU time 3.9 seconds
Started May 04 03:50:09 PM PDT 24
Finished May 04 03:50:13 PM PDT 24
Peak memory 214296 kb
Host smart-bd623501-df39-40b8-bcb6-dffa2dadd23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826779523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3826779523
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3977329449
Short name T216
Test name
Test status
Simulation time 187799359 ps
CPU time 4.66 seconds
Started May 04 03:50:12 PM PDT 24
Finished May 04 03:50:17 PM PDT 24
Peak memory 220148 kb
Host smart-5fa39c11-ecc5-4a0c-b675-578a4dc9706a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977329449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3977329449
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.2395151220
Short name T912
Test name
Test status
Simulation time 2231763229 ps
CPU time 9.52 seconds
Started May 04 03:50:08 PM PDT 24
Finished May 04 03:50:18 PM PDT 24
Peak memory 210196 kb
Host smart-998565b0-bc65-4500-be1a-fb8f877486c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395151220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.2395151220
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1125445840
Short name T107
Test name
Test status
Simulation time 253154610 ps
CPU time 3.45 seconds
Started May 04 03:50:16 PM PDT 24
Finished May 04 03:50:21 PM PDT 24
Peak memory 207112 kb
Host smart-0a74e57c-a94a-43fa-9802-a8a79770280a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125445840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1125445840
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3413149380
Short name T902
Test name
Test status
Simulation time 58678536 ps
CPU time 3.03 seconds
Started May 04 03:50:10 PM PDT 24
Finished May 04 03:50:13 PM PDT 24
Peak memory 208336 kb
Host smart-54ad577f-842d-42ca-bfca-41bf91ea0246
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413149380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3413149380
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.4062927852
Short name T693
Test name
Test status
Simulation time 208652113 ps
CPU time 3.73 seconds
Started May 04 03:50:13 PM PDT 24
Finished May 04 03:50:18 PM PDT 24
Peak memory 208768 kb
Host smart-5ec74974-73ab-4e67-aa92-f635dc5a6e4c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062927852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.4062927852
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1864677642
Short name T1071
Test name
Test status
Simulation time 54918854 ps
CPU time 3.05 seconds
Started May 04 03:50:10 PM PDT 24
Finished May 04 03:50:13 PM PDT 24
Peak memory 206908 kb
Host smart-5f11cd93-9f39-49b3-939b-43776bda2eaa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864677642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1864677642
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3424039902
Short name T594
Test name
Test status
Simulation time 248277387 ps
CPU time 4.15 seconds
Started May 04 03:50:14 PM PDT 24
Finished May 04 03:50:19 PM PDT 24
Peak memory 210228 kb
Host smart-aba769ee-46c5-4d33-b619-5339b6768fbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424039902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3424039902
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.4051127794
Short name T789
Test name
Test status
Simulation time 320977876 ps
CPU time 3.34 seconds
Started May 04 03:50:16 PM PDT 24
Finished May 04 03:50:20 PM PDT 24
Peak memory 208396 kb
Host smart-eb8c7267-43d2-4517-a528-ba9f4f4abe79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051127794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.4051127794
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.574409821
Short name T210
Test name
Test status
Simulation time 613751010 ps
CPU time 12.6 seconds
Started May 04 03:50:21 PM PDT 24
Finished May 04 03:50:34 PM PDT 24
Peak memory 216296 kb
Host smart-4eaf57ba-ddbe-4de4-869c-90f952c84ac0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574409821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.574409821
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.830464665
Short name T217
Test name
Test status
Simulation time 486731923 ps
CPU time 5.9 seconds
Started May 04 03:50:15 PM PDT 24
Finished May 04 03:50:21 PM PDT 24
Peak memory 222520 kb
Host smart-cf2a8b70-498e-448b-8c9c-9cf2df1148bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830464665 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.830464665
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.459655038
Short name T303
Test name
Test status
Simulation time 452092868 ps
CPU time 6.26 seconds
Started May 04 03:50:09 PM PDT 24
Finished May 04 03:50:16 PM PDT 24
Peak memory 208020 kb
Host smart-26c11453-4ec0-4026-9001-92d9d1c3e969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459655038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.459655038
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.274673412
Short name T699
Test name
Test status
Simulation time 1230960739 ps
CPU time 6.26 seconds
Started May 04 03:50:15 PM PDT 24
Finished May 04 03:50:22 PM PDT 24
Peak memory 210612 kb
Host smart-100ea95f-1bbf-4e45-9931-93ad7aa15350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274673412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.274673412
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2456721253
Short name T597
Test name
Test status
Simulation time 37032828 ps
CPU time 0.85 seconds
Started May 04 03:50:17 PM PDT 24
Finished May 04 03:50:19 PM PDT 24
Peak memory 205848 kb
Host smart-473bad3e-0753-4522-baf6-05d747190e40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456721253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2456721253
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3814125760
Short name T750
Test name
Test status
Simulation time 26028322 ps
CPU time 1.86 seconds
Started May 04 03:50:17 PM PDT 24
Finished May 04 03:50:20 PM PDT 24
Peak memory 208520 kb
Host smart-7b7b6e96-f0bb-4db2-9cb4-c61067c01a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814125760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3814125760
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2664467562
Short name T815
Test name
Test status
Simulation time 102485187 ps
CPU time 2.59 seconds
Started May 04 03:50:17 PM PDT 24
Finished May 04 03:50:20 PM PDT 24
Peak memory 210000 kb
Host smart-1c024901-81f7-4140-aec8-28ccead38473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664467562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2664467562
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.871582705
Short name T718
Test name
Test status
Simulation time 152647106 ps
CPU time 4.58 seconds
Started May 04 03:50:20 PM PDT 24
Finished May 04 03:50:26 PM PDT 24
Peak memory 208728 kb
Host smart-6a7ec4d4-5c65-4a02-9d59-9e91c5bc7a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871582705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.871582705
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.1839947307
Short name T20
Test name
Test status
Simulation time 3899713942 ps
CPU time 9.4 seconds
Started May 04 03:50:18 PM PDT 24
Finished May 04 03:50:28 PM PDT 24
Peak memory 214304 kb
Host smart-3c9d0db0-8e0c-43d8-af72-b0de8c67ff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839947307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.1839947307
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2531032762
Short name T603
Test name
Test status
Simulation time 83930154 ps
CPU time 3.8 seconds
Started May 04 03:50:14 PM PDT 24
Finished May 04 03:50:19 PM PDT 24
Peak memory 218016 kb
Host smart-927e2d24-b96c-464c-b108-dec9857f44c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531032762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2531032762
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3673333888
Short name T615
Test name
Test status
Simulation time 421167852 ps
CPU time 5.12 seconds
Started May 04 03:50:17 PM PDT 24
Finished May 04 03:50:22 PM PDT 24
Peak memory 207180 kb
Host smart-5d7282f9-b5f7-4caa-94ae-a05e5b1c1303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673333888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3673333888
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2789025951
Short name T684
Test name
Test status
Simulation time 125398915 ps
CPU time 2.35 seconds
Started May 04 03:50:20 PM PDT 24
Finished May 04 03:50:23 PM PDT 24
Peak memory 206680 kb
Host smart-9d375e5a-85e2-471d-8b9a-f0b8b9e59daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789025951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2789025951
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2904014157
Short name T977
Test name
Test status
Simulation time 1865880095 ps
CPU time 8.4 seconds
Started May 04 03:50:15 PM PDT 24
Finished May 04 03:50:24 PM PDT 24
Peak memory 207948 kb
Host smart-78845ec1-df4a-4f46-8159-4ada09e8b051
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904014157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2904014157
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2814029139
Short name T771
Test name
Test status
Simulation time 311378447 ps
CPU time 3.89 seconds
Started May 04 03:50:18 PM PDT 24
Finished May 04 03:50:23 PM PDT 24
Peak memory 208540 kb
Host smart-2db561da-5bdc-4978-942d-82948a52b45c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814029139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2814029139
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3186938231
Short name T315
Test name
Test status
Simulation time 331032383 ps
CPU time 3.45 seconds
Started May 04 03:50:15 PM PDT 24
Finished May 04 03:50:19 PM PDT 24
Peak memory 206884 kb
Host smart-f3ba9182-216c-4cef-8a87-34d6eb503e9e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186938231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3186938231
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.308252841
Short name T700
Test name
Test status
Simulation time 43320439 ps
CPU time 2.76 seconds
Started May 04 03:50:16 PM PDT 24
Finished May 04 03:50:20 PM PDT 24
Peak memory 218344 kb
Host smart-9027c054-3d0c-4c42-b44d-62957384da51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308252841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.308252841
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.4030420234
Short name T927
Test name
Test status
Simulation time 687907724 ps
CPU time 8.45 seconds
Started May 04 03:50:16 PM PDT 24
Finished May 04 03:50:25 PM PDT 24
Peak memory 206640 kb
Host smart-1ccaab24-2906-4e2d-9bc1-ffa665c427d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030420234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.4030420234
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1482057759
Short name T1038
Test name
Test status
Simulation time 173031319 ps
CPU time 4.13 seconds
Started May 04 03:50:17 PM PDT 24
Finished May 04 03:50:22 PM PDT 24
Peak memory 208888 kb
Host smart-0ea17c26-7835-487f-82cb-94184a1e5139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482057759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1482057759
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.3883059734
Short name T991
Test name
Test status
Simulation time 800995802 ps
CPU time 9 seconds
Started May 04 03:50:13 PM PDT 24
Finished May 04 03:50:23 PM PDT 24
Peak memory 222716 kb
Host smart-b819c741-2106-4dc4-b759-d83d010d8497
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883059734 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.3883059734
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.832180056
Short name T403
Test name
Test status
Simulation time 121617224 ps
CPU time 2.68 seconds
Started May 04 03:50:15 PM PDT 24
Finished May 04 03:50:18 PM PDT 24
Peak memory 209796 kb
Host smart-d76bc1a9-5e86-4f36-802f-f47d7d9c91b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832180056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.832180056
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.283949559
Short name T692
Test name
Test status
Simulation time 29288315 ps
CPU time 0.84 seconds
Started May 04 03:50:21 PM PDT 24
Finished May 04 03:50:22 PM PDT 24
Peak memory 205888 kb
Host smart-d4471211-adfd-4a00-9404-48334afb12f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283949559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.283949559
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2429659476
Short name T283
Test name
Test status
Simulation time 36129128 ps
CPU time 2.86 seconds
Started May 04 03:50:21 PM PDT 24
Finished May 04 03:50:25 PM PDT 24
Peak memory 214324 kb
Host smart-d6c760a6-0631-41b3-9471-c6fed08bbdb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2429659476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2429659476
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.424952197
Short name T780
Test name
Test status
Simulation time 140936650 ps
CPU time 6.72 seconds
Started May 04 03:50:20 PM PDT 24
Finished May 04 03:50:27 PM PDT 24
Peak memory 214248 kb
Host smart-429c7625-54d9-4ee5-99db-3c95f933f268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424952197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.424952197
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.301608235
Short name T59
Test name
Test status
Simulation time 67899349 ps
CPU time 3.58 seconds
Started May 04 03:50:20 PM PDT 24
Finished May 04 03:50:25 PM PDT 24
Peak memory 219744 kb
Host smart-8cc6c569-e2fc-4ec8-9041-a3c8ed09aa93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301608235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.301608235
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1432455657
Short name T968
Test name
Test status
Simulation time 243848361 ps
CPU time 4.19 seconds
Started May 04 03:50:21 PM PDT 24
Finished May 04 03:50:26 PM PDT 24
Peak memory 220120 kb
Host smart-ea277821-ad69-4c71-8e89-f0090ec641d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432455657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1432455657
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.935006176
Short name T289
Test name
Test status
Simulation time 801089900 ps
CPU time 12.27 seconds
Started May 04 03:50:20 PM PDT 24
Finished May 04 03:50:33 PM PDT 24
Peak memory 214232 kb
Host smart-7a67cb87-21b5-4ff5-b94f-ce08454de143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935006176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.935006176
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_random.3442215451
Short name T930
Test name
Test status
Simulation time 549268589 ps
CPU time 5.16 seconds
Started May 04 03:50:21 PM PDT 24
Finished May 04 03:50:27 PM PDT 24
Peak memory 210004 kb
Host smart-dfe7a2e2-fef8-4665-b3dc-9f7f7b0b8166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442215451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3442215451
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2597997608
Short name T708
Test name
Test status
Simulation time 4324891324 ps
CPU time 86 seconds
Started May 04 03:50:18 PM PDT 24
Finished May 04 03:51:44 PM PDT 24
Peak memory 209068 kb
Host smart-2b2d1db5-ba34-4172-b209-54bf837f891f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597997608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2597997608
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.405076119
Short name T134
Test name
Test status
Simulation time 239914961 ps
CPU time 6.76 seconds
Started May 04 03:50:15 PM PDT 24
Finished May 04 03:50:23 PM PDT 24
Peak memory 207792 kb
Host smart-2c6a325f-65f9-4004-a2bf-3bc6ce981a1a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405076119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.405076119
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.531481540
Short name T600
Test name
Test status
Simulation time 347960859 ps
CPU time 7.97 seconds
Started May 04 03:50:17 PM PDT 24
Finished May 04 03:50:26 PM PDT 24
Peak memory 207828 kb
Host smart-280f7b0e-b951-4c43-abc7-1552acb44c44
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531481540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.531481540
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.1283414676
Short name T925
Test name
Test status
Simulation time 34443514 ps
CPU time 2.39 seconds
Started May 04 03:50:21 PM PDT 24
Finished May 04 03:50:24 PM PDT 24
Peak memory 206828 kb
Host smart-6e155e72-d02b-4032-89b4-504c0201d994
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283414676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.1283414676
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1083881759
Short name T1018
Test name
Test status
Simulation time 56229758 ps
CPU time 2.48 seconds
Started May 04 03:50:21 PM PDT 24
Finished May 04 03:50:24 PM PDT 24
Peak memory 209328 kb
Host smart-67df03df-fc9b-4e90-b2b6-e039cc40d585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083881759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1083881759
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3781493792
Short name T2
Test name
Test status
Simulation time 289811347 ps
CPU time 4.2 seconds
Started May 04 03:50:17 PM PDT 24
Finished May 04 03:50:22 PM PDT 24
Peak memory 208040 kb
Host smart-32227298-2a10-4e3b-8eec-554344644770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781493792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3781493792
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3339116489
Short name T49
Test name
Test status
Simulation time 2175311011 ps
CPU time 10.2 seconds
Started May 04 03:50:21 PM PDT 24
Finished May 04 03:50:32 PM PDT 24
Peak memory 216228 kb
Host smart-940d33bd-cf10-459e-9bdb-4e90354d1012
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339116489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3339116489
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.168176802
Short name T664
Test name
Test status
Simulation time 120192492 ps
CPU time 4.87 seconds
Started May 04 03:50:20 PM PDT 24
Finished May 04 03:50:26 PM PDT 24
Peak memory 222572 kb
Host smart-51907ba8-f63d-45ea-b3eb-4a900632745c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168176802 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.168176802
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3922533944
Short name T195
Test name
Test status
Simulation time 1518720243 ps
CPU time 10.39 seconds
Started May 04 03:50:19 PM PDT 24
Finished May 04 03:50:30 PM PDT 24
Peak memory 208436 kb
Host smart-11711673-003f-49ee-9f91-877bb257a0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922533944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3922533944
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2556077985
Short name T35
Test name
Test status
Simulation time 55801417 ps
CPU time 1.46 seconds
Started May 04 03:50:20 PM PDT 24
Finished May 04 03:50:22 PM PDT 24
Peak memory 209696 kb
Host smart-aad074f3-a4ab-4d70-a76b-5588663dc56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556077985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2556077985
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.621505746
Short name T858
Test name
Test status
Simulation time 46827130 ps
CPU time 0.74 seconds
Started May 04 03:46:42 PM PDT 24
Finished May 04 03:46:44 PM PDT 24
Peak memory 205860 kb
Host smart-4c243fb6-ba71-40b2-a591-bc68e2e1a8c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621505746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.621505746
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1968207865
Short name T802
Test name
Test status
Simulation time 71929917 ps
CPU time 3.54 seconds
Started May 04 03:46:36 PM PDT 24
Finished May 04 03:46:39 PM PDT 24
Peak memory 207392 kb
Host smart-df107b6c-c512-4ef3-b80b-d51d534489a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968207865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1968207865
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1787711759
Short name T909
Test name
Test status
Simulation time 122747371 ps
CPU time 2.3 seconds
Started May 04 03:46:30 PM PDT 24
Finished May 04 03:46:33 PM PDT 24
Peak memory 214288 kb
Host smart-faf5bb82-3a4c-4d07-9165-29bf63b2397f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787711759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1787711759
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2731839484
Short name T98
Test name
Test status
Simulation time 70283754 ps
CPU time 3.45 seconds
Started May 04 03:46:34 PM PDT 24
Finished May 04 03:46:38 PM PDT 24
Peak memory 209068 kb
Host smart-f4e81d67-5fa9-49a5-8f37-9ac0a73590e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731839484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2731839484
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.174247436
Short name T796
Test name
Test status
Simulation time 659392357 ps
CPU time 5.48 seconds
Started May 04 03:46:34 PM PDT 24
Finished May 04 03:46:40 PM PDT 24
Peak memory 208896 kb
Host smart-206137c9-6185-403e-9bc0-260113ce6cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174247436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.174247436
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1146301042
Short name T911
Test name
Test status
Simulation time 2645758936 ps
CPU time 86.87 seconds
Started May 04 03:46:28 PM PDT 24
Finished May 04 03:47:55 PM PDT 24
Peak memory 218400 kb
Host smart-7b19fe14-e429-4596-93e9-5a79359a88be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146301042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1146301042
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1224911110
Short name T312
Test name
Test status
Simulation time 91967213 ps
CPU time 3.74 seconds
Started May 04 03:46:29 PM PDT 24
Finished May 04 03:46:33 PM PDT 24
Peak memory 207324 kb
Host smart-34f88b75-4a40-440b-a532-367590c0cc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224911110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1224911110
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3179108053
Short name T1049
Test name
Test status
Simulation time 160401753 ps
CPU time 4.46 seconds
Started May 04 03:46:30 PM PDT 24
Finished May 04 03:46:35 PM PDT 24
Peak memory 208696 kb
Host smart-004e806d-12bd-4291-b108-1bb0f0bdec43
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179108053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3179108053
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.978514792
Short name T846
Test name
Test status
Simulation time 774255500 ps
CPU time 4.76 seconds
Started May 04 03:46:29 PM PDT 24
Finished May 04 03:46:34 PM PDT 24
Peak memory 207184 kb
Host smart-665fe7e4-4ab7-4caf-806c-e341fc46ff1b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978514792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.978514792
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.803814232
Short name T776
Test name
Test status
Simulation time 46112909 ps
CPU time 2.08 seconds
Started May 04 03:46:32 PM PDT 24
Finished May 04 03:46:34 PM PDT 24
Peak memory 208556 kb
Host smart-5109ac93-aff9-4fe9-976f-c5f376a79e66
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803814232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.803814232
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3259479598
Short name T887
Test name
Test status
Simulation time 135709771 ps
CPU time 3.24 seconds
Started May 04 03:46:34 PM PDT 24
Finished May 04 03:46:38 PM PDT 24
Peak memory 214400 kb
Host smart-74a9703e-f052-4a1a-a1e1-5b2696a27d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259479598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3259479598
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2411305938
Short name T12
Test name
Test status
Simulation time 91346305 ps
CPU time 1.82 seconds
Started May 04 03:46:30 PM PDT 24
Finished May 04 03:46:32 PM PDT 24
Peak memory 206676 kb
Host smart-40ead08c-c9f6-4cda-9420-73927921c416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411305938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2411305938
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.261504695
Short name T204
Test name
Test status
Simulation time 2376630497 ps
CPU time 45.16 seconds
Started May 04 03:46:41 PM PDT 24
Finished May 04 03:47:27 PM PDT 24
Peak memory 216228 kb
Host smart-289fc02a-aaeb-4c77-9f03-594f91026a81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261504695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.261504695
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.3844184964
Short name T1042
Test name
Test status
Simulation time 510436958 ps
CPU time 6.19 seconds
Started May 04 03:46:41 PM PDT 24
Finished May 04 03:46:48 PM PDT 24
Peak memory 219420 kb
Host smart-7e804377-d892-48e8-82fc-d7eb087db1e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844184964 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.3844184964
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2370275540
Short name T580
Test name
Test status
Simulation time 2122122150 ps
CPU time 69.67 seconds
Started May 04 03:46:34 PM PDT 24
Finished May 04 03:47:44 PM PDT 24
Peak memory 209072 kb
Host smart-e9dc05dd-2216-4ce3-906b-803377d20c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370275540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2370275540
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3495483756
Short name T961
Test name
Test status
Simulation time 59448935 ps
CPU time 2.14 seconds
Started May 04 03:46:41 PM PDT 24
Finished May 04 03:46:44 PM PDT 24
Peak memory 210076 kb
Host smart-8ae85c83-6521-4894-b19c-6207574fdc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495483756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3495483756
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.904079239
Short name T570
Test name
Test status
Simulation time 32373027 ps
CPU time 0.71 seconds
Started May 04 03:46:49 PM PDT 24
Finished May 04 03:46:50 PM PDT 24
Peak memory 205880 kb
Host smart-ee4925b3-660f-42d1-ba1c-a0577372f862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904079239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.904079239
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.327562399
Short name T424
Test name
Test status
Simulation time 57572807 ps
CPU time 2.57 seconds
Started May 04 03:46:41 PM PDT 24
Finished May 04 03:46:44 PM PDT 24
Peak memory 214304 kb
Host smart-901aa7db-0392-40d6-b29c-d722c59006ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=327562399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.327562399
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.587663049
Short name T158
Test name
Test status
Simulation time 606515279 ps
CPU time 7.86 seconds
Started May 04 03:46:47 PM PDT 24
Finished May 04 03:46:55 PM PDT 24
Peak memory 218340 kb
Host smart-ab3ee2d2-c0bf-4dd7-af45-cabc36e09dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587663049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.587663049
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1698214922
Short name T331
Test name
Test status
Simulation time 190119902 ps
CPU time 1.83 seconds
Started May 04 03:46:41 PM PDT 24
Finished May 04 03:46:43 PM PDT 24
Peak memory 218356 kb
Host smart-cc26fcc2-f55c-44a3-9f98-cc24434ea032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698214922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1698214922
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1261414843
Short name T90
Test name
Test status
Simulation time 168489049 ps
CPU time 6.95 seconds
Started May 04 03:46:49 PM PDT 24
Finished May 04 03:46:56 PM PDT 24
Peak memory 219124 kb
Host smart-fe5e284b-05bb-4cf2-a93d-814d1eb7c285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261414843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1261414843
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1855098571
Short name T202
Test name
Test status
Simulation time 402559447 ps
CPU time 5.27 seconds
Started May 04 03:46:46 PM PDT 24
Finished May 04 03:46:51 PM PDT 24
Peak memory 222396 kb
Host smart-7501b8b1-1b57-4a6d-9d64-4cdcb4c72afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855098571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1855098571
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.436804460
Short name T722
Test name
Test status
Simulation time 168073399 ps
CPU time 1.82 seconds
Started May 04 03:46:40 PM PDT 24
Finished May 04 03:46:42 PM PDT 24
Peak memory 206440 kb
Host smart-8f69741c-b22f-4713-8f23-3b24c49e304f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436804460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.436804460
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1458543711
Short name T306
Test name
Test status
Simulation time 40647108 ps
CPU time 3.06 seconds
Started May 04 03:46:42 PM PDT 24
Finished May 04 03:46:46 PM PDT 24
Peak memory 210084 kb
Host smart-cc9df129-b473-406f-825c-a2517e532981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458543711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1458543711
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1605073715
Short name T834
Test name
Test status
Simulation time 858949056 ps
CPU time 23.36 seconds
Started May 04 03:46:41 PM PDT 24
Finished May 04 03:47:06 PM PDT 24
Peak memory 208148 kb
Host smart-d58819ab-3c7d-4023-8d70-5181def9ea81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605073715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1605073715
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.11414261
Short name T841
Test name
Test status
Simulation time 766974641 ps
CPU time 6.21 seconds
Started May 04 03:46:41 PM PDT 24
Finished May 04 03:46:48 PM PDT 24
Peak memory 208800 kb
Host smart-51af088d-fccb-4e1c-a5db-38705efeb2de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11414261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.11414261
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.4145937054
Short name T383
Test name
Test status
Simulation time 118646326 ps
CPU time 2.29 seconds
Started May 04 03:46:41 PM PDT 24
Finished May 04 03:46:43 PM PDT 24
Peak memory 206864 kb
Host smart-2c16c9c9-094e-41cd-85b4-fdc4c92fee18
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145937054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.4145937054
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2374055087
Short name T691
Test name
Test status
Simulation time 85263608 ps
CPU time 3.09 seconds
Started May 04 03:46:42 PM PDT 24
Finished May 04 03:46:46 PM PDT 24
Peak memory 208816 kb
Host smart-373195f2-203f-4fb2-86a0-922639240aba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374055087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2374055087
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.675691241
Short name T182
Test name
Test status
Simulation time 4449102215 ps
CPU time 45.68 seconds
Started May 04 03:46:46 PM PDT 24
Finished May 04 03:47:32 PM PDT 24
Peak memory 214452 kb
Host smart-b78cf29d-553d-49a7-90d0-c8c630bb09de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675691241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.675691241
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2047189230
Short name T913
Test name
Test status
Simulation time 179488689 ps
CPU time 2.54 seconds
Started May 04 03:46:39 PM PDT 24
Finished May 04 03:46:42 PM PDT 24
Peak memory 206696 kb
Host smart-95d318ee-c166-46bd-98d8-1b40f4f161ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047189230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2047189230
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.679316208
Short name T65
Test name
Test status
Simulation time 1395875603 ps
CPU time 29.68 seconds
Started May 04 03:46:46 PM PDT 24
Finished May 04 03:47:16 PM PDT 24
Peak memory 222444 kb
Host smart-258be20d-e086-4f43-9b7d-6654ed14e0bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679316208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.679316208
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1317273595
Short name T685
Test name
Test status
Simulation time 128473849 ps
CPU time 2.81 seconds
Started May 04 03:46:46 PM PDT 24
Finished May 04 03:46:49 PM PDT 24
Peak memory 218252 kb
Host smart-7d9add28-2465-4ecc-ab65-4dbdf83916b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317273595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1317273595
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2757740595
Short name T660
Test name
Test status
Simulation time 68730421 ps
CPU time 2.35 seconds
Started May 04 03:46:47 PM PDT 24
Finished May 04 03:46:50 PM PDT 24
Peak memory 210452 kb
Host smart-deb2e31e-93f6-4acc-b866-d76d880df8b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757740595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2757740595
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3532783687
Short name T735
Test name
Test status
Simulation time 48882722 ps
CPU time 0.92 seconds
Started May 04 03:46:53 PM PDT 24
Finished May 04 03:46:55 PM PDT 24
Peak memory 205884 kb
Host smart-5dfd3fde-d803-45ee-9a7d-0620f864bd98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532783687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3532783687
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3699589274
Short name T111
Test name
Test status
Simulation time 183044310 ps
CPU time 3.45 seconds
Started May 04 03:46:46 PM PDT 24
Finished May 04 03:46:50 PM PDT 24
Peak memory 214220 kb
Host smart-8b6d36ca-e695-4a6a-b6d8-a2b66424d6dc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3699589274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3699589274
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2198591024
Short name T1040
Test name
Test status
Simulation time 267577203 ps
CPU time 2.62 seconds
Started May 04 03:46:46 PM PDT 24
Finished May 04 03:46:50 PM PDT 24
Peak memory 208996 kb
Host smart-5cefbe09-8226-41fe-9289-9cba439fbec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198591024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2198591024
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2576725562
Short name T373
Test name
Test status
Simulation time 247298595 ps
CPU time 3.74 seconds
Started May 04 03:46:48 PM PDT 24
Finished May 04 03:46:52 PM PDT 24
Peak memory 209732 kb
Host smart-300b6078-1f72-4402-899c-189ea7ccc8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576725562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2576725562
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.867746402
Short name T294
Test name
Test status
Simulation time 167519137 ps
CPU time 8 seconds
Started May 04 03:46:47 PM PDT 24
Finished May 04 03:46:56 PM PDT 24
Peak memory 214196 kb
Host smart-d3769832-7a95-4d39-8486-a93cce4587e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867746402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.867746402
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1297616506
Short name T987
Test name
Test status
Simulation time 49898601 ps
CPU time 2.86 seconds
Started May 04 03:46:48 PM PDT 24
Finished May 04 03:46:52 PM PDT 24
Peak memory 220200 kb
Host smart-5863f657-f502-48df-86b6-7eedc069fa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297616506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1297616506
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2763002828
Short name T890
Test name
Test status
Simulation time 558927006 ps
CPU time 5.09 seconds
Started May 04 03:46:46 PM PDT 24
Finished May 04 03:46:52 PM PDT 24
Peak memory 207616 kb
Host smart-e5e9dfcf-1ab7-4099-a645-7f0f42095b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763002828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2763002828
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1503412498
Short name T742
Test name
Test status
Simulation time 411380596 ps
CPU time 4.36 seconds
Started May 04 03:46:47 PM PDT 24
Finished May 04 03:46:52 PM PDT 24
Peak memory 208780 kb
Host smart-f716d549-b080-4ce6-8d4a-06ccad715e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503412498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1503412498
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.341126454
Short name T745
Test name
Test status
Simulation time 764311953 ps
CPU time 8.51 seconds
Started May 04 03:46:47 PM PDT 24
Finished May 04 03:46:56 PM PDT 24
Peak memory 208776 kb
Host smart-8079958d-bf21-4064-92bc-9fc3d9f22e83
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341126454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.341126454
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2557660190
Short name T364
Test name
Test status
Simulation time 60888042 ps
CPU time 2.62 seconds
Started May 04 03:46:49 PM PDT 24
Finished May 04 03:46:52 PM PDT 24
Peak memory 207612 kb
Host smart-93f7e835-1e3d-4020-9e8c-c3748250e2af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557660190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2557660190
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1489167645
Short name T809
Test name
Test status
Simulation time 115871225 ps
CPU time 3.1 seconds
Started May 04 03:46:46 PM PDT 24
Finished May 04 03:46:50 PM PDT 24
Peak memory 207176 kb
Host smart-abc7ec38-05ab-4674-9f63-ca084cb74183
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489167645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1489167645
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3310820638
Short name T981
Test name
Test status
Simulation time 179877745 ps
CPU time 4.64 seconds
Started May 04 03:46:52 PM PDT 24
Finished May 04 03:46:57 PM PDT 24
Peak memory 208652 kb
Host smart-f62db37b-c563-43d4-b1c8-3cfa8cf8fca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310820638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3310820638
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3109339573
Short name T812
Test name
Test status
Simulation time 122578390 ps
CPU time 2.23 seconds
Started May 04 03:46:47 PM PDT 24
Finished May 04 03:46:50 PM PDT 24
Peak memory 206744 kb
Host smart-e69894b4-52cd-42a9-98dd-8866a970a4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109339573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3109339573
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.528225960
Short name T326
Test name
Test status
Simulation time 6902727211 ps
CPU time 53.86 seconds
Started May 04 03:46:55 PM PDT 24
Finished May 04 03:47:49 PM PDT 24
Peak memory 222596 kb
Host smart-4bbca6b0-34e8-4d4f-b7f4-0874a2ed1f7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528225960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.528225960
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3673551462
Short name T608
Test name
Test status
Simulation time 278245736 ps
CPU time 4.63 seconds
Started May 04 03:46:54 PM PDT 24
Finished May 04 03:47:00 PM PDT 24
Peak memory 222664 kb
Host smart-d05976f8-768e-4b7e-9635-6e6c403e0c0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673551462 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3673551462
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.538140166
Short name T933
Test name
Test status
Simulation time 425189895 ps
CPU time 4.7 seconds
Started May 04 03:46:46 PM PDT 24
Finished May 04 03:46:51 PM PDT 24
Peak memory 207260 kb
Host smart-dc5c38ac-6d60-4dc3-be10-5288a63e5f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538140166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.538140166
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.4245977363
Short name T61
Test name
Test status
Simulation time 186854616 ps
CPU time 3.95 seconds
Started May 04 03:46:53 PM PDT 24
Finished May 04 03:46:57 PM PDT 24
Peak memory 210748 kb
Host smart-8f4c0e4f-b1b1-41ad-9ad7-8dceadbacdad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245977363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.4245977363
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.790412331
Short name T613
Test name
Test status
Simulation time 16051516 ps
CPU time 0.73 seconds
Started May 04 03:46:59 PM PDT 24
Finished May 04 03:47:01 PM PDT 24
Peak memory 205796 kb
Host smart-e5832325-0b60-498a-a7c3-62446d06004d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790412331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.790412331
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2606466259
Short name T945
Test name
Test status
Simulation time 75702560 ps
CPU time 4.38 seconds
Started May 04 03:46:59 PM PDT 24
Finished May 04 03:47:04 PM PDT 24
Peak memory 218344 kb
Host smart-f8afdb06-58a8-4675-b98f-1e0dc7fa25fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606466259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2606466259
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1628065599
Short name T321
Test name
Test status
Simulation time 146964238 ps
CPU time 3.36 seconds
Started May 04 03:46:54 PM PDT 24
Finished May 04 03:46:58 PM PDT 24
Peak memory 209720 kb
Host smart-8fde4d51-8057-4e57-9700-81a86f570ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628065599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1628065599
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2778784669
Short name T576
Test name
Test status
Simulation time 121986357 ps
CPU time 5.46 seconds
Started May 04 03:46:54 PM PDT 24
Finished May 04 03:47:00 PM PDT 24
Peak memory 209224 kb
Host smart-f22b5be5-0e2c-44b0-a94f-4797d68f81b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778784669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2778784669
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1900411737
Short name T367
Test name
Test status
Simulation time 329718899 ps
CPU time 4.66 seconds
Started May 04 03:46:58 PM PDT 24
Finished May 04 03:47:04 PM PDT 24
Peak memory 211084 kb
Host smart-c2cac07c-fb04-4e47-b8c2-fee646589007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900411737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1900411737
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1219815557
Short name T208
Test name
Test status
Simulation time 163875654 ps
CPU time 2.9 seconds
Started May 04 03:46:54 PM PDT 24
Finished May 04 03:46:58 PM PDT 24
Peak memory 222460 kb
Host smart-949c3e92-d8d4-4dd8-b49f-fd9f1b664ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219815557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1219815557
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2469554508
Short name T948
Test name
Test status
Simulation time 4931988968 ps
CPU time 66.19 seconds
Started May 04 03:46:53 PM PDT 24
Finished May 04 03:48:00 PM PDT 24
Peak memory 214364 kb
Host smart-b0fcb943-6bc4-40a8-aa25-e0acbf11e8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469554508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2469554508
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2306134513
Short name T353
Test name
Test status
Simulation time 1239511885 ps
CPU time 8.77 seconds
Started May 04 03:46:52 PM PDT 24
Finished May 04 03:47:01 PM PDT 24
Peak memory 208692 kb
Host smart-9361207f-7f7b-40fd-adb6-4d1fdd23d9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306134513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2306134513
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3483466427
Short name T668
Test name
Test status
Simulation time 88306268 ps
CPU time 3.31 seconds
Started May 04 03:46:54 PM PDT 24
Finished May 04 03:46:58 PM PDT 24
Peak memory 207900 kb
Host smart-1ee3864b-7747-4f2b-9631-a9242d11720a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483466427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3483466427
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3263646070
Short name T707
Test name
Test status
Simulation time 200330840 ps
CPU time 3.27 seconds
Started May 04 03:46:52 PM PDT 24
Finished May 04 03:46:56 PM PDT 24
Peak memory 209036 kb
Host smart-918a121c-cebe-4de5-bac7-402ee82e0d52
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263646070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3263646070
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1779466983
Short name T921
Test name
Test status
Simulation time 1618656000 ps
CPU time 24.52 seconds
Started May 04 03:46:52 PM PDT 24
Finished May 04 03:47:17 PM PDT 24
Peak memory 208536 kb
Host smart-d151206d-9529-42a9-8da3-04632ce19c99
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779466983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1779466983
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.260542429
Short name T370
Test name
Test status
Simulation time 1098194347 ps
CPU time 13.05 seconds
Started May 04 03:47:00 PM PDT 24
Finished May 04 03:47:14 PM PDT 24
Peak memory 209508 kb
Host smart-3e45bca2-34f8-4911-b266-94ff492ad583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260542429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.260542429
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.397239294
Short name T635
Test name
Test status
Simulation time 983447434 ps
CPU time 32.58 seconds
Started May 04 03:46:52 PM PDT 24
Finished May 04 03:47:25 PM PDT 24
Peak memory 207904 kb
Host smart-0f25e3ad-f8a7-4b76-8fe6-e153ae9a21a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397239294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.397239294
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.63474147
Short name T211
Test name
Test status
Simulation time 220854630 ps
CPU time 7.38 seconds
Started May 04 03:46:58 PM PDT 24
Finished May 04 03:47:06 PM PDT 24
Peak memory 219996 kb
Host smart-d45cc260-07c5-49ff-8cf9-145922498887
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63474147 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.63474147
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2070158005
Short name T942
Test name
Test status
Simulation time 2189897287 ps
CPU time 48.89 seconds
Started May 04 03:46:54 PM PDT 24
Finished May 04 03:47:43 PM PDT 24
Peak memory 219972 kb
Host smart-18cc824b-c10e-4b61-9aef-e06b1fc079ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070158005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2070158005
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.690319461
Short name T610
Test name
Test status
Simulation time 84337434 ps
CPU time 1.6 seconds
Started May 04 03:46:59 PM PDT 24
Finished May 04 03:47:02 PM PDT 24
Peak memory 208424 kb
Host smart-04f8ad30-c9c6-4a62-803b-c8b5a7f5d0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690319461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.690319461
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.465547524
Short name T584
Test name
Test status
Simulation time 15130040 ps
CPU time 0.82 seconds
Started May 04 03:47:09 PM PDT 24
Finished May 04 03:47:11 PM PDT 24
Peak memory 205900 kb
Host smart-40b0db31-58c9-4843-87a1-2f91b2da3c7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465547524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.465547524
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3756350177
Short name T267
Test name
Test status
Simulation time 59612361 ps
CPU time 4.4 seconds
Started May 04 03:47:00 PM PDT 24
Finished May 04 03:47:05 PM PDT 24
Peak memory 214836 kb
Host smart-11b01a9c-c323-4d8f-b7bd-e37fa60653c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3756350177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3756350177
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2598746619
Short name T733
Test name
Test status
Simulation time 137772489 ps
CPU time 4.85 seconds
Started May 04 03:47:00 PM PDT 24
Finished May 04 03:47:06 PM PDT 24
Peak memory 209656 kb
Host smart-36ef9235-8491-49e0-b0ac-2348b2ecd619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598746619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2598746619
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2183146845
Short name T956
Test name
Test status
Simulation time 458987096 ps
CPU time 10.4 seconds
Started May 04 03:46:59 PM PDT 24
Finished May 04 03:47:10 PM PDT 24
Peak memory 209148 kb
Host smart-0a3af059-088e-494e-a8df-09264fbb8646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183146845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2183146845
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2909014179
Short name T824
Test name
Test status
Simulation time 571766768 ps
CPU time 4.57 seconds
Started May 04 03:46:59 PM PDT 24
Finished May 04 03:47:05 PM PDT 24
Peak memory 209632 kb
Host smart-5bf61006-c24a-408a-a087-0842454cc02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909014179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2909014179
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3267713773
Short name T358
Test name
Test status
Simulation time 377975969 ps
CPU time 8.85 seconds
Started May 04 03:46:58 PM PDT 24
Finished May 04 03:47:07 PM PDT 24
Peak memory 214320 kb
Host smart-1ca7cfd3-8b6a-42a9-bc66-a663da962b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267713773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3267713773
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3152428314
Short name T716
Test name
Test status
Simulation time 5930817233 ps
CPU time 15.93 seconds
Started May 04 03:46:57 PM PDT 24
Finished May 04 03:47:14 PM PDT 24
Peak memory 208472 kb
Host smart-f7e82db7-a4d8-4eab-9f95-ae05b1f6baa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152428314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3152428314
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.995618354
Short name T574
Test name
Test status
Simulation time 219751761 ps
CPU time 8 seconds
Started May 04 03:46:59 PM PDT 24
Finished May 04 03:47:08 PM PDT 24
Peak memory 208072 kb
Host smart-b633edeb-bece-4851-9823-a16260d9909a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995618354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.995618354
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2127416511
Short name T641
Test name
Test status
Simulation time 4441985535 ps
CPU time 85.98 seconds
Started May 04 03:46:59 PM PDT 24
Finished May 04 03:48:25 PM PDT 24
Peak memory 208556 kb
Host smart-f953834e-ac86-4dab-8626-7cf6156e068b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127416511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2127416511
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3367938946
Short name T920
Test name
Test status
Simulation time 184110296 ps
CPU time 2.57 seconds
Started May 04 03:46:58 PM PDT 24
Finished May 04 03:47:02 PM PDT 24
Peak memory 208472 kb
Host smart-dea3e786-54bb-4637-bd6d-a90dc6129222
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367938946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3367938946
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.171063673
Short name T830
Test name
Test status
Simulation time 265310283 ps
CPU time 2.21 seconds
Started May 04 03:47:06 PM PDT 24
Finished May 04 03:47:08 PM PDT 24
Peak memory 215952 kb
Host smart-9ac9d40d-4e36-46e8-bf9b-828e6ff0e7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171063673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.171063673
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2413985892
Short name T1024
Test name
Test status
Simulation time 350100598 ps
CPU time 2.12 seconds
Started May 04 03:47:00 PM PDT 24
Finished May 04 03:47:03 PM PDT 24
Peak memory 208372 kb
Host smart-ed2aaea9-a3b1-469a-808f-5de6e3acae49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413985892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2413985892
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1932494404
Short name T1062
Test name
Test status
Simulation time 16671079278 ps
CPU time 112.3 seconds
Started May 04 03:47:08 PM PDT 24
Finished May 04 03:49:00 PM PDT 24
Peak memory 220924 kb
Host smart-b66993d4-291c-47ee-9b2d-2943bab15b37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932494404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1932494404
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3256185150
Short name T300
Test name
Test status
Simulation time 605085425 ps
CPU time 5.14 seconds
Started May 04 03:46:59 PM PDT 24
Finished May 04 03:47:05 PM PDT 24
Peak memory 222500 kb
Host smart-33ebb646-b688-4dfb-8620-47cecebb904e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256185150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3256185150
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2833916048
Short name T687
Test name
Test status
Simulation time 163690444 ps
CPU time 3.46 seconds
Started May 04 03:47:07 PM PDT 24
Finished May 04 03:47:11 PM PDT 24
Peak memory 210488 kb
Host smart-c8c03c54-324b-48d1-a065-257d72734bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833916048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2833916048
Directory /workspace/9.keymgr_sync_async_fault_cross/latest