SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
invalid_hw_input_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[OtpRootKeyInvalid] | 1048 | 1 | T23 | 20 | T119 | 1 | T25 | 40 | ||||
auto[OtpRootKeyValidLow] | 181 | 1 | T23 | 7 | T25 | 7 | T26 | 7 | ||||
auto[LcStateInvalid] | 72 | 1 | T105 | 12 | T342 | 48 | T405 | 12 | ||||
auto[OtpDevIdInvalid] | 80 | 1 | T405 | 24 | T406 | 12 | T279 | 8 | ||||
auto[RomDigestInvalid] | 144 | 1 | T24 | 24 | T103 | 36 | T99 | 60 | ||||
auto[RomDigestValidLow] | 24 | 1 | T105 | 12 | T373 | 12 | - | - | ||||
auto[FlashCreatorSeedInvalid] | 56 | 1 | T405 | 12 | T103 | 24 | T407 | 8 | ||||
auto[FlashOwnerSeedInvalid] | 96 | 1 | T22 | 24 | T98 | 36 | T99 | 12 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |