Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
69.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	18	31	63.27

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	17	18	51.43	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	73	1			T43	1		T44	1		T6	3
auto[OpGenId]	13	1			T222	2		T225	1		T227	1
auto[OpGenSwOut]	33	1			T29	1		T109	1		T33	1
auto[OpGenHwOut]	21	1			T119	1		T6	1		T7	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1915	1			T119	2		T109	4		T110	3
auto[StInit]	140	1			T2	1		T43	1		T38	1
auto[StCreatorRootKey]	58	1			T15	1		T29	1		T119	1
auto[StOwnerIntKey]	42	1			T37	1		T53	1		T6	1
auto[StOwnerKey]	27	1			T4	1		T5	1		T9	1
auto[StDisabled]	313	1			T6	2		T30	1		T7	10
auto[StInvalid]	46	1			T36	1		T106	1		T92	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3477

1

T1

1

T2

2

T3

1

auto[1]

140

1

T29

1

T43

1

T44

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1904	1			T119	2		T109	4		T110	3
auto[StReset]	auto[1]	11	1			T47	1		T86	1		T228	1
auto[StInit]	auto[0]	63	1			T2	1		T38	1		T119	1
auto[StInit]	auto[1]	77	1			T43	1		T44	1		T119	1
auto[StCreatorRootKey]	auto[0]	33	1			T15	1		T119	1		T50	1
auto[StCreatorRootKey]	auto[1]	25	1			T29	1		T6	1		T110	1
auto[StOwnerIntKey]	auto[0]	29	1			T37	1		T53	1		T19	1
auto[StOwnerIntKey]	auto[1]	13	1			T6	1		T54	1		T86	2
auto[StOwnerKey]	auto[0]	22	1			T4	1		T5	1		T9	1
auto[StOwnerKey]	auto[1]	5	1			T6	1		T34	1		T71	1
auto[StDisabled]	auto[0]	304	1			T6	1		T30	1		T7	10
auto[StDisabled]	auto[1]	9	1			T6	1		T61	1		T62	1
auto[StInvalid]	auto[0]	46	1			T36	1		T106	1		T92	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	17	18	51.43	17

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]]	[auto[OpGenId]]	--	--	3
[auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	3

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	11	1			T47	1		T86	1		T228	1
auto[StInit]	auto[OpAdvance]	35	1			T43	1		T44	1		T110	1
auto[StInit]	auto[OpGenId]	11	1			T222	2		T225	1		T227	1
auto[StInit]	auto[OpGenSwOut]	19	1			T109	1		T33	1		T229	1
auto[StInit]	auto[OpGenHwOut]	12	1			T119	1		T81	1		T227	1
auto[StCreatorRootKey]	auto[OpAdvance]	12	1			T6	1		T110	1		T7	1
auto[StCreatorRootKey]	auto[OpGenId]	2	1			T230	1		T160	1		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T29	1		T231	1		T86	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	4	1			T7	1		T45	1		T232	1
auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T6	1		T54	1		T86	2
auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T161	1		T233	1		T234	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	2	1			T235	1		T236	1		-	-
auto[StOwnerKey]	auto[OpAdvance]	2	1			T6	1		T71	1		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	1	1			T237	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T34	1		T238	1		-	-
auto[StDisabled]	auto[OpAdvance]	5	1			T62	1		T227	1		T239	1
auto[StDisabled]	auto[OpGenSwOut]	3	1			T61	1		T240	1		T241	1
auto[StDisabled]	auto[OpGenHwOut]	1	1			T6	1		-	-		-	-