Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg
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Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
79.79 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv


Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 51 0 51 100.00
Crosses 330 77 253 76.67


Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
aes_sl_avail 2 0 2 100.00 100 1 1 2
aes_sl_avail_cp 2 0 2 100.00 100 1 1 2
kmac_sl_avail 2 0 2 100.00 100 1 1 2
kmac_sl_avail_cp 2 0 2 100.00 100 1 1 2
op 5 0 5 100.00 100 1 1 0
op_cp 5 0 5 100.00 100 1 1 0
otbn_sl_avail 2 0 2 100.00 100 1 1 2
otbn_sl_avail_cp 2 0 2 100.00 100 1 1 2
regwen_cp 2 0 2 100.00 100 1 1 2
sideload_clear 8 0 8 100.00 100 1 1 8
sideload_clear_cp 5 0 5 100.00 100 1 1 0
state 7 0 7 100.00 100 1 1 0
state_cp 7 0 7 100.00 100 1 1 0


Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg
CROSS   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   PRINT MISSING   COMMENT   
sideload_clear_x_state_op_cross 280 58 222 79.29 100 1 1 0
sideload_clear_x_sl_avail_cross 40 19 21 52.50 100 1 1 0
sideload_clear_x_regwen_cross 10 0 10 100.00 100 1 1 0


Summary for Variable aes_sl_avail

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for aes_sl_avail

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 4304 1 T5 1 T15 1 T16 3
auto[1] 475 1 T5 1 T16 1 T17 1


Summary for Variable aes_sl_avail_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for aes_sl_avail_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 4304 1 T5 1 T15 1 T16 3
auto[1] 475 1 T5 1 T16 1 T17 1


Summary for Variable kmac_sl_avail

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for kmac_sl_avail

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 4226 1 T5 2 T15 1 T16 4
auto[1] 553 1 T17 2 T27 1 T28 1


Summary for Variable kmac_sl_avail_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for kmac_sl_avail_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 4226 1 T5 2 T15 1 T16 4
auto[1] 553 1 T17 2 T27 1 T28 1


Summary for Variable op

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for op

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[OpAdvance] 370 1 T17 1 T28 2 T211 1
auto[OpGenId] 964 1 T9 1 T17 1 T27 2
auto[OpGenSwOut] 1011 1 T16 1 T17 2 T27 2
auto[OpGenHwOut] 2372 1 T5 2 T15 1 T16 2
auto[OpDisable] 62 1 T16 1 T7 2 T64 1


Summary for Variable op_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 5 0 5 100.00


Automatically Generated Bins for op_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[OpAdvance] 370 1 T17 1 T28 2 T211 1
auto[OpGenId] 964 1 T9 1 T17 1 T27 2
auto[OpGenSwOut] 1011 1 T16 1 T17 2 T27 2
auto[OpGenHwOut] 2372 1 T5 2 T15 1 T16 2
auto[OpDisable] 62 1 T16 1 T7 2 T64 1


Summary for Variable otbn_sl_avail

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_sl_avail

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 4263 1 T5 2 T15 1 T16 1
auto[1] 516 1 T16 3 T18 4 T27 1


Summary for Variable otbn_sl_avail_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for otbn_sl_avail_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 4263 1 T5 2 T15 1 T16 1
auto[1] 516 1 T16 3 T18 4 T27 1


Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 4494 1 T5 2 T15 1 T16 4
auto[1] 285 1 T17 1 T137 2 T144 6


Summary for Variable sideload_clear

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 8 0 8 100.00


Automatically Generated Bins for sideload_clear

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 1632 1 T5 1 T15 1 T16 1
auto[1] 679 1 T16 1 T17 2 T18 3
auto[2] 621 1 T16 2 T18 2 T27 1
auto[3] 629 1 T17 1 T18 1 T23 2
auto[4] 311 1 T5 1 T18 1 T223 1
auto[5] 323 1 T9 1 T28 1 T223 1
auto[6] 285 1 T29 1 T211 1 T90 1
auto[7] 299 1 T18 1 T27 1 T28 1


Summary for Variable sideload_clear_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 5 0 5 100.00


User Defined Bins for sideload_clear_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
clear_all 1218 1 T5 1 T9 1 T18 2
clear_one[1] 679 1 T16 1 T17 2 T18 3
clear_one[2] 621 1 T16 2 T18 2 T27 1
clear_one[3] 629 1 T17 1 T18 1 T23 2
clear_none 1632 1 T5 1 T15 1 T16 1


Summary for Variable state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for state

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] 861 1 T16 1 T9 1 T18 4
auto[StInit] 690 1 T15 1 T9 1 T18 1
auto[StCreatorRootKey] 521 1 T5 1 T16 1 T9 1
auto[StOwnerIntKey] 460 1 T5 1 T18 1 T27 1
auto[StOwnerKey] 439 1 T17 2 T18 1 T28 1
auto[StDisabled] 1652 1 T16 2 T17 2 T18 4
auto[StInvalid] 156 1 T36 5 T106 4 T92 1


Summary for Variable state_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for state_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[StReset] 861 1 T16 1 T9 1 T18 4
auto[StInit] 690 1 T15 1 T9 1 T18 1
auto[StCreatorRootKey] 521 1 T5 1 T16 1 T9 1
auto[StOwnerIntKey] 460 1 T5 1 T18 1 T27 1
auto[StOwnerKey] 439 1 T17 2 T18 1 T28 1
auto[StDisabled] 1652 1 T16 2 T17 2 T18 4
auto[StInvalid] 156 1 T36 5 T106 4 T92 1


Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 280 58 222 79.29 58


Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins
sideload_clear   state   op   COUNT   AT LEAST   NUMBER   STATUS   
[auto[0] - auto[1]] [auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]] [auto[OpDisable]] -- -- 10
[auto[0] - auto[1]] [auto[StInvalid]] [auto[OpDisable]] -- -- 2
[auto[2]] [auto[StReset]] [auto[OpAdvance]] 0 1 1
[auto[2]] [auto[StReset]] [auto[OpDisable]] 0 1 1
[auto[2]] [auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]] [auto[OpDisable]] -- -- 4
[auto[2]] [auto[StInvalid]] [auto[OpAdvance]] 0 1 1
[auto[2]] [auto[StInvalid]] [auto[OpDisable]] 0 1 1
[auto[3]] [auto[StReset]] [auto[OpAdvance]] 0 1 1
[auto[3]] [auto[StReset]] [auto[OpDisable]] 0 1 1
[auto[3]] [auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]] [auto[OpDisable]] -- -- 4
[auto[3]] [auto[StInvalid]] [auto[OpDisable]] 0 1 1
[auto[4]] [auto[StReset]] [auto[OpAdvance]] 0 1 1
[auto[4]] [auto[StReset]] [auto[OpDisable]] 0 1 1
[auto[4]] [auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]] [auto[OpDisable]] -- -- 4
[auto[4]] [auto[StInvalid]] [auto[OpAdvance]] 0 1 1
[auto[4]] [auto[StInvalid]] [auto[OpGenHwOut] , auto[OpDisable]] -- -- 2
[auto[5] - auto[6]] [auto[StReset]] [auto[OpAdvance]] -- -- 2
[auto[5] - auto[6]] [auto[StReset]] [auto[OpDisable]] -- -- 2
[auto[5] - auto[6]] [auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]] [auto[OpDisable]] -- -- 8
[auto[5] - auto[6]] [auto[StInvalid]] [auto[OpDisable]] -- -- 2
[auto[7]] [auto[StReset]] [auto[OpAdvance]] 0 1 1
[auto[7]] [auto[StReset]] [auto[OpDisable]] 0 1 1
[auto[7]] [auto[StInit] , auto[StCreatorRootKey]] [auto[OpDisable]] -- -- 2
[auto[7]] [auto[StOwnerIntKey]] [auto[OpAdvance]] 0 1 1
[auto[7]] [auto[StOwnerIntKey]] [auto[OpDisable]] 0 1 1
[auto[7]] [auto[StOwnerKey]] [auto[OpDisable]] 0 1 1
[auto[7]] [auto[StInvalid]] [auto[OpDisable]] 0 1 1


Covered bins
sideload_clear   state   op   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] auto[StReset] auto[OpAdvance] 1 1 T242 1 - - - -
auto[0] auto[StReset] auto[OpGenId] 110 1 T23 1 T211 1 T206 1
auto[0] auto[StReset] auto[OpGenSwOut] 145 1 T16 1 T27 1 T29 1
auto[0] auto[StReset] auto[OpGenHwOut] 225 1 T9 1 T18 2 T36 1
auto[0] auto[StInit] auto[OpAdvance] 33 1 T25 1 T205 1 T54 1
auto[0] auto[StInit] auto[OpGenId] 109 1 T28 1 T44 1 T135 1
auto[0] auto[StInit] auto[OpGenSwOut] 76 1 T110 1 T7 1 T33 1
auto[0] auto[StInit] auto[OpGenHwOut] 192 1 T15 1 T9 1 T89 1
auto[0] auto[StCreatorRootKey] auto[OpAdvance] 15 1 T90 1 T84 1 T71 1
auto[0] auto[StCreatorRootKey] auto[OpGenId] 45 1 T136 1 T7 1 T218 1
auto[0] auto[StCreatorRootKey] auto[OpGenSwOut] 50 1 T46 1 T30 1 T193 1
auto[0] auto[StCreatorRootKey] auto[OpGenHwOut] 71 1 T5 1 T91 1 T138 1
auto[0] auto[StOwnerIntKey] auto[OpAdvance] 9 1 T144 1 T243 1 T244 1
auto[0] auto[StOwnerIntKey] auto[OpGenId] 20 1 T212 1 T243 1 T245 1
auto[0] auto[StOwnerIntKey] auto[OpGenSwOut] 21 1 T7 1 T61 2 T81 1
auto[0] auto[StOwnerIntKey] auto[OpGenHwOut] 52 1 T18 1 T140 1 T246 1
auto[0] auto[StOwnerKey] auto[OpAdvance] 11 1 T247 1 T248 1 T249 1
auto[0] auto[StOwnerKey] auto[OpGenId] 15 1 T52 1 T250 2 T251 1
auto[0] auto[StOwnerKey] auto[OpGenSwOut] 27 1 T17 1 T6 1 T7 2
auto[0] auto[StOwnerKey] auto[OpGenHwOut] 50 1 T6 1 T61 1 T59 1
auto[0] auto[StDisabled] auto[OpAdvance] 21 1 T7 1 T205 1 T252 1
auto[0] auto[StDisabled] auto[OpGenId] 56 1 T206 1 T205 1 T61 1
auto[0] auto[StDisabled] auto[OpGenSwOut] 56 1 T7 2 T61 2 T52 1
auto[0] auto[StDisabled] auto[OpGenHwOut] 165 1 T18 1 T91 1 T140 2
auto[0] auto[StDisabled] auto[OpDisable] 12 1 T61 1 T45 1 T227 1
auto[0] auto[StInvalid] auto[OpAdvance] 3 1 T207 1 T253 1 T254 1
auto[0] auto[StInvalid] auto[OpGenId] 11 1 T36 1 T69 1 T220 2
auto[0] auto[StInvalid] auto[OpGenSwOut] 12 1 T36 1 T106 1 T51 1
auto[0] auto[StInvalid] auto[OpGenHwOut] 19 1 T92 1 T94 1 T255 1
auto[1] auto[StReset] auto[OpAdvance] 1 1 T256 1 - - - -
auto[1] auto[StReset] auto[OpGenId] 17 1 T206 1 T67 1 T257 1
auto[1] auto[StReset] auto[OpGenSwOut] 13 1 T64 1 T61 1 T81 1
auto[1] auto[StReset] auto[OpGenHwOut] 38 1 T18 1 T138 1 T221 1
auto[1] auto[StInit] auto[OpAdvance] 12 1 T24 1 T26 1 T93 1
auto[1] auto[StInit] auto[OpGenId] 13 1 T27 1 T61 1 T82 1
auto[1] auto[StInit] auto[OpGenSwOut] 9 1 T23 2 T258 1 T61 1
auto[1] auto[StInit] auto[OpGenHwOut] 19 1 T259 1 T105 1 T260 1
auto[1] auto[StCreatorRootKey] auto[OpAdvance] 1 1 T261 1 - - - -
auto[1] auto[StCreatorRootKey] auto[OpGenId] 11 1 T54 1 T262 1 T225 1
auto[1] auto[StCreatorRootKey] auto[OpGenSwOut] 16 1 T252 1 T263 1 T264 1
auto[1] auto[StCreatorRootKey] auto[OpGenHwOut] 49 1 T18 1 T140 1 T64 1
auto[1] auto[StOwnerIntKey] auto[OpAdvance] 10 1 T214 1 T265 1 T266 1
auto[1] auto[StOwnerIntKey] auto[OpGenId] 18 1 T267 1 T52 1 T86 1
auto[1] auto[StOwnerIntKey] auto[OpGenSwOut] 14 1 T135 1 T52 1 T232 1
auto[1] auto[StOwnerIntKey] auto[OpGenHwOut] 46 1 T138 1 T7 1 T268 1
auto[1] auto[StOwnerKey] auto[OpAdvance] 12 1 T17 1 T208 1 T269 1
auto[1] auto[StOwnerKey] auto[OpGenId] 18 1 T135 1 T7 2 T144 1
auto[1] auto[StOwnerKey] auto[OpGenSwOut] 16 1 T144 1 T270 1 T271 1
auto[1] auto[StOwnerKey] auto[OpGenHwOut] 41 1 T268 1 T224 1 T190 1
auto[1] auto[StDisabled] auto[OpAdvance] 26 1 T89 1 T61 1 T272 1
auto[1] auto[StDisabled] auto[OpGenId] 39 1 T212 1 T61 1 T67 1
auto[1] auto[StDisabled] auto[OpGenSwOut] 52 1 T17 1 T46 1 T52 1
auto[1] auto[StDisabled] auto[OpGenHwOut] 148 1 T18 1 T27 1 T89 1
auto[1] auto[StDisabled] auto[OpDisable] 14 1 T16 1 T7 1 T66 1
auto[1] auto[StInvalid] auto[OpAdvance] 8 1 T106 1 T273 1 T274 1
auto[1] auto[StInvalid] auto[OpGenId] 7 1 T220 1 T275 1 T95 1
auto[1] auto[StInvalid] auto[OpGenSwOut] 8 1 T106 1 T69 1 T94 1
auto[1] auto[StInvalid] auto[OpGenHwOut] 3 1 T276 1 T273 1 T277 1
auto[2] auto[StReset] auto[OpGenId] 12 1 T67 1 T71 1 T227 1
auto[2] auto[StReset] auto[OpGenSwOut] 15 1 T81 1 T278 1 T279 1
auto[2] auto[StReset] auto[OpGenHwOut] 37 1 T18 1 T226 1 T246 1
auto[2] auto[StInit] auto[OpAdvance] 5 1 T93 1 T280 1 T253 1
auto[2] auto[StInit] auto[OpGenId] 14 1 T23 1 T24 1 T46 1
auto[2] auto[StInit] auto[OpGenSwOut] 14 1 T59 1 T105 1 T281 1
auto[2] auto[StInit] auto[OpGenHwOut] 31 1 T18 1 T24 1 T191 1
auto[2] auto[StCreatorRootKey] auto[OpAdvance] 3 1 T266 1 T282 1 T283 1
auto[2] auto[StCreatorRootKey] auto[OpGenId] 10 1 T52 1 T71 1 T284 1
auto[2] auto[StCreatorRootKey] auto[OpGenSwOut] 14 1 T206 1 T62 1 T285 1
auto[2] auto[StCreatorRootKey] auto[OpGenHwOut] 38 1 T16 1 T135 1 T286 1
auto[2] auto[StOwnerIntKey] auto[OpAdvance] 6 1 T287 1 T288 1 T289 1
auto[2] auto[StOwnerIntKey] auto[OpGenId] 12 1 T27 1 T239 1 T278 1
auto[2] auto[StOwnerIntKey] auto[OpGenSwOut] 15 1 T72 1 T290 1 T291 1
auto[2] auto[StOwnerIntKey] auto[OpGenHwOut] 39 1 T224 1 T190 1 T191 1
auto[2] auto[StOwnerKey] auto[OpAdvance] 7 1 T28 1 T288 1 T292 1
auto[2] auto[StOwnerKey] auto[OpGenId] 12 1 T61 1 T71 1 T288 1
auto[2] auto[StOwnerKey] auto[OpGenSwOut] 10 1 T218 1 T287 1 T225 1
auto[2] auto[StOwnerKey] auto[OpGenHwOut] 28 1 T91 1 T293 1 T294 1
auto[2] auto[StDisabled] auto[OpAdvance] 22 1 T89 1 T61 1 T288 1
auto[2] auto[StDisabled] auto[OpGenId] 50 1 T28 1 T136 1 T7 1
auto[2] auto[StDisabled] auto[OpGenSwOut] 44 1 T137 1 T61 2 T252 1
auto[2] auto[StDisabled] auto[OpGenHwOut] 158 1 T16 1 T91 1 T140 1
auto[2] auto[StDisabled] auto[OpDisable] 3 1 T261 1 T295 1 T49 1
auto[2] auto[StInvalid] auto[OpGenId] 7 1 T36 1 T296 1 T297 1
auto[2] auto[StInvalid] auto[OpGenSwOut] 10 1 T69 1 T216 1 T275 1
auto[2] auto[StInvalid] auto[OpGenHwOut] 5 1 T69 1 T298 1 T299 1
auto[3] auto[StReset] auto[OpGenId] 22 1 T23 1 T252 1 T300 1
auto[3] auto[StReset] auto[OpGenSwOut] 24 1 T24 1 T206 1 T61 1
auto[3] auto[StReset] auto[OpGenHwOut] 42 1 T138 1 T190 1 T191 1
auto[3] auto[StInit] auto[OpAdvance] 7 1 T19 1 T26 1 T301 1
auto[3] auto[StInit] auto[OpGenId] 14 1 T139 1 T7 1 T302 1
auto[3] auto[StInit] auto[OpGenSwOut] 14 1 T104 1 T85 1 T303 1
auto[3] auto[StInit] auto[OpGenHwOut] 21 1 T23 1 T221 1 T286 1
auto[3] auto[StCreatorRootKey] auto[OpAdvance] 9 1 T159 2 T75 1 T304 1
auto[3] auto[StCreatorRootKey] auto[OpGenId] 9 1 T225 1 T280 1 T305 1
auto[3] auto[StCreatorRootKey] auto[OpGenSwOut] 13 1 T7 1 T19 1 T302 2
auto[3] auto[StCreatorRootKey] auto[OpGenHwOut] 32 1 T268 1 T205 1 T189 1
auto[3] auto[StOwnerIntKey] auto[OpAdvance] 7 1 T89 1 T284 1 T40 1
auto[3] auto[StOwnerIntKey] auto[OpGenId] 11 1 T205 1 T61 1 T306 1
auto[3] auto[StOwnerIntKey] auto[OpGenSwOut] 13 1 T263 1 T303 1 T278 1
auto[3] auto[StOwnerIntKey] auto[OpGenHwOut] 34 1 T223 1 T7 1 T307 1
auto[3] auto[StOwnerKey] auto[OpAdvance] 4 1 T308 1 T309 1 T310 1
auto[3] auto[StOwnerKey] auto[OpGenId] 11 1 T159 3 T302 1 T261 1
auto[3] auto[StOwnerKey] auto[OpGenSwOut] 15 1 T289 1 T239 1 T291 1
auto[3] auto[StOwnerKey] auto[OpGenHwOut] 36 1 T18 1 T140 1 T286 1
auto[3] auto[StDisabled] auto[OpAdvance] 23 1 T137 1 T302 1 T311 1
auto[3] auto[StDisabled] auto[OpGenId] 48 1 T17 1 T137 2 T7 1
auto[3] auto[StDisabled] auto[OpGenSwOut] 45 1 T28 1 T6 1 T193 1
auto[3] auto[StDisabled] auto[OpGenHwOut] 141 1 T223 1 T136 1 T138 1
auto[3] auto[StDisabled] auto[OpDisable] 11 1 T7 1 T64 1 T61 1
auto[3] auto[StInvalid] auto[OpAdvance] 3 1 T277 1 T312 1 T313 1
auto[3] auto[StInvalid] auto[OpGenId] 7 1 T36 1 T95 1 T279 1
auto[3] auto[StInvalid] auto[OpGenSwOut] 3 1 T216 1 T255 1 T314 1
auto[3] auto[StInvalid] auto[OpGenHwOut] 10 1 T51 1 T315 1 T279 1
auto[4] auto[StReset] auto[OpGenId] 16 1 T7 1 T25 1 T104 1
auto[4] auto[StReset] auto[OpGenSwOut] 8 1 T64 1 T67 1 T216 1
auto[4] auto[StReset] auto[OpGenHwOut] 22 1 T246 1 T316 1 T285 1
auto[4] auto[StInit] auto[OpAdvance] 1 1 T317 1 - - - -
auto[4] auto[StInit] auto[OpGenId] 4 1 T72 1 T318 1 T49 1
auto[4] auto[StInit] auto[OpGenSwOut] 9 1 T7 1 T26 1 T287 1
auto[4] auto[StInit] auto[OpGenHwOut] 10 1 T71 2 T319 1 T239 1
auto[4] auto[StCreatorRootKey] auto[OpAdvance] 5 1 T320 1 T321 1 T322 1
auto[4] auto[StCreatorRootKey] auto[OpGenId] 3 1 T61 1 T323 1 T324 1
auto[4] auto[StCreatorRootKey] auto[OpGenSwOut] 5 1 T325 1 T326 1 T327 1
auto[4] auto[StCreatorRootKey] auto[OpGenHwOut] 14 1 T223 1 T221 1 T226 1
auto[4] auto[StOwnerIntKey] auto[OpAdvance] 3 1 T54 1 T81 1 T322 1
auto[4] auto[StOwnerIntKey] auto[OpGenId] 3 1 T137 1 T61 1 T328 1
auto[4] auto[StOwnerIntKey] auto[OpGenSwOut] 8 1 T225 1 T329 1 T77 1
auto[4] auto[StOwnerIntKey] auto[OpGenHwOut] 16 1 T5 1 T226 1 T260 1
auto[4] auto[StOwnerKey] auto[OpAdvance] 4 1 T278 1 T330 1 T331 1
auto[4] auto[StOwnerKey] auto[OpGenId] 5 1 T300 1 T332 1 T278 1
auto[4] auto[StOwnerKey] auto[OpGenSwOut] 5 1 T214 1 T333 1 T334 1
auto[4] auto[StOwnerKey] auto[OpGenHwOut] 14 1 T221 1 T335 1 T319 1
auto[4] auto[StDisabled] auto[OpAdvance] 10 1 T144 1 T159 1 T72 1
auto[4] auto[StDisabled] auto[OpGenId] 26 1 T159 1 T336 1 T302 1
auto[4] auto[StDisabled] auto[OpGenSwOut] 34 1 T7 1 T218 1 T144 1
auto[4] auto[StDisabled] auto[OpGenHwOut] 68 1 T18 1 T205 1 T246 1
auto[4] auto[StDisabled] auto[OpDisable] 12 1 T72 1 T337 1 T278 1
auto[4] auto[StInvalid] auto[OpGenId] 3 1 T36 1 T338 2 - -
auto[4] auto[StInvalid] auto[OpGenSwOut] 3 1 T315 1 T273 1 T297 1
auto[5] auto[StReset] auto[OpGenId] 12 1 T213 1 T287 1 T225 1
auto[5] auto[StReset] auto[OpGenSwOut] 11 1 T25 1 T225 1 T239 1
auto[5] auto[StReset] auto[OpGenHwOut] 24 1 T246 1 T259 1 T339 1
auto[5] auto[StInit] auto[OpAdvance] 5 1 T320 1 T340 1 T341 1
auto[5] auto[StInit] auto[OpGenId] 4 1 T26 1 T81 1 T342 1
auto[5] auto[StInit] auto[OpGenSwOut] 5 1 T261 1 T343 1 T344 1
auto[5] auto[StInit] auto[OpGenHwOut] 13 1 T25 1 T316 1 T345 1
auto[5] auto[StCreatorRootKey] auto[OpAdvance] 5 1 T28 1 T284 1 T346 1
auto[5] auto[StCreatorRootKey] auto[OpGenId] 13 1 T9 1 T71 1 T347 1
auto[5] auto[StCreatorRootKey] auto[OpGenSwOut] 4 1 T34 1 T348 1 T349 1
auto[5] auto[StCreatorRootKey] auto[OpGenHwOut] 23 1 T350 1 T335 1 T351 1
auto[5] auto[StOwnerIntKey] auto[OpAdvance] 3 1 T245 1 T352 1 T353 1
auto[5] auto[StOwnerIntKey] auto[OpGenId] 5 1 T337 1 T77 1 T354 1
auto[5] auto[StOwnerIntKey] auto[OpGenSwOut] 7 1 T355 1 T72 1 T347 1
auto[5] auto[StOwnerIntKey] auto[OpGenHwOut] 18 1 T356 1 T319 1 T357 1
auto[5] auto[StOwnerKey] auto[OpAdvance] 5 1 T250 1 T344 1 T242 1
auto[5] auto[StOwnerKey] auto[OpGenId] 3 1 T358 1 T318 1 T359 1
auto[5] auto[StOwnerKey] auto[OpGenSwOut] 9 1 T61 1 T360 1 T361 3
auto[5] auto[StOwnerKey] auto[OpGenHwOut] 16 1 T362 1 T265 1 T363 1
auto[5] auto[StDisabled] auto[OpAdvance] 12 1 T144 1 T245 1 T364 1
auto[5] auto[StDisabled] auto[OpGenId] 23 1 T7 2 T250 1 T81 1
auto[5] auto[StDisabled] auto[OpGenSwOut] 23 1 T206 1 T212 1 T205 1
auto[5] auto[StDisabled] auto[OpGenHwOut] 69 1 T223 1 T140 1 T206 1
auto[5] auto[StDisabled] auto[OpDisable] 1 1 T365 1 - - - -
auto[5] auto[StInvalid] auto[OpAdvance] 2 1 T366 1 T299 1 - -
auto[5] auto[StInvalid] auto[OpGenId] 2 1 T366 1 T367 1 - -
auto[5] auto[StInvalid] auto[OpGenSwOut] 3 1 T275 1 T368 1 T312 1
auto[5] auto[StInvalid] auto[OpGenHwOut] 3 1 T253 1 T369 1 T370 1
auto[6] auto[StReset] auto[OpGenId] 7 1 T29 1 T371 1 T340 1
auto[6] auto[StReset] auto[OpGenSwOut] 6 1 T206 1 T253 1 T372 1
auto[6] auto[StReset] auto[OpGenHwOut] 17 1 T221 1 T286 2 T345 1
auto[6] auto[StInit] auto[OpAdvance] 6 1 T373 1 T374 1 T344 1
auto[6] auto[StInit] auto[OpGenId] 7 1 T85 1 T278 1 T333 1
auto[6] auto[StInit] auto[OpGenSwOut] 6 1 T26 1 T85 1 T375 1
auto[6] auto[StInit] auto[OpGenHwOut] 17 1 T24 1 T25 1 T246 1
auto[6] auto[StCreatorRootKey] auto[OpAdvance] 5 1 T7 1 T267 1 T376 1
auto[6] auto[StCreatorRootKey] auto[OpGenId] 7 1 T225 1 T377 1 T60 1
auto[6] auto[StCreatorRootKey] auto[OpGenSwOut] 6 1 T378 1 T77 1 T318 1
auto[6] auto[StCreatorRootKey] auto[OpGenHwOut] 12 1 T293 1 T339 1 T225 1
auto[6] auto[StOwnerIntKey] auto[OpAdvance] 7 1 T211 1 T379 1 T380 1
auto[6] auto[StOwnerIntKey] auto[OpGenId] 7 1 T218 1 T71 1 T381 1
auto[6] auto[StOwnerIntKey] auto[OpGenSwOut] 3 1 T382 1 T49 1 T383 1
auto[6] auto[StOwnerIntKey] auto[OpGenHwOut] 19 1 T91 1 T221 1 T286 1
auto[6] auto[StOwnerKey] auto[OpAdvance] 3 1 T30 1 T384 2 - -
auto[6] auto[StOwnerKey] auto[OpGenId] 2 1 T321 1 T385 1 - -
auto[6] auto[StOwnerKey] auto[OpGenSwOut] 10 1 T239 1 T278 1 T321 1
auto[6] auto[StOwnerKey] auto[OpGenHwOut] 15 1 T223 1 T138 1 T386 1
auto[6] auto[StDisabled] auto[OpAdvance] 7 1 T7 1 T239 1 T96 1
auto[6] auto[StDisabled] auto[OpGenId] 22 1 T61 2 T71 1 T225 1
auto[6] auto[StDisabled] auto[OpGenSwOut] 22 1 T7 2 T387 1 T388 1
auto[6] auto[StDisabled] auto[OpGenHwOut] 58 1 T90 1 T190 1 T61 1
auto[6] auto[StDisabled] auto[OpDisable] 3 1 T257 1 T225 1 T344 1
auto[6] auto[StInvalid] auto[OpAdvance] 3 1 T273 1 T389 1 T390 1
auto[6] auto[StInvalid] auto[OpGenId] 3 1 T276 1 T391 1 T392 1
auto[6] auto[StInvalid] auto[OpGenSwOut] 2 1 T216 1 T253 1 - -
auto[6] auto[StInvalid] auto[OpGenHwOut] 3 1 T106 1 T279 1 T274 1
auto[7] auto[StReset] auto[OpGenId] 7 1 T81 1 T393 1 T375 1
auto[7] auto[StReset] auto[OpGenSwOut] 12 1 T302 1 T104 1 T220 1
auto[7] auto[StReset] auto[OpGenHwOut] 17 1 T7 1 T192 1 T71 1
auto[7] auto[StInit] auto[OpAdvance] 2 1 T342 1 T373 1 - -
auto[7] auto[StInit] auto[OpGenId] 8 1 T61 1 T342 1 T394 1
auto[7] auto[StInit] auto[OpGenSwOut] 3 1 T161 1 T395 1 T234 1
auto[7] auto[StInit] auto[OpGenHwOut] 7 1 T226 1 T335 1 T337 1
auto[7] auto[StCreatorRootKey] auto[OpAdvance] 2 1 T396 1 T49 1 - -
auto[7] auto[StCreatorRootKey] auto[OpGenId] 3 1 T397 1 T385 1 T398 1
auto[7] auto[StCreatorRootKey] auto[OpGenSwOut] 10 1 T27 1 T211 1 T61 1
auto[7] auto[StCreatorRootKey] auto[OpGenHwOut] 18 1 T192 1 T307 1 T260 1
auto[7] auto[StOwnerIntKey] auto[OpGenId] 10 1 T28 1 T225 1 T361 1
auto[7] auto[StOwnerIntKey] auto[OpGenSwOut] 7 1 T52 1 T247 1 T96 1
auto[7] auto[StOwnerIntKey] auto[OpGenHwOut] 17 1 T192 1 T62 1 T399 1
auto[7] auto[StOwnerKey] auto[OpAdvance] 6 1 T225 1 T232 1 T337 1
auto[7] auto[StOwnerKey] auto[OpGenId] 5 1 T303 1 T400 1 T343 1
auto[7] auto[StOwnerKey] auto[OpGenSwOut] 7 1 T285 1 T311 1 T81 1
auto[7] auto[StOwnerKey] auto[OpGenHwOut] 17 1 T226 1 T246 1 T189 1
auto[7] auto[StDisabled] auto[OpAdvance] 13 1 T266 1 T343 3 T401 2
auto[7] auto[StDisabled] auto[OpGenId] 22 1 T263 1 T81 2 T71 1
auto[7] auto[StDisabled] auto[OpGenSwOut] 16 1 T213 1 T355 1 T257 1
auto[7] auto[StDisabled] auto[OpGenHwOut] 71 1 T18 1 T91 1 T223 1
auto[7] auto[StDisabled] auto[OpDisable] 6 1 T81 1 T74 1 T402 1
auto[7] auto[StInvalid] auto[OpAdvance] 2 1 T366 1 T368 1 - -
auto[7] auto[StInvalid] auto[OpGenId] 4 1 T216 1 T220 1 T275 1
auto[7] auto[StInvalid] auto[OpGenSwOut] 3 1 T315 1 T403 1 T370 1
auto[7] auto[StInvalid] auto[OpGenHwOut] 4 1 T216 1 T255 1 T404 1


Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 40 19 21 52.50 19


Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes
sideload_clear_cp   aes_sl_avail   kmac_sl_avail   otbn_sl_avail   COUNT   AT LEAST   NUMBER   STATUS   
[clear_all] [auto[0]] [auto[1]] * -- -- 2
[clear_all] [auto[1]] * * -- -- 4
[clear_one[1]] [auto[1]] * * -- -- 4
[clear_one[2]] * [auto[1]] * -- -- 4
[clear_one[3]] * * [auto[1]] -- -- 4


Uncovered bins
sideload_clear_cpaes_sl_availkmac_sl_availotbn_sl_availCOUNTAT LEASTNUMBERSTATUS
[clear_all] [auto[0]] [auto[0]] [auto[1]] 0 1 1


Covered bins
sideload_clear_cp   aes_sl_avail   kmac_sl_avail   otbn_sl_avail   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
clear_all auto[0] auto[0] auto[0] 1218 1 T5 1 T9 1 T18 2
clear_one[1] auto[0] auto[0] auto[0] 403 1 T17 1 T18 1 T27 1
clear_one[1] auto[0] auto[0] auto[1] 101 1 T16 1 T18 2 T91 1
clear_one[1] auto[0] auto[1] auto[0] 129 1 T17 1 T223 1 T46 1
clear_one[1] auto[0] auto[1] auto[1] 46 1 T27 1 T89 1 T208 1
clear_one[2] auto[0] auto[0] auto[0] 356 1 T18 2 T27 1 T23 1
clear_one[2] auto[0] auto[0] auto[1] 117 1 T16 1 T91 2 T206 1
clear_one[2] auto[1] auto[0] auto[0] 104 1 T140 1 T135 1 T137 1
clear_one[2] auto[1] auto[0] auto[1] 44 1 T16 1 T61 1 T252 1
clear_one[3] auto[0] auto[0] auto[0] 373 1 T18 1 T23 2 T89 1
clear_one[3] auto[0] auto[1] auto[0] 120 1 T17 1 T28 1 T223 2
clear_one[3] auto[1] auto[0] auto[0] 97 1 T140 1 T7 2 T286 2
clear_one[3] auto[1] auto[1] auto[0] 39 1 T136 1 T137 3 T61 1
clear_none auto[0] auto[0] auto[0] 1140 1 T15 1 T16 1 T9 2
clear_none auto[0] auto[0] auto[1] 128 1 T18 2 T91 2 T138 2
clear_none auto[0] auto[1] auto[0] 134 1 T46 1 T136 1 T221 2
clear_none auto[0] auto[1] auto[1] 39 1 T110 1 T7 1 T159 1
clear_none auto[1] auto[0] auto[0] 119 1 T5 1 T17 1 T140 3
clear_none auto[1] auto[0] auto[1] 26 1 T136 1 T61 1 T267 1
clear_none auto[1] auto[1] auto[0] 31 1 T206 2 T7 3 T61 3
clear_none auto[1] auto[1] auto[1] 15 1 T6 1 T59 1 T265 1


Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 10 0 10 100.00


Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins
sideload_clear_cp   regwen_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
clear_all auto[0] 1135 1 T5 1 T9 1 T18 2
clear_all auto[1] 83 1 T144 2 T159 4 T302 1
clear_one[1] auto[0] 632 1 T16 1 T17 1 T18 3
clear_one[1] auto[1] 47 1 T17 1 T144 1 T243 7
clear_one[2] auto[0] 583 1 T16 2 T18 2 T27 1
clear_one[2] auto[1] 38 1 T287 1 T288 5 T396 4
clear_one[3] auto[0] 579 1 T17 1 T18 1 T23 2
clear_one[3] auto[1] 50 1 T137 2 T159 4 T302 4
clear_none auto[0] 1565 1 T5 1 T15 1 T16 1
clear_none auto[1] 67 1 T144 3 T159 2 T311 2