Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10465

1

T1

3

T2

12

T4

6

auto[Attestation]

7227

1

T1

5

T2

1

T4

3

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2641	1			T2	3		T5	3		T16	1
auto[Aes]	3079	1			T2	3		T4	3		T5	4
auto[Kmac]	3159	1			T1	1		T2	1		T4	1
auto[Otbn]	3334	1			T1	1		T2	3		T4	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7160	1			T1	8		T2	1		T4	4
auto[OpGenId]	5479	1			T1	6		T2	3		T4	4
auto[OpGenSwOut]	5546	1			T1	2		T2	2		T4	4
auto[OpGenHwOut]	6667	1			T2	8		T4	1		T5	9
auto[OpDisable]	117	1			T16	1		T46	1		T7	3

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9316

1

T1

8

T2

1

T4

10

auto[OpDoneFail]

15653

1

T1

8

T2

13

T4

3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5642	1			T1	1		T2	13		T4	1
auto[StInit]	4099	1			T1	2		T2	1		T4	4
auto[StCreatorRootKey]	2844	1			T1	2		T4	4		T5	5
auto[StOwnerIntKey]	2434	1			T1	2		T4	2		T5	5
auto[StOwnerKey]	2076	1			T1	2		T4	2		T5	2
auto[StDisabled]	6805	1			T1	7		T16	2		T17	16
auto[StInvalid]	1069	1			T36	22		T106	29		T92	28

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	291	1			T16	1		T9	2		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	127	1			T9	1		T23	3		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	74	1			T6	1		T203	1		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	54	1			T37	1		T6	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T136	1		T7	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	193	1			T17	3		T137	1		T206	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	30	1			T106	3		T94	2		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	254	1			T23	1		T29	3		T44	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	139	1			T23	2		T7	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	62	1			T4	2		T27	2		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	68	1			T28	1		T209	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	50	1			T7	1		T61	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	201	1			T27	1		T89	1		T90	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	29	1			T36	1		T92	1		T94	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	290	1			T2	1		T23	1		T29	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	122	1			T23	1		T24	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	79	1			T89	1		T6	2		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	59	1			T135	1		T210	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	58	1			T4	1		T88	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	161	1			T27	1		T89	1		T90	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	33	1			T36	1		T106	3		T92	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	324	1			T2	1		T16	1		T9	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	108	1			T23	2		T44	1		T136	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	75	1			T9	1		T211	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	75	1			T28	1		T53	1		T137	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	58	1			T1	1		T7	1		T203	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	185	1			T27	1		T90	1		T7	5
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	46	1			T106	3		T92	1		T69	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	56	1			T7	4		T61	4		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	123	1			T23	1		T38	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	84	1			T30	1		T212	1		T205	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	69	1			T90	1		T6	3		T205	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	37	1			T213	1		T214	1		T215	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	197	1			T27	1		T28	3		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	36	1			T36	3		T69	1		T51	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	41	1			T7	5		T61	2		T216	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	95	1			T24	3		T7	2		T203	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	69	1			T37	1		T7	2		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	67	1			T5	1		T88	1		T90	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	45	1			T17	1		T6	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	156	1			T27	1		T137	2		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	38	1			T36	2		T106	1		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	54	1			T7	1		T61	4		T217	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	106	1			T1	1		T23	3		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	57	1			T211	1		T137	1		T159	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	50	1			T28	1		T53	1		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	64	1			T7	1		T218	1		T61	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	165	1			T17	1		T90	1		T137	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	33	1			T36	1		T106	1		T92	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T7	1		T61	4		T216	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	116	1			T4	1		T5	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	96	1			T139	1		T30	1		T206	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	53	1			T208	1		T61	1		T219	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	48	1			T7	1		T144	1		T61	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	190	1			T90	1		T136	1		T205	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	33	1			T106	4		T92	1		T207	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	236	1			T2	3		T23	2		T29	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	106	1			T211	1		T24	3		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	70	1			T17	1		T27	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	63	1			T17	1		T6	2		T61	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	48	1			T6	2		T144	1		T61	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	146	1			T27	1		T144	1		T159	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	34	1			T92	1		T94	1		T220	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	350	1			T2	2		T16	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	158	1			T15	1		T17	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	96	1			T5	1		T139	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	93	1			T4	1		T16	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	80	1			T27	1		T140	1		T137	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	255	1			T16	1		T27	1		T90	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	22	1			T106	1		T94	1		T216	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	397	1			T23	1		T24	1		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	113	1			T15	1		T9	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	102	1			T53	1		T7	1		T192	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	84	1			T5	1		T37	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	73	1			T211	1		T6	1		T221	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	257	1			T17	1		T27	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	35	1			T92	1		T94	1		T51	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	478	1			T2	2		T9	4		T18	10
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	119	1			T23	2		T119	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	99	1			T16	1		T91	1		T139	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	90	1			T91	1		T37	1		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	78	1			T18	1		T211	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	252	1			T18	1		T27	2		T89	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	40	1			T36	1		T106	1		T94	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	50	1			T7	1		T61	1		T216	5
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	113	1			T5	1		T23	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	72	1			T137	1		T6	1		T7	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	54	1			T5	2		T7	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T61	1		T62	1		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	148	1			T17	1		T7	2		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	22	1			T106	1		T94	2		T220	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	45	1			T61	3		T52	1		T222	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	125	1			T2	1		T90	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	97	1			T139	1		T140	1		T135	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	92	1			T16	1		T17	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	70	1			T5	2		T211	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	239	1			T140	4		T136	1		T137	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	43	1			T36	1		T106	1		T92	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	49	1			T61	2		T216	2		T81	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	141	1			T5	1		T9	1		T89	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	112	1			T223	1		T46	1		T139	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	109	1			T223	1		T221	1		T210	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	76	1			T223	1		T208	1		T224	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	248	1			T17	1		T223	2		T137	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	32	1			T36	1		T69	1		T94	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	46	1			T61	1		T216	1		T225	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	123	1			T5	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	109	1			T18	1		T138	1		T110	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	78	1			T18	1		T210	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	68	1			T211	1		T226	1		T189	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	248	1			T17	2		T18	3		T90	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	33	1			T106	1		T69	1		T51	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	174	1			T37	1		T6	2		T7	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	652	1			T16	1		T9	3		T17	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	165	1			T4	2		T27	2		T209	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	638	1			T27	1		T23	3		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	180	1			T4	1		T88	1		T89	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	622	1			T2	1		T27	1		T23	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	190	1			T1	1		T9	1		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	681	1			T2	1		T16	1		T9	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	175	1			T90	1		T6	3		T30	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	427	1			T27	1		T23	1		T28	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	166	1			T5	1		T17	1		T88	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	345	1			T27	1		T24	3		T36	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	159	1			T211	1		T53	1		T137	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	370	1			T1	1		T17	1		T23	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	181	1			T139	1		T30	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	421	1			T4	1		T5	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	166	1			T17	2		T27	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	537	1			T2	3		T27	1		T23	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	253	1			T4	1		T5	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	801	1			T2	2		T15	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	242	1			T5	1		T211	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	819	1			T15	1		T9	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	250	1			T16	1		T18	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	906	1			T2	2		T9	4		T18	11
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	164	1			T5	2		T137	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	346	1			T5	1		T17	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	248	1			T5	2		T16	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	463	1			T2	1		T90	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	280	1			T223	3		T46	1		T139	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	487	1			T5	1		T9	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	241	1			T18	2		T211	1		T138	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	464	1			T5	1		T17	3		T18	4