Unified Coverage Report :: Group Instance : attest_sw_binding

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	28671	1		T1	17	T2	14	T4	15
auto[134217728:268435455]	11	1		T250	1	T288	1	T396	2
auto[268435456:402653183]	8	1		T243	1	T401	1	T425	1
auto[402653184:536870911]	7	1		T311	2	T287	1	T426	2
auto[536870912:671088639]	6	1		T380	1	T427	1	T428	1
auto[671088640:805306367]	11	1		T302	1	T311	1	T243	1
auto[805306368:939524095]	4	1		T243	2	T256	1	T328	1
auto[939524096:1073741823]	8	1		T288	1	T429	1	T426	2
auto[1073741824:1207959551]	7	1		T302	1	T214	1	T288	1
auto[1207959552:1342177279]	6	1		T396	1	T430	1	T425	1
auto[1342177280:1476395007]	9	1		T302	1	T250	1	T243	1
auto[1476395008:1610612735]	10	1		T159	1	T311	1	T243	1
auto[1610612736:1744830463]	5	1		T144	1	T425	1	T428	1
auto[1744830464:1879048191]	10	1		T144	1	T159	1	T250	2
auto[1879048192:2013265919]	8	1		T159	1	T311	1	T244	1
auto[2013265920:2147483647]	7	1		T379	1	T425	1	T352	1
auto[2147483648:2281701375]	6	1		T159	1	T431	1	T322	1
auto[2281701376:2415919103]	9	1		T159	2	T308	1	T426	1
auto[2415919104:2550136831]	8	1		T302	1	T250	1	T284	1
auto[2550136832:2684354559]	9	1		T302	1	T243	1	T432	1
auto[2684354560:2818572287]	11	1		T144	1	T311	1	T243	1
auto[2818572288:2952790015]	6	1		T159	1	T250	1	T243	1
auto[2952790016:3087007743]	9	1		T159	1	T288	1	T266	1
auto[3087007744:3221225471]	11	1		T144	1	T311	1	T250	1
auto[3221225472:3355443199]	8	1		T17	1	T243	3	T426	2
auto[3355443200:3489660927]	8	1		T243	1	T430	1	T426	2
auto[3489660928:3623878655]	9	1		T144	1	T311	1	T243	1
auto[3623878656:3758096383]	10	1		T243	2	T429	1	T426	1
auto[3758096384:3892314111]	7	1		T144	1	T302	1	T245	1
auto[3892314112:4026531839]	4	1		T380	1	T431	2	T353	1
auto[4026531840:4160749567]	7	1		T250	1	T379	1	T425	1
auto[4160749568:4294967295]	7	1		T159	1	T250	1	T308	2

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	28658	1		T1	17	T2	14	T4	15
auto[0:134217727]	auto[1]	13	1		T266	1	T308	1	T401	1
auto[134217728:268435455]	auto[1]	11	1		T250	1	T288	1	T396	2
auto[268435456:402653183]	auto[1]	8	1		T243	1	T401	1	T425	1
auto[402653184:536870911]	auto[1]	7	1		T311	2	T287	1	T426	2
auto[536870912:671088639]	auto[1]	6	1		T380	1	T427	1	T428	1
auto[671088640:805306367]	auto[1]	11	1		T302	1	T311	1	T243	1
auto[805306368:939524095]	auto[1]	4	1		T243	2	T256	1	T328	1
auto[939524096:1073741823]	auto[1]	8	1		T288	1	T429	1	T426	2
auto[1073741824:1207959551]	auto[1]	7	1		T302	1	T214	1	T288	1
auto[1207959552:1342177279]	auto[1]	6	1		T396	1	T430	1	T425	1
auto[1342177280:1476395007]	auto[1]	9	1		T302	1	T250	1	T243	1
auto[1476395008:1610612735]	auto[1]	10	1		T159	1	T311	1	T243	1
auto[1610612736:1744830463]	auto[1]	5	1		T144	1	T425	1	T428	1
auto[1744830464:1879048191]	auto[1]	10	1		T144	1	T159	1	T250	2
auto[1879048192:2013265919]	auto[1]	8	1		T159	1	T311	1	T244	1
auto[2013265920:2147483647]	auto[1]	7	1		T379	1	T425	1	T352	1
auto[2147483648:2281701375]	auto[1]	6	1		T159	1	T431	1	T322	1
auto[2281701376:2415919103]	auto[1]	9	1		T159	2	T308	1	T426	1
auto[2415919104:2550136831]	auto[1]	8	1		T302	1	T250	1	T284	1
auto[2550136832:2684354559]	auto[1]	9	1		T302	1	T243	1	T432	1
auto[2684354560:2818572287]	auto[1]	11	1		T144	1	T311	1	T243	1
auto[2818572288:2952790015]	auto[1]	6	1		T159	1	T250	1	T243	1
auto[2952790016:3087007743]	auto[1]	9	1		T159	1	T288	1	T266	1
auto[3087007744:3221225471]	auto[1]	11	1		T144	1	T311	1	T250	1
auto[3221225472:3355443199]	auto[1]	8	1		T17	1	T243	3	T426	2
auto[3355443200:3489660927]	auto[1]	8	1		T243	1	T430	1	T426	2
auto[3489660928:3623878655]	auto[1]	9	1		T144	1	T311	1	T243	1
auto[3623878656:3758096383]	auto[1]	10	1		T243	2	T429	1	T426	1
auto[3758096384:3892314111]	auto[1]	7	1		T144	1	T302	1	T245	1
auto[3892314112:4026531839]	auto[1]	4	1		T380	1	T431	2	T353	1
auto[4026531840:4160749567]	auto[1]	7	1		T250	1	T379	1	T425	1
auto[4160749568:4294967295]	auto[1]	7	1		T159	1	T250	1	T308	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

auto[0]

1437

T15

T16

auto[1]

1550

T16

T17

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	90	1		T16	1	T23	1	T24	2
auto[134217728:268435455]	90	1		T89	1	T6	3	T106	1
auto[268435456:402653183]	104	1		T17	1	T36	2	T7	2
auto[402653184:536870911]	88	1		T17	1	T7	1	T64	1
auto[536870912:671088639]	102	1		T27	1	T23	1	T106	1
auto[671088640:805306367]	94	1		T16	1	T27	1	T6	1
auto[805306368:939524095]	92	1		T29	1	T7	5	T69	1
auto[939524096:1073741823]	105	1		T9	1	T6	1	T106	1
auto[1073741824:1207959551]	71	1		T16	1	T28	1	T46	1
auto[1207959552:1342177279]	106	1		T24	1	T46	1	T7	2
auto[1342177280:1476395007]	98	1		T16	1	T28	1	T36	1
auto[1476395008:1610612735]	94	1		T15	1	T36	1	T6	1
auto[1610612736:1744830463]	95	1		T23	1	T28	1	T89	1
auto[1744830464:1879048191]	85	1		T5	1	T23	1	T28	1
auto[1879048192:2013265919]	89	1		T211	1	T137	1	T6	1
auto[2013265920:2147483647]	92	1		T9	1	T27	1	T136	1
auto[2147483648:2281701375]	84	1		T6	1	T30	1	T7	4
auto[2281701376:2415919103]	102	1		T28	1	T89	1	T90	1
auto[2415919104:2550136831]	71	1		T27	1	T24	1	T36	1
auto[2550136832:2684354559]	93	1		T211	1	T44	1	T24	1
auto[2684354560:2818572287]	105	1		T9	1	T27	1	T90	1
auto[2818572288:2952790015]	93	1		T17	1	T44	1	T36	1
auto[2952790016:3087007743]	94	1		T27	1	T43	1	T36	1
auto[3087007744:3221225471]	92	1		T9	1	T206	1	T7	3
auto[3221225472:3355443199]	106	1		T27	1	T36	1	T6	1
auto[3355443200:3489660927]	89	1		T24	1	T46	1	T136	1
auto[3489660928:3623878655]	70	1		T44	1	T206	1	T110	1
auto[3623878656:3758096383]	104	1		T6	1	T7	2	T205	1
auto[3758096384:3892314111]	104	1		T23	2	T6	1	T25	1
auto[3892314112:4026531839]	100	1		T211	1	T206	1	T7	2
auto[4026531840:4160749567]	85	1		T7	2	T92	1	T128	1
auto[4160749568:4294967295]	100	1		T89	1	T6	1	T7	2

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	42	1		T16	1	T23	1	T24	2
auto[0:134217727]	auto[1]	48	1		T139	1	T206	1	T7	1
auto[134217728:268435455]	auto[0]	46	1		T6	1	T7	1	T433	1
auto[134217728:268435455]	auto[1]	44	1		T89	1	T6	2	T106	1
auto[268435456:402653183]	auto[0]	42	1		T36	2	T7	1	T258	1
auto[268435456:402653183]	auto[1]	62	1		T17	1	T7	1	T258	1
auto[402653184:536870911]	auto[0]	38	1		T7	1	T26	1	T59	1
auto[402653184:536870911]	auto[1]	50	1		T17	1	T64	1	T61	3
auto[536870912:671088639]	auto[0]	45	1		T23	1	T106	1	T61	1
auto[536870912:671088639]	auto[1]	57	1		T27	1	T7	1	T64	1
auto[671088640:805306367]	auto[0]	43	1		T7	1	T54	1	T159	1
auto[671088640:805306367]	auto[1]	51	1		T16	1	T27	1	T6	1
auto[805306368:939524095]	auto[0]	47	1		T7	4	T61	1	T26	1
auto[805306368:939524095]	auto[1]	45	1		T29	1	T7	1	T69	1
auto[939524096:1073741823]	auto[0]	55	1		T9	1	T106	1	T92	1
auto[939524096:1073741823]	auto[1]	50	1		T6	1	T25	1	T54	1
auto[1073741824:1207959551]	auto[0]	39	1		T16	1	T46	1	T137	1
auto[1073741824:1207959551]	auto[1]	32	1		T28	1	T210	1	T232	1
auto[1207959552:1342177279]	auto[0]	50	1		T24	1	T46	1	T54	1
auto[1207959552:1342177279]	auto[1]	56	1		T7	2	T144	1	T94	1
auto[1342177280:1476395007]	auto[0]	45	1		T16	1	T6	1	T7	1
auto[1342177280:1476395007]	auto[1]	53	1		T28	1	T36	1	T128	1
auto[1476395008:1610612735]	auto[0]	51	1		T15	1	T52	1	T217	1
auto[1476395008:1610612735]	auto[1]	43	1		T36	1	T6	1	T144	1
auto[1610612736:1744830463]	auto[0]	43	1		T23	1	T43	1	T106	1
auto[1610612736:1744830463]	auto[1]	52	1		T28	1	T89	1	T144	1
auto[1744830464:1879048191]	auto[0]	46	1		T5	1	T23	1	T28	1
auto[1744830464:1879048191]	auto[1]	39	1		T208	1	T105	1	T434	1
auto[1879048192:2013265919]	auto[0]	44	1		T211	1	T6	1	T159	1
auto[1879048192:2013265919]	auto[1]	45	1		T137	1	T110	1	T7	1
auto[2013265920:2147483647]	auto[0]	42	1		T25	1	T19	1	T8	1
auto[2013265920:2147483647]	auto[1]	50	1		T9	1	T27	1	T136	1
auto[2147483648:2281701375]	auto[0]	39	1		T6	1	T30	1	T7	2
auto[2147483648:2281701375]	auto[1]	45	1		T7	2	T92	1	T311	1
auto[2281701376:2415919103]	auto[0]	44	1		T28	1	T24	1	T6	1
auto[2281701376:2415919103]	auto[1]	58	1		T89	1	T90	1	T110	1
auto[2415919104:2550136831]	auto[0]	38	1		T24	1	T36	1	T52	1
auto[2415919104:2550136831]	auto[1]	33	1		T27	1	T7	1	T61	1
auto[2550136832:2684354559]	auto[0]	46	1		T211	1	T44	1	T24	1
auto[2550136832:2684354559]	auto[1]	47	1		T30	1	T205	1	T159	1
auto[2684354560:2818572287]	auto[0]	37	1		T9	1	T61	1	T93	1
auto[2684354560:2818572287]	auto[1]	68	1		T27	1	T90	1	T44	1
auto[2818572288:2952790015]	auto[0]	48	1		T44	1	T36	1	T6	1
auto[2818572288:2952790015]	auto[1]	45	1		T17	1	T61	1	T93	1
auto[2952790016:3087007743]	auto[0]	44	1		T36	1	T110	1	T258	1
auto[2952790016:3087007743]	auto[1]	50	1		T27	1	T43	1	T137	1
auto[3087007744:3221225471]	auto[0]	48	1		T9	1	T7	3	T205	1
auto[3087007744:3221225471]	auto[1]	44	1		T206	1	T208	1	T58	1
auto[3221225472:3355443199]	auto[0]	46	1		T27	1	T7	1	T61	3
auto[3221225472:3355443199]	auto[1]	60	1		T36	1	T6	1	T110	1
auto[3355443200:3489660927]	auto[0]	41	1		T205	1	T92	1	T26	1
auto[3355443200:3489660927]	auto[1]	48	1		T24	1	T46	1	T136	1
auto[3489660928:3623878655]	auto[0]	39	1		T92	1	T67	1	T267	1
auto[3489660928:3623878655]	auto[1]	31	1		T44	1	T206	1	T110	1
auto[3623878656:3758096383]	auto[0]	50	1		T205	1	T54	1	T144	1
auto[3623878656:3758096383]	auto[1]	54	1		T6	1	T7	2	T144	1
auto[3758096384:3892314111]	auto[0]	55	1		T23	2	T6	1	T25	1
auto[3758096384:3892314111]	auto[1]	49	1		T252	1	T336	1	T229	1
auto[3892314112:4026531839]	auto[0]	53	1		T206	1	T7	1	T67	1
auto[3892314112:4026531839]	auto[1]	47	1		T211	1	T7	1	T61	2
auto[4026531840:4160749567]	auto[0]	42	1		T7	2	T128	1	T270	1
auto[4026531840:4160749567]	auto[1]	43	1		T92	1	T62	1	T59	1
auto[4160749568:4294967295]	auto[0]	49	1		T435	1	T104	1	T231	1
auto[4160749568:4294967295]	auto[1]	51	1		T89	1	T6	1	T7	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

auto[0]

1416

T15

T16

auto[1]

1567

T16

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	99	1		T9	1	T23	1	T89	2
auto[134217728:268435455]	80	1		T7	1	T205	1	T67	1
auto[268435456:402653183]	108	1		T211	1	T136	1	T206	1
auto[402653184:536870911]	109	1		T29	1	T137	2	T7	1
auto[536870912:671088639]	83	1		T23	1	T106	1	T7	1
auto[671088640:805306367]	83	1		T9	1	T28	1	T89	1
auto[805306368:939524095]	98	1		T36	1	T6	1	T208	1
auto[939524096:1073741823]	106	1		T36	1	T7	1	T61	3
auto[1073741824:1207959551]	96	1		T43	1	T36	1	T6	1
auto[1207959552:1342177279]	85	1		T28	1	T211	1	T24	1
auto[1342177280:1476395007]	94	1		T15	1	T17	1	T27	1
auto[1476395008:1610612735]	107	1		T46	1	T206	1	T7	1
auto[1610612736:1744830463]	91	1		T16	1	T27	1	T30	1
auto[1744830464:1879048191]	95	1		T16	1	T90	1	T6	2
auto[1879048192:2013265919]	82	1		T27	1	T23	1	T24	1
auto[2013265920:2147483647]	108	1		T9	1	T17	1	T46	1
auto[2147483648:2281701375]	98	1		T27	1	T24	1	T6	1
auto[2281701376:2415919103]	89	1		T16	1	T9	1	T36	1
auto[2415919104:2550136831]	98	1		T23	1	T44	1	T24	2
auto[2550136832:2684354559]	88	1		T7	1	T92	1	T128	1
auto[2684354560:2818572287]	88	1		T44	1	T36	1	T6	2
auto[2818572288:2952790015]	91	1		T16	1	T89	1	T46	1
auto[2952790016:3087007743]	88	1		T6	1	T7	2	T258	1
auto[3087007744:3221225471]	91	1		T5	1	T17	1	T28	1
auto[3221225472:3355443199]	102	1		T27	1	T24	1	T30	1
auto[3355443200:3489660927]	99	1		T27	1	T23	1	T28	1
auto[3489660928:3623878655]	98	1		T27	1	T7	2	T54	2
auto[3623878656:3758096383]	82	1		T28	1	T7	1	T159	1
auto[3758096384:3892314111]	99	1		T44	1	T139	1	T6	1
auto[3892314112:4026531839]	69	1		T90	1	T24	1	T36	1
auto[4026531840:4160749567]	96	1		T258	1	T61	3	T263	1
auto[4160749568:4294967295]	83	1		T23	1	T211	1	T6	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	51	1		T9	1	T23	1	T106	1
auto[0:134217727]	auto[1]	48	1		T89	2	T7	1	T64	1
auto[134217728:268435455]	auto[0]	40	1		T205	1	T67	1	T417	1
auto[134217728:268435455]	auto[1]	40	1		T7	1	T62	1	T51	1
auto[268435456:402653183]	auto[0]	46	1		T211	1	T205	1	T270	1
auto[268435456:402653183]	auto[1]	62	1		T136	1	T206	1	T7	1
auto[402653184:536870911]	auto[0]	61	1		T137	1	T7	1	T69	1
auto[402653184:536870911]	auto[1]	48	1		T29	1	T137	1	T144	1
auto[536870912:671088639]	auto[0]	37	1		T23	1	T26	1	T51	1
auto[536870912:671088639]	auto[1]	46	1		T106	1	T7	1	T25	1
auto[671088640:805306367]	auto[0]	32	1		T9	1	T67	1	T62	1
auto[671088640:805306367]	auto[1]	51	1		T28	1	T89	1	T136	1
auto[805306368:939524095]	auto[0]	50	1		T36	1	T92	1	T433	1
auto[805306368:939524095]	auto[1]	48	1		T6	1	T208	1	T61	1
auto[939524096:1073741823]	auto[0]	51	1		T36	1	T7	1	T26	1
auto[939524096:1073741823]	auto[1]	55	1		T61	3	T58	1	T267	1
auto[1073741824:1207959551]	auto[0]	46	1		T43	1	T36	1	T106	1
auto[1073741824:1207959551]	auto[1]	50	1		T6	1	T110	1	T7	1
auto[1207959552:1342177279]	auto[0]	44	1		T24	1	T61	1	T270	1
auto[1207959552:1342177279]	auto[1]	41	1		T28	1	T211	1	T137	1
auto[1342177280:1476395007]	auto[0]	49	1		T15	1	T106	1	T7	2
auto[1342177280:1476395007]	auto[1]	45	1		T17	1	T27	1	T208	1
auto[1476395008:1610612735]	auto[0]	57	1		T206	1	T7	1	T54	1
auto[1476395008:1610612735]	auto[1]	50	1		T46	1	T54	1	T252	1
auto[1610612736:1744830463]	auto[0]	46	1		T61	1	T93	1	T263	1
auto[1610612736:1744830463]	auto[1]	45	1		T16	1	T27	1	T30	1
auto[1744830464:1879048191]	auto[0]	41	1		T6	2	T25	1	T92	1
auto[1744830464:1879048191]	auto[1]	54	1		T16	1	T90	1	T7	1
auto[1879048192:2013265919]	auto[0]	34	1		T27	1	T23	1	T24	1
auto[1879048192:2013265919]	auto[1]	48	1		T110	1	T92	1	T311	1
auto[2013265920:2147483647]	auto[0]	55	1		T159	1	T67	1	T263	1
auto[2013265920:2147483647]	auto[1]	53	1		T9	1	T17	1	T46	1
auto[2147483648:2281701375]	auto[0]	45	1		T27	1	T24	1	T58	1
auto[2147483648:2281701375]	auto[1]	53	1		T6	1	T61	1	T94	1
auto[2281701376:2415919103]	auto[0]	35	1		T16	1	T9	1	T7	2
auto[2281701376:2415919103]	auto[1]	54	1		T36	1	T6	1	T210	1
auto[2415919104:2550136831]	auto[0]	42	1		T23	1	T24	2	T19	1
auto[2415919104:2550136831]	auto[1]	56	1		T44	1	T6	1	T7	1
auto[2550136832:2684354559]	auto[0]	41	1		T159	1	T26	2	T232	1
auto[2550136832:2684354559]	auto[1]	47	1		T7	1	T92	1	T128	1
auto[2684354560:2818572287]	auto[0]	41	1		T44	1	T36	1	T6	1
auto[2684354560:2818572287]	auto[1]	47	1		T6	1	T7	1	T61	2
auto[2818572288:2952790015]	auto[0]	43	1		T16	1	T46	1	T61	1
auto[2818572288:2952790015]	auto[1]	48	1		T89	1	T110	1	T61	3
auto[2952790016:3087007743]	auto[0]	41	1		T7	2	T205	1	T62	1
auto[2952790016:3087007743]	auto[1]	47	1		T6	1	T258	1	T144	1
auto[3087007744:3221225471]	auto[0]	42	1		T43	1	T6	1	T7	2
auto[3087007744:3221225471]	auto[1]	49	1		T5	1	T17	1	T28	1
auto[3221225472:3355443199]	auto[0]	49	1		T24	1	T7	2	T258	1
auto[3221225472:3355443199]	auto[1]	53	1		T27	1	T30	1	T206	1
auto[3355443200:3489660927]	auto[0]	47	1		T23	1	T28	1	T43	1
auto[3355443200:3489660927]	auto[1]	52	1		T27	1	T61	1	T94	1
auto[3489660928:3623878655]	auto[0]	47	1		T7	2	T54	1	T263	1
auto[3489660928:3623878655]	auto[1]	51	1		T27	1	T54	1	T61	1
auto[3623878656:3758096383]	auto[0]	34	1		T159	1	T61	1	T93	1
auto[3623878656:3758096383]	auto[1]	48	1		T28	1	T7	1	T222	1
auto[3758096384:3892314111]	auto[0]	48	1		T6	1	T30	1	T7	1
auto[3758096384:3892314111]	auto[1]	51	1		T44	1	T139	1	T110	1
auto[3892314112:4026531839]	auto[0]	33	1		T24	1	T7	1	T54	1
auto[3892314112:4026531839]	auto[1]	36	1		T90	1	T36	1	T6	1
auto[4026531840:4160749567]	auto[0]	53	1		T258	1	T61	1	T104	1
auto[4026531840:4160749567]	auto[1]	43	1		T61	2	T263	1	T52	1
auto[4160749568:4294967295]	auto[0]	35	1		T258	1	T92	2	T33	1
auto[4160749568:4294967295]	auto[1]	48	1		T23	1	T211	1	T6	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

auto[0]

1413

T15

T16

auto[1]

1570

T16

T17

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	85	1		T9	1	T44	1	T137	1
auto[134217728:268435455]	72	1		T23	1	T43	1	T30	1
auto[268435456:402653183]	100	1		T17	1	T28	1	T36	1
auto[402653184:536870911]	101	1		T90	1	T36	1	T6	1
auto[536870912:671088639]	77	1		T27	1	T36	1	T6	1
auto[671088640:805306367]	92	1		T24	1	T6	1	T206	2
auto[805306368:939524095]	100	1		T7	1	T205	1	T57	1
auto[939524096:1073741823]	87	1		T89	1	T43	1	T6	1
auto[1073741824:1207959551]	112	1		T89	1	T137	1	T110	1
auto[1207959552:1342177279]	91	1		T28	1	T29	1	T211	1
auto[1342177280:1476395007]	95	1		T15	1	T16	1	T27	1
auto[1476395008:1610612735]	96	1		T23	1	T36	1	T206	1
auto[1610612736:1744830463]	102	1		T23	1	T258	1	T69	1
auto[1744830464:1879048191]	114	1		T16	1	T6	1	T54	1
auto[1879048192:2013265919]	96	1		T17	1	T28	1	T46	1
auto[2013265920:2147483647]	104	1		T27	1	T23	1	T24	1
auto[2147483648:2281701375]	73	1		T46	1	T7	1	T64	1
auto[2281701376:2415919103]	82	1		T23	1	T211	1	T44	1
auto[2415919104:2550136831]	86	1		T17	1	T7	4	T61	2
auto[2550136832:2684354559]	94	1		T28	1	T24	1	T6	2
auto[2684354560:2818572287]	96	1		T27	1	T211	1	T43	1
auto[2818572288:2952790015]	98	1		T9	1	T23	1	T24	1
auto[2952790016:3087007743]	104	1		T5	1	T90	1	T36	1
auto[3087007744:3221225471]	92	1		T9	1	T24	1	T6	1
auto[3221225472:3355443199]	101	1		T27	1	T36	1	T139	1
auto[3355443200:3489660927]	86	1		T206	1	T106	1	T258	1
auto[3489660928:3623878655]	94	1		T27	2	T28	1	T24	1
auto[3623878656:3758096383]	100	1		T16	1	T9	1	T46	1
auto[3758096384:3892314111]	85	1		T16	1	T7	1	T54	1
auto[3892314112:4026531839]	88	1		T159	1	T61	1	T336	1
auto[4026531840:4160749567]	90	1		T36	1	T136	1	T137	1
auto[4160749568:4294967295]	90	1		T89	1	T44	1	T24	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	39	1		T9	1	T44	1	T106	1
auto[0:134217727]	auto[1]	46	1		T137	1	T205	1	T144	1
auto[134217728:268435455]	auto[0]	33	1		T23	1	T43	1	T62	1
auto[134217728:268435455]	auto[1]	39	1		T30	1	T92	1	T61	1
auto[268435456:402653183]	auto[0]	49	1		T36	1	T128	1	T61	1
auto[268435456:402653183]	auto[1]	51	1		T17	1	T28	1	T137	1
auto[402653184:536870911]	auto[0]	52	1		T36	1	T144	1	T159	1
auto[402653184:536870911]	auto[1]	49	1		T90	1	T6	1	T206	1
auto[536870912:671088639]	auto[0]	39	1		T27	1	T36	1	T7	1
auto[536870912:671088639]	auto[1]	38	1		T6	1	T25	1	T54	1
auto[671088640:805306367]	auto[0]	44	1		T24	1	T6	1	T206	1
auto[671088640:805306367]	auto[1]	48	1		T206	1	T61	2	T59	1
auto[805306368:939524095]	auto[0]	54	1		T7	1	T205	1	T59	1
auto[805306368:939524095]	auto[1]	46	1		T57	1	T311	1	T101	1
auto[939524096:1073741823]	auto[0]	37	1		T7	2	T225	2	T232	1
auto[939524096:1073741823]	auto[1]	50	1		T89	1	T43	1	T6	1
auto[1073741824:1207959551]	auto[0]	48	1		T258	1	T26	1	T93	1
auto[1073741824:1207959551]	auto[1]	64	1		T89	1	T137	1	T110	1
auto[1207959552:1342177279]	auto[0]	45	1		T211	1	T92	1	T144	1
auto[1207959552:1342177279]	auto[1]	46	1		T28	1	T29	1	T44	1
auto[1342177280:1476395007]	auto[0]	53	1		T15	1	T16	1	T26	1
auto[1342177280:1476395007]	auto[1]	42	1		T27	1	T89	1	T52	1
auto[1476395008:1610612735]	auto[0]	46	1		T36	1	T7	1	T93	1
auto[1476395008:1610612735]	auto[1]	50	1		T23	1	T206	1	T7	1
auto[1610612736:1744830463]	auto[0]	51	1		T23	1	T258	1	T311	1
auto[1610612736:1744830463]	auto[1]	51	1		T69	1	T100	1	T216	1
auto[1744830464:1879048191]	auto[0]	56	1		T16	1	T54	1	T159	1
auto[1744830464:1879048191]	auto[1]	58	1		T6	1	T144	1	T65	1
auto[1879048192:2013265919]	auto[0]	47	1		T7	2	T54	1	T69	1
auto[1879048192:2013265919]	auto[1]	49	1		T17	1	T28	1	T46	1
auto[2013265920:2147483647]	auto[0]	43	1		T27	1	T23	1	T24	1
auto[2013265920:2147483647]	auto[1]	61	1		T110	1	T7	1	T263	1
auto[2147483648:2281701375]	auto[0]	32	1		T46	1	T7	1	T61	1
auto[2147483648:2281701375]	auto[1]	41	1		T64	1	T59	1	T257	1
auto[2281701376:2415919103]	auto[0]	46	1		T23	1	T211	1	T44	1
auto[2281701376:2415919103]	auto[1]	36	1		T136	1	T6	1	T262	1
auto[2415919104:2550136831]	auto[0]	31	1		T7	1	T61	1	T347	1
auto[2415919104:2550136831]	auto[1]	55	1		T17	1	T7	3	T61	1
auto[2550136832:2684354559]	auto[0]	45	1		T28	1	T24	1	T6	2
auto[2550136832:2684354559]	auto[1]	49	1		T30	1	T144	1	T61	3
auto[2684354560:2818572287]	auto[0]	45	1		T211	1	T43	1	T7	2
auto[2684354560:2818572287]	auto[1]	51	1		T27	1	T6	1	T30	1
auto[2818572288:2952790015]	auto[0]	45	1		T23	1	T24	1	T26	1
auto[2818572288:2952790015]	auto[1]	53	1		T9	1	T6	1	T210	1
auto[2952790016:3087007743]	auto[0]	50	1		T5	1	T36	1	T7	3
auto[2952790016:3087007743]	auto[1]	54	1		T90	1	T6	1	T110	2
auto[3087007744:3221225471]	auto[0]	51	1		T9	1	T24	1	T258	1
auto[3087007744:3221225471]	auto[1]	41	1		T6	1	T205	1	T64	1
auto[3221225472:3355443199]	auto[0]	54	1		T139	1	T7	1	T263	1
auto[3221225472:3355443199]	auto[1]	47	1		T27	1	T36	1	T206	1
auto[3355443200:3489660927]	auto[0]	37	1		T106	1	T93	1	T408	1
auto[3355443200:3489660927]	auto[1]	49	1		T206	1	T258	1	T69	1
auto[3489660928:3623878655]	auto[0]	44	1		T24	1	T6	1	T7	1
auto[3489660928:3623878655]	auto[1]	50	1		T27	2	T28	1	T7	1
auto[3623878656:3758096383]	auto[0]	41	1		T106	1	T7	1	T62	1
auto[3623878656:3758096383]	auto[1]	59	1		T16	1	T9	1	T46	1
auto[3758096384:3892314111]	auto[0]	40	1		T7	1	T54	1	T52	1
auto[3758096384:3892314111]	auto[1]	45	1		T16	1	T61	2	T58	2
auto[3892314112:4026531839]	auto[0]	36	1		T52	1	T356	1	T81	1
auto[3892314112:4026531839]	auto[1]	52	1		T159	1	T61	1	T336	1
auto[4026531840:4160749567]	auto[0]	36	1		T25	2	T92	1	T144	1
auto[4026531840:4160749567]	auto[1]	54	1		T36	1	T136	1	T137	1
auto[4160749568:4294967295]	auto[0]	44	1		T89	1	T24	1	T36	1
auto[4160749568:4294967295]	auto[1]	46	1		T44	1	T6	1	T110	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

auto[0]

1444

T15

T16

auto[1]

1544

T17

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	100	1		T36	1	T6	1	T110	1
auto[134217728:268435455]	92	1		T137	1	T7	2	T69	1
auto[268435456:402653183]	81	1		T6	1	T7	1	T33	1
auto[402653184:536870911]	106	1		T23	1	T24	1	T136	1
auto[536870912:671088639]	106	1		T17	1	T27	1	T28	1
auto[671088640:805306367]	79	1		T23	1	T206	1	T7	1
auto[805306368:939524095]	90	1		T36	1	T6	1	T210	1
auto[939524096:1073741823]	101	1		T89	1	T90	1	T110	1
auto[1073741824:1207959551]	92	1		T24	1	T7	1	T205	1
auto[1207959552:1342177279]	102	1		T9	1	T43	1	T206	2
auto[1342177280:1476395007]	105	1		T211	1	T24	1	T137	1
auto[1476395008:1610612735]	110	1		T9	1	T28	1	T29	1
auto[1610612736:1744830463]	92	1		T17	1	T36	1	T7	1
auto[1744830464:1879048191]	104	1		T27	1	T89	1	T206	1
auto[1879048192:2013265919]	93	1		T5	1	T27	1	T23	1
auto[2013265920:2147483647]	95	1		T15	1	T27	1	T36	1
auto[2147483648:2281701375]	80	1		T16	1	T36	1	T7	1
auto[2281701376:2415919103]	99	1		T6	1	T7	3	T258	1
auto[2415919104:2550136831]	102	1		T44	1	T24	1	T106	1
auto[2550136832:2684354559]	107	1		T23	1	T44	1	T36	1
auto[2684354560:2818572287]	82	1		T16	1	T27	1	T43	1
auto[2818572288:2952790015]	87	1		T16	1	T44	1	T24	1
auto[2952790016:3087007743]	82	1		T27	1	T106	1	T61	2
auto[3087007744:3221225471]	87	1		T9	1	T211	1	T44	1
auto[3221225472:3355443199]	100	1		T9	1	T23	1	T28	1
auto[3355443200:3489660927]	95	1		T139	1	T206	1	T7	2
auto[3489660928:3623878655]	77	1		T16	1	T24	1	T36	1
auto[3623878656:3758096383]	86	1		T17	1	T23	1	T28	1
auto[3758096384:3892314111]	96	1		T27	1	T46	1	T7	1
auto[3892314112:4026531839]	85	1		T36	1	T136	1	T6	1
auto[4026531840:4160749567]	83	1		T46	1	T137	1	T6	1
auto[4160749568:4294967295]	92	1		T28	1	T46	1	T7	1