Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0] 3992 1 T9 6 T27 14 T23 10
auto[1] 1981 1 T5 2 T15 2 T16 8



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] 200 1 T16 2 T6 4 T30 2
auto[134217728:268435455] 152 1 T28 2 T211 2 T89 2
auto[268435456:402653183] 178 1 T5 2 T28 2 T46 2
auto[402653184:536870911] 190 1 T27 2 T24 2 T92 2
auto[536870912:671088639] 178 1 T89 2 T90 2 T36 2
auto[671088640:805306367] 200 1 T17 2 T27 2 T28 2
auto[805306368:939524095] 208 1 T44 4 T206 2 T7 2
auto[939524096:1073741823] 172 1 T15 2 T27 2 T36 2
auto[1073741824:1207959551] 190 1 T28 2 T43 2 T6 2
auto[1207959552:1342177279] 158 1 T43 2 T7 4 T54 2
auto[1342177280:1476395007] 176 1 T206 2 T7 8 T69 2
auto[1476395008:1610612735] 180 1 T16 2 T24 2 T137 2
auto[1610612736:1744830463] 166 1 T36 2 T258 2 T92 4
auto[1744830464:1879048191] 206 1 T23 2 T7 8 T208 2
auto[1879048192:2013265919] 209 1 T36 4 T6 2 T106 2
auto[2013265920:2147483647] 190 1 T9 2 T23 2 T6 4
auto[2147483648:2281701375] 174 1 T24 2 T136 2 T7 2
auto[2281701376:2415919103] 170 1 T16 2 T24 2 T7 4
auto[2415919104:2550136831] 194 1 T90 2 T44 2 T24 2
auto[2550136832:2684354559] 136 1 T9 2 T210 2 T61 4
auto[2684354560:2818572287] 200 1 T7 2 T258 2 T205 2
auto[2818572288:2952790015] 232 1 T27 4 T36 2 T258 2
auto[2952790016:3087007743] 148 1 T17 2 T23 6 T6 2
auto[3087007744:3221225471] 214 1 T9 2 T17 2 T211 2
auto[3221225472:3355443199] 188 1 T9 2 T27 2 T24 2
auto[3355443200:3489660927] 196 1 T24 2 T30 2 T7 2
auto[3489660928:3623878655] 192 1 T9 2 T28 2 T6 2
auto[3623878656:3758096383] 192 1 T43 2 T44 2 T6 2
auto[3758096384:3892314111] 190 1 T23 2 T29 2 T137 2
auto[3892314112:4026531839] 210 1 T89 2 T6 2 T7 2
auto[4026531840:4160749567] 194 1 T27 2 T6 2 T30 2
auto[4160749568:4294967295] 190 1 T16 2 T211 2 T36 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cp   regwen_cp   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
auto[0:134217727] auto[0] 134 1 T30 2 T7 2 T144 2
auto[0:134217727] auto[1] 66 1 T16 2 T6 4 T7 4
auto[134217728:268435455] auto[0] 88 1 T211 2 T208 2 T61 2
auto[134217728:268435455] auto[1] 64 1 T28 2 T89 2 T110 2
auto[268435456:402653183] auto[0] 112 1 T46 2 T7 2 T144 2
auto[268435456:402653183] auto[1] 66 1 T5 2 T28 2 T6 2
auto[402653184:536870911] auto[0] 130 1 T27 2 T24 2 T92 2
auto[402653184:536870911] auto[1] 60 1 T336 2 T52 2 T105 2
auto[536870912:671088639] auto[0] 118 1 T90 2 T36 2 T46 2
auto[536870912:671088639] auto[1] 60 1 T89 2 T206 2 T106 2
auto[671088640:805306367] auto[0] 138 1 T27 2 T36 2 T258 2
auto[671088640:805306367] auto[1] 62 1 T17 2 T28 2 T89 2
auto[805306368:939524095] auto[0] 136 1 T206 2 T7 2 T51 2
auto[805306368:939524095] auto[1] 72 1 T44 4 T128 2 T61 2
auto[939524096:1073741823] auto[0] 104 1 T27 2 T110 2 T7 4
auto[939524096:1073741823] auto[1] 68 1 T15 2 T36 2 T206 2
auto[1073741824:1207959551] auto[0] 134 1 T6 2 T19 2 T52 2
auto[1073741824:1207959551] auto[1] 56 1 T28 2 T43 2 T110 2
auto[1207959552:1342177279] auto[0] 96 1 T54 2 T61 2 T311 2
auto[1207959552:1342177279] auto[1] 62 1 T43 2 T7 4 T69 2
auto[1342177280:1476395007] auto[0] 132 1 T206 2 T7 4 T144 2
auto[1342177280:1476395007] auto[1] 44 1 T7 4 T69 2 T61 2
auto[1476395008:1610612735] auto[0] 130 1 T24 2 T137 2 T30 2
auto[1476395008:1610612735] auto[1] 50 1 T16 2 T33 2 T128 2
auto[1610612736:1744830463] auto[0] 98 1 T36 2 T258 2 T61 2
auto[1610612736:1744830463] auto[1] 68 1 T92 4 T61 2 T222 2
auto[1744830464:1879048191] auto[0] 134 1 T23 2 T7 6 T208 2
auto[1744830464:1879048191] auto[1] 72 1 T7 2 T434 2 T440 2
auto[1879048192:2013265919] auto[0] 148 1 T36 4 T6 2 T106 2
auto[1879048192:2013265919] auto[1] 61 1 T7 2 T336 2 T51 2
auto[2013265920:2147483647] auto[0] 120 1 T9 2 T23 2 T6 4
auto[2013265920:2147483647] auto[1] 70 1 T7 4 T64 2 T435 2
auto[2147483648:2281701375] auto[0] 126 1 T24 2 T7 2 T258 2
auto[2147483648:2281701375] auto[1] 48 1 T136 2 T61 2 T434 2
auto[2281701376:2415919103] auto[0] 110 1 T24 2 T7 4 T252 2
auto[2281701376:2415919103] auto[1] 60 1 T16 2 T81 2 T71 2
auto[2415919104:2550136831] auto[0] 140 1 T90 2 T44 2 T24 2
auto[2415919104:2550136831] auto[1] 54 1 T206 2 T7 2 T25 2
auto[2550136832:2684354559] auto[0] 94 1 T210 2 T61 2 T19 2
auto[2550136832:2684354559] auto[1] 42 1 T9 2 T61 2 T267 2
auto[2684354560:2818572287] auto[0] 134 1 T205 2 T69 2 T93 2
auto[2684354560:2818572287] auto[1] 66 1 T7 2 T258 2 T128 2
auto[2818572288:2952790015] auto[0] 154 1 T27 4 T36 2 T258 2
auto[2818572288:2952790015] auto[1] 78 1 T25 2 T267 2 T214 2
auto[2952790016:3087007743] auto[0] 92 1 T23 4 T6 2 T110 2
auto[2952790016:3087007743] auto[1] 56 1 T17 2 T23 2 T52 2
auto[3087007744:3221225471] auto[0] 130 1 T9 2 T7 4 T270 2
auto[3087007744:3221225471] auto[1] 84 1 T17 2 T211 2 T136 2
auto[3221225472:3355443199] auto[0] 134 1 T9 2 T27 2 T24 2
auto[3221225472:3355443199] auto[1] 54 1 T139 2 T61 2 T19 2
auto[3355443200:3489660927] auto[0] 142 1 T24 2 T30 2 T7 2
auto[3355443200:3489660927] auto[1] 54 1 T433 2 T45 2 T216 2
auto[3489660928:3623878655] auto[0] 136 1 T6 2 T258 2 T144 4
auto[3489660928:3623878655] auto[1] 56 1 T9 2 T28 2 T267 2
auto[3623878656:3758096383] auto[0] 132 1 T6 2 T206 2 T106 2
auto[3623878656:3758096383] auto[1] 60 1 T43 2 T44 2 T66 2
auto[3758096384:3892314111] auto[0] 126 1 T23 2 T29 2 T137 2
auto[3758096384:3892314111] auto[1] 64 1 T25 2 T61 2 T52 2
auto[3892314112:4026531839] auto[0] 150 1 T89 2 T6 2 T61 2
auto[3892314112:4026531839] auto[1] 60 1 T7 2 T61 2 T52 2
auto[4026531840:4160749567] auto[0] 122 1 T27 2 T6 2 T30 2
auto[4026531840:4160749567] auto[1] 72 1 T110 2 T7 2 T69 2
auto[4160749568:4294967295] auto[0] 118 1 T211 2 T46 2 T54 2
auto[4160749568:4294967295] auto[1] 72 1 T16 2 T36 2 T92 2