Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2595

1

T15

1

T16

4

T9

4

auto[1]

302

1

T17

1

T137

3

T144

11

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T23	1		T28	1		T137	1
auto[134217728:268435455]	87	1			T16	1		T17	1		T24	1
auto[268435456:402653183]	99	1			T9	1		T61	2		T26	1
auto[402653184:536870911]	79	1			T36	1		T139	1		T110	1
auto[536870912:671088639]	82	1			T24	1		T7	2		T25	1
auto[671088640:805306367]	106	1			T89	2		T90	1		T24	1
auto[805306368:939524095]	80	1			T27	1		T90	1		T24	1
auto[939524096:1073741823]	91	1			T16	1		T28	1		T43	1
auto[1073741824:1207959551]	97	1			T27	1		T28	1		T6	1
auto[1207959552:1342177279]	68	1			T36	1		T6	1		T205	1
auto[1342177280:1476395007]	78	1			T9	1		T27	1		T36	1
auto[1476395008:1610612735]	106	1			T208	1		T144	1		T159	1
auto[1610612736:1744830463]	89	1			T27	1		T137	1		T6	1
auto[1744830464:1879048191]	101	1			T211	1		T89	1		T24	1
auto[1879048192:2013265919]	108	1			T28	1		T252	1		T435	1
auto[2013265920:2147483647]	75	1			T137	1		T69	1		T159	1
auto[2147483648:2281701375]	87	1			T23	1		T110	1		T25	1
auto[2281701376:2415919103]	85	1			T15	1		T23	1		T211	1
auto[2415919104:2550136831]	85	1			T24	1		T206	1		T110	1
auto[2550136832:2684354559]	96	1			T17	1		T7	5		T25	1
auto[2684354560:2818572287]	95	1			T110	1		T106	1		T7	1
auto[2818572288:2952790015]	81	1			T29	1		T61	1		T58	1
auto[2952790016:3087007743]	102	1			T17	1		T110	1		T7	1
auto[3087007744:3221225471]	87	1			T27	1		T23	1		T30	1
auto[3221225472:3355443199]	87	1			T211	1		T136	1		T69	1
auto[3355443200:3489660927]	104	1			T27	1		T46	1		T136	1
auto[3489660928:3623878655]	97	1			T16	1		T17	1		T24	1
auto[3623878656:3758096383]	80	1			T9	1		T23	1		T206	1
auto[3758096384:3892314111]	97	1			T27	1		T36	2		T7	1
auto[3892314112:4026531839]	99	1			T16	1		T9	1		T110	1
auto[4026531840:4160749567]	94	1			T23	1		T46	2		T144	4
auto[4160749568:4294967295]	86	1			T28	1		T30	2		T206	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	77	1			T23	1		T28	1		T206	1
auto[0:134217727]	auto[1]	12	1			T137	1		T144	1		T159	1
auto[134217728:268435455]	auto[0]	77	1			T16	1		T17	1		T24	1
auto[134217728:268435455]	auto[1]	10	1			T159	1		T311	1		T308	1
auto[268435456:402653183]	auto[0]	95	1			T9	1		T61	2		T26	1
auto[268435456:402653183]	auto[1]	4	1			T432	1		T441	1		T322	1
auto[402653184:536870911]	auto[0]	70	1			T36	1		T139	1		T110	1
auto[402653184:536870911]	auto[1]	9	1			T426	1		T242	2		T428	1
auto[536870912:671088639]	auto[0]	69	1			T24	1		T7	2		T25	1
auto[536870912:671088639]	auto[1]	13	1			T144	1		T302	1		T250	1
auto[671088640:805306367]	auto[0]	99	1			T89	2		T90	1		T24	1
auto[671088640:805306367]	auto[1]	7	1			T159	1		T287	1		T396	1
auto[805306368:939524095]	auto[0]	71	1			T27	1		T90	1		T24	1
auto[805306368:939524095]	auto[1]	9	1			T144	1		T250	1		T243	1
auto[939524096:1073741823]	auto[0]	81	1			T16	1		T28	1		T43	1
auto[939524096:1073741823]	auto[1]	10	1			T159	1		T250	1		T429	1
auto[1073741824:1207959551]	auto[0]	93	1			T27	1		T28	1		T6	1
auto[1073741824:1207959551]	auto[1]	4	1			T250	1		T379	1		T441	2
auto[1207959552:1342177279]	auto[0]	60	1			T36	1		T6	1		T205	1
auto[1207959552:1342177279]	auto[1]	8	1			T144	1		T159	1		T311	2
auto[1342177280:1476395007]	auto[0]	69	1			T9	1		T27	1		T36	1
auto[1342177280:1476395007]	auto[1]	9	1			T137	1		T287	1		T436	1
auto[1476395008:1610612735]	auto[0]	96	1			T208	1		T144	1		T61	2
auto[1476395008:1610612735]	auto[1]	10	1			T159	1		T250	1		T288	1
auto[1610612736:1744830463]	auto[0]	80	1			T27	1		T6	1		T206	1
auto[1610612736:1744830463]	auto[1]	9	1			T137	1		T144	1		T159	1
auto[1744830464:1879048191]	auto[0]	92	1			T211	1		T89	1		T24	1
auto[1744830464:1879048191]	auto[1]	9	1			T284	1		T436	1		T401	1
auto[1879048192:2013265919]	auto[0]	92	1			T28	1		T252	1		T435	1
auto[1879048192:2013265919]	auto[1]	16	1			T302	1		T311	1		T243	1
auto[2013265920:2147483647]	auto[0]	65	1			T137	1		T69	1		T61	1
auto[2013265920:2147483647]	auto[1]	10	1			T159	1		T250	1		T287	1
auto[2147483648:2281701375]	auto[0]	79	1			T23	1		T110	1		T25	1
auto[2147483648:2281701375]	auto[1]	8	1			T250	1		T429	1		T244	1
auto[2281701376:2415919103]	auto[0]	75	1			T15	1		T23	1		T211	1
auto[2281701376:2415919103]	auto[1]	10	1			T144	1		T250	1		T288	1
auto[2415919104:2550136831]	auto[0]	74	1			T24	1		T206	1		T110	1
auto[2415919104:2550136831]	auto[1]	11	1			T159	2		T214	1		T311	1
auto[2550136832:2684354559]	auto[0]	84	1			T17	1		T7	5		T25	1
auto[2550136832:2684354559]	auto[1]	12	1			T159	1		T287	1		T266	1
auto[2684354560:2818572287]	auto[0]	84	1			T110	1		T106	1		T7	1
auto[2684354560:2818572287]	auto[1]	11	1			T144	1		T287	1		T243	1
auto[2818572288:2952790015]	auto[0]	72	1			T29	1		T61	1		T58	1
auto[2818572288:2952790015]	auto[1]	9	1			T214	1		T243	1		T245	1
auto[2952790016:3087007743]	auto[0]	99	1			T17	1		T110	1		T7	1
auto[2952790016:3087007743]	auto[1]	3	1			T159	1		T426	1		T441	1
auto[3087007744:3221225471]	auto[0]	74	1			T27	1		T23	1		T30	1
auto[3087007744:3221225471]	auto[1]	13	1			T159	1		T311	2		T426	1
auto[3221225472:3355443199]	auto[0]	78	1			T211	1		T136	1		T69	1
auto[3221225472:3355443199]	auto[1]	9	1			T243	1		T430	1		T432	1
auto[3355443200:3489660927]	auto[0]	97	1			T27	1		T46	1		T136	1
auto[3355443200:3489660927]	auto[1]	7	1			T396	1		T426	2		T401	1
auto[3489660928:3623878655]	auto[0]	83	1			T16	1		T24	1		T36	1
auto[3489660928:3623878655]	auto[1]	14	1			T17	1		T159	1		T302	2
auto[3623878656:3758096383]	auto[0]	67	1			T9	1		T23	1		T206	1
auto[3623878656:3758096383]	auto[1]	13	1			T288	1		T266	1		T396	1
auto[3758096384:3892314111]	auto[0]	90	1			T27	1		T36	2		T7	1
auto[3758096384:3892314111]	auto[1]	7	1			T243	2		T429	2		T401	1
auto[3892314112:4026531839]	auto[0]	89	1			T16	1		T9	1		T110	1
auto[3892314112:4026531839]	auto[1]	10	1			T302	1		T426	1		T379	1
auto[4026531840:4160749567]	auto[0]	87	1			T23	1		T46	2		T144	2
auto[4026531840:4160749567]	auto[1]	7	1			T144	2		T429	1		T308	1
auto[4160749568:4294967295]	auto[0]	77	1			T28	1		T30	2		T206	1
auto[4160749568:4294967295]	auto[1]	9	1			T144	2		T426	1		T436	1